1 //===-- FastISel.cpp - Implementation of the FastISel class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #define DEBUG_TYPE "isel"
43 #include "llvm/CodeGen/FastISel.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/Analysis/Loads.h"
46 #include "llvm/CodeGen/Analysis.h"
47 #include "llvm/CodeGen/FunctionLoweringInfo.h"
48 #include "llvm/CodeGen/MachineInstrBuilder.h"
49 #include "llvm/CodeGen/MachineModuleInfo.h"
50 #include "llvm/CodeGen/MachineRegisterInfo.h"
51 #include "llvm/DebugInfo.h"
52 #include "llvm/IR/DataLayout.h"
53 #include "llvm/IR/Function.h"
54 #include "llvm/IR/GlobalVariable.h"
55 #include "llvm/IR/Instructions.h"
56 #include "llvm/IR/IntrinsicInst.h"
57 #include "llvm/IR/Operator.h"
58 #include "llvm/Support/Debug.h"
59 #include "llvm/Support/ErrorHandling.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetLibraryInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetMachine.h"
66 STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by "
67 "target-independent selector");
68 STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by "
69 "target-specific selector");
70 STATISTIC(NumFastIselDead, "Number of dead insts removed on failure");
72 /// startNewBlock - Set the current block to which generated machine
73 /// instructions will be appended, and clear the local CSE map.
75 void FastISel::startNewBlock() {
76 LocalValueMap.clear();
80 // Advance the emit start point past any EH_LABEL instructions.
81 MachineBasicBlock::iterator
82 I = FuncInfo.MBB->begin(), E = FuncInfo.MBB->end();
83 while (I != E && I->getOpcode() == TargetOpcode::EH_LABEL) {
87 LastLocalValue = EmitStartPt;
90 void FastISel::flushLocalValueMap() {
91 LocalValueMap.clear();
92 LastLocalValue = EmitStartPt;
96 bool FastISel::hasTrivialKill(const Value *V) const {
97 // Don't consider constants or arguments to have trivial kills.
98 const Instruction *I = dyn_cast<Instruction>(V);
102 // No-op casts are trivially coalesced by fast-isel.
103 if (const CastInst *Cast = dyn_cast<CastInst>(I))
104 if (Cast->isNoopCast(TD.getIntPtrType(Cast->getContext())) &&
105 !hasTrivialKill(Cast->getOperand(0)))
108 // GEPs with all zero indices are trivially coalesced by fast-isel.
109 if (const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(I))
110 if (GEP->hasAllZeroIndices() && !hasTrivialKill(GEP->getOperand(0)))
113 // Only instructions with a single use in the same basic block are considered
114 // to have trivial kills.
115 return I->hasOneUse() &&
116 !(I->getOpcode() == Instruction::BitCast ||
117 I->getOpcode() == Instruction::PtrToInt ||
118 I->getOpcode() == Instruction::IntToPtr) &&
119 cast<Instruction>(*I->use_begin())->getParent() == I->getParent();
122 unsigned FastISel::getRegForValue(const Value *V) {
123 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
124 // Don't handle non-simple values in FastISel.
125 if (!RealVT.isSimple())
128 // Ignore illegal types. We must do this before looking up the value
129 // in ValueMap because Arguments are given virtual registers regardless
130 // of whether FastISel can handle them.
131 MVT VT = RealVT.getSimpleVT();
132 if (!TLI.isTypeLegal(VT)) {
133 // Handle integer promotions, though, because they're common and easy.
134 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
135 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
140 // Look up the value to see if we already have a register for it.
141 unsigned Reg = lookUpRegForValue(V);
145 // In bottom-up mode, just create the virtual register which will be used
146 // to hold the value. It will be materialized later.
147 if (isa<Instruction>(V) &&
148 (!isa<AllocaInst>(V) ||
149 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
150 return FuncInfo.InitializeRegForValue(V);
152 SavePoint SaveInsertPt = enterLocalValueArea();
154 // Materialize the value in a register. Emit any instructions in the
156 Reg = materializeRegForValue(V, VT);
158 leaveLocalValueArea(SaveInsertPt);
163 /// materializeRegForValue - Helper for getRegForValue. This function is
164 /// called when the value isn't already available in a register and must
165 /// be materialized with new instructions.
166 unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
169 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
170 if (CI->getValue().getActiveBits() <= 64)
171 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
172 } else if (isa<AllocaInst>(V)) {
173 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
174 } else if (isa<ConstantPointerNull>(V)) {
175 // Translate this as an integer zero so that it can be
176 // local-CSE'd with actual integer zeros.
178 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
179 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
180 if (CF->isNullValue()) {
181 Reg = TargetMaterializeFloatZero(CF);
183 // Try to emit the constant directly.
184 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
188 // Try to emit the constant by using an integer constant with a cast.
189 const APFloat &Flt = CF->getValueAPF();
190 EVT IntVT = TLI.getPointerTy();
193 uint32_t IntBitWidth = IntVT.getSizeInBits();
195 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
196 APFloat::rmTowardZero, &isExact);
198 APInt IntVal(IntBitWidth, x);
200 unsigned IntegerReg =
201 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
203 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
204 IntegerReg, /*Kill=*/false);
207 } else if (const Operator *Op = dyn_cast<Operator>(V)) {
208 if (!SelectOperator(Op, Op->getOpcode()))
209 if (!isa<Instruction>(Op) ||
210 !TargetSelectInstruction(cast<Instruction>(Op)))
212 Reg = lookUpRegForValue(Op);
213 } else if (isa<UndefValue>(V)) {
214 Reg = createResultReg(TLI.getRegClassFor(VT));
215 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
216 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
219 // If target-independent code couldn't handle the value, give target-specific
221 if (!Reg && isa<Constant>(V))
222 Reg = TargetMaterializeConstant(cast<Constant>(V));
224 // Don't cache constant materializations in the general ValueMap.
225 // To do so would require tracking what uses they dominate.
227 LocalValueMap[V] = Reg;
228 LastLocalValue = MRI.getVRegDef(Reg);
233 unsigned FastISel::lookUpRegForValue(const Value *V) {
234 // Look up the value to see if we already have a register for it. We
235 // cache values defined by Instructions across blocks, and other values
236 // only locally. This is because Instructions already have the SSA
237 // def-dominates-use requirement enforced.
238 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
239 if (I != FuncInfo.ValueMap.end())
241 return LocalValueMap[V];
244 /// UpdateValueMap - Update the value map to include the new mapping for this
245 /// instruction, or insert an extra copy to get the result in a previous
246 /// determined register.
247 /// NOTE: This is only necessary because we might select a block that uses
248 /// a value before we select the block that defines the value. It might be
249 /// possible to fix this by selecting blocks in reverse postorder.
250 void FastISel::UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) {
251 if (!isa<Instruction>(I)) {
252 LocalValueMap[I] = Reg;
256 unsigned &AssignedReg = FuncInfo.ValueMap[I];
257 if (AssignedReg == 0)
258 // Use the new register.
260 else if (Reg != AssignedReg) {
261 // Arrange for uses of AssignedReg to be replaced by uses of Reg.
262 for (unsigned i = 0; i < NumRegs; i++)
263 FuncInfo.RegFixups[AssignedReg+i] = Reg+i;
269 std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) {
270 unsigned IdxN = getRegForValue(Idx);
272 // Unhandled operand. Halt "fast" selection and bail.
273 return std::pair<unsigned, bool>(0, false);
275 bool IdxNIsKill = hasTrivialKill(Idx);
277 // If the index is smaller or larger than intptr_t, truncate or extend it.
278 MVT PtrVT = TLI.getPointerTy();
279 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
280 if (IdxVT.bitsLT(PtrVT)) {
281 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND,
285 else if (IdxVT.bitsGT(PtrVT)) {
286 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE,
290 return std::pair<unsigned, bool>(IdxN, IdxNIsKill);
293 void FastISel::recomputeInsertPt() {
294 if (getLastLocalValue()) {
295 FuncInfo.InsertPt = getLastLocalValue();
296 FuncInfo.MBB = FuncInfo.InsertPt->getParent();
299 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
301 // Now skip past any EH_LABELs, which must remain at the beginning.
302 while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
303 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
307 void FastISel::removeDeadCode(MachineBasicBlock::iterator I,
308 MachineBasicBlock::iterator E) {
309 assert (I && E && std::distance(I, E) > 0 && "Invalid iterator!");
311 MachineInstr *Dead = &*I;
313 Dead->eraseFromParent();
319 FastISel::SavePoint FastISel::enterLocalValueArea() {
320 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt;
324 SavePoint SP = { OldInsertPt, OldDL };
328 void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) {
329 if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
330 LastLocalValue = llvm::prior(FuncInfo.InsertPt);
332 // Restore the previous insert position.
333 FuncInfo.InsertPt = OldInsertPt.InsertPt;
337 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
338 /// which has an opcode which directly corresponds to the given ISD opcode.
340 bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) {
341 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
342 if (VT == MVT::Other || !VT.isSimple())
343 // Unhandled type. Halt "fast" selection and bail.
346 // We only handle legal types. For example, on x86-32 the instruction
347 // selector contains all of the 64-bit instructions from x86-64,
348 // under the assumption that i64 won't be used if the target doesn't
350 if (!TLI.isTypeLegal(VT)) {
351 // MVT::i1 is special. Allow AND, OR, or XOR because they
352 // don't require additional zeroing, which makes them easy.
354 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
355 ISDOpcode == ISD::XOR))
356 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
361 // Check if the first operand is a constant, and handle it as "ri". At -O0,
362 // we don't have anything that canonicalizes operand order.
363 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
364 if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
365 unsigned Op1 = getRegForValue(I->getOperand(1));
366 if (Op1 == 0) return false;
368 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
370 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
371 Op1IsKill, CI->getZExtValue(),
373 if (ResultReg == 0) return false;
375 // We successfully emitted code for the given LLVM Instruction.
376 UpdateValueMap(I, ResultReg);
381 unsigned Op0 = getRegForValue(I->getOperand(0));
382 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail.
385 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
387 // Check if the second operand is a constant and handle it appropriately.
388 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
389 uint64_t Imm = CI->getZExtValue();
391 // Transform "sdiv exact X, 8" -> "sra X, 3".
392 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
393 cast<BinaryOperator>(I)->isExact() &&
394 isPowerOf2_64(Imm)) {
396 ISDOpcode = ISD::SRA;
399 // Transform "urem x, pow2" -> "and x, pow2-1".
400 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) &&
401 isPowerOf2_64(Imm)) {
403 ISDOpcode = ISD::AND;
406 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
407 Op0IsKill, Imm, VT.getSimpleVT());
408 if (ResultReg == 0) return false;
410 // We successfully emitted code for the given LLVM Instruction.
411 UpdateValueMap(I, ResultReg);
415 // Check if the second operand is a constant float.
416 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
417 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
418 ISDOpcode, Op0, Op0IsKill, CF);
419 if (ResultReg != 0) {
420 // We successfully emitted code for the given LLVM Instruction.
421 UpdateValueMap(I, ResultReg);
426 unsigned Op1 = getRegForValue(I->getOperand(1));
428 // Unhandled operand. Halt "fast" selection and bail.
431 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
433 // Now we have both operands in registers. Emit the instruction.
434 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
439 // Target-specific code wasn't able to find a machine opcode for
440 // the given ISD opcode and type. Halt "fast" selection and bail.
443 // We successfully emitted code for the given LLVM Instruction.
444 UpdateValueMap(I, ResultReg);
448 bool FastISel::SelectGetElementPtr(const User *I) {
449 unsigned N = getRegForValue(I->getOperand(0));
451 // Unhandled operand. Halt "fast" selection and bail.
454 bool NIsKill = hasTrivialKill(I->getOperand(0));
456 // Keep a running tab of the total offset to coalesce multiple N = N + Offset
457 // into a single N = N + TotalOffset.
458 uint64_t TotalOffs = 0;
459 // FIXME: What's a good SWAG number for MaxOffs?
460 uint64_t MaxOffs = 2048;
461 Type *Ty = I->getOperand(0)->getType();
462 MVT VT = TLI.getPointerTy();
463 for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1,
464 E = I->op_end(); OI != E; ++OI) {
465 const Value *Idx = *OI;
466 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
467 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
470 TotalOffs += TD.getStructLayout(StTy)->getElementOffset(Field);
471 if (TotalOffs >= MaxOffs) {
472 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
474 // Unhandled operand. Halt "fast" selection and bail.
480 Ty = StTy->getElementType(Field);
482 Ty = cast<SequentialType>(Ty)->getElementType();
484 // If this is a constant subscript, handle it quickly.
485 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
486 if (CI->isZero()) continue;
489 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
490 if (TotalOffs >= MaxOffs) {
491 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
493 // Unhandled operand. Halt "fast" selection and bail.
501 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
503 // Unhandled operand. Halt "fast" selection and bail.
509 // N = N + Idx * ElementSize;
510 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
511 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx);
512 unsigned IdxN = Pair.first;
513 bool IdxNIsKill = Pair.second;
515 // Unhandled operand. Halt "fast" selection and bail.
518 if (ElementSize != 1) {
519 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT);
521 // Unhandled operand. Halt "fast" selection and bail.
525 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill);
527 // Unhandled operand. Halt "fast" selection and bail.
532 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
534 // Unhandled operand. Halt "fast" selection and bail.
538 // We successfully emitted code for the given LLVM Instruction.
539 UpdateValueMap(I, N);
543 bool FastISel::SelectCall(const User *I) {
544 const CallInst *Call = cast<CallInst>(I);
546 // Handle simple inline asms.
547 if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledValue())) {
548 // Don't attempt to handle constraints.
549 if (!IA->getConstraintString().empty())
552 unsigned ExtraInfo = 0;
553 if (IA->hasSideEffects())
554 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
555 if (IA->isAlignStack())
556 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
558 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
559 TII.get(TargetOpcode::INLINEASM))
560 .addExternalSymbol(IA->getAsmString().c_str())
565 MachineModuleInfo &MMI = FuncInfo.MF->getMMI();
566 ComputeUsesVAFloatArgument(*Call, &MMI);
568 const Function *F = Call->getCalledFunction();
569 if (!F) return false;
571 // Handle selected intrinsic function calls.
572 switch (F->getIntrinsicID()) {
574 // At -O0 we don't care about the lifetime intrinsics.
575 case Intrinsic::lifetime_start:
576 case Intrinsic::lifetime_end:
577 // The donothing intrinsic does, well, nothing.
578 case Intrinsic::donothing:
581 case Intrinsic::dbg_declare: {
582 const DbgDeclareInst *DI = cast<DbgDeclareInst>(Call);
583 if (!DIVariable(DI->getVariable()).Verify() ||
584 !FuncInfo.MF->getMMI().hasDebugInfo()) {
585 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
589 const Value *Address = DI->getAddress();
590 if (!Address || isa<UndefValue>(Address)) {
591 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
597 if (const Argument *Arg = dyn_cast<Argument>(Address)) {
598 // Some arguments' frame index is recorded during argument lowering.
599 Offset = FuncInfo.getArgumentFrameIndex(Arg);
601 Reg = TRI.getFrameRegister(*FuncInfo.MF);
604 Reg = lookUpRegForValue(Address);
606 // If we have a VLA that has a "use" in a metadata node that's then used
607 // here but it has no other uses, then we have a problem. E.g.,
609 // int foo (const int *x) {
614 // If we assign 'a' a vreg and fast isel later on has to use the selection
615 // DAG isel, it will want to copy the value to the vreg. However, there are
616 // no uses, which goes counter to what selection DAG isel expects.
617 if (!Reg && !Address->use_empty() && isa<Instruction>(Address) &&
618 (!isa<AllocaInst>(Address) ||
619 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Address))))
620 Reg = FuncInfo.InitializeRegForValue(Address);
623 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
624 TII.get(TargetOpcode::DBG_VALUE))
625 .addReg(Reg, RegState::Debug).addImm(Offset)
626 .addMetadata(DI->getVariable());
628 // We can't yet handle anything else here because it would require
629 // generating code, thus altering codegen because of debug info.
630 DEBUG(dbgs() << "Dropping debug info for " << DI);
633 case Intrinsic::dbg_value: {
634 // This form of DBG_VALUE is target-independent.
635 const DbgValueInst *DI = cast<DbgValueInst>(Call);
636 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
637 const Value *V = DI->getValue();
639 // Currently the optimizer can produce this; insert an undef to
640 // help debugging. Probably the optimizer should not do this.
641 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
642 .addReg(0U).addImm(DI->getOffset())
643 .addMetadata(DI->getVariable());
644 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
645 if (CI->getBitWidth() > 64)
646 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
647 .addCImm(CI).addImm(DI->getOffset())
648 .addMetadata(DI->getVariable());
650 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
651 .addImm(CI->getZExtValue()).addImm(DI->getOffset())
652 .addMetadata(DI->getVariable());
653 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
654 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
655 .addFPImm(CF).addImm(DI->getOffset())
656 .addMetadata(DI->getVariable());
657 } else if (unsigned Reg = lookUpRegForValue(V)) {
658 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
659 .addReg(Reg, RegState::Debug).addImm(DI->getOffset())
660 .addMetadata(DI->getVariable());
662 // We can't yet handle anything else here because it would require
663 // generating code, thus altering codegen because of debug info.
664 DEBUG(dbgs() << "Dropping debug info for " << DI);
668 case Intrinsic::objectsize: {
669 ConstantInt *CI = cast<ConstantInt>(Call->getArgOperand(1));
670 unsigned long long Res = CI->isZero() ? -1ULL : 0;
671 Constant *ResCI = ConstantInt::get(Call->getType(), Res);
672 unsigned ResultReg = getRegForValue(ResCI);
675 UpdateValueMap(Call, ResultReg);
680 // Usually, it does not make sense to initialize a value,
681 // make an unrelated function call and use the value, because
682 // it tends to be spilled on the stack. So, we move the pointer
683 // to the last local value to the beginning of the block, so that
684 // all the values which have already been materialized,
685 // appear after the call. It also makes sense to skip intrinsics
686 // since they tend to be inlined.
687 if (!isa<IntrinsicInst>(F))
688 flushLocalValueMap();
690 // An arbitrary call. Bail.
694 bool FastISel::SelectCast(const User *I, unsigned Opcode) {
695 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
696 EVT DstVT = TLI.getValueType(I->getType());
698 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
699 DstVT == MVT::Other || !DstVT.isSimple())
700 // Unhandled type. Halt "fast" selection and bail.
703 // Check if the destination type is legal.
704 if (!TLI.isTypeLegal(DstVT))
707 // Check if the source operand is legal.
708 if (!TLI.isTypeLegal(SrcVT))
711 unsigned InputReg = getRegForValue(I->getOperand(0));
713 // Unhandled operand. Halt "fast" selection and bail.
716 bool InputRegIsKill = hasTrivialKill(I->getOperand(0));
718 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
721 InputReg, InputRegIsKill);
725 UpdateValueMap(I, ResultReg);
729 bool FastISel::SelectBitCast(const User *I) {
730 // If the bitcast doesn't change the type, just use the operand value.
731 if (I->getType() == I->getOperand(0)->getType()) {
732 unsigned Reg = getRegForValue(I->getOperand(0));
735 UpdateValueMap(I, Reg);
739 // Bitcasts of other values become reg-reg copies or BITCAST operators.
740 EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType());
741 EVT DstEVT = TLI.getValueType(I->getType());
742 if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||
743 !TLI.isTypeLegal(SrcEVT) || !TLI.isTypeLegal(DstEVT))
744 // Unhandled type. Halt "fast" selection and bail.
747 MVT SrcVT = SrcEVT.getSimpleVT();
748 MVT DstVT = DstEVT.getSimpleVT();
749 unsigned Op0 = getRegForValue(I->getOperand(0));
751 // Unhandled operand. Halt "fast" selection and bail.
754 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
756 // First, try to perform the bitcast by inserting a reg-reg copy.
757 unsigned ResultReg = 0;
758 if (SrcVT == DstVT) {
759 const TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
760 const TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
761 // Don't attempt a cross-class copy. It will likely fail.
762 if (SrcClass == DstClass) {
763 ResultReg = createResultReg(DstClass);
764 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
765 ResultReg).addReg(Op0);
769 // If the reg-reg copy failed, select a BITCAST opcode.
771 ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
776 UpdateValueMap(I, ResultReg);
781 FastISel::SelectInstruction(const Instruction *I) {
782 // Just before the terminator instruction, insert instructions to
783 // feed PHI nodes in successor blocks.
784 if (isa<TerminatorInst>(I))
785 if (!HandlePHINodesInSuccessorBlocks(I->getParent()))
788 DL = I->getDebugLoc();
790 MachineBasicBlock::iterator SavedInsertPt = FuncInfo.InsertPt;
792 // As a special case, don't handle calls to builtin library functions that
793 // may be translated directly to target instructions.
794 if (const CallInst *Call = dyn_cast<CallInst>(I)) {
795 const Function *F = Call->getCalledFunction();
797 if (F && !F->hasLocalLinkage() && F->hasName() &&
798 LibInfo->getLibFunc(F->getName(), Func) &&
799 LibInfo->hasOptimizedCodeGen(Func))
803 // First, try doing target-independent selection.
804 if (SelectOperator(I, I->getOpcode())) {
805 ++NumFastIselSuccessIndependent;
809 // Remove dead code. However, ignore call instructions since we've flushed
810 // the local value map and recomputed the insert point.
811 if (!isa<CallInst>(I)) {
813 if (SavedInsertPt != FuncInfo.InsertPt)
814 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
817 // Next, try calling the target to attempt to handle the instruction.
818 SavedInsertPt = FuncInfo.InsertPt;
819 if (TargetSelectInstruction(I)) {
820 ++NumFastIselSuccessTarget;
824 // Check for dead code and remove as necessary.
826 if (SavedInsertPt != FuncInfo.InsertPt)
827 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
833 /// FastEmitBranch - Emit an unconditional branch to the given block,
834 /// unless it is the immediate (fall-through) successor, and update
837 FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) {
839 if (FuncInfo.MBB->getBasicBlock()->size() > 1 && FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
840 // For more accurate line information if this is the only instruction
841 // in the block then emit it, otherwise we have the unconditional
842 // fall-through case, which needs no instructions.
844 // The unconditional branch case.
845 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL,
846 SmallVector<MachineOperand, 0>(), DL);
848 FuncInfo.MBB->addSuccessor(MSucc);
851 /// SelectFNeg - Emit an FNeg operation.
854 FastISel::SelectFNeg(const User *I) {
855 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
856 if (OpReg == 0) return false;
858 bool OpRegIsKill = hasTrivialKill(I);
860 // If the target has ISD::FNEG, use it.
861 EVT VT = TLI.getValueType(I->getType());
862 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
863 ISD::FNEG, OpReg, OpRegIsKill);
864 if (ResultReg != 0) {
865 UpdateValueMap(I, ResultReg);
869 // Bitcast the value to integer, twiddle the sign bit with xor,
870 // and then bitcast it back to floating-point.
871 if (VT.getSizeInBits() > 64) return false;
872 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
873 if (!TLI.isTypeLegal(IntVT))
876 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
877 ISD::BITCAST, OpReg, OpRegIsKill);
881 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR,
882 IntReg, /*Kill=*/true,
883 UINT64_C(1) << (VT.getSizeInBits()-1),
884 IntVT.getSimpleVT());
885 if (IntResultReg == 0)
888 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
889 ISD::BITCAST, IntResultReg, /*Kill=*/true);
893 UpdateValueMap(I, ResultReg);
898 FastISel::SelectExtractValue(const User *U) {
899 const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U);
903 // Make sure we only try to handle extracts with a legal result. But also
904 // allow i1 because it's easy.
905 EVT RealVT = TLI.getValueType(EVI->getType(), /*AllowUnknown=*/true);
906 if (!RealVT.isSimple())
908 MVT VT = RealVT.getSimpleVT();
909 if (!TLI.isTypeLegal(VT) && VT != MVT::i1)
912 const Value *Op0 = EVI->getOperand(0);
913 Type *AggTy = Op0->getType();
915 // Get the base result register.
917 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0);
918 if (I != FuncInfo.ValueMap.end())
919 ResultReg = I->second;
920 else if (isa<Instruction>(Op0))
921 ResultReg = FuncInfo.InitializeRegForValue(Op0);
923 return false; // fast-isel can't handle aggregate constants at the moment
925 // Get the actual result register, which is an offset from the base register.
926 unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
928 SmallVector<EVT, 4> AggValueVTs;
929 ComputeValueVTs(TLI, AggTy, AggValueVTs);
931 for (unsigned i = 0; i < VTIndex; i++)
932 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
934 UpdateValueMap(EVI, ResultReg);
939 FastISel::SelectOperator(const User *I, unsigned Opcode) {
941 case Instruction::Add:
942 return SelectBinaryOp(I, ISD::ADD);
943 case Instruction::FAdd:
944 return SelectBinaryOp(I, ISD::FADD);
945 case Instruction::Sub:
946 return SelectBinaryOp(I, ISD::SUB);
947 case Instruction::FSub:
948 // FNeg is currently represented in LLVM IR as a special case of FSub.
949 if (BinaryOperator::isFNeg(I))
950 return SelectFNeg(I);
951 return SelectBinaryOp(I, ISD::FSUB);
952 case Instruction::Mul:
953 return SelectBinaryOp(I, ISD::MUL);
954 case Instruction::FMul:
955 return SelectBinaryOp(I, ISD::FMUL);
956 case Instruction::SDiv:
957 return SelectBinaryOp(I, ISD::SDIV);
958 case Instruction::UDiv:
959 return SelectBinaryOp(I, ISD::UDIV);
960 case Instruction::FDiv:
961 return SelectBinaryOp(I, ISD::FDIV);
962 case Instruction::SRem:
963 return SelectBinaryOp(I, ISD::SREM);
964 case Instruction::URem:
965 return SelectBinaryOp(I, ISD::UREM);
966 case Instruction::FRem:
967 return SelectBinaryOp(I, ISD::FREM);
968 case Instruction::Shl:
969 return SelectBinaryOp(I, ISD::SHL);
970 case Instruction::LShr:
971 return SelectBinaryOp(I, ISD::SRL);
972 case Instruction::AShr:
973 return SelectBinaryOp(I, ISD::SRA);
974 case Instruction::And:
975 return SelectBinaryOp(I, ISD::AND);
976 case Instruction::Or:
977 return SelectBinaryOp(I, ISD::OR);
978 case Instruction::Xor:
979 return SelectBinaryOp(I, ISD::XOR);
981 case Instruction::GetElementPtr:
982 return SelectGetElementPtr(I);
984 case Instruction::Br: {
985 const BranchInst *BI = cast<BranchInst>(I);
987 if (BI->isUnconditional()) {
988 const BasicBlock *LLVMSucc = BI->getSuccessor(0);
989 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
990 FastEmitBranch(MSucc, BI->getDebugLoc());
994 // Conditional branches are not handed yet.
995 // Halt "fast" selection and bail.
999 case Instruction::Unreachable:
1003 case Instruction::Alloca:
1004 // FunctionLowering has the static-sized case covered.
1005 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
1008 // Dynamic-sized alloca is not handled yet.
1011 case Instruction::Call:
1012 return SelectCall(I);
1014 case Instruction::BitCast:
1015 return SelectBitCast(I);
1017 case Instruction::FPToSI:
1018 return SelectCast(I, ISD::FP_TO_SINT);
1019 case Instruction::ZExt:
1020 return SelectCast(I, ISD::ZERO_EXTEND);
1021 case Instruction::SExt:
1022 return SelectCast(I, ISD::SIGN_EXTEND);
1023 case Instruction::Trunc:
1024 return SelectCast(I, ISD::TRUNCATE);
1025 case Instruction::SIToFP:
1026 return SelectCast(I, ISD::SINT_TO_FP);
1028 case Instruction::IntToPtr: // Deliberate fall-through.
1029 case Instruction::PtrToInt: {
1030 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1031 EVT DstVT = TLI.getValueType(I->getType());
1032 if (DstVT.bitsGT(SrcVT))
1033 return SelectCast(I, ISD::ZERO_EXTEND);
1034 if (DstVT.bitsLT(SrcVT))
1035 return SelectCast(I, ISD::TRUNCATE);
1036 unsigned Reg = getRegForValue(I->getOperand(0));
1037 if (Reg == 0) return false;
1038 UpdateValueMap(I, Reg);
1042 case Instruction::ExtractValue:
1043 return SelectExtractValue(I);
1045 case Instruction::PHI:
1046 llvm_unreachable("FastISel shouldn't visit PHI nodes!");
1049 // Unhandled instruction. Halt "fast" selection and bail.
1054 FastISel::FastISel(FunctionLoweringInfo &funcInfo,
1055 const TargetLibraryInfo *libInfo)
1056 : FuncInfo(funcInfo),
1057 MRI(FuncInfo.MF->getRegInfo()),
1058 MFI(*FuncInfo.MF->getFrameInfo()),
1059 MCP(*FuncInfo.MF->getConstantPool()),
1060 TM(FuncInfo.MF->getTarget()),
1061 TD(*TM.getDataLayout()),
1062 TII(*TM.getInstrInfo()),
1063 TLI(*TM.getTargetLowering()),
1064 TRI(*TM.getRegisterInfo()),
1068 FastISel::~FastISel() {}
1070 unsigned FastISel::FastEmit_(MVT, MVT,
1075 unsigned FastISel::FastEmit_r(MVT, MVT,
1077 unsigned /*Op0*/, bool /*Op0IsKill*/) {
1081 unsigned FastISel::FastEmit_rr(MVT, MVT,
1083 unsigned /*Op0*/, bool /*Op0IsKill*/,
1084 unsigned /*Op1*/, bool /*Op1IsKill*/) {
1088 unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1092 unsigned FastISel::FastEmit_f(MVT, MVT,
1093 unsigned, const ConstantFP * /*FPImm*/) {
1097 unsigned FastISel::FastEmit_ri(MVT, MVT,
1099 unsigned /*Op0*/, bool /*Op0IsKill*/,
1104 unsigned FastISel::FastEmit_rf(MVT, MVT,
1106 unsigned /*Op0*/, bool /*Op0IsKill*/,
1107 const ConstantFP * /*FPImm*/) {
1111 unsigned FastISel::FastEmit_rri(MVT, MVT,
1113 unsigned /*Op0*/, bool /*Op0IsKill*/,
1114 unsigned /*Op1*/, bool /*Op1IsKill*/,
1119 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
1120 /// to emit an instruction with an immediate operand using FastEmit_ri.
1121 /// If that fails, it materializes the immediate into a register and try
1122 /// FastEmit_rr instead.
1123 unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode,
1124 unsigned Op0, bool Op0IsKill,
1125 uint64_t Imm, MVT ImmType) {
1126 // If this is a multiply by a power of two, emit this as a shift left.
1127 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
1130 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
1131 // div x, 8 -> srl x, 3
1136 // Horrible hack (to be removed), check to make sure shift amounts are
1138 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
1139 Imm >= VT.getSizeInBits())
1142 // First check if immediate type is legal. If not, we can't use the ri form.
1143 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1146 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
1147 if (MaterialReg == 0) {
1148 // This is a bit ugly/slow, but failing here means falling out of
1149 // fast-isel, which would be very slow.
1150 IntegerType *ITy = IntegerType::get(FuncInfo.Fn->getContext(),
1151 VT.getSizeInBits());
1152 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
1154 return FastEmit_rr(VT, VT, Opcode,
1156 MaterialReg, /*Kill=*/true);
1159 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
1160 return MRI.createVirtualRegister(RC);
1163 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
1164 const TargetRegisterClass* RC) {
1165 unsigned ResultReg = createResultReg(RC);
1166 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1168 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg);
1172 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
1173 const TargetRegisterClass *RC,
1174 unsigned Op0, bool Op0IsKill) {
1175 unsigned ResultReg = createResultReg(RC);
1176 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1178 if (II.getNumDefs() >= 1)
1179 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1180 .addReg(Op0, Op0IsKill * RegState::Kill);
1182 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1183 .addReg(Op0, Op0IsKill * RegState::Kill);
1184 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1185 ResultReg).addReg(II.ImplicitDefs[0]);
1191 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
1192 const TargetRegisterClass *RC,
1193 unsigned Op0, bool Op0IsKill,
1194 unsigned Op1, bool Op1IsKill) {
1195 unsigned ResultReg = createResultReg(RC);
1196 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1198 if (II.getNumDefs() >= 1)
1199 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1200 .addReg(Op0, Op0IsKill * RegState::Kill)
1201 .addReg(Op1, Op1IsKill * RegState::Kill);
1203 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1204 .addReg(Op0, Op0IsKill * RegState::Kill)
1205 .addReg(Op1, Op1IsKill * RegState::Kill);
1206 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1207 ResultReg).addReg(II.ImplicitDefs[0]);
1212 unsigned FastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
1213 const TargetRegisterClass *RC,
1214 unsigned Op0, bool Op0IsKill,
1215 unsigned Op1, bool Op1IsKill,
1216 unsigned Op2, bool Op2IsKill) {
1217 unsigned ResultReg = createResultReg(RC);
1218 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1220 if (II.getNumDefs() >= 1)
1221 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1222 .addReg(Op0, Op0IsKill * RegState::Kill)
1223 .addReg(Op1, Op1IsKill * RegState::Kill)
1224 .addReg(Op2, Op2IsKill * RegState::Kill);
1226 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1227 .addReg(Op0, Op0IsKill * RegState::Kill)
1228 .addReg(Op1, Op1IsKill * RegState::Kill)
1229 .addReg(Op2, Op2IsKill * RegState::Kill);
1230 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1231 ResultReg).addReg(II.ImplicitDefs[0]);
1236 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
1237 const TargetRegisterClass *RC,
1238 unsigned Op0, bool Op0IsKill,
1240 unsigned ResultReg = createResultReg(RC);
1241 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1243 if (II.getNumDefs() >= 1)
1244 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1245 .addReg(Op0, Op0IsKill * RegState::Kill)
1248 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1249 .addReg(Op0, Op0IsKill * RegState::Kill)
1251 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1252 ResultReg).addReg(II.ImplicitDefs[0]);
1257 unsigned FastISel::FastEmitInst_rii(unsigned MachineInstOpcode,
1258 const TargetRegisterClass *RC,
1259 unsigned Op0, bool Op0IsKill,
1260 uint64_t Imm1, uint64_t Imm2) {
1261 unsigned ResultReg = createResultReg(RC);
1262 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1264 if (II.getNumDefs() >= 1)
1265 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1266 .addReg(Op0, Op0IsKill * RegState::Kill)
1270 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1271 .addReg(Op0, Op0IsKill * RegState::Kill)
1274 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1275 ResultReg).addReg(II.ImplicitDefs[0]);
1280 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
1281 const TargetRegisterClass *RC,
1282 unsigned Op0, bool Op0IsKill,
1283 const ConstantFP *FPImm) {
1284 unsigned ResultReg = createResultReg(RC);
1285 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1287 if (II.getNumDefs() >= 1)
1288 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1289 .addReg(Op0, Op0IsKill * RegState::Kill)
1292 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1293 .addReg(Op0, Op0IsKill * RegState::Kill)
1295 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1296 ResultReg).addReg(II.ImplicitDefs[0]);
1301 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
1302 const TargetRegisterClass *RC,
1303 unsigned Op0, bool Op0IsKill,
1304 unsigned Op1, bool Op1IsKill,
1306 unsigned ResultReg = createResultReg(RC);
1307 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1309 if (II.getNumDefs() >= 1)
1310 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1311 .addReg(Op0, Op0IsKill * RegState::Kill)
1312 .addReg(Op1, Op1IsKill * RegState::Kill)
1315 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1316 .addReg(Op0, Op0IsKill * RegState::Kill)
1317 .addReg(Op1, Op1IsKill * RegState::Kill)
1319 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1320 ResultReg).addReg(II.ImplicitDefs[0]);
1325 unsigned FastISel::FastEmitInst_rrii(unsigned MachineInstOpcode,
1326 const TargetRegisterClass *RC,
1327 unsigned Op0, bool Op0IsKill,
1328 unsigned Op1, bool Op1IsKill,
1329 uint64_t Imm1, uint64_t Imm2) {
1330 unsigned ResultReg = createResultReg(RC);
1331 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1333 if (II.getNumDefs() >= 1)
1334 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1335 .addReg(Op0, Op0IsKill * RegState::Kill)
1336 .addReg(Op1, Op1IsKill * RegState::Kill)
1337 .addImm(Imm1).addImm(Imm2);
1339 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1340 .addReg(Op0, Op0IsKill * RegState::Kill)
1341 .addReg(Op1, Op1IsKill * RegState::Kill)
1342 .addImm(Imm1).addImm(Imm2);
1343 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1344 ResultReg).addReg(II.ImplicitDefs[0]);
1349 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
1350 const TargetRegisterClass *RC,
1352 unsigned ResultReg = createResultReg(RC);
1353 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1355 if (II.getNumDefs() >= 1)
1356 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm);
1358 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm);
1359 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1360 ResultReg).addReg(II.ImplicitDefs[0]);
1365 unsigned FastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
1366 const TargetRegisterClass *RC,
1367 uint64_t Imm1, uint64_t Imm2) {
1368 unsigned ResultReg = createResultReg(RC);
1369 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1371 if (II.getNumDefs() >= 1)
1372 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1373 .addImm(Imm1).addImm(Imm2);
1375 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm1).addImm(Imm2);
1376 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1377 ResultReg).addReg(II.ImplicitDefs[0]);
1382 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
1383 unsigned Op0, bool Op0IsKill,
1385 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1386 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1387 "Cannot yet extract from physregs");
1388 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
1389 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
1390 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
1391 DL, TII.get(TargetOpcode::COPY), ResultReg)
1392 .addReg(Op0, getKillRegState(Op0IsKill), Idx);
1396 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1397 /// with all but the least significant bit set to zero.
1398 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1399 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
1402 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
1403 /// Emit code to ensure constants are copied into registers when needed.
1404 /// Remember the virtual registers that need to be added to the Machine PHI
1405 /// nodes as input. We cannot just directly add them, because expansion
1406 /// might result in multiple MBB's for one BB. As such, the start of the
1407 /// BB might correspond to a different MBB than the end.
1408 bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
1409 const TerminatorInst *TI = LLVMBB->getTerminator();
1411 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
1412 unsigned OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size();
1414 // Check successor nodes' PHI nodes that expect a constant to be available
1416 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
1417 const BasicBlock *SuccBB = TI->getSuccessor(succ);
1418 if (!isa<PHINode>(SuccBB->begin())) continue;
1419 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
1421 // If this terminator has multiple identical successors (common for
1422 // switches), only handle each succ once.
1423 if (!SuccsHandled.insert(SuccMBB)) continue;
1425 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
1427 // At this point we know that there is a 1-1 correspondence between LLVM PHI
1428 // nodes and Machine PHI nodes, but the incoming operands have not been
1430 for (BasicBlock::const_iterator I = SuccBB->begin();
1431 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
1433 // Ignore dead phi's.
1434 if (PN->use_empty()) continue;
1436 // Only handle legal types. Two interesting things to note here. First,
1437 // by bailing out early, we may leave behind some dead instructions,
1438 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
1439 // own moves. Second, this check is necessary because FastISel doesn't
1440 // use CreateRegs to create registers, so it always creates
1441 // exactly one register for each non-void instruction.
1442 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
1443 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
1444 // Handle integer promotions, though, because they're common and easy.
1445 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
1446 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT);
1448 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
1453 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
1455 // Set the DebugLoc for the copy. Prefer the location of the operand
1456 // if there is one; use the location of the PHI otherwise.
1457 DL = PN->getDebugLoc();
1458 if (const Instruction *Inst = dyn_cast<Instruction>(PHIOp))
1459 DL = Inst->getDebugLoc();
1461 unsigned Reg = getRegForValue(PHIOp);
1463 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
1466 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));