1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/Target/TargetData.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/SmallPtrSet.h"
39 #include "llvm/ADT/Statistic.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/MathExtras.h"
47 STATISTIC(NodesCombined , "Number of dag nodes combined");
48 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
49 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
54 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
55 cl::desc("Pop up a window to show dags before the first "
58 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
59 cl::desc("Pop up a window to show dags before the second "
62 static const bool ViewDAGCombine1 = false;
63 static const bool ViewDAGCombine2 = false;
67 CombinerAA("combiner-alias-analysis", cl::Hidden,
68 cl::desc("Turn on alias analysis during testing"));
71 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
72 cl::desc("Include global information in alias analysis"));
74 //------------------------------ DAGCombiner ---------------------------------//
76 class VISIBILITY_HIDDEN DAGCombiner {
81 // Worklist of all of the nodes that need to be simplified.
82 std::vector<SDNode*> WorkList;
84 // AA - Used for DAG load/store alias analysis.
87 /// AddUsersToWorkList - When an instruction is simplified, add all users of
88 /// the instruction to the work lists because they might get more simplified
91 void AddUsersToWorkList(SDNode *N) {
92 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
97 /// removeFromWorkList - remove all instances of N from the worklist.
99 void removeFromWorkList(SDNode *N) {
100 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
104 /// visit - call the node-specific routine that knows how to fold each
105 /// particular type of node.
106 SDOperand visit(SDNode *N);
109 /// AddToWorkList - Add to the work list making sure it's instance is at the
110 /// the back (next to be processed.)
111 void AddToWorkList(SDNode *N) {
112 removeFromWorkList(N);
113 WorkList.push_back(N);
116 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
118 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
120 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
121 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
122 DOUT << " and " << NumTo-1 << " other values\n";
123 std::vector<SDNode*> NowDead;
124 DAG.ReplaceAllUsesWith(N, To, &NowDead);
127 // Push the new nodes and any users onto the worklist
128 for (unsigned i = 0, e = NumTo; i != e; ++i) {
129 AddToWorkList(To[i].Val);
130 AddUsersToWorkList(To[i].Val);
134 // Nodes can be reintroduced into the worklist. Make sure we do not
135 // process a node that has been replaced.
136 removeFromWorkList(N);
137 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
138 removeFromWorkList(NowDead[i]);
140 // Finally, since the node is now dead, remove it from the graph.
142 return SDOperand(N, 0);
145 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
146 return CombineTo(N, &Res, 1, AddTo);
149 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
151 SDOperand To[] = { Res0, Res1 };
152 return CombineTo(N, To, 2, AddTo);
156 /// SimplifyDemandedBits - Check the specified integer node value to see if
157 /// it can be simplified or if things it uses can be simplified by bit
158 /// propagation. If so, return true.
159 bool SimplifyDemandedBits(SDOperand Op, uint64_t Demanded = ~0ULL) {
160 TargetLowering::TargetLoweringOpt TLO(DAG);
161 uint64_t KnownZero, KnownOne;
162 Demanded &= MVT::getIntVTBitMask(Op.getValueType());
163 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
167 AddToWorkList(Op.Val);
169 // Replace the old value with the new one.
171 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
172 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
175 std::vector<SDNode*> NowDead;
176 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &NowDead);
178 // Push the new node and any (possibly new) users onto the worklist.
179 AddToWorkList(TLO.New.Val);
180 AddUsersToWorkList(TLO.New.Val);
182 // Nodes can end up on the worklist more than once. Make sure we do
183 // not process a node that has been replaced.
184 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
185 removeFromWorkList(NowDead[i]);
187 // Finally, if the node is now dead, remove it from the graph. The node
188 // may not be dead if the replacement process recursively simplified to
189 // something else needing this node.
190 if (TLO.Old.Val->use_empty()) {
191 removeFromWorkList(TLO.Old.Val);
193 // If the operands of this node are only used by the node, they will now
194 // be dead. Make sure to visit them first to delete dead nodes early.
195 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i)
196 if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
197 AddToWorkList(TLO.Old.Val->getOperand(i).Val);
199 DAG.DeleteNode(TLO.Old.Val);
204 bool CombineToPreIndexedLoadStore(SDNode *N);
205 bool CombineToPostIndexedLoadStore(SDNode *N);
208 /// combine - call the node-specific routine that knows how to fold each
209 /// particular type of node. If that doesn't do anything, try the
210 /// target-specific DAG combines.
211 SDOperand combine(SDNode *N);
213 // Visitation implementation - Implement dag node combining for different
214 // node types. The semantics are as follows:
216 // SDOperand.Val == 0 - No change was made
217 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
218 // otherwise - N should be replaced by the returned Operand.
220 SDOperand visitTokenFactor(SDNode *N);
221 SDOperand visitADD(SDNode *N);
222 SDOperand visitSUB(SDNode *N);
223 SDOperand visitADDC(SDNode *N);
224 SDOperand visitADDE(SDNode *N);
225 SDOperand visitMUL(SDNode *N);
226 SDOperand visitSDIV(SDNode *N);
227 SDOperand visitUDIV(SDNode *N);
228 SDOperand visitSREM(SDNode *N);
229 SDOperand visitUREM(SDNode *N);
230 SDOperand visitMULHU(SDNode *N);
231 SDOperand visitMULHS(SDNode *N);
232 SDOperand visitSMUL_LOHI(SDNode *N);
233 SDOperand visitUMUL_LOHI(SDNode *N);
234 SDOperand visitSDIVREM(SDNode *N);
235 SDOperand visitUDIVREM(SDNode *N);
236 SDOperand visitAND(SDNode *N);
237 SDOperand visitOR(SDNode *N);
238 SDOperand visitXOR(SDNode *N);
239 SDOperand SimplifyVBinOp(SDNode *N);
240 SDOperand visitSHL(SDNode *N);
241 SDOperand visitSRA(SDNode *N);
242 SDOperand visitSRL(SDNode *N);
243 SDOperand visitCTLZ(SDNode *N);
244 SDOperand visitCTTZ(SDNode *N);
245 SDOperand visitCTPOP(SDNode *N);
246 SDOperand visitSELECT(SDNode *N);
247 SDOperand visitSELECT_CC(SDNode *N);
248 SDOperand visitSETCC(SDNode *N);
249 SDOperand visitSIGN_EXTEND(SDNode *N);
250 SDOperand visitZERO_EXTEND(SDNode *N);
251 SDOperand visitANY_EXTEND(SDNode *N);
252 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
253 SDOperand visitTRUNCATE(SDNode *N);
254 SDOperand visitBIT_CONVERT(SDNode *N);
255 SDOperand visitFADD(SDNode *N);
256 SDOperand visitFSUB(SDNode *N);
257 SDOperand visitFMUL(SDNode *N);
258 SDOperand visitFDIV(SDNode *N);
259 SDOperand visitFREM(SDNode *N);
260 SDOperand visitFCOPYSIGN(SDNode *N);
261 SDOperand visitSINT_TO_FP(SDNode *N);
262 SDOperand visitUINT_TO_FP(SDNode *N);
263 SDOperand visitFP_TO_SINT(SDNode *N);
264 SDOperand visitFP_TO_UINT(SDNode *N);
265 SDOperand visitFP_ROUND(SDNode *N);
266 SDOperand visitFP_ROUND_INREG(SDNode *N);
267 SDOperand visitFP_EXTEND(SDNode *N);
268 SDOperand visitFNEG(SDNode *N);
269 SDOperand visitFABS(SDNode *N);
270 SDOperand visitBRCOND(SDNode *N);
271 SDOperand visitBR_CC(SDNode *N);
272 SDOperand visitLOAD(SDNode *N);
273 SDOperand visitSTORE(SDNode *N);
274 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
275 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N);
276 SDOperand visitBUILD_VECTOR(SDNode *N);
277 SDOperand visitCONCAT_VECTORS(SDNode *N);
278 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
280 SDOperand XformToShuffleWithZero(SDNode *N);
281 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
283 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
284 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
285 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
286 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
287 SDOperand N3, ISD::CondCode CC,
288 bool NotExtCompare = false);
289 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
290 ISD::CondCode Cond, bool foldBooleans = true);
291 bool SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp);
292 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
293 SDOperand BuildSDIV(SDNode *N);
294 SDOperand BuildUDIV(SDNode *N);
295 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
296 SDOperand ReduceLoadWidth(SDNode *N);
298 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask);
300 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
301 /// looking for aliasing nodes and adding them to the Aliases vector.
302 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
303 SmallVector<SDOperand, 8> &Aliases);
305 /// isAlias - Return true if there is any possibility that the two addresses
307 bool isAlias(SDOperand Ptr1, int64_t Size1,
308 const Value *SrcValue1, int SrcValueOffset1,
309 SDOperand Ptr2, int64_t Size2,
310 const Value *SrcValue2, int SrcValueOffset2);
312 /// FindAliasInfo - Extracts the relevant alias information from the memory
313 /// node. Returns true if the operand was a load.
314 bool FindAliasInfo(SDNode *N,
315 SDOperand &Ptr, int64_t &Size,
316 const Value *&SrcValue, int &SrcValueOffset);
318 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
319 /// looking for a better chain (aliasing node.)
320 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
323 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
325 TLI(D.getTargetLoweringInfo()),
326 AfterLegalize(false),
329 /// Run - runs the dag combiner on all nodes in the work list
330 void Run(bool RunningAfterLegalize);
334 //===----------------------------------------------------------------------===//
335 // TargetLowering::DAGCombinerInfo implementation
336 //===----------------------------------------------------------------------===//
338 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
339 ((DAGCombiner*)DC)->AddToWorkList(N);
342 SDOperand TargetLowering::DAGCombinerInfo::
343 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
344 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
347 SDOperand TargetLowering::DAGCombinerInfo::
348 CombineTo(SDNode *N, SDOperand Res) {
349 return ((DAGCombiner*)DC)->CombineTo(N, Res);
353 SDOperand TargetLowering::DAGCombinerInfo::
354 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
355 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
359 //===----------------------------------------------------------------------===//
361 //===----------------------------------------------------------------------===//
363 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
364 /// specified expression for the same cost as the expression itself, or 2 if we
365 /// can compute the negated form more cheaply than the expression itself.
366 static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) {
367 // No compile time optimizations on this type.
368 if (Op.getValueType() == MVT::ppcf128)
371 // fneg is removable even if it has multiple uses.
372 if (Op.getOpcode() == ISD::FNEG) return 2;
374 // Don't allow anything with multiple uses.
375 if (!Op.hasOneUse()) return 0;
377 // Don't recurse exponentially.
378 if (Depth > 6) return 0;
380 switch (Op.getOpcode()) {
381 default: return false;
382 case ISD::ConstantFP:
385 // FIXME: determine better conditions for this xform.
386 if (!UnsafeFPMath) return 0;
389 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
392 return isNegatibleForFree(Op.getOperand(1), Depth+1);
394 // We can't turn -(A-B) into B-A when we honor signed zeros.
395 if (!UnsafeFPMath) return 0;
402 if (HonorSignDependentRoundingFPMath()) return 0;
404 // -(X*Y) -> (-X * Y) or (X*-Y)
405 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
408 return isNegatibleForFree(Op.getOperand(1), Depth+1);
413 return isNegatibleForFree(Op.getOperand(0), Depth+1);
417 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
418 /// returns the newly negated expression.
419 static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
420 unsigned Depth = 0) {
421 // fneg is removable even if it has multiple uses.
422 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
424 // Don't allow anything with multiple uses.
425 assert(Op.hasOneUse() && "Unknown reuse!");
427 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
428 switch (Op.getOpcode()) {
429 default: assert(0 && "Unknown code");
430 case ISD::ConstantFP: {
431 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
433 return DAG.getConstantFP(V, Op.getValueType());
436 // FIXME: determine better conditions for this xform.
437 assert(UnsafeFPMath);
440 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
441 return DAG.getNode(ISD::FSUB, Op.getValueType(),
442 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
445 return DAG.getNode(ISD::FSUB, Op.getValueType(),
446 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1),
449 // We can't turn -(A-B) into B-A when we honor signed zeros.
450 assert(UnsafeFPMath);
453 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
454 if (N0CFP->getValueAPF().isZero())
455 return Op.getOperand(1);
458 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1),
463 assert(!HonorSignDependentRoundingFPMath());
466 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
467 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
468 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
472 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
474 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1));
479 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
480 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1));
485 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
486 // that selects between the values 1 and 0, making it equivalent to a setcc.
487 // Also, set the incoming LHS, RHS, and CC references to the appropriate
488 // nodes based on the type of node we are checking. This simplifies life a
489 // bit for the callers.
490 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
492 if (N.getOpcode() == ISD::SETCC) {
493 LHS = N.getOperand(0);
494 RHS = N.getOperand(1);
495 CC = N.getOperand(2);
498 if (N.getOpcode() == ISD::SELECT_CC &&
499 N.getOperand(2).getOpcode() == ISD::Constant &&
500 N.getOperand(3).getOpcode() == ISD::Constant &&
501 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
502 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
503 LHS = N.getOperand(0);
504 RHS = N.getOperand(1);
505 CC = N.getOperand(4);
511 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
512 // one use. If this is true, it allows the users to invert the operation for
513 // free when it is profitable to do so.
514 static bool isOneUseSetCC(SDOperand N) {
515 SDOperand N0, N1, N2;
516 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
521 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
522 MVT::ValueType VT = N0.getValueType();
523 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
524 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
525 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
526 if (isa<ConstantSDNode>(N1)) {
527 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
528 AddToWorkList(OpNode.Val);
529 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
530 } else if (N0.hasOneUse()) {
531 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
532 AddToWorkList(OpNode.Val);
533 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
536 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
537 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
538 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
539 if (isa<ConstantSDNode>(N0)) {
540 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
541 AddToWorkList(OpNode.Val);
542 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
543 } else if (N1.hasOneUse()) {
544 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
545 AddToWorkList(OpNode.Val);
546 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
552 //===----------------------------------------------------------------------===//
553 // Main DAG Combiner implementation
554 //===----------------------------------------------------------------------===//
556 void DAGCombiner::Run(bool RunningAfterLegalize) {
557 // set the instance variable, so that the various visit routines may use it.
558 AfterLegalize = RunningAfterLegalize;
560 // Add all the dag nodes to the worklist.
561 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
562 E = DAG.allnodes_end(); I != E; ++I)
563 WorkList.push_back(I);
565 // Create a dummy node (which is not added to allnodes), that adds a reference
566 // to the root node, preventing it from being deleted, and tracking any
567 // changes of the root.
568 HandleSDNode Dummy(DAG.getRoot());
570 // The root of the dag may dangle to deleted nodes until the dag combiner is
571 // done. Set it to null to avoid confusion.
572 DAG.setRoot(SDOperand());
574 // while the worklist isn't empty, inspect the node on the end of it and
575 // try and combine it.
576 while (!WorkList.empty()) {
577 SDNode *N = WorkList.back();
580 // If N has no uses, it is dead. Make sure to revisit all N's operands once
581 // N is deleted from the DAG, since they too may now be dead or may have a
582 // reduced number of uses, allowing other xforms.
583 if (N->use_empty() && N != &Dummy) {
584 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
585 AddToWorkList(N->getOperand(i).Val);
591 SDOperand RV = combine(N);
595 // If we get back the same node we passed in, rather than a new node or
596 // zero, we know that the node must have defined multiple values and
597 // CombineTo was used. Since CombineTo takes care of the worklist
598 // mechanics for us, we have no work to do in this case.
600 assert(N->getOpcode() != ISD::DELETED_NODE &&
601 RV.Val->getOpcode() != ISD::DELETED_NODE &&
602 "Node was deleted but visit returned new node!");
604 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
605 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
607 std::vector<SDNode*> NowDead;
608 if (N->getNumValues() == RV.Val->getNumValues())
609 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
611 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
613 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
616 // Push the new node and any users onto the worklist
617 AddToWorkList(RV.Val);
618 AddUsersToWorkList(RV.Val);
620 // Nodes can be reintroduced into the worklist. Make sure we do not
621 // process a node that has been replaced.
622 removeFromWorkList(N);
623 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
624 removeFromWorkList(NowDead[i]);
626 // Finally, since the node is now dead, remove it from the graph.
632 // If the root changed (e.g. it was a dead load, update the root).
633 DAG.setRoot(Dummy.getValue());
636 SDOperand DAGCombiner::visit(SDNode *N) {
637 switch(N->getOpcode()) {
639 case ISD::TokenFactor: return visitTokenFactor(N);
640 case ISD::ADD: return visitADD(N);
641 case ISD::SUB: return visitSUB(N);
642 case ISD::ADDC: return visitADDC(N);
643 case ISD::ADDE: return visitADDE(N);
644 case ISD::MUL: return visitMUL(N);
645 case ISD::SDIV: return visitSDIV(N);
646 case ISD::UDIV: return visitUDIV(N);
647 case ISD::SREM: return visitSREM(N);
648 case ISD::UREM: return visitUREM(N);
649 case ISD::MULHU: return visitMULHU(N);
650 case ISD::MULHS: return visitMULHS(N);
651 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
652 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
653 case ISD::SDIVREM: return visitSDIVREM(N);
654 case ISD::UDIVREM: return visitUDIVREM(N);
655 case ISD::AND: return visitAND(N);
656 case ISD::OR: return visitOR(N);
657 case ISD::XOR: return visitXOR(N);
658 case ISD::SHL: return visitSHL(N);
659 case ISD::SRA: return visitSRA(N);
660 case ISD::SRL: return visitSRL(N);
661 case ISD::CTLZ: return visitCTLZ(N);
662 case ISD::CTTZ: return visitCTTZ(N);
663 case ISD::CTPOP: return visitCTPOP(N);
664 case ISD::SELECT: return visitSELECT(N);
665 case ISD::SELECT_CC: return visitSELECT_CC(N);
666 case ISD::SETCC: return visitSETCC(N);
667 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
668 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
669 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
670 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
671 case ISD::TRUNCATE: return visitTRUNCATE(N);
672 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
673 case ISD::FADD: return visitFADD(N);
674 case ISD::FSUB: return visitFSUB(N);
675 case ISD::FMUL: return visitFMUL(N);
676 case ISD::FDIV: return visitFDIV(N);
677 case ISD::FREM: return visitFREM(N);
678 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
679 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
680 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
681 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
682 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
683 case ISD::FP_ROUND: return visitFP_ROUND(N);
684 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
685 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
686 case ISD::FNEG: return visitFNEG(N);
687 case ISD::FABS: return visitFABS(N);
688 case ISD::BRCOND: return visitBRCOND(N);
689 case ISD::BR_CC: return visitBR_CC(N);
690 case ISD::LOAD: return visitLOAD(N);
691 case ISD::STORE: return visitSTORE(N);
692 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
693 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
694 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
695 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
696 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
701 SDOperand DAGCombiner::combine(SDNode *N) {
703 SDOperand RV = visit(N);
705 // If nothing happened, try a target-specific DAG combine.
707 assert(N->getOpcode() != ISD::DELETED_NODE &&
708 "Node was deleted but visit returned NULL!");
710 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
711 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
713 // Expose the DAG combiner to the target combiner impls.
714 TargetLowering::DAGCombinerInfo
715 DagCombineInfo(DAG, !AfterLegalize, false, this);
717 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
724 /// getInputChainForNode - Given a node, return its input chain if it has one,
725 /// otherwise return a null sd operand.
726 static SDOperand getInputChainForNode(SDNode *N) {
727 if (unsigned NumOps = N->getNumOperands()) {
728 if (N->getOperand(0).getValueType() == MVT::Other)
729 return N->getOperand(0);
730 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
731 return N->getOperand(NumOps-1);
732 for (unsigned i = 1; i < NumOps-1; ++i)
733 if (N->getOperand(i).getValueType() == MVT::Other)
734 return N->getOperand(i);
736 return SDOperand(0, 0);
739 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
740 // If N has two operands, where one has an input chain equal to the other,
741 // the 'other' chain is redundant.
742 if (N->getNumOperands() == 2) {
743 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
744 return N->getOperand(0);
745 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
746 return N->getOperand(1);
749 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
750 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
751 SmallPtrSet<SDNode*, 16> SeenOps;
752 bool Changed = false; // If we should replace this token factor.
754 // Start out with this token factor.
757 // Iterate through token factors. The TFs grows when new token factors are
759 for (unsigned i = 0; i < TFs.size(); ++i) {
762 // Check each of the operands.
763 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
764 SDOperand Op = TF->getOperand(i);
766 switch (Op.getOpcode()) {
767 case ISD::EntryToken:
768 // Entry tokens don't need to be added to the list. They are
773 case ISD::TokenFactor:
774 if ((CombinerAA || Op.hasOneUse()) &&
775 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
776 // Queue up for processing.
777 TFs.push_back(Op.Val);
778 // Clean up in case the token factor is removed.
779 AddToWorkList(Op.Val);
786 // Only add if it isn't already in the list.
787 if (SeenOps.insert(Op.Val))
798 // If we've change things around then replace token factor.
800 if (Ops.size() == 0) {
801 // The entry token is the only possible outcome.
802 Result = DAG.getEntryNode();
804 // New and improved token factor.
805 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
808 // Don't add users to work list.
809 return CombineTo(N, Result, false);
816 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
817 MVT::ValueType VT = N0.getValueType();
818 SDOperand N00 = N0.getOperand(0);
819 SDOperand N01 = N0.getOperand(1);
820 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
821 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
822 isa<ConstantSDNode>(N00.getOperand(1))) {
823 N0 = DAG.getNode(ISD::ADD, VT,
824 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
825 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
826 return DAG.getNode(ISD::ADD, VT, N0, N1);
832 SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
834 MVT::ValueType VT = N->getValueType(0);
835 unsigned Opc = N->getOpcode();
836 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
837 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
838 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
839 ISD::CondCode CC = ISD::SETCC_INVALID;
841 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
843 SDOperand CCOp = Slct.getOperand(0);
844 if (CCOp.getOpcode() == ISD::SETCC)
845 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
848 bool DoXform = false;
850 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
852 if (LHS.getOpcode() == ISD::Constant &&
853 cast<ConstantSDNode>(LHS)->isNullValue())
855 else if (CC != ISD::SETCC_INVALID &&
856 RHS.getOpcode() == ISD::Constant &&
857 cast<ConstantSDNode>(RHS)->isNullValue()) {
859 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType()
860 : Slct.getOperand(0).getOperand(0).getValueType());
861 CC = ISD::getSetCCInverse(CC, isInt);
867 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS);
869 return DAG.getSelectCC(OtherOp, Result,
870 Slct.getOperand(0), Slct.getOperand(1), CC);
871 SDOperand CCOp = Slct.getOperand(0);
873 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
874 CCOp.getOperand(1), CC);
875 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
880 SDOperand DAGCombiner::visitADD(SDNode *N) {
881 SDOperand N0 = N->getOperand(0);
882 SDOperand N1 = N->getOperand(1);
883 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
884 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
885 MVT::ValueType VT = N0.getValueType();
888 if (MVT::isVector(VT)) {
889 SDOperand FoldedVOp = SimplifyVBinOp(N);
890 if (FoldedVOp.Val) return FoldedVOp;
893 // fold (add x, undef) -> undef
894 if (N0.getOpcode() == ISD::UNDEF)
896 if (N1.getOpcode() == ISD::UNDEF)
898 // fold (add c1, c2) -> c1+c2
900 return DAG.getNode(ISD::ADD, VT, N0, N1);
901 // canonicalize constant to RHS
903 return DAG.getNode(ISD::ADD, VT, N1, N0);
904 // fold (add x, 0) -> x
905 if (N1C && N1C->isNullValue())
907 // fold ((c1-A)+c2) -> (c1+c2)-A
908 if (N1C && N0.getOpcode() == ISD::SUB)
909 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
910 return DAG.getNode(ISD::SUB, VT,
911 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
914 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
917 // fold ((0-A) + B) -> B-A
918 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
919 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
920 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
921 // fold (A + (0-B)) -> A-B
922 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
923 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
924 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
925 // fold (A+(B-A)) -> B
926 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
927 return N1.getOperand(0);
929 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
930 return SDOperand(N, 0);
932 // fold (a+b) -> (a|b) iff a and b share no bits.
933 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
934 uint64_t LHSZero, LHSOne;
935 uint64_t RHSZero, RHSOne;
936 uint64_t Mask = MVT::getIntVTBitMask(VT);
937 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
939 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
941 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
942 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
943 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
944 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
945 return DAG.getNode(ISD::OR, VT, N0, N1);
949 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
950 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
951 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
952 if (Result.Val) return Result;
954 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
955 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
956 if (Result.Val) return Result;
959 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
960 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
961 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG);
962 if (Result.Val) return Result;
964 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
965 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
966 if (Result.Val) return Result;
972 SDOperand DAGCombiner::visitADDC(SDNode *N) {
973 SDOperand N0 = N->getOperand(0);
974 SDOperand N1 = N->getOperand(1);
975 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
976 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
977 MVT::ValueType VT = N0.getValueType();
979 // If the flag result is dead, turn this into an ADD.
980 if (N->hasNUsesOfValue(0, 1))
981 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
982 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
984 // canonicalize constant to RHS.
986 SDOperand Ops[] = { N1, N0 };
987 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
990 // fold (addc x, 0) -> x + no carry out
991 if (N1C && N1C->isNullValue())
992 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
994 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
995 uint64_t LHSZero, LHSOne;
996 uint64_t RHSZero, RHSOne;
997 uint64_t Mask = MVT::getIntVTBitMask(VT);
998 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1000 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1002 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1003 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1004 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1005 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1006 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
1007 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
1013 SDOperand DAGCombiner::visitADDE(SDNode *N) {
1014 SDOperand N0 = N->getOperand(0);
1015 SDOperand N1 = N->getOperand(1);
1016 SDOperand CarryIn = N->getOperand(2);
1017 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1018 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1019 //MVT::ValueType VT = N0.getValueType();
1021 // canonicalize constant to RHS
1023 SDOperand Ops[] = { N1, N0, CarryIn };
1024 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
1027 // fold (adde x, y, false) -> (addc x, y)
1028 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
1029 SDOperand Ops[] = { N1, N0 };
1030 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
1038 SDOperand DAGCombiner::visitSUB(SDNode *N) {
1039 SDOperand N0 = N->getOperand(0);
1040 SDOperand N1 = N->getOperand(1);
1041 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1042 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1043 MVT::ValueType VT = N0.getValueType();
1046 if (MVT::isVector(VT)) {
1047 SDOperand FoldedVOp = SimplifyVBinOp(N);
1048 if (FoldedVOp.Val) return FoldedVOp;
1051 // fold (sub x, x) -> 0
1053 return DAG.getConstant(0, N->getValueType(0));
1054 // fold (sub c1, c2) -> c1-c2
1056 return DAG.getNode(ISD::SUB, VT, N0, N1);
1057 // fold (sub x, c) -> (add x, -c)
1059 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
1060 // fold (A+B)-A -> B
1061 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1062 return N0.getOperand(1);
1063 // fold (A+B)-B -> A
1064 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1065 return N0.getOperand(0);
1066 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1067 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
1068 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
1069 if (Result.Val) return Result;
1071 // If either operand of a sub is undef, the result is undef
1072 if (N0.getOpcode() == ISD::UNDEF)
1074 if (N1.getOpcode() == ISD::UNDEF)
1080 SDOperand DAGCombiner::visitMUL(SDNode *N) {
1081 SDOperand N0 = N->getOperand(0);
1082 SDOperand N1 = N->getOperand(1);
1083 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1084 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1085 MVT::ValueType VT = N0.getValueType();
1088 if (MVT::isVector(VT)) {
1089 SDOperand FoldedVOp = SimplifyVBinOp(N);
1090 if (FoldedVOp.Val) return FoldedVOp;
1093 // fold (mul x, undef) -> 0
1094 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1095 return DAG.getConstant(0, VT);
1096 // fold (mul c1, c2) -> c1*c2
1098 return DAG.getNode(ISD::MUL, VT, N0, N1);
1099 // canonicalize constant to RHS
1101 return DAG.getNode(ISD::MUL, VT, N1, N0);
1102 // fold (mul x, 0) -> 0
1103 if (N1C && N1C->isNullValue())
1105 // fold (mul x, -1) -> 0-x
1106 if (N1C && N1C->isAllOnesValue())
1107 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1108 // fold (mul x, (1 << c)) -> x << c
1109 if (N1C && isPowerOf2_64(N1C->getValue()))
1110 return DAG.getNode(ISD::SHL, VT, N0,
1111 DAG.getConstant(Log2_64(N1C->getValue()),
1112 TLI.getShiftAmountTy()));
1113 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1114 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
1115 // FIXME: If the input is something that is easily negated (e.g. a
1116 // single-use add), we should put the negate there.
1117 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
1118 DAG.getNode(ISD::SHL, VT, N0,
1119 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
1120 TLI.getShiftAmountTy())));
1123 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1124 if (N1C && N0.getOpcode() == ISD::SHL &&
1125 isa<ConstantSDNode>(N0.getOperand(1))) {
1126 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
1127 AddToWorkList(C3.Val);
1128 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
1131 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1134 SDOperand Sh(0,0), Y(0,0);
1135 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1136 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1137 N0.Val->hasOneUse()) {
1139 } else if (N1.getOpcode() == ISD::SHL &&
1140 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
1144 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
1145 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
1148 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1149 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1150 isa<ConstantSDNode>(N0.getOperand(1))) {
1151 return DAG.getNode(ISD::ADD, VT,
1152 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
1153 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
1157 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
1164 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
1165 SDOperand N0 = N->getOperand(0);
1166 SDOperand N1 = N->getOperand(1);
1167 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1168 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1169 MVT::ValueType VT = N->getValueType(0);
1172 if (MVT::isVector(VT)) {
1173 SDOperand FoldedVOp = SimplifyVBinOp(N);
1174 if (FoldedVOp.Val) return FoldedVOp;
1177 // fold (sdiv c1, c2) -> c1/c2
1178 if (N0C && N1C && !N1C->isNullValue())
1179 return DAG.getNode(ISD::SDIV, VT, N0, N1);
1180 // fold (sdiv X, 1) -> X
1181 if (N1C && N1C->getSignExtended() == 1LL)
1183 // fold (sdiv X, -1) -> 0-X
1184 if (N1C && N1C->isAllOnesValue())
1185 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1186 // If we know the sign bits of both operands are zero, strength reduce to a
1187 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1188 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1189 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1190 DAG.MaskedValueIsZero(N0, SignBit))
1191 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
1192 // fold (sdiv X, pow2) -> simple ops after legalize
1193 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
1194 (isPowerOf2_64(N1C->getSignExtended()) ||
1195 isPowerOf2_64(-N1C->getSignExtended()))) {
1196 // If dividing by powers of two is cheap, then don't perform the following
1198 if (TLI.isPow2DivCheap())
1200 int64_t pow2 = N1C->getSignExtended();
1201 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1202 unsigned lg2 = Log2_64(abs2);
1203 // Splat the sign bit into the register
1204 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
1205 DAG.getConstant(MVT::getSizeInBits(VT)-1,
1206 TLI.getShiftAmountTy()));
1207 AddToWorkList(SGN.Val);
1208 // Add (N0 < 0) ? abs2 - 1 : 0;
1209 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
1210 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
1211 TLI.getShiftAmountTy()));
1212 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
1213 AddToWorkList(SRL.Val);
1214 AddToWorkList(ADD.Val); // Divide by pow2
1215 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
1216 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
1217 // If we're dividing by a positive value, we're done. Otherwise, we must
1218 // negate the result.
1221 AddToWorkList(SRA.Val);
1222 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
1224 // if integer divide is expensive and we satisfy the requirements, emit an
1225 // alternate sequence.
1226 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
1227 !TLI.isIntDivCheap()) {
1228 SDOperand Op = BuildSDIV(N);
1229 if (Op.Val) return Op;
1233 if (N0.getOpcode() == ISD::UNDEF)
1234 return DAG.getConstant(0, VT);
1235 // X / undef -> undef
1236 if (N1.getOpcode() == ISD::UNDEF)
1242 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
1243 SDOperand N0 = N->getOperand(0);
1244 SDOperand N1 = N->getOperand(1);
1245 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1246 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1247 MVT::ValueType VT = N->getValueType(0);
1250 if (MVT::isVector(VT)) {
1251 SDOperand FoldedVOp = SimplifyVBinOp(N);
1252 if (FoldedVOp.Val) return FoldedVOp;
1255 // fold (udiv c1, c2) -> c1/c2
1256 if (N0C && N1C && !N1C->isNullValue())
1257 return DAG.getNode(ISD::UDIV, VT, N0, N1);
1258 // fold (udiv x, (1 << c)) -> x >>u c
1259 if (N1C && isPowerOf2_64(N1C->getValue()))
1260 return DAG.getNode(ISD::SRL, VT, N0,
1261 DAG.getConstant(Log2_64(N1C->getValue()),
1262 TLI.getShiftAmountTy()));
1263 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1264 if (N1.getOpcode() == ISD::SHL) {
1265 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1266 if (isPowerOf2_64(SHC->getValue())) {
1267 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
1268 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
1269 DAG.getConstant(Log2_64(SHC->getValue()),
1271 AddToWorkList(Add.Val);
1272 return DAG.getNode(ISD::SRL, VT, N0, Add);
1276 // fold (udiv x, c) -> alternate
1277 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1278 SDOperand Op = BuildUDIV(N);
1279 if (Op.Val) return Op;
1283 if (N0.getOpcode() == ISD::UNDEF)
1284 return DAG.getConstant(0, VT);
1285 // X / undef -> undef
1286 if (N1.getOpcode() == ISD::UNDEF)
1292 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1293 SDOperand N0 = N->getOperand(0);
1294 SDOperand N1 = N->getOperand(1);
1295 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1296 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1297 MVT::ValueType VT = N->getValueType(0);
1299 // fold (srem c1, c2) -> c1%c2
1300 if (N0C && N1C && !N1C->isNullValue())
1301 return DAG.getNode(ISD::SREM, VT, N0, N1);
1302 // If we know the sign bits of both operands are zero, strength reduce to a
1303 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1304 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1305 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1306 DAG.MaskedValueIsZero(N0, SignBit))
1307 return DAG.getNode(ISD::UREM, VT, N0, N1);
1309 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1310 // the remainder operation.
1311 if (N1C && !N1C->isNullValue()) {
1312 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1313 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1314 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1315 AddToWorkList(Div.Val);
1316 AddToWorkList(Mul.Val);
1321 if (N0.getOpcode() == ISD::UNDEF)
1322 return DAG.getConstant(0, VT);
1323 // X % undef -> undef
1324 if (N1.getOpcode() == ISD::UNDEF)
1330 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1331 SDOperand N0 = N->getOperand(0);
1332 SDOperand N1 = N->getOperand(1);
1333 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1334 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1335 MVT::ValueType VT = N->getValueType(0);
1337 // fold (urem c1, c2) -> c1%c2
1338 if (N0C && N1C && !N1C->isNullValue())
1339 return DAG.getNode(ISD::UREM, VT, N0, N1);
1340 // fold (urem x, pow2) -> (and x, pow2-1)
1341 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1342 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1343 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1344 if (N1.getOpcode() == ISD::SHL) {
1345 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1346 if (isPowerOf2_64(SHC->getValue())) {
1347 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1348 AddToWorkList(Add.Val);
1349 return DAG.getNode(ISD::AND, VT, N0, Add);
1354 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1355 // the remainder operation.
1356 if (N1C && !N1C->isNullValue()) {
1357 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1358 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1359 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1360 AddToWorkList(Div.Val);
1361 AddToWorkList(Mul.Val);
1366 if (N0.getOpcode() == ISD::UNDEF)
1367 return DAG.getConstant(0, VT);
1368 // X % undef -> undef
1369 if (N1.getOpcode() == ISD::UNDEF)
1375 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1376 SDOperand N0 = N->getOperand(0);
1377 SDOperand N1 = N->getOperand(1);
1378 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1379 MVT::ValueType VT = N->getValueType(0);
1381 // fold (mulhs x, 0) -> 0
1382 if (N1C && N1C->isNullValue())
1384 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1385 if (N1C && N1C->getValue() == 1)
1386 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1387 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1388 TLI.getShiftAmountTy()));
1389 // fold (mulhs x, undef) -> 0
1390 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1391 return DAG.getConstant(0, VT);
1396 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1397 SDOperand N0 = N->getOperand(0);
1398 SDOperand N1 = N->getOperand(1);
1399 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1400 MVT::ValueType VT = N->getValueType(0);
1402 // fold (mulhu x, 0) -> 0
1403 if (N1C && N1C->isNullValue())
1405 // fold (mulhu x, 1) -> 0
1406 if (N1C && N1C->getValue() == 1)
1407 return DAG.getConstant(0, N0.getValueType());
1408 // fold (mulhu x, undef) -> 0
1409 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1410 return DAG.getConstant(0, VT);
1415 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1416 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1417 /// that are being performed. Return true if a simplification was made.
1419 bool DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N,
1420 unsigned LoOp, unsigned HiOp) {
1421 // If the high half is not needed, just compute the low half.
1422 bool HiExists = N->hasAnyUseOfValue(1);
1425 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1426 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0),
1427 DAG.getNode(LoOp, N->getValueType(0),
1429 N->getNumOperands()));
1433 // If the low half is not needed, just compute the high half.
1434 bool LoExists = N->hasAnyUseOfValue(0);
1437 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1438 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1),
1439 DAG.getNode(HiOp, N->getValueType(1),
1441 N->getNumOperands()));
1445 // If both halves are used, return as it is.
1446 if (LoExists && HiExists)
1449 // If the two computed results can be simplified separately, separate them.
1450 bool RetVal = false;
1452 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0),
1453 N->op_begin(), N->getNumOperands());
1454 SDOperand LoOpt = combine(Lo.Val);
1455 if (LoOpt.Val && LoOpt != Lo &&
1456 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) {
1458 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), LoOpt);
1463 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1),
1464 N->op_begin(), N->getNumOperands());
1465 SDOperand HiOpt = combine(Hi.Val);
1466 if (HiOpt.Val && HiOpt != Hi &&
1467 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) {
1469 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), HiOpt);
1476 SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1478 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
1484 SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1486 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
1492 SDOperand DAGCombiner::visitSDIVREM(SDNode *N) {
1494 if (SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM))
1500 SDOperand DAGCombiner::visitUDIVREM(SDNode *N) {
1502 if (SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM))
1508 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1509 /// two operands of the same opcode, try to simplify it.
1510 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1511 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1512 MVT::ValueType VT = N0.getValueType();
1513 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1515 // For each of OP in AND/OR/XOR:
1516 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1517 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1518 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1519 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1520 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1521 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1522 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1523 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1524 N0.getOperand(0).getValueType(),
1525 N0.getOperand(0), N1.getOperand(0));
1526 AddToWorkList(ORNode.Val);
1527 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1530 // For each of OP in SHL/SRL/SRA/AND...
1531 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1532 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1533 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1534 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1535 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1536 N0.getOperand(1) == N1.getOperand(1)) {
1537 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1538 N0.getOperand(0).getValueType(),
1539 N0.getOperand(0), N1.getOperand(0));
1540 AddToWorkList(ORNode.Val);
1541 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1547 SDOperand DAGCombiner::visitAND(SDNode *N) {
1548 SDOperand N0 = N->getOperand(0);
1549 SDOperand N1 = N->getOperand(1);
1550 SDOperand LL, LR, RL, RR, CC0, CC1;
1551 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1552 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1553 MVT::ValueType VT = N1.getValueType();
1556 if (MVT::isVector(VT)) {
1557 SDOperand FoldedVOp = SimplifyVBinOp(N);
1558 if (FoldedVOp.Val) return FoldedVOp;
1561 // fold (and x, undef) -> 0
1562 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1563 return DAG.getConstant(0, VT);
1564 // fold (and c1, c2) -> c1&c2
1566 return DAG.getNode(ISD::AND, VT, N0, N1);
1567 // canonicalize constant to RHS
1569 return DAG.getNode(ISD::AND, VT, N1, N0);
1570 // fold (and x, -1) -> x
1571 if (N1C && N1C->isAllOnesValue())
1573 // if (and x, c) is known to be zero, return 0
1574 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1575 return DAG.getConstant(0, VT);
1577 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1580 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1581 if (N1C && N0.getOpcode() == ISD::OR)
1582 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1583 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1585 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1586 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1587 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1588 if (DAG.MaskedValueIsZero(N0.getOperand(0),
1589 ~N1C->getValue() & InMask)) {
1590 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1593 // Replace uses of the AND with uses of the Zero extend node.
1596 // We actually want to replace all uses of the any_extend with the
1597 // zero_extend, to avoid duplicating things. This will later cause this
1598 // AND to be folded.
1599 CombineTo(N0.Val, Zext);
1600 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1603 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1604 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1605 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1606 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1608 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1609 MVT::isInteger(LL.getValueType())) {
1610 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1611 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1612 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1613 AddToWorkList(ORNode.Val);
1614 return DAG.getSetCC(VT, ORNode, LR, Op1);
1616 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1617 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1618 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1619 AddToWorkList(ANDNode.Val);
1620 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1622 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1623 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1624 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1625 AddToWorkList(ORNode.Val);
1626 return DAG.getSetCC(VT, ORNode, LR, Op1);
1629 // canonicalize equivalent to ll == rl
1630 if (LL == RR && LR == RL) {
1631 Op1 = ISD::getSetCCSwappedOperands(Op1);
1634 if (LL == RL && LR == RR) {
1635 bool isInteger = MVT::isInteger(LL.getValueType());
1636 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1637 if (Result != ISD::SETCC_INVALID)
1638 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1642 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1643 if (N0.getOpcode() == N1.getOpcode()) {
1644 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1645 if (Tmp.Val) return Tmp;
1648 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1649 // fold (and (sra)) -> (and (srl)) when possible.
1650 if (!MVT::isVector(VT) &&
1651 SimplifyDemandedBits(SDOperand(N, 0)))
1652 return SDOperand(N, 0);
1653 // fold (zext_inreg (extload x)) -> (zextload x)
1654 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
1655 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1656 MVT::ValueType EVT = LN0->getLoadedVT();
1657 // If we zero all the possible extended bits, then we can turn this into
1658 // a zextload if we are running before legalize or the operation is legal.
1659 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1660 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1661 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1662 LN0->getBasePtr(), LN0->getSrcValue(),
1663 LN0->getSrcValueOffset(), EVT,
1665 LN0->getAlignment());
1667 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1668 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1671 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1672 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
1674 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1675 MVT::ValueType EVT = LN0->getLoadedVT();
1676 // If we zero all the possible extended bits, then we can turn this into
1677 // a zextload if we are running before legalize or the operation is legal.
1678 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1679 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1680 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1681 LN0->getBasePtr(), LN0->getSrcValue(),
1682 LN0->getSrcValueOffset(), EVT,
1684 LN0->getAlignment());
1686 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1687 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1691 // fold (and (load x), 255) -> (zextload x, i8)
1692 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1693 if (N1C && N0.getOpcode() == ISD::LOAD) {
1694 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1695 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1696 LN0->getAddressingMode() == ISD::UNINDEXED &&
1698 MVT::ValueType EVT, LoadedVT;
1699 if (N1C->getValue() == 255)
1701 else if (N1C->getValue() == 65535)
1703 else if (N1C->getValue() == ~0U)
1708 LoadedVT = LN0->getLoadedVT();
1709 if (EVT != MVT::Other && LoadedVT > EVT &&
1710 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1711 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1712 // For big endian targets, we need to add an offset to the pointer to
1713 // load the correct bytes. For little endian systems, we merely need to
1714 // read fewer bytes from the same pointer.
1715 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8;
1716 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8;
1717 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
1718 unsigned Alignment = LN0->getAlignment();
1719 SDOperand NewPtr = LN0->getBasePtr();
1720 if (!TLI.isLittleEndian()) {
1721 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1722 DAG.getConstant(PtrOff, PtrType));
1723 Alignment = MinAlign(Alignment, PtrOff);
1725 AddToWorkList(NewPtr.Val);
1727 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1728 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
1729 LN0->isVolatile(), Alignment);
1731 CombineTo(N0.Val, Load, Load.getValue(1));
1732 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1740 SDOperand DAGCombiner::visitOR(SDNode *N) {
1741 SDOperand N0 = N->getOperand(0);
1742 SDOperand N1 = N->getOperand(1);
1743 SDOperand LL, LR, RL, RR, CC0, CC1;
1744 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1745 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1746 MVT::ValueType VT = N1.getValueType();
1747 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1750 if (MVT::isVector(VT)) {
1751 SDOperand FoldedVOp = SimplifyVBinOp(N);
1752 if (FoldedVOp.Val) return FoldedVOp;
1755 // fold (or x, undef) -> -1
1756 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1757 return DAG.getConstant(~0ULL, VT);
1758 // fold (or c1, c2) -> c1|c2
1760 return DAG.getNode(ISD::OR, VT, N0, N1);
1761 // canonicalize constant to RHS
1763 return DAG.getNode(ISD::OR, VT, N1, N0);
1764 // fold (or x, 0) -> x
1765 if (N1C && N1C->isNullValue())
1767 // fold (or x, -1) -> -1
1768 if (N1C && N1C->isAllOnesValue())
1770 // fold (or x, c) -> c iff (x & ~c) == 0
1772 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1775 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1778 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1779 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1780 isa<ConstantSDNode>(N0.getOperand(1))) {
1781 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1782 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1784 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1786 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1787 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1788 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1789 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1791 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1792 MVT::isInteger(LL.getValueType())) {
1793 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1794 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1795 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1796 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1797 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1798 AddToWorkList(ORNode.Val);
1799 return DAG.getSetCC(VT, ORNode, LR, Op1);
1801 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1802 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1803 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1804 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1805 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1806 AddToWorkList(ANDNode.Val);
1807 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1810 // canonicalize equivalent to ll == rl
1811 if (LL == RR && LR == RL) {
1812 Op1 = ISD::getSetCCSwappedOperands(Op1);
1815 if (LL == RL && LR == RR) {
1816 bool isInteger = MVT::isInteger(LL.getValueType());
1817 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1818 if (Result != ISD::SETCC_INVALID)
1819 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1823 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1824 if (N0.getOpcode() == N1.getOpcode()) {
1825 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1826 if (Tmp.Val) return Tmp;
1829 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1830 if (N0.getOpcode() == ISD::AND &&
1831 N1.getOpcode() == ISD::AND &&
1832 N0.getOperand(1).getOpcode() == ISD::Constant &&
1833 N1.getOperand(1).getOpcode() == ISD::Constant &&
1834 // Don't increase # computations.
1835 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1836 // We can only do this xform if we know that bits from X that are set in C2
1837 // but not in C1 are already zero. Likewise for Y.
1838 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1839 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1841 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1842 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1843 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1844 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1849 // See if this is some rotate idiom.
1850 if (SDNode *Rot = MatchRotate(N0, N1))
1851 return SDOperand(Rot, 0);
1857 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1858 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1859 if (Op.getOpcode() == ISD::AND) {
1860 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1861 Mask = Op.getOperand(1);
1862 Op = Op.getOperand(0);
1868 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1876 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1877 // idioms for rotate, and if the target supports rotation instructions, generate
1879 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1880 // Must be a legal type. Expanded an promoted things won't work with rotates.
1881 MVT::ValueType VT = LHS.getValueType();
1882 if (!TLI.isTypeLegal(VT)) return 0;
1884 // The target must have at least one rotate flavor.
1885 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1886 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1887 if (!HasROTL && !HasROTR) return 0;
1889 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1890 SDOperand LHSShift; // The shift.
1891 SDOperand LHSMask; // AND value if any.
1892 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1893 return 0; // Not part of a rotate.
1895 SDOperand RHSShift; // The shift.
1896 SDOperand RHSMask; // AND value if any.
1897 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1898 return 0; // Not part of a rotate.
1900 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1901 return 0; // Not shifting the same value.
1903 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1904 return 0; // Shifts must disagree.
1906 // Canonicalize shl to left side in a shl/srl pair.
1907 if (RHSShift.getOpcode() == ISD::SHL) {
1908 std::swap(LHS, RHS);
1909 std::swap(LHSShift, RHSShift);
1910 std::swap(LHSMask , RHSMask );
1913 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1914 SDOperand LHSShiftArg = LHSShift.getOperand(0);
1915 SDOperand LHSShiftAmt = LHSShift.getOperand(1);
1916 SDOperand RHSShiftAmt = RHSShift.getOperand(1);
1918 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1919 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1920 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
1921 RHSShiftAmt.getOpcode() == ISD::Constant) {
1922 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
1923 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
1924 if ((LShVal + RShVal) != OpSizeInBits)
1929 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
1931 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
1933 // If there is an AND of either shifted operand, apply it to the result.
1934 if (LHSMask.Val || RHSMask.Val) {
1935 uint64_t Mask = MVT::getIntVTBitMask(VT);
1938 uint64_t RHSBits = (1ULL << LShVal)-1;
1939 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1942 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1943 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1946 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1952 // If there is a mask here, and we have a variable shift, we can't be sure
1953 // that we're masking out the right stuff.
1954 if (LHSMask.Val || RHSMask.Val)
1957 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1958 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1959 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
1960 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
1961 if (ConstantSDNode *SUBC =
1962 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
1963 if (SUBC->getValue() == OpSizeInBits)
1965 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1967 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1971 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1972 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1973 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
1974 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
1975 if (ConstantSDNode *SUBC =
1976 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
1977 if (SUBC->getValue() == OpSizeInBits)
1979 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1981 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1985 // Look for sign/zext/any-extended cases:
1986 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1987 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1988 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
1989 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1990 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1991 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
1992 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
1993 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
1994 if (RExtOp0.getOpcode() == ISD::SUB &&
1995 RExtOp0.getOperand(1) == LExtOp0) {
1996 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1998 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1999 // (rotl x, (sub 32, y))
2000 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2001 if (SUBC->getValue() == OpSizeInBits) {
2003 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2005 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
2008 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2009 RExtOp0 == LExtOp0.getOperand(1)) {
2010 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2012 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2013 // (rotr x, (sub 32, y))
2014 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2015 if (SUBC->getValue() == OpSizeInBits) {
2017 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
2019 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2029 SDOperand DAGCombiner::visitXOR(SDNode *N) {
2030 SDOperand N0 = N->getOperand(0);
2031 SDOperand N1 = N->getOperand(1);
2032 SDOperand LHS, RHS, CC;
2033 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2034 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2035 MVT::ValueType VT = N0.getValueType();
2038 if (MVT::isVector(VT)) {
2039 SDOperand FoldedVOp = SimplifyVBinOp(N);
2040 if (FoldedVOp.Val) return FoldedVOp;
2043 // fold (xor x, undef) -> undef
2044 if (N0.getOpcode() == ISD::UNDEF)
2046 if (N1.getOpcode() == ISD::UNDEF)
2048 // fold (xor c1, c2) -> c1^c2
2050 return DAG.getNode(ISD::XOR, VT, N0, N1);
2051 // canonicalize constant to RHS
2053 return DAG.getNode(ISD::XOR, VT, N1, N0);
2054 // fold (xor x, 0) -> x
2055 if (N1C && N1C->isNullValue())
2058 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
2061 // fold !(x cc y) -> (x !cc y)
2062 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2063 bool isInt = MVT::isInteger(LHS.getValueType());
2064 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2066 if (N0.getOpcode() == ISD::SETCC)
2067 return DAG.getSetCC(VT, LHS, RHS, NotCC);
2068 if (N0.getOpcode() == ISD::SELECT_CC)
2069 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
2070 assert(0 && "Unhandled SetCC Equivalent!");
2073 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2074 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2075 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2076 SDOperand V = N0.getOperand(0);
2077 V = DAG.getNode(ISD::XOR, V.getValueType(), V,
2078 DAG.getConstant(1, V.getValueType()));
2079 AddToWorkList(V.Val);
2080 return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
2083 // fold !(x or y) -> (!x and !y) iff x or y are setcc
2084 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
2085 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2086 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2087 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2088 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2089 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2090 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2091 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2092 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2095 // fold !(x or y) -> (!x and !y) iff x or y are constants
2096 if (N1C && N1C->isAllOnesValue() &&
2097 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2098 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2099 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2100 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2101 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2102 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2103 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2104 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2107 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
2108 if (N1C && N0.getOpcode() == ISD::XOR) {
2109 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2110 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2112 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
2113 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
2115 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
2116 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
2118 // fold (xor x, x) -> 0
2120 if (!MVT::isVector(VT)) {
2121 return DAG.getConstant(0, VT);
2122 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
2123 // Produce a vector of zeros.
2124 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
2125 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
2126 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2130 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2131 if (N0.getOpcode() == N1.getOpcode()) {
2132 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2133 if (Tmp.Val) return Tmp;
2136 // Simplify the expression using non-local knowledge.
2137 if (!MVT::isVector(VT) &&
2138 SimplifyDemandedBits(SDOperand(N, 0)))
2139 return SDOperand(N, 0);
2144 SDOperand DAGCombiner::visitSHL(SDNode *N) {
2145 SDOperand N0 = N->getOperand(0);
2146 SDOperand N1 = N->getOperand(1);
2147 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2148 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2149 MVT::ValueType VT = N0.getValueType();
2150 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2152 // fold (shl c1, c2) -> c1<<c2
2154 return DAG.getNode(ISD::SHL, VT, N0, N1);
2155 // fold (shl 0, x) -> 0
2156 if (N0C && N0C->isNullValue())
2158 // fold (shl x, c >= size(x)) -> undef
2159 if (N1C && N1C->getValue() >= OpSizeInBits)
2160 return DAG.getNode(ISD::UNDEF, VT);
2161 // fold (shl x, 0) -> x
2162 if (N1C && N1C->isNullValue())
2164 // if (shl x, c) is known to be zero, return 0
2165 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
2166 return DAG.getConstant(0, VT);
2167 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2168 return SDOperand(N, 0);
2169 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
2170 if (N1C && N0.getOpcode() == ISD::SHL &&
2171 N0.getOperand(1).getOpcode() == ISD::Constant) {
2172 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2173 uint64_t c2 = N1C->getValue();
2174 if (c1 + c2 > OpSizeInBits)
2175 return DAG.getConstant(0, VT);
2176 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
2177 DAG.getConstant(c1 + c2, N1.getValueType()));
2179 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
2180 // (srl (and x, -1 << c1), c1-c2)
2181 if (N1C && N0.getOpcode() == ISD::SRL &&
2182 N0.getOperand(1).getOpcode() == ISD::Constant) {
2183 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2184 uint64_t c2 = N1C->getValue();
2185 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2186 DAG.getConstant(~0ULL << c1, VT));
2188 return DAG.getNode(ISD::SHL, VT, Mask,
2189 DAG.getConstant(c2-c1, N1.getValueType()));
2191 return DAG.getNode(ISD::SRL, VT, Mask,
2192 DAG.getConstant(c1-c2, N1.getValueType()));
2194 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
2195 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2196 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2197 DAG.getConstant(~0ULL << N1C->getValue(), VT));
2201 SDOperand DAGCombiner::visitSRA(SDNode *N) {
2202 SDOperand N0 = N->getOperand(0);
2203 SDOperand N1 = N->getOperand(1);
2204 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2205 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2206 MVT::ValueType VT = N0.getValueType();
2208 // fold (sra c1, c2) -> c1>>c2
2210 return DAG.getNode(ISD::SRA, VT, N0, N1);
2211 // fold (sra 0, x) -> 0
2212 if (N0C && N0C->isNullValue())
2214 // fold (sra -1, x) -> -1
2215 if (N0C && N0C->isAllOnesValue())
2217 // fold (sra x, c >= size(x)) -> undef
2218 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
2219 return DAG.getNode(ISD::UNDEF, VT);
2220 // fold (sra x, 0) -> x
2221 if (N1C && N1C->isNullValue())
2223 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2225 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2226 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
2229 default: EVT = MVT::Other; break;
2230 case 1: EVT = MVT::i1; break;
2231 case 8: EVT = MVT::i8; break;
2232 case 16: EVT = MVT::i16; break;
2233 case 32: EVT = MVT::i32; break;
2235 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
2236 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
2237 DAG.getValueType(EVT));
2240 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
2241 if (N1C && N0.getOpcode() == ISD::SRA) {
2242 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2243 unsigned Sum = N1C->getValue() + C1->getValue();
2244 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
2245 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
2246 DAG.getConstant(Sum, N1C->getValueType(0)));
2250 // Simplify, based on bits shifted out of the LHS.
2251 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2252 return SDOperand(N, 0);
2255 // If the sign bit is known to be zero, switch this to a SRL.
2256 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
2257 return DAG.getNode(ISD::SRL, VT, N0, N1);
2261 SDOperand DAGCombiner::visitSRL(SDNode *N) {
2262 SDOperand N0 = N->getOperand(0);
2263 SDOperand N1 = N->getOperand(1);
2264 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2265 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2266 MVT::ValueType VT = N0.getValueType();
2267 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2269 // fold (srl c1, c2) -> c1 >>u c2
2271 return DAG.getNode(ISD::SRL, VT, N0, N1);
2272 // fold (srl 0, x) -> 0
2273 if (N0C && N0C->isNullValue())
2275 // fold (srl x, c >= size(x)) -> undef
2276 if (N1C && N1C->getValue() >= OpSizeInBits)
2277 return DAG.getNode(ISD::UNDEF, VT);
2278 // fold (srl x, 0) -> x
2279 if (N1C && N1C->isNullValue())
2281 // if (srl x, c) is known to be zero, return 0
2282 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
2283 return DAG.getConstant(0, VT);
2285 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
2286 if (N1C && N0.getOpcode() == ISD::SRL &&
2287 N0.getOperand(1).getOpcode() == ISD::Constant) {
2288 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2289 uint64_t c2 = N1C->getValue();
2290 if (c1 + c2 > OpSizeInBits)
2291 return DAG.getConstant(0, VT);
2292 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
2293 DAG.getConstant(c1 + c2, N1.getValueType()));
2296 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2297 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2298 // Shifting in all undef bits?
2299 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
2300 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
2301 return DAG.getNode(ISD::UNDEF, VT);
2303 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
2304 AddToWorkList(SmallShift.Val);
2305 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
2308 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2309 // bit, which is unmodified by sra.
2310 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
2311 if (N0.getOpcode() == ISD::SRA)
2312 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
2315 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2316 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2317 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
2318 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
2319 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2321 // If any of the input bits are KnownOne, then the input couldn't be all
2322 // zeros, thus the result of the srl will always be zero.
2323 if (KnownOne) return DAG.getConstant(0, VT);
2325 // If all of the bits input the to ctlz node are known to be zero, then
2326 // the result of the ctlz is "32" and the result of the shift is one.
2327 uint64_t UnknownBits = ~KnownZero & Mask;
2328 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2330 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2331 if ((UnknownBits & (UnknownBits-1)) == 0) {
2332 // Okay, we know that only that the single bit specified by UnknownBits
2333 // could be set on input to the CTLZ node. If this bit is set, the SRL
2334 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2335 // to an SRL,XOR pair, which is likely to simplify more.
2336 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
2337 SDOperand Op = N0.getOperand(0);
2339 Op = DAG.getNode(ISD::SRL, VT, Op,
2340 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
2341 AddToWorkList(Op.Val);
2343 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
2347 // fold operands of srl based on knowledge that the low bits are not
2349 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2350 return SDOperand(N, 0);
2355 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
2356 SDOperand N0 = N->getOperand(0);
2357 MVT::ValueType VT = N->getValueType(0);
2359 // fold (ctlz c1) -> c2
2360 if (isa<ConstantSDNode>(N0))
2361 return DAG.getNode(ISD::CTLZ, VT, N0);
2365 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
2366 SDOperand N0 = N->getOperand(0);
2367 MVT::ValueType VT = N->getValueType(0);
2369 // fold (cttz c1) -> c2
2370 if (isa<ConstantSDNode>(N0))
2371 return DAG.getNode(ISD::CTTZ, VT, N0);
2375 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
2376 SDOperand N0 = N->getOperand(0);
2377 MVT::ValueType VT = N->getValueType(0);
2379 // fold (ctpop c1) -> c2
2380 if (isa<ConstantSDNode>(N0))
2381 return DAG.getNode(ISD::CTPOP, VT, N0);
2385 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
2386 SDOperand N0 = N->getOperand(0);
2387 SDOperand N1 = N->getOperand(1);
2388 SDOperand N2 = N->getOperand(2);
2389 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2390 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2391 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2392 MVT::ValueType VT = N->getValueType(0);
2393 MVT::ValueType VT0 = N0.getValueType();
2395 // fold select C, X, X -> X
2398 // fold select true, X, Y -> X
2399 if (N0C && !N0C->isNullValue())
2401 // fold select false, X, Y -> Y
2402 if (N0C && N0C->isNullValue())
2404 // fold select C, 1, X -> C | X
2405 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
2406 return DAG.getNode(ISD::OR, VT, N0, N2);
2407 // fold select C, 0, 1 -> ~C
2408 if (MVT::isInteger(VT) && MVT::isInteger(VT0) &&
2409 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) {
2410 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
2413 AddToWorkList(XORNode.Val);
2414 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0))
2415 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
2416 return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
2418 // fold select C, 0, X -> ~C & X
2419 if (VT == VT0 && N1C && N1C->isNullValue()) {
2420 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2421 AddToWorkList(XORNode.Val);
2422 return DAG.getNode(ISD::AND, VT, XORNode, N2);
2424 // fold select C, X, 1 -> ~C | X
2425 if (VT == VT0 && N2C && N2C->getValue() == 1) {
2426 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2427 AddToWorkList(XORNode.Val);
2428 return DAG.getNode(ISD::OR, VT, XORNode, N1);
2430 // fold select C, X, 0 -> C & X
2431 // FIXME: this should check for C type == X type, not i1?
2432 if (MVT::i1 == VT && N2C && N2C->isNullValue())
2433 return DAG.getNode(ISD::AND, VT, N0, N1);
2434 // fold X ? X : Y --> X ? 1 : Y --> X | Y
2435 if (MVT::i1 == VT && N0 == N1)
2436 return DAG.getNode(ISD::OR, VT, N0, N2);
2437 // fold X ? Y : X --> X ? Y : 0 --> X & Y
2438 if (MVT::i1 == VT && N0 == N2)
2439 return DAG.getNode(ISD::AND, VT, N0, N1);
2441 // If we can fold this based on the true/false value, do so.
2442 if (SimplifySelectOps(N, N1, N2))
2443 return SDOperand(N, 0); // Don't revisit N.
2445 // fold selects based on a setcc into other things, such as min/max/abs
2446 if (N0.getOpcode() == ISD::SETCC)
2448 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2449 // having to say they don't support SELECT_CC on every type the DAG knows
2450 // about, since there is no way to mark an opcode illegal at all value types
2451 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
2452 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
2453 N1, N2, N0.getOperand(2));
2455 return SimplifySelect(N0, N1, N2);
2459 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
2460 SDOperand N0 = N->getOperand(0);
2461 SDOperand N1 = N->getOperand(1);
2462 SDOperand N2 = N->getOperand(2);
2463 SDOperand N3 = N->getOperand(3);
2464 SDOperand N4 = N->getOperand(4);
2465 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2467 // fold select_cc lhs, rhs, x, x, cc -> x
2471 // Determine if the condition we're dealing with is constant
2472 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2473 if (SCC.Val) AddToWorkList(SCC.Val);
2475 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
2476 if (SCCC->getValue())
2477 return N2; // cond always true -> true val
2479 return N3; // cond always false -> false val
2482 // Fold to a simpler select_cc
2483 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2484 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
2485 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2488 // If we can fold this based on the true/false value, do so.
2489 if (SimplifySelectOps(N, N2, N3))
2490 return SDOperand(N, 0); // Don't revisit N.
2492 // fold select_cc into other things, such as min/max/abs
2493 return SimplifySelectCC(N0, N1, N2, N3, CC);
2496 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
2497 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2498 cast<CondCodeSDNode>(N->getOperand(2))->get());
2501 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
2502 // "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))"
2503 // transformation. Returns true if extension are possible and the above
2504 // mentioned transformation is profitable.
2505 static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0,
2507 SmallVector<SDNode*, 4> &ExtendNodes,
2508 TargetLowering &TLI) {
2509 bool HasCopyToRegUses = false;
2510 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
2511 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end();
2516 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
2517 if (User->getOpcode() == ISD::SETCC) {
2518 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
2519 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
2520 // Sign bits will be lost after a zext.
2523 for (unsigned i = 0; i != 2; ++i) {
2524 SDOperand UseOp = User->getOperand(i);
2527 if (!isa<ConstantSDNode>(UseOp))
2532 ExtendNodes.push_back(User);
2534 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2535 SDOperand UseOp = User->getOperand(i);
2537 // If truncate from extended type to original load type is free
2538 // on this target, then it's ok to extend a CopyToReg.
2539 if (isTruncFree && User->getOpcode() == ISD::CopyToReg)
2540 HasCopyToRegUses = true;
2548 if (HasCopyToRegUses) {
2549 bool BothLiveOut = false;
2550 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
2553 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2554 SDOperand UseOp = User->getOperand(i);
2555 if (UseOp.Val == N && UseOp.ResNo == 0) {
2562 // Both unextended and extended values are live out. There had better be
2563 // good a reason for the transformation.
2564 return ExtendNodes.size();
2569 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2570 SDOperand N0 = N->getOperand(0);
2571 MVT::ValueType VT = N->getValueType(0);
2573 // fold (sext c1) -> c1
2574 if (isa<ConstantSDNode>(N0))
2575 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2577 // fold (sext (sext x)) -> (sext x)
2578 // fold (sext (aext x)) -> (sext x)
2579 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2580 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2582 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2583 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2584 if (N0.getOpcode() == ISD::TRUNCATE) {
2585 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2586 if (NarrowLoad.Val) {
2587 if (NarrowLoad.Val != N0.Val)
2588 CombineTo(N0.Val, NarrowLoad);
2589 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
2593 // See if the value being truncated is already sign extended. If so, just
2594 // eliminate the trunc/sext pair.
2595 if (N0.getOpcode() == ISD::TRUNCATE) {
2596 SDOperand Op = N0.getOperand(0);
2597 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2598 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2599 unsigned DestBits = MVT::getSizeInBits(VT);
2600 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2602 if (OpBits == DestBits) {
2603 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2604 // bits, it is already ready.
2605 if (NumSignBits > DestBits-MidBits)
2607 } else if (OpBits < DestBits) {
2608 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2609 // bits, just sext from i32.
2610 if (NumSignBits > OpBits-MidBits)
2611 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2613 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2614 // bits, just truncate to i32.
2615 if (NumSignBits > OpBits-MidBits)
2616 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2619 // fold (sext (truncate x)) -> (sextinreg x).
2620 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2621 N0.getValueType())) {
2622 if (Op.getValueType() < VT)
2623 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2624 else if (Op.getValueType() > VT)
2625 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2626 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2627 DAG.getValueType(N0.getValueType()));
2631 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2632 if (ISD::isNON_EXTLoad(N0.Val) &&
2633 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2634 bool DoXform = true;
2635 SmallVector<SDNode*, 4> SetCCs;
2636 if (!N0.hasOneUse())
2637 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
2639 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2640 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2641 LN0->getBasePtr(), LN0->getSrcValue(),
2642 LN0->getSrcValueOffset(),
2645 LN0->getAlignment());
2646 CombineTo(N, ExtLoad);
2647 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
2648 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
2649 // Extend SetCC uses if necessary.
2650 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
2651 SDNode *SetCC = SetCCs[i];
2652 SmallVector<SDOperand, 4> Ops;
2653 for (unsigned j = 0; j != 2; ++j) {
2654 SDOperand SOp = SetCC->getOperand(j);
2656 Ops.push_back(ExtLoad);
2658 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp));
2660 Ops.push_back(SetCC->getOperand(2));
2661 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
2662 &Ops[0], Ops.size()));
2664 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2668 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2669 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2670 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2671 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2672 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2673 MVT::ValueType EVT = LN0->getLoadedVT();
2674 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2675 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2676 LN0->getBasePtr(), LN0->getSrcValue(),
2677 LN0->getSrcValueOffset(), EVT,
2679 LN0->getAlignment());
2680 CombineTo(N, ExtLoad);
2681 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2682 ExtLoad.getValue(1));
2683 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2687 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
2688 if (N0.getOpcode() == ISD::SETCC) {
2690 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2691 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
2692 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2693 if (SCC.Val) return SCC;
2699 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2700 SDOperand N0 = N->getOperand(0);
2701 MVT::ValueType VT = N->getValueType(0);
2703 // fold (zext c1) -> c1
2704 if (isa<ConstantSDNode>(N0))
2705 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2706 // fold (zext (zext x)) -> (zext x)
2707 // fold (zext (aext x)) -> (zext x)
2708 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2709 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2711 // fold (zext (truncate (load x))) -> (zext (smaller load x))
2712 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
2713 if (N0.getOpcode() == ISD::TRUNCATE) {
2714 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2715 if (NarrowLoad.Val) {
2716 if (NarrowLoad.Val != N0.Val)
2717 CombineTo(N0.Val, NarrowLoad);
2718 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
2722 // fold (zext (truncate x)) -> (and x, mask)
2723 if (N0.getOpcode() == ISD::TRUNCATE &&
2724 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2725 SDOperand Op = N0.getOperand(0);
2726 if (Op.getValueType() < VT) {
2727 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2728 } else if (Op.getValueType() > VT) {
2729 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2731 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2734 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2735 if (N0.getOpcode() == ISD::AND &&
2736 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2737 N0.getOperand(1).getOpcode() == ISD::Constant) {
2738 SDOperand X = N0.getOperand(0).getOperand(0);
2739 if (X.getValueType() < VT) {
2740 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2741 } else if (X.getValueType() > VT) {
2742 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2744 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2745 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2748 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2749 if (ISD::isNON_EXTLoad(N0.Val) &&
2750 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2751 bool DoXform = true;
2752 SmallVector<SDNode*, 4> SetCCs;
2753 if (!N0.hasOneUse())
2754 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
2756 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2757 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2758 LN0->getBasePtr(), LN0->getSrcValue(),
2759 LN0->getSrcValueOffset(),
2762 LN0->getAlignment());
2763 CombineTo(N, ExtLoad);
2764 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
2765 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
2766 // Extend SetCC uses if necessary.
2767 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
2768 SDNode *SetCC = SetCCs[i];
2769 SmallVector<SDOperand, 4> Ops;
2770 for (unsigned j = 0; j != 2; ++j) {
2771 SDOperand SOp = SetCC->getOperand(j);
2773 Ops.push_back(ExtLoad);
2775 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp));
2777 Ops.push_back(SetCC->getOperand(2));
2778 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
2779 &Ops[0], Ops.size()));
2781 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2785 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2786 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2787 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2788 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2789 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2790 MVT::ValueType EVT = LN0->getLoadedVT();
2791 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2792 LN0->getBasePtr(), LN0->getSrcValue(),
2793 LN0->getSrcValueOffset(), EVT,
2795 LN0->getAlignment());
2796 CombineTo(N, ExtLoad);
2797 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2798 ExtLoad.getValue(1));
2799 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2802 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2803 if (N0.getOpcode() == ISD::SETCC) {
2805 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2806 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2807 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2808 if (SCC.Val) return SCC;
2814 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2815 SDOperand N0 = N->getOperand(0);
2816 MVT::ValueType VT = N->getValueType(0);
2818 // fold (aext c1) -> c1
2819 if (isa<ConstantSDNode>(N0))
2820 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2821 // fold (aext (aext x)) -> (aext x)
2822 // fold (aext (zext x)) -> (zext x)
2823 // fold (aext (sext x)) -> (sext x)
2824 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2825 N0.getOpcode() == ISD::ZERO_EXTEND ||
2826 N0.getOpcode() == ISD::SIGN_EXTEND)
2827 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2829 // fold (aext (truncate (load x))) -> (aext (smaller load x))
2830 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
2831 if (N0.getOpcode() == ISD::TRUNCATE) {
2832 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2833 if (NarrowLoad.Val) {
2834 if (NarrowLoad.Val != N0.Val)
2835 CombineTo(N0.Val, NarrowLoad);
2836 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
2840 // fold (aext (truncate x))
2841 if (N0.getOpcode() == ISD::TRUNCATE) {
2842 SDOperand TruncOp = N0.getOperand(0);
2843 if (TruncOp.getValueType() == VT)
2844 return TruncOp; // x iff x size == zext size.
2845 if (TruncOp.getValueType() > VT)
2846 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2847 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2850 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2851 if (N0.getOpcode() == ISD::AND &&
2852 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2853 N0.getOperand(1).getOpcode() == ISD::Constant) {
2854 SDOperand X = N0.getOperand(0).getOperand(0);
2855 if (X.getValueType() < VT) {
2856 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2857 } else if (X.getValueType() > VT) {
2858 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2860 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2861 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2864 // fold (aext (load x)) -> (aext (truncate (extload x)))
2865 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2866 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2867 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2868 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2869 LN0->getBasePtr(), LN0->getSrcValue(),
2870 LN0->getSrcValueOffset(),
2873 LN0->getAlignment());
2874 CombineTo(N, ExtLoad);
2875 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2876 ExtLoad.getValue(1));
2877 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2880 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2881 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2882 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2883 if (N0.getOpcode() == ISD::LOAD &&
2884 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2886 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2887 MVT::ValueType EVT = LN0->getLoadedVT();
2888 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2889 LN0->getChain(), LN0->getBasePtr(),
2891 LN0->getSrcValueOffset(), EVT,
2893 LN0->getAlignment());
2894 CombineTo(N, ExtLoad);
2895 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2896 ExtLoad.getValue(1));
2897 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2900 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2901 if (N0.getOpcode() == ISD::SETCC) {
2903 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2904 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2905 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2913 /// GetDemandedBits - See if the specified operand can be simplified with the
2914 /// knowledge that only the bits specified by Mask are used. If so, return the
2915 /// simpler operand, otherwise return a null SDOperand.
2916 SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) {
2917 switch (V.getOpcode()) {
2921 // If the LHS or RHS don't contribute bits to the or, drop them.
2922 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
2923 return V.getOperand(1);
2924 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
2925 return V.getOperand(0);
2928 // Only look at single-use SRLs.
2929 if (!V.Val->hasOneUse())
2931 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
2932 // See if we can recursively simplify the LHS.
2933 unsigned Amt = RHSC->getValue();
2934 Mask = (Mask << Amt) & MVT::getIntVTBitMask(V.getValueType());
2935 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), Mask);
2936 if (SimplifyLHS.Val) {
2937 return DAG.getNode(ISD::SRL, V.getValueType(),
2938 SimplifyLHS, V.getOperand(1));
2945 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
2946 /// bits and then truncated to a narrower type and where N is a multiple
2947 /// of number of bits of the narrower type, transform it to a narrower load
2948 /// from address + N / num of bits of new type. If the result is to be
2949 /// extended, also fold the extension to form a extending load.
2950 SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
2951 unsigned Opc = N->getOpcode();
2952 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2953 SDOperand N0 = N->getOperand(0);
2954 MVT::ValueType VT = N->getValueType(0);
2955 MVT::ValueType EVT = N->getValueType(0);
2957 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
2959 if (Opc == ISD::SIGN_EXTEND_INREG) {
2960 ExtType = ISD::SEXTLOAD;
2961 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2962 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
2966 unsigned EVTBits = MVT::getSizeInBits(EVT);
2968 bool CombineSRL = false;
2969 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
2970 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2971 ShAmt = N01->getValue();
2972 // Is the shift amount a multiple of size of VT?
2973 if ((ShAmt & (EVTBits-1)) == 0) {
2974 N0 = N0.getOperand(0);
2975 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
2982 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2983 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
2984 // zero extended form: by shrinking the load, we lose track of the fact
2985 // that it is already zero extended.
2986 // FIXME: This should be reevaluated.
2988 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
2989 "Cannot truncate to larger type!");
2990 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2991 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2992 // For big endian targets, we need to adjust the offset to the pointer to
2993 // load the correct bytes.
2994 if (!TLI.isLittleEndian()) {
2995 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType());
2996 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT);
2997 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
2999 uint64_t PtrOff = ShAmt / 8;
3000 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3001 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
3002 DAG.getConstant(PtrOff, PtrType));
3003 AddToWorkList(NewPtr.Val);
3004 SDOperand Load = (ExtType == ISD::NON_EXTLOAD)
3005 ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
3006 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3007 LN0->isVolatile(), NewAlign)
3008 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
3009 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
3010 LN0->isVolatile(), NewAlign);
3013 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
3014 CombineTo(N->getOperand(0).Val, Load);
3016 CombineTo(N0.Val, Load, Load.getValue(1));
3018 if (Opc == ISD::SIGN_EXTEND_INREG)
3019 return DAG.getNode(Opc, VT, Load, N->getOperand(1));
3021 return DAG.getNode(Opc, VT, Load);
3023 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3030 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3031 SDOperand N0 = N->getOperand(0);
3032 SDOperand N1 = N->getOperand(1);
3033 MVT::ValueType VT = N->getValueType(0);
3034 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
3035 unsigned EVTBits = MVT::getSizeInBits(EVT);
3037 // fold (sext_in_reg c1) -> c1
3038 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3039 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
3041 // If the input is already sign extended, just drop the extension.
3042 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
3045 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3046 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3047 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
3048 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
3051 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3052 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
3053 return DAG.getZeroExtendInReg(N0, EVT);
3055 // fold operands of sext_in_reg based on knowledge that the top bits are not
3057 if (SimplifyDemandedBits(SDOperand(N, 0)))
3058 return SDOperand(N, 0);
3060 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3061 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3062 SDOperand NarrowLoad = ReduceLoadWidth(N);
3066 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
3067 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
3068 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3069 if (N0.getOpcode() == ISD::SRL) {
3070 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3071 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
3072 // We can turn this into an SRA iff the input to the SRL is already sign
3074 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3075 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
3076 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
3080 // fold (sext_inreg (extload x)) -> (sextload x)
3081 if (ISD::isEXTLoad(N0.Val) &&
3082 ISD::isUNINDEXEDLoad(N0.Val) &&
3083 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
3084 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
3085 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3086 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
3087 LN0->getBasePtr(), LN0->getSrcValue(),
3088 LN0->getSrcValueOffset(), EVT,
3090 LN0->getAlignment());
3091 CombineTo(N, ExtLoad);
3092 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
3093 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3095 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3096 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
3098 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
3099 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
3100 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3101 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
3102 LN0->getBasePtr(), LN0->getSrcValue(),
3103 LN0->getSrcValueOffset(), EVT,
3105 LN0->getAlignment());
3106 CombineTo(N, ExtLoad);
3107 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
3108 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3113 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
3114 SDOperand N0 = N->getOperand(0);
3115 MVT::ValueType VT = N->getValueType(0);
3118 if (N0.getValueType() == N->getValueType(0))
3120 // fold (truncate c1) -> c1
3121 if (isa<ConstantSDNode>(N0))
3122 return DAG.getNode(ISD::TRUNCATE, VT, N0);
3123 // fold (truncate (truncate x)) -> (truncate x)
3124 if (N0.getOpcode() == ISD::TRUNCATE)
3125 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3126 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3127 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
3128 N0.getOpcode() == ISD::ANY_EXTEND) {
3129 if (N0.getOperand(0).getValueType() < VT)
3130 // if the source is smaller than the dest, we still need an extend
3131 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
3132 else if (N0.getOperand(0).getValueType() > VT)
3133 // if the source is larger than the dest, than we just need the truncate
3134 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3136 // if the source and dest are the same type, we can drop both the extend
3138 return N0.getOperand(0);
3141 // See if we can simplify the input to this truncate through knowledge that
3142 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3144 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT));
3146 return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
3148 // fold (truncate (load x)) -> (smaller load x)
3149 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3150 return ReduceLoadWidth(N);
3153 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3154 SDOperand N0 = N->getOperand(0);
3155 MVT::ValueType VT = N->getValueType(0);
3157 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3158 // Only do this before legalize, since afterward the target may be depending
3159 // on the bitconvert.
3160 // First check to see if this is all constant.
3161 if (!AfterLegalize &&
3162 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
3163 MVT::isVector(VT)) {
3164 bool isSimple = true;
3165 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3166 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3167 N0.getOperand(i).getOpcode() != ISD::Constant &&
3168 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3173 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0));
3174 assert(!MVT::isVector(DestEltVT) &&
3175 "Element type of vector ValueType must not be vector!");
3177 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
3181 // If the input is a constant, let getNode() fold it.
3182 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3183 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3184 if (Res.Val != N) return Res;
3187 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
3188 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3190 // fold (conv (load x)) -> (load (conv*)x)
3191 // If the resultant load doesn't need a higher alignment than the original!
3192 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() &&
3193 TLI.isOperationLegal(ISD::LOAD, VT)) {
3194 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3195 unsigned Align = TLI.getTargetMachine().getTargetData()->
3196 getABITypeAlignment(MVT::getTypeForValueType(VT));
3197 unsigned OrigAlign = LN0->getAlignment();
3198 if (Align <= OrigAlign) {
3199 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
3200 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3201 LN0->isVolatile(), Align);
3203 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
3212 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3213 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3214 /// destination element value type.
3215 SDOperand DAGCombiner::
3216 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
3217 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
3219 // If this is already the right type, we're done.
3220 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
3222 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
3223 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
3225 // If this is a conversion of N elements of one type to N elements of another
3226 // type, convert each element. This handles FP<->INT cases.
3227 if (SrcBitSize == DstBitSize) {
3228 SmallVector<SDOperand, 8> Ops;
3229 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3230 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
3231 AddToWorkList(Ops.back().Val);
3234 MVT::getVectorType(DstEltVT,
3235 MVT::getVectorNumElements(BV->getValueType(0)));
3236 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3239 // Otherwise, we're growing or shrinking the elements. To avoid having to
3240 // handle annoying details of growing/shrinking FP values, we convert them to
3242 if (MVT::isFloatingPoint(SrcEltVT)) {
3243 // Convert the input float vector to a int vector where the elements are the
3245 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3246 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
3247 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
3251 // Now we know the input is an integer vector. If the output is a FP type,
3252 // convert to integer first, then to FP of the right size.
3253 if (MVT::isFloatingPoint(DstEltVT)) {
3254 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3255 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
3256 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val;
3258 // Next, convert to FP elements of the same size.
3259 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3262 // Okay, we know the src/dst types are both integers of differing types.
3263 // Handling growing first.
3264 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
3265 if (SrcBitSize < DstBitSize) {
3266 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3268 SmallVector<SDOperand, 8> Ops;
3269 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3270 i += NumInputsPerOutput) {
3271 bool isLE = TLI.isLittleEndian();
3272 uint64_t NewBits = 0;
3273 bool EltIsUndef = true;
3274 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3275 // Shift the previously computed bits over.
3276 NewBits <<= SrcBitSize;
3277 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3278 if (Op.getOpcode() == ISD::UNDEF) continue;
3281 NewBits |= cast<ConstantSDNode>(Op)->getValue();
3285 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3287 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3290 MVT::ValueType VT = MVT::getVectorType(DstEltVT,
3292 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3295 // Finally, this must be the case where we are shrinking elements: each input
3296 // turns into multiple outputs.
3297 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3298 SmallVector<SDOperand, 8> Ops;
3299 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3300 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3301 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3302 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3305 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
3307 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3308 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
3309 OpVal >>= DstBitSize;
3310 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3313 // For big endian targets, swap the order of the pieces of each element.
3314 if (!TLI.isLittleEndian())
3315 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3317 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size());
3318 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3323 SDOperand DAGCombiner::visitFADD(SDNode *N) {
3324 SDOperand N0 = N->getOperand(0);
3325 SDOperand N1 = N->getOperand(1);
3326 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3327 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3328 MVT::ValueType VT = N->getValueType(0);
3331 if (MVT::isVector(VT)) {
3332 SDOperand FoldedVOp = SimplifyVBinOp(N);
3333 if (FoldedVOp.Val) return FoldedVOp;
3336 // fold (fadd c1, c2) -> c1+c2
3337 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3338 return DAG.getNode(ISD::FADD, VT, N0, N1);
3339 // canonicalize constant to RHS
3340 if (N0CFP && !N1CFP)
3341 return DAG.getNode(ISD::FADD, VT, N1, N0);
3342 // fold (A + (-B)) -> A-B
3343 if (isNegatibleForFree(N1) == 2)
3344 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG));
3345 // fold ((-A) + B) -> B-A
3346 if (isNegatibleForFree(N0) == 2)
3347 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG));
3349 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3350 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3351 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3352 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
3353 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
3358 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
3359 SDOperand N0 = N->getOperand(0);
3360 SDOperand N1 = N->getOperand(1);
3361 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3362 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3363 MVT::ValueType VT = N->getValueType(0);
3366 if (MVT::isVector(VT)) {
3367 SDOperand FoldedVOp = SimplifyVBinOp(N);
3368 if (FoldedVOp.Val) return FoldedVOp;
3371 // fold (fsub c1, c2) -> c1-c2
3372 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3373 return DAG.getNode(ISD::FSUB, VT, N0, N1);
3375 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
3376 if (isNegatibleForFree(N1))
3377 return GetNegatedExpression(N1, DAG);
3378 return DAG.getNode(ISD::FNEG, VT, N1);
3380 // fold (A-(-B)) -> A+B
3381 if (isNegatibleForFree(N1))
3382 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG));
3387 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
3388 SDOperand N0 = N->getOperand(0);
3389 SDOperand N1 = N->getOperand(1);
3390 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3391 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3392 MVT::ValueType VT = N->getValueType(0);
3395 if (MVT::isVector(VT)) {
3396 SDOperand FoldedVOp = SimplifyVBinOp(N);
3397 if (FoldedVOp.Val) return FoldedVOp;
3400 // fold (fmul c1, c2) -> c1*c2
3401 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3402 return DAG.getNode(ISD::FMUL, VT, N0, N1);
3403 // canonicalize constant to RHS
3404 if (N0CFP && !N1CFP)
3405 return DAG.getNode(ISD::FMUL, VT, N1, N0);
3406 // fold (fmul X, 2.0) -> (fadd X, X)
3407 if (N1CFP && N1CFP->isExactlyValue(+2.0))
3408 return DAG.getNode(ISD::FADD, VT, N0, N0);
3409 // fold (fmul X, -1.0) -> (fneg X)
3410 if (N1CFP && N1CFP->isExactlyValue(-1.0))
3411 return DAG.getNode(ISD::FNEG, VT, N0);
3414 if (char LHSNeg = isNegatibleForFree(N0)) {
3415 if (char RHSNeg = isNegatibleForFree(N1)) {
3416 // Both can be negated for free, check to see if at least one is cheaper
3418 if (LHSNeg == 2 || RHSNeg == 2)
3419 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG),
3420 GetNegatedExpression(N1, DAG));
3424 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
3425 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
3426 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3427 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
3428 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
3433 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
3434 SDOperand N0 = N->getOperand(0);
3435 SDOperand N1 = N->getOperand(1);
3436 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3437 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3438 MVT::ValueType VT = N->getValueType(0);
3441 if (MVT::isVector(VT)) {
3442 SDOperand FoldedVOp = SimplifyVBinOp(N);
3443 if (FoldedVOp.Val) return FoldedVOp;
3446 // fold (fdiv c1, c2) -> c1/c2
3447 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3448 return DAG.getNode(ISD::FDIV, VT, N0, N1);
3452 if (char LHSNeg = isNegatibleForFree(N0)) {
3453 if (char RHSNeg = isNegatibleForFree(N1)) {
3454 // Both can be negated for free, check to see if at least one is cheaper
3456 if (LHSNeg == 2 || RHSNeg == 2)
3457 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG),
3458 GetNegatedExpression(N1, DAG));
3465 SDOperand DAGCombiner::visitFREM(SDNode *N) {
3466 SDOperand N0 = N->getOperand(0);
3467 SDOperand N1 = N->getOperand(1);
3468 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3469 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3470 MVT::ValueType VT = N->getValueType(0);
3472 // fold (frem c1, c2) -> fmod(c1,c2)
3473 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3474 return DAG.getNode(ISD::FREM, VT, N0, N1);
3479 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
3480 SDOperand N0 = N->getOperand(0);
3481 SDOperand N1 = N->getOperand(1);
3482 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3483 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3484 MVT::ValueType VT = N->getValueType(0);
3486 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
3487 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
3490 const APFloat& V = N1CFP->getValueAPF();
3491 // copysign(x, c1) -> fabs(x) iff ispos(c1)
3492 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
3493 if (!V.isNegative())
3494 return DAG.getNode(ISD::FABS, VT, N0);
3496 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
3499 // copysign(fabs(x), y) -> copysign(x, y)
3500 // copysign(fneg(x), y) -> copysign(x, y)
3501 // copysign(copysign(x,z), y) -> copysign(x, y)
3502 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
3503 N0.getOpcode() == ISD::FCOPYSIGN)
3504 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
3506 // copysign(x, abs(y)) -> abs(x)
3507 if (N1.getOpcode() == ISD::FABS)
3508 return DAG.getNode(ISD::FABS, VT, N0);
3510 // copysign(x, copysign(y,z)) -> copysign(x, z)
3511 if (N1.getOpcode() == ISD::FCOPYSIGN)
3512 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
3514 // copysign(x, fp_extend(y)) -> copysign(x, y)
3515 // copysign(x, fp_round(y)) -> copysign(x, y)
3516 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
3517 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
3524 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
3525 SDOperand N0 = N->getOperand(0);
3526 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3527 MVT::ValueType VT = N->getValueType(0);
3529 // fold (sint_to_fp c1) -> c1fp
3530 if (N0C && N0.getValueType() != MVT::ppcf128)
3531 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
3535 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
3536 SDOperand N0 = N->getOperand(0);
3537 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3538 MVT::ValueType VT = N->getValueType(0);
3540 // fold (uint_to_fp c1) -> c1fp
3541 if (N0C && N0.getValueType() != MVT::ppcf128)
3542 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
3546 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
3547 SDOperand N0 = N->getOperand(0);
3548 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3549 MVT::ValueType VT = N->getValueType(0);
3551 // fold (fp_to_sint c1fp) -> c1
3553 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
3557 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
3558 SDOperand N0 = N->getOperand(0);
3559 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3560 MVT::ValueType VT = N->getValueType(0);
3562 // fold (fp_to_uint c1fp) -> c1
3563 if (N0CFP && VT != MVT::ppcf128)
3564 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
3568 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
3569 SDOperand N0 = N->getOperand(0);
3570 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3571 MVT::ValueType VT = N->getValueType(0);
3573 // fold (fp_round c1fp) -> c1fp
3574 if (N0CFP && N0.getValueType() != MVT::ppcf128)
3575 return DAG.getNode(ISD::FP_ROUND, VT, N0);
3577 // fold (fp_round (fp_extend x)) -> x
3578 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
3579 return N0.getOperand(0);
3581 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
3582 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
3583 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
3584 AddToWorkList(Tmp.Val);
3585 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
3591 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
3592 SDOperand N0 = N->getOperand(0);
3593 MVT::ValueType VT = N->getValueType(0);
3594 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3595 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3597 // fold (fp_round_inreg c1fp) -> c1fp
3599 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT);
3600 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
3605 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
3606 SDOperand N0 = N->getOperand(0);
3607 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3608 MVT::ValueType VT = N->getValueType(0);
3610 // fold (fp_extend c1fp) -> c1fp
3611 if (N0CFP && VT != MVT::ppcf128)
3612 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
3614 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
3615 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3616 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
3617 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3618 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
3619 LN0->getBasePtr(), LN0->getSrcValue(),
3620 LN0->getSrcValueOffset(),
3623 LN0->getAlignment());
3624 CombineTo(N, ExtLoad);
3625 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
3626 ExtLoad.getValue(1));
3627 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3634 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
3635 SDOperand N0 = N->getOperand(0);
3637 if (isNegatibleForFree(N0))
3638 return GetNegatedExpression(N0, DAG);
3643 SDOperand DAGCombiner::visitFABS(SDNode *N) {
3644 SDOperand N0 = N->getOperand(0);
3645 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3646 MVT::ValueType VT = N->getValueType(0);
3648 // fold (fabs c1) -> fabs(c1)
3649 if (N0CFP && VT != MVT::ppcf128)
3650 return DAG.getNode(ISD::FABS, VT, N0);
3651 // fold (fabs (fabs x)) -> (fabs x)
3652 if (N0.getOpcode() == ISD::FABS)
3653 return N->getOperand(0);
3654 // fold (fabs (fneg x)) -> (fabs x)
3655 // fold (fabs (fcopysign x, y)) -> (fabs x)
3656 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
3657 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
3662 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
3663 SDOperand Chain = N->getOperand(0);
3664 SDOperand N1 = N->getOperand(1);
3665 SDOperand N2 = N->getOperand(2);
3666 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3668 // never taken branch, fold to chain
3669 if (N1C && N1C->isNullValue())
3671 // unconditional branch
3672 if (N1C && N1C->getValue() == 1)
3673 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
3674 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
3676 if (N1.getOpcode() == ISD::SETCC &&
3677 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
3678 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
3679 N1.getOperand(0), N1.getOperand(1), N2);
3684 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
3686 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
3687 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
3688 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
3690 // Use SimplifySetCC to simplify SETCC's.
3691 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
3692 if (Simp.Val) AddToWorkList(Simp.Val);
3694 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
3696 // fold br_cc true, dest -> br dest (unconditional branch)
3697 if (SCCC && SCCC->getValue())
3698 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
3700 // fold br_cc false, dest -> unconditional fall through
3701 if (SCCC && SCCC->isNullValue())
3702 return N->getOperand(0);
3704 // fold to a simpler setcc
3705 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
3706 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
3707 Simp.getOperand(2), Simp.getOperand(0),
3708 Simp.getOperand(1), N->getOperand(4));
3713 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
3714 /// pre-indexed load / store when the base pointer is a add or subtract
3715 /// and it has other uses besides the load / store. After the
3716 /// transformation, the new indexed load / store has effectively folded
3717 /// the add / subtract in and all of its other uses are redirected to the
3718 /// new load / store.
3719 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
3726 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3727 if (LD->getAddressingMode() != ISD::UNINDEXED)
3729 VT = LD->getLoadedVT();
3730 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
3731 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
3733 Ptr = LD->getBasePtr();
3734 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3735 if (ST->getAddressingMode() != ISD::UNINDEXED)
3737 VT = ST->getStoredVT();
3738 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
3739 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
3741 Ptr = ST->getBasePtr();
3746 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
3747 // out. There is no reason to make this a preinc/predec.
3748 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
3749 Ptr.Val->hasOneUse())
3752 // Ask the target to do addressing mode selection.
3755 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3756 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
3758 // Don't create a indexed load / store with zero offset.
3759 if (isa<ConstantSDNode>(Offset) &&
3760 cast<ConstantSDNode>(Offset)->getValue() == 0)
3763 // Try turning it into a pre-indexed load / store except when:
3764 // 1) The new base ptr is a frame index.
3765 // 2) If N is a store and the new base ptr is either the same as or is a
3766 // predecessor of the value being stored.
3767 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
3768 // that would create a cycle.
3769 // 4) All uses are load / store ops that use it as old base ptr.
3771 // Check #1. Preinc'ing a frame index would require copying the stack pointer
3772 // (plus the implicit offset) to a register to preinc anyway.
3773 if (isa<FrameIndexSDNode>(BasePtr))
3778 SDOperand Val = cast<StoreSDNode>(N)->getValue();
3779 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val))
3783 // Now check for #3 and #4.
3784 bool RealUse = false;
3785 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3786 E = Ptr.Val->use_end(); I != E; ++I) {
3790 if (Use->isPredecessor(N))
3793 if (!((Use->getOpcode() == ISD::LOAD &&
3794 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
3795 (Use->getOpcode() == ISD::STORE) &&
3796 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
3804 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
3806 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3809 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
3810 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3812 std::vector<SDNode*> NowDead;
3814 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3816 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3819 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3823 // Nodes can end up on the worklist more than once. Make sure we do
3824 // not process a node that has been replaced.
3825 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3826 removeFromWorkList(NowDead[i]);
3827 // Finally, since the node is now dead, remove it from the graph.
3830 // Replace the uses of Ptr with uses of the updated base value.
3831 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
3833 removeFromWorkList(Ptr.Val);
3834 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3835 removeFromWorkList(NowDead[i]);
3836 DAG.DeleteNode(Ptr.Val);
3841 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
3842 /// add / sub of the base pointer node into a post-indexed load / store.
3843 /// The transformation folded the add / subtract into the new indexed
3844 /// load / store effectively and all of its uses are redirected to the
3845 /// new load / store.
3846 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
3853 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3854 if (LD->getAddressingMode() != ISD::UNINDEXED)
3856 VT = LD->getLoadedVT();
3857 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
3858 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
3860 Ptr = LD->getBasePtr();
3861 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3862 if (ST->getAddressingMode() != ISD::UNINDEXED)
3864 VT = ST->getStoredVT();
3865 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
3866 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
3868 Ptr = ST->getBasePtr();
3873 if (Ptr.Val->hasOneUse())
3876 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3877 E = Ptr.Val->use_end(); I != E; ++I) {
3880 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
3885 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3886 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
3888 std::swap(BasePtr, Offset);
3891 // Don't create a indexed load / store with zero offset.
3892 if (isa<ConstantSDNode>(Offset) &&
3893 cast<ConstantSDNode>(Offset)->getValue() == 0)
3896 // Try turning it into a post-indexed load / store except when
3897 // 1) All uses are load / store ops that use it as base ptr.
3898 // 2) Op must be independent of N, i.e. Op is neither a predecessor
3899 // nor a successor of N. Otherwise, if Op is folded that would
3903 bool TryNext = false;
3904 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
3905 EE = BasePtr.Val->use_end(); II != EE; ++II) {
3910 // If all the uses are load / store addresses, then don't do the
3912 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
3913 bool RealUse = false;
3914 for (SDNode::use_iterator III = Use->use_begin(),
3915 EEE = Use->use_end(); III != EEE; ++III) {
3916 SDNode *UseUse = *III;
3917 if (!((UseUse->getOpcode() == ISD::LOAD &&
3918 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
3919 (UseUse->getOpcode() == ISD::STORE) &&
3920 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
3934 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
3935 SDOperand Result = isLoad
3936 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
3937 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3940 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
3941 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3943 std::vector<SDNode*> NowDead;
3945 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3947 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3950 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3954 // Nodes can end up on the worklist more than once. Make sure we do
3955 // not process a node that has been replaced.
3956 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3957 removeFromWorkList(NowDead[i]);
3958 // Finally, since the node is now dead, remove it from the graph.
3961 // Replace the uses of Use with uses of the updated base value.
3962 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
3963 Result.getValue(isLoad ? 1 : 0),
3965 removeFromWorkList(Op);
3966 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3967 removeFromWorkList(NowDead[i]);
3978 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
3979 LoadSDNode *LD = cast<LoadSDNode>(N);
3980 SDOperand Chain = LD->getChain();
3981 SDOperand Ptr = LD->getBasePtr();
3983 // If load is not volatile and there are no uses of the loaded value (and
3984 // the updated indexed value in case of indexed loads), change uses of the
3985 // chain value into uses of the chain input (i.e. delete the dead load).
3986 if (!LD->isVolatile()) {
3987 if (N->getValueType(1) == MVT::Other) {
3989 if (N->hasNUsesOfValue(0, 0))
3990 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
3993 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
3994 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
3995 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0));
3996 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1));
3997 SDOperand To[] = { Undef0, Undef1, Chain };
3998 return CombineTo(N, To, 3);
4003 // If this load is directly stored, replace the load value with the stored
4005 // TODO: Handle store large -> read small portion.
4006 // TODO: Handle TRUNCSTORE/LOADEXT
4007 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4008 if (ISD::isNON_TRUNCStore(Chain.Val)) {
4009 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
4010 if (PrevST->getBasePtr() == Ptr &&
4011 PrevST->getValue().getValueType() == N->getValueType(0))
4012 return CombineTo(N, Chain.getOperand(1), Chain);
4017 // Walk up chain skipping non-aliasing memory nodes.
4018 SDOperand BetterChain = FindBetterChain(N, Chain);
4020 // If there is a better chain.
4021 if (Chain != BetterChain) {
4024 // Replace the chain to void dependency.
4025 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4026 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
4027 LD->getSrcValue(), LD->getSrcValueOffset(),
4028 LD->isVolatile(), LD->getAlignment());
4030 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
4031 LD->getValueType(0),
4032 BetterChain, Ptr, LD->getSrcValue(),
4033 LD->getSrcValueOffset(),
4036 LD->getAlignment());
4039 // Create token factor to keep old chain connected.
4040 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
4041 Chain, ReplLoad.getValue(1));
4043 // Replace uses with load result and token factor. Don't add users
4045 return CombineTo(N, ReplLoad.getValue(0), Token, false);
4049 // Try transforming N to an indexed load.
4050 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4051 return SDOperand(N, 0);
4056 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
4057 StoreSDNode *ST = cast<StoreSDNode>(N);
4058 SDOperand Chain = ST->getChain();
4059 SDOperand Value = ST->getValue();
4060 SDOperand Ptr = ST->getBasePtr();
4062 // If this is a store of a bit convert, store the input value if the
4063 // resultant store does not need a higher alignment than the original.
4064 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
4065 ST->getAddressingMode() == ISD::UNINDEXED) {
4066 unsigned Align = ST->getAlignment();
4067 MVT::ValueType SVT = Value.getOperand(0).getValueType();
4068 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
4069 getABITypeAlignment(MVT::getTypeForValueType(SVT));
4070 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
4071 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
4072 ST->getSrcValueOffset(), ST->isVolatile(), Align);
4075 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
4076 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
4077 if (Value.getOpcode() != ISD::TargetConstantFP) {
4079 switch (CFP->getValueType(0)) {
4080 default: assert(0 && "Unknown FP type");
4081 case MVT::f80: // We don't do this for these yet.
4086 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
4087 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
4088 convertToAPInt().getZExtValue(), MVT::i32);
4089 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4090 ST->getSrcValueOffset(), ST->isVolatile(),
4091 ST->getAlignment());
4095 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
4096 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
4097 getZExtValue(), MVT::i64);
4098 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4099 ST->getSrcValueOffset(), ST->isVolatile(),
4100 ST->getAlignment());
4101 } else if (TLI.isTypeLegal(MVT::i32)) {
4102 // Many FP stores are not made apparent until after legalize, e.g. for
4103 // argument passing. Since this is so common, custom legalize the
4104 // 64-bit integer store into two 32-bit stores.
4105 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue();
4106 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
4107 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
4108 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
4110 int SVOffset = ST->getSrcValueOffset();
4111 unsigned Alignment = ST->getAlignment();
4112 bool isVolatile = ST->isVolatile();
4114 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
4115 ST->getSrcValueOffset(),
4116 isVolatile, ST->getAlignment());
4117 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4118 DAG.getConstant(4, Ptr.getValueType()));
4120 Alignment = MinAlign(Alignment, 4U);
4121 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
4122 SVOffset, isVolatile, Alignment);
4123 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
4131 // Walk up chain skipping non-aliasing memory nodes.
4132 SDOperand BetterChain = FindBetterChain(N, Chain);
4134 // If there is a better chain.
4135 if (Chain != BetterChain) {
4136 // Replace the chain to avoid dependency.
4137 SDOperand ReplStore;
4138 if (ST->isTruncatingStore()) {
4139 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
4140 ST->getSrcValue(), ST->getSrcValueOffset(), ST->getStoredVT(),
4141 ST->isVolatile(), ST->getAlignment());
4143 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
4144 ST->getSrcValue(), ST->getSrcValueOffset(),
4145 ST->isVolatile(), ST->getAlignment());
4148 // Create token to keep both nodes around.
4150 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
4152 // Don't add users to work list.
4153 return CombineTo(N, Token, false);
4157 // Try transforming N to an indexed store.
4158 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4159 return SDOperand(N, 0);
4161 // FIXME: is there such a think as a truncating indexed store?
4162 if (ST->isTruncatingStore() && ST->getAddressingMode() == ISD::UNINDEXED &&
4163 MVT::isInteger(Value.getValueType())) {
4164 // See if we can simplify the input to this truncstore with knowledge that
4165 // only the low bits are being used. For example:
4166 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
4168 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT()));
4169 AddToWorkList(Value.Val);
4171 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
4172 ST->getSrcValueOffset(), ST->getStoredVT(),
4173 ST->isVolatile(), ST->getAlignment());
4175 // Otherwise, see if we can simplify the operation with
4176 // SimplifyDemandedBits, which only works if the value has a single use.
4177 if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT())))
4178 return SDOperand(N, 0);
4184 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
4185 SDOperand InVec = N->getOperand(0);
4186 SDOperand InVal = N->getOperand(1);
4187 SDOperand EltNo = N->getOperand(2);
4189 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
4190 // vector with the inserted element.
4191 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
4192 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4193 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
4194 if (Elt < Ops.size())
4196 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
4197 &Ops[0], Ops.size());
4203 SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
4204 SDOperand InVec = N->getOperand(0);
4205 SDOperand EltNo = N->getOperand(1);
4207 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr)
4208 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
4209 if (isa<ConstantSDNode>(EltNo)) {
4210 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4211 bool NewLoad = false;
4213 MVT::ValueType VT = InVec.getValueType();
4214 MVT::ValueType EVT = MVT::getVectorElementType(VT);
4215 MVT::ValueType LVT = EVT;
4216 unsigned NumElts = MVT::getVectorNumElements(VT);
4217 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
4218 MVT::ValueType BCVT = InVec.getOperand(0).getValueType();
4219 if (!MVT::isVector(BCVT) ||
4220 NumElts != MVT::getVectorNumElements(BCVT))
4222 InVec = InVec.getOperand(0);
4223 EVT = MVT::getVectorElementType(BCVT);
4226 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4227 InVec.getOperand(0).getValueType() == EVT &&
4228 ISD::isNormalLoad(InVec.getOperand(0).Val) &&
4229 InVec.getOperand(0).hasOneUse()) {
4230 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0));
4231 unsigned Align = LN0->getAlignment();
4233 // Check the resultant load doesn't need a higher alignment than the
4235 unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
4236 getABITypeAlignment(MVT::getTypeForValueType(LVT));
4237 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align)
4242 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(),
4243 LN0->getSrcValue(), LN0->getSrcValueOffset(),
4244 LN0->isVolatile(), Align);
4252 SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
4253 unsigned NumInScalars = N->getNumOperands();
4254 MVT::ValueType VT = N->getValueType(0);
4255 unsigned NumElts = MVT::getVectorNumElements(VT);
4256 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4258 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
4259 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
4260 // at most two distinct vectors, turn this into a shuffle node.
4261 SDOperand VecIn1, VecIn2;
4262 for (unsigned i = 0; i != NumInScalars; ++i) {
4263 // Ignore undef inputs.
4264 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4266 // If this input is something other than a EXTRACT_VECTOR_ELT with a
4267 // constant index, bail out.
4268 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4269 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
4270 VecIn1 = VecIn2 = SDOperand(0, 0);
4274 // If the input vector type disagrees with the result of the build_vector,
4275 // we can't make a shuffle.
4276 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
4277 if (ExtractedFromVec.getValueType() != VT) {
4278 VecIn1 = VecIn2 = SDOperand(0, 0);
4282 // Otherwise, remember this. We allow up to two distinct input vectors.
4283 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
4286 if (VecIn1.Val == 0) {
4287 VecIn1 = ExtractedFromVec;
4288 } else if (VecIn2.Val == 0) {
4289 VecIn2 = ExtractedFromVec;
4292 VecIn1 = VecIn2 = SDOperand(0, 0);
4297 // If everything is good, we can make a shuffle operation.
4299 SmallVector<SDOperand, 8> BuildVecIndices;
4300 for (unsigned i = 0; i != NumInScalars; ++i) {
4301 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
4302 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
4306 SDOperand Extract = N->getOperand(i);
4308 // If extracting from the first vector, just use the index directly.
4309 if (Extract.getOperand(0) == VecIn1) {
4310 BuildVecIndices.push_back(Extract.getOperand(1));
4314 // Otherwise, use InIdx + VecSize
4315 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
4316 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars,
4317 TLI.getPointerTy()));
4320 // Add count and size info.
4321 MVT::ValueType BuildVecVT =
4322 MVT::getVectorType(TLI.getPointerTy(), NumElts);
4324 // Return the new VECTOR_SHUFFLE node.
4330 // Use an undef build_vector as input for the second operand.
4331 std::vector<SDOperand> UnOps(NumInScalars,
4332 DAG.getNode(ISD::UNDEF,
4334 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
4335 &UnOps[0], UnOps.size());
4336 AddToWorkList(Ops[1].Val);
4338 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
4339 &BuildVecIndices[0], BuildVecIndices.size());
4340 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3);
4346 SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
4347 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
4348 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
4349 // inputs come from at most two distinct vectors, turn this into a shuffle
4352 // If we only have one input vector, we don't need to do any concatenation.
4353 if (N->getNumOperands() == 1) {
4354 return N->getOperand(0);
4360 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
4361 SDOperand ShufMask = N->getOperand(2);
4362 unsigned NumElts = ShufMask.getNumOperands();
4364 // If the shuffle mask is an identity operation on the LHS, return the LHS.
4365 bool isIdentity = true;
4366 for (unsigned i = 0; i != NumElts; ++i) {
4367 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4368 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
4373 if (isIdentity) return N->getOperand(0);
4375 // If the shuffle mask is an identity operation on the RHS, return the RHS.
4377 for (unsigned i = 0; i != NumElts; ++i) {
4378 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4379 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
4384 if (isIdentity) return N->getOperand(1);
4386 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
4388 bool isUnary = true;
4389 bool isSplat = true;
4391 unsigned BaseIdx = 0;
4392 for (unsigned i = 0; i != NumElts; ++i)
4393 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
4394 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
4395 int V = (Idx < NumElts) ? 0 : 1;
4409 SDOperand N0 = N->getOperand(0);
4410 SDOperand N1 = N->getOperand(1);
4411 // Normalize unary shuffle so the RHS is undef.
4412 if (isUnary && VecNum == 1)
4415 // If it is a splat, check if the argument vector is a build_vector with
4416 // all scalar elements the same.
4420 // If this is a bit convert that changes the element type of the vector but
4421 // not the number of vector elements, look through it. Be careful not to
4422 // look though conversions that change things like v4f32 to v2f64.
4423 if (V->getOpcode() == ISD::BIT_CONVERT) {
4424 SDOperand ConvInput = V->getOperand(0);
4425 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts)
4429 if (V->getOpcode() == ISD::BUILD_VECTOR) {
4430 unsigned NumElems = V->getNumOperands();
4431 if (NumElems > BaseIdx) {
4433 bool AllSame = true;
4434 for (unsigned i = 0; i != NumElems; ++i) {
4435 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
4436 Base = V->getOperand(i);
4440 // Splat of <u, u, u, u>, return <u, u, u, u>
4443 for (unsigned i = 0; i != NumElems; ++i) {
4444 if (V->getOperand(i) != Base) {
4449 // Splat of <x, x, x, x>, return <x, x, x, x>
4456 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
4458 if (isUnary || N0 == N1) {
4459 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
4461 SmallVector<SDOperand, 8> MappedOps;
4462 for (unsigned i = 0; i != NumElts; ++i) {
4463 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
4464 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
4465 MappedOps.push_back(ShufMask.getOperand(i));
4468 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
4469 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
4472 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
4473 &MappedOps[0], MappedOps.size());
4474 AddToWorkList(ShufMask.Val);
4475 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
4477 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
4484 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
4485 /// an AND to a vector_shuffle with the destination vector and a zero vector.
4486 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
4487 /// vector_shuffle V, Zero, <0, 4, 2, 4>
4488 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
4489 SDOperand LHS = N->getOperand(0);
4490 SDOperand RHS = N->getOperand(1);
4491 if (N->getOpcode() == ISD::AND) {
4492 if (RHS.getOpcode() == ISD::BIT_CONVERT)
4493 RHS = RHS.getOperand(0);
4494 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
4495 std::vector<SDOperand> IdxOps;
4496 unsigned NumOps = RHS.getNumOperands();
4497 unsigned NumElts = NumOps;
4498 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType());
4499 for (unsigned i = 0; i != NumElts; ++i) {
4500 SDOperand Elt = RHS.getOperand(i);
4501 if (!isa<ConstantSDNode>(Elt))
4503 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
4504 IdxOps.push_back(DAG.getConstant(i, EVT));
4505 else if (cast<ConstantSDNode>(Elt)->isNullValue())
4506 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
4511 // Let's see if the target supports this vector_shuffle.
4512 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
4515 // Return the new VECTOR_SHUFFLE node.
4516 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts);
4517 std::vector<SDOperand> Ops;
4518 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
4520 AddToWorkList(LHS.Val);
4521 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
4522 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4523 &ZeroOps[0], ZeroOps.size()));
4524 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4525 &IdxOps[0], IdxOps.size()));
4526 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
4527 &Ops[0], Ops.size());
4528 if (VT != LHS.getValueType()) {
4529 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result);
4537 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
4538 SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
4539 // After legalize, the target may be depending on adds and other
4540 // binary ops to provide legal ways to construct constants or other
4541 // things. Simplifying them may result in a loss of legality.
4542 if (AfterLegalize) return SDOperand();
4544 MVT::ValueType VT = N->getValueType(0);
4545 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!");
4547 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4548 SDOperand LHS = N->getOperand(0);
4549 SDOperand RHS = N->getOperand(1);
4550 SDOperand Shuffle = XformToShuffleWithZero(N);
4551 if (Shuffle.Val) return Shuffle;
4553 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
4555 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
4556 RHS.getOpcode() == ISD::BUILD_VECTOR) {
4557 SmallVector<SDOperand, 8> Ops;
4558 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
4559 SDOperand LHSOp = LHS.getOperand(i);
4560 SDOperand RHSOp = RHS.getOperand(i);
4561 // If these two elements can't be folded, bail out.
4562 if ((LHSOp.getOpcode() != ISD::UNDEF &&
4563 LHSOp.getOpcode() != ISD::Constant &&
4564 LHSOp.getOpcode() != ISD::ConstantFP) ||
4565 (RHSOp.getOpcode() != ISD::UNDEF &&
4566 RHSOp.getOpcode() != ISD::Constant &&
4567 RHSOp.getOpcode() != ISD::ConstantFP))
4569 // Can't fold divide by zero.
4570 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
4571 N->getOpcode() == ISD::FDIV) {
4572 if ((RHSOp.getOpcode() == ISD::Constant &&
4573 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
4574 (RHSOp.getOpcode() == ISD::ConstantFP &&
4575 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero()))
4578 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
4579 AddToWorkList(Ops.back().Val);
4580 assert((Ops.back().getOpcode() == ISD::UNDEF ||
4581 Ops.back().getOpcode() == ISD::Constant ||
4582 Ops.back().getOpcode() == ISD::ConstantFP) &&
4583 "Scalar binop didn't fold!");
4586 if (Ops.size() == LHS.getNumOperands()) {
4587 MVT::ValueType VT = LHS.getValueType();
4588 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
4595 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
4596 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
4598 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
4599 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4600 // If we got a simplified select_cc node back from SimplifySelectCC, then
4601 // break it down into a new SETCC node, and a new SELECT node, and then return
4602 // the SELECT node, since we were called with a SELECT node.
4604 // Check to see if we got a select_cc back (to turn into setcc/select).
4605 // Otherwise, just return whatever node we got back, like fabs.
4606 if (SCC.getOpcode() == ISD::SELECT_CC) {
4607 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
4608 SCC.getOperand(0), SCC.getOperand(1),
4610 AddToWorkList(SETCC.Val);
4611 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
4612 SCC.getOperand(3), SETCC);
4619 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
4620 /// are the two values being selected between, see if we can simplify the
4621 /// select. Callers of this should assume that TheSelect is deleted if this
4622 /// returns true. As such, they should return the appropriate thing (e.g. the
4623 /// node) back to the top-level of the DAG combiner loop to avoid it being
4626 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
4629 // If this is a select from two identical things, try to pull the operation
4630 // through the select.
4631 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
4632 // If this is a load and the token chain is identical, replace the select
4633 // of two loads with a load through a select of the address to load from.
4634 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
4635 // constants have been dropped into the constant pool.
4636 if (LHS.getOpcode() == ISD::LOAD &&
4637 // Token chains must be identical.
4638 LHS.getOperand(0) == RHS.getOperand(0)) {
4639 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
4640 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
4642 // If this is an EXTLOAD, the VT's must match.
4643 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
4644 // FIXME: this conflates two src values, discarding one. This is not
4645 // the right thing to do, but nothing uses srcvalues now. When they do,
4646 // turn SrcValue into a list of locations.
4648 if (TheSelect->getOpcode() == ISD::SELECT) {
4649 // Check that the condition doesn't reach either load. If so, folding
4650 // this will induce a cycle into the DAG.
4651 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4652 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
4653 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
4654 TheSelect->getOperand(0), LLD->getBasePtr(),
4658 // Check that the condition doesn't reach either load. If so, folding
4659 // this will induce a cycle into the DAG.
4660 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4661 !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4662 !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
4663 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
4664 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
4665 TheSelect->getOperand(0),
4666 TheSelect->getOperand(1),
4667 LLD->getBasePtr(), RLD->getBasePtr(),
4668 TheSelect->getOperand(4));
4674 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
4675 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
4676 Addr,LLD->getSrcValue(),
4677 LLD->getSrcValueOffset(),
4679 LLD->getAlignment());
4681 Load = DAG.getExtLoad(LLD->getExtensionType(),
4682 TheSelect->getValueType(0),
4683 LLD->getChain(), Addr, LLD->getSrcValue(),
4684 LLD->getSrcValueOffset(),
4687 LLD->getAlignment());
4689 // Users of the select now use the result of the load.
4690 CombineTo(TheSelect, Load);
4692 // Users of the old loads now use the new load's chain. We know the
4693 // old-load value is dead now.
4694 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
4695 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
4705 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
4706 SDOperand N2, SDOperand N3,
4707 ISD::CondCode CC, bool NotExtCompare) {
4709 MVT::ValueType VT = N2.getValueType();
4710 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
4711 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
4712 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
4714 // Determine if the condition we're dealing with is constant
4715 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
4716 if (SCC.Val) AddToWorkList(SCC.Val);
4717 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
4719 // fold select_cc true, x, y -> x
4720 if (SCCC && SCCC->getValue())
4722 // fold select_cc false, x, y -> y
4723 if (SCCC && SCCC->getValue() == 0)
4726 // Check to see if we can simplify the select into an fabs node
4727 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
4728 // Allow either -0.0 or 0.0
4729 if (CFP->getValueAPF().isZero()) {
4730 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
4731 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
4732 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
4733 N2 == N3.getOperand(0))
4734 return DAG.getNode(ISD::FABS, VT, N0);
4736 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
4737 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
4738 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
4739 N2.getOperand(0) == N3)
4740 return DAG.getNode(ISD::FABS, VT, N3);
4744 // Check to see if we can perform the "gzip trick", transforming
4745 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
4746 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
4747 MVT::isInteger(N0.getValueType()) &&
4748 MVT::isInteger(N2.getValueType()) &&
4749 (N1C->isNullValue() || // (a < 0) ? b : 0
4750 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
4751 MVT::ValueType XType = N0.getValueType();
4752 MVT::ValueType AType = N2.getValueType();
4753 if (XType >= AType) {
4754 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
4755 // single-bit constant.
4756 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
4757 unsigned ShCtV = Log2_64(N2C->getValue());
4758 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
4759 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
4760 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
4761 AddToWorkList(Shift.Val);
4762 if (XType > AType) {
4763 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4764 AddToWorkList(Shift.Val);
4766 return DAG.getNode(ISD::AND, AType, Shift, N2);
4768 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4769 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4770 TLI.getShiftAmountTy()));
4771 AddToWorkList(Shift.Val);
4772 if (XType > AType) {
4773 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4774 AddToWorkList(Shift.Val);
4776 return DAG.getNode(ISD::AND, AType, Shift, N2);
4780 // fold select C, 16, 0 -> shl C, 4
4781 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
4782 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
4784 // If the caller doesn't want us to simplify this into a zext of a compare,
4786 if (NotExtCompare && N2C->getValue() == 1)
4789 // Get a SetCC of the condition
4790 // FIXME: Should probably make sure that setcc is legal if we ever have a
4791 // target where it isn't.
4792 SDOperand Temp, SCC;
4793 // cast from setcc result type to select result type
4794 if (AfterLegalize) {
4795 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4796 if (N2.getValueType() < SCC.getValueType())
4797 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
4799 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4801 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
4802 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4804 AddToWorkList(SCC.Val);
4805 AddToWorkList(Temp.Val);
4807 if (N2C->getValue() == 1)
4809 // shl setcc result by log2 n2c
4810 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
4811 DAG.getConstant(Log2_64(N2C->getValue()),
4812 TLI.getShiftAmountTy()));
4815 // Check to see if this is the equivalent of setcc
4816 // FIXME: Turn all of these into setcc if setcc if setcc is legal
4817 // otherwise, go ahead with the folds.
4818 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
4819 MVT::ValueType XType = N0.getValueType();
4820 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
4821 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4822 if (Res.getValueType() != VT)
4823 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
4827 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
4828 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
4829 TLI.isOperationLegal(ISD::CTLZ, XType)) {
4830 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
4831 return DAG.getNode(ISD::SRL, XType, Ctlz,
4832 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
4833 TLI.getShiftAmountTy()));
4835 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
4836 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
4837 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
4839 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
4840 DAG.getConstant(~0ULL, XType));
4841 return DAG.getNode(ISD::SRL, XType,
4842 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
4843 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4844 TLI.getShiftAmountTy()));
4846 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
4847 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
4848 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
4849 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4850 TLI.getShiftAmountTy()));
4851 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
4855 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
4856 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4857 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
4858 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
4859 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) {
4860 MVT::ValueType XType = N0.getValueType();
4861 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4862 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4863 TLI.getShiftAmountTy()));
4864 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4865 AddToWorkList(Shift.Val);
4866 AddToWorkList(Add.Val);
4867 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4869 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
4870 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4871 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
4872 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
4873 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
4874 MVT::ValueType XType = N0.getValueType();
4875 if (SubC->isNullValue() && MVT::isInteger(XType)) {
4876 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4877 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4878 TLI.getShiftAmountTy()));
4879 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4880 AddToWorkList(Shift.Val);
4881 AddToWorkList(Add.Val);
4882 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4890 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
4891 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
4892 SDOperand N1, ISD::CondCode Cond,
4893 bool foldBooleans) {
4894 TargetLowering::DAGCombinerInfo
4895 DagCombineInfo(DAG, !AfterLegalize, false, this);
4896 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
4899 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
4900 /// return a DAG expression to select that will generate the same value by
4901 /// multiplying by a magic number. See:
4902 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4903 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
4904 std::vector<SDNode*> Built;
4905 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
4907 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4913 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
4914 /// return a DAG expression to select that will generate the same value by
4915 /// multiplying by a magic number. See:
4916 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4917 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
4918 std::vector<SDNode*> Built;
4919 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
4921 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4927 /// FindBaseOffset - Return true if base is known not to alias with anything
4928 /// but itself. Provides base object and offset as results.
4929 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4930 // Assume it is a primitive operation.
4931 Base = Ptr; Offset = 0;
4933 // If it's an adding a simple constant then integrate the offset.
4934 if (Base.getOpcode() == ISD::ADD) {
4935 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4936 Base = Base.getOperand(0);
4937 Offset += C->getValue();
4941 // If it's any of the following then it can't alias with anything but itself.
4942 return isa<FrameIndexSDNode>(Base) ||
4943 isa<ConstantPoolSDNode>(Base) ||
4944 isa<GlobalAddressSDNode>(Base);
4947 /// isAlias - Return true if there is any possibility that the two addresses
4949 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4950 const Value *SrcValue1, int SrcValueOffset1,
4951 SDOperand Ptr2, int64_t Size2,
4952 const Value *SrcValue2, int SrcValueOffset2)
4954 // If they are the same then they must be aliases.
4955 if (Ptr1 == Ptr2) return true;
4957 // Gather base node and offset information.
4958 SDOperand Base1, Base2;
4959 int64_t Offset1, Offset2;
4960 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4961 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4963 // If they have a same base address then...
4964 if (Base1 == Base2) {
4965 // Check to see if the addresses overlap.
4966 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4969 // If we know both bases then they can't alias.
4970 if (KnownBase1 && KnownBase2) return false;
4972 if (CombinerGlobalAA) {
4973 // Use alias analysis information.
4974 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
4975 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
4976 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
4977 AliasAnalysis::AliasResult AAResult =
4978 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
4979 if (AAResult == AliasAnalysis::NoAlias)
4983 // Otherwise we have to assume they alias.
4987 /// FindAliasInfo - Extracts the relevant alias information from the memory
4988 /// node. Returns true if the operand was a load.
4989 bool DAGCombiner::FindAliasInfo(SDNode *N,
4990 SDOperand &Ptr, int64_t &Size,
4991 const Value *&SrcValue, int &SrcValueOffset) {
4992 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4993 Ptr = LD->getBasePtr();
4994 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4995 SrcValue = LD->getSrcValue();
4996 SrcValueOffset = LD->getSrcValueOffset();
4998 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4999 Ptr = ST->getBasePtr();
5000 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
5001 SrcValue = ST->getSrcValue();
5002 SrcValueOffset = ST->getSrcValueOffset();
5004 assert(0 && "FindAliasInfo expected a memory operand");
5010 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
5011 /// looking for aliasing nodes and adding them to the Aliases vector.
5012 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
5013 SmallVector<SDOperand, 8> &Aliases) {
5014 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
5015 std::set<SDNode *> Visited; // Visited node set.
5017 // Get alias information for node.
5020 const Value *SrcValue;
5022 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
5025 Chains.push_back(OriginalChain);
5027 // Look at each chain and determine if it is an alias. If so, add it to the
5028 // aliases list. If not, then continue up the chain looking for the next
5030 while (!Chains.empty()) {
5031 SDOperand Chain = Chains.back();
5034 // Don't bother if we've been before.
5035 if (Visited.find(Chain.Val) != Visited.end()) continue;
5036 Visited.insert(Chain.Val);
5038 switch (Chain.getOpcode()) {
5039 case ISD::EntryToken:
5040 // Entry token is ideal chain operand, but handled in FindBetterChain.
5045 // Get alias information for Chain.
5048 const Value *OpSrcValue;
5049 int OpSrcValueOffset;
5050 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
5051 OpSrcValue, OpSrcValueOffset);
5053 // If chain is alias then stop here.
5054 if (!(IsLoad && IsOpLoad) &&
5055 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
5056 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
5057 Aliases.push_back(Chain);
5059 // Look further up the chain.
5060 Chains.push_back(Chain.getOperand(0));
5061 // Clean up old chain.
5062 AddToWorkList(Chain.Val);
5067 case ISD::TokenFactor:
5068 // We have to check each of the operands of the token factor, so we queue
5069 // then up. Adding the operands to the queue (stack) in reverse order
5070 // maintains the original order and increases the likelihood that getNode
5071 // will find a matching token factor (CSE.)
5072 for (unsigned n = Chain.getNumOperands(); n;)
5073 Chains.push_back(Chain.getOperand(--n));
5074 // Eliminate the token factor if we can.
5075 AddToWorkList(Chain.Val);
5079 // For all other instructions we will just have to take what we can get.
5080 Aliases.push_back(Chain);
5086 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
5087 /// for a better chain (aliasing node.)
5088 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
5089 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
5091 // Accumulate all the aliases to this node.
5092 GatherAllAliases(N, OldChain, Aliases);
5094 if (Aliases.size() == 0) {
5095 // If no operands then chain to entry token.
5096 return DAG.getEntryNode();
5097 } else if (Aliases.size() == 1) {
5098 // If a single operand then chain to it. We don't need to revisit it.
5102 // Construct a custom tailored token factor.
5103 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5104 &Aliases[0], Aliases.size());
5106 // Make sure the old chain gets cleaned up.
5107 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
5112 // SelectionDAG::Combine - This is the entry point for the file.
5114 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
5115 if (!RunningAfterLegalize && ViewDAGCombine1)
5117 if (RunningAfterLegalize && ViewDAGCombine2)
5119 /// run - This is the main entry point to this class.
5121 DAGCombiner(*this, AA).Run(RunningAfterLegalize);