1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "dagcombine"
16 #include "llvm/CodeGen/SelectionDAG.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Target/TargetData.h"
21 #include "llvm/Target/TargetFrameInfo.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/SmallPtrSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
35 STATISTIC(NodesCombined , "Number of dag nodes combined");
36 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
37 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
42 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
43 cl::desc("Pop up a window to show dags before the first "
46 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
47 cl::desc("Pop up a window to show dags before the second "
50 static const bool ViewDAGCombine1 = false;
51 static const bool ViewDAGCombine2 = false;
55 CombinerAA("combiner-alias-analysis", cl::Hidden,
56 cl::desc("Turn on alias analysis during testing"));
59 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
60 cl::desc("Include global information in alias analysis"));
62 //------------------------------ DAGCombiner ---------------------------------//
64 class VISIBILITY_HIDDEN DAGCombiner {
69 // Worklist of all of the nodes that need to be simplified.
70 std::vector<SDNode*> WorkList;
72 // AA - Used for DAG load/store alias analysis.
75 /// AddUsersToWorkList - When an instruction is simplified, add all users of
76 /// the instruction to the work lists because they might get more simplified
79 void AddUsersToWorkList(SDNode *N) {
80 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
82 AddToWorkList(UI->getUser());
85 /// visit - call the node-specific routine that knows how to fold each
86 /// particular type of node.
87 SDOperand visit(SDNode *N);
90 /// AddToWorkList - Add to the work list making sure it's instance is at the
91 /// the back (next to be processed.)
92 void AddToWorkList(SDNode *N) {
93 removeFromWorkList(N);
94 WorkList.push_back(N);
97 /// removeFromWorkList - remove all instances of N from the worklist.
99 void removeFromWorkList(SDNode *N) {
100 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
104 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
107 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
108 return CombineTo(N, &Res, 1, AddTo);
111 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
113 SDOperand To[] = { Res0, Res1 };
114 return CombineTo(N, To, 2, AddTo);
119 /// SimplifyDemandedBits - Check the specified integer node value to see if
120 /// it can be simplified or if things it uses can be simplified by bit
121 /// propagation. If so, return true.
122 bool SimplifyDemandedBits(SDOperand Op) {
123 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits());
124 return SimplifyDemandedBits(Op, Demanded);
127 bool SimplifyDemandedBits(SDOperand Op, const APInt &Demanded);
129 bool CombineToPreIndexedLoadStore(SDNode *N);
130 bool CombineToPostIndexedLoadStore(SDNode *N);
133 /// combine - call the node-specific routine that knows how to fold each
134 /// particular type of node. If that doesn't do anything, try the
135 /// target-specific DAG combines.
136 SDOperand combine(SDNode *N);
138 // Visitation implementation - Implement dag node combining for different
139 // node types. The semantics are as follows:
141 // SDOperand.Val == 0 - No change was made
142 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
143 // otherwise - N should be replaced by the returned Operand.
145 SDOperand visitTokenFactor(SDNode *N);
146 SDOperand visitMERGE_VALUES(SDNode *N);
147 SDOperand visitADD(SDNode *N);
148 SDOperand visitSUB(SDNode *N);
149 SDOperand visitADDC(SDNode *N);
150 SDOperand visitADDE(SDNode *N);
151 SDOperand visitMUL(SDNode *N);
152 SDOperand visitSDIV(SDNode *N);
153 SDOperand visitUDIV(SDNode *N);
154 SDOperand visitSREM(SDNode *N);
155 SDOperand visitUREM(SDNode *N);
156 SDOperand visitMULHU(SDNode *N);
157 SDOperand visitMULHS(SDNode *N);
158 SDOperand visitSMUL_LOHI(SDNode *N);
159 SDOperand visitUMUL_LOHI(SDNode *N);
160 SDOperand visitSDIVREM(SDNode *N);
161 SDOperand visitUDIVREM(SDNode *N);
162 SDOperand visitAND(SDNode *N);
163 SDOperand visitOR(SDNode *N);
164 SDOperand visitXOR(SDNode *N);
165 SDOperand SimplifyVBinOp(SDNode *N);
166 SDOperand visitSHL(SDNode *N);
167 SDOperand visitSRA(SDNode *N);
168 SDOperand visitSRL(SDNode *N);
169 SDOperand visitCTLZ(SDNode *N);
170 SDOperand visitCTTZ(SDNode *N);
171 SDOperand visitCTPOP(SDNode *N);
172 SDOperand visitSELECT(SDNode *N);
173 SDOperand visitSELECT_CC(SDNode *N);
174 SDOperand visitSETCC(SDNode *N);
175 SDOperand visitSIGN_EXTEND(SDNode *N);
176 SDOperand visitZERO_EXTEND(SDNode *N);
177 SDOperand visitANY_EXTEND(SDNode *N);
178 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
179 SDOperand visitTRUNCATE(SDNode *N);
180 SDOperand visitBIT_CONVERT(SDNode *N);
181 SDOperand visitBUILD_PAIR(SDNode *N);
182 SDOperand visitFADD(SDNode *N);
183 SDOperand visitFSUB(SDNode *N);
184 SDOperand visitFMUL(SDNode *N);
185 SDOperand visitFDIV(SDNode *N);
186 SDOperand visitFREM(SDNode *N);
187 SDOperand visitFCOPYSIGN(SDNode *N);
188 SDOperand visitSINT_TO_FP(SDNode *N);
189 SDOperand visitUINT_TO_FP(SDNode *N);
190 SDOperand visitFP_TO_SINT(SDNode *N);
191 SDOperand visitFP_TO_UINT(SDNode *N);
192 SDOperand visitFP_ROUND(SDNode *N);
193 SDOperand visitFP_ROUND_INREG(SDNode *N);
194 SDOperand visitFP_EXTEND(SDNode *N);
195 SDOperand visitFNEG(SDNode *N);
196 SDOperand visitFABS(SDNode *N);
197 SDOperand visitBRCOND(SDNode *N);
198 SDOperand visitBR_CC(SDNode *N);
199 SDOperand visitLOAD(SDNode *N);
200 SDOperand visitSTORE(SDNode *N);
201 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
202 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N);
203 SDOperand visitBUILD_VECTOR(SDNode *N);
204 SDOperand visitCONCAT_VECTORS(SDNode *N);
205 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
207 SDOperand XformToShuffleWithZero(SDNode *N);
208 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
210 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt);
212 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
213 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
214 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
215 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
216 SDOperand N3, ISD::CondCode CC,
217 bool NotExtCompare = false);
218 SDOperand SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
219 ISD::CondCode Cond, bool foldBooleans = true);
220 SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
222 SDOperand CombineConsecutiveLoads(SDNode *N, MVT VT);
223 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
224 SDOperand BuildSDIV(SDNode *N);
225 SDOperand BuildUDIV(SDNode *N);
226 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
227 SDOperand ReduceLoadWidth(SDNode *N);
229 SDOperand GetDemandedBits(SDOperand V, const APInt &Mask);
231 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
232 /// looking for aliasing nodes and adding them to the Aliases vector.
233 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
234 SmallVector<SDOperand, 8> &Aliases);
236 /// isAlias - Return true if there is any possibility that the two addresses
238 bool isAlias(SDOperand Ptr1, int64_t Size1,
239 const Value *SrcValue1, int SrcValueOffset1,
240 SDOperand Ptr2, int64_t Size2,
241 const Value *SrcValue2, int SrcValueOffset2);
243 /// FindAliasInfo - Extracts the relevant alias information from the memory
244 /// node. Returns true if the operand was a load.
245 bool FindAliasInfo(SDNode *N,
246 SDOperand &Ptr, int64_t &Size,
247 const Value *&SrcValue, int &SrcValueOffset);
249 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
250 /// looking for a better chain (aliasing node.)
251 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
254 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
256 TLI(D.getTargetLoweringInfo()),
257 AfterLegalize(false),
260 /// Run - runs the dag combiner on all nodes in the work list
261 void Run(bool RunningAfterLegalize);
267 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
268 /// nodes from the worklist.
269 class VISIBILITY_HIDDEN WorkListRemover :
270 public SelectionDAG::DAGUpdateListener {
273 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
275 virtual void NodeDeleted(SDNode *N, SDNode *E) {
276 DC.removeFromWorkList(N);
279 virtual void NodeUpdated(SDNode *N) {
285 //===----------------------------------------------------------------------===//
286 // TargetLowering::DAGCombinerInfo implementation
287 //===----------------------------------------------------------------------===//
289 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
290 ((DAGCombiner*)DC)->AddToWorkList(N);
293 SDOperand TargetLowering::DAGCombinerInfo::
294 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
295 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
298 SDOperand TargetLowering::DAGCombinerInfo::
299 CombineTo(SDNode *N, SDOperand Res) {
300 return ((DAGCombiner*)DC)->CombineTo(N, Res);
304 SDOperand TargetLowering::DAGCombinerInfo::
305 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
306 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
310 //===----------------------------------------------------------------------===//
312 //===----------------------------------------------------------------------===//
314 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
315 /// specified expression for the same cost as the expression itself, or 2 if we
316 /// can compute the negated form more cheaply than the expression itself.
317 static char isNegatibleForFree(SDOperand Op, bool AfterLegalize,
318 unsigned Depth = 0) {
319 // No compile time optimizations on this type.
320 if (Op.getValueType() == MVT::ppcf128)
323 // fneg is removable even if it has multiple uses.
324 if (Op.getOpcode() == ISD::FNEG) return 2;
326 // Don't allow anything with multiple uses.
327 if (!Op.hasOneUse()) return 0;
329 // Don't recurse exponentially.
330 if (Depth > 6) return 0;
332 switch (Op.getOpcode()) {
333 default: return false;
334 case ISD::ConstantFP:
335 // Don't invert constant FP values after legalize. The negated constant
336 // isn't necessarily legal.
337 return AfterLegalize ? 0 : 1;
339 // FIXME: determine better conditions for this xform.
340 if (!UnsafeFPMath) return 0;
343 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1))
346 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1);
348 // We can't turn -(A-B) into B-A when we honor signed zeros.
349 if (!UnsafeFPMath) return 0;
356 if (HonorSignDependentRoundingFPMath()) return 0;
358 // -(X*Y) -> (-X * Y) or (X*-Y)
359 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1))
362 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1);
367 return isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1);
371 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
372 /// returns the newly negated expression.
373 static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
374 bool AfterLegalize, unsigned Depth = 0) {
375 // fneg is removable even if it has multiple uses.
376 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
378 // Don't allow anything with multiple uses.
379 assert(Op.hasOneUse() && "Unknown reuse!");
381 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
382 switch (Op.getOpcode()) {
383 default: assert(0 && "Unknown code");
384 case ISD::ConstantFP: {
385 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
387 return DAG.getConstantFP(V, Op.getValueType());
390 // FIXME: determine better conditions for this xform.
391 assert(UnsafeFPMath);
394 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1))
395 return DAG.getNode(ISD::FSUB, Op.getValueType(),
396 GetNegatedExpression(Op.getOperand(0), DAG,
397 AfterLegalize, Depth+1),
400 return DAG.getNode(ISD::FSUB, Op.getValueType(),
401 GetNegatedExpression(Op.getOperand(1), DAG,
402 AfterLegalize, Depth+1),
405 // We can't turn -(A-B) into B-A when we honor signed zeros.
406 assert(UnsafeFPMath);
409 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
410 if (N0CFP->getValueAPF().isZero())
411 return Op.getOperand(1);
414 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1),
419 assert(!HonorSignDependentRoundingFPMath());
422 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1))
423 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
424 GetNegatedExpression(Op.getOperand(0), DAG,
425 AfterLegalize, Depth+1),
429 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
431 GetNegatedExpression(Op.getOperand(1), DAG,
432 AfterLegalize, Depth+1));
436 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
437 GetNegatedExpression(Op.getOperand(0), DAG,
438 AfterLegalize, Depth+1));
440 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(),
441 GetNegatedExpression(Op.getOperand(0), DAG,
442 AfterLegalize, Depth+1),
448 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
449 // that selects between the values 1 and 0, making it equivalent to a setcc.
450 // Also, set the incoming LHS, RHS, and CC references to the appropriate
451 // nodes based on the type of node we are checking. This simplifies life a
452 // bit for the callers.
453 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
455 if (N.getOpcode() == ISD::SETCC) {
456 LHS = N.getOperand(0);
457 RHS = N.getOperand(1);
458 CC = N.getOperand(2);
461 if (N.getOpcode() == ISD::SELECT_CC &&
462 N.getOperand(2).getOpcode() == ISD::Constant &&
463 N.getOperand(3).getOpcode() == ISD::Constant &&
464 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
465 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
466 LHS = N.getOperand(0);
467 RHS = N.getOperand(1);
468 CC = N.getOperand(4);
474 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
475 // one use. If this is true, it allows the users to invert the operation for
476 // free when it is profitable to do so.
477 static bool isOneUseSetCC(SDOperand N) {
478 SDOperand N0, N1, N2;
479 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
484 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
485 MVT VT = N0.getValueType();
486 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
487 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
488 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
489 if (isa<ConstantSDNode>(N1)) {
490 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
491 AddToWorkList(OpNode.Val);
492 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
493 } else if (N0.hasOneUse()) {
494 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
495 AddToWorkList(OpNode.Val);
496 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
499 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
500 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
501 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
502 if (isa<ConstantSDNode>(N0)) {
503 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
504 AddToWorkList(OpNode.Val);
505 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
506 } else if (N1.hasOneUse()) {
507 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
508 AddToWorkList(OpNode.Val);
509 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
515 SDOperand DAGCombiner::CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
517 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
519 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
520 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
521 DOUT << " and " << NumTo-1 << " other values\n";
522 WorkListRemover DeadNodes(*this);
523 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
526 // Push the new nodes and any users onto the worklist
527 for (unsigned i = 0, e = NumTo; i != e; ++i) {
528 AddToWorkList(To[i].Val);
529 AddUsersToWorkList(To[i].Val);
533 // Nodes can be reintroduced into the worklist. Make sure we do not
534 // process a node that has been replaced.
535 removeFromWorkList(N);
537 // Finally, since the node is now dead, remove it from the graph.
539 return SDOperand(N, 0);
542 /// SimplifyDemandedBits - Check the specified integer node value to see if
543 /// it can be simplified or if things it uses can be simplified by bit
544 /// propagation. If so, return true.
545 bool DAGCombiner::SimplifyDemandedBits(SDOperand Op, const APInt &Demanded) {
546 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize);
547 APInt KnownZero, KnownOne;
548 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
552 AddToWorkList(Op.Val);
554 // Replace the old value with the new one.
556 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
557 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
560 // Replace all uses. If any nodes become isomorphic to other nodes and
561 // are deleted, make sure to remove them from our worklist.
562 WorkListRemover DeadNodes(*this);
563 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
565 // Push the new node and any (possibly new) users onto the worklist.
566 AddToWorkList(TLO.New.Val);
567 AddUsersToWorkList(TLO.New.Val);
569 // Finally, if the node is now dead, remove it from the graph. The node
570 // may not be dead if the replacement process recursively simplified to
571 // something else needing this node.
572 if (TLO.Old.Val->use_empty()) {
573 removeFromWorkList(TLO.Old.Val);
575 // If the operands of this node are only used by the node, they will now
576 // be dead. Make sure to visit them first to delete dead nodes early.
577 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i)
578 if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
579 AddToWorkList(TLO.Old.Val->getOperand(i).Val);
581 DAG.DeleteNode(TLO.Old.Val);
586 //===----------------------------------------------------------------------===//
587 // Main DAG Combiner implementation
588 //===----------------------------------------------------------------------===//
590 void DAGCombiner::Run(bool RunningAfterLegalize) {
591 // set the instance variable, so that the various visit routines may use it.
592 AfterLegalize = RunningAfterLegalize;
594 // Add all the dag nodes to the worklist.
595 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
596 E = DAG.allnodes_end(); I != E; ++I)
597 WorkList.push_back(I);
599 // Create a dummy node (which is not added to allnodes), that adds a reference
600 // to the root node, preventing it from being deleted, and tracking any
601 // changes of the root.
602 HandleSDNode Dummy(DAG.getRoot());
604 // The root of the dag may dangle to deleted nodes until the dag combiner is
605 // done. Set it to null to avoid confusion.
606 DAG.setRoot(SDOperand());
608 // while the worklist isn't empty, inspect the node on the end of it and
609 // try and combine it.
610 while (!WorkList.empty()) {
611 SDNode *N = WorkList.back();
614 // If N has no uses, it is dead. Make sure to revisit all N's operands once
615 // N is deleted from the DAG, since they too may now be dead or may have a
616 // reduced number of uses, allowing other xforms.
617 if (N->use_empty() && N != &Dummy) {
618 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
619 AddToWorkList(N->getOperand(i).Val);
625 SDOperand RV = combine(N);
632 // If we get back the same node we passed in, rather than a new node or
633 // zero, we know that the node must have defined multiple values and
634 // CombineTo was used. Since CombineTo takes care of the worklist
635 // mechanics for us, we have no work to do in this case.
639 assert(N->getOpcode() != ISD::DELETED_NODE &&
640 RV.Val->getOpcode() != ISD::DELETED_NODE &&
641 "Node was deleted but visit returned new node!");
643 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
644 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
646 WorkListRemover DeadNodes(*this);
647 if (N->getNumValues() == RV.Val->getNumValues())
648 DAG.ReplaceAllUsesWith(N, RV.Val, &DeadNodes);
650 assert(N->getValueType(0) == RV.getValueType() &&
651 N->getNumValues() == 1 && "Type mismatch");
653 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
656 // Push the new node and any users onto the worklist
657 AddToWorkList(RV.Val);
658 AddUsersToWorkList(RV.Val);
660 // Add any uses of the old node to the worklist in case this node is the
661 // last one that uses them. They may become dead after this node is
663 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
664 AddToWorkList(N->getOperand(i).Val);
666 // Nodes can be reintroduced into the worklist. Make sure we do not
667 // process a node that has been replaced.
668 removeFromWorkList(N);
670 // Finally, since the node is now dead, remove it from the graph.
674 // If the root changed (e.g. it was a dead load, update the root).
675 DAG.setRoot(Dummy.getValue());
678 SDOperand DAGCombiner::visit(SDNode *N) {
679 switch(N->getOpcode()) {
681 case ISD::TokenFactor: return visitTokenFactor(N);
682 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
683 case ISD::ADD: return visitADD(N);
684 case ISD::SUB: return visitSUB(N);
685 case ISD::ADDC: return visitADDC(N);
686 case ISD::ADDE: return visitADDE(N);
687 case ISD::MUL: return visitMUL(N);
688 case ISD::SDIV: return visitSDIV(N);
689 case ISD::UDIV: return visitUDIV(N);
690 case ISD::SREM: return visitSREM(N);
691 case ISD::UREM: return visitUREM(N);
692 case ISD::MULHU: return visitMULHU(N);
693 case ISD::MULHS: return visitMULHS(N);
694 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
695 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
696 case ISD::SDIVREM: return visitSDIVREM(N);
697 case ISD::UDIVREM: return visitUDIVREM(N);
698 case ISD::AND: return visitAND(N);
699 case ISD::OR: return visitOR(N);
700 case ISD::XOR: return visitXOR(N);
701 case ISD::SHL: return visitSHL(N);
702 case ISD::SRA: return visitSRA(N);
703 case ISD::SRL: return visitSRL(N);
704 case ISD::CTLZ: return visitCTLZ(N);
705 case ISD::CTTZ: return visitCTTZ(N);
706 case ISD::CTPOP: return visitCTPOP(N);
707 case ISD::SELECT: return visitSELECT(N);
708 case ISD::SELECT_CC: return visitSELECT_CC(N);
709 case ISD::SETCC: return visitSETCC(N);
710 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
711 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
712 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
713 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
714 case ISD::TRUNCATE: return visitTRUNCATE(N);
715 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
716 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
717 case ISD::FADD: return visitFADD(N);
718 case ISD::FSUB: return visitFSUB(N);
719 case ISD::FMUL: return visitFMUL(N);
720 case ISD::FDIV: return visitFDIV(N);
721 case ISD::FREM: return visitFREM(N);
722 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
723 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
724 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
725 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
726 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
727 case ISD::FP_ROUND: return visitFP_ROUND(N);
728 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
729 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
730 case ISD::FNEG: return visitFNEG(N);
731 case ISD::FABS: return visitFABS(N);
732 case ISD::BRCOND: return visitBRCOND(N);
733 case ISD::BR_CC: return visitBR_CC(N);
734 case ISD::LOAD: return visitLOAD(N);
735 case ISD::STORE: return visitSTORE(N);
736 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
737 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
738 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
739 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
740 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
745 SDOperand DAGCombiner::combine(SDNode *N) {
747 SDOperand RV = visit(N);
749 // If nothing happened, try a target-specific DAG combine.
751 assert(N->getOpcode() != ISD::DELETED_NODE &&
752 "Node was deleted but visit returned NULL!");
754 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
755 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
757 // Expose the DAG combiner to the target combiner impls.
758 TargetLowering::DAGCombinerInfo
759 DagCombineInfo(DAG, !AfterLegalize, false, this);
761 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
765 // If N is a commutative binary node, try commuting it to enable more
768 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
769 N->getNumValues() == 1) {
770 SDOperand N0 = N->getOperand(0);
771 SDOperand N1 = N->getOperand(1);
772 // Constant operands are canonicalized to RHS.
773 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
774 SDOperand Ops[] = { N1, N0 };
775 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
778 return SDOperand(CSENode, 0);
785 /// getInputChainForNode - Given a node, return its input chain if it has one,
786 /// otherwise return a null sd operand.
787 static SDOperand getInputChainForNode(SDNode *N) {
788 if (unsigned NumOps = N->getNumOperands()) {
789 if (N->getOperand(0).getValueType() == MVT::Other)
790 return N->getOperand(0);
791 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
792 return N->getOperand(NumOps-1);
793 for (unsigned i = 1; i < NumOps-1; ++i)
794 if (N->getOperand(i).getValueType() == MVT::Other)
795 return N->getOperand(i);
797 return SDOperand(0, 0);
800 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
801 // If N has two operands, where one has an input chain equal to the other,
802 // the 'other' chain is redundant.
803 if (N->getNumOperands() == 2) {
804 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
805 return N->getOperand(0);
806 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
807 return N->getOperand(1);
810 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
811 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
812 SmallPtrSet<SDNode*, 16> SeenOps;
813 bool Changed = false; // If we should replace this token factor.
815 // Start out with this token factor.
818 // Iterate through token factors. The TFs grows when new token factors are
820 for (unsigned i = 0; i < TFs.size(); ++i) {
823 // Check each of the operands.
824 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
825 SDOperand Op = TF->getOperand(i);
827 switch (Op.getOpcode()) {
828 case ISD::EntryToken:
829 // Entry tokens don't need to be added to the list. They are
834 case ISD::TokenFactor:
835 if ((CombinerAA || Op.hasOneUse()) &&
836 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
837 // Queue up for processing.
838 TFs.push_back(Op.Val);
839 // Clean up in case the token factor is removed.
840 AddToWorkList(Op.Val);
847 // Only add if it isn't already in the list.
848 if (SeenOps.insert(Op.Val))
859 // If we've change things around then replace token factor.
862 // The entry token is the only possible outcome.
863 Result = DAG.getEntryNode();
865 // New and improved token factor.
866 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
869 // Don't add users to work list.
870 return CombineTo(N, Result, false);
876 /// MERGE_VALUES can always be eliminated.
877 SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) {
878 WorkListRemover DeadNodes(*this);
879 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
880 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, i), N->getOperand(i),
882 removeFromWorkList(N);
884 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
889 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
890 MVT VT = N0.getValueType();
891 SDOperand N00 = N0.getOperand(0);
892 SDOperand N01 = N0.getOperand(1);
893 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
894 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
895 isa<ConstantSDNode>(N00.getOperand(1))) {
896 N0 = DAG.getNode(ISD::ADD, VT,
897 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
898 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
899 return DAG.getNode(ISD::ADD, VT, N0, N1);
905 SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
907 MVT VT = N->getValueType(0);
908 unsigned Opc = N->getOpcode();
909 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
910 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
911 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
912 ISD::CondCode CC = ISD::SETCC_INVALID;
914 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
916 SDOperand CCOp = Slct.getOperand(0);
917 if (CCOp.getOpcode() == ISD::SETCC)
918 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
921 bool DoXform = false;
923 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
925 if (LHS.getOpcode() == ISD::Constant &&
926 cast<ConstantSDNode>(LHS)->isNullValue())
928 else if (CC != ISD::SETCC_INVALID &&
929 RHS.getOpcode() == ISD::Constant &&
930 cast<ConstantSDNode>(RHS)->isNullValue()) {
932 SDOperand Op0 = Slct.getOperand(0);
933 bool isInt = (isSlctCC ? Op0.getValueType() :
934 Op0.getOperand(0).getValueType()).isInteger();
935 CC = ISD::getSetCCInverse(CC, isInt);
941 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS);
943 return DAG.getSelectCC(OtherOp, Result,
944 Slct.getOperand(0), Slct.getOperand(1), CC);
945 SDOperand CCOp = Slct.getOperand(0);
947 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
948 CCOp.getOperand(1), CC);
949 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
954 SDOperand DAGCombiner::visitADD(SDNode *N) {
955 SDOperand N0 = N->getOperand(0);
956 SDOperand N1 = N->getOperand(1);
957 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
958 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
959 MVT VT = N0.getValueType();
963 SDOperand FoldedVOp = SimplifyVBinOp(N);
964 if (FoldedVOp.Val) return FoldedVOp;
967 // fold (add x, undef) -> undef
968 if (N0.getOpcode() == ISD::UNDEF)
970 if (N1.getOpcode() == ISD::UNDEF)
972 // fold (add c1, c2) -> c1+c2
974 return DAG.getConstant(N0C->getAPIntValue() + N1C->getAPIntValue(), VT);
975 // canonicalize constant to RHS
977 return DAG.getNode(ISD::ADD, VT, N1, N0);
978 // fold (add x, 0) -> x
979 if (N1C && N1C->isNullValue())
981 // fold ((c1-A)+c2) -> (c1+c2)-A
982 if (N1C && N0.getOpcode() == ISD::SUB)
983 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
984 return DAG.getNode(ISD::SUB, VT,
985 DAG.getConstant(N1C->getAPIntValue()+
986 N0C->getAPIntValue(), VT),
989 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
992 // fold ((0-A) + B) -> B-A
993 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
994 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
995 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
996 // fold (A + (0-B)) -> A-B
997 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
998 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
999 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
1000 // fold (A+(B-A)) -> B
1001 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1002 return N1.getOperand(0);
1004 if (!VT.isVector() && SimplifyDemandedBits(SDOperand(N, 0)))
1005 return SDOperand(N, 0);
1007 // fold (a+b) -> (a|b) iff a and b share no bits.
1008 if (VT.isInteger() && !VT.isVector()) {
1009 APInt LHSZero, LHSOne;
1010 APInt RHSZero, RHSOne;
1011 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1012 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1013 if (LHSZero.getBoolValue()) {
1014 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1016 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1017 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1018 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1019 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1020 return DAG.getNode(ISD::OR, VT, N0, N1);
1024 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1025 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
1026 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
1027 if (Result.Val) return Result;
1029 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
1030 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
1031 if (Result.Val) return Result;
1034 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1035 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
1036 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG);
1037 if (Result.Val) return Result;
1039 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
1040 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
1041 if (Result.Val) return Result;
1047 SDOperand DAGCombiner::visitADDC(SDNode *N) {
1048 SDOperand N0 = N->getOperand(0);
1049 SDOperand N1 = N->getOperand(1);
1050 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1051 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1052 MVT VT = N0.getValueType();
1054 // If the flag result is dead, turn this into an ADD.
1055 if (N->hasNUsesOfValue(0, 1))
1056 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
1057 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
1059 // canonicalize constant to RHS.
1061 SDOperand Ops[] = { N1, N0 };
1062 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
1065 // fold (addc x, 0) -> x + no carry out
1066 if (N1C && N1C->isNullValue())
1067 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
1069 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1070 APInt LHSZero, LHSOne;
1071 APInt RHSZero, RHSOne;
1072 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1073 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1074 if (LHSZero.getBoolValue()) {
1075 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1077 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1078 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1079 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1080 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1081 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
1082 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
1088 SDOperand DAGCombiner::visitADDE(SDNode *N) {
1089 SDOperand N0 = N->getOperand(0);
1090 SDOperand N1 = N->getOperand(1);
1091 SDOperand CarryIn = N->getOperand(2);
1092 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1093 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1094 //MVT VT = N0.getValueType();
1096 // canonicalize constant to RHS
1098 SDOperand Ops[] = { N1, N0, CarryIn };
1099 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
1102 // fold (adde x, y, false) -> (addc x, y)
1103 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
1104 SDOperand Ops[] = { N1, N0 };
1105 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
1113 SDOperand DAGCombiner::visitSUB(SDNode *N) {
1114 SDOperand N0 = N->getOperand(0);
1115 SDOperand N1 = N->getOperand(1);
1116 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1117 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1118 MVT VT = N0.getValueType();
1121 if (VT.isVector()) {
1122 SDOperand FoldedVOp = SimplifyVBinOp(N);
1123 if (FoldedVOp.Val) return FoldedVOp;
1126 // fold (sub x, x) -> 0
1128 return DAG.getConstant(0, N->getValueType(0));
1129 // fold (sub c1, c2) -> c1-c2
1131 return DAG.getNode(ISD::SUB, VT, N0, N1);
1132 // fold (sub x, c) -> (add x, -c)
1134 return DAG.getNode(ISD::ADD, VT, N0,
1135 DAG.getConstant(-N1C->getAPIntValue(), VT));
1136 // fold (A+B)-A -> B
1137 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1138 return N0.getOperand(1);
1139 // fold (A+B)-B -> A
1140 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1141 return N0.getOperand(0);
1142 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1143 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
1144 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
1145 if (Result.Val) return Result;
1147 // If either operand of a sub is undef, the result is undef
1148 if (N0.getOpcode() == ISD::UNDEF)
1150 if (N1.getOpcode() == ISD::UNDEF)
1156 SDOperand DAGCombiner::visitMUL(SDNode *N) {
1157 SDOperand N0 = N->getOperand(0);
1158 SDOperand N1 = N->getOperand(1);
1159 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1160 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1161 MVT VT = N0.getValueType();
1164 if (VT.isVector()) {
1165 SDOperand FoldedVOp = SimplifyVBinOp(N);
1166 if (FoldedVOp.Val) return FoldedVOp;
1169 // fold (mul x, undef) -> 0
1170 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1171 return DAG.getConstant(0, VT);
1172 // fold (mul c1, c2) -> c1*c2
1174 return DAG.getNode(ISD::MUL, VT, N0, N1);
1175 // canonicalize constant to RHS
1177 return DAG.getNode(ISD::MUL, VT, N1, N0);
1178 // fold (mul x, 0) -> 0
1179 if (N1C && N1C->isNullValue())
1181 // fold (mul x, -1) -> 0-x
1182 if (N1C && N1C->isAllOnesValue())
1183 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1184 // fold (mul x, (1 << c)) -> x << c
1185 if (N1C && N1C->getAPIntValue().isPowerOf2())
1186 return DAG.getNode(ISD::SHL, VT, N0,
1187 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1188 TLI.getShiftAmountTy()));
1189 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1190 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
1191 // FIXME: If the input is something that is easily negated (e.g. a
1192 // single-use add), we should put the negate there.
1193 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
1194 DAG.getNode(ISD::SHL, VT, N0,
1195 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
1196 TLI.getShiftAmountTy())));
1199 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1200 if (N1C && N0.getOpcode() == ISD::SHL &&
1201 isa<ConstantSDNode>(N0.getOperand(1))) {
1202 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
1203 AddToWorkList(C3.Val);
1204 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
1207 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1210 SDOperand Sh(0,0), Y(0,0);
1211 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1212 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1213 N0.Val->hasOneUse()) {
1215 } else if (N1.getOpcode() == ISD::SHL &&
1216 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
1220 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
1221 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
1224 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1225 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1226 isa<ConstantSDNode>(N0.getOperand(1))) {
1227 return DAG.getNode(ISD::ADD, VT,
1228 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
1229 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
1233 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
1240 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
1241 SDOperand N0 = N->getOperand(0);
1242 SDOperand N1 = N->getOperand(1);
1243 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1244 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1245 MVT VT = N->getValueType(0);
1248 if (VT.isVector()) {
1249 SDOperand FoldedVOp = SimplifyVBinOp(N);
1250 if (FoldedVOp.Val) return FoldedVOp;
1253 // fold (sdiv c1, c2) -> c1/c2
1254 if (N0C && N1C && !N1C->isNullValue())
1255 return DAG.getNode(ISD::SDIV, VT, N0, N1);
1256 // fold (sdiv X, 1) -> X
1257 if (N1C && N1C->getSignExtended() == 1LL)
1259 // fold (sdiv X, -1) -> 0-X
1260 if (N1C && N1C->isAllOnesValue())
1261 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1262 // If we know the sign bits of both operands are zero, strength reduce to a
1263 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1264 if (!VT.isVector()) {
1265 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1266 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
1268 // fold (sdiv X, pow2) -> simple ops after legalize
1269 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1270 (isPowerOf2_64(N1C->getSignExtended()) ||
1271 isPowerOf2_64(-N1C->getSignExtended()))) {
1272 // If dividing by powers of two is cheap, then don't perform the following
1274 if (TLI.isPow2DivCheap())
1276 int64_t pow2 = N1C->getSignExtended();
1277 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1278 unsigned lg2 = Log2_64(abs2);
1279 // Splat the sign bit into the register
1280 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
1281 DAG.getConstant(VT.getSizeInBits()-1,
1282 TLI.getShiftAmountTy()));
1283 AddToWorkList(SGN.Val);
1284 // Add (N0 < 0) ? abs2 - 1 : 0;
1285 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
1286 DAG.getConstant(VT.getSizeInBits()-lg2,
1287 TLI.getShiftAmountTy()));
1288 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
1289 AddToWorkList(SRL.Val);
1290 AddToWorkList(ADD.Val); // Divide by pow2
1291 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
1292 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
1293 // If we're dividing by a positive value, we're done. Otherwise, we must
1294 // negate the result.
1297 AddToWorkList(SRA.Val);
1298 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
1300 // if integer divide is expensive and we satisfy the requirements, emit an
1301 // alternate sequence.
1302 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
1303 !TLI.isIntDivCheap()) {
1304 SDOperand Op = BuildSDIV(N);
1305 if (Op.Val) return Op;
1309 if (N0.getOpcode() == ISD::UNDEF)
1310 return DAG.getConstant(0, VT);
1311 // X / undef -> undef
1312 if (N1.getOpcode() == ISD::UNDEF)
1318 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
1319 SDOperand N0 = N->getOperand(0);
1320 SDOperand N1 = N->getOperand(1);
1321 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1322 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1323 MVT VT = N->getValueType(0);
1326 if (VT.isVector()) {
1327 SDOperand FoldedVOp = SimplifyVBinOp(N);
1328 if (FoldedVOp.Val) return FoldedVOp;
1331 // fold (udiv c1, c2) -> c1/c2
1332 if (N0C && N1C && !N1C->isNullValue())
1333 return DAG.getNode(ISD::UDIV, VT, N0, N1);
1334 // fold (udiv x, (1 << c)) -> x >>u c
1335 if (N1C && N1C->getAPIntValue().isPowerOf2())
1336 return DAG.getNode(ISD::SRL, VT, N0,
1337 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1338 TLI.getShiftAmountTy()));
1339 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1340 if (N1.getOpcode() == ISD::SHL) {
1341 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1342 if (SHC->getAPIntValue().isPowerOf2()) {
1343 MVT ADDVT = N1.getOperand(1).getValueType();
1344 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
1345 DAG.getConstant(SHC->getAPIntValue()
1348 AddToWorkList(Add.Val);
1349 return DAG.getNode(ISD::SRL, VT, N0, Add);
1353 // fold (udiv x, c) -> alternate
1354 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1355 SDOperand Op = BuildUDIV(N);
1356 if (Op.Val) return Op;
1360 if (N0.getOpcode() == ISD::UNDEF)
1361 return DAG.getConstant(0, VT);
1362 // X / undef -> undef
1363 if (N1.getOpcode() == ISD::UNDEF)
1369 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1370 SDOperand N0 = N->getOperand(0);
1371 SDOperand N1 = N->getOperand(1);
1372 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1373 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1374 MVT VT = N->getValueType(0);
1376 // fold (srem c1, c2) -> c1%c2
1377 if (N0C && N1C && !N1C->isNullValue())
1378 return DAG.getNode(ISD::SREM, VT, N0, N1);
1379 // If we know the sign bits of both operands are zero, strength reduce to a
1380 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1381 if (!VT.isVector()) {
1382 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1383 return DAG.getNode(ISD::UREM, VT, N0, N1);
1386 // If X/C can be simplified by the division-by-constant logic, lower
1387 // X%C to the equivalent of X-X/C*C.
1388 if (N1C && !N1C->isNullValue()) {
1389 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1390 AddToWorkList(Div.Val);
1391 SDOperand OptimizedDiv = combine(Div.Val);
1392 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
1393 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
1394 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1395 AddToWorkList(Mul.Val);
1401 if (N0.getOpcode() == ISD::UNDEF)
1402 return DAG.getConstant(0, VT);
1403 // X % undef -> undef
1404 if (N1.getOpcode() == ISD::UNDEF)
1410 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1411 SDOperand N0 = N->getOperand(0);
1412 SDOperand N1 = N->getOperand(1);
1413 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1414 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1415 MVT VT = N->getValueType(0);
1417 // fold (urem c1, c2) -> c1%c2
1418 if (N0C && N1C && !N1C->isNullValue())
1419 return DAG.getNode(ISD::UREM, VT, N0, N1);
1420 // fold (urem x, pow2) -> (and x, pow2-1)
1421 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1422 return DAG.getNode(ISD::AND, VT, N0,
1423 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1424 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1425 if (N1.getOpcode() == ISD::SHL) {
1426 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1427 if (SHC->getAPIntValue().isPowerOf2()) {
1429 DAG.getNode(ISD::ADD, VT, N1,
1430 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1432 AddToWorkList(Add.Val);
1433 return DAG.getNode(ISD::AND, VT, N0, Add);
1438 // If X/C can be simplified by the division-by-constant logic, lower
1439 // X%C to the equivalent of X-X/C*C.
1440 if (N1C && !N1C->isNullValue()) {
1441 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1442 SDOperand OptimizedDiv = combine(Div.Val);
1443 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
1444 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
1445 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1446 AddToWorkList(Mul.Val);
1452 if (N0.getOpcode() == ISD::UNDEF)
1453 return DAG.getConstant(0, VT);
1454 // X % undef -> undef
1455 if (N1.getOpcode() == ISD::UNDEF)
1461 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1462 SDOperand N0 = N->getOperand(0);
1463 SDOperand N1 = N->getOperand(1);
1464 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1465 MVT VT = N->getValueType(0);
1467 // fold (mulhs x, 0) -> 0
1468 if (N1C && N1C->isNullValue())
1470 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1471 if (N1C && N1C->getAPIntValue() == 1)
1472 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1473 DAG.getConstant(N0.getValueType().getSizeInBits()-1,
1474 TLI.getShiftAmountTy()));
1475 // fold (mulhs x, undef) -> 0
1476 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1477 return DAG.getConstant(0, VT);
1482 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1483 SDOperand N0 = N->getOperand(0);
1484 SDOperand N1 = N->getOperand(1);
1485 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1486 MVT VT = N->getValueType(0);
1488 // fold (mulhu x, 0) -> 0
1489 if (N1C && N1C->isNullValue())
1491 // fold (mulhu x, 1) -> 0
1492 if (N1C && N1C->getAPIntValue() == 1)
1493 return DAG.getConstant(0, N0.getValueType());
1494 // fold (mulhu x, undef) -> 0
1495 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1496 return DAG.getConstant(0, VT);
1501 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1502 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1503 /// that are being performed. Return true if a simplification was made.
1505 SDOperand DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1507 // If the high half is not needed, just compute the low half.
1508 bool HiExists = N->hasAnyUseOfValue(1);
1511 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1512 SDOperand Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(),
1513 N->getNumOperands());
1514 return CombineTo(N, Res, Res);
1517 // If the low half is not needed, just compute the high half.
1518 bool LoExists = N->hasAnyUseOfValue(0);
1521 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1522 SDOperand Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(),
1523 N->getNumOperands());
1524 return CombineTo(N, Res, Res);
1527 // If both halves are used, return as it is.
1528 if (LoExists && HiExists)
1531 // If the two computed results can be simplified separately, separate them.
1533 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0),
1534 N->op_begin(), N->getNumOperands());
1535 AddToWorkList(Lo.Val);
1536 SDOperand LoOpt = combine(Lo.Val);
1537 if (LoOpt.Val && LoOpt.Val != Lo.Val &&
1538 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))
1539 return CombineTo(N, LoOpt, LoOpt);
1543 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1),
1544 N->op_begin(), N->getNumOperands());
1545 AddToWorkList(Hi.Val);
1546 SDOperand HiOpt = combine(Hi.Val);
1547 if (HiOpt.Val && HiOpt != Hi &&
1548 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))
1549 return CombineTo(N, HiOpt, HiOpt);
1554 SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1555 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1556 if (Res.Val) return Res;
1561 SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1562 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
1563 if (Res.Val) return Res;
1568 SDOperand DAGCombiner::visitSDIVREM(SDNode *N) {
1569 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
1570 if (Res.Val) return Res;
1575 SDOperand DAGCombiner::visitUDIVREM(SDNode *N) {
1576 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
1577 if (Res.Val) return Res;
1582 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1583 /// two operands of the same opcode, try to simplify it.
1584 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1585 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1586 MVT VT = N0.getValueType();
1587 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1589 // For each of OP in AND/OR/XOR:
1590 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1591 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1592 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1593 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1594 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1595 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1596 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1597 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1598 N0.getOperand(0).getValueType(),
1599 N0.getOperand(0), N1.getOperand(0));
1600 AddToWorkList(ORNode.Val);
1601 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1604 // For each of OP in SHL/SRL/SRA/AND...
1605 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1606 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1607 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1608 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1609 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1610 N0.getOperand(1) == N1.getOperand(1)) {
1611 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1612 N0.getOperand(0).getValueType(),
1613 N0.getOperand(0), N1.getOperand(0));
1614 AddToWorkList(ORNode.Val);
1615 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1621 SDOperand DAGCombiner::visitAND(SDNode *N) {
1622 SDOperand N0 = N->getOperand(0);
1623 SDOperand N1 = N->getOperand(1);
1624 SDOperand LL, LR, RL, RR, CC0, CC1;
1625 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1626 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1627 MVT VT = N1.getValueType();
1628 unsigned BitWidth = VT.getSizeInBits();
1631 if (VT.isVector()) {
1632 SDOperand FoldedVOp = SimplifyVBinOp(N);
1633 if (FoldedVOp.Val) return FoldedVOp;
1636 // fold (and x, undef) -> 0
1637 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1638 return DAG.getConstant(0, VT);
1639 // fold (and c1, c2) -> c1&c2
1641 return DAG.getNode(ISD::AND, VT, N0, N1);
1642 // canonicalize constant to RHS
1644 return DAG.getNode(ISD::AND, VT, N1, N0);
1645 // fold (and x, -1) -> x
1646 if (N1C && N1C->isAllOnesValue())
1648 // if (and x, c) is known to be zero, return 0
1649 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0),
1650 APInt::getAllOnesValue(BitWidth)))
1651 return DAG.getConstant(0, VT);
1653 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1656 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1657 if (N1C && N0.getOpcode() == ISD::OR)
1658 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1659 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
1661 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1662 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1663 SDOperand N0Op0 = N0.getOperand(0);
1664 APInt Mask = ~N1C->getAPIntValue();
1665 Mask.trunc(N0Op0.getValueSizeInBits());
1666 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
1667 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1670 // Replace uses of the AND with uses of the Zero extend node.
1673 // We actually want to replace all uses of the any_extend with the
1674 // zero_extend, to avoid duplicating things. This will later cause this
1675 // AND to be folded.
1676 CombineTo(N0.Val, Zext);
1677 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1680 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1681 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1682 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1683 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1685 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1686 LL.getValueType().isInteger()) {
1687 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1688 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
1689 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1690 AddToWorkList(ORNode.Val);
1691 return DAG.getSetCC(VT, ORNode, LR, Op1);
1693 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1694 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1695 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1696 AddToWorkList(ANDNode.Val);
1697 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1699 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1700 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1701 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1702 AddToWorkList(ORNode.Val);
1703 return DAG.getSetCC(VT, ORNode, LR, Op1);
1706 // canonicalize equivalent to ll == rl
1707 if (LL == RR && LR == RL) {
1708 Op1 = ISD::getSetCCSwappedOperands(Op1);
1711 if (LL == RL && LR == RR) {
1712 bool isInteger = LL.getValueType().isInteger();
1713 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1714 if (Result != ISD::SETCC_INVALID)
1715 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1719 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1720 if (N0.getOpcode() == N1.getOpcode()) {
1721 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1722 if (Tmp.Val) return Tmp;
1725 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1726 // fold (and (sra)) -> (and (srl)) when possible.
1727 if (!VT.isVector() &&
1728 SimplifyDemandedBits(SDOperand(N, 0)))
1729 return SDOperand(N, 0);
1730 // fold (zext_inreg (extload x)) -> (zextload x)
1731 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
1732 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1733 MVT EVT = LN0->getMemoryVT();
1734 // If we zero all the possible extended bits, then we can turn this into
1735 // a zextload if we are running before legalize or the operation is legal.
1736 unsigned BitWidth = N1.getValueSizeInBits();
1737 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1738 BitWidth - EVT.getSizeInBits())) &&
1739 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1740 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1741 LN0->getBasePtr(), LN0->getSrcValue(),
1742 LN0->getSrcValueOffset(), EVT,
1744 LN0->getAlignment());
1746 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1747 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1750 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1751 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
1753 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1754 MVT EVT = LN0->getMemoryVT();
1755 // If we zero all the possible extended bits, then we can turn this into
1756 // a zextload if we are running before legalize or the operation is legal.
1757 unsigned BitWidth = N1.getValueSizeInBits();
1758 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1759 BitWidth - EVT.getSizeInBits())) &&
1760 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1761 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1762 LN0->getBasePtr(), LN0->getSrcValue(),
1763 LN0->getSrcValueOffset(), EVT,
1765 LN0->getAlignment());
1767 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1768 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1772 // fold (and (load x), 255) -> (zextload x, i8)
1773 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1774 if (N1C && N0.getOpcode() == ISD::LOAD) {
1775 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1776 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1777 LN0->isUnindexed() && N0.hasOneUse()) {
1778 MVT EVT = MVT::Other;
1779 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
1780 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
1781 EVT = MVT::getIntegerVT(ActiveBits);
1783 MVT LoadedVT = LN0->getMemoryVT();
1784 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) &&
1785 // Loading a non-byte sized integer is only valid if the extra bits
1786 // in memory that complete the byte are zero, which is not known here.
1787 // TODO: remove isSimple check when apint codegen support lands.
1788 EVT.isSimple() && EVT.isByteSized() &&
1789 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1790 MVT PtrType = N0.getOperand(1).getValueType();
1791 // For big endian targets, we need to add an offset to the pointer to
1792 // load the correct bytes. For little endian systems, we merely need to
1793 // read fewer bytes from the same pointer.
1794 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8;
1795 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8;
1796 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
1797 unsigned Alignment = LN0->getAlignment();
1798 SDOperand NewPtr = LN0->getBasePtr();
1799 if (TLI.isBigEndian()) {
1800 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1801 DAG.getConstant(PtrOff, PtrType));
1802 Alignment = MinAlign(Alignment, PtrOff);
1804 AddToWorkList(NewPtr.Val);
1806 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1807 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
1808 LN0->isVolatile(), Alignment);
1810 CombineTo(N0.Val, Load, Load.getValue(1));
1811 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1819 SDOperand DAGCombiner::visitOR(SDNode *N) {
1820 SDOperand N0 = N->getOperand(0);
1821 SDOperand N1 = N->getOperand(1);
1822 SDOperand LL, LR, RL, RR, CC0, CC1;
1823 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1824 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1825 MVT VT = N1.getValueType();
1828 if (VT.isVector()) {
1829 SDOperand FoldedVOp = SimplifyVBinOp(N);
1830 if (FoldedVOp.Val) return FoldedVOp;
1833 // fold (or x, undef) -> -1
1834 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1835 return DAG.getConstant(~0ULL, VT);
1836 // fold (or c1, c2) -> c1|c2
1838 return DAG.getNode(ISD::OR, VT, N0, N1);
1839 // canonicalize constant to RHS
1841 return DAG.getNode(ISD::OR, VT, N1, N0);
1842 // fold (or x, 0) -> x
1843 if (N1C && N1C->isNullValue())
1845 // fold (or x, -1) -> -1
1846 if (N1C && N1C->isAllOnesValue())
1848 // fold (or x, c) -> c iff (x & ~c) == 0
1849 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
1852 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1855 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1856 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1857 isa<ConstantSDNode>(N0.getOperand(1))) {
1858 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1859 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1861 DAG.getConstant(N1C->getAPIntValue() |
1862 C1->getAPIntValue(), VT));
1864 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1865 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1866 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1867 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1869 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1870 LL.getValueType().isInteger()) {
1871 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1872 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1873 if (cast<ConstantSDNode>(LR)->isNullValue() &&
1874 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1875 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1876 AddToWorkList(ORNode.Val);
1877 return DAG.getSetCC(VT, ORNode, LR, Op1);
1879 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1880 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1881 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1882 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1883 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1884 AddToWorkList(ANDNode.Val);
1885 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1888 // canonicalize equivalent to ll == rl
1889 if (LL == RR && LR == RL) {
1890 Op1 = ISD::getSetCCSwappedOperands(Op1);
1893 if (LL == RL && LR == RR) {
1894 bool isInteger = LL.getValueType().isInteger();
1895 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1896 if (Result != ISD::SETCC_INVALID)
1897 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1901 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1902 if (N0.getOpcode() == N1.getOpcode()) {
1903 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1904 if (Tmp.Val) return Tmp;
1907 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1908 if (N0.getOpcode() == ISD::AND &&
1909 N1.getOpcode() == ISD::AND &&
1910 N0.getOperand(1).getOpcode() == ISD::Constant &&
1911 N1.getOperand(1).getOpcode() == ISD::Constant &&
1912 // Don't increase # computations.
1913 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1914 // We can only do this xform if we know that bits from X that are set in C2
1915 // but not in C1 are already zero. Likewise for Y.
1916 const APInt &LHSMask =
1917 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1918 const APInt &RHSMask =
1919 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
1921 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1922 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1923 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1924 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1929 // See if this is some rotate idiom.
1930 if (SDNode *Rot = MatchRotate(N0, N1))
1931 return SDOperand(Rot, 0);
1937 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1938 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1939 if (Op.getOpcode() == ISD::AND) {
1940 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1941 Mask = Op.getOperand(1);
1942 Op = Op.getOperand(0);
1948 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1956 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1957 // idioms for rotate, and if the target supports rotation instructions, generate
1959 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1960 // Must be a legal type. Expanded an promoted things won't work with rotates.
1961 MVT VT = LHS.getValueType();
1962 if (!TLI.isTypeLegal(VT)) return 0;
1964 // The target must have at least one rotate flavor.
1965 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1966 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1967 if (!HasROTL && !HasROTR) return 0;
1969 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1970 SDOperand LHSShift; // The shift.
1971 SDOperand LHSMask; // AND value if any.
1972 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1973 return 0; // Not part of a rotate.
1975 SDOperand RHSShift; // The shift.
1976 SDOperand RHSMask; // AND value if any.
1977 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1978 return 0; // Not part of a rotate.
1980 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1981 return 0; // Not shifting the same value.
1983 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1984 return 0; // Shifts must disagree.
1986 // Canonicalize shl to left side in a shl/srl pair.
1987 if (RHSShift.getOpcode() == ISD::SHL) {
1988 std::swap(LHS, RHS);
1989 std::swap(LHSShift, RHSShift);
1990 std::swap(LHSMask , RHSMask );
1993 unsigned OpSizeInBits = VT.getSizeInBits();
1994 SDOperand LHSShiftArg = LHSShift.getOperand(0);
1995 SDOperand LHSShiftAmt = LHSShift.getOperand(1);
1996 SDOperand RHSShiftAmt = RHSShift.getOperand(1);
1998 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1999 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2000 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2001 RHSShiftAmt.getOpcode() == ISD::Constant) {
2002 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
2003 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
2004 if ((LShVal + RShVal) != OpSizeInBits)
2009 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
2011 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
2013 // If there is an AND of either shifted operand, apply it to the result.
2014 if (LHSMask.Val || RHSMask.Val) {
2015 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2018 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2019 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2022 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2023 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2026 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
2032 // If there is a mask here, and we have a variable shift, we can't be sure
2033 // that we're masking out the right stuff.
2034 if (LHSMask.Val || RHSMask.Val)
2037 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2038 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2039 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2040 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2041 if (ConstantSDNode *SUBC =
2042 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2043 if (SUBC->getAPIntValue() == OpSizeInBits) {
2045 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2047 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
2052 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2053 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2054 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2055 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2056 if (ConstantSDNode *SUBC =
2057 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2058 if (SUBC->getAPIntValue() == OpSizeInBits) {
2060 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2062 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
2067 // Look for sign/zext/any-extended cases:
2068 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2069 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2070 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
2071 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2072 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2073 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
2074 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
2075 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
2076 if (RExtOp0.getOpcode() == ISD::SUB &&
2077 RExtOp0.getOperand(1) == LExtOp0) {
2078 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2080 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2081 // (rotl x, (sub 32, y))
2082 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2083 if (SUBC->getAPIntValue() == OpSizeInBits) {
2085 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2087 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
2090 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2091 RExtOp0 == LExtOp0.getOperand(1)) {
2092 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2094 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2095 // (rotr x, (sub 32, y))
2096 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2097 if (SUBC->getAPIntValue() == OpSizeInBits) {
2099 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
2101 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2111 SDOperand DAGCombiner::visitXOR(SDNode *N) {
2112 SDOperand N0 = N->getOperand(0);
2113 SDOperand N1 = N->getOperand(1);
2114 SDOperand LHS, RHS, CC;
2115 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2116 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2117 MVT VT = N0.getValueType();
2120 if (VT.isVector()) {
2121 SDOperand FoldedVOp = SimplifyVBinOp(N);
2122 if (FoldedVOp.Val) return FoldedVOp;
2125 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2126 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2127 return DAG.getConstant(0, VT);
2128 // fold (xor x, undef) -> undef
2129 if (N0.getOpcode() == ISD::UNDEF)
2131 if (N1.getOpcode() == ISD::UNDEF)
2133 // fold (xor c1, c2) -> c1^c2
2135 return DAG.getNode(ISD::XOR, VT, N0, N1);
2136 // canonicalize constant to RHS
2138 return DAG.getNode(ISD::XOR, VT, N1, N0);
2139 // fold (xor x, 0) -> x
2140 if (N1C && N1C->isNullValue())
2143 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
2146 // fold !(x cc y) -> (x !cc y)
2147 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2148 bool isInt = LHS.getValueType().isInteger();
2149 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2151 if (N0.getOpcode() == ISD::SETCC)
2152 return DAG.getSetCC(VT, LHS, RHS, NotCC);
2153 if (N0.getOpcode() == ISD::SELECT_CC)
2154 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
2155 assert(0 && "Unhandled SetCC Equivalent!");
2158 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2159 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2160 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2161 SDOperand V = N0.getOperand(0);
2162 V = DAG.getNode(ISD::XOR, V.getValueType(), V,
2163 DAG.getConstant(1, V.getValueType()));
2164 AddToWorkList(V.Val);
2165 return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
2168 // fold !(x or y) -> (!x and !y) iff x or y are setcc
2169 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2170 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2171 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2172 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2173 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2174 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2175 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2176 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2177 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2180 // fold !(x or y) -> (!x and !y) iff x or y are constants
2181 if (N1C && N1C->isAllOnesValue() &&
2182 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2183 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2184 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2185 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2186 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2187 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2188 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2189 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2192 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
2193 if (N1C && N0.getOpcode() == ISD::XOR) {
2194 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2195 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2197 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
2198 DAG.getConstant(N1C->getAPIntValue()^
2199 N00C->getAPIntValue(), VT));
2201 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
2202 DAG.getConstant(N1C->getAPIntValue()^
2203 N01C->getAPIntValue(), VT));
2205 // fold (xor x, x) -> 0
2207 if (!VT.isVector()) {
2208 return DAG.getConstant(0, VT);
2209 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
2210 // Produce a vector of zeros.
2211 SDOperand El = DAG.getConstant(0, VT.getVectorElementType());
2212 std::vector<SDOperand> Ops(VT.getVectorNumElements(), El);
2213 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2217 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2218 if (N0.getOpcode() == N1.getOpcode()) {
2219 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2220 if (Tmp.Val) return Tmp;
2223 // Simplify the expression using non-local knowledge.
2224 if (!VT.isVector() &&
2225 SimplifyDemandedBits(SDOperand(N, 0)))
2226 return SDOperand(N, 0);
2231 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2232 /// the shift amount is a constant.
2233 SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2234 SDNode *LHS = N->getOperand(0).Val;
2235 if (!LHS->hasOneUse()) return SDOperand();
2237 // We want to pull some binops through shifts, so that we have (and (shift))
2238 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2239 // thing happens with address calculations, so it's important to canonicalize
2241 bool HighBitSet = false; // Can we transform this if the high bit is set?
2243 switch (LHS->getOpcode()) {
2244 default: return SDOperand();
2247 HighBitSet = false; // We can only transform sra if the high bit is clear.
2250 HighBitSet = true; // We can only transform sra if the high bit is set.
2253 if (N->getOpcode() != ISD::SHL)
2254 return SDOperand(); // only shl(add) not sr[al](add).
2255 HighBitSet = false; // We can only transform sra if the high bit is clear.
2259 // We require the RHS of the binop to be a constant as well.
2260 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2261 if (!BinOpCst) return SDOperand();
2264 // FIXME: disable this for unless the input to the binop is a shift by a
2265 // constant. If it is not a shift, it pessimizes some common cases like:
2267 //void foo(int *X, int i) { X[i & 1235] = 1; }
2268 //int bar(int *X, int i) { return X[i & 255]; }
2269 SDNode *BinOpLHSVal = LHS->getOperand(0).Val;
2270 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2271 BinOpLHSVal->getOpcode() != ISD::SRA &&
2272 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2273 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2276 MVT VT = N->getValueType(0);
2278 // If this is a signed shift right, and the high bit is modified
2279 // by the logical operation, do not perform the transformation.
2280 // The highBitSet boolean indicates the value of the high bit of
2281 // the constant which would cause it to be modified for this
2283 if (N->getOpcode() == ISD::SRA) {
2284 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2285 if (BinOpRHSSignSet != HighBitSet)
2289 // Fold the constants, shifting the binop RHS by the shift amount.
2290 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0),
2291 LHS->getOperand(1), N->getOperand(1));
2293 // Create the new shift.
2294 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0),
2297 // Create the new binop.
2298 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS);
2302 SDOperand DAGCombiner::visitSHL(SDNode *N) {
2303 SDOperand N0 = N->getOperand(0);
2304 SDOperand N1 = N->getOperand(1);
2305 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2306 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2307 MVT VT = N0.getValueType();
2308 unsigned OpSizeInBits = VT.getSizeInBits();
2310 // fold (shl c1, c2) -> c1<<c2
2312 return DAG.getNode(ISD::SHL, VT, N0, N1);
2313 // fold (shl 0, x) -> 0
2314 if (N0C && N0C->isNullValue())
2316 // fold (shl x, c >= size(x)) -> undef
2317 if (N1C && N1C->getValue() >= OpSizeInBits)
2318 return DAG.getNode(ISD::UNDEF, VT);
2319 // fold (shl x, 0) -> x
2320 if (N1C && N1C->isNullValue())
2322 // if (shl x, c) is known to be zero, return 0
2323 if (DAG.MaskedValueIsZero(SDOperand(N, 0),
2324 APInt::getAllOnesValue(VT.getSizeInBits())))
2325 return DAG.getConstant(0, VT);
2326 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2327 return SDOperand(N, 0);
2328 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
2329 if (N1C && N0.getOpcode() == ISD::SHL &&
2330 N0.getOperand(1).getOpcode() == ISD::Constant) {
2331 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2332 uint64_t c2 = N1C->getValue();
2333 if (c1 + c2 > OpSizeInBits)
2334 return DAG.getConstant(0, VT);
2335 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
2336 DAG.getConstant(c1 + c2, N1.getValueType()));
2338 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
2339 // (srl (and x, -1 << c1), c1-c2)
2340 if (N1C && N0.getOpcode() == ISD::SRL &&
2341 N0.getOperand(1).getOpcode() == ISD::Constant) {
2342 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2343 uint64_t c2 = N1C->getValue();
2344 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2345 DAG.getConstant(~0ULL << c1, VT));
2347 return DAG.getNode(ISD::SHL, VT, Mask,
2348 DAG.getConstant(c2-c1, N1.getValueType()));
2350 return DAG.getNode(ISD::SRL, VT, Mask,
2351 DAG.getConstant(c1-c2, N1.getValueType()));
2353 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
2354 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2355 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2356 DAG.getConstant(~0ULL << N1C->getValue(), VT));
2358 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2361 SDOperand DAGCombiner::visitSRA(SDNode *N) {
2362 SDOperand N0 = N->getOperand(0);
2363 SDOperand N1 = N->getOperand(1);
2364 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2365 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2366 MVT VT = N0.getValueType();
2368 // fold (sra c1, c2) -> c1>>c2
2370 return DAG.getNode(ISD::SRA, VT, N0, N1);
2371 // fold (sra 0, x) -> 0
2372 if (N0C && N0C->isNullValue())
2374 // fold (sra -1, x) -> -1
2375 if (N0C && N0C->isAllOnesValue())
2377 // fold (sra x, c >= size(x)) -> undef
2378 if (N1C && N1C->getValue() >= VT.getSizeInBits())
2379 return DAG.getNode(ISD::UNDEF, VT);
2380 // fold (sra x, 0) -> x
2381 if (N1C && N1C->isNullValue())
2383 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2385 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2386 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getValue();
2387 MVT EVT = MVT::getIntegerVT(LowBits);
2388 // TODO: turn on when apint codegen support lands.
2389 // if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
2390 if (EVT.isSimple() && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
2391 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
2392 DAG.getValueType(EVT));
2395 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
2396 if (N1C && N0.getOpcode() == ISD::SRA) {
2397 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2398 unsigned Sum = N1C->getValue() + C1->getValue();
2399 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1;
2400 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
2401 DAG.getConstant(Sum, N1C->getValueType(0)));
2405 // fold sra (shl X, m), result_size - n
2406 // -> (sign_extend (trunc (shl X, result_size - n - m))) for
2407 // result_size - n != m.
2408 // If truncate is free for the target sext(shl) is likely to result in better
2410 if (N0.getOpcode() == ISD::SHL) {
2411 // Get the two constanst of the shifts, CN0 = m, CN = n.
2412 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2414 // Determine what the truncate's result bitsize and type would be.
2415 unsigned VTValSize = VT.getSizeInBits();
2417 MVT::getIntegerVT(VTValSize - N1C->getValue());
2418 // Determine the residual right-shift amount.
2419 unsigned ShiftAmt = N1C->getValue() - N01C->getValue();
2421 // If the shift is not a no-op (in which case this should be just a sign
2422 // extend already), the truncated to type is legal, sign_extend is legal
2423 // on that type, and the the truncate to that type is both legal and free,
2424 // perform the transform.
2426 TLI.isTypeLegal(TruncVT) &&
2427 TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) &&
2428 TLI.isOperationLegal(ISD::TRUNCATE, VT) &&
2429 TLI.isTruncateFree(VT, TruncVT)) {
2431 SDOperand Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy());
2432 SDOperand Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt);
2433 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift);
2434 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc);
2439 // Simplify, based on bits shifted out of the LHS.
2440 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2441 return SDOperand(N, 0);
2444 // If the sign bit is known to be zero, switch this to a SRL.
2445 if (DAG.SignBitIsZero(N0))
2446 return DAG.getNode(ISD::SRL, VT, N0, N1);
2448 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2451 SDOperand DAGCombiner::visitSRL(SDNode *N) {
2452 SDOperand N0 = N->getOperand(0);
2453 SDOperand N1 = N->getOperand(1);
2454 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2455 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2456 MVT VT = N0.getValueType();
2457 unsigned OpSizeInBits = VT.getSizeInBits();
2459 // fold (srl c1, c2) -> c1 >>u c2
2461 return DAG.getNode(ISD::SRL, VT, N0, N1);
2462 // fold (srl 0, x) -> 0
2463 if (N0C && N0C->isNullValue())
2465 // fold (srl x, c >= size(x)) -> undef
2466 if (N1C && N1C->getValue() >= OpSizeInBits)
2467 return DAG.getNode(ISD::UNDEF, VT);
2468 // fold (srl x, 0) -> x
2469 if (N1C && N1C->isNullValue())
2471 // if (srl x, c) is known to be zero, return 0
2472 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0),
2473 APInt::getAllOnesValue(OpSizeInBits)))
2474 return DAG.getConstant(0, VT);
2476 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
2477 if (N1C && N0.getOpcode() == ISD::SRL &&
2478 N0.getOperand(1).getOpcode() == ISD::Constant) {
2479 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2480 uint64_t c2 = N1C->getValue();
2481 if (c1 + c2 > OpSizeInBits)
2482 return DAG.getConstant(0, VT);
2483 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
2484 DAG.getConstant(c1 + c2, N1.getValueType()));
2487 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2488 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2489 // Shifting in all undef bits?
2490 MVT SmallVT = N0.getOperand(0).getValueType();
2491 if (N1C->getValue() >= SmallVT.getSizeInBits())
2492 return DAG.getNode(ISD::UNDEF, VT);
2494 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
2495 AddToWorkList(SmallShift.Val);
2496 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
2499 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2500 // bit, which is unmodified by sra.
2501 if (N1C && N1C->getValue()+1 == VT.getSizeInBits()) {
2502 if (N0.getOpcode() == ISD::SRA)
2503 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
2506 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2507 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2508 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
2509 APInt KnownZero, KnownOne;
2510 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
2511 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2513 // If any of the input bits are KnownOne, then the input couldn't be all
2514 // zeros, thus the result of the srl will always be zero.
2515 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
2517 // If all of the bits input the to ctlz node are known to be zero, then
2518 // the result of the ctlz is "32" and the result of the shift is one.
2519 APInt UnknownBits = ~KnownZero & Mask;
2520 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2522 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2523 if ((UnknownBits & (UnknownBits-1)) == 0) {
2524 // Okay, we know that only that the single bit specified by UnknownBits
2525 // could be set on input to the CTLZ node. If this bit is set, the SRL
2526 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2527 // to an SRL,XOR pair, which is likely to simplify more.
2528 unsigned ShAmt = UnknownBits.countTrailingZeros();
2529 SDOperand Op = N0.getOperand(0);
2531 Op = DAG.getNode(ISD::SRL, VT, Op,
2532 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
2533 AddToWorkList(Op.Val);
2535 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
2539 // fold operands of srl based on knowledge that the low bits are not
2541 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2542 return SDOperand(N, 0);
2544 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2547 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
2548 SDOperand N0 = N->getOperand(0);
2549 MVT VT = N->getValueType(0);
2551 // fold (ctlz c1) -> c2
2552 if (isa<ConstantSDNode>(N0))
2553 return DAG.getNode(ISD::CTLZ, VT, N0);
2557 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
2558 SDOperand N0 = N->getOperand(0);
2559 MVT VT = N->getValueType(0);
2561 // fold (cttz c1) -> c2
2562 if (isa<ConstantSDNode>(N0))
2563 return DAG.getNode(ISD::CTTZ, VT, N0);
2567 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
2568 SDOperand N0 = N->getOperand(0);
2569 MVT VT = N->getValueType(0);
2571 // fold (ctpop c1) -> c2
2572 if (isa<ConstantSDNode>(N0))
2573 return DAG.getNode(ISD::CTPOP, VT, N0);
2577 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
2578 SDOperand N0 = N->getOperand(0);
2579 SDOperand N1 = N->getOperand(1);
2580 SDOperand N2 = N->getOperand(2);
2581 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2582 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2583 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2584 MVT VT = N->getValueType(0);
2585 MVT VT0 = N0.getValueType();
2587 // fold select C, X, X -> X
2590 // fold select true, X, Y -> X
2591 if (N0C && !N0C->isNullValue())
2593 // fold select false, X, Y -> Y
2594 if (N0C && N0C->isNullValue())
2596 // fold select C, 1, X -> C | X
2597 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
2598 return DAG.getNode(ISD::OR, VT, N0, N2);
2599 // fold select C, 0, 1 -> ~C
2600 if (VT.isInteger() && VT0.isInteger() &&
2601 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
2602 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
2605 AddToWorkList(XORNode.Val);
2607 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
2608 return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
2610 // fold select C, 0, X -> ~C & X
2611 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2612 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2613 AddToWorkList(XORNode.Val);
2614 return DAG.getNode(ISD::AND, VT, XORNode, N2);
2616 // fold select C, X, 1 -> ~C | X
2617 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
2618 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2619 AddToWorkList(XORNode.Val);
2620 return DAG.getNode(ISD::OR, VT, XORNode, N1);
2622 // fold select C, X, 0 -> C & X
2623 // FIXME: this should check for C type == X type, not i1?
2624 if (VT == MVT::i1 && N2C && N2C->isNullValue())
2625 return DAG.getNode(ISD::AND, VT, N0, N1);
2626 // fold X ? X : Y --> X ? 1 : Y --> X | Y
2627 if (VT == MVT::i1 && N0 == N1)
2628 return DAG.getNode(ISD::OR, VT, N0, N2);
2629 // fold X ? Y : X --> X ? Y : 0 --> X & Y
2630 if (VT == MVT::i1 && N0 == N2)
2631 return DAG.getNode(ISD::AND, VT, N0, N1);
2633 // If we can fold this based on the true/false value, do so.
2634 if (SimplifySelectOps(N, N1, N2))
2635 return SDOperand(N, 0); // Don't revisit N.
2637 // fold selects based on a setcc into other things, such as min/max/abs
2638 if (N0.getOpcode() == ISD::SETCC) {
2640 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2641 // having to say they don't support SELECT_CC on every type the DAG knows
2642 // about, since there is no way to mark an opcode illegal at all value types
2643 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
2644 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
2645 N1, N2, N0.getOperand(2));
2647 return SimplifySelect(N0, N1, N2);
2652 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
2653 SDOperand N0 = N->getOperand(0);
2654 SDOperand N1 = N->getOperand(1);
2655 SDOperand N2 = N->getOperand(2);
2656 SDOperand N3 = N->getOperand(3);
2657 SDOperand N4 = N->getOperand(4);
2658 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2660 // fold select_cc lhs, rhs, x, x, cc -> x
2664 // Determine if the condition we're dealing with is constant
2665 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
2666 if (SCC.Val) AddToWorkList(SCC.Val);
2668 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
2669 if (!SCCC->isNullValue())
2670 return N2; // cond always true -> true val
2672 return N3; // cond always false -> false val
2675 // Fold to a simpler select_cc
2676 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2677 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
2678 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2681 // If we can fold this based on the true/false value, do so.
2682 if (SimplifySelectOps(N, N2, N3))
2683 return SDOperand(N, 0); // Don't revisit N.
2685 // fold select_cc into other things, such as min/max/abs
2686 return SimplifySelectCC(N0, N1, N2, N3, CC);
2689 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
2690 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2691 cast<CondCodeSDNode>(N->getOperand(2))->get());
2694 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
2695 // "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))"
2696 // transformation. Returns true if extension are possible and the above
2697 // mentioned transformation is profitable.
2698 static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0,
2700 SmallVector<SDNode*, 4> &ExtendNodes,
2701 TargetLowering &TLI) {
2702 bool HasCopyToRegUses = false;
2703 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
2704 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end();
2706 SDNode *User = UI->getUser();
2709 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
2710 if (User->getOpcode() == ISD::SETCC) {
2711 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
2712 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
2713 // Sign bits will be lost after a zext.
2716 for (unsigned i = 0; i != 2; ++i) {
2717 SDOperand UseOp = User->getOperand(i);
2720 if (!isa<ConstantSDNode>(UseOp))
2725 ExtendNodes.push_back(User);
2727 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2728 SDOperand UseOp = User->getOperand(i);
2730 // If truncate from extended type to original load type is free
2731 // on this target, then it's ok to extend a CopyToReg.
2732 if (isTruncFree && User->getOpcode() == ISD::CopyToReg)
2733 HasCopyToRegUses = true;
2741 if (HasCopyToRegUses) {
2742 bool BothLiveOut = false;
2743 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
2745 SDNode *User = UI->getUser();
2746 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2747 SDOperand UseOp = User->getOperand(i);
2748 if (UseOp.Val == N && UseOp.ResNo == 0) {
2755 // Both unextended and extended values are live out. There had better be
2756 // good a reason for the transformation.
2757 return ExtendNodes.size();
2762 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2763 SDOperand N0 = N->getOperand(0);
2764 MVT VT = N->getValueType(0);
2766 // fold (sext c1) -> c1
2767 if (isa<ConstantSDNode>(N0))
2768 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2770 // fold (sext (sext x)) -> (sext x)
2771 // fold (sext (aext x)) -> (sext x)
2772 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2773 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2775 if (N0.getOpcode() == ISD::TRUNCATE) {
2776 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2777 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2778 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2779 if (NarrowLoad.Val) {
2780 if (NarrowLoad.Val != N0.Val)
2781 CombineTo(N0.Val, NarrowLoad);
2782 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
2785 // See if the value being truncated is already sign extended. If so, just
2786 // eliminate the trunc/sext pair.
2787 SDOperand Op = N0.getOperand(0);
2788 unsigned OpBits = Op.getValueType().getSizeInBits();
2789 unsigned MidBits = N0.getValueType().getSizeInBits();
2790 unsigned DestBits = VT.getSizeInBits();
2791 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2793 if (OpBits == DestBits) {
2794 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2795 // bits, it is already ready.
2796 if (NumSignBits > DestBits-MidBits)
2798 } else if (OpBits < DestBits) {
2799 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2800 // bits, just sext from i32.
2801 if (NumSignBits > OpBits-MidBits)
2802 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2804 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2805 // bits, just truncate to i32.
2806 if (NumSignBits > OpBits-MidBits)
2807 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2810 // fold (sext (truncate x)) -> (sextinreg x).
2811 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2812 N0.getValueType())) {
2813 if (Op.getValueType().bitsLT(VT))
2814 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2815 else if (Op.getValueType().bitsGT(VT))
2816 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2817 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2818 DAG.getValueType(N0.getValueType()));
2822 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2823 if (ISD::isNON_EXTLoad(N0.Val) &&
2824 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2825 bool DoXform = true;
2826 SmallVector<SDNode*, 4> SetCCs;
2827 if (!N0.hasOneUse())
2828 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
2830 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2831 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2832 LN0->getBasePtr(), LN0->getSrcValue(),
2833 LN0->getSrcValueOffset(),
2836 LN0->getAlignment());
2837 CombineTo(N, ExtLoad);
2838 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
2839 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
2840 // Extend SetCC uses if necessary.
2841 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
2842 SDNode *SetCC = SetCCs[i];
2843 SmallVector<SDOperand, 4> Ops;
2844 for (unsigned j = 0; j != 2; ++j) {
2845 SDOperand SOp = SetCC->getOperand(j);
2847 Ops.push_back(ExtLoad);
2849 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp));
2851 Ops.push_back(SetCC->getOperand(2));
2852 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
2853 &Ops[0], Ops.size()));
2855 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2859 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2860 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2861 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2862 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2863 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2864 MVT EVT = LN0->getMemoryVT();
2865 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2866 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2867 LN0->getBasePtr(), LN0->getSrcValue(),
2868 LN0->getSrcValueOffset(), EVT,
2870 LN0->getAlignment());
2871 CombineTo(N, ExtLoad);
2872 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2873 ExtLoad.getValue(1));
2874 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2878 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
2879 if (N0.getOpcode() == ISD::SETCC) {
2881 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2882 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
2883 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2884 if (SCC.Val) return SCC;
2887 // fold (sext x) -> (zext x) if the sign bit is known zero.
2888 if ((!AfterLegalize || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
2889 DAG.SignBitIsZero(N0))
2890 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2895 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2896 SDOperand N0 = N->getOperand(0);
2897 MVT VT = N->getValueType(0);
2899 // fold (zext c1) -> c1
2900 if (isa<ConstantSDNode>(N0))
2901 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2902 // fold (zext (zext x)) -> (zext x)
2903 // fold (zext (aext x)) -> (zext x)
2904 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2905 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2907 // fold (zext (truncate (load x))) -> (zext (smaller load x))
2908 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
2909 if (N0.getOpcode() == ISD::TRUNCATE) {
2910 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2911 if (NarrowLoad.Val) {
2912 if (NarrowLoad.Val != N0.Val)
2913 CombineTo(N0.Val, NarrowLoad);
2914 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
2918 // fold (zext (truncate x)) -> (and x, mask)
2919 if (N0.getOpcode() == ISD::TRUNCATE &&
2920 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2921 SDOperand Op = N0.getOperand(0);
2922 if (Op.getValueType().bitsLT(VT)) {
2923 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2924 } else if (Op.getValueType().bitsGT(VT)) {
2925 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2927 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2930 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2931 if (N0.getOpcode() == ISD::AND &&
2932 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2933 N0.getOperand(1).getOpcode() == ISD::Constant) {
2934 SDOperand X = N0.getOperand(0).getOperand(0);
2935 if (X.getValueType().bitsLT(VT)) {
2936 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2937 } else if (X.getValueType().bitsGT(VT)) {
2938 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2940 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2941 Mask.zext(VT.getSizeInBits());
2942 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2945 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2946 if (ISD::isNON_EXTLoad(N0.Val) &&
2947 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2948 bool DoXform = true;
2949 SmallVector<SDNode*, 4> SetCCs;
2950 if (!N0.hasOneUse())
2951 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
2953 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2954 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2955 LN0->getBasePtr(), LN0->getSrcValue(),
2956 LN0->getSrcValueOffset(),
2959 LN0->getAlignment());
2960 CombineTo(N, ExtLoad);
2961 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
2962 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
2963 // Extend SetCC uses if necessary.
2964 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
2965 SDNode *SetCC = SetCCs[i];
2966 SmallVector<SDOperand, 4> Ops;
2967 for (unsigned j = 0; j != 2; ++j) {
2968 SDOperand SOp = SetCC->getOperand(j);
2970 Ops.push_back(ExtLoad);
2972 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp));
2974 Ops.push_back(SetCC->getOperand(2));
2975 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
2976 &Ops[0], Ops.size()));
2978 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2982 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2983 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2984 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2985 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2986 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2987 MVT EVT = LN0->getMemoryVT();
2988 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2989 LN0->getBasePtr(), LN0->getSrcValue(),
2990 LN0->getSrcValueOffset(), EVT,
2992 LN0->getAlignment());
2993 CombineTo(N, ExtLoad);
2994 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2995 ExtLoad.getValue(1));
2996 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2999 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3000 if (N0.getOpcode() == ISD::SETCC) {
3002 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
3003 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3004 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3005 if (SCC.Val) return SCC;
3011 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
3012 SDOperand N0 = N->getOperand(0);
3013 MVT VT = N->getValueType(0);
3015 // fold (aext c1) -> c1
3016 if (isa<ConstantSDNode>(N0))
3017 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
3018 // fold (aext (aext x)) -> (aext x)
3019 // fold (aext (zext x)) -> (zext x)
3020 // fold (aext (sext x)) -> (sext x)
3021 if (N0.getOpcode() == ISD::ANY_EXTEND ||
3022 N0.getOpcode() == ISD::ZERO_EXTEND ||
3023 N0.getOpcode() == ISD::SIGN_EXTEND)
3024 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
3026 // fold (aext (truncate (load x))) -> (aext (smaller load x))
3027 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3028 if (N0.getOpcode() == ISD::TRUNCATE) {
3029 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
3030 if (NarrowLoad.Val) {
3031 if (NarrowLoad.Val != N0.Val)
3032 CombineTo(N0.Val, NarrowLoad);
3033 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
3037 // fold (aext (truncate x))
3038 if (N0.getOpcode() == ISD::TRUNCATE) {
3039 SDOperand TruncOp = N0.getOperand(0);
3040 if (TruncOp.getValueType() == VT)
3041 return TruncOp; // x iff x size == zext size.
3042 if (TruncOp.getValueType().bitsGT(VT))
3043 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
3044 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
3047 // fold (aext (and (trunc x), cst)) -> (and x, cst).
3048 if (N0.getOpcode() == ISD::AND &&
3049 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3050 N0.getOperand(1).getOpcode() == ISD::Constant) {
3051 SDOperand X = N0.getOperand(0).getOperand(0);
3052 if (X.getValueType().bitsLT(VT)) {
3053 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
3054 } else if (X.getValueType().bitsGT(VT)) {
3055 X = DAG.getNode(ISD::TRUNCATE, VT, X);
3057 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3058 Mask.zext(VT.getSizeInBits());
3059 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
3062 // fold (aext (load x)) -> (aext (truncate (extload x)))
3063 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3064 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
3065 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3066 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
3067 LN0->getBasePtr(), LN0->getSrcValue(),
3068 LN0->getSrcValueOffset(),
3071 LN0->getAlignment());
3072 CombineTo(N, ExtLoad);
3073 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
3074 ExtLoad.getValue(1));
3075 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3078 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
3079 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
3080 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
3081 if (N0.getOpcode() == ISD::LOAD &&
3082 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
3084 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3085 MVT EVT = LN0->getMemoryVT();
3086 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
3087 LN0->getChain(), LN0->getBasePtr(),
3089 LN0->getSrcValueOffset(), EVT,
3091 LN0->getAlignment());
3092 CombineTo(N, ExtLoad);
3093 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
3094 ExtLoad.getValue(1));
3095 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3098 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3099 if (N0.getOpcode() == ISD::SETCC) {
3101 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
3102 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3103 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3111 /// GetDemandedBits - See if the specified operand can be simplified with the
3112 /// knowledge that only the bits specified by Mask are used. If so, return the
3113 /// simpler operand, otherwise return a null SDOperand.
3114 SDOperand DAGCombiner::GetDemandedBits(SDOperand V, const APInt &Mask) {
3115 switch (V.getOpcode()) {
3119 // If the LHS or RHS don't contribute bits to the or, drop them.
3120 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
3121 return V.getOperand(1);
3122 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
3123 return V.getOperand(0);
3126 // Only look at single-use SRLs.
3127 if (!V.Val->hasOneUse())
3129 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3130 // See if we can recursively simplify the LHS.
3131 unsigned Amt = RHSC->getValue();
3132 APInt NewMask = Mask << Amt;
3133 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
3134 if (SimplifyLHS.Val) {
3135 return DAG.getNode(ISD::SRL, V.getValueType(),
3136 SimplifyLHS, V.getOperand(1));
3143 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3144 /// bits and then truncated to a narrower type and where N is a multiple
3145 /// of number of bits of the narrower type, transform it to a narrower load
3146 /// from address + N / num of bits of new type. If the result is to be
3147 /// extended, also fold the extension to form a extending load.
3148 SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
3149 unsigned Opc = N->getOpcode();
3150 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3151 SDOperand N0 = N->getOperand(0);
3152 MVT VT = N->getValueType(0);
3153 MVT EVT = N->getValueType(0);
3155 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
3157 if (Opc == ISD::SIGN_EXTEND_INREG) {
3158 ExtType = ISD::SEXTLOAD;
3159 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3160 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
3164 unsigned EVTBits = EVT.getSizeInBits();
3166 bool CombineSRL = false;
3167 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
3168 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3169 ShAmt = N01->getValue();
3170 // Is the shift amount a multiple of size of VT?
3171 if ((ShAmt & (EVTBits-1)) == 0) {
3172 N0 = N0.getOperand(0);
3173 if (N0.getValueType().getSizeInBits() <= EVTBits)
3180 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3181 // Do not allow folding to a non-byte-sized integer here. These only
3182 // load correctly if the extra bits in memory that complete the byte
3183 // are zero, which is not known here.
3185 assert(N0.getValueType().getSizeInBits() > EVTBits &&
3186 "Cannot truncate to larger type!");
3187 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3188 MVT PtrType = N0.getOperand(1).getValueType();
3189 // For big endian targets, we need to adjust the offset to the pointer to
3190 // load the correct bytes.
3191 if (TLI.isBigEndian()) {
3192 unsigned LVTStoreBits = N0.getValueType().getStoreSizeInBits();
3193 unsigned EVTStoreBits = EVT.getStoreSizeInBits();
3194 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3196 uint64_t PtrOff = ShAmt / 8;
3197 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3198 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
3199 DAG.getConstant(PtrOff, PtrType));
3200 AddToWorkList(NewPtr.Val);
3201 SDOperand Load = (ExtType == ISD::NON_EXTLOAD)
3202 ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
3203 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3204 LN0->isVolatile(), NewAlign)
3205 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
3206 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
3207 LN0->isVolatile(), NewAlign);
3210 WorkListRemover DeadNodes(*this);
3211 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
3213 CombineTo(N->getOperand(0).Val, Load);
3215 CombineTo(N0.Val, Load, Load.getValue(1));
3217 if (Opc == ISD::SIGN_EXTEND_INREG)
3218 return DAG.getNode(Opc, VT, Load, N->getOperand(1));
3220 return DAG.getNode(Opc, VT, Load);
3222 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3229 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3230 SDOperand N0 = N->getOperand(0);
3231 SDOperand N1 = N->getOperand(1);
3232 MVT VT = N->getValueType(0);
3233 MVT EVT = cast<VTSDNode>(N1)->getVT();
3234 unsigned VTBits = VT.getSizeInBits();
3235 unsigned EVTBits = EVT.getSizeInBits();
3237 // fold (sext_in_reg c1) -> c1
3238 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3239 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
3241 // If the input is already sign extended, just drop the extension.
3242 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1)
3245 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3246 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3247 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
3248 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
3251 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3252 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
3253 return DAG.getZeroExtendInReg(N0, EVT);
3255 // fold operands of sext_in_reg based on knowledge that the top bits are not
3257 if (SimplifyDemandedBits(SDOperand(N, 0)))
3258 return SDOperand(N, 0);
3260 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3261 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3262 SDOperand NarrowLoad = ReduceLoadWidth(N);
3266 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
3267 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
3268 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3269 if (N0.getOpcode() == ISD::SRL) {
3270 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3271 if (ShAmt->getValue()+EVTBits <= VT.getSizeInBits()) {
3272 // We can turn this into an SRA iff the input to the SRL is already sign
3274 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3275 if (VT.getSizeInBits()-(ShAmt->getValue()+EVTBits) < InSignBits)
3276 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
3280 // fold (sext_inreg (extload x)) -> (sextload x)
3281 if (ISD::isEXTLoad(N0.Val) &&
3282 ISD::isUNINDEXEDLoad(N0.Val) &&
3283 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3284 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
3285 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3286 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
3287 LN0->getBasePtr(), LN0->getSrcValue(),
3288 LN0->getSrcValueOffset(), EVT,
3290 LN0->getAlignment());
3291 CombineTo(N, ExtLoad);
3292 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
3293 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3295 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3296 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
3298 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3299 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
3300 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3301 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
3302 LN0->getBasePtr(), LN0->getSrcValue(),
3303 LN0->getSrcValueOffset(), EVT,
3305 LN0->getAlignment());
3306 CombineTo(N, ExtLoad);
3307 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
3308 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3313 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
3314 SDOperand N0 = N->getOperand(0);
3315 MVT VT = N->getValueType(0);
3318 if (N0.getValueType() == N->getValueType(0))
3320 // fold (truncate c1) -> c1
3321 if (isa<ConstantSDNode>(N0))
3322 return DAG.getNode(ISD::TRUNCATE, VT, N0);
3323 // fold (truncate (truncate x)) -> (truncate x)
3324 if (N0.getOpcode() == ISD::TRUNCATE)
3325 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3326 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3327 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
3328 N0.getOpcode() == ISD::ANY_EXTEND) {
3329 if (N0.getOperand(0).getValueType().bitsLT(VT))
3330 // if the source is smaller than the dest, we still need an extend
3331 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
3332 else if (N0.getOperand(0).getValueType().bitsGT(VT))
3333 // if the source is larger than the dest, than we just need the truncate
3334 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3336 // if the source and dest are the same type, we can drop both the extend
3338 return N0.getOperand(0);
3341 // See if we can simplify the input to this truncate through knowledge that
3342 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3345 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
3346 VT.getSizeInBits()));
3348 return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
3350 // fold (truncate (load x)) -> (smaller load x)
3351 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3352 return ReduceLoadWidth(N);
3355 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
3356 SDOperand Elt = N->getOperand(i);
3357 if (Elt.getOpcode() != ISD::MERGE_VALUES)
3359 return Elt.getOperand(Elt.ResNo).Val;
3362 /// CombineConsecutiveLoads - build_pair (load, load) -> load
3363 /// if load locations are consecutive.
3364 SDOperand DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
3365 assert(N->getOpcode() == ISD::BUILD_PAIR);
3367 SDNode *LD1 = getBuildPairElt(N, 0);
3368 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
3370 MVT LD1VT = LD1->getValueType(0);
3371 SDNode *LD2 = getBuildPairElt(N, 1);
3372 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3373 if (ISD::isNON_EXTLoad(LD2) &&
3375 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
3376 LoadSDNode *LD = cast<LoadSDNode>(LD1);
3377 unsigned Align = LD->getAlignment();
3378 unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
3379 getABITypeAlignment(VT.getTypeForMVT());
3380 if ((!AfterLegalize || TLI.isTypeLegal(VT)) &&
3381 TLI.isOperationLegal(ISD::LOAD, VT) && NewAlign <= Align)
3382 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(),
3383 LD->getSrcValue(), LD->getSrcValueOffset(),
3384 LD->isVolatile(), Align);
3389 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3390 SDOperand N0 = N->getOperand(0);
3391 MVT VT = N->getValueType(0);
3393 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3394 // Only do this before legalize, since afterward the target may be depending
3395 // on the bitconvert.
3396 // First check to see if this is all constant.
3397 if (!AfterLegalize &&
3398 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
3400 bool isSimple = true;
3401 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3402 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3403 N0.getOperand(i).getOpcode() != ISD::Constant &&
3404 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3409 MVT DestEltVT = N->getValueType(0).getVectorElementType();
3410 assert(!DestEltVT.isVector() &&
3411 "Element type of vector ValueType must not be vector!");
3413 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
3417 // If the input is a constant, let getNode() fold it.
3418 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3419 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3420 if (Res.Val != N) return Res;
3423 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
3424 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3426 // fold (conv (load x)) -> (load (conv*)x)
3427 // If the resultant load doesn't need a higher alignment than the original!
3428 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() &&
3429 TLI.isOperationLegal(ISD::LOAD, VT)) {
3430 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3431 unsigned Align = TLI.getTargetMachine().getTargetData()->
3432 getABITypeAlignment(VT.getTypeForMVT());
3433 unsigned OrigAlign = LN0->getAlignment();
3434 if (Align <= OrigAlign) {
3435 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
3436 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3437 LN0->isVolatile(), Align);
3439 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
3445 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit)
3446 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit)
3447 // This often reduces constant pool loads.
3448 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
3449 N0.Val->hasOneUse() && VT.isInteger() && !VT.isVector()) {
3450 SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3451 AddToWorkList(NewConv.Val);
3453 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3454 if (N0.getOpcode() == ISD::FNEG)
3455 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT));
3456 assert(N0.getOpcode() == ISD::FABS);
3457 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT));
3460 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign'
3461 // Note that we don't handle copysign(x,cst) because this can always be folded
3462 // to an fneg or fabs.
3463 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() &&
3464 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
3465 VT.isInteger() && !VT.isVector()) {
3466 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
3467 SDOperand X = DAG.getNode(ISD::BIT_CONVERT,
3468 MVT::getIntegerVT(OrigXWidth),
3470 AddToWorkList(X.Val);
3472 // If X has a different width than the result/lhs, sext it or truncate it.
3473 unsigned VTWidth = VT.getSizeInBits();
3474 if (OrigXWidth < VTWidth) {
3475 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X);
3476 AddToWorkList(X.Val);
3477 } else if (OrigXWidth > VTWidth) {
3478 // To get the sign bit in the right place, we have to shift it right
3479 // before truncating.
3480 X = DAG.getNode(ISD::SRL, X.getValueType(), X,
3481 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
3482 AddToWorkList(X.Val);
3483 X = DAG.getNode(ISD::TRUNCATE, VT, X);
3484 AddToWorkList(X.Val);
3487 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3488 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT));
3489 AddToWorkList(X.Val);
3491 SDOperand Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3492 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT));
3493 AddToWorkList(Cst.Val);
3495 return DAG.getNode(ISD::OR, VT, X, Cst);
3498 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
3499 if (N0.getOpcode() == ISD::BUILD_PAIR) {
3500 SDOperand CombineLD = CombineConsecutiveLoads(N0.Val, VT);
3508 SDOperand DAGCombiner::visitBUILD_PAIR(SDNode *N) {
3509 MVT VT = N->getValueType(0);
3510 return CombineConsecutiveLoads(N, VT);
3513 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3514 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3515 /// destination element value type.
3516 SDOperand DAGCombiner::
3517 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
3518 MVT SrcEltVT = BV->getOperand(0).getValueType();
3520 // If this is already the right type, we're done.
3521 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
3523 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
3524 unsigned DstBitSize = DstEltVT.getSizeInBits();
3526 // If this is a conversion of N elements of one type to N elements of another
3527 // type, convert each element. This handles FP<->INT cases.
3528 if (SrcBitSize == DstBitSize) {
3529 SmallVector<SDOperand, 8> Ops;
3530 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3531 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
3532 AddToWorkList(Ops.back().Val);
3534 MVT VT = MVT::getVectorVT(DstEltVT,
3535 BV->getValueType(0).getVectorNumElements());
3536 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3539 // Otherwise, we're growing or shrinking the elements. To avoid having to
3540 // handle annoying details of growing/shrinking FP values, we convert them to
3542 if (SrcEltVT.isFloatingPoint()) {
3543 // Convert the input float vector to a int vector where the elements are the
3545 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3546 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits());
3547 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
3551 // Now we know the input is an integer vector. If the output is a FP type,
3552 // convert to integer first, then to FP of the right size.
3553 if (DstEltVT.isFloatingPoint()) {
3554 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3555 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits());
3556 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val;
3558 // Next, convert to FP elements of the same size.
3559 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3562 // Okay, we know the src/dst types are both integers of differing types.
3563 // Handling growing first.
3564 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
3565 if (SrcBitSize < DstBitSize) {
3566 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3568 SmallVector<SDOperand, 8> Ops;
3569 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3570 i += NumInputsPerOutput) {
3571 bool isLE = TLI.isLittleEndian();
3572 APInt NewBits = APInt(DstBitSize, 0);
3573 bool EltIsUndef = true;
3574 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3575 // Shift the previously computed bits over.
3576 NewBits <<= SrcBitSize;
3577 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3578 if (Op.getOpcode() == ISD::UNDEF) continue;
3582 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize);
3586 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3588 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3591 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size());
3592 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3595 // Finally, this must be the case where we are shrinking elements: each input
3596 // turns into multiple outputs.
3597 bool isS2V = ISD::isScalarToVector(BV);
3598 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3599 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands());
3600 SmallVector<SDOperand, 8> Ops;
3601 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3602 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3603 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3604 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3607 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue();
3608 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3609 APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
3610 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3611 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
3612 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
3613 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]);
3614 OpVal = OpVal.lshr(DstBitSize);
3617 // For big endian targets, swap the order of the pieces of each element.
3618 if (TLI.isBigEndian())
3619 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3621 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3626 SDOperand DAGCombiner::visitFADD(SDNode *N) {
3627 SDOperand N0 = N->getOperand(0);
3628 SDOperand N1 = N->getOperand(1);
3629 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3630 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3631 MVT VT = N->getValueType(0);
3634 if (VT.isVector()) {
3635 SDOperand FoldedVOp = SimplifyVBinOp(N);
3636 if (FoldedVOp.Val) return FoldedVOp;
3639 // fold (fadd c1, c2) -> c1+c2
3640 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3641 return DAG.getNode(ISD::FADD, VT, N0, N1);
3642 // canonicalize constant to RHS
3643 if (N0CFP && !N1CFP)
3644 return DAG.getNode(ISD::FADD, VT, N1, N0);
3645 // fold (A + (-B)) -> A-B
3646 if (isNegatibleForFree(N1, AfterLegalize) == 2)
3647 return DAG.getNode(ISD::FSUB, VT, N0,
3648 GetNegatedExpression(N1, DAG, AfterLegalize));
3649 // fold ((-A) + B) -> B-A
3650 if (isNegatibleForFree(N0, AfterLegalize) == 2)
3651 return DAG.getNode(ISD::FSUB, VT, N1,
3652 GetNegatedExpression(N0, DAG, AfterLegalize));
3654 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3655 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3656 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3657 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
3658 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
3663 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
3664 SDOperand N0 = N->getOperand(0);
3665 SDOperand N1 = N->getOperand(1);
3666 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3667 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3668 MVT VT = N->getValueType(0);
3671 if (VT.isVector()) {
3672 SDOperand FoldedVOp = SimplifyVBinOp(N);
3673 if (FoldedVOp.Val) return FoldedVOp;
3676 // fold (fsub c1, c2) -> c1-c2
3677 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3678 return DAG.getNode(ISD::FSUB, VT, N0, N1);
3680 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
3681 if (isNegatibleForFree(N1, AfterLegalize))
3682 return GetNegatedExpression(N1, DAG, AfterLegalize);
3683 return DAG.getNode(ISD::FNEG, VT, N1);
3685 // fold (A-(-B)) -> A+B
3686 if (isNegatibleForFree(N1, AfterLegalize))
3687 return DAG.getNode(ISD::FADD, VT, N0,
3688 GetNegatedExpression(N1, DAG, AfterLegalize));
3693 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
3694 SDOperand N0 = N->getOperand(0);
3695 SDOperand N1 = N->getOperand(1);
3696 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3697 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3698 MVT VT = N->getValueType(0);
3701 if (VT.isVector()) {
3702 SDOperand FoldedVOp = SimplifyVBinOp(N);
3703 if (FoldedVOp.Val) return FoldedVOp;
3706 // fold (fmul c1, c2) -> c1*c2
3707 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3708 return DAG.getNode(ISD::FMUL, VT, N0, N1);
3709 // canonicalize constant to RHS
3710 if (N0CFP && !N1CFP)
3711 return DAG.getNode(ISD::FMUL, VT, N1, N0);
3712 // fold (fmul X, 2.0) -> (fadd X, X)
3713 if (N1CFP && N1CFP->isExactlyValue(+2.0))
3714 return DAG.getNode(ISD::FADD, VT, N0, N0);
3715 // fold (fmul X, -1.0) -> (fneg X)
3716 if (N1CFP && N1CFP->isExactlyValue(-1.0))
3717 return DAG.getNode(ISD::FNEG, VT, N0);
3720 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) {
3721 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) {
3722 // Both can be negated for free, check to see if at least one is cheaper
3724 if (LHSNeg == 2 || RHSNeg == 2)
3725 return DAG.getNode(ISD::FMUL, VT,
3726 GetNegatedExpression(N0, DAG, AfterLegalize),
3727 GetNegatedExpression(N1, DAG, AfterLegalize));
3731 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
3732 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
3733 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3734 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
3735 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
3740 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
3741 SDOperand N0 = N->getOperand(0);
3742 SDOperand N1 = N->getOperand(1);
3743 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3744 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3745 MVT VT = N->getValueType(0);
3748 if (VT.isVector()) {
3749 SDOperand FoldedVOp = SimplifyVBinOp(N);
3750 if (FoldedVOp.Val) return FoldedVOp;
3753 // fold (fdiv c1, c2) -> c1/c2
3754 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3755 return DAG.getNode(ISD::FDIV, VT, N0, N1);
3759 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) {
3760 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) {
3761 // Both can be negated for free, check to see if at least one is cheaper
3763 if (LHSNeg == 2 || RHSNeg == 2)
3764 return DAG.getNode(ISD::FDIV, VT,
3765 GetNegatedExpression(N0, DAG, AfterLegalize),
3766 GetNegatedExpression(N1, DAG, AfterLegalize));
3773 SDOperand DAGCombiner::visitFREM(SDNode *N) {
3774 SDOperand N0 = N->getOperand(0);
3775 SDOperand N1 = N->getOperand(1);
3776 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3777 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3778 MVT VT = N->getValueType(0);
3780 // fold (frem c1, c2) -> fmod(c1,c2)
3781 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3782 return DAG.getNode(ISD::FREM, VT, N0, N1);
3787 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
3788 SDOperand N0 = N->getOperand(0);
3789 SDOperand N1 = N->getOperand(1);
3790 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3791 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3792 MVT VT = N->getValueType(0);
3794 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
3795 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
3798 const APFloat& V = N1CFP->getValueAPF();
3799 // copysign(x, c1) -> fabs(x) iff ispos(c1)
3800 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
3801 if (!V.isNegative())
3802 return DAG.getNode(ISD::FABS, VT, N0);
3804 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
3807 // copysign(fabs(x), y) -> copysign(x, y)
3808 // copysign(fneg(x), y) -> copysign(x, y)
3809 // copysign(copysign(x,z), y) -> copysign(x, y)
3810 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
3811 N0.getOpcode() == ISD::FCOPYSIGN)
3812 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
3814 // copysign(x, abs(y)) -> abs(x)
3815 if (N1.getOpcode() == ISD::FABS)
3816 return DAG.getNode(ISD::FABS, VT, N0);
3818 // copysign(x, copysign(y,z)) -> copysign(x, z)
3819 if (N1.getOpcode() == ISD::FCOPYSIGN)
3820 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
3822 // copysign(x, fp_extend(y)) -> copysign(x, y)
3823 // copysign(x, fp_round(y)) -> copysign(x, y)
3824 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
3825 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
3832 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
3833 SDOperand N0 = N->getOperand(0);
3834 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3835 MVT VT = N->getValueType(0);
3837 // fold (sint_to_fp c1) -> c1fp
3838 if (N0C && N0.getValueType() != MVT::ppcf128)
3839 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
3843 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
3844 SDOperand N0 = N->getOperand(0);
3845 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3846 MVT VT = N->getValueType(0);
3848 // fold (uint_to_fp c1) -> c1fp
3849 if (N0C && N0.getValueType() != MVT::ppcf128)
3850 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
3854 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
3855 SDOperand N0 = N->getOperand(0);
3856 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3857 MVT VT = N->getValueType(0);
3859 // fold (fp_to_sint c1fp) -> c1
3861 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
3865 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
3866 SDOperand N0 = N->getOperand(0);
3867 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3868 MVT VT = N->getValueType(0);
3870 // fold (fp_to_uint c1fp) -> c1
3871 if (N0CFP && VT != MVT::ppcf128)
3872 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
3876 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
3877 SDOperand N0 = N->getOperand(0);
3878 SDOperand N1 = N->getOperand(1);
3879 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3880 MVT VT = N->getValueType(0);
3882 // fold (fp_round c1fp) -> c1fp
3883 if (N0CFP && N0.getValueType() != MVT::ppcf128)
3884 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1);
3886 // fold (fp_round (fp_extend x)) -> x
3887 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
3888 return N0.getOperand(0);
3890 // fold (fp_round (fp_round x)) -> (fp_round x)
3891 if (N0.getOpcode() == ISD::FP_ROUND) {
3892 // This is a value preserving truncation if both round's are.
3893 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
3894 N0.Val->getConstantOperandVal(1) == 1;
3895 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0),
3896 DAG.getIntPtrConstant(IsTrunc));
3899 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
3900 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
3901 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1);
3902 AddToWorkList(Tmp.Val);
3903 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
3909 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
3910 SDOperand N0 = N->getOperand(0);
3911 MVT VT = N->getValueType(0);
3912 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3913 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3915 // fold (fp_round_inreg c1fp) -> c1fp
3917 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT);
3918 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
3923 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
3924 SDOperand N0 = N->getOperand(0);
3925 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3926 MVT VT = N->getValueType(0);
3928 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
3929 if (N->hasOneUse() &&
3930 N->use_begin()->getSDOperand().getOpcode() == ISD::FP_ROUND)
3933 // fold (fp_extend c1fp) -> c1fp
3934 if (N0CFP && VT != MVT::ppcf128)
3935 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
3937 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
3939 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){
3940 SDOperand In = N0.getOperand(0);
3941 if (In.getValueType() == VT) return In;
3942 if (VT.bitsLT(In.getValueType()))
3943 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1));
3944 return DAG.getNode(ISD::FP_EXTEND, VT, In);
3947 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
3948 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3949 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
3950 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3951 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
3952 LN0->getBasePtr(), LN0->getSrcValue(),
3953 LN0->getSrcValueOffset(),
3956 LN0->getAlignment());
3957 CombineTo(N, ExtLoad);
3958 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad,
3959 DAG.getIntPtrConstant(1)),
3960 ExtLoad.getValue(1));
3961 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3968 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
3969 SDOperand N0 = N->getOperand(0);
3971 if (isNegatibleForFree(N0, AfterLegalize))
3972 return GetNegatedExpression(N0, DAG, AfterLegalize);
3974 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
3975 // constant pool values.
3976 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
3977 N0.getOperand(0).getValueType().isInteger() &&
3978 !N0.getOperand(0).getValueType().isVector()) {
3979 SDOperand Int = N0.getOperand(0);
3980 MVT IntVT = Int.getValueType();
3981 if (IntVT.isInteger() && !IntVT.isVector()) {
3982 Int = DAG.getNode(ISD::XOR, IntVT, Int,
3983 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT));
3984 AddToWorkList(Int.Val);
3985 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
3992 SDOperand DAGCombiner::visitFABS(SDNode *N) {
3993 SDOperand N0 = N->getOperand(0);
3994 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3995 MVT VT = N->getValueType(0);
3997 // fold (fabs c1) -> fabs(c1)
3998 if (N0CFP && VT != MVT::ppcf128)
3999 return DAG.getNode(ISD::FABS, VT, N0);
4000 // fold (fabs (fabs x)) -> (fabs x)
4001 if (N0.getOpcode() == ISD::FABS)
4002 return N->getOperand(0);
4003 // fold (fabs (fneg x)) -> (fabs x)
4004 // fold (fabs (fcopysign x, y)) -> (fabs x)
4005 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
4006 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
4008 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
4009 // constant pool values.
4010 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
4011 N0.getOperand(0).getValueType().isInteger() &&
4012 !N0.getOperand(0).getValueType().isVector()) {
4013 SDOperand Int = N0.getOperand(0);
4014 MVT IntVT = Int.getValueType();
4015 if (IntVT.isInteger() && !IntVT.isVector()) {
4016 Int = DAG.getNode(ISD::AND, IntVT, Int,
4017 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT));
4018 AddToWorkList(Int.Val);
4019 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
4026 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
4027 SDOperand Chain = N->getOperand(0);
4028 SDOperand N1 = N->getOperand(1);
4029 SDOperand N2 = N->getOperand(2);
4030 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4032 // never taken branch, fold to chain
4033 if (N1C && N1C->isNullValue())
4035 // unconditional branch
4036 if (N1C && N1C->getAPIntValue() == 1)
4037 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
4038 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
4040 if (N1.getOpcode() == ISD::SETCC &&
4041 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
4042 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
4043 N1.getOperand(0), N1.getOperand(1), N2);
4048 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
4050 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
4051 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
4052 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
4054 // Use SimplifySetCC to simplify SETCC's.
4055 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
4056 if (Simp.Val) AddToWorkList(Simp.Val);
4058 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
4060 // fold br_cc true, dest -> br dest (unconditional branch)
4061 if (SCCC && !SCCC->isNullValue())
4062 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
4064 // fold br_cc false, dest -> unconditional fall through
4065 if (SCCC && SCCC->isNullValue())
4066 return N->getOperand(0);
4068 // fold to a simpler setcc
4069 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
4070 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
4071 Simp.getOperand(2), Simp.getOperand(0),
4072 Simp.getOperand(1), N->getOperand(4));
4077 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
4078 /// pre-indexed load / store when the base pointer is a add or subtract
4079 /// and it has other uses besides the load / store. After the
4080 /// transformation, the new indexed load / store has effectively folded
4081 /// the add / subtract in and all of its other uses are redirected to the
4082 /// new load / store.
4083 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
4090 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4091 if (LD->isIndexed())
4093 VT = LD->getMemoryVT();
4094 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
4095 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
4097 Ptr = LD->getBasePtr();
4098 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4099 if (ST->isIndexed())
4101 VT = ST->getMemoryVT();
4102 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
4103 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
4105 Ptr = ST->getBasePtr();
4110 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
4111 // out. There is no reason to make this a preinc/predec.
4112 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
4113 Ptr.Val->hasOneUse())
4116 // Ask the target to do addressing mode selection.
4119 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4120 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
4122 // Don't create a indexed load / store with zero offset.
4123 if (isa<ConstantSDNode>(Offset) &&
4124 cast<ConstantSDNode>(Offset)->isNullValue())
4127 // Try turning it into a pre-indexed load / store except when:
4128 // 1) The new base ptr is a frame index.
4129 // 2) If N is a store and the new base ptr is either the same as or is a
4130 // predecessor of the value being stored.
4131 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
4132 // that would create a cycle.
4133 // 4) All uses are load / store ops that use it as old base ptr.
4135 // Check #1. Preinc'ing a frame index would require copying the stack pointer
4136 // (plus the implicit offset) to a register to preinc anyway.
4137 if (isa<FrameIndexSDNode>(BasePtr))
4142 SDOperand Val = cast<StoreSDNode>(N)->getValue();
4143 if (Val == BasePtr || BasePtr.Val->isPredecessorOf(Val.Val))
4147 // Now check for #3 and #4.
4148 bool RealUse = false;
4149 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
4150 E = Ptr.Val->use_end(); I != E; ++I) {
4151 SDNode *Use = I->getUser();
4154 if (Use->isPredecessorOf(N))
4157 if (!((Use->getOpcode() == ISD::LOAD &&
4158 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
4159 (Use->getOpcode() == ISD::STORE &&
4160 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
4168 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
4170 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
4173 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
4174 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
4176 WorkListRemover DeadNodes(*this);
4178 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
4180 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
4183 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
4187 // Finally, since the node is now dead, remove it from the graph.
4190 // Replace the uses of Ptr with uses of the updated base value.
4191 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
4193 removeFromWorkList(Ptr.Val);
4194 DAG.DeleteNode(Ptr.Val);
4199 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
4200 /// add / sub of the base pointer node into a post-indexed load / store.
4201 /// The transformation folded the add / subtract into the new indexed
4202 /// load / store effectively and all of its uses are redirected to the
4203 /// new load / store.
4204 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
4211 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4212 if (LD->isIndexed())
4214 VT = LD->getMemoryVT();
4215 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
4216 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
4218 Ptr = LD->getBasePtr();
4219 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4220 if (ST->isIndexed())
4222 VT = ST->getMemoryVT();
4223 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
4224 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
4226 Ptr = ST->getBasePtr();
4231 if (Ptr.Val->hasOneUse())
4234 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
4235 E = Ptr.Val->use_end(); I != E; ++I) {
4236 SDNode *Op = I->getUser();
4238 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
4243 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4244 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
4246 std::swap(BasePtr, Offset);
4249 // Don't create a indexed load / store with zero offset.
4250 if (isa<ConstantSDNode>(Offset) &&
4251 cast<ConstantSDNode>(Offset)->isNullValue())
4254 // Try turning it into a post-indexed load / store except when
4255 // 1) All uses are load / store ops that use it as base ptr.
4256 // 2) Op must be independent of N, i.e. Op is neither a predecessor
4257 // nor a successor of N. Otherwise, if Op is folded that would
4261 bool TryNext = false;
4262 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
4263 EE = BasePtr.Val->use_end(); II != EE; ++II) {
4264 SDNode *Use = II->getUser();
4268 // If all the uses are load / store addresses, then don't do the
4270 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
4271 bool RealUse = false;
4272 for (SDNode::use_iterator III = Use->use_begin(),
4273 EEE = Use->use_end(); III != EEE; ++III) {
4274 SDNode *UseUse = III->getUser();
4275 if (!((UseUse->getOpcode() == ISD::LOAD &&
4276 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
4277 (UseUse->getOpcode() == ISD::STORE &&
4278 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)))
4292 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
4293 SDOperand Result = isLoad
4294 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
4295 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
4298 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
4299 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
4301 WorkListRemover DeadNodes(*this);
4303 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
4305 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
4308 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
4312 // Finally, since the node is now dead, remove it from the graph.
4315 // Replace the uses of Use with uses of the updated base value.
4316 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
4317 Result.getValue(isLoad ? 1 : 0),
4319 removeFromWorkList(Op);
4328 /// InferAlignment - If we can infer some alignment information from this
4329 /// pointer, return it.
4330 static unsigned InferAlignment(SDOperand Ptr, SelectionDAG &DAG) {
4331 // If this is a direct reference to a stack slot, use information about the
4332 // stack slot's alignment.
4333 int FrameIdx = 1 << 31;
4334 int64_t FrameOffset = 0;
4335 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) {
4336 FrameIdx = FI->getIndex();
4337 } else if (Ptr.getOpcode() == ISD::ADD &&
4338 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4339 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4340 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4341 FrameOffset = Ptr.getConstantOperandVal(1);
4344 if (FrameIdx != (1 << 31)) {
4345 // FIXME: Handle FI+CST.
4346 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
4347 if (MFI.isFixedObjectIndex(FrameIdx)) {
4348 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx);
4350 // The alignment of the frame index can be determined from its offset from
4351 // the incoming frame position. If the frame object is at offset 32 and
4352 // the stack is guaranteed to be 16-byte aligned, then we know that the
4353 // object is 16-byte aligned.
4354 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment();
4355 unsigned Align = MinAlign(ObjectOffset, StackAlign);
4357 // Finally, the frame object itself may have a known alignment. Factor
4358 // the alignment + offset into a new alignment. For example, if we know
4359 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a
4360 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte
4361 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc.
4362 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx),
4364 return std::max(Align, FIInfoAlign);
4371 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
4372 LoadSDNode *LD = cast<LoadSDNode>(N);
4373 SDOperand Chain = LD->getChain();
4374 SDOperand Ptr = LD->getBasePtr();
4376 // Try to infer better alignment information than the load already has.
4377 if (LD->isUnindexed()) {
4378 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4379 if (Align > LD->getAlignment())
4380 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
4381 Chain, Ptr, LD->getSrcValue(),
4382 LD->getSrcValueOffset(), LD->getMemoryVT(),
4383 LD->isVolatile(), Align);
4388 // If load is not volatile and there are no uses of the loaded value (and
4389 // the updated indexed value in case of indexed loads), change uses of the
4390 // chain value into uses of the chain input (i.e. delete the dead load).
4391 if (!LD->isVolatile()) {
4392 if (N->getValueType(1) == MVT::Other) {
4394 if (N->hasNUsesOfValue(0, 0)) {
4395 // It's not safe to use the two value CombineTo variant here. e.g.
4396 // v1, chain2 = load chain1, loc
4397 // v2, chain3 = load chain2, loc
4399 // Now we replace use of chain2 with chain1. This makes the second load
4400 // isomorphic to the one we are deleting, and thus makes this load live.
4401 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4402 DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG));
4404 WorkListRemover DeadNodes(*this);
4405 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &DeadNodes);
4406 if (N->use_empty()) {
4407 removeFromWorkList(N);
4410 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
4414 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
4415 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
4416 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0));
4417 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4418 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG));
4419 DOUT << " and 2 other values\n";
4420 WorkListRemover DeadNodes(*this);
4421 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &DeadNodes);
4422 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1),
4423 DAG.getNode(ISD::UNDEF, N->getValueType(1)),
4425 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &DeadNodes);
4426 removeFromWorkList(N);
4428 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
4433 // If this load is directly stored, replace the load value with the stored
4435 // TODO: Handle store large -> read small portion.
4436 // TODO: Handle TRUNCSTORE/LOADEXT
4437 if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
4438 !LD->isVolatile()) {
4439 if (ISD::isNON_TRUNCStore(Chain.Val)) {
4440 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
4441 if (PrevST->getBasePtr() == Ptr &&
4442 PrevST->getValue().getValueType() == N->getValueType(0))
4443 return CombineTo(N, Chain.getOperand(1), Chain);
4448 // Walk up chain skipping non-aliasing memory nodes.
4449 SDOperand BetterChain = FindBetterChain(N, Chain);
4451 // If there is a better chain.
4452 if (Chain != BetterChain) {
4455 // Replace the chain to void dependency.
4456 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4457 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
4458 LD->getSrcValue(), LD->getSrcValueOffset(),
4459 LD->isVolatile(), LD->getAlignment());
4461 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
4462 LD->getValueType(0),
4463 BetterChain, Ptr, LD->getSrcValue(),
4464 LD->getSrcValueOffset(),
4467 LD->getAlignment());
4470 // Create token factor to keep old chain connected.
4471 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
4472 Chain, ReplLoad.getValue(1));
4474 // Replace uses with load result and token factor. Don't add users
4476 return CombineTo(N, ReplLoad.getValue(0), Token, false);
4480 // Try transforming N to an indexed load.
4481 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4482 return SDOperand(N, 0);
4488 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
4489 StoreSDNode *ST = cast<StoreSDNode>(N);
4490 SDOperand Chain = ST->getChain();
4491 SDOperand Value = ST->getValue();
4492 SDOperand Ptr = ST->getBasePtr();
4494 // Try to infer better alignment information than the store already has.
4495 if (ST->isUnindexed()) {
4496 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4497 if (Align > ST->getAlignment())
4498 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(),
4499 ST->getSrcValueOffset(), ST->getMemoryVT(),
4500 ST->isVolatile(), Align);
4504 // If this is a store of a bit convert, store the input value if the
4505 // resultant store does not need a higher alignment than the original.
4506 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
4507 ST->isUnindexed()) {
4508 unsigned Align = ST->getAlignment();
4509 MVT SVT = Value.getOperand(0).getValueType();
4510 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
4511 getABITypeAlignment(SVT.getTypeForMVT());
4512 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
4513 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
4514 ST->getSrcValueOffset(), ST->isVolatile(), Align);
4517 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
4518 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
4519 if (Value.getOpcode() != ISD::TargetConstantFP) {
4521 switch (CFP->getValueType(0).getSimpleVT()) {
4522 default: assert(0 && "Unknown FP type");
4523 case MVT::f80: // We don't do this for these yet.
4528 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
4529 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
4530 convertToAPInt().getZExtValue(), MVT::i32);
4531 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4532 ST->getSrcValueOffset(), ST->isVolatile(),
4533 ST->getAlignment());
4537 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
4538 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
4539 getZExtValue(), MVT::i64);
4540 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4541 ST->getSrcValueOffset(), ST->isVolatile(),
4542 ST->getAlignment());
4543 } else if (TLI.isTypeLegal(MVT::i32)) {
4544 // Many FP stores are not made apparent until after legalize, e.g. for
4545 // argument passing. Since this is so common, custom legalize the
4546 // 64-bit integer store into two 32-bit stores.
4547 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue();
4548 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
4549 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
4550 if (TLI.isBigEndian()) std::swap(Lo, Hi);
4552 int SVOffset = ST->getSrcValueOffset();
4553 unsigned Alignment = ST->getAlignment();
4554 bool isVolatile = ST->isVolatile();
4556 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
4557 ST->getSrcValueOffset(),
4558 isVolatile, ST->getAlignment());
4559 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4560 DAG.getConstant(4, Ptr.getValueType()));
4562 Alignment = MinAlign(Alignment, 4U);
4563 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
4564 SVOffset, isVolatile, Alignment);
4565 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
4573 // Walk up chain skipping non-aliasing memory nodes.
4574 SDOperand BetterChain = FindBetterChain(N, Chain);
4576 // If there is a better chain.
4577 if (Chain != BetterChain) {
4578 // Replace the chain to avoid dependency.
4579 SDOperand ReplStore;
4580 if (ST->isTruncatingStore()) {
4581 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
4582 ST->getSrcValue(),ST->getSrcValueOffset(),
4584 ST->isVolatile(), ST->getAlignment());
4586 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
4587 ST->getSrcValue(), ST->getSrcValueOffset(),
4588 ST->isVolatile(), ST->getAlignment());
4591 // Create token to keep both nodes around.
4593 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
4595 // Don't add users to work list.
4596 return CombineTo(N, Token, false);
4600 // Try transforming N to an indexed store.
4601 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4602 return SDOperand(N, 0);
4604 // FIXME: is there such a thing as a truncating indexed store?
4605 if (ST->isTruncatingStore() && ST->isUnindexed() &&
4606 Value.getValueType().isInteger()) {
4607 // See if we can simplify the input to this truncstore with knowledge that
4608 // only the low bits are being used. For example:
4609 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
4611 GetDemandedBits(Value,
4612 APInt::getLowBitsSet(Value.getValueSizeInBits(),
4613 ST->getMemoryVT().getSizeInBits()));
4614 AddToWorkList(Value.Val);
4616 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
4617 ST->getSrcValueOffset(), ST->getMemoryVT(),
4618 ST->isVolatile(), ST->getAlignment());
4620 // Otherwise, see if we can simplify the operation with
4621 // SimplifyDemandedBits, which only works if the value has a single use.
4622 if (SimplifyDemandedBits(Value,
4623 APInt::getLowBitsSet(
4624 Value.getValueSizeInBits(),
4625 ST->getMemoryVT().getSizeInBits())))
4626 return SDOperand(N, 0);
4629 // If this is a load followed by a store to the same location, then the store
4631 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
4632 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
4633 ST->isUnindexed() && !ST->isVolatile() &&
4634 // There can't be any side effects between the load and store, such as
4636 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) {
4637 // The store is dead, remove it.
4642 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
4643 // truncating store. We can do this even if this is already a truncstore.
4644 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
4645 && TLI.isTypeLegal(Value.getOperand(0).getValueType()) &&
4646 Value.Val->hasOneUse() && ST->isUnindexed() &&
4647 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
4648 ST->getMemoryVT())) {
4649 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
4650 ST->getSrcValueOffset(), ST->getMemoryVT(),
4651 ST->isVolatile(), ST->getAlignment());
4657 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
4658 SDOperand InVec = N->getOperand(0);
4659 SDOperand InVal = N->getOperand(1);
4660 SDOperand EltNo = N->getOperand(2);
4662 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
4663 // vector with the inserted element.
4664 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
4665 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4666 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
4667 if (Elt < Ops.size())
4669 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
4670 &Ops[0], Ops.size());
4676 SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
4677 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
4678 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
4679 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
4681 // Perform only after legalization to ensure build_vector / vector_shuffle
4682 // optimizations have already been done.
4683 if (!AfterLegalize) return SDOperand();
4685 SDOperand InVec = N->getOperand(0);
4686 SDOperand EltNo = N->getOperand(1);
4688 if (isa<ConstantSDNode>(EltNo)) {
4689 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4690 bool NewLoad = false;
4691 MVT VT = InVec.getValueType();
4692 MVT EVT = VT.getVectorElementType();
4694 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
4695 MVT BCVT = InVec.getOperand(0).getValueType();
4696 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()))
4698 InVec = InVec.getOperand(0);
4699 EVT = BCVT.getVectorElementType();
4703 LoadSDNode *LN0 = NULL;
4704 if (ISD::isNormalLoad(InVec.Val))
4705 LN0 = cast<LoadSDNode>(InVec);
4706 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4707 InVec.getOperand(0).getValueType() == EVT &&
4708 ISD::isNormalLoad(InVec.getOperand(0).Val)) {
4709 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
4710 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) {
4711 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
4713 // (load $addr+1*size)
4714 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2).
4715 getOperand(Elt))->getValue();
4716 unsigned NumElems = InVec.getOperand(2).getNumOperands();
4717 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
4718 if (InVec.getOpcode() == ISD::BIT_CONVERT)
4719 InVec = InVec.getOperand(0);
4720 if (ISD::isNormalLoad(InVec.Val)) {
4721 LN0 = cast<LoadSDNode>(InVec);
4722 Elt = (Idx < NumElems) ? Idx : Idx - NumElems;
4725 if (!LN0 || !LN0->hasOneUse())
4728 unsigned Align = LN0->getAlignment();
4730 // Check the resultant load doesn't need a higher alignment than the
4732 unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
4733 getABITypeAlignment(LVT.getTypeForMVT());
4734 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align)
4739 SDOperand NewPtr = LN0->getBasePtr();
4741 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
4742 MVT PtrType = NewPtr.getValueType();
4743 if (TLI.isBigEndian())
4744 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
4745 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
4746 DAG.getConstant(PtrOff, PtrType));
4748 return DAG.getLoad(LVT, LN0->getChain(), NewPtr,
4749 LN0->getSrcValue(), LN0->getSrcValueOffset(),
4750 LN0->isVolatile(), Align);
4756 SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
4757 unsigned NumInScalars = N->getNumOperands();
4758 MVT VT = N->getValueType(0);
4759 unsigned NumElts = VT.getVectorNumElements();
4760 MVT EltType = VT.getVectorElementType();
4762 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
4763 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
4764 // at most two distinct vectors, turn this into a shuffle node.
4765 SDOperand VecIn1, VecIn2;
4766 for (unsigned i = 0; i != NumInScalars; ++i) {
4767 // Ignore undef inputs.
4768 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4770 // If this input is something other than a EXTRACT_VECTOR_ELT with a
4771 // constant index, bail out.
4772 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4773 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
4774 VecIn1 = VecIn2 = SDOperand(0, 0);
4778 // If the input vector type disagrees with the result of the build_vector,
4779 // we can't make a shuffle.
4780 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
4781 if (ExtractedFromVec.getValueType() != VT) {
4782 VecIn1 = VecIn2 = SDOperand(0, 0);
4786 // Otherwise, remember this. We allow up to two distinct input vectors.
4787 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
4790 if (VecIn1.Val == 0) {
4791 VecIn1 = ExtractedFromVec;
4792 } else if (VecIn2.Val == 0) {
4793 VecIn2 = ExtractedFromVec;
4796 VecIn1 = VecIn2 = SDOperand(0, 0);
4801 // If everything is good, we can make a shuffle operation.
4803 SmallVector<SDOperand, 8> BuildVecIndices;
4804 for (unsigned i = 0; i != NumInScalars; ++i) {
4805 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
4806 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
4810 SDOperand Extract = N->getOperand(i);
4812 // If extracting from the first vector, just use the index directly.
4813 if (Extract.getOperand(0) == VecIn1) {
4814 BuildVecIndices.push_back(Extract.getOperand(1));
4818 // Otherwise, use InIdx + VecSize
4819 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
4820 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars));
4823 // Add count and size info.
4824 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts);
4826 // Return the new VECTOR_SHUFFLE node.
4832 // Use an undef build_vector as input for the second operand.
4833 std::vector<SDOperand> UnOps(NumInScalars,
4834 DAG.getNode(ISD::UNDEF,
4836 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
4837 &UnOps[0], UnOps.size());
4838 AddToWorkList(Ops[1].Val);
4840 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
4841 &BuildVecIndices[0], BuildVecIndices.size());
4842 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3);
4848 SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
4849 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
4850 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
4851 // inputs come from at most two distinct vectors, turn this into a shuffle
4854 // If we only have one input vector, we don't need to do any concatenation.
4855 if (N->getNumOperands() == 1) {
4856 return N->getOperand(0);
4862 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
4863 SDOperand ShufMask = N->getOperand(2);
4864 unsigned NumElts = ShufMask.getNumOperands();
4866 // If the shuffle mask is an identity operation on the LHS, return the LHS.
4867 bool isIdentity = true;
4868 for (unsigned i = 0; i != NumElts; ++i) {
4869 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4870 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
4875 if (isIdentity) return N->getOperand(0);
4877 // If the shuffle mask is an identity operation on the RHS, return the RHS.
4879 for (unsigned i = 0; i != NumElts; ++i) {
4880 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4881 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
4886 if (isIdentity) return N->getOperand(1);
4888 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
4890 bool isUnary = true;
4891 bool isSplat = true;
4893 unsigned BaseIdx = 0;
4894 for (unsigned i = 0; i != NumElts; ++i)
4895 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
4896 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
4897 int V = (Idx < NumElts) ? 0 : 1;
4911 SDOperand N0 = N->getOperand(0);
4912 SDOperand N1 = N->getOperand(1);
4913 // Normalize unary shuffle so the RHS is undef.
4914 if (isUnary && VecNum == 1)
4917 // If it is a splat, check if the argument vector is a build_vector with
4918 // all scalar elements the same.
4922 // If this is a bit convert that changes the element type of the vector but
4923 // not the number of vector elements, look through it. Be careful not to
4924 // look though conversions that change things like v4f32 to v2f64.
4925 if (V->getOpcode() == ISD::BIT_CONVERT) {
4926 SDOperand ConvInput = V->getOperand(0);
4927 if (ConvInput.getValueType().getVectorNumElements() == NumElts)
4931 if (V->getOpcode() == ISD::BUILD_VECTOR) {
4932 unsigned NumElems = V->getNumOperands();
4933 if (NumElems > BaseIdx) {
4935 bool AllSame = true;
4936 for (unsigned i = 0; i != NumElems; ++i) {
4937 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
4938 Base = V->getOperand(i);
4942 // Splat of <u, u, u, u>, return <u, u, u, u>
4945 for (unsigned i = 0; i != NumElems; ++i) {
4946 if (V->getOperand(i) != Base) {
4951 // Splat of <x, x, x, x>, return <x, x, x, x>
4958 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
4960 if (isUnary || N0 == N1) {
4961 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
4963 SmallVector<SDOperand, 8> MappedOps;
4964 for (unsigned i = 0; i != NumElts; ++i) {
4965 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
4966 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
4967 MappedOps.push_back(ShufMask.getOperand(i));
4970 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
4971 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
4974 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
4975 &MappedOps[0], MappedOps.size());
4976 AddToWorkList(ShufMask.Val);
4977 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
4979 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
4986 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
4987 /// an AND to a vector_shuffle with the destination vector and a zero vector.
4988 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
4989 /// vector_shuffle V, Zero, <0, 4, 2, 4>
4990 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
4991 SDOperand LHS = N->getOperand(0);
4992 SDOperand RHS = N->getOperand(1);
4993 if (N->getOpcode() == ISD::AND) {
4994 if (RHS.getOpcode() == ISD::BIT_CONVERT)
4995 RHS = RHS.getOperand(0);
4996 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
4997 std::vector<SDOperand> IdxOps;
4998 unsigned NumOps = RHS.getNumOperands();
4999 unsigned NumElts = NumOps;
5000 MVT EVT = RHS.getValueType().getVectorElementType();
5001 for (unsigned i = 0; i != NumElts; ++i) {
5002 SDOperand Elt = RHS.getOperand(i);
5003 if (!isa<ConstantSDNode>(Elt))
5005 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
5006 IdxOps.push_back(DAG.getConstant(i, EVT));
5007 else if (cast<ConstantSDNode>(Elt)->isNullValue())
5008 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
5013 // Let's see if the target supports this vector_shuffle.
5014 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
5017 // Return the new VECTOR_SHUFFLE node.
5018 MVT VT = MVT::getVectorVT(EVT, NumElts);
5019 std::vector<SDOperand> Ops;
5020 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
5022 AddToWorkList(LHS.Val);
5023 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
5024 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
5025 &ZeroOps[0], ZeroOps.size()));
5026 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
5027 &IdxOps[0], IdxOps.size()));
5028 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
5029 &Ops[0], Ops.size());
5030 if (VT != LHS.getValueType()) {
5031 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result);
5039 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
5040 SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
5041 // After legalize, the target may be depending on adds and other
5042 // binary ops to provide legal ways to construct constants or other
5043 // things. Simplifying them may result in a loss of legality.
5044 if (AfterLegalize) return SDOperand();
5046 MVT VT = N->getValueType(0);
5047 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
5049 MVT EltType = VT.getVectorElementType();
5050 SDOperand LHS = N->getOperand(0);
5051 SDOperand RHS = N->getOperand(1);
5052 SDOperand Shuffle = XformToShuffleWithZero(N);
5053 if (Shuffle.Val) return Shuffle;
5055 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
5057 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
5058 RHS.getOpcode() == ISD::BUILD_VECTOR) {
5059 SmallVector<SDOperand, 8> Ops;
5060 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
5061 SDOperand LHSOp = LHS.getOperand(i);
5062 SDOperand RHSOp = RHS.getOperand(i);
5063 // If these two elements can't be folded, bail out.
5064 if ((LHSOp.getOpcode() != ISD::UNDEF &&
5065 LHSOp.getOpcode() != ISD::Constant &&
5066 LHSOp.getOpcode() != ISD::ConstantFP) ||
5067 (RHSOp.getOpcode() != ISD::UNDEF &&
5068 RHSOp.getOpcode() != ISD::Constant &&
5069 RHSOp.getOpcode() != ISD::ConstantFP))
5071 // Can't fold divide by zero.
5072 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
5073 N->getOpcode() == ISD::FDIV) {
5074 if ((RHSOp.getOpcode() == ISD::Constant &&
5075 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
5076 (RHSOp.getOpcode() == ISD::ConstantFP &&
5077 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero()))
5080 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
5081 AddToWorkList(Ops.back().Val);
5082 assert((Ops.back().getOpcode() == ISD::UNDEF ||
5083 Ops.back().getOpcode() == ISD::Constant ||
5084 Ops.back().getOpcode() == ISD::ConstantFP) &&
5085 "Scalar binop didn't fold!");
5088 if (Ops.size() == LHS.getNumOperands()) {
5089 MVT VT = LHS.getValueType();
5090 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
5097 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
5098 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
5100 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
5101 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5102 // If we got a simplified select_cc node back from SimplifySelectCC, then
5103 // break it down into a new SETCC node, and a new SELECT node, and then return
5104 // the SELECT node, since we were called with a SELECT node.
5106 // Check to see if we got a select_cc back (to turn into setcc/select).
5107 // Otherwise, just return whatever node we got back, like fabs.
5108 if (SCC.getOpcode() == ISD::SELECT_CC) {
5109 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
5110 SCC.getOperand(0), SCC.getOperand(1),
5112 AddToWorkList(SETCC.Val);
5113 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
5114 SCC.getOperand(3), SETCC);
5121 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
5122 /// are the two values being selected between, see if we can simplify the
5123 /// select. Callers of this should assume that TheSelect is deleted if this
5124 /// returns true. As such, they should return the appropriate thing (e.g. the
5125 /// node) back to the top-level of the DAG combiner loop to avoid it being
5128 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
5131 // If this is a select from two identical things, try to pull the operation
5132 // through the select.
5133 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
5134 // If this is a load and the token chain is identical, replace the select
5135 // of two loads with a load through a select of the address to load from.
5136 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
5137 // constants have been dropped into the constant pool.
5138 if (LHS.getOpcode() == ISD::LOAD &&
5139 // Token chains must be identical.
5140 LHS.getOperand(0) == RHS.getOperand(0)) {
5141 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
5142 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
5144 // If this is an EXTLOAD, the VT's must match.
5145 if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
5146 // FIXME: this conflates two src values, discarding one. This is not
5147 // the right thing to do, but nothing uses srcvalues now. When they do,
5148 // turn SrcValue into a list of locations.
5150 if (TheSelect->getOpcode() == ISD::SELECT) {
5151 // Check that the condition doesn't reach either load. If so, folding
5152 // this will induce a cycle into the DAG.
5153 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
5154 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val)) {
5155 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
5156 TheSelect->getOperand(0), LLD->getBasePtr(),
5160 // Check that the condition doesn't reach either load. If so, folding
5161 // this will induce a cycle into the DAG.
5162 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
5163 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
5164 !LLD->isPredecessorOf(TheSelect->getOperand(1).Val) &&
5165 !RLD->isPredecessorOf(TheSelect->getOperand(1).Val)) {
5166 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
5167 TheSelect->getOperand(0),
5168 TheSelect->getOperand(1),
5169 LLD->getBasePtr(), RLD->getBasePtr(),
5170 TheSelect->getOperand(4));
5176 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
5177 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
5178 Addr,LLD->getSrcValue(),
5179 LLD->getSrcValueOffset(),
5181 LLD->getAlignment());
5183 Load = DAG.getExtLoad(LLD->getExtensionType(),
5184 TheSelect->getValueType(0),
5185 LLD->getChain(), Addr, LLD->getSrcValue(),
5186 LLD->getSrcValueOffset(),
5189 LLD->getAlignment());
5191 // Users of the select now use the result of the load.
5192 CombineTo(TheSelect, Load);
5194 // Users of the old loads now use the new load's chain. We know the
5195 // old-load value is dead now.
5196 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
5197 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
5207 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
5208 SDOperand N2, SDOperand N3,
5209 ISD::CondCode CC, bool NotExtCompare) {
5211 MVT VT = N2.getValueType();
5212 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
5213 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
5214 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
5216 // Determine if the condition we're dealing with is constant
5217 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
5218 if (SCC.Val) AddToWorkList(SCC.Val);
5219 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
5221 // fold select_cc true, x, y -> x
5222 if (SCCC && !SCCC->isNullValue())
5224 // fold select_cc false, x, y -> y
5225 if (SCCC && SCCC->isNullValue())
5228 // Check to see if we can simplify the select into an fabs node
5229 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
5230 // Allow either -0.0 or 0.0
5231 if (CFP->getValueAPF().isZero()) {
5232 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
5233 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
5234 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
5235 N2 == N3.getOperand(0))
5236 return DAG.getNode(ISD::FABS, VT, N0);
5238 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
5239 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
5240 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
5241 N2.getOperand(0) == N3)
5242 return DAG.getNode(ISD::FABS, VT, N3);
5246 // Check to see if we can perform the "gzip trick", transforming
5247 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
5248 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
5249 N0.getValueType().isInteger() &&
5250 N2.getValueType().isInteger() &&
5251 (N1C->isNullValue() || // (a < 0) ? b : 0
5252 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
5253 MVT XType = N0.getValueType();
5254 MVT AType = N2.getValueType();
5255 if (XType.bitsGE(AType)) {
5256 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
5257 // single-bit constant.
5258 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
5259 unsigned ShCtV = N2C->getAPIntValue().logBase2();
5260 ShCtV = XType.getSizeInBits()-ShCtV-1;
5261 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
5262 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
5263 AddToWorkList(Shift.Val);
5264 if (XType.bitsGT(AType)) {
5265 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
5266 AddToWorkList(Shift.Val);
5268 return DAG.getNode(ISD::AND, AType, Shift, N2);
5270 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
5271 DAG.getConstant(XType.getSizeInBits()-1,
5272 TLI.getShiftAmountTy()));
5273 AddToWorkList(Shift.Val);
5274 if (XType.bitsGT(AType)) {
5275 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
5276 AddToWorkList(Shift.Val);
5278 return DAG.getNode(ISD::AND, AType, Shift, N2);
5282 // fold select C, 16, 0 -> shl C, 4
5283 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
5284 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
5286 // If the caller doesn't want us to simplify this into a zext of a compare,
5288 if (NotExtCompare && N2C->getAPIntValue() == 1)
5291 // Get a SetCC of the condition
5292 // FIXME: Should probably make sure that setcc is legal if we ever have a
5293 // target where it isn't.
5294 SDOperand Temp, SCC;
5295 // cast from setcc result type to select result type
5296 if (AfterLegalize) {
5297 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
5298 if (N2.getValueType().bitsLT(SCC.getValueType()))
5299 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
5301 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
5303 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
5304 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
5306 AddToWorkList(SCC.Val);
5307 AddToWorkList(Temp.Val);
5309 if (N2C->getAPIntValue() == 1)
5311 // shl setcc result by log2 n2c
5312 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
5313 DAG.getConstant(N2C->getAPIntValue().logBase2(),
5314 TLI.getShiftAmountTy()));
5317 // Check to see if this is the equivalent of setcc
5318 // FIXME: Turn all of these into setcc if setcc if setcc is legal
5319 // otherwise, go ahead with the folds.
5320 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
5321 MVT XType = N0.getValueType();
5322 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) {
5323 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
5324 if (Res.getValueType() != VT)
5325 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
5329 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
5330 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
5331 TLI.isOperationLegal(ISD::CTLZ, XType)) {
5332 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
5333 return DAG.getNode(ISD::SRL, XType, Ctlz,
5334 DAG.getConstant(Log2_32(XType.getSizeInBits()),
5335 TLI.getShiftAmountTy()));
5337 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
5338 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
5339 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
5341 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
5342 DAG.getConstant(~0ULL, XType));
5343 return DAG.getNode(ISD::SRL, XType,
5344 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
5345 DAG.getConstant(XType.getSizeInBits()-1,
5346 TLI.getShiftAmountTy()));
5348 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
5349 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
5350 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
5351 DAG.getConstant(XType.getSizeInBits()-1,
5352 TLI.getShiftAmountTy()));
5353 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
5357 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
5358 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5359 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
5360 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
5361 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
5362 MVT XType = N0.getValueType();
5363 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
5364 DAG.getConstant(XType.getSizeInBits()-1,
5365 TLI.getShiftAmountTy()));
5366 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
5367 AddToWorkList(Shift.Val);
5368 AddToWorkList(Add.Val);
5369 return DAG.getNode(ISD::XOR, XType, Add, Shift);
5371 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
5372 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5373 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
5374 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
5375 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
5376 MVT XType = N0.getValueType();
5377 if (SubC->isNullValue() && XType.isInteger()) {
5378 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
5379 DAG.getConstant(XType.getSizeInBits()-1,
5380 TLI.getShiftAmountTy()));
5381 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
5382 AddToWorkList(Shift.Val);
5383 AddToWorkList(Add.Val);
5384 return DAG.getNode(ISD::XOR, XType, Add, Shift);
5392 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
5393 SDOperand DAGCombiner::SimplifySetCC(MVT VT, SDOperand N0,
5394 SDOperand N1, ISD::CondCode Cond,
5395 bool foldBooleans) {
5396 TargetLowering::DAGCombinerInfo
5397 DagCombineInfo(DAG, !AfterLegalize, false, this);
5398 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
5401 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
5402 /// return a DAG expression to select that will generate the same value by
5403 /// multiplying by a magic number. See:
5404 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5405 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
5406 std::vector<SDNode*> Built;
5407 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
5409 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5415 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
5416 /// return a DAG expression to select that will generate the same value by
5417 /// multiplying by a magic number. See:
5418 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5419 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
5420 std::vector<SDNode*> Built;
5421 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
5423 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5429 /// FindBaseOffset - Return true if base is known not to alias with anything
5430 /// but itself. Provides base object and offset as results.
5431 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
5432 // Assume it is a primitive operation.
5433 Base = Ptr; Offset = 0;
5435 // If it's an adding a simple constant then integrate the offset.
5436 if (Base.getOpcode() == ISD::ADD) {
5437 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
5438 Base = Base.getOperand(0);
5439 Offset += C->getValue();
5443 // If it's any of the following then it can't alias with anything but itself.
5444 return isa<FrameIndexSDNode>(Base) ||
5445 isa<ConstantPoolSDNode>(Base) ||
5446 isa<GlobalAddressSDNode>(Base);
5449 /// isAlias - Return true if there is any possibility that the two addresses
5451 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
5452 const Value *SrcValue1, int SrcValueOffset1,
5453 SDOperand Ptr2, int64_t Size2,
5454 const Value *SrcValue2, int SrcValueOffset2)
5456 // If they are the same then they must be aliases.
5457 if (Ptr1 == Ptr2) return true;
5459 // Gather base node and offset information.
5460 SDOperand Base1, Base2;
5461 int64_t Offset1, Offset2;
5462 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
5463 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
5465 // If they have a same base address then...
5466 if (Base1 == Base2) {
5467 // Check to see if the addresses overlap.
5468 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
5471 // If we know both bases then they can't alias.
5472 if (KnownBase1 && KnownBase2) return false;
5474 if (CombinerGlobalAA) {
5475 // Use alias analysis information.
5476 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
5477 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
5478 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
5479 AliasAnalysis::AliasResult AAResult =
5480 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
5481 if (AAResult == AliasAnalysis::NoAlias)
5485 // Otherwise we have to assume they alias.
5489 /// FindAliasInfo - Extracts the relevant alias information from the memory
5490 /// node. Returns true if the operand was a load.
5491 bool DAGCombiner::FindAliasInfo(SDNode *N,
5492 SDOperand &Ptr, int64_t &Size,
5493 const Value *&SrcValue, int &SrcValueOffset) {
5494 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5495 Ptr = LD->getBasePtr();
5496 Size = LD->getMemoryVT().getSizeInBits() >> 3;
5497 SrcValue = LD->getSrcValue();
5498 SrcValueOffset = LD->getSrcValueOffset();
5500 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5501 Ptr = ST->getBasePtr();
5502 Size = ST->getMemoryVT().getSizeInBits() >> 3;
5503 SrcValue = ST->getSrcValue();
5504 SrcValueOffset = ST->getSrcValueOffset();
5506 assert(0 && "FindAliasInfo expected a memory operand");
5512 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
5513 /// looking for aliasing nodes and adding them to the Aliases vector.
5514 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
5515 SmallVector<SDOperand, 8> &Aliases) {
5516 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
5517 std::set<SDNode *> Visited; // Visited node set.
5519 // Get alias information for node.
5522 const Value *SrcValue;
5524 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
5527 Chains.push_back(OriginalChain);
5529 // Look at each chain and determine if it is an alias. If so, add it to the
5530 // aliases list. If not, then continue up the chain looking for the next
5532 while (!Chains.empty()) {
5533 SDOperand Chain = Chains.back();
5536 // Don't bother if we've been before.
5537 if (Visited.find(Chain.Val) != Visited.end()) continue;
5538 Visited.insert(Chain.Val);
5540 switch (Chain.getOpcode()) {
5541 case ISD::EntryToken:
5542 // Entry token is ideal chain operand, but handled in FindBetterChain.
5547 // Get alias information for Chain.
5550 const Value *OpSrcValue;
5551 int OpSrcValueOffset;
5552 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
5553 OpSrcValue, OpSrcValueOffset);
5555 // If chain is alias then stop here.
5556 if (!(IsLoad && IsOpLoad) &&
5557 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
5558 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
5559 Aliases.push_back(Chain);
5561 // Look further up the chain.
5562 Chains.push_back(Chain.getOperand(0));
5563 // Clean up old chain.
5564 AddToWorkList(Chain.Val);
5569 case ISD::TokenFactor:
5570 // We have to check each of the operands of the token factor, so we queue
5571 // then up. Adding the operands to the queue (stack) in reverse order
5572 // maintains the original order and increases the likelihood that getNode
5573 // will find a matching token factor (CSE.)
5574 for (unsigned n = Chain.getNumOperands(); n;)
5575 Chains.push_back(Chain.getOperand(--n));
5576 // Eliminate the token factor if we can.
5577 AddToWorkList(Chain.Val);
5581 // For all other instructions we will just have to take what we can get.
5582 Aliases.push_back(Chain);
5588 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
5589 /// for a better chain (aliasing node.)
5590 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
5591 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
5593 // Accumulate all the aliases to this node.
5594 GatherAllAliases(N, OldChain, Aliases);
5596 if (Aliases.size() == 0) {
5597 // If no operands then chain to entry token.
5598 return DAG.getEntryNode();
5599 } else if (Aliases.size() == 1) {
5600 // If a single operand then chain to it. We don't need to revisit it.
5604 // Construct a custom tailored token factor.
5605 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5606 &Aliases[0], Aliases.size());
5608 // Make sure the old chain gets cleaned up.
5609 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
5614 // SelectionDAG::Combine - This is the entry point for the file.
5616 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
5617 if (!RunningAfterLegalize && ViewDAGCombine1)
5619 if (RunningAfterLegalize && ViewDAGCombine2)
5621 /// run - This is the main entry point to this class.
5623 DAGCombiner(*this, AA).Run(RunningAfterLegalize);