1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/Target/TargetData.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/SmallPtrSet.h"
39 #include "llvm/ADT/Statistic.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/MathExtras.h"
47 STATISTIC(NodesCombined , "Number of dag nodes combined");
48 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
49 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
54 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
55 cl::desc("Pop up a window to show dags before the first "
58 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
59 cl::desc("Pop up a window to show dags before the second "
62 static const bool ViewDAGCombine1 = false;
63 static const bool ViewDAGCombine2 = false;
67 CombinerAA("combiner-alias-analysis", cl::Hidden,
68 cl::desc("Turn on alias analysis during testing"));
71 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
72 cl::desc("Include global information in alias analysis"));
74 //------------------------------ DAGCombiner ---------------------------------//
76 class VISIBILITY_HIDDEN DAGCombiner {
81 // Worklist of all of the nodes that need to be simplified.
82 std::vector<SDNode*> WorkList;
84 // AA - Used for DAG load/store alias analysis.
87 /// AddUsersToWorkList - When an instruction is simplified, add all users of
88 /// the instruction to the work lists because they might get more simplified
91 void AddUsersToWorkList(SDNode *N) {
92 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
97 /// removeFromWorkList - remove all instances of N from the worklist.
99 void removeFromWorkList(SDNode *N) {
100 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
105 /// AddToWorkList - Add to the work list making sure it's instance is at the
106 /// the back (next to be processed.)
107 void AddToWorkList(SDNode *N) {
108 removeFromWorkList(N);
109 WorkList.push_back(N);
112 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
114 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
116 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
117 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
118 DOUT << " and " << NumTo-1 << " other values\n";
119 std::vector<SDNode*> NowDead;
120 DAG.ReplaceAllUsesWith(N, To, &NowDead);
123 // Push the new nodes and any users onto the worklist
124 for (unsigned i = 0, e = NumTo; i != e; ++i) {
125 AddToWorkList(To[i].Val);
126 AddUsersToWorkList(To[i].Val);
130 // Nodes can be reintroduced into the worklist. Make sure we do not
131 // process a node that has been replaced.
132 removeFromWorkList(N);
133 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
134 removeFromWorkList(NowDead[i]);
136 // Finally, since the node is now dead, remove it from the graph.
138 return SDOperand(N, 0);
141 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
142 return CombineTo(N, &Res, 1, AddTo);
145 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
147 SDOperand To[] = { Res0, Res1 };
148 return CombineTo(N, To, 2, AddTo);
152 /// SimplifyDemandedBits - Check the specified integer node value to see if
153 /// it can be simplified or if things it uses can be simplified by bit
154 /// propagation. If so, return true.
155 bool SimplifyDemandedBits(SDOperand Op) {
156 TargetLowering::TargetLoweringOpt TLO(DAG);
157 uint64_t KnownZero, KnownOne;
158 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
159 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
163 AddToWorkList(Op.Val);
165 // Replace the old value with the new one.
167 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
168 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
171 std::vector<SDNode*> NowDead;
172 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
174 // Push the new node and any (possibly new) users onto the worklist.
175 AddToWorkList(TLO.New.Val);
176 AddUsersToWorkList(TLO.New.Val);
178 // Nodes can end up on the worklist more than once. Make sure we do
179 // not process a node that has been replaced.
180 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
181 removeFromWorkList(NowDead[i]);
183 // Finally, if the node is now dead, remove it from the graph. The node
184 // may not be dead if the replacement process recursively simplified to
185 // something else needing this node.
186 if (TLO.Old.Val->use_empty()) {
187 removeFromWorkList(TLO.Old.Val);
189 // If the operands of this node are only used by the node, they will now
190 // be dead. Make sure to visit them first to delete dead nodes early.
191 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i)
192 if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
193 AddToWorkList(TLO.Old.Val->getOperand(i).Val);
195 DAG.DeleteNode(TLO.Old.Val);
200 bool CombineToPreIndexedLoadStore(SDNode *N);
201 bool CombineToPostIndexedLoadStore(SDNode *N);
204 /// visit - call the node-specific routine that knows how to fold each
205 /// particular type of node.
206 SDOperand visit(SDNode *N);
208 // Visitation implementation - Implement dag node combining for different
209 // node types. The semantics are as follows:
211 // SDOperand.Val == 0 - No change was made
212 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
213 // otherwise - N should be replaced by the returned Operand.
215 SDOperand visitTokenFactor(SDNode *N);
216 SDOperand visitADD(SDNode *N);
217 SDOperand visitSUB(SDNode *N);
218 SDOperand visitADDC(SDNode *N);
219 SDOperand visitADDE(SDNode *N);
220 SDOperand visitMUL(SDNode *N);
221 SDOperand visitSDIV(SDNode *N);
222 SDOperand visitUDIV(SDNode *N);
223 SDOperand visitSREM(SDNode *N);
224 SDOperand visitUREM(SDNode *N);
225 SDOperand visitMULHU(SDNode *N);
226 SDOperand visitMULHS(SDNode *N);
227 SDOperand visitAND(SDNode *N);
228 SDOperand visitOR(SDNode *N);
229 SDOperand visitXOR(SDNode *N);
230 SDOperand SimplifyVBinOp(SDNode *N);
231 SDOperand visitSHL(SDNode *N);
232 SDOperand visitSRA(SDNode *N);
233 SDOperand visitSRL(SDNode *N);
234 SDOperand visitCTLZ(SDNode *N);
235 SDOperand visitCTTZ(SDNode *N);
236 SDOperand visitCTPOP(SDNode *N);
237 SDOperand visitSELECT(SDNode *N);
238 SDOperand visitSELECT_CC(SDNode *N);
239 SDOperand visitSETCC(SDNode *N);
240 SDOperand visitSIGN_EXTEND(SDNode *N);
241 SDOperand visitZERO_EXTEND(SDNode *N);
242 SDOperand visitANY_EXTEND(SDNode *N);
243 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
244 SDOperand visitTRUNCATE(SDNode *N);
245 SDOperand visitBIT_CONVERT(SDNode *N);
246 SDOperand visitFADD(SDNode *N);
247 SDOperand visitFSUB(SDNode *N);
248 SDOperand visitFMUL(SDNode *N);
249 SDOperand visitFDIV(SDNode *N);
250 SDOperand visitFREM(SDNode *N);
251 SDOperand visitFCOPYSIGN(SDNode *N);
252 SDOperand visitSINT_TO_FP(SDNode *N);
253 SDOperand visitUINT_TO_FP(SDNode *N);
254 SDOperand visitFP_TO_SINT(SDNode *N);
255 SDOperand visitFP_TO_UINT(SDNode *N);
256 SDOperand visitFP_ROUND(SDNode *N);
257 SDOperand visitFP_ROUND_INREG(SDNode *N);
258 SDOperand visitFP_EXTEND(SDNode *N);
259 SDOperand visitFNEG(SDNode *N);
260 SDOperand visitFABS(SDNode *N);
261 SDOperand visitBRCOND(SDNode *N);
262 SDOperand visitBR_CC(SDNode *N);
263 SDOperand visitLOAD(SDNode *N);
264 SDOperand visitSTORE(SDNode *N);
265 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
266 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N);
267 SDOperand visitBUILD_VECTOR(SDNode *N);
268 SDOperand visitCONCAT_VECTORS(SDNode *N);
269 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
271 SDOperand XformToShuffleWithZero(SDNode *N);
272 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
274 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
275 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
276 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
277 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
278 SDOperand N3, ISD::CondCode CC,
279 bool NotExtCompare = false);
280 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
281 ISD::CondCode Cond, bool foldBooleans = true);
282 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
283 SDOperand BuildSDIV(SDNode *N);
284 SDOperand BuildUDIV(SDNode *N);
285 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
286 SDOperand ReduceLoadWidth(SDNode *N);
288 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
289 /// looking for aliasing nodes and adding them to the Aliases vector.
290 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
291 SmallVector<SDOperand, 8> &Aliases);
293 /// isAlias - Return true if there is any possibility that the two addresses
295 bool isAlias(SDOperand Ptr1, int64_t Size1,
296 const Value *SrcValue1, int SrcValueOffset1,
297 SDOperand Ptr2, int64_t Size2,
298 const Value *SrcValue2, int SrcValueOffset2);
300 /// FindAliasInfo - Extracts the relevant alias information from the memory
301 /// node. Returns true if the operand was a load.
302 bool FindAliasInfo(SDNode *N,
303 SDOperand &Ptr, int64_t &Size,
304 const Value *&SrcValue, int &SrcValueOffset);
306 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
307 /// looking for a better chain (aliasing node.)
308 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
311 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
313 TLI(D.getTargetLoweringInfo()),
314 AfterLegalize(false),
317 /// Run - runs the dag combiner on all nodes in the work list
318 void Run(bool RunningAfterLegalize);
322 //===----------------------------------------------------------------------===//
323 // TargetLowering::DAGCombinerInfo implementation
324 //===----------------------------------------------------------------------===//
326 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
327 ((DAGCombiner*)DC)->AddToWorkList(N);
330 SDOperand TargetLowering::DAGCombinerInfo::
331 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
332 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
335 SDOperand TargetLowering::DAGCombinerInfo::
336 CombineTo(SDNode *N, SDOperand Res) {
337 return ((DAGCombiner*)DC)->CombineTo(N, Res);
341 SDOperand TargetLowering::DAGCombinerInfo::
342 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
343 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
347 //===----------------------------------------------------------------------===//
349 //===----------------------------------------------------------------------===//
351 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
352 /// specified expression for the same cost as the expression itself, or 2 if we
353 /// can compute the negated form more cheaply than the expression itself.
354 static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) {
355 // fneg is removable even if it has multiple uses.
356 if (Op.getOpcode() == ISD::FNEG) return 2;
358 // Don't allow anything with multiple uses.
359 if (!Op.hasOneUse()) return 0;
361 // Don't recurse exponentially.
362 if (Depth > 6) return 0;
364 switch (Op.getOpcode()) {
365 default: return false;
366 case ISD::ConstantFP:
369 // FIXME: determine better conditions for this xform.
370 if (!UnsafeFPMath) return 0;
373 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
376 return isNegatibleForFree(Op.getOperand(1), Depth+1);
378 // We can't turn -(A-B) into B-A when we honor signed zeros.
379 if (!UnsafeFPMath) return 0;
386 if (HonorSignDependentRoundingFPMath()) return 0;
388 // -(X*Y) -> (-X * Y) or (X*-Y)
389 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
392 return isNegatibleForFree(Op.getOperand(1), Depth+1);
397 return isNegatibleForFree(Op.getOperand(0), Depth+1);
401 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
402 /// returns the newly negated expression.
403 static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
404 unsigned Depth = 0) {
405 // fneg is removable even if it has multiple uses.
406 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
408 // Don't allow anything with multiple uses.
409 assert(Op.hasOneUse() && "Unknown reuse!");
411 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
412 switch (Op.getOpcode()) {
413 default: assert(0 && "Unknown code");
414 case ISD::ConstantFP: {
415 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
417 return DAG.getConstantFP(V, Op.getValueType());
420 // FIXME: determine better conditions for this xform.
421 assert(UnsafeFPMath);
424 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
425 return DAG.getNode(ISD::FSUB, Op.getValueType(),
426 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
429 return DAG.getNode(ISD::FSUB, Op.getValueType(),
430 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1),
433 // We can't turn -(A-B) into B-A when we honor signed zeros.
434 assert(UnsafeFPMath);
437 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
438 if (N0CFP->getValueAPF().isZero())
439 return Op.getOperand(1);
442 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1),
447 assert(!HonorSignDependentRoundingFPMath());
450 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
451 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
452 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
456 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
458 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1));
463 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
464 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1));
469 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
470 // that selects between the values 1 and 0, making it equivalent to a setcc.
471 // Also, set the incoming LHS, RHS, and CC references to the appropriate
472 // nodes based on the type of node we are checking. This simplifies life a
473 // bit for the callers.
474 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
476 if (N.getOpcode() == ISD::SETCC) {
477 LHS = N.getOperand(0);
478 RHS = N.getOperand(1);
479 CC = N.getOperand(2);
482 if (N.getOpcode() == ISD::SELECT_CC &&
483 N.getOperand(2).getOpcode() == ISD::Constant &&
484 N.getOperand(3).getOpcode() == ISD::Constant &&
485 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
486 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
487 LHS = N.getOperand(0);
488 RHS = N.getOperand(1);
489 CC = N.getOperand(4);
495 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
496 // one use. If this is true, it allows the users to invert the operation for
497 // free when it is profitable to do so.
498 static bool isOneUseSetCC(SDOperand N) {
499 SDOperand N0, N1, N2;
500 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
505 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
506 MVT::ValueType VT = N0.getValueType();
507 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
508 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
509 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
510 if (isa<ConstantSDNode>(N1)) {
511 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
512 AddToWorkList(OpNode.Val);
513 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
514 } else if (N0.hasOneUse()) {
515 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
516 AddToWorkList(OpNode.Val);
517 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
520 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
521 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
522 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
523 if (isa<ConstantSDNode>(N0)) {
524 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
525 AddToWorkList(OpNode.Val);
526 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
527 } else if (N1.hasOneUse()) {
528 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
529 AddToWorkList(OpNode.Val);
530 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
536 //===----------------------------------------------------------------------===//
537 // Main DAG Combiner implementation
538 //===----------------------------------------------------------------------===//
540 void DAGCombiner::Run(bool RunningAfterLegalize) {
541 // set the instance variable, so that the various visit routines may use it.
542 AfterLegalize = RunningAfterLegalize;
544 // Add all the dag nodes to the worklist.
545 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
546 E = DAG.allnodes_end(); I != E; ++I)
547 WorkList.push_back(I);
549 // Create a dummy node (which is not added to allnodes), that adds a reference
550 // to the root node, preventing it from being deleted, and tracking any
551 // changes of the root.
552 HandleSDNode Dummy(DAG.getRoot());
554 // The root of the dag may dangle to deleted nodes until the dag combiner is
555 // done. Set it to null to avoid confusion.
556 DAG.setRoot(SDOperand());
558 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
559 TargetLowering::DAGCombinerInfo
560 DagCombineInfo(DAG, !RunningAfterLegalize, false, this);
562 // while the worklist isn't empty, inspect the node on the end of it and
563 // try and combine it.
564 while (!WorkList.empty()) {
565 SDNode *N = WorkList.back();
568 // If N has no uses, it is dead. Make sure to revisit all N's operands once
569 // N is deleted from the DAG, since they too may now be dead or may have a
570 // reduced number of uses, allowing other xforms.
571 if (N->use_empty() && N != &Dummy) {
572 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
573 AddToWorkList(N->getOperand(i).Val);
579 SDOperand RV = visit(N);
581 // If nothing happened, try a target-specific DAG combine.
583 assert(N->getOpcode() != ISD::DELETED_NODE &&
584 "Node was deleted but visit returned NULL!");
585 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
586 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
587 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
592 // If we get back the same node we passed in, rather than a new node or
593 // zero, we know that the node must have defined multiple values and
594 // CombineTo was used. Since CombineTo takes care of the worklist
595 // mechanics for us, we have no work to do in this case.
597 assert(N->getOpcode() != ISD::DELETED_NODE &&
598 RV.Val->getOpcode() != ISD::DELETED_NODE &&
599 "Node was deleted but visit returned new node!");
601 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
602 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
604 std::vector<SDNode*> NowDead;
605 if (N->getNumValues() == RV.Val->getNumValues())
606 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
608 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
610 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
613 // Push the new node and any users onto the worklist
614 AddToWorkList(RV.Val);
615 AddUsersToWorkList(RV.Val);
617 // Nodes can be reintroduced into the worklist. Make sure we do not
618 // process a node that has been replaced.
619 removeFromWorkList(N);
620 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
621 removeFromWorkList(NowDead[i]);
623 // Finally, since the node is now dead, remove it from the graph.
629 // If the root changed (e.g. it was a dead load, update the root).
630 DAG.setRoot(Dummy.getValue());
633 SDOperand DAGCombiner::visit(SDNode *N) {
634 switch(N->getOpcode()) {
636 case ISD::TokenFactor: return visitTokenFactor(N);
637 case ISD::ADD: return visitADD(N);
638 case ISD::SUB: return visitSUB(N);
639 case ISD::ADDC: return visitADDC(N);
640 case ISD::ADDE: return visitADDE(N);
641 case ISD::MUL: return visitMUL(N);
642 case ISD::SDIV: return visitSDIV(N);
643 case ISD::UDIV: return visitUDIV(N);
644 case ISD::SREM: return visitSREM(N);
645 case ISD::UREM: return visitUREM(N);
646 case ISD::MULHU: return visitMULHU(N);
647 case ISD::MULHS: return visitMULHS(N);
648 case ISD::AND: return visitAND(N);
649 case ISD::OR: return visitOR(N);
650 case ISD::XOR: return visitXOR(N);
651 case ISD::SHL: return visitSHL(N);
652 case ISD::SRA: return visitSRA(N);
653 case ISD::SRL: return visitSRL(N);
654 case ISD::CTLZ: return visitCTLZ(N);
655 case ISD::CTTZ: return visitCTTZ(N);
656 case ISD::CTPOP: return visitCTPOP(N);
657 case ISD::SELECT: return visitSELECT(N);
658 case ISD::SELECT_CC: return visitSELECT_CC(N);
659 case ISD::SETCC: return visitSETCC(N);
660 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
661 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
662 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
663 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
664 case ISD::TRUNCATE: return visitTRUNCATE(N);
665 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
666 case ISD::FADD: return visitFADD(N);
667 case ISD::FSUB: return visitFSUB(N);
668 case ISD::FMUL: return visitFMUL(N);
669 case ISD::FDIV: return visitFDIV(N);
670 case ISD::FREM: return visitFREM(N);
671 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
672 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
673 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
674 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
675 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
676 case ISD::FP_ROUND: return visitFP_ROUND(N);
677 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
678 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
679 case ISD::FNEG: return visitFNEG(N);
680 case ISD::FABS: return visitFABS(N);
681 case ISD::BRCOND: return visitBRCOND(N);
682 case ISD::BR_CC: return visitBR_CC(N);
683 case ISD::LOAD: return visitLOAD(N);
684 case ISD::STORE: return visitSTORE(N);
685 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
686 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
687 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
688 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
689 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
694 /// getInputChainForNode - Given a node, return its input chain if it has one,
695 /// otherwise return a null sd operand.
696 static SDOperand getInputChainForNode(SDNode *N) {
697 if (unsigned NumOps = N->getNumOperands()) {
698 if (N->getOperand(0).getValueType() == MVT::Other)
699 return N->getOperand(0);
700 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
701 return N->getOperand(NumOps-1);
702 for (unsigned i = 1; i < NumOps-1; ++i)
703 if (N->getOperand(i).getValueType() == MVT::Other)
704 return N->getOperand(i);
706 return SDOperand(0, 0);
709 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
710 // If N has two operands, where one has an input chain equal to the other,
711 // the 'other' chain is redundant.
712 if (N->getNumOperands() == 2) {
713 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
714 return N->getOperand(0);
715 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
716 return N->getOperand(1);
719 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
720 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
721 SmallPtrSet<SDNode*, 16> SeenOps;
722 bool Changed = false; // If we should replace this token factor.
724 // Start out with this token factor.
727 // Iterate through token factors. The TFs grows when new token factors are
729 for (unsigned i = 0; i < TFs.size(); ++i) {
732 // Check each of the operands.
733 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
734 SDOperand Op = TF->getOperand(i);
736 switch (Op.getOpcode()) {
737 case ISD::EntryToken:
738 // Entry tokens don't need to be added to the list. They are
743 case ISD::TokenFactor:
744 if ((CombinerAA || Op.hasOneUse()) &&
745 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
746 // Queue up for processing.
747 TFs.push_back(Op.Val);
748 // Clean up in case the token factor is removed.
749 AddToWorkList(Op.Val);
756 // Only add if it isn't already in the list.
757 if (SeenOps.insert(Op.Val))
768 // If we've change things around then replace token factor.
770 if (Ops.size() == 0) {
771 // The entry token is the only possible outcome.
772 Result = DAG.getEntryNode();
774 // New and improved token factor.
775 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
778 // Don't add users to work list.
779 return CombineTo(N, Result, false);
786 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
787 MVT::ValueType VT = N0.getValueType();
788 SDOperand N00 = N0.getOperand(0);
789 SDOperand N01 = N0.getOperand(1);
790 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
791 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
792 isa<ConstantSDNode>(N00.getOperand(1))) {
793 N0 = DAG.getNode(ISD::ADD, VT,
794 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
795 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
796 return DAG.getNode(ISD::ADD, VT, N0, N1);
802 SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
804 MVT::ValueType VT = N->getValueType(0);
805 unsigned Opc = N->getOpcode();
806 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
807 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
808 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
809 ISD::CondCode CC = ISD::SETCC_INVALID;
811 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
813 SDOperand CCOp = Slct.getOperand(0);
814 if (CCOp.getOpcode() == ISD::SETCC)
815 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
818 bool DoXform = false;
820 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
822 if (LHS.getOpcode() == ISD::Constant &&
823 cast<ConstantSDNode>(LHS)->isNullValue())
825 else if (CC != ISD::SETCC_INVALID &&
826 RHS.getOpcode() == ISD::Constant &&
827 cast<ConstantSDNode>(RHS)->isNullValue()) {
829 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType()
830 : Slct.getOperand(0).getOperand(0).getValueType());
831 CC = ISD::getSetCCInverse(CC, isInt);
837 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS);
839 return DAG.getSelectCC(OtherOp, Result,
840 Slct.getOperand(0), Slct.getOperand(1), CC);
841 SDOperand CCOp = Slct.getOperand(0);
843 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
844 CCOp.getOperand(1), CC);
845 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
850 SDOperand DAGCombiner::visitADD(SDNode *N) {
851 SDOperand N0 = N->getOperand(0);
852 SDOperand N1 = N->getOperand(1);
853 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
854 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
855 MVT::ValueType VT = N0.getValueType();
858 if (MVT::isVector(VT)) {
859 SDOperand FoldedVOp = SimplifyVBinOp(N);
860 if (FoldedVOp.Val) return FoldedVOp;
863 // fold (add x, undef) -> undef
864 if (N0.getOpcode() == ISD::UNDEF)
866 if (N1.getOpcode() == ISD::UNDEF)
868 // fold (add c1, c2) -> c1+c2
870 return DAG.getNode(ISD::ADD, VT, N0, N1);
871 // canonicalize constant to RHS
873 return DAG.getNode(ISD::ADD, VT, N1, N0);
874 // fold (add x, 0) -> x
875 if (N1C && N1C->isNullValue())
877 // fold ((c1-A)+c2) -> (c1+c2)-A
878 if (N1C && N0.getOpcode() == ISD::SUB)
879 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
880 return DAG.getNode(ISD::SUB, VT,
881 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
884 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
887 // fold ((0-A) + B) -> B-A
888 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
889 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
890 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
891 // fold (A + (0-B)) -> A-B
892 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
893 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
894 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
895 // fold (A+(B-A)) -> B
896 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
897 return N1.getOperand(0);
899 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
900 return SDOperand(N, 0);
902 // fold (a+b) -> (a|b) iff a and b share no bits.
903 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
904 uint64_t LHSZero, LHSOne;
905 uint64_t RHSZero, RHSOne;
906 uint64_t Mask = MVT::getIntVTBitMask(VT);
907 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
909 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
911 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
912 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
913 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
914 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
915 return DAG.getNode(ISD::OR, VT, N0, N1);
919 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
920 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
921 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
922 if (Result.Val) return Result;
924 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
925 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
926 if (Result.Val) return Result;
929 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
930 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
931 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG);
932 if (Result.Val) return Result;
934 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
935 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
936 if (Result.Val) return Result;
942 SDOperand DAGCombiner::visitADDC(SDNode *N) {
943 SDOperand N0 = N->getOperand(0);
944 SDOperand N1 = N->getOperand(1);
945 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
946 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
947 MVT::ValueType VT = N0.getValueType();
949 // If the flag result is dead, turn this into an ADD.
950 if (N->hasNUsesOfValue(0, 1))
951 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
952 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
954 // canonicalize constant to RHS.
956 SDOperand Ops[] = { N1, N0 };
957 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
960 // fold (addc x, 0) -> x + no carry out
961 if (N1C && N1C->isNullValue())
962 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
964 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
965 uint64_t LHSZero, LHSOne;
966 uint64_t RHSZero, RHSOne;
967 uint64_t Mask = MVT::getIntVTBitMask(VT);
968 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
970 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
972 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
973 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
974 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
975 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
976 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
977 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
983 SDOperand DAGCombiner::visitADDE(SDNode *N) {
984 SDOperand N0 = N->getOperand(0);
985 SDOperand N1 = N->getOperand(1);
986 SDOperand CarryIn = N->getOperand(2);
987 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
988 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
989 //MVT::ValueType VT = N0.getValueType();
991 // canonicalize constant to RHS
993 SDOperand Ops[] = { N1, N0, CarryIn };
994 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
997 // fold (adde x, y, false) -> (addc x, y)
998 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
999 SDOperand Ops[] = { N1, N0 };
1000 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
1008 SDOperand DAGCombiner::visitSUB(SDNode *N) {
1009 SDOperand N0 = N->getOperand(0);
1010 SDOperand N1 = N->getOperand(1);
1011 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1012 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1013 MVT::ValueType VT = N0.getValueType();
1016 if (MVT::isVector(VT)) {
1017 SDOperand FoldedVOp = SimplifyVBinOp(N);
1018 if (FoldedVOp.Val) return FoldedVOp;
1021 // fold (sub x, x) -> 0
1023 return DAG.getConstant(0, N->getValueType(0));
1024 // fold (sub c1, c2) -> c1-c2
1026 return DAG.getNode(ISD::SUB, VT, N0, N1);
1027 // fold (sub x, c) -> (add x, -c)
1029 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
1030 // fold (A+B)-A -> B
1031 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1032 return N0.getOperand(1);
1033 // fold (A+B)-B -> A
1034 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1035 return N0.getOperand(0);
1036 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1037 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
1038 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
1039 if (Result.Val) return Result;
1041 // If either operand of a sub is undef, the result is undef
1042 if (N0.getOpcode() == ISD::UNDEF)
1044 if (N1.getOpcode() == ISD::UNDEF)
1050 SDOperand DAGCombiner::visitMUL(SDNode *N) {
1051 SDOperand N0 = N->getOperand(0);
1052 SDOperand N1 = N->getOperand(1);
1053 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1054 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1055 MVT::ValueType VT = N0.getValueType();
1058 if (MVT::isVector(VT)) {
1059 SDOperand FoldedVOp = SimplifyVBinOp(N);
1060 if (FoldedVOp.Val) return FoldedVOp;
1063 // fold (mul x, undef) -> 0
1064 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1065 return DAG.getConstant(0, VT);
1066 // fold (mul c1, c2) -> c1*c2
1068 return DAG.getNode(ISD::MUL, VT, N0, N1);
1069 // canonicalize constant to RHS
1071 return DAG.getNode(ISD::MUL, VT, N1, N0);
1072 // fold (mul x, 0) -> 0
1073 if (N1C && N1C->isNullValue())
1075 // fold (mul x, -1) -> 0-x
1076 if (N1C && N1C->isAllOnesValue())
1077 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1078 // fold (mul x, (1 << c)) -> x << c
1079 if (N1C && isPowerOf2_64(N1C->getValue()))
1080 return DAG.getNode(ISD::SHL, VT, N0,
1081 DAG.getConstant(Log2_64(N1C->getValue()),
1082 TLI.getShiftAmountTy()));
1083 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1084 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
1085 // FIXME: If the input is something that is easily negated (e.g. a
1086 // single-use add), we should put the negate there.
1087 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
1088 DAG.getNode(ISD::SHL, VT, N0,
1089 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
1090 TLI.getShiftAmountTy())));
1093 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1094 if (N1C && N0.getOpcode() == ISD::SHL &&
1095 isa<ConstantSDNode>(N0.getOperand(1))) {
1096 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
1097 AddToWorkList(C3.Val);
1098 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
1101 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1104 SDOperand Sh(0,0), Y(0,0);
1105 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1106 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1107 N0.Val->hasOneUse()) {
1109 } else if (N1.getOpcode() == ISD::SHL &&
1110 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
1114 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
1115 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
1118 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1119 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1120 isa<ConstantSDNode>(N0.getOperand(1))) {
1121 return DAG.getNode(ISD::ADD, VT,
1122 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
1123 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
1127 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
1134 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
1135 SDOperand N0 = N->getOperand(0);
1136 SDOperand N1 = N->getOperand(1);
1137 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1138 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1139 MVT::ValueType VT = N->getValueType(0);
1142 if (MVT::isVector(VT)) {
1143 SDOperand FoldedVOp = SimplifyVBinOp(N);
1144 if (FoldedVOp.Val) return FoldedVOp;
1147 // fold (sdiv c1, c2) -> c1/c2
1148 if (N0C && N1C && !N1C->isNullValue())
1149 return DAG.getNode(ISD::SDIV, VT, N0, N1);
1150 // fold (sdiv X, 1) -> X
1151 if (N1C && N1C->getSignExtended() == 1LL)
1153 // fold (sdiv X, -1) -> 0-X
1154 if (N1C && N1C->isAllOnesValue())
1155 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1156 // If we know the sign bits of both operands are zero, strength reduce to a
1157 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1158 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1159 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1160 DAG.MaskedValueIsZero(N0, SignBit))
1161 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
1162 // fold (sdiv X, pow2) -> simple ops after legalize
1163 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
1164 (isPowerOf2_64(N1C->getSignExtended()) ||
1165 isPowerOf2_64(-N1C->getSignExtended()))) {
1166 // If dividing by powers of two is cheap, then don't perform the following
1168 if (TLI.isPow2DivCheap())
1170 int64_t pow2 = N1C->getSignExtended();
1171 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1172 unsigned lg2 = Log2_64(abs2);
1173 // Splat the sign bit into the register
1174 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
1175 DAG.getConstant(MVT::getSizeInBits(VT)-1,
1176 TLI.getShiftAmountTy()));
1177 AddToWorkList(SGN.Val);
1178 // Add (N0 < 0) ? abs2 - 1 : 0;
1179 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
1180 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
1181 TLI.getShiftAmountTy()));
1182 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
1183 AddToWorkList(SRL.Val);
1184 AddToWorkList(ADD.Val); // Divide by pow2
1185 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
1186 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
1187 // If we're dividing by a positive value, we're done. Otherwise, we must
1188 // negate the result.
1191 AddToWorkList(SRA.Val);
1192 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
1194 // if integer divide is expensive and we satisfy the requirements, emit an
1195 // alternate sequence.
1196 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
1197 !TLI.isIntDivCheap()) {
1198 SDOperand Op = BuildSDIV(N);
1199 if (Op.Val) return Op;
1203 if (N0.getOpcode() == ISD::UNDEF)
1204 return DAG.getConstant(0, VT);
1205 // X / undef -> undef
1206 if (N1.getOpcode() == ISD::UNDEF)
1212 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
1213 SDOperand N0 = N->getOperand(0);
1214 SDOperand N1 = N->getOperand(1);
1215 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1216 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1217 MVT::ValueType VT = N->getValueType(0);
1220 if (MVT::isVector(VT)) {
1221 SDOperand FoldedVOp = SimplifyVBinOp(N);
1222 if (FoldedVOp.Val) return FoldedVOp;
1225 // fold (udiv c1, c2) -> c1/c2
1226 if (N0C && N1C && !N1C->isNullValue())
1227 return DAG.getNode(ISD::UDIV, VT, N0, N1);
1228 // fold (udiv x, (1 << c)) -> x >>u c
1229 if (N1C && isPowerOf2_64(N1C->getValue()))
1230 return DAG.getNode(ISD::SRL, VT, N0,
1231 DAG.getConstant(Log2_64(N1C->getValue()),
1232 TLI.getShiftAmountTy()));
1233 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1234 if (N1.getOpcode() == ISD::SHL) {
1235 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1236 if (isPowerOf2_64(SHC->getValue())) {
1237 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
1238 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
1239 DAG.getConstant(Log2_64(SHC->getValue()),
1241 AddToWorkList(Add.Val);
1242 return DAG.getNode(ISD::SRL, VT, N0, Add);
1246 // fold (udiv x, c) -> alternate
1247 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1248 SDOperand Op = BuildUDIV(N);
1249 if (Op.Val) return Op;
1253 if (N0.getOpcode() == ISD::UNDEF)
1254 return DAG.getConstant(0, VT);
1255 // X / undef -> undef
1256 if (N1.getOpcode() == ISD::UNDEF)
1262 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1263 SDOperand N0 = N->getOperand(0);
1264 SDOperand N1 = N->getOperand(1);
1265 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1266 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1267 MVT::ValueType VT = N->getValueType(0);
1269 // fold (srem c1, c2) -> c1%c2
1270 if (N0C && N1C && !N1C->isNullValue())
1271 return DAG.getNode(ISD::SREM, VT, N0, N1);
1272 // If we know the sign bits of both operands are zero, strength reduce to a
1273 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1274 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1275 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1276 DAG.MaskedValueIsZero(N0, SignBit))
1277 return DAG.getNode(ISD::UREM, VT, N0, N1);
1279 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1280 // the remainder operation.
1281 if (N1C && !N1C->isNullValue()) {
1282 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1283 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1284 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1285 AddToWorkList(Div.Val);
1286 AddToWorkList(Mul.Val);
1291 if (N0.getOpcode() == ISD::UNDEF)
1292 return DAG.getConstant(0, VT);
1293 // X % undef -> undef
1294 if (N1.getOpcode() == ISD::UNDEF)
1300 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1301 SDOperand N0 = N->getOperand(0);
1302 SDOperand N1 = N->getOperand(1);
1303 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1304 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1305 MVT::ValueType VT = N->getValueType(0);
1307 // fold (urem c1, c2) -> c1%c2
1308 if (N0C && N1C && !N1C->isNullValue())
1309 return DAG.getNode(ISD::UREM, VT, N0, N1);
1310 // fold (urem x, pow2) -> (and x, pow2-1)
1311 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1312 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1313 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1314 if (N1.getOpcode() == ISD::SHL) {
1315 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1316 if (isPowerOf2_64(SHC->getValue())) {
1317 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1318 AddToWorkList(Add.Val);
1319 return DAG.getNode(ISD::AND, VT, N0, Add);
1324 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1325 // the remainder operation.
1326 if (N1C && !N1C->isNullValue()) {
1327 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1328 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1329 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1330 AddToWorkList(Div.Val);
1331 AddToWorkList(Mul.Val);
1336 if (N0.getOpcode() == ISD::UNDEF)
1337 return DAG.getConstant(0, VT);
1338 // X % undef -> undef
1339 if (N1.getOpcode() == ISD::UNDEF)
1345 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1346 SDOperand N0 = N->getOperand(0);
1347 SDOperand N1 = N->getOperand(1);
1348 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1349 MVT::ValueType VT = N->getValueType(0);
1351 // fold (mulhs x, 0) -> 0
1352 if (N1C && N1C->isNullValue())
1354 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1355 if (N1C && N1C->getValue() == 1)
1356 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1357 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1358 TLI.getShiftAmountTy()));
1359 // fold (mulhs x, undef) -> 0
1360 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1361 return DAG.getConstant(0, VT);
1366 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1367 SDOperand N0 = N->getOperand(0);
1368 SDOperand N1 = N->getOperand(1);
1369 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1370 MVT::ValueType VT = N->getValueType(0);
1372 // fold (mulhu x, 0) -> 0
1373 if (N1C && N1C->isNullValue())
1375 // fold (mulhu x, 1) -> 0
1376 if (N1C && N1C->getValue() == 1)
1377 return DAG.getConstant(0, N0.getValueType());
1378 // fold (mulhu x, undef) -> 0
1379 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1380 return DAG.getConstant(0, VT);
1385 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1386 /// two operands of the same opcode, try to simplify it.
1387 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1388 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1389 MVT::ValueType VT = N0.getValueType();
1390 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1392 // For each of OP in AND/OR/XOR:
1393 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1394 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1395 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1396 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1397 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1398 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1399 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1400 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1401 N0.getOperand(0).getValueType(),
1402 N0.getOperand(0), N1.getOperand(0));
1403 AddToWorkList(ORNode.Val);
1404 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1407 // For each of OP in SHL/SRL/SRA/AND...
1408 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1409 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1410 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1411 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1412 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1413 N0.getOperand(1) == N1.getOperand(1)) {
1414 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1415 N0.getOperand(0).getValueType(),
1416 N0.getOperand(0), N1.getOperand(0));
1417 AddToWorkList(ORNode.Val);
1418 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1424 SDOperand DAGCombiner::visitAND(SDNode *N) {
1425 SDOperand N0 = N->getOperand(0);
1426 SDOperand N1 = N->getOperand(1);
1427 SDOperand LL, LR, RL, RR, CC0, CC1;
1428 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1429 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1430 MVT::ValueType VT = N1.getValueType();
1433 if (MVT::isVector(VT)) {
1434 SDOperand FoldedVOp = SimplifyVBinOp(N);
1435 if (FoldedVOp.Val) return FoldedVOp;
1438 // fold (and x, undef) -> 0
1439 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1440 return DAG.getConstant(0, VT);
1441 // fold (and c1, c2) -> c1&c2
1443 return DAG.getNode(ISD::AND, VT, N0, N1);
1444 // canonicalize constant to RHS
1446 return DAG.getNode(ISD::AND, VT, N1, N0);
1447 // fold (and x, -1) -> x
1448 if (N1C && N1C->isAllOnesValue())
1450 // if (and x, c) is known to be zero, return 0
1451 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1452 return DAG.getConstant(0, VT);
1454 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1457 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1458 if (N1C && N0.getOpcode() == ISD::OR)
1459 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1460 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1462 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1463 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1464 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1465 if (DAG.MaskedValueIsZero(N0.getOperand(0),
1466 ~N1C->getValue() & InMask)) {
1467 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1470 // Replace uses of the AND with uses of the Zero extend node.
1473 // We actually want to replace all uses of the any_extend with the
1474 // zero_extend, to avoid duplicating things. This will later cause this
1475 // AND to be folded.
1476 CombineTo(N0.Val, Zext);
1477 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1480 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1481 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1482 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1483 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1485 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1486 MVT::isInteger(LL.getValueType())) {
1487 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1488 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1489 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1490 AddToWorkList(ORNode.Val);
1491 return DAG.getSetCC(VT, ORNode, LR, Op1);
1493 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1494 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1495 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1496 AddToWorkList(ANDNode.Val);
1497 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1499 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1500 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1501 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1502 AddToWorkList(ORNode.Val);
1503 return DAG.getSetCC(VT, ORNode, LR, Op1);
1506 // canonicalize equivalent to ll == rl
1507 if (LL == RR && LR == RL) {
1508 Op1 = ISD::getSetCCSwappedOperands(Op1);
1511 if (LL == RL && LR == RR) {
1512 bool isInteger = MVT::isInteger(LL.getValueType());
1513 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1514 if (Result != ISD::SETCC_INVALID)
1515 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1519 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1520 if (N0.getOpcode() == N1.getOpcode()) {
1521 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1522 if (Tmp.Val) return Tmp;
1525 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1526 // fold (and (sra)) -> (and (srl)) when possible.
1527 if (!MVT::isVector(VT) &&
1528 SimplifyDemandedBits(SDOperand(N, 0)))
1529 return SDOperand(N, 0);
1530 // fold (zext_inreg (extload x)) -> (zextload x)
1531 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
1532 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1533 MVT::ValueType EVT = LN0->getLoadedVT();
1534 // If we zero all the possible extended bits, then we can turn this into
1535 // a zextload if we are running before legalize or the operation is legal.
1536 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1537 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1538 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1539 LN0->getBasePtr(), LN0->getSrcValue(),
1540 LN0->getSrcValueOffset(), EVT,
1542 LN0->getAlignment());
1544 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1545 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1548 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1549 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
1551 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1552 MVT::ValueType EVT = LN0->getLoadedVT();
1553 // If we zero all the possible extended bits, then we can turn this into
1554 // a zextload if we are running before legalize or the operation is legal.
1555 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1556 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1557 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1558 LN0->getBasePtr(), LN0->getSrcValue(),
1559 LN0->getSrcValueOffset(), EVT,
1561 LN0->getAlignment());
1563 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1564 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1568 // fold (and (load x), 255) -> (zextload x, i8)
1569 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1570 if (N1C && N0.getOpcode() == ISD::LOAD) {
1571 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1572 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1573 LN0->getAddressingMode() == ISD::UNINDEXED &&
1575 MVT::ValueType EVT, LoadedVT;
1576 if (N1C->getValue() == 255)
1578 else if (N1C->getValue() == 65535)
1580 else if (N1C->getValue() == ~0U)
1585 LoadedVT = LN0->getLoadedVT();
1586 if (EVT != MVT::Other && LoadedVT > EVT &&
1587 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1588 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1589 // For big endian targets, we need to add an offset to the pointer to
1590 // load the correct bytes. For little endian systems, we merely need to
1591 // read fewer bytes from the same pointer.
1593 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1594 SDOperand NewPtr = LN0->getBasePtr();
1595 if (!TLI.isLittleEndian())
1596 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1597 DAG.getConstant(PtrOff, PtrType));
1598 AddToWorkList(NewPtr.Val);
1600 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1601 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
1602 LN0->isVolatile(), LN0->getAlignment());
1604 CombineTo(N0.Val, Load, Load.getValue(1));
1605 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1613 SDOperand DAGCombiner::visitOR(SDNode *N) {
1614 SDOperand N0 = N->getOperand(0);
1615 SDOperand N1 = N->getOperand(1);
1616 SDOperand LL, LR, RL, RR, CC0, CC1;
1617 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1618 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1619 MVT::ValueType VT = N1.getValueType();
1620 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1623 if (MVT::isVector(VT)) {
1624 SDOperand FoldedVOp = SimplifyVBinOp(N);
1625 if (FoldedVOp.Val) return FoldedVOp;
1628 // fold (or x, undef) -> -1
1629 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1630 return DAG.getConstant(~0ULL, VT);
1631 // fold (or c1, c2) -> c1|c2
1633 return DAG.getNode(ISD::OR, VT, N0, N1);
1634 // canonicalize constant to RHS
1636 return DAG.getNode(ISD::OR, VT, N1, N0);
1637 // fold (or x, 0) -> x
1638 if (N1C && N1C->isNullValue())
1640 // fold (or x, -1) -> -1
1641 if (N1C && N1C->isAllOnesValue())
1643 // fold (or x, c) -> c iff (x & ~c) == 0
1645 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1648 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1651 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1652 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1653 isa<ConstantSDNode>(N0.getOperand(1))) {
1654 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1655 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1657 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1659 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1660 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1661 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1662 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1664 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1665 MVT::isInteger(LL.getValueType())) {
1666 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1667 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1668 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1669 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1670 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1671 AddToWorkList(ORNode.Val);
1672 return DAG.getSetCC(VT, ORNode, LR, Op1);
1674 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1675 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1676 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1677 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1678 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1679 AddToWorkList(ANDNode.Val);
1680 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1683 // canonicalize equivalent to ll == rl
1684 if (LL == RR && LR == RL) {
1685 Op1 = ISD::getSetCCSwappedOperands(Op1);
1688 if (LL == RL && LR == RR) {
1689 bool isInteger = MVT::isInteger(LL.getValueType());
1690 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1691 if (Result != ISD::SETCC_INVALID)
1692 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1696 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1697 if (N0.getOpcode() == N1.getOpcode()) {
1698 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1699 if (Tmp.Val) return Tmp;
1702 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1703 if (N0.getOpcode() == ISD::AND &&
1704 N1.getOpcode() == ISD::AND &&
1705 N0.getOperand(1).getOpcode() == ISD::Constant &&
1706 N1.getOperand(1).getOpcode() == ISD::Constant &&
1707 // Don't increase # computations.
1708 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1709 // We can only do this xform if we know that bits from X that are set in C2
1710 // but not in C1 are already zero. Likewise for Y.
1711 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1712 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1714 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1715 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1716 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1717 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1722 // See if this is some rotate idiom.
1723 if (SDNode *Rot = MatchRotate(N0, N1))
1724 return SDOperand(Rot, 0);
1730 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1731 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1732 if (Op.getOpcode() == ISD::AND) {
1733 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1734 Mask = Op.getOperand(1);
1735 Op = Op.getOperand(0);
1741 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1749 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1750 // idioms for rotate, and if the target supports rotation instructions, generate
1752 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1753 // Must be a legal type. Expanded an promoted things won't work with rotates.
1754 MVT::ValueType VT = LHS.getValueType();
1755 if (!TLI.isTypeLegal(VT)) return 0;
1757 // The target must have at least one rotate flavor.
1758 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1759 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1760 if (!HasROTL && !HasROTR) return 0;
1762 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1763 SDOperand LHSShift; // The shift.
1764 SDOperand LHSMask; // AND value if any.
1765 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1766 return 0; // Not part of a rotate.
1768 SDOperand RHSShift; // The shift.
1769 SDOperand RHSMask; // AND value if any.
1770 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1771 return 0; // Not part of a rotate.
1773 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1774 return 0; // Not shifting the same value.
1776 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1777 return 0; // Shifts must disagree.
1779 // Canonicalize shl to left side in a shl/srl pair.
1780 if (RHSShift.getOpcode() == ISD::SHL) {
1781 std::swap(LHS, RHS);
1782 std::swap(LHSShift, RHSShift);
1783 std::swap(LHSMask , RHSMask );
1786 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1787 SDOperand LHSShiftArg = LHSShift.getOperand(0);
1788 SDOperand LHSShiftAmt = LHSShift.getOperand(1);
1789 SDOperand RHSShiftAmt = RHSShift.getOperand(1);
1791 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1792 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1793 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
1794 RHSShiftAmt.getOpcode() == ISD::Constant) {
1795 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
1796 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
1797 if ((LShVal + RShVal) != OpSizeInBits)
1802 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
1804 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
1806 // If there is an AND of either shifted operand, apply it to the result.
1807 if (LHSMask.Val || RHSMask.Val) {
1808 uint64_t Mask = MVT::getIntVTBitMask(VT);
1811 uint64_t RHSBits = (1ULL << LShVal)-1;
1812 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1815 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1816 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1819 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1825 // If there is a mask here, and we have a variable shift, we can't be sure
1826 // that we're masking out the right stuff.
1827 if (LHSMask.Val || RHSMask.Val)
1830 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1831 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1832 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
1833 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
1834 if (ConstantSDNode *SUBC =
1835 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
1836 if (SUBC->getValue() == OpSizeInBits)
1838 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1840 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1844 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1845 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1846 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
1847 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
1848 if (ConstantSDNode *SUBC =
1849 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
1850 if (SUBC->getValue() == OpSizeInBits)
1852 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1854 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1858 // Look for sign/zext/any-extended cases:
1859 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1860 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1861 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
1862 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1863 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1864 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
1865 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
1866 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
1867 if (RExtOp0.getOpcode() == ISD::SUB &&
1868 RExtOp0.getOperand(1) == LExtOp0) {
1869 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1871 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1872 // (rotl x, (sub 32, y))
1873 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
1874 if (SUBC->getValue() == OpSizeInBits) {
1876 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1878 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1881 } else if (LExtOp0.getOpcode() == ISD::SUB &&
1882 RExtOp0 == LExtOp0.getOperand(1)) {
1883 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
1885 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
1886 // (rotr x, (sub 32, y))
1887 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
1888 if (SUBC->getValue() == OpSizeInBits) {
1890 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
1892 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1902 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1903 SDOperand N0 = N->getOperand(0);
1904 SDOperand N1 = N->getOperand(1);
1905 SDOperand LHS, RHS, CC;
1906 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1907 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1908 MVT::ValueType VT = N0.getValueType();
1911 if (MVT::isVector(VT)) {
1912 SDOperand FoldedVOp = SimplifyVBinOp(N);
1913 if (FoldedVOp.Val) return FoldedVOp;
1916 // fold (xor x, undef) -> undef
1917 if (N0.getOpcode() == ISD::UNDEF)
1919 if (N1.getOpcode() == ISD::UNDEF)
1921 // fold (xor c1, c2) -> c1^c2
1923 return DAG.getNode(ISD::XOR, VT, N0, N1);
1924 // canonicalize constant to RHS
1926 return DAG.getNode(ISD::XOR, VT, N1, N0);
1927 // fold (xor x, 0) -> x
1928 if (N1C && N1C->isNullValue())
1931 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1934 // fold !(x cc y) -> (x !cc y)
1935 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1936 bool isInt = MVT::isInteger(LHS.getValueType());
1937 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1939 if (N0.getOpcode() == ISD::SETCC)
1940 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1941 if (N0.getOpcode() == ISD::SELECT_CC)
1942 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1943 assert(0 && "Unhandled SetCC Equivalent!");
1946 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
1947 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
1948 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
1949 SDOperand V = N0.getOperand(0);
1950 V = DAG.getNode(ISD::XOR, V.getValueType(), V,
1951 DAG.getConstant(V.getValueType(), 1));
1952 AddToWorkList(V.Val);
1953 return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
1956 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1957 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
1958 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1959 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1960 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1961 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1962 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1963 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1964 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1965 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1968 // fold !(x or y) -> (!x and !y) iff x or y are constants
1969 if (N1C && N1C->isAllOnesValue() &&
1970 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1971 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1972 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1973 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1974 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1975 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1976 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1977 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1980 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1981 if (N1C && N0.getOpcode() == ISD::XOR) {
1982 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1983 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1985 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1986 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1988 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1989 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1991 // fold (xor x, x) -> 0
1993 if (!MVT::isVector(VT)) {
1994 return DAG.getConstant(0, VT);
1995 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1996 // Produce a vector of zeros.
1997 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
1998 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1999 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2003 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2004 if (N0.getOpcode() == N1.getOpcode()) {
2005 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2006 if (Tmp.Val) return Tmp;
2009 // Simplify the expression using non-local knowledge.
2010 if (!MVT::isVector(VT) &&
2011 SimplifyDemandedBits(SDOperand(N, 0)))
2012 return SDOperand(N, 0);
2017 SDOperand DAGCombiner::visitSHL(SDNode *N) {
2018 SDOperand N0 = N->getOperand(0);
2019 SDOperand N1 = N->getOperand(1);
2020 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2021 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2022 MVT::ValueType VT = N0.getValueType();
2023 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2025 // fold (shl c1, c2) -> c1<<c2
2027 return DAG.getNode(ISD::SHL, VT, N0, N1);
2028 // fold (shl 0, x) -> 0
2029 if (N0C && N0C->isNullValue())
2031 // fold (shl x, c >= size(x)) -> undef
2032 if (N1C && N1C->getValue() >= OpSizeInBits)
2033 return DAG.getNode(ISD::UNDEF, VT);
2034 // fold (shl x, 0) -> x
2035 if (N1C && N1C->isNullValue())
2037 // if (shl x, c) is known to be zero, return 0
2038 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
2039 return DAG.getConstant(0, VT);
2040 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2041 return SDOperand(N, 0);
2042 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
2043 if (N1C && N0.getOpcode() == ISD::SHL &&
2044 N0.getOperand(1).getOpcode() == ISD::Constant) {
2045 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2046 uint64_t c2 = N1C->getValue();
2047 if (c1 + c2 > OpSizeInBits)
2048 return DAG.getConstant(0, VT);
2049 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
2050 DAG.getConstant(c1 + c2, N1.getValueType()));
2052 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
2053 // (srl (and x, -1 << c1), c1-c2)
2054 if (N1C && N0.getOpcode() == ISD::SRL &&
2055 N0.getOperand(1).getOpcode() == ISD::Constant) {
2056 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2057 uint64_t c2 = N1C->getValue();
2058 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2059 DAG.getConstant(~0ULL << c1, VT));
2061 return DAG.getNode(ISD::SHL, VT, Mask,
2062 DAG.getConstant(c2-c1, N1.getValueType()));
2064 return DAG.getNode(ISD::SRL, VT, Mask,
2065 DAG.getConstant(c1-c2, N1.getValueType()));
2067 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
2068 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2069 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2070 DAG.getConstant(~0ULL << N1C->getValue(), VT));
2074 SDOperand DAGCombiner::visitSRA(SDNode *N) {
2075 SDOperand N0 = N->getOperand(0);
2076 SDOperand N1 = N->getOperand(1);
2077 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2078 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2079 MVT::ValueType VT = N0.getValueType();
2081 // fold (sra c1, c2) -> c1>>c2
2083 return DAG.getNode(ISD::SRA, VT, N0, N1);
2084 // fold (sra 0, x) -> 0
2085 if (N0C && N0C->isNullValue())
2087 // fold (sra -1, x) -> -1
2088 if (N0C && N0C->isAllOnesValue())
2090 // fold (sra x, c >= size(x)) -> undef
2091 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
2092 return DAG.getNode(ISD::UNDEF, VT);
2093 // fold (sra x, 0) -> x
2094 if (N1C && N1C->isNullValue())
2096 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2098 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2099 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
2102 default: EVT = MVT::Other; break;
2103 case 1: EVT = MVT::i1; break;
2104 case 8: EVT = MVT::i8; break;
2105 case 16: EVT = MVT::i16; break;
2106 case 32: EVT = MVT::i32; break;
2108 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
2109 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
2110 DAG.getValueType(EVT));
2113 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
2114 if (N1C && N0.getOpcode() == ISD::SRA) {
2115 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2116 unsigned Sum = N1C->getValue() + C1->getValue();
2117 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
2118 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
2119 DAG.getConstant(Sum, N1C->getValueType(0)));
2123 // Simplify, based on bits shifted out of the LHS.
2124 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2125 return SDOperand(N, 0);
2128 // If the sign bit is known to be zero, switch this to a SRL.
2129 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
2130 return DAG.getNode(ISD::SRL, VT, N0, N1);
2134 SDOperand DAGCombiner::visitSRL(SDNode *N) {
2135 SDOperand N0 = N->getOperand(0);
2136 SDOperand N1 = N->getOperand(1);
2137 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2138 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2139 MVT::ValueType VT = N0.getValueType();
2140 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2142 // fold (srl c1, c2) -> c1 >>u c2
2144 return DAG.getNode(ISD::SRL, VT, N0, N1);
2145 // fold (srl 0, x) -> 0
2146 if (N0C && N0C->isNullValue())
2148 // fold (srl x, c >= size(x)) -> undef
2149 if (N1C && N1C->getValue() >= OpSizeInBits)
2150 return DAG.getNode(ISD::UNDEF, VT);
2151 // fold (srl x, 0) -> x
2152 if (N1C && N1C->isNullValue())
2154 // if (srl x, c) is known to be zero, return 0
2155 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
2156 return DAG.getConstant(0, VT);
2158 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
2159 if (N1C && N0.getOpcode() == ISD::SRL &&
2160 N0.getOperand(1).getOpcode() == ISD::Constant) {
2161 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2162 uint64_t c2 = N1C->getValue();
2163 if (c1 + c2 > OpSizeInBits)
2164 return DAG.getConstant(0, VT);
2165 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
2166 DAG.getConstant(c1 + c2, N1.getValueType()));
2169 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2170 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2171 // Shifting in all undef bits?
2172 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
2173 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
2174 return DAG.getNode(ISD::UNDEF, VT);
2176 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
2177 AddToWorkList(SmallShift.Val);
2178 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
2181 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2182 // bit, which is unmodified by sra.
2183 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
2184 if (N0.getOpcode() == ISD::SRA)
2185 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
2188 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2189 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2190 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
2191 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
2192 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2194 // If any of the input bits are KnownOne, then the input couldn't be all
2195 // zeros, thus the result of the srl will always be zero.
2196 if (KnownOne) return DAG.getConstant(0, VT);
2198 // If all of the bits input the to ctlz node are known to be zero, then
2199 // the result of the ctlz is "32" and the result of the shift is one.
2200 uint64_t UnknownBits = ~KnownZero & Mask;
2201 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2203 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2204 if ((UnknownBits & (UnknownBits-1)) == 0) {
2205 // Okay, we know that only that the single bit specified by UnknownBits
2206 // could be set on input to the CTLZ node. If this bit is set, the SRL
2207 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2208 // to an SRL,XOR pair, which is likely to simplify more.
2209 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
2210 SDOperand Op = N0.getOperand(0);
2212 Op = DAG.getNode(ISD::SRL, VT, Op,
2213 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
2214 AddToWorkList(Op.Val);
2216 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
2220 // fold operands of srl based on knowledge that the low bits are not
2222 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2223 return SDOperand(N, 0);
2228 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
2229 SDOperand N0 = N->getOperand(0);
2230 MVT::ValueType VT = N->getValueType(0);
2232 // fold (ctlz c1) -> c2
2233 if (isa<ConstantSDNode>(N0))
2234 return DAG.getNode(ISD::CTLZ, VT, N0);
2238 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
2239 SDOperand N0 = N->getOperand(0);
2240 MVT::ValueType VT = N->getValueType(0);
2242 // fold (cttz c1) -> c2
2243 if (isa<ConstantSDNode>(N0))
2244 return DAG.getNode(ISD::CTTZ, VT, N0);
2248 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
2249 SDOperand N0 = N->getOperand(0);
2250 MVT::ValueType VT = N->getValueType(0);
2252 // fold (ctpop c1) -> c2
2253 if (isa<ConstantSDNode>(N0))
2254 return DAG.getNode(ISD::CTPOP, VT, N0);
2258 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
2259 SDOperand N0 = N->getOperand(0);
2260 SDOperand N1 = N->getOperand(1);
2261 SDOperand N2 = N->getOperand(2);
2262 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2263 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2264 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2265 MVT::ValueType VT = N->getValueType(0);
2266 MVT::ValueType VT0 = N0.getValueType();
2268 // fold select C, X, X -> X
2271 // fold select true, X, Y -> X
2272 if (N0C && !N0C->isNullValue())
2274 // fold select false, X, Y -> Y
2275 if (N0C && N0C->isNullValue())
2277 // fold select C, 1, X -> C | X
2278 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
2279 return DAG.getNode(ISD::OR, VT, N0, N2);
2280 // fold select C, 0, 1 -> ~C
2281 if (MVT::isInteger(VT) && MVT::isInteger(VT0) &&
2282 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) {
2283 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
2286 AddToWorkList(XORNode.Val);
2287 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0))
2288 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
2289 return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
2291 // fold select C, 0, X -> ~C & X
2292 if (VT == VT0 && N1C && N1C->isNullValue()) {
2293 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2294 AddToWorkList(XORNode.Val);
2295 return DAG.getNode(ISD::AND, VT, XORNode, N2);
2297 // fold select C, X, 1 -> ~C | X
2298 if (VT == VT0 && N2C && N2C->getValue() == 1) {
2299 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2300 AddToWorkList(XORNode.Val);
2301 return DAG.getNode(ISD::OR, VT, XORNode, N1);
2303 // fold select C, X, 0 -> C & X
2304 // FIXME: this should check for C type == X type, not i1?
2305 if (MVT::i1 == VT && N2C && N2C->isNullValue())
2306 return DAG.getNode(ISD::AND, VT, N0, N1);
2307 // fold X ? X : Y --> X ? 1 : Y --> X | Y
2308 if (MVT::i1 == VT && N0 == N1)
2309 return DAG.getNode(ISD::OR, VT, N0, N2);
2310 // fold X ? Y : X --> X ? Y : 0 --> X & Y
2311 if (MVT::i1 == VT && N0 == N2)
2312 return DAG.getNode(ISD::AND, VT, N0, N1);
2314 // If we can fold this based on the true/false value, do so.
2315 if (SimplifySelectOps(N, N1, N2))
2316 return SDOperand(N, 0); // Don't revisit N.
2318 // fold selects based on a setcc into other things, such as min/max/abs
2319 if (N0.getOpcode() == ISD::SETCC)
2321 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2322 // having to say they don't support SELECT_CC on every type the DAG knows
2323 // about, since there is no way to mark an opcode illegal at all value types
2324 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
2325 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
2326 N1, N2, N0.getOperand(2));
2328 return SimplifySelect(N0, N1, N2);
2332 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
2333 SDOperand N0 = N->getOperand(0);
2334 SDOperand N1 = N->getOperand(1);
2335 SDOperand N2 = N->getOperand(2);
2336 SDOperand N3 = N->getOperand(3);
2337 SDOperand N4 = N->getOperand(4);
2338 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2340 // fold select_cc lhs, rhs, x, x, cc -> x
2344 // Determine if the condition we're dealing with is constant
2345 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2346 if (SCC.Val) AddToWorkList(SCC.Val);
2348 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
2349 if (SCCC->getValue())
2350 return N2; // cond always true -> true val
2352 return N3; // cond always false -> false val
2355 // Fold to a simpler select_cc
2356 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2357 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
2358 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2361 // If we can fold this based on the true/false value, do so.
2362 if (SimplifySelectOps(N, N2, N3))
2363 return SDOperand(N, 0); // Don't revisit N.
2365 // fold select_cc into other things, such as min/max/abs
2366 return SimplifySelectCC(N0, N1, N2, N3, CC);
2369 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
2370 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2371 cast<CondCodeSDNode>(N->getOperand(2))->get());
2374 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2375 SDOperand N0 = N->getOperand(0);
2376 MVT::ValueType VT = N->getValueType(0);
2378 // fold (sext c1) -> c1
2379 if (isa<ConstantSDNode>(N0))
2380 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2382 // fold (sext (sext x)) -> (sext x)
2383 // fold (sext (aext x)) -> (sext x)
2384 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2385 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2387 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2388 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2389 if (N0.getOpcode() == ISD::TRUNCATE) {
2390 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2391 if (NarrowLoad.Val) {
2392 if (NarrowLoad.Val != N0.Val)
2393 CombineTo(N0.Val, NarrowLoad);
2394 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
2398 // See if the value being truncated is already sign extended. If so, just
2399 // eliminate the trunc/sext pair.
2400 if (N0.getOpcode() == ISD::TRUNCATE) {
2401 SDOperand Op = N0.getOperand(0);
2402 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2403 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2404 unsigned DestBits = MVT::getSizeInBits(VT);
2405 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2407 if (OpBits == DestBits) {
2408 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2409 // bits, it is already ready.
2410 if (NumSignBits > DestBits-MidBits)
2412 } else if (OpBits < DestBits) {
2413 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2414 // bits, just sext from i32.
2415 if (NumSignBits > OpBits-MidBits)
2416 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2418 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2419 // bits, just truncate to i32.
2420 if (NumSignBits > OpBits-MidBits)
2421 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2424 // fold (sext (truncate x)) -> (sextinreg x).
2425 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2426 N0.getValueType())) {
2427 if (Op.getValueType() < VT)
2428 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2429 else if (Op.getValueType() > VT)
2430 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2431 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2432 DAG.getValueType(N0.getValueType()));
2436 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2437 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2438 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2439 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2440 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2441 LN0->getBasePtr(), LN0->getSrcValue(),
2442 LN0->getSrcValueOffset(),
2445 LN0->getAlignment());
2446 CombineTo(N, ExtLoad);
2447 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2448 ExtLoad.getValue(1));
2449 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2452 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2453 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2454 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2455 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2456 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2457 MVT::ValueType EVT = LN0->getLoadedVT();
2458 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2459 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2460 LN0->getBasePtr(), LN0->getSrcValue(),
2461 LN0->getSrcValueOffset(), EVT,
2463 LN0->getAlignment());
2464 CombineTo(N, ExtLoad);
2465 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2466 ExtLoad.getValue(1));
2467 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2471 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
2472 if (N0.getOpcode() == ISD::SETCC) {
2474 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2475 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
2476 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2477 if (SCC.Val) return SCC;
2483 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2484 SDOperand N0 = N->getOperand(0);
2485 MVT::ValueType VT = N->getValueType(0);
2487 // fold (zext c1) -> c1
2488 if (isa<ConstantSDNode>(N0))
2489 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2490 // fold (zext (zext x)) -> (zext x)
2491 // fold (zext (aext x)) -> (zext x)
2492 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2493 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2495 // fold (zext (truncate (load x))) -> (zext (smaller load x))
2496 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
2497 if (N0.getOpcode() == ISD::TRUNCATE) {
2498 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2499 if (NarrowLoad.Val) {
2500 if (NarrowLoad.Val != N0.Val)
2501 CombineTo(N0.Val, NarrowLoad);
2502 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
2506 // fold (zext (truncate x)) -> (and x, mask)
2507 if (N0.getOpcode() == ISD::TRUNCATE &&
2508 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2509 SDOperand Op = N0.getOperand(0);
2510 if (Op.getValueType() < VT) {
2511 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2512 } else if (Op.getValueType() > VT) {
2513 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2515 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2518 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2519 if (N0.getOpcode() == ISD::AND &&
2520 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2521 N0.getOperand(1).getOpcode() == ISD::Constant) {
2522 SDOperand X = N0.getOperand(0).getOperand(0);
2523 if (X.getValueType() < VT) {
2524 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2525 } else if (X.getValueType() > VT) {
2526 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2528 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2529 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2532 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2533 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2534 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2535 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2536 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2537 LN0->getBasePtr(), LN0->getSrcValue(),
2538 LN0->getSrcValueOffset(),
2541 LN0->getAlignment());
2542 CombineTo(N, ExtLoad);
2543 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2544 ExtLoad.getValue(1));
2545 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2548 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2549 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2550 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2551 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2552 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2553 MVT::ValueType EVT = LN0->getLoadedVT();
2554 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2555 LN0->getBasePtr(), LN0->getSrcValue(),
2556 LN0->getSrcValueOffset(), EVT,
2558 LN0->getAlignment());
2559 CombineTo(N, ExtLoad);
2560 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2561 ExtLoad.getValue(1));
2562 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2565 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2566 if (N0.getOpcode() == ISD::SETCC) {
2568 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2569 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2570 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2571 if (SCC.Val) return SCC;
2577 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2578 SDOperand N0 = N->getOperand(0);
2579 MVT::ValueType VT = N->getValueType(0);
2581 // fold (aext c1) -> c1
2582 if (isa<ConstantSDNode>(N0))
2583 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2584 // fold (aext (aext x)) -> (aext x)
2585 // fold (aext (zext x)) -> (zext x)
2586 // fold (aext (sext x)) -> (sext x)
2587 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2588 N0.getOpcode() == ISD::ZERO_EXTEND ||
2589 N0.getOpcode() == ISD::SIGN_EXTEND)
2590 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2592 // fold (aext (truncate (load x))) -> (aext (smaller load x))
2593 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
2594 if (N0.getOpcode() == ISD::TRUNCATE) {
2595 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2596 if (NarrowLoad.Val) {
2597 if (NarrowLoad.Val != N0.Val)
2598 CombineTo(N0.Val, NarrowLoad);
2599 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
2603 // fold (aext (truncate x))
2604 if (N0.getOpcode() == ISD::TRUNCATE) {
2605 SDOperand TruncOp = N0.getOperand(0);
2606 if (TruncOp.getValueType() == VT)
2607 return TruncOp; // x iff x size == zext size.
2608 if (TruncOp.getValueType() > VT)
2609 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2610 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2613 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2614 if (N0.getOpcode() == ISD::AND &&
2615 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2616 N0.getOperand(1).getOpcode() == ISD::Constant) {
2617 SDOperand X = N0.getOperand(0).getOperand(0);
2618 if (X.getValueType() < VT) {
2619 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2620 } else if (X.getValueType() > VT) {
2621 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2623 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2624 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2627 // fold (aext (load x)) -> (aext (truncate (extload x)))
2628 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2629 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2630 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2631 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2632 LN0->getBasePtr(), LN0->getSrcValue(),
2633 LN0->getSrcValueOffset(),
2636 LN0->getAlignment());
2637 CombineTo(N, ExtLoad);
2638 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2639 ExtLoad.getValue(1));
2640 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2643 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2644 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2645 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2646 if (N0.getOpcode() == ISD::LOAD &&
2647 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2649 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2650 MVT::ValueType EVT = LN0->getLoadedVT();
2651 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2652 LN0->getChain(), LN0->getBasePtr(),
2654 LN0->getSrcValueOffset(), EVT,
2656 LN0->getAlignment());
2657 CombineTo(N, ExtLoad);
2658 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2659 ExtLoad.getValue(1));
2660 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2663 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2664 if (N0.getOpcode() == ISD::SETCC) {
2666 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2667 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2668 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2676 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
2677 /// bits and then truncated to a narrower type and where N is a multiple
2678 /// of number of bits of the narrower type, transform it to a narrower load
2679 /// from address + N / num of bits of new type. If the result is to be
2680 /// extended, also fold the extension to form a extending load.
2681 SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
2682 unsigned Opc = N->getOpcode();
2683 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2684 SDOperand N0 = N->getOperand(0);
2685 MVT::ValueType VT = N->getValueType(0);
2686 MVT::ValueType EVT = N->getValueType(0);
2688 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
2690 if (Opc == ISD::SIGN_EXTEND_INREG) {
2691 ExtType = ISD::SEXTLOAD;
2692 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2693 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
2697 unsigned EVTBits = MVT::getSizeInBits(EVT);
2699 bool CombineSRL = false;
2700 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
2701 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2702 ShAmt = N01->getValue();
2703 // Is the shift amount a multiple of size of VT?
2704 if ((ShAmt & (EVTBits-1)) == 0) {
2705 N0 = N0.getOperand(0);
2706 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
2713 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2714 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
2715 // zero extended form: by shrinking the load, we lose track of the fact
2716 // that it is already zero extended.
2717 // FIXME: This should be reevaluated.
2719 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
2720 "Cannot truncate to larger type!");
2721 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2722 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2723 // For big endian targets, we need to adjust the offset to the pointer to
2724 // load the correct bytes.
2725 if (!TLI.isLittleEndian())
2726 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits;
2727 uint64_t PtrOff = ShAmt / 8;
2728 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2729 DAG.getConstant(PtrOff, PtrType));
2730 AddToWorkList(NewPtr.Val);
2731 SDOperand Load = (ExtType == ISD::NON_EXTLOAD)
2732 ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
2733 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2734 LN0->isVolatile(), LN0->getAlignment())
2735 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
2736 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
2737 LN0->isVolatile(), LN0->getAlignment());
2740 std::vector<SDNode*> NowDead;
2741 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead);
2742 CombineTo(N->getOperand(0).Val, Load);
2744 CombineTo(N0.Val, Load, Load.getValue(1));
2746 if (Opc == ISD::SIGN_EXTEND_INREG)
2747 return DAG.getNode(Opc, VT, Load, N->getOperand(1));
2749 return DAG.getNode(Opc, VT, Load);
2751 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2758 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2759 SDOperand N0 = N->getOperand(0);
2760 SDOperand N1 = N->getOperand(1);
2761 MVT::ValueType VT = N->getValueType(0);
2762 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2763 unsigned EVTBits = MVT::getSizeInBits(EVT);
2765 // fold (sext_in_reg c1) -> c1
2766 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2767 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2769 // If the input is already sign extended, just drop the extension.
2770 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2773 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2774 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2775 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2776 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2779 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
2780 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2781 return DAG.getZeroExtendInReg(N0, EVT);
2783 // fold operands of sext_in_reg based on knowledge that the top bits are not
2785 if (SimplifyDemandedBits(SDOperand(N, 0)))
2786 return SDOperand(N, 0);
2788 // fold (sext_in_reg (load x)) -> (smaller sextload x)
2789 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
2790 SDOperand NarrowLoad = ReduceLoadWidth(N);
2794 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2795 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2796 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2797 if (N0.getOpcode() == ISD::SRL) {
2798 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2799 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2800 // We can turn this into an SRA iff the input to the SRL is already sign
2802 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
2803 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2804 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2808 // fold (sext_inreg (extload x)) -> (sextload x)
2809 if (ISD::isEXTLoad(N0.Val) &&
2810 ISD::isUNINDEXEDLoad(N0.Val) &&
2811 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2812 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2813 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2814 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2815 LN0->getBasePtr(), LN0->getSrcValue(),
2816 LN0->getSrcValueOffset(), EVT,
2818 LN0->getAlignment());
2819 CombineTo(N, ExtLoad);
2820 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2821 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2823 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2824 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2826 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2827 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2828 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2829 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2830 LN0->getBasePtr(), LN0->getSrcValue(),
2831 LN0->getSrcValueOffset(), EVT,
2833 LN0->getAlignment());
2834 CombineTo(N, ExtLoad);
2835 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2836 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2841 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2842 SDOperand N0 = N->getOperand(0);
2843 MVT::ValueType VT = N->getValueType(0);
2846 if (N0.getValueType() == N->getValueType(0))
2848 // fold (truncate c1) -> c1
2849 if (isa<ConstantSDNode>(N0))
2850 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2851 // fold (truncate (truncate x)) -> (truncate x)
2852 if (N0.getOpcode() == ISD::TRUNCATE)
2853 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2854 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2855 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2856 N0.getOpcode() == ISD::ANY_EXTEND) {
2857 if (N0.getOperand(0).getValueType() < VT)
2858 // if the source is smaller than the dest, we still need an extend
2859 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2860 else if (N0.getOperand(0).getValueType() > VT)
2861 // if the source is larger than the dest, than we just need the truncate
2862 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2864 // if the source and dest are the same type, we can drop both the extend
2866 return N0.getOperand(0);
2869 // fold (truncate (load x)) -> (smaller load x)
2870 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
2871 return ReduceLoadWidth(N);
2874 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2875 SDOperand N0 = N->getOperand(0);
2876 MVT::ValueType VT = N->getValueType(0);
2878 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
2879 // Only do this before legalize, since afterward the target may be depending
2880 // on the bitconvert.
2881 // First check to see if this is all constant.
2882 if (!AfterLegalize &&
2883 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
2884 MVT::isVector(VT)) {
2885 bool isSimple = true;
2886 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
2887 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2888 N0.getOperand(i).getOpcode() != ISD::Constant &&
2889 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2894 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0));
2895 assert(!MVT::isVector(DestEltVT) &&
2896 "Element type of vector ValueType must not be vector!");
2898 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
2902 // If the input is a constant, let getNode() fold it.
2903 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2904 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2905 if (Res.Val != N) return Res;
2908 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2909 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2911 // fold (conv (load x)) -> (load (conv*)x)
2912 // If the resultant load doesn't need a higher alignment than the original!
2913 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() &&
2914 TLI.isOperationLegal(ISD::LOAD, VT)) {
2915 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2916 unsigned Align = TLI.getTargetMachine().getTargetData()->
2917 getABITypeAlignment(MVT::getTypeForValueType(VT));
2918 unsigned OrigAlign = LN0->getAlignment();
2919 if (Align <= OrigAlign) {
2920 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2921 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2922 LN0->isVolatile(), Align);
2924 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2933 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
2934 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2935 /// destination element value type.
2936 SDOperand DAGCombiner::
2937 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2938 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2940 // If this is already the right type, we're done.
2941 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2943 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2944 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2946 // If this is a conversion of N elements of one type to N elements of another
2947 // type, convert each element. This handles FP<->INT cases.
2948 if (SrcBitSize == DstBitSize) {
2949 SmallVector<SDOperand, 8> Ops;
2950 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2951 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2952 AddToWorkList(Ops.back().Val);
2955 MVT::getVectorType(DstEltVT,
2956 MVT::getVectorNumElements(BV->getValueType(0)));
2957 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2960 // Otherwise, we're growing or shrinking the elements. To avoid having to
2961 // handle annoying details of growing/shrinking FP values, we convert them to
2963 if (MVT::isFloatingPoint(SrcEltVT)) {
2964 // Convert the input float vector to a int vector where the elements are the
2966 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2967 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2968 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
2972 // Now we know the input is an integer vector. If the output is a FP type,
2973 // convert to integer first, then to FP of the right size.
2974 if (MVT::isFloatingPoint(DstEltVT)) {
2975 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2976 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2977 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val;
2979 // Next, convert to FP elements of the same size.
2980 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
2983 // Okay, we know the src/dst types are both integers of differing types.
2984 // Handling growing first.
2985 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2986 if (SrcBitSize < DstBitSize) {
2987 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2989 SmallVector<SDOperand, 8> Ops;
2990 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
2991 i += NumInputsPerOutput) {
2992 bool isLE = TLI.isLittleEndian();
2993 uint64_t NewBits = 0;
2994 bool EltIsUndef = true;
2995 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2996 // Shift the previously computed bits over.
2997 NewBits <<= SrcBitSize;
2998 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2999 if (Op.getOpcode() == ISD::UNDEF) continue;
3002 NewBits |= cast<ConstantSDNode>(Op)->getValue();
3006 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3008 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3011 MVT::ValueType VT = MVT::getVectorType(DstEltVT,
3013 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3016 // Finally, this must be the case where we are shrinking elements: each input
3017 // turns into multiple outputs.
3018 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3019 SmallVector<SDOperand, 8> Ops;
3020 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3021 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3022 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3023 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3026 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
3028 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3029 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
3030 OpVal >>= DstBitSize;
3031 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3034 // For big endian targets, swap the order of the pieces of each element.
3035 if (!TLI.isLittleEndian())
3036 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3038 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size());
3039 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3044 SDOperand DAGCombiner::visitFADD(SDNode *N) {
3045 SDOperand N0 = N->getOperand(0);
3046 SDOperand N1 = N->getOperand(1);
3047 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3048 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3049 MVT::ValueType VT = N->getValueType(0);
3052 if (MVT::isVector(VT)) {
3053 SDOperand FoldedVOp = SimplifyVBinOp(N);
3054 if (FoldedVOp.Val) return FoldedVOp;
3057 // fold (fadd c1, c2) -> c1+c2
3059 return DAG.getNode(ISD::FADD, VT, N0, N1);
3060 // canonicalize constant to RHS
3061 if (N0CFP && !N1CFP)
3062 return DAG.getNode(ISD::FADD, VT, N1, N0);
3063 // fold (A + (-B)) -> A-B
3064 if (isNegatibleForFree(N1) == 2)
3065 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG));
3066 // fold ((-A) + B) -> B-A
3067 if (isNegatibleForFree(N0) == 2)
3068 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG));
3070 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3071 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3072 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3073 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
3074 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
3079 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
3080 SDOperand N0 = N->getOperand(0);
3081 SDOperand N1 = N->getOperand(1);
3082 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3083 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3084 MVT::ValueType VT = N->getValueType(0);
3087 if (MVT::isVector(VT)) {
3088 SDOperand FoldedVOp = SimplifyVBinOp(N);
3089 if (FoldedVOp.Val) return FoldedVOp;
3092 // fold (fsub c1, c2) -> c1-c2
3094 return DAG.getNode(ISD::FSUB, VT, N0, N1);
3096 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
3097 if (isNegatibleForFree(N1))
3098 return GetNegatedExpression(N1, DAG);
3099 return DAG.getNode(ISD::FNEG, VT, N1);
3101 // fold (A-(-B)) -> A+B
3102 if (isNegatibleForFree(N1))
3103 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG));
3108 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
3109 SDOperand N0 = N->getOperand(0);
3110 SDOperand N1 = N->getOperand(1);
3111 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3112 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3113 MVT::ValueType VT = N->getValueType(0);
3116 if (MVT::isVector(VT)) {
3117 SDOperand FoldedVOp = SimplifyVBinOp(N);
3118 if (FoldedVOp.Val) return FoldedVOp;
3121 // fold (fmul c1, c2) -> c1*c2
3123 return DAG.getNode(ISD::FMUL, VT, N0, N1);
3124 // canonicalize constant to RHS
3125 if (N0CFP && !N1CFP)
3126 return DAG.getNode(ISD::FMUL, VT, N1, N0);
3127 // fold (fmul X, 2.0) -> (fadd X, X)
3128 if (N1CFP && N1CFP->isExactlyValue(+2.0))
3129 return DAG.getNode(ISD::FADD, VT, N0, N0);
3130 // fold (fmul X, -1.0) -> (fneg X)
3131 if (N1CFP && N1CFP->isExactlyValue(-1.0))
3132 return DAG.getNode(ISD::FNEG, VT, N0);
3135 if (char LHSNeg = isNegatibleForFree(N0)) {
3136 if (char RHSNeg = isNegatibleForFree(N1)) {
3137 // Both can be negated for free, check to see if at least one is cheaper
3139 if (LHSNeg == 2 || RHSNeg == 2)
3140 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG),
3141 GetNegatedExpression(N1, DAG));
3145 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
3146 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
3147 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3148 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
3149 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
3154 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
3155 SDOperand N0 = N->getOperand(0);
3156 SDOperand N1 = N->getOperand(1);
3157 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3158 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3159 MVT::ValueType VT = N->getValueType(0);
3162 if (MVT::isVector(VT)) {
3163 SDOperand FoldedVOp = SimplifyVBinOp(N);
3164 if (FoldedVOp.Val) return FoldedVOp;
3167 // fold (fdiv c1, c2) -> c1/c2
3169 return DAG.getNode(ISD::FDIV, VT, N0, N1);
3173 if (char LHSNeg = isNegatibleForFree(N0)) {
3174 if (char RHSNeg = isNegatibleForFree(N1)) {
3175 // Both can be negated for free, check to see if at least one is cheaper
3177 if (LHSNeg == 2 || RHSNeg == 2)
3178 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG),
3179 GetNegatedExpression(N1, DAG));
3186 SDOperand DAGCombiner::visitFREM(SDNode *N) {
3187 SDOperand N0 = N->getOperand(0);
3188 SDOperand N1 = N->getOperand(1);
3189 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3190 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3191 MVT::ValueType VT = N->getValueType(0);
3193 // fold (frem c1, c2) -> fmod(c1,c2)
3195 return DAG.getNode(ISD::FREM, VT, N0, N1);
3200 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
3201 SDOperand N0 = N->getOperand(0);
3202 SDOperand N1 = N->getOperand(1);
3203 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3204 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3205 MVT::ValueType VT = N->getValueType(0);
3207 if (N0CFP && N1CFP) // Constant fold
3208 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
3211 const APFloat& V = N1CFP->getValueAPF();
3212 // copysign(x, c1) -> fabs(x) iff ispos(c1)
3213 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
3214 if (!V.isNegative())
3215 return DAG.getNode(ISD::FABS, VT, N0);
3217 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
3220 // copysign(fabs(x), y) -> copysign(x, y)
3221 // copysign(fneg(x), y) -> copysign(x, y)
3222 // copysign(copysign(x,z), y) -> copysign(x, y)
3223 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
3224 N0.getOpcode() == ISD::FCOPYSIGN)
3225 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
3227 // copysign(x, abs(y)) -> abs(x)
3228 if (N1.getOpcode() == ISD::FABS)
3229 return DAG.getNode(ISD::FABS, VT, N0);
3231 // copysign(x, copysign(y,z)) -> copysign(x, z)
3232 if (N1.getOpcode() == ISD::FCOPYSIGN)
3233 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
3235 // copysign(x, fp_extend(y)) -> copysign(x, y)
3236 // copysign(x, fp_round(y)) -> copysign(x, y)
3237 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
3238 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
3245 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
3246 SDOperand N0 = N->getOperand(0);
3247 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3248 MVT::ValueType VT = N->getValueType(0);
3250 // fold (sint_to_fp c1) -> c1fp
3252 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
3256 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
3257 SDOperand N0 = N->getOperand(0);
3258 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3259 MVT::ValueType VT = N->getValueType(0);
3261 // fold (uint_to_fp c1) -> c1fp
3263 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
3267 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
3268 SDOperand N0 = N->getOperand(0);
3269 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3270 MVT::ValueType VT = N->getValueType(0);
3272 // fold (fp_to_sint c1fp) -> c1
3274 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
3278 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
3279 SDOperand N0 = N->getOperand(0);
3280 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3281 MVT::ValueType VT = N->getValueType(0);
3283 // fold (fp_to_uint c1fp) -> c1
3285 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
3289 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
3290 SDOperand N0 = N->getOperand(0);
3291 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3292 MVT::ValueType VT = N->getValueType(0);
3294 // fold (fp_round c1fp) -> c1fp
3296 return DAG.getNode(ISD::FP_ROUND, VT, N0);
3298 // fold (fp_round (fp_extend x)) -> x
3299 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
3300 return N0.getOperand(0);
3302 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
3303 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
3304 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
3305 AddToWorkList(Tmp.Val);
3306 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
3312 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
3313 SDOperand N0 = N->getOperand(0);
3314 MVT::ValueType VT = N->getValueType(0);
3315 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3316 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3318 // fold (fp_round_inreg c1fp) -> c1fp
3320 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT);
3321 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
3326 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
3327 SDOperand N0 = N->getOperand(0);
3328 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3329 MVT::ValueType VT = N->getValueType(0);
3331 // fold (fp_extend c1fp) -> c1fp
3333 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
3335 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
3336 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3337 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
3338 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3339 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
3340 LN0->getBasePtr(), LN0->getSrcValue(),
3341 LN0->getSrcValueOffset(),
3344 LN0->getAlignment());
3345 CombineTo(N, ExtLoad);
3346 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
3347 ExtLoad.getValue(1));
3348 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3355 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
3356 SDOperand N0 = N->getOperand(0);
3358 if (isNegatibleForFree(N0))
3359 return GetNegatedExpression(N0, DAG);
3364 SDOperand DAGCombiner::visitFABS(SDNode *N) {
3365 SDOperand N0 = N->getOperand(0);
3366 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3367 MVT::ValueType VT = N->getValueType(0);
3369 // fold (fabs c1) -> fabs(c1)
3371 return DAG.getNode(ISD::FABS, VT, N0);
3372 // fold (fabs (fabs x)) -> (fabs x)
3373 if (N0.getOpcode() == ISD::FABS)
3374 return N->getOperand(0);
3375 // fold (fabs (fneg x)) -> (fabs x)
3376 // fold (fabs (fcopysign x, y)) -> (fabs x)
3377 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
3378 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
3383 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
3384 SDOperand Chain = N->getOperand(0);
3385 SDOperand N1 = N->getOperand(1);
3386 SDOperand N2 = N->getOperand(2);
3387 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3389 // never taken branch, fold to chain
3390 if (N1C && N1C->isNullValue())
3392 // unconditional branch
3393 if (N1C && N1C->getValue() == 1)
3394 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
3395 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
3397 if (N1.getOpcode() == ISD::SETCC &&
3398 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
3399 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
3400 N1.getOperand(0), N1.getOperand(1), N2);
3405 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
3407 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
3408 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
3409 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
3411 // Use SimplifySetCC to simplify SETCC's.
3412 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
3413 if (Simp.Val) AddToWorkList(Simp.Val);
3415 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
3417 // fold br_cc true, dest -> br dest (unconditional branch)
3418 if (SCCC && SCCC->getValue())
3419 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
3421 // fold br_cc false, dest -> unconditional fall through
3422 if (SCCC && SCCC->isNullValue())
3423 return N->getOperand(0);
3425 // fold to a simpler setcc
3426 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
3427 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
3428 Simp.getOperand(2), Simp.getOperand(0),
3429 Simp.getOperand(1), N->getOperand(4));
3434 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
3435 /// pre-indexed load / store when the base pointer is a add or subtract
3436 /// and it has other uses besides the load / store. After the
3437 /// transformation, the new indexed load / store has effectively folded
3438 /// the add / subtract in and all of its other uses are redirected to the
3439 /// new load / store.
3440 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
3447 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3448 if (LD->getAddressingMode() != ISD::UNINDEXED)
3450 VT = LD->getLoadedVT();
3451 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
3452 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
3454 Ptr = LD->getBasePtr();
3455 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3456 if (ST->getAddressingMode() != ISD::UNINDEXED)
3458 VT = ST->getStoredVT();
3459 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
3460 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
3462 Ptr = ST->getBasePtr();
3467 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
3468 // out. There is no reason to make this a preinc/predec.
3469 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
3470 Ptr.Val->hasOneUse())
3473 // Ask the target to do addressing mode selection.
3476 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3477 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
3479 // Don't create a indexed load / store with zero offset.
3480 if (isa<ConstantSDNode>(Offset) &&
3481 cast<ConstantSDNode>(Offset)->getValue() == 0)
3484 // Try turning it into a pre-indexed load / store except when:
3485 // 1) The new base ptr is a frame index.
3486 // 2) If N is a store and the new base ptr is either the same as or is a
3487 // predecessor of the value being stored.
3488 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
3489 // that would create a cycle.
3490 // 4) All uses are load / store ops that use it as old base ptr.
3492 // Check #1. Preinc'ing a frame index would require copying the stack pointer
3493 // (plus the implicit offset) to a register to preinc anyway.
3494 if (isa<FrameIndexSDNode>(BasePtr))
3499 SDOperand Val = cast<StoreSDNode>(N)->getValue();
3500 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val))
3504 // Now check for #3 and #4.
3505 bool RealUse = false;
3506 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3507 E = Ptr.Val->use_end(); I != E; ++I) {
3511 if (Use->isPredecessor(N))
3514 if (!((Use->getOpcode() == ISD::LOAD &&
3515 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
3516 (Use->getOpcode() == ISD::STORE) &&
3517 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
3525 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
3527 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3530 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
3531 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3533 std::vector<SDNode*> NowDead;
3535 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3537 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3540 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3544 // Nodes can end up on the worklist more than once. Make sure we do
3545 // not process a node that has been replaced.
3546 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3547 removeFromWorkList(NowDead[i]);
3548 // Finally, since the node is now dead, remove it from the graph.
3551 // Replace the uses of Ptr with uses of the updated base value.
3552 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
3554 removeFromWorkList(Ptr.Val);
3555 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3556 removeFromWorkList(NowDead[i]);
3557 DAG.DeleteNode(Ptr.Val);
3562 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
3563 /// add / sub of the base pointer node into a post-indexed load / store.
3564 /// The transformation folded the add / subtract into the new indexed
3565 /// load / store effectively and all of its uses are redirected to the
3566 /// new load / store.
3567 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
3574 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3575 if (LD->getAddressingMode() != ISD::UNINDEXED)
3577 VT = LD->getLoadedVT();
3578 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
3579 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
3581 Ptr = LD->getBasePtr();
3582 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3583 if (ST->getAddressingMode() != ISD::UNINDEXED)
3585 VT = ST->getStoredVT();
3586 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
3587 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
3589 Ptr = ST->getBasePtr();
3594 if (Ptr.Val->hasOneUse())
3597 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3598 E = Ptr.Val->use_end(); I != E; ++I) {
3601 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
3606 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3607 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
3609 std::swap(BasePtr, Offset);
3612 // Don't create a indexed load / store with zero offset.
3613 if (isa<ConstantSDNode>(Offset) &&
3614 cast<ConstantSDNode>(Offset)->getValue() == 0)
3617 // Try turning it into a post-indexed load / store except when
3618 // 1) All uses are load / store ops that use it as base ptr.
3619 // 2) Op must be independent of N, i.e. Op is neither a predecessor
3620 // nor a successor of N. Otherwise, if Op is folded that would
3624 bool TryNext = false;
3625 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
3626 EE = BasePtr.Val->use_end(); II != EE; ++II) {
3631 // If all the uses are load / store addresses, then don't do the
3633 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
3634 bool RealUse = false;
3635 for (SDNode::use_iterator III = Use->use_begin(),
3636 EEE = Use->use_end(); III != EEE; ++III) {
3637 SDNode *UseUse = *III;
3638 if (!((UseUse->getOpcode() == ISD::LOAD &&
3639 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
3640 (UseUse->getOpcode() == ISD::STORE) &&
3641 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
3655 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
3656 SDOperand Result = isLoad
3657 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
3658 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3661 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
3662 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3664 std::vector<SDNode*> NowDead;
3666 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3668 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3671 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3675 // Nodes can end up on the worklist more than once. Make sure we do
3676 // not process a node that has been replaced.
3677 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3678 removeFromWorkList(NowDead[i]);
3679 // Finally, since the node is now dead, remove it from the graph.
3682 // Replace the uses of Use with uses of the updated base value.
3683 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
3684 Result.getValue(isLoad ? 1 : 0),
3686 removeFromWorkList(Op);
3687 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3688 removeFromWorkList(NowDead[i]);
3699 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
3700 LoadSDNode *LD = cast<LoadSDNode>(N);
3701 SDOperand Chain = LD->getChain();
3702 SDOperand Ptr = LD->getBasePtr();
3704 // If load is not volatile and there are no uses of the loaded value (and
3705 // the updated indexed value in case of indexed loads), change uses of the
3706 // chain value into uses of the chain input (i.e. delete the dead load).
3707 if (!LD->isVolatile()) {
3708 if (N->getValueType(1) == MVT::Other) {
3710 if (N->hasNUsesOfValue(0, 0))
3711 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
3714 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
3715 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
3716 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0));
3717 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1));
3718 SDOperand To[] = { Undef0, Undef1, Chain };
3719 return CombineTo(N, To, 3);
3724 // If this load is directly stored, replace the load value with the stored
3726 // TODO: Handle store large -> read small portion.
3727 // TODO: Handle TRUNCSTORE/LOADEXT
3728 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3729 if (ISD::isNON_TRUNCStore(Chain.Val)) {
3730 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
3731 if (PrevST->getBasePtr() == Ptr &&
3732 PrevST->getValue().getValueType() == N->getValueType(0))
3733 return CombineTo(N, Chain.getOperand(1), Chain);
3738 // Walk up chain skipping non-aliasing memory nodes.
3739 SDOperand BetterChain = FindBetterChain(N, Chain);
3741 // If there is a better chain.
3742 if (Chain != BetterChain) {
3745 // Replace the chain to void dependency.
3746 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3747 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
3748 LD->getSrcValue(), LD->getSrcValueOffset(),
3749 LD->isVolatile(), LD->getAlignment());
3751 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
3752 LD->getValueType(0),
3753 BetterChain, Ptr, LD->getSrcValue(),
3754 LD->getSrcValueOffset(),
3757 LD->getAlignment());
3760 // Create token factor to keep old chain connected.
3761 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
3762 Chain, ReplLoad.getValue(1));
3764 // Replace uses with load result and token factor. Don't add users
3766 return CombineTo(N, ReplLoad.getValue(0), Token, false);
3770 // Try transforming N to an indexed load.
3771 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3772 return SDOperand(N, 0);
3777 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
3778 StoreSDNode *ST = cast<StoreSDNode>(N);
3779 SDOperand Chain = ST->getChain();
3780 SDOperand Value = ST->getValue();
3781 SDOperand Ptr = ST->getBasePtr();
3783 // If this is a store of a bit convert, store the input value if the
3784 // resultant store does not need a higher alignment than the original.
3785 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
3786 ST->getAddressingMode() == ISD::UNINDEXED) {
3787 unsigned Align = ST->getAlignment();
3788 MVT::ValueType SVT = Value.getOperand(0).getValueType();
3789 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
3790 getABITypeAlignment(MVT::getTypeForValueType(SVT));
3791 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
3792 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
3793 ST->getSrcValueOffset(), ST->isVolatile(), Align);
3796 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
3797 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
3798 if (Value.getOpcode() != ISD::TargetConstantFP) {
3800 switch (CFP->getValueType(0)) {
3801 default: assert(0 && "Unknown FP type");
3802 case MVT::f80: // We don't do this for these yet.
3807 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
3808 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
3809 convertToAPInt().getZExtValue(), MVT::i32);
3810 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3811 ST->getSrcValueOffset(), ST->isVolatile(),
3812 ST->getAlignment());
3816 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
3817 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
3818 getZExtValue(), MVT::i64);
3819 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3820 ST->getSrcValueOffset(), ST->isVolatile(),
3821 ST->getAlignment());
3822 } else if (TLI.isTypeLegal(MVT::i32)) {
3823 // Many FP stores are not make apparent until after legalize, e.g. for
3824 // argument passing. Since this is so common, custom legalize the
3825 // 64-bit integer store into two 32-bit stores.
3826 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue();
3827 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
3828 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
3829 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
3831 int SVOffset = ST->getSrcValueOffset();
3832 unsigned Alignment = ST->getAlignment();
3833 bool isVolatile = ST->isVolatile();
3835 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
3836 ST->getSrcValueOffset(),
3837 isVolatile, ST->getAlignment());
3838 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3839 DAG.getConstant(4, Ptr.getValueType()));
3843 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
3844 SVOffset, isVolatile, Alignment);
3845 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
3853 // Walk up chain skipping non-aliasing memory nodes.
3854 SDOperand BetterChain = FindBetterChain(N, Chain);
3856 // If there is a better chain.
3857 if (Chain != BetterChain) {
3858 // Replace the chain to avoid dependency.
3859 SDOperand ReplStore;
3860 if (ST->isTruncatingStore()) {
3861 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
3862 ST->getSrcValue(), ST->getSrcValueOffset(), ST->getStoredVT(),
3863 ST->isVolatile(), ST->getAlignment());
3865 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
3866 ST->getSrcValue(), ST->getSrcValueOffset(),
3867 ST->isVolatile(), ST->getAlignment());
3870 // Create token to keep both nodes around.
3872 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
3874 // Don't add users to work list.
3875 return CombineTo(N, Token, false);
3879 // Try transforming N to an indexed store.
3880 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3881 return SDOperand(N, 0);
3886 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
3887 SDOperand InVec = N->getOperand(0);
3888 SDOperand InVal = N->getOperand(1);
3889 SDOperand EltNo = N->getOperand(2);
3891 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
3892 // vector with the inserted element.
3893 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
3894 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3895 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
3896 if (Elt < Ops.size())
3898 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
3899 &Ops[0], Ops.size());
3905 SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
3906 SDOperand InVec = N->getOperand(0);
3907 SDOperand EltNo = N->getOperand(1);
3909 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr)
3910 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
3911 if (isa<ConstantSDNode>(EltNo)) {
3912 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3913 bool NewLoad = false;
3915 MVT::ValueType VT = InVec.getValueType();
3916 MVT::ValueType EVT = MVT::getVectorElementType(VT);
3917 MVT::ValueType LVT = EVT;
3918 unsigned NumElts = MVT::getVectorNumElements(VT);
3919 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
3920 MVT::ValueType BCVT = InVec.getOperand(0).getValueType();
3921 if (NumElts != MVT::getVectorNumElements(BCVT))
3923 InVec = InVec.getOperand(0);
3924 EVT = MVT::getVectorElementType(BCVT);
3927 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3928 InVec.getOperand(0).getValueType() == EVT &&
3929 ISD::isNormalLoad(InVec.getOperand(0).Val) &&
3930 InVec.getOperand(0).hasOneUse()) {
3931 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0));
3932 unsigned Align = LN0->getAlignment();
3934 // Check the resultant load doesn't need a higher alignment than the
3936 unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
3937 getABITypeAlignment(MVT::getTypeForValueType(LVT));
3938 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align)
3943 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(),
3944 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3945 LN0->isVolatile(), Align);
3953 SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
3954 unsigned NumInScalars = N->getNumOperands();
3955 MVT::ValueType VT = N->getValueType(0);
3956 unsigned NumElts = MVT::getVectorNumElements(VT);
3957 MVT::ValueType EltType = MVT::getVectorElementType(VT);
3959 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
3960 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
3961 // at most two distinct vectors, turn this into a shuffle node.
3962 SDOperand VecIn1, VecIn2;
3963 for (unsigned i = 0; i != NumInScalars; ++i) {
3964 // Ignore undef inputs.
3965 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3967 // If this input is something other than a EXTRACT_VECTOR_ELT with a
3968 // constant index, bail out.
3969 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
3970 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
3971 VecIn1 = VecIn2 = SDOperand(0, 0);
3975 // If the input vector type disagrees with the result of the build_vector,
3976 // we can't make a shuffle.
3977 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
3978 if (ExtractedFromVec.getValueType() != VT) {
3979 VecIn1 = VecIn2 = SDOperand(0, 0);
3983 // Otherwise, remember this. We allow up to two distinct input vectors.
3984 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
3987 if (VecIn1.Val == 0) {
3988 VecIn1 = ExtractedFromVec;
3989 } else if (VecIn2.Val == 0) {
3990 VecIn2 = ExtractedFromVec;
3993 VecIn1 = VecIn2 = SDOperand(0, 0);
3998 // If everything is good, we can make a shuffle operation.
4000 SmallVector<SDOperand, 8> BuildVecIndices;
4001 for (unsigned i = 0; i != NumInScalars; ++i) {
4002 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
4003 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
4007 SDOperand Extract = N->getOperand(i);
4009 // If extracting from the first vector, just use the index directly.
4010 if (Extract.getOperand(0) == VecIn1) {
4011 BuildVecIndices.push_back(Extract.getOperand(1));
4015 // Otherwise, use InIdx + VecSize
4016 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
4017 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars,
4018 TLI.getPointerTy()));
4021 // Add count and size info.
4022 MVT::ValueType BuildVecVT =
4023 MVT::getVectorType(TLI.getPointerTy(), NumElts);
4025 // Return the new VECTOR_SHUFFLE node.
4031 // Use an undef build_vector as input for the second operand.
4032 std::vector<SDOperand> UnOps(NumInScalars,
4033 DAG.getNode(ISD::UNDEF,
4035 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
4036 &UnOps[0], UnOps.size());
4037 AddToWorkList(Ops[1].Val);
4039 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
4040 &BuildVecIndices[0], BuildVecIndices.size());
4041 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3);
4047 SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
4048 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
4049 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
4050 // inputs come from at most two distinct vectors, turn this into a shuffle
4053 // If we only have one input vector, we don't need to do any concatenation.
4054 if (N->getNumOperands() == 1) {
4055 return N->getOperand(0);
4061 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
4062 SDOperand ShufMask = N->getOperand(2);
4063 unsigned NumElts = ShufMask.getNumOperands();
4065 // If the shuffle mask is an identity operation on the LHS, return the LHS.
4066 bool isIdentity = true;
4067 for (unsigned i = 0; i != NumElts; ++i) {
4068 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4069 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
4074 if (isIdentity) return N->getOperand(0);
4076 // If the shuffle mask is an identity operation on the RHS, return the RHS.
4078 for (unsigned i = 0; i != NumElts; ++i) {
4079 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4080 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
4085 if (isIdentity) return N->getOperand(1);
4087 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
4089 bool isUnary = true;
4090 bool isSplat = true;
4092 unsigned BaseIdx = 0;
4093 for (unsigned i = 0; i != NumElts; ++i)
4094 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
4095 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
4096 int V = (Idx < NumElts) ? 0 : 1;
4110 SDOperand N0 = N->getOperand(0);
4111 SDOperand N1 = N->getOperand(1);
4112 // Normalize unary shuffle so the RHS is undef.
4113 if (isUnary && VecNum == 1)
4116 // If it is a splat, check if the argument vector is a build_vector with
4117 // all scalar elements the same.
4121 // If this is a bit convert that changes the element type of the vector but
4122 // not the number of vector elements, look through it. Be careful not to
4123 // look though conversions that change things like v4f32 to v2f64.
4124 if (V->getOpcode() == ISD::BIT_CONVERT) {
4125 SDOperand ConvInput = V->getOperand(0);
4126 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts)
4130 if (V->getOpcode() == ISD::BUILD_VECTOR) {
4131 unsigned NumElems = V->getNumOperands();
4132 if (NumElems > BaseIdx) {
4134 bool AllSame = true;
4135 for (unsigned i = 0; i != NumElems; ++i) {
4136 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
4137 Base = V->getOperand(i);
4141 // Splat of <u, u, u, u>, return <u, u, u, u>
4144 for (unsigned i = 0; i != NumElems; ++i) {
4145 if (V->getOperand(i) != Base) {
4150 // Splat of <x, x, x, x>, return <x, x, x, x>
4157 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
4159 if (isUnary || N0 == N1) {
4160 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
4162 SmallVector<SDOperand, 8> MappedOps;
4163 for (unsigned i = 0; i != NumElts; ++i) {
4164 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
4165 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
4166 MappedOps.push_back(ShufMask.getOperand(i));
4169 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
4170 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
4173 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
4174 &MappedOps[0], MappedOps.size());
4175 AddToWorkList(ShufMask.Val);
4176 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
4178 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
4185 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
4186 /// an AND to a vector_shuffle with the destination vector and a zero vector.
4187 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
4188 /// vector_shuffle V, Zero, <0, 4, 2, 4>
4189 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
4190 SDOperand LHS = N->getOperand(0);
4191 SDOperand RHS = N->getOperand(1);
4192 if (N->getOpcode() == ISD::AND) {
4193 if (RHS.getOpcode() == ISD::BIT_CONVERT)
4194 RHS = RHS.getOperand(0);
4195 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
4196 std::vector<SDOperand> IdxOps;
4197 unsigned NumOps = RHS.getNumOperands();
4198 unsigned NumElts = NumOps;
4199 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType());
4200 for (unsigned i = 0; i != NumElts; ++i) {
4201 SDOperand Elt = RHS.getOperand(i);
4202 if (!isa<ConstantSDNode>(Elt))
4204 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
4205 IdxOps.push_back(DAG.getConstant(i, EVT));
4206 else if (cast<ConstantSDNode>(Elt)->isNullValue())
4207 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
4212 // Let's see if the target supports this vector_shuffle.
4213 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
4216 // Return the new VECTOR_SHUFFLE node.
4217 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts);
4218 std::vector<SDOperand> Ops;
4219 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
4221 AddToWorkList(LHS.Val);
4222 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
4223 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4224 &ZeroOps[0], ZeroOps.size()));
4225 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4226 &IdxOps[0], IdxOps.size()));
4227 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
4228 &Ops[0], Ops.size());
4229 if (VT != LHS.getValueType()) {
4230 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result);
4238 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
4239 SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
4240 // After legalize, the target may be depending on adds and other
4241 // binary ops to provide legal ways to construct constants or other
4242 // things. Simplifying them may result in a loss of legality.
4243 if (AfterLegalize) return SDOperand();
4245 MVT::ValueType VT = N->getValueType(0);
4246 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!");
4248 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4249 SDOperand LHS = N->getOperand(0);
4250 SDOperand RHS = N->getOperand(1);
4251 SDOperand Shuffle = XformToShuffleWithZero(N);
4252 if (Shuffle.Val) return Shuffle;
4254 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
4256 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
4257 RHS.getOpcode() == ISD::BUILD_VECTOR) {
4258 SmallVector<SDOperand, 8> Ops;
4259 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
4260 SDOperand LHSOp = LHS.getOperand(i);
4261 SDOperand RHSOp = RHS.getOperand(i);
4262 // If these two elements can't be folded, bail out.
4263 if ((LHSOp.getOpcode() != ISD::UNDEF &&
4264 LHSOp.getOpcode() != ISD::Constant &&
4265 LHSOp.getOpcode() != ISD::ConstantFP) ||
4266 (RHSOp.getOpcode() != ISD::UNDEF &&
4267 RHSOp.getOpcode() != ISD::Constant &&
4268 RHSOp.getOpcode() != ISD::ConstantFP))
4270 // Can't fold divide by zero.
4271 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
4272 N->getOpcode() == ISD::FDIV) {
4273 if ((RHSOp.getOpcode() == ISD::Constant &&
4274 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
4275 (RHSOp.getOpcode() == ISD::ConstantFP &&
4276 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero()))
4279 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
4280 AddToWorkList(Ops.back().Val);
4281 assert((Ops.back().getOpcode() == ISD::UNDEF ||
4282 Ops.back().getOpcode() == ISD::Constant ||
4283 Ops.back().getOpcode() == ISD::ConstantFP) &&
4284 "Scalar binop didn't fold!");
4287 if (Ops.size() == LHS.getNumOperands()) {
4288 MVT::ValueType VT = LHS.getValueType();
4289 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
4296 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
4297 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
4299 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
4300 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4301 // If we got a simplified select_cc node back from SimplifySelectCC, then
4302 // break it down into a new SETCC node, and a new SELECT node, and then return
4303 // the SELECT node, since we were called with a SELECT node.
4305 // Check to see if we got a select_cc back (to turn into setcc/select).
4306 // Otherwise, just return whatever node we got back, like fabs.
4307 if (SCC.getOpcode() == ISD::SELECT_CC) {
4308 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
4309 SCC.getOperand(0), SCC.getOperand(1),
4311 AddToWorkList(SETCC.Val);
4312 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
4313 SCC.getOperand(3), SETCC);
4320 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
4321 /// are the two values being selected between, see if we can simplify the
4322 /// select. Callers of this should assume that TheSelect is deleted if this
4323 /// returns true. As such, they should return the appropriate thing (e.g. the
4324 /// node) back to the top-level of the DAG combiner loop to avoid it being
4327 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
4330 // If this is a select from two identical things, try to pull the operation
4331 // through the select.
4332 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
4333 // If this is a load and the token chain is identical, replace the select
4334 // of two loads with a load through a select of the address to load from.
4335 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
4336 // constants have been dropped into the constant pool.
4337 if (LHS.getOpcode() == ISD::LOAD &&
4338 // Token chains must be identical.
4339 LHS.getOperand(0) == RHS.getOperand(0)) {
4340 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
4341 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
4343 // If this is an EXTLOAD, the VT's must match.
4344 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
4345 // FIXME: this conflates two src values, discarding one. This is not
4346 // the right thing to do, but nothing uses srcvalues now. When they do,
4347 // turn SrcValue into a list of locations.
4349 if (TheSelect->getOpcode() == ISD::SELECT) {
4350 // Check that the condition doesn't reach either load. If so, folding
4351 // this will induce a cycle into the DAG.
4352 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4353 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
4354 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
4355 TheSelect->getOperand(0), LLD->getBasePtr(),
4359 // Check that the condition doesn't reach either load. If so, folding
4360 // this will induce a cycle into the DAG.
4361 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4362 !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4363 !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
4364 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
4365 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
4366 TheSelect->getOperand(0),
4367 TheSelect->getOperand(1),
4368 LLD->getBasePtr(), RLD->getBasePtr(),
4369 TheSelect->getOperand(4));
4375 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
4376 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
4377 Addr,LLD->getSrcValue(),
4378 LLD->getSrcValueOffset(),
4380 LLD->getAlignment());
4382 Load = DAG.getExtLoad(LLD->getExtensionType(),
4383 TheSelect->getValueType(0),
4384 LLD->getChain(), Addr, LLD->getSrcValue(),
4385 LLD->getSrcValueOffset(),
4388 LLD->getAlignment());
4390 // Users of the select now use the result of the load.
4391 CombineTo(TheSelect, Load);
4393 // Users of the old loads now use the new load's chain. We know the
4394 // old-load value is dead now.
4395 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
4396 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
4406 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
4407 SDOperand N2, SDOperand N3,
4408 ISD::CondCode CC, bool NotExtCompare) {
4410 MVT::ValueType VT = N2.getValueType();
4411 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
4412 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
4413 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
4415 // Determine if the condition we're dealing with is constant
4416 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
4417 if (SCC.Val) AddToWorkList(SCC.Val);
4418 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
4420 // fold select_cc true, x, y -> x
4421 if (SCCC && SCCC->getValue())
4423 // fold select_cc false, x, y -> y
4424 if (SCCC && SCCC->getValue() == 0)
4427 // Check to see if we can simplify the select into an fabs node
4428 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
4429 // Allow either -0.0 or 0.0
4430 if (CFP->getValueAPF().isZero()) {
4431 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
4432 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
4433 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
4434 N2 == N3.getOperand(0))
4435 return DAG.getNode(ISD::FABS, VT, N0);
4437 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
4438 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
4439 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
4440 N2.getOperand(0) == N3)
4441 return DAG.getNode(ISD::FABS, VT, N3);
4445 // Check to see if we can perform the "gzip trick", transforming
4446 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
4447 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
4448 MVT::isInteger(N0.getValueType()) &&
4449 MVT::isInteger(N2.getValueType()) &&
4450 (N1C->isNullValue() || // (a < 0) ? b : 0
4451 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
4452 MVT::ValueType XType = N0.getValueType();
4453 MVT::ValueType AType = N2.getValueType();
4454 if (XType >= AType) {
4455 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
4456 // single-bit constant.
4457 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
4458 unsigned ShCtV = Log2_64(N2C->getValue());
4459 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
4460 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
4461 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
4462 AddToWorkList(Shift.Val);
4463 if (XType > AType) {
4464 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4465 AddToWorkList(Shift.Val);
4467 return DAG.getNode(ISD::AND, AType, Shift, N2);
4469 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4470 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4471 TLI.getShiftAmountTy()));
4472 AddToWorkList(Shift.Val);
4473 if (XType > AType) {
4474 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4475 AddToWorkList(Shift.Val);
4477 return DAG.getNode(ISD::AND, AType, Shift, N2);
4481 // fold select C, 16, 0 -> shl C, 4
4482 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
4483 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
4485 // If the caller doesn't want us to simplify this into a zext of a compare,
4487 if (NotExtCompare && N2C->getValue() == 1)
4490 // Get a SetCC of the condition
4491 // FIXME: Should probably make sure that setcc is legal if we ever have a
4492 // target where it isn't.
4493 SDOperand Temp, SCC;
4494 // cast from setcc result type to select result type
4495 if (AfterLegalize) {
4496 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4497 if (N2.getValueType() < SCC.getValueType())
4498 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
4500 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4502 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
4503 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4505 AddToWorkList(SCC.Val);
4506 AddToWorkList(Temp.Val);
4508 if (N2C->getValue() == 1)
4510 // shl setcc result by log2 n2c
4511 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
4512 DAG.getConstant(Log2_64(N2C->getValue()),
4513 TLI.getShiftAmountTy()));
4516 // Check to see if this is the equivalent of setcc
4517 // FIXME: Turn all of these into setcc if setcc if setcc is legal
4518 // otherwise, go ahead with the folds.
4519 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
4520 MVT::ValueType XType = N0.getValueType();
4521 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
4522 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4523 if (Res.getValueType() != VT)
4524 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
4528 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
4529 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
4530 TLI.isOperationLegal(ISD::CTLZ, XType)) {
4531 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
4532 return DAG.getNode(ISD::SRL, XType, Ctlz,
4533 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
4534 TLI.getShiftAmountTy()));
4536 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
4537 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
4538 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
4540 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
4541 DAG.getConstant(~0ULL, XType));
4542 return DAG.getNode(ISD::SRL, XType,
4543 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
4544 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4545 TLI.getShiftAmountTy()));
4547 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
4548 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
4549 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
4550 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4551 TLI.getShiftAmountTy()));
4552 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
4556 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
4557 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4558 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
4559 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
4560 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) {
4561 MVT::ValueType XType = N0.getValueType();
4562 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4563 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4564 TLI.getShiftAmountTy()));
4565 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4566 AddToWorkList(Shift.Val);
4567 AddToWorkList(Add.Val);
4568 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4570 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
4571 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4572 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
4573 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
4574 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
4575 MVT::ValueType XType = N0.getValueType();
4576 if (SubC->isNullValue() && MVT::isInteger(XType)) {
4577 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4578 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4579 TLI.getShiftAmountTy()));
4580 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4581 AddToWorkList(Shift.Val);
4582 AddToWorkList(Add.Val);
4583 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4591 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
4592 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
4593 SDOperand N1, ISD::CondCode Cond,
4594 bool foldBooleans) {
4595 TargetLowering::DAGCombinerInfo
4596 DagCombineInfo(DAG, !AfterLegalize, false, this);
4597 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
4600 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
4601 /// return a DAG expression to select that will generate the same value by
4602 /// multiplying by a magic number. See:
4603 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4604 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
4605 std::vector<SDNode*> Built;
4606 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
4608 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4614 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
4615 /// return a DAG expression to select that will generate the same value by
4616 /// multiplying by a magic number. See:
4617 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4618 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
4619 std::vector<SDNode*> Built;
4620 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
4622 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4628 /// FindBaseOffset - Return true if base is known not to alias with anything
4629 /// but itself. Provides base object and offset as results.
4630 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4631 // Assume it is a primitive operation.
4632 Base = Ptr; Offset = 0;
4634 // If it's an adding a simple constant then integrate the offset.
4635 if (Base.getOpcode() == ISD::ADD) {
4636 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4637 Base = Base.getOperand(0);
4638 Offset += C->getValue();
4642 // If it's any of the following then it can't alias with anything but itself.
4643 return isa<FrameIndexSDNode>(Base) ||
4644 isa<ConstantPoolSDNode>(Base) ||
4645 isa<GlobalAddressSDNode>(Base);
4648 /// isAlias - Return true if there is any possibility that the two addresses
4650 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4651 const Value *SrcValue1, int SrcValueOffset1,
4652 SDOperand Ptr2, int64_t Size2,
4653 const Value *SrcValue2, int SrcValueOffset2)
4655 // If they are the same then they must be aliases.
4656 if (Ptr1 == Ptr2) return true;
4658 // Gather base node and offset information.
4659 SDOperand Base1, Base2;
4660 int64_t Offset1, Offset2;
4661 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4662 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4664 // If they have a same base address then...
4665 if (Base1 == Base2) {
4666 // Check to see if the addresses overlap.
4667 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4670 // If we know both bases then they can't alias.
4671 if (KnownBase1 && KnownBase2) return false;
4673 if (CombinerGlobalAA) {
4674 // Use alias analysis information.
4675 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
4676 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
4677 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
4678 AliasAnalysis::AliasResult AAResult =
4679 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
4680 if (AAResult == AliasAnalysis::NoAlias)
4684 // Otherwise we have to assume they alias.
4688 /// FindAliasInfo - Extracts the relevant alias information from the memory
4689 /// node. Returns true if the operand was a load.
4690 bool DAGCombiner::FindAliasInfo(SDNode *N,
4691 SDOperand &Ptr, int64_t &Size,
4692 const Value *&SrcValue, int &SrcValueOffset) {
4693 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4694 Ptr = LD->getBasePtr();
4695 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4696 SrcValue = LD->getSrcValue();
4697 SrcValueOffset = LD->getSrcValueOffset();
4699 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4700 Ptr = ST->getBasePtr();
4701 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4702 SrcValue = ST->getSrcValue();
4703 SrcValueOffset = ST->getSrcValueOffset();
4705 assert(0 && "FindAliasInfo expected a memory operand");
4711 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4712 /// looking for aliasing nodes and adding them to the Aliases vector.
4713 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4714 SmallVector<SDOperand, 8> &Aliases) {
4715 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4716 std::set<SDNode *> Visited; // Visited node set.
4718 // Get alias information for node.
4721 const Value *SrcValue;
4723 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
4726 Chains.push_back(OriginalChain);
4728 // Look at each chain and determine if it is an alias. If so, add it to the
4729 // aliases list. If not, then continue up the chain looking for the next
4731 while (!Chains.empty()) {
4732 SDOperand Chain = Chains.back();
4735 // Don't bother if we've been before.
4736 if (Visited.find(Chain.Val) != Visited.end()) continue;
4737 Visited.insert(Chain.Val);
4739 switch (Chain.getOpcode()) {
4740 case ISD::EntryToken:
4741 // Entry token is ideal chain operand, but handled in FindBetterChain.
4746 // Get alias information for Chain.
4749 const Value *OpSrcValue;
4750 int OpSrcValueOffset;
4751 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
4752 OpSrcValue, OpSrcValueOffset);
4754 // If chain is alias then stop here.
4755 if (!(IsLoad && IsOpLoad) &&
4756 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
4757 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
4758 Aliases.push_back(Chain);
4760 // Look further up the chain.
4761 Chains.push_back(Chain.getOperand(0));
4762 // Clean up old chain.
4763 AddToWorkList(Chain.Val);
4768 case ISD::TokenFactor:
4769 // We have to check each of the operands of the token factor, so we queue
4770 // then up. Adding the operands to the queue (stack) in reverse order
4771 // maintains the original order and increases the likelihood that getNode
4772 // will find a matching token factor (CSE.)
4773 for (unsigned n = Chain.getNumOperands(); n;)
4774 Chains.push_back(Chain.getOperand(--n));
4775 // Eliminate the token factor if we can.
4776 AddToWorkList(Chain.Val);
4780 // For all other instructions we will just have to take what we can get.
4781 Aliases.push_back(Chain);
4787 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4788 /// for a better chain (aliasing node.)
4789 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4790 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4792 // Accumulate all the aliases to this node.
4793 GatherAllAliases(N, OldChain, Aliases);
4795 if (Aliases.size() == 0) {
4796 // If no operands then chain to entry token.
4797 return DAG.getEntryNode();
4798 } else if (Aliases.size() == 1) {
4799 // If a single operand then chain to it. We don't need to revisit it.
4803 // Construct a custom tailored token factor.
4804 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4805 &Aliases[0], Aliases.size());
4807 // Make sure the old chain gets cleaned up.
4808 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4813 // SelectionDAG::Combine - This is the entry point for the file.
4815 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
4816 if (!RunningAfterLegalize && ViewDAGCombine1)
4818 if (RunningAfterLegalize && ViewDAGCombine2)
4820 /// run - This is the main entry point to this class.
4822 DAGCombiner(*this, AA).Run(RunningAfterLegalize);