1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: Should add a corresponding version of fold AND with
20 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
23 // FIXME: select C, pow2, pow2 -> something smart
24 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
25 // FIXME: (select C, load A, load B) -> load (select C, A, B)
26 // FIXME: Dead stores -> nuke
27 // FIXME: shr X, (and Y,31) -> shr X, Y
28 // FIXME: TRUNC (LOAD) -> EXT_LOAD/LOAD(smaller)
29 // FIXME: mul (x, const) -> shifts + adds
30 // FIXME: undef values
31 // FIXME: make truncate see through SIGN_EXTEND and AND
32 // FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
33 // FIXME: verify that getNode can't return extends with an operand whose type
34 // is >= to that of the extend.
35 // FIXME: divide by zero is currently left unfolded. do we want to turn this
37 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
38 // FIXME: reassociate (X+C)+Y into (X+Y)+C if the inner expression has one use
40 //===----------------------------------------------------------------------===//
42 #define DEBUG_TYPE "dagcombine"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/MathExtras.h"
47 #include "llvm/Target/TargetLowering.h"
53 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
60 // Worklist of all of the nodes that need to be simplified.
61 std::vector<SDNode*> WorkList;
63 /// AddUsersToWorkList - When an instruction is simplified, add all users of
64 /// the instruction to the work lists because they might get more simplified
67 void AddUsersToWorkList(SDNode *N) {
68 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
70 WorkList.push_back(*UI);
73 /// removeFromWorkList - remove all instances of N from the worklist.
74 void removeFromWorkList(SDNode *N) {
75 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
79 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
81 DEBUG(std::cerr << "\nReplacing "; N->dump();
82 std::cerr << "\nWith: "; To[0].Val->dump();
83 std::cerr << " and " << To.size()-1 << " other values\n");
84 std::vector<SDNode*> NowDead;
85 DAG.ReplaceAllUsesWith(N, To, &NowDead);
87 // Push the new nodes and any users onto the worklist
88 for (unsigned i = 0, e = To.size(); i != e; ++i) {
89 WorkList.push_back(To[i].Val);
90 AddUsersToWorkList(To[i].Val);
93 // Nodes can end up on the worklist more than once. Make sure we do
94 // not process a node that has been replaced.
95 removeFromWorkList(N);
96 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
97 removeFromWorkList(NowDead[i]);
99 // Finally, since the node is now dead, remove it from the graph.
101 return SDOperand(N, 0);
104 SDOperand CombineTo(SDNode *N, SDOperand Res) {
105 std::vector<SDOperand> To;
107 return CombineTo(N, To);
110 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
111 std::vector<SDOperand> To;
114 return CombineTo(N, To);
117 /// visit - call the node-specific routine that knows how to fold each
118 /// particular type of node.
119 SDOperand visit(SDNode *N);
121 // Visitation implementation - Implement dag node combining for different
122 // node types. The semantics are as follows:
124 // SDOperand.Val == 0 - No change was made
125 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
126 // otherwise - N should be replaced by the returned Operand.
128 SDOperand visitTokenFactor(SDNode *N);
129 SDOperand visitADD(SDNode *N);
130 SDOperand visitSUB(SDNode *N);
131 SDOperand visitMUL(SDNode *N);
132 SDOperand visitSDIV(SDNode *N);
133 SDOperand visitUDIV(SDNode *N);
134 SDOperand visitSREM(SDNode *N);
135 SDOperand visitUREM(SDNode *N);
136 SDOperand visitMULHU(SDNode *N);
137 SDOperand visitMULHS(SDNode *N);
138 SDOperand visitAND(SDNode *N);
139 SDOperand visitOR(SDNode *N);
140 SDOperand visitXOR(SDNode *N);
141 SDOperand visitSHL(SDNode *N);
142 SDOperand visitSRA(SDNode *N);
143 SDOperand visitSRL(SDNode *N);
144 SDOperand visitCTLZ(SDNode *N);
145 SDOperand visitCTTZ(SDNode *N);
146 SDOperand visitCTPOP(SDNode *N);
147 SDOperand visitSELECT(SDNode *N);
148 SDOperand visitSELECT_CC(SDNode *N);
149 SDOperand visitSETCC(SDNode *N);
150 SDOperand visitSIGN_EXTEND(SDNode *N);
151 SDOperand visitZERO_EXTEND(SDNode *N);
152 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
153 SDOperand visitTRUNCATE(SDNode *N);
155 SDOperand visitFADD(SDNode *N);
156 SDOperand visitFSUB(SDNode *N);
157 SDOperand visitFMUL(SDNode *N);
158 SDOperand visitFDIV(SDNode *N);
159 SDOperand visitFREM(SDNode *N);
160 SDOperand visitSINT_TO_FP(SDNode *N);
161 SDOperand visitUINT_TO_FP(SDNode *N);
162 SDOperand visitFP_TO_SINT(SDNode *N);
163 SDOperand visitFP_TO_UINT(SDNode *N);
164 SDOperand visitFP_ROUND(SDNode *N);
165 SDOperand visitFP_ROUND_INREG(SDNode *N);
166 SDOperand visitFP_EXTEND(SDNode *N);
167 SDOperand visitFNEG(SDNode *N);
168 SDOperand visitFABS(SDNode *N);
169 SDOperand visitBRCOND(SDNode *N);
170 SDOperand visitBRCONDTWOWAY(SDNode *N);
171 SDOperand visitBR_CC(SDNode *N);
172 SDOperand visitBRTWOWAY_CC(SDNode *N);
174 SDOperand visitLOAD(SDNode *N);
175 SDOperand visitSTORE(SDNode *N);
177 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
178 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
179 SDOperand N3, ISD::CondCode CC);
180 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
181 ISD::CondCode Cond, bool foldBooleans = true);
183 DAGCombiner(SelectionDAG &D)
184 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
186 /// Run - runs the dag combiner on all nodes in the work list
187 void Run(bool RunningAfterLegalize);
191 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use
192 /// this predicate to simplify operations downstream. Op and Mask are known to
193 /// be the same type.
194 static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
195 const TargetLowering &TLI) {
197 if (Mask == 0) return true;
199 // If we know the result of a setcc has the top bits zero, use this info.
200 switch (Op.getOpcode()) {
202 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
204 return ((Mask & 1) == 0) &&
205 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
207 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
208 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
209 case ISD::ZERO_EXTEND:
210 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
211 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
212 case ISD::AssertZext:
213 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
214 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
216 // If either of the operands has zero bits, the result will too.
217 if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) ||
218 MaskedValueIsZero(Op.getOperand(0), Mask, TLI))
220 // (X & C1) & C2 == 0 iff C1 & C2 == 0.
221 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
222 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
226 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
227 MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
229 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
230 MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
232 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
233 MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
235 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
236 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
237 uint64_t NewVal = Mask << ShAmt->getValue();
238 SrcBits = MVT::getSizeInBits(Op.getValueType());
239 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
240 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
244 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
245 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
246 uint64_t NewVal = Mask >> ShAmt->getValue();
247 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
251 // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits.
252 if ((Mask&(Mask+1)) == 0) { // All low bits
253 if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
254 MaskedValueIsZero(Op.getOperand(1), Mask, TLI))
259 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
260 // We know that the top bits of C-X are clear if X contains less bits
261 // than C (i.e. no wrap-around can happen). For example, 20-X is
262 // positive if we can prove that X is >= 0 and < 16.
263 unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0));
264 if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear
265 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
266 uint64_t MaskV = (1ULL << (63-NLZ))-1;
267 if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) {
268 // High bits are clear this value is known to be >= C.
269 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
270 if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0)
279 // Bit counting instructions can not set the high bits of the result
280 // register. The max number of bits sets depends on the input.
281 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
283 // TODO we could handle some SRA cases here.
289 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
290 // that selects between the values 1 and 0, making it equivalent to a setcc.
291 // Also, set the incoming LHS, RHS, and CC references to the appropriate
292 // nodes based on the type of node we are checking. This simplifies life a
293 // bit for the callers.
294 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
296 if (N.getOpcode() == ISD::SETCC) {
297 LHS = N.getOperand(0);
298 RHS = N.getOperand(1);
299 CC = N.getOperand(2);
302 if (N.getOpcode() == ISD::SELECT_CC &&
303 N.getOperand(2).getOpcode() == ISD::Constant &&
304 N.getOperand(3).getOpcode() == ISD::Constant &&
305 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
306 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
307 LHS = N.getOperand(0);
308 RHS = N.getOperand(1);
309 CC = N.getOperand(4);
315 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
316 // one use. If this is true, it allows the users to invert the operation for
317 // free when it is profitable to do so.
318 static bool isOneUseSetCC(SDOperand N) {
319 SDOperand N0, N1, N2;
320 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
325 // FIXME: This should probably go in the ISD class rather than being duplicated
327 static bool isCommutativeBinOp(unsigned Opcode) {
333 case ISD::XOR: return true;
334 default: return false; // FIXME: Need commutative info for user ops!
338 void DAGCombiner::Run(bool RunningAfterLegalize) {
339 // set the instance variable, so that the various visit routines may use it.
340 AfterLegalize = RunningAfterLegalize;
342 // Add all the dag nodes to the worklist.
343 WorkList.insert(WorkList.end(), DAG.allnodes_begin(), DAG.allnodes_end());
345 // Create a dummy node (which is not added to allnodes), that adds a reference
346 // to the root node, preventing it from being deleted, and tracking any
347 // changes of the root.
348 HandleSDNode Dummy(DAG.getRoot());
350 // while the worklist isn't empty, inspect the node on the end of it and
351 // try and combine it.
352 while (!WorkList.empty()) {
353 SDNode *N = WorkList.back();
356 // If N has no uses, it is dead. Make sure to revisit all N's operands once
357 // N is deleted from the DAG, since they too may now be dead or may have a
358 // reduced number of uses, allowing other xforms.
359 if (N->use_empty() && N != &Dummy) {
360 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
361 WorkList.push_back(N->getOperand(i).Val);
363 removeFromWorkList(N);
368 SDOperand RV = visit(N);
371 // If we get back the same node we passed in, rather than a new node or
372 // zero, we know that the node must have defined multiple values and
373 // CombineTo was used. Since CombineTo takes care of the worklist
374 // mechanics for us, we have no work to do in this case.
376 DEBUG(std::cerr << "\nReplacing "; N->dump();
377 std::cerr << "\nWith: "; RV.Val->dump();
379 std::vector<SDNode*> NowDead;
380 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
382 // Push the new node and any users onto the worklist
383 WorkList.push_back(RV.Val);
384 AddUsersToWorkList(RV.Val);
386 // Nodes can end up on the worklist more than once. Make sure we do
387 // not process a node that has been replaced.
388 removeFromWorkList(N);
389 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
390 removeFromWorkList(NowDead[i]);
392 // Finally, since the node is now dead, remove it from the graph.
398 // If the root changed (e.g. it was a dead load, update the root).
399 DAG.setRoot(Dummy.getValue());
402 SDOperand DAGCombiner::visit(SDNode *N) {
403 switch(N->getOpcode()) {
405 case ISD::TokenFactor: return visitTokenFactor(N);
406 case ISD::ADD: return visitADD(N);
407 case ISD::SUB: return visitSUB(N);
408 case ISD::MUL: return visitMUL(N);
409 case ISD::SDIV: return visitSDIV(N);
410 case ISD::UDIV: return visitUDIV(N);
411 case ISD::SREM: return visitSREM(N);
412 case ISD::UREM: return visitUREM(N);
413 case ISD::MULHU: return visitMULHU(N);
414 case ISD::MULHS: return visitMULHS(N);
415 case ISD::AND: return visitAND(N);
416 case ISD::OR: return visitOR(N);
417 case ISD::XOR: return visitXOR(N);
418 case ISD::SHL: return visitSHL(N);
419 case ISD::SRA: return visitSRA(N);
420 case ISD::SRL: return visitSRL(N);
421 case ISD::CTLZ: return visitCTLZ(N);
422 case ISD::CTTZ: return visitCTTZ(N);
423 case ISD::CTPOP: return visitCTPOP(N);
424 case ISD::SELECT: return visitSELECT(N);
425 case ISD::SELECT_CC: return visitSELECT_CC(N);
426 case ISD::SETCC: return visitSETCC(N);
427 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
428 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
429 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
430 case ISD::TRUNCATE: return visitTRUNCATE(N);
431 case ISD::FADD: return visitFADD(N);
432 case ISD::FSUB: return visitFSUB(N);
433 case ISD::FMUL: return visitFMUL(N);
434 case ISD::FDIV: return visitFDIV(N);
435 case ISD::FREM: return visitFREM(N);
436 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
437 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
438 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
439 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
440 case ISD::FP_ROUND: return visitFP_ROUND(N);
441 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
442 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
443 case ISD::FNEG: return visitFNEG(N);
444 case ISD::FABS: return visitFABS(N);
445 case ISD::BRCOND: return visitBRCOND(N);
446 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
447 case ISD::BR_CC: return visitBR_CC(N);
448 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
449 case ISD::LOAD: return visitLOAD(N);
450 case ISD::STORE: return visitSTORE(N);
455 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
456 // If the token factor has two operands and one is the entry token, replace
457 // the token factor with the other operand.
458 if (N->getNumOperands() == 2) {
459 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
460 return N->getOperand(1);
461 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
462 return N->getOperand(0);
467 SDOperand DAGCombiner::visitADD(SDNode *N) {
468 SDOperand N0 = N->getOperand(0);
469 SDOperand N1 = N->getOperand(1);
470 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
471 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
472 MVT::ValueType VT = N0.getValueType();
474 // fold (add c1, c2) -> c1+c2
476 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT);
477 // canonicalize constant to RHS
482 // fold (add x, 0) -> x
483 if (N1C && N1C->isNullValue())
485 // fold (add (add x, c1), c2) -> (add x, c1+c2)
486 if (N1C && N0.getOpcode() == ISD::ADD) {
487 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
488 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
490 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1),
491 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT));
493 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0),
494 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT));
496 // fold ((0-A) + B) -> B-A
497 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
498 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
499 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
500 // fold (A + (0-B)) -> A-B
501 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
502 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
503 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
504 // fold (A+(B-A)) -> B
505 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
506 return N1.getOperand(0);
510 SDOperand DAGCombiner::visitSUB(SDNode *N) {
511 SDOperand N0 = N->getOperand(0);
512 SDOperand N1 = N->getOperand(1);
513 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
514 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
516 // fold (sub c1, c2) -> c1-c2
518 return DAG.getConstant(N0C->getValue() - N1C->getValue(),
520 // fold (sub x, c) -> (add x, -c)
522 return DAG.getNode(ISD::ADD, N0.getValueType(), N0,
523 DAG.getConstant(-N1C->getValue(), N0.getValueType()));
526 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
527 return N0.getOperand(1);
529 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
530 return N0.getOperand(0);
534 SDOperand DAGCombiner::visitMUL(SDNode *N) {
535 SDOperand N0 = N->getOperand(0);
536 SDOperand N1 = N->getOperand(1);
537 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
538 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
539 MVT::ValueType VT = N0.getValueType();
541 // fold (mul c1, c2) -> c1*c2
543 return DAG.getConstant(N0C->getValue() * N1C->getValue(),
545 // canonicalize constant to RHS
550 // fold (mul x, 0) -> 0
551 if (N1C && N1C->isNullValue())
553 // fold (mul x, -1) -> 0-x
554 if (N1C && N1C->isAllOnesValue())
555 return DAG.getNode(ISD::SUB, N->getValueType(0),
556 DAG.getConstant(0, N->getValueType(0)), N0);
557 // fold (mul x, (1 << c)) -> x << c
558 if (N1C && isPowerOf2_64(N1C->getValue()))
559 return DAG.getNode(ISD::SHL, N->getValueType(0), N0,
560 DAG.getConstant(Log2_64(N1C->getValue()),
561 TLI.getShiftAmountTy()));
562 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2)
563 if (N1C && N0.getOpcode() == ISD::MUL) {
564 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
565 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
567 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1),
568 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT));
570 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0),
571 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT));
576 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
577 SDOperand N0 = N->getOperand(0);
578 SDOperand N1 = N->getOperand(1);
579 MVT::ValueType VT = N->getValueType(0);
580 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
581 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
583 // fold (sdiv c1, c2) -> c1/c2
584 if (N0C && N1C && !N1C->isNullValue())
585 return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(),
587 // If we know the sign bits of both operands are zero, strength reduce to a
588 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
589 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
590 if (MaskedValueIsZero(N1, SignBit, TLI) &&
591 MaskedValueIsZero(N0, SignBit, TLI))
592 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
596 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
597 SDOperand N0 = N->getOperand(0);
598 SDOperand N1 = N->getOperand(1);
599 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
600 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
602 // fold (udiv c1, c2) -> c1/c2
603 if (N0C && N1C && !N1C->isNullValue())
604 return DAG.getConstant(N0C->getValue() / N1C->getValue(),
606 // fold (udiv x, (1 << c)) -> x >>u c
607 if (N1C && isPowerOf2_64(N1C->getValue()))
608 return DAG.getNode(ISD::SRL, N->getValueType(0), N0,
609 DAG.getConstant(Log2_64(N1C->getValue()),
610 TLI.getShiftAmountTy()));
614 SDOperand DAGCombiner::visitSREM(SDNode *N) {
615 SDOperand N0 = N->getOperand(0);
616 SDOperand N1 = N->getOperand(1);
617 MVT::ValueType VT = N->getValueType(0);
618 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
619 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
621 // fold (srem c1, c2) -> c1%c2
622 if (N0C && N1C && !N1C->isNullValue())
623 return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(),
625 // If we know the sign bits of both operands are zero, strength reduce to a
626 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
627 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
628 if (MaskedValueIsZero(N1, SignBit, TLI) &&
629 MaskedValueIsZero(N0, SignBit, TLI))
630 return DAG.getNode(ISD::UREM, N1.getValueType(), N0, N1);
634 SDOperand DAGCombiner::visitUREM(SDNode *N) {
635 SDOperand N0 = N->getOperand(0);
636 SDOperand N1 = N->getOperand(1);
637 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
638 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
640 // fold (urem c1, c2) -> c1%c2
641 if (N0C && N1C && !N1C->isNullValue())
642 return DAG.getConstant(N0C->getValue() % N1C->getValue(),
644 // fold (urem x, pow2) -> (and x, pow2-1)
645 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
646 return DAG.getNode(ISD::AND, N0.getValueType(), N0,
647 DAG.getConstant(N1C->getValue()-1, N1.getValueType()));
651 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
652 SDOperand N0 = N->getOperand(0);
653 SDOperand N1 = N->getOperand(1);
654 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
656 // fold (mulhs x, 0) -> 0
657 if (N1C && N1C->isNullValue())
659 // fold (mulhs x, 1) -> (sra x, size(x)-1)
660 if (N1C && N1C->getValue() == 1)
661 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
662 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
663 TLI.getShiftAmountTy()));
667 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
668 SDOperand N0 = N->getOperand(0);
669 SDOperand N1 = N->getOperand(1);
670 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
672 // fold (mulhu x, 0) -> 0
673 if (N1C && N1C->isNullValue())
675 // fold (mulhu x, 1) -> 0
676 if (N1C && N1C->getValue() == 1)
677 return DAG.getConstant(0, N0.getValueType());
681 SDOperand DAGCombiner::visitAND(SDNode *N) {
682 SDOperand N0 = N->getOperand(0);
683 SDOperand N1 = N->getOperand(1);
684 SDOperand LL, LR, RL, RR, CC0, CC1;
685 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
686 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
687 MVT::ValueType VT = N1.getValueType();
688 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
690 // fold (and c1, c2) -> c1&c2
692 return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT);
693 // canonicalize constant to RHS
698 // fold (and x, -1) -> x
699 if (N1C && N1C->isAllOnesValue())
701 // if (and x, c) is known to be zero, return 0
702 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
703 return DAG.getConstant(0, VT);
704 // fold (and x, c) -> x iff (x & ~c) == 0
705 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
708 // fold (and (and x, c1), c2) -> (and x, c1^c2)
709 if (N1C && N0.getOpcode() == ISD::AND) {
710 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
711 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
713 return DAG.getNode(ISD::AND, VT, N0.getOperand(1),
714 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT));
716 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
717 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT));
719 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
720 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
721 unsigned ExtendBits =
722 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
723 if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0)
724 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
726 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
727 if (N0.getOpcode() == ISD::OR && N1C)
728 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
729 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
731 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
732 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
733 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
734 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
736 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
737 MVT::isInteger(LL.getValueType())) {
738 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
739 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
740 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
741 WorkList.push_back(ORNode.Val);
742 return DAG.getSetCC(VT, ORNode, LR, Op1);
744 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
745 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
746 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
747 WorkList.push_back(ANDNode.Val);
748 return DAG.getSetCC(VT, ANDNode, LR, Op1);
750 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
751 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
752 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
753 WorkList.push_back(ORNode.Val);
754 return DAG.getSetCC(VT, ORNode, LR, Op1);
757 // canonicalize equivalent to ll == rl
758 if (LL == RR && LR == RL) {
759 Op1 = ISD::getSetCCSwappedOperands(Op1);
762 if (LL == RL && LR == RR) {
763 bool isInteger = MVT::isInteger(LL.getValueType());
764 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
765 if (Result != ISD::SETCC_INVALID)
766 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
769 // fold (and (zext x), (zext y)) -> (zext (and x, y))
770 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
771 N1.getOpcode() == ISD::ZERO_EXTEND &&
772 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
773 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
774 N0.getOperand(0), N1.getOperand(0));
775 WorkList.push_back(ANDNode.Val);
776 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
778 // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y))
779 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
780 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) &&
781 N0.getOperand(1) == N1.getOperand(1)) {
782 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
783 N0.getOperand(0), N1.getOperand(0));
784 WorkList.push_back(ANDNode.Val);
785 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
790 SDOperand DAGCombiner::visitOR(SDNode *N) {
791 SDOperand N0 = N->getOperand(0);
792 SDOperand N1 = N->getOperand(1);
793 SDOperand LL, LR, RL, RR, CC0, CC1;
794 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
795 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
796 MVT::ValueType VT = N1.getValueType();
797 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
799 // fold (or c1, c2) -> c1|c2
801 return DAG.getConstant(N0C->getValue() | N1C->getValue(),
803 // canonicalize constant to RHS
808 // fold (or x, 0) -> x
809 if (N1C && N1C->isNullValue())
811 // fold (or x, -1) -> -1
812 if (N1C && N1C->isAllOnesValue())
814 // fold (or x, c) -> c iff (x & ~c) == 0
815 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
818 // fold (or (or x, c1), c2) -> (or x, c1|c2)
819 if (N1C && N0.getOpcode() == ISD::OR) {
820 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
821 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
823 return DAG.getNode(ISD::OR, VT, N0.getOperand(1),
824 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT));
826 return DAG.getNode(ISD::OR, VT, N0.getOperand(0),
827 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT));
829 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
830 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
831 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
832 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
834 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
835 MVT::isInteger(LL.getValueType())) {
836 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
837 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
838 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
839 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
840 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
841 WorkList.push_back(ORNode.Val);
842 return DAG.getSetCC(VT, ORNode, LR, Op1);
844 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
845 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
846 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
847 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
848 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
849 WorkList.push_back(ANDNode.Val);
850 return DAG.getSetCC(VT, ANDNode, LR, Op1);
853 // canonicalize equivalent to ll == rl
854 if (LL == RR && LR == RL) {
855 Op1 = ISD::getSetCCSwappedOperands(Op1);
858 if (LL == RL && LR == RR) {
859 bool isInteger = MVT::isInteger(LL.getValueType());
860 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
861 if (Result != ISD::SETCC_INVALID)
862 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
865 // fold (or (zext x), (zext y)) -> (zext (or x, y))
866 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
867 N1.getOpcode() == ISD::ZERO_EXTEND &&
868 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
869 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
870 N0.getOperand(0), N1.getOperand(0));
871 WorkList.push_back(ORNode.Val);
872 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
877 SDOperand DAGCombiner::visitXOR(SDNode *N) {
878 SDOperand N0 = N->getOperand(0);
879 SDOperand N1 = N->getOperand(1);
880 SDOperand LHS, RHS, CC;
881 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
882 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
883 MVT::ValueType VT = N0.getValueType();
885 // fold (xor c1, c2) -> c1^c2
887 return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT);
888 // canonicalize constant to RHS
893 // fold (xor x, 0) -> x
894 if (N1C && N1C->isNullValue())
896 // fold !(x cc y) -> (x !cc y)
897 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
898 bool isInt = MVT::isInteger(LHS.getValueType());
899 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
901 if (N0.getOpcode() == ISD::SETCC)
902 return DAG.getSetCC(VT, LHS, RHS, NotCC);
903 if (N0.getOpcode() == ISD::SELECT_CC)
904 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
905 assert(0 && "Unhandled SetCC Equivalent!");
908 // fold !(x or y) -> (!x and !y) iff x or y are setcc
909 if (N1C && N1C->getValue() == 1 &&
910 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
911 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
912 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
913 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
914 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
915 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
916 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
917 return DAG.getNode(NewOpcode, VT, LHS, RHS);
920 // fold !(x or y) -> (!x and !y) iff x or y are constants
921 if (N1C && N1C->isAllOnesValue() &&
922 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
923 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
924 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
925 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
926 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
927 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
928 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
929 return DAG.getNode(NewOpcode, VT, LHS, RHS);
932 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
933 if (N1C && N0.getOpcode() == ISD::XOR) {
934 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
935 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
937 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
938 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
940 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
941 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
943 // fold (xor x, x) -> 0
945 return DAG.getConstant(0, VT);
946 // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
947 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
948 N1.getOpcode() == ISD::ZERO_EXTEND &&
949 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
950 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
951 N0.getOperand(0), N1.getOperand(0));
952 WorkList.push_back(XORNode.Val);
953 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
958 SDOperand DAGCombiner::visitSHL(SDNode *N) {
959 SDOperand N0 = N->getOperand(0);
960 SDOperand N1 = N->getOperand(1);
961 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
962 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
963 MVT::ValueType VT = N0.getValueType();
964 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
966 // fold (shl c1, c2) -> c1<<c2
968 return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT);
969 // fold (shl 0, x) -> 0
970 if (N0C && N0C->isNullValue())
972 // fold (shl x, c >= size(x)) -> undef
973 if (N1C && N1C->getValue() >= OpSizeInBits)
974 return DAG.getNode(ISD::UNDEF, VT);
975 // fold (shl x, 0) -> x
976 if (N1C && N1C->isNullValue())
978 // if (shl x, c) is known to be zero, return 0
979 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
980 return DAG.getConstant(0, VT);
981 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
982 if (N1C && N0.getOpcode() == ISD::SHL &&
983 N0.getOperand(1).getOpcode() == ISD::Constant) {
984 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
985 uint64_t c2 = N1C->getValue();
986 if (c1 + c2 > OpSizeInBits)
987 return DAG.getConstant(0, VT);
988 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
989 DAG.getConstant(c1 + c2, N1.getValueType()));
991 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
992 // (srl (and x, -1 << c1), c1-c2)
993 if (N1C && N0.getOpcode() == ISD::SRL &&
994 N0.getOperand(1).getOpcode() == ISD::Constant) {
995 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
996 uint64_t c2 = N1C->getValue();
997 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
998 DAG.getConstant(~0ULL << c1, VT));
1000 return DAG.getNode(ISD::SHL, VT, Mask,
1001 DAG.getConstant(c2-c1, N1.getValueType()));
1003 return DAG.getNode(ISD::SRL, VT, Mask,
1004 DAG.getConstant(c1-c2, N1.getValueType()));
1006 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1007 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1008 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1009 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1013 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1014 SDOperand N0 = N->getOperand(0);
1015 SDOperand N1 = N->getOperand(1);
1016 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1017 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1018 MVT::ValueType VT = N0.getValueType();
1019 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1021 // fold (sra c1, c2) -> c1>>c2
1023 return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT);
1024 // fold (sra 0, x) -> 0
1025 if (N0C && N0C->isNullValue())
1027 // fold (sra -1, x) -> -1
1028 if (N0C && N0C->isAllOnesValue())
1030 // fold (sra x, c >= size(x)) -> undef
1031 if (N1C && N1C->getValue() >= OpSizeInBits)
1032 return DAG.getNode(ISD::UNDEF, VT);
1033 // fold (sra x, 0) -> x
1034 if (N1C && N1C->isNullValue())
1036 // If the sign bit is known to be zero, switch this to a SRL.
1037 if (N1C && MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI))
1038 return DAG.getNode(ISD::SRL, VT, N0, N1);
1042 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1043 SDOperand N0 = N->getOperand(0);
1044 SDOperand N1 = N->getOperand(1);
1045 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1046 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1047 MVT::ValueType VT = N0.getValueType();
1048 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1050 // fold (srl c1, c2) -> c1 >>u c2
1052 return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT);
1053 // fold (srl 0, x) -> 0
1054 if (N0C && N0C->isNullValue())
1056 // fold (srl x, c >= size(x)) -> undef
1057 if (N1C && N1C->getValue() >= OpSizeInBits)
1058 return DAG.getNode(ISD::UNDEF, VT);
1059 // fold (srl x, 0) -> x
1060 if (N1C && N1C->isNullValue())
1062 // if (srl x, c) is known to be zero, return 0
1063 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
1064 return DAG.getConstant(0, VT);
1065 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1066 if (N1C && N0.getOpcode() == ISD::SRL &&
1067 N0.getOperand(1).getOpcode() == ISD::Constant) {
1068 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1069 uint64_t c2 = N1C->getValue();
1070 if (c1 + c2 > OpSizeInBits)
1071 return DAG.getConstant(0, VT);
1072 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1073 DAG.getConstant(c1 + c2, N1.getValueType()));
1078 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1079 SDOperand N0 = N->getOperand(0);
1080 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1082 // fold (ctlz c1) -> c2
1084 return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()),
1089 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1090 SDOperand N0 = N->getOperand(0);
1091 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1093 // fold (cttz c1) -> c2
1095 return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()),
1100 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1101 SDOperand N0 = N->getOperand(0);
1102 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1104 // fold (ctpop c1) -> c2
1106 return DAG.getConstant(CountPopulation_64(N0C->getValue()),
1111 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1112 SDOperand N0 = N->getOperand(0);
1113 SDOperand N1 = N->getOperand(1);
1114 SDOperand N2 = N->getOperand(2);
1115 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1116 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1117 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1118 MVT::ValueType VT = N->getValueType(0);
1120 // fold select C, X, X -> X
1123 // fold select true, X, Y -> X
1124 if (N0C && !N0C->isNullValue())
1126 // fold select false, X, Y -> Y
1127 if (N0C && N0C->isNullValue())
1129 // fold select C, 1, X -> C | X
1130 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1131 return DAG.getNode(ISD::OR, VT, N0, N2);
1132 // fold select C, 0, X -> ~C & X
1133 // FIXME: this should check for C type == X type, not i1?
1134 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1135 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1136 WorkList.push_back(XORNode.Val);
1137 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1139 // fold select C, X, 1 -> ~C | X
1140 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1141 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1142 WorkList.push_back(XORNode.Val);
1143 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1145 // fold select C, X, 0 -> C & X
1146 // FIXME: this should check for C type == X type, not i1?
1147 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1148 return DAG.getNode(ISD::AND, VT, N0, N1);
1149 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1150 if (MVT::i1 == VT && N0 == N1)
1151 return DAG.getNode(ISD::OR, VT, N0, N2);
1152 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1153 if (MVT::i1 == VT && N0 == N2)
1154 return DAG.getNode(ISD::AND, VT, N0, N1);
1155 // fold selects based on a setcc into other things, such as min/max/abs
1156 if (N0.getOpcode() == ISD::SETCC)
1157 return SimplifySelect(N0, N1, N2);
1161 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1162 SDOperand N0 = N->getOperand(0);
1163 SDOperand N1 = N->getOperand(1);
1164 SDOperand N2 = N->getOperand(2);
1165 SDOperand N3 = N->getOperand(3);
1166 SDOperand N4 = N->getOperand(4);
1167 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1168 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1169 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1170 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1172 // Determine if the condition we're dealing with is constant
1173 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1174 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1176 // fold select_cc lhs, rhs, x, x, cc -> x
1179 // fold select_cc into other things, such as min/max/abs
1180 return SimplifySelectCC(N0, N1, N2, N3, CC);
1183 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1184 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1185 cast<CondCodeSDNode>(N->getOperand(2))->get());
1188 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1189 SDOperand N0 = N->getOperand(0);
1190 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1191 MVT::ValueType VT = N->getValueType(0);
1193 // fold (sext c1) -> c1
1195 return DAG.getConstant(N0C->getSignExtended(), VT);
1196 // fold (sext (sext x)) -> (sext x)
1197 if (N0.getOpcode() == ISD::SIGN_EXTEND)
1198 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1202 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1203 SDOperand N0 = N->getOperand(0);
1204 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1205 MVT::ValueType VT = N->getValueType(0);
1207 // fold (zext c1) -> c1
1209 return DAG.getConstant(N0C->getValue(), VT);
1210 // fold (zext (zext x)) -> (zext x)
1211 if (N0.getOpcode() == ISD::ZERO_EXTEND)
1212 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1216 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1217 SDOperand N0 = N->getOperand(0);
1218 SDOperand N1 = N->getOperand(1);
1219 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1220 MVT::ValueType VT = N->getValueType(0);
1221 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1222 unsigned EVTBits = MVT::getSizeInBits(EVT);
1224 // fold (sext_in_reg c1) -> c1
1226 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1227 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1229 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1230 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1231 cast<VTSDNode>(N0.getOperand(1))->getVT() < EVT) {
1234 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1235 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1236 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1237 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1239 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1240 if (N0.getOpcode() == ISD::AssertSext &&
1241 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1244 // fold (sext_in_reg (sextload x)) -> (sextload x)
1245 if (N0.getOpcode() == ISD::SEXTLOAD &&
1246 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1249 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1250 if (N0.getOpcode() == ISD::SETCC &&
1251 TLI.getSetCCResultContents() ==
1252 TargetLowering::ZeroOrNegativeOneSetCCResult)
1254 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1255 if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI))
1256 return DAG.getNode(ISD::AND, N0.getValueType(), N0,
1257 DAG.getConstant(~0ULL >> (64-EVTBits), VT));
1258 // fold (sext_in_reg (srl x)) -> sra x
1259 if (N0.getOpcode() == ISD::SRL &&
1260 N0.getOperand(1).getOpcode() == ISD::Constant &&
1261 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
1262 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
1268 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1269 SDOperand N0 = N->getOperand(0);
1270 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1271 MVT::ValueType VT = N->getValueType(0);
1274 if (N0.getValueType() == N->getValueType(0))
1276 // fold (truncate c1) -> c1
1278 return DAG.getConstant(N0C->getValue(), VT);
1279 // fold (truncate (truncate x)) -> (truncate x)
1280 if (N0.getOpcode() == ISD::TRUNCATE)
1281 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1282 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1283 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
1284 if (N0.getValueType() < VT)
1285 // if the source is smaller than the dest, we still need an extend
1286 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1287 else if (N0.getValueType() > VT)
1288 // if the source is larger than the dest, than we just need the truncate
1289 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1291 // if the source and dest are the same type, we can drop both the extend
1293 return N0.getOperand(0);
1298 SDOperand DAGCombiner::visitFADD(SDNode *N) {
1299 SDOperand N0 = N->getOperand(0);
1300 SDOperand N1 = N->getOperand(1);
1301 MVT::ValueType VT = N->getValueType(0);
1303 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1304 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1305 // fold floating point (fadd c1, c2)
1306 return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(),
1307 N->getValueType(0));
1309 // fold (A + (-B)) -> A-B
1310 if (N1.getOpcode() == ISD::FNEG)
1311 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
1313 // fold ((-A) + B) -> B-A
1314 if (N0.getOpcode() == ISD::FNEG)
1315 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
1320 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
1321 SDOperand N0 = N->getOperand(0);
1322 SDOperand N1 = N->getOperand(1);
1323 MVT::ValueType VT = N->getValueType(0);
1325 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1326 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1327 // fold floating point (fsub c1, c2)
1328 return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(),
1329 N->getValueType(0));
1331 // fold (A-(-B)) -> A+B
1332 if (N1.getOpcode() == ISD::FNEG)
1333 return DAG.getNode(ISD::FADD, N0.getValueType(), N0, N1.getOperand(0));
1338 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
1339 SDOperand N0 = N->getOperand(0);
1340 SDOperand N1 = N->getOperand(1);
1341 MVT::ValueType VT = N->getValueType(0);
1343 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1344 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1345 // fold floating point (fmul c1, c2)
1346 return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(),
1347 N->getValueType(0));
1352 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
1353 SDOperand N0 = N->getOperand(0);
1354 SDOperand N1 = N->getOperand(1);
1355 MVT::ValueType VT = N->getValueType(0);
1357 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1358 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1359 // fold floating point (fdiv c1, c2)
1360 return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(),
1361 N->getValueType(0));
1366 SDOperand DAGCombiner::visitFREM(SDNode *N) {
1367 SDOperand N0 = N->getOperand(0);
1368 SDOperand N1 = N->getOperand(1);
1369 MVT::ValueType VT = N->getValueType(0);
1371 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1372 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1373 // fold floating point (frem c1, c2) -> fmod(c1, c2)
1374 return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()),
1375 N->getValueType(0));
1381 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
1382 SDOperand N0 = N->getOperand(0);
1383 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1385 // fold (sint_to_fp c1) -> c1fp
1387 return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0));
1391 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
1392 SDOperand N0 = N->getOperand(0);
1393 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1395 // fold (uint_to_fp c1) -> c1fp
1397 return DAG.getConstantFP(N0C->getValue(), N->getValueType(0));
1401 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
1402 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1404 // fold (fp_to_sint c1fp) -> c1
1406 return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0));
1410 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1411 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1413 // fold (fp_to_uint c1fp) -> c1
1415 return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0));
1419 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
1420 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1422 // fold (fp_round c1fp) -> c1fp
1424 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
1428 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
1429 SDOperand N0 = N->getOperand(0);
1430 MVT::ValueType VT = N->getValueType(0);
1431 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1432 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1434 // fold (fp_round_inreg c1fp) -> c1fp
1436 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
1437 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
1442 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
1443 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1445 // fold (fp_extend c1fp) -> c1fp
1447 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
1451 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
1452 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1453 // fold (neg c1) -> -c1
1455 return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0));
1456 // fold (neg (sub x, y)) -> (sub y, x)
1457 if (N->getOperand(0).getOpcode() == ISD::SUB)
1458 return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1),
1460 // fold (neg (neg x)) -> x
1461 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1462 return N->getOperand(0).getOperand(0);
1466 SDOperand DAGCombiner::visitFABS(SDNode *N) {
1467 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1468 // fold (fabs c1) -> fabs(c1)
1470 return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0));
1471 // fold (fabs (fabs x)) -> (fabs x)
1472 if (N->getOperand(0).getOpcode() == ISD::FABS)
1473 return N->getOperand(0);
1474 // fold (fabs (fneg x)) -> (fabs x)
1475 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1476 return DAG.getNode(ISD::FABS, N->getValueType(0),
1477 N->getOperand(0).getOperand(0));
1481 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
1482 SDOperand Chain = N->getOperand(0);
1483 SDOperand N1 = N->getOperand(1);
1484 SDOperand N2 = N->getOperand(2);
1485 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1487 // never taken branch, fold to chain
1488 if (N1C && N1C->isNullValue())
1490 // unconditional branch
1491 if (N1C && N1C->getValue() == 1)
1492 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1496 SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
1497 SDOperand Chain = N->getOperand(0);
1498 SDOperand N1 = N->getOperand(1);
1499 SDOperand N2 = N->getOperand(2);
1500 SDOperand N3 = N->getOperand(3);
1501 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1503 // unconditional branch to true mbb
1504 if (N1C && N1C->getValue() == 1)
1505 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1506 // unconditional branch to false mbb
1507 if (N1C && N1C->isNullValue())
1508 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
1512 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
1514 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
1515 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
1516 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
1518 // Use SimplifySetCC to simplify SETCC's.
1519 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
1520 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
1522 // fold br_cc true, dest -> br dest (unconditional branch)
1523 if (SCCC && SCCC->getValue())
1524 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
1526 // fold br_cc false, dest -> unconditional fall through
1527 if (SCCC && SCCC->isNullValue())
1528 return N->getOperand(0);
1529 // fold to a simpler setcc
1530 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
1531 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
1532 Simp.getOperand(2), Simp.getOperand(0),
1533 Simp.getOperand(1), N->getOperand(4));
1537 SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
1538 SDOperand Chain = N->getOperand(0);
1539 SDOperand CCN = N->getOperand(1);
1540 SDOperand LHS = N->getOperand(2);
1541 SDOperand RHS = N->getOperand(3);
1542 SDOperand N4 = N->getOperand(4);
1543 SDOperand N5 = N->getOperand(5);
1545 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
1546 cast<CondCodeSDNode>(CCN)->get(), false);
1547 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1549 // fold select_cc lhs, rhs, x, x, cc -> x
1551 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
1552 // fold select_cc true, x, y -> x
1553 if (SCCC && SCCC->getValue())
1554 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
1555 // fold select_cc false, x, y -> y
1556 if (SCCC && SCCC->isNullValue())
1557 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
1558 // fold to a simpler setcc
1559 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1560 return DAG.getBR2Way_CC(Chain, SCC.getOperand(2), SCC.getOperand(0),
1561 SCC.getOperand(1), N4, N5);
1565 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
1566 SDOperand Chain = N->getOperand(0);
1567 SDOperand Ptr = N->getOperand(1);
1568 SDOperand SrcValue = N->getOperand(2);
1570 // If this load is directly stored, replace the load value with the stored
1572 // TODO: Handle store large -> read small portion.
1573 // TODO: Handle TRUNCSTORE/EXTLOAD
1574 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
1575 Chain.getOperand(1).getValueType() == N->getValueType(0))
1576 return CombineTo(N, Chain.getOperand(1), Chain);
1581 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
1582 SDOperand Chain = N->getOperand(0);
1583 SDOperand Value = N->getOperand(1);
1584 SDOperand Ptr = N->getOperand(2);
1585 SDOperand SrcValue = N->getOperand(3);
1587 // If this is a store that kills a previous store, remove the previous store.
1588 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
1589 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */) {
1590 // Create a new store of Value that replaces both stores.
1591 SDNode *PrevStore = Chain.Val;
1592 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
1594 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
1595 PrevStore->getOperand(0), Value, Ptr,
1597 CombineTo(N, NewStore); // Nuke this store.
1598 CombineTo(PrevStore, NewStore); // Nuke the previous store.
1599 return SDOperand(N, 0);
1605 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
1606 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
1608 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
1609 cast<CondCodeSDNode>(N0.getOperand(2))->get());
1610 // If we got a simplified select_cc node back from SimplifySelectCC, then
1611 // break it down into a new SETCC node, and a new SELECT node, and then return
1612 // the SELECT node, since we were called with a SELECT node.
1614 // Check to see if we got a select_cc back (to turn into setcc/select).
1615 // Otherwise, just return whatever node we got back, like fabs.
1616 if (SCC.getOpcode() == ISD::SELECT_CC) {
1617 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
1618 SCC.getOperand(0), SCC.getOperand(1),
1620 WorkList.push_back(SETCC.Val);
1621 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
1622 SCC.getOperand(3), SETCC);
1629 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
1630 SDOperand N2, SDOperand N3,
1633 MVT::ValueType VT = N2.getValueType();
1634 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1635 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1636 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
1637 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
1639 // Determine if the condition we're dealing with is constant
1640 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1641 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1643 // fold select_cc true, x, y -> x
1644 if (SCCC && SCCC->getValue())
1646 // fold select_cc false, x, y -> y
1647 if (SCCC && SCCC->getValue() == 0)
1650 // Check to see if we can simplify the select into an fabs node
1651 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1652 // Allow either -0.0 or 0.0
1653 if (CFP->getValue() == 0.0) {
1654 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
1655 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
1656 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
1657 N2 == N3.getOperand(0))
1658 return DAG.getNode(ISD::FABS, VT, N0);
1660 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
1661 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
1662 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
1663 N2.getOperand(0) == N3)
1664 return DAG.getNode(ISD::FABS, VT, N3);
1668 // Check to see if we can perform the "gzip trick", transforming
1669 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
1670 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
1671 MVT::isInteger(N0.getValueType()) &&
1672 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
1673 MVT::ValueType XType = N0.getValueType();
1674 MVT::ValueType AType = N2.getValueType();
1675 if (XType >= AType) {
1676 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
1677 // single-bit constant.
1678 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
1679 unsigned ShCtV = Log2_64(N2C->getValue());
1680 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
1681 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
1682 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
1683 WorkList.push_back(Shift.Val);
1684 if (XType > AType) {
1685 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
1686 WorkList.push_back(Shift.Val);
1688 return DAG.getNode(ISD::AND, AType, Shift, N2);
1690 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
1691 DAG.getConstant(MVT::getSizeInBits(XType)-1,
1692 TLI.getShiftAmountTy()));
1693 WorkList.push_back(Shift.Val);
1694 if (XType > AType) {
1695 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
1696 WorkList.push_back(Shift.Val);
1698 return DAG.getNode(ISD::AND, AType, Shift, N2);
1702 // fold select C, 16, 0 -> shl C, 4
1703 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
1704 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
1705 // Get a SetCC of the condition
1706 // FIXME: Should probably make sure that setcc is legal if we ever have a
1707 // target where it isn't.
1708 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
1709 WorkList.push_back(SCC.Val);
1710 // cast from setcc result type to select result type
1712 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
1714 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
1715 WorkList.push_back(Temp.Val);
1716 // shl setcc result by log2 n2c
1717 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
1718 DAG.getConstant(Log2_64(N2C->getValue()),
1719 TLI.getShiftAmountTy()));
1722 // Check to see if this is the equivalent of setcc
1723 // FIXME: Turn all of these into setcc if setcc if setcc is legal
1724 // otherwise, go ahead with the folds.
1725 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
1726 MVT::ValueType XType = N0.getValueType();
1727 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
1728 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
1729 if (Res.getValueType() != VT)
1730 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
1734 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
1735 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
1736 TLI.isOperationLegal(ISD::CTLZ, XType)) {
1737 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
1738 return DAG.getNode(ISD::SRL, XType, Ctlz,
1739 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
1740 TLI.getShiftAmountTy()));
1742 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
1743 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
1744 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
1746 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
1747 DAG.getConstant(~0ULL, XType));
1748 return DAG.getNode(ISD::SRL, XType,
1749 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
1750 DAG.getConstant(MVT::getSizeInBits(XType)-1,
1751 TLI.getShiftAmountTy()));
1753 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
1754 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
1755 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
1756 DAG.getConstant(MVT::getSizeInBits(XType)-1,
1757 TLI.getShiftAmountTy()));
1758 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
1762 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
1763 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
1764 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
1765 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
1766 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
1767 MVT::ValueType XType = N0.getValueType();
1768 if (SubC->isNullValue() && MVT::isInteger(XType)) {
1769 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
1770 DAG.getConstant(MVT::getSizeInBits(XType)-1,
1771 TLI.getShiftAmountTy()));
1772 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
1773 WorkList.push_back(Shift.Val);
1774 WorkList.push_back(Add.Val);
1775 return DAG.getNode(ISD::XOR, XType, Add, Shift);
1783 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
1784 SDOperand N1, ISD::CondCode Cond,
1785 bool foldBooleans) {
1786 // These setcc operations always fold.
1790 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1792 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1795 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
1796 uint64_t C1 = N1C->getValue();
1797 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
1798 uint64_t C0 = N0C->getValue();
1800 // Sign extend the operands if required
1801 if (ISD::isSignedIntSetCC(Cond)) {
1802 C0 = N0C->getSignExtended();
1803 C1 = N1C->getSignExtended();
1807 default: assert(0 && "Unknown integer setcc!");
1808 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
1809 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
1810 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
1811 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
1812 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
1813 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
1814 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
1815 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
1816 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
1817 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
1820 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1821 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1822 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
1824 // If the comparison constant has bits in the upper part, the
1825 // zero-extended value could never match.
1826 if (C1 & (~0ULL << InSize)) {
1827 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
1831 case ISD::SETEQ: return DAG.getConstant(0, VT);
1834 case ISD::SETNE: return DAG.getConstant(1, VT);
1837 // True if the sign bit of C1 is set.
1838 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
1841 // True if the sign bit of C1 isn't set.
1842 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
1848 // Otherwise, we can perform the comparison with the low bits.
1856 return DAG.getSetCC(VT, N0.getOperand(0),
1857 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
1860 break; // todo, be more careful with signed comparisons
1862 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1863 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1864 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1865 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
1866 MVT::ValueType ExtDstTy = N0.getValueType();
1867 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
1869 // If the extended part has any inconsistent bits, it cannot ever
1870 // compare equal. In other words, they have to be all ones or all
1873 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
1874 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1875 return DAG.getConstant(Cond == ISD::SETNE, VT);
1878 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
1879 if (Op0Ty == ExtSrcTy) {
1880 ZextOp = N0.getOperand(0);
1882 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
1883 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
1884 DAG.getConstant(Imm, Op0Ty));
1886 WorkList.push_back(ZextOp.Val);
1887 // Otherwise, make this a use of a zext.
1888 return DAG.getSetCC(VT, ZextOp,
1889 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
1894 uint64_t MinVal, MaxVal;
1895 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
1896 if (ISD::isSignedIntSetCC(Cond)) {
1897 MinVal = 1ULL << (OperandBitSize-1);
1898 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
1899 MaxVal = ~0ULL >> (65-OperandBitSize);
1904 MaxVal = ~0ULL >> (64-OperandBitSize);
1907 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1908 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1909 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1910 --C1; // X >= C0 --> X > (C0-1)
1911 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1912 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1915 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1916 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1917 ++C1; // X <= C0 --> X < (C0+1)
1918 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1919 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1922 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1923 return DAG.getConstant(0, VT); // X < MIN --> false
1925 // Canonicalize setgt X, Min --> setne X, Min
1926 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1927 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1929 // If we have setult X, 1, turn it into seteq X, 0
1930 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1931 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
1933 // If we have setugt X, Max-1, turn it into seteq X, Max
1934 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1935 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
1938 // If we have "setcc X, C0", check to see if we can shrink the immediate
1941 // SETUGT X, SINTMAX -> SETLT X, 0
1942 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
1943 C1 == (~0ULL >> (65-OperandBitSize)))
1944 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
1947 // FIXME: Implement the rest of these.
1949 // Fold bit comparisons when we can.
1950 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1951 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1952 if (ConstantSDNode *AndRHS =
1953 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1954 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1955 // Perform the xform if the AND RHS is a single bit.
1956 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
1957 return DAG.getNode(ISD::SRL, VT, N0,
1958 DAG.getConstant(Log2_64(AndRHS->getValue()),
1959 TLI.getShiftAmountTy()));
1961 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
1962 // (X & 8) == 8 --> (X & 8) >> 3
1963 // Perform the xform if C1 is a single bit.
1964 if ((C1 & (C1-1)) == 0) {
1965 return DAG.getNode(ISD::SRL, VT, N0,
1966 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
1971 } else if (isa<ConstantSDNode>(N0.Val)) {
1972 // Ensure that the constant occurs on the RHS.
1973 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1976 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
1977 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
1978 double C0 = N0C->getValue(), C1 = N1C->getValue();
1981 default: break; // FIXME: Implement the rest of these!
1982 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
1983 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
1984 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
1985 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
1986 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
1987 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
1990 // Ensure that the constant occurs on the RHS.
1991 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1995 // We can always fold X == Y for integer setcc's.
1996 if (MVT::isInteger(N0.getValueType()))
1997 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1998 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1999 if (UOF == 2) // FP operators that are undefined on NaNs.
2000 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2001 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2002 return DAG.getConstant(UOF, VT);
2003 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2004 // if it is not already.
2005 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO;
2006 if (NewCond != Cond)
2007 return DAG.getSetCC(VT, N0, N1, NewCond);
2010 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2011 MVT::isInteger(N0.getValueType())) {
2012 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2013 N0.getOpcode() == ISD::XOR) {
2014 // Simplify (X+Y) == (X+Z) --> Y == Z
2015 if (N0.getOpcode() == N1.getOpcode()) {
2016 if (N0.getOperand(0) == N1.getOperand(0))
2017 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2018 if (N0.getOperand(1) == N1.getOperand(1))
2019 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
2020 if (isCommutativeBinOp(N0.getOpcode())) {
2021 // If X op Y == Y op X, try other combinations.
2022 if (N0.getOperand(0) == N1.getOperand(1))
2023 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
2024 if (N0.getOperand(1) == N1.getOperand(0))
2025 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2029 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes.
2030 if (N0.getOpcode() == ISD::XOR)
2031 if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2032 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2033 // If we know that all of the inverted bits are zero, don't bother
2034 // performing the inversion.
2035 if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI))
2036 return DAG.getSetCC(VT, N0.getOperand(0),
2037 DAG.getConstant(XORC->getValue()^RHSC->getValue(),
2038 N0.getValueType()), Cond);
2041 // Simplify (X+Z) == X --> Z == 0
2042 if (N0.getOperand(0) == N1)
2043 return DAG.getSetCC(VT, N0.getOperand(1),
2044 DAG.getConstant(0, N0.getValueType()), Cond);
2045 if (N0.getOperand(1) == N1) {
2046 if (isCommutativeBinOp(N0.getOpcode()))
2047 return DAG.getSetCC(VT, N0.getOperand(0),
2048 DAG.getConstant(0, N0.getValueType()), Cond);
2050 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2051 // (Z-X) == X --> Z == X<<1
2052 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
2054 DAG.getConstant(1,TLI.getShiftAmountTy()));
2055 WorkList.push_back(SH.Val);
2056 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
2061 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2062 N1.getOpcode() == ISD::XOR) {
2063 // Simplify X == (X+Z) --> Z == 0
2064 if (N1.getOperand(0) == N0) {
2065 return DAG.getSetCC(VT, N1.getOperand(1),
2066 DAG.getConstant(0, N1.getValueType()), Cond);
2067 } else if (N1.getOperand(1) == N0) {
2068 if (isCommutativeBinOp(N1.getOpcode())) {
2069 return DAG.getSetCC(VT, N1.getOperand(0),
2070 DAG.getConstant(0, N1.getValueType()), Cond);
2072 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2073 // X == (Z-X) --> X<<1 == Z
2074 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
2075 DAG.getConstant(1,TLI.getShiftAmountTy()));
2076 WorkList.push_back(SH.Val);
2077 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
2083 // Fold away ALL boolean setcc's.
2085 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2087 default: assert(0 && "Unknown integer setcc!");
2088 case ISD::SETEQ: // X == Y -> (X^Y)^1
2089 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2090 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
2091 WorkList.push_back(Temp.Val);
2093 case ISD::SETNE: // X != Y --> (X^Y)
2094 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2096 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
2097 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
2098 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2099 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
2100 WorkList.push_back(Temp.Val);
2102 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
2103 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
2104 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2105 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
2106 WorkList.push_back(Temp.Val);
2108 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
2109 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
2110 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2111 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
2112 WorkList.push_back(Temp.Val);
2114 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
2115 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
2116 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2117 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
2120 if (VT != MVT::i1) {
2121 WorkList.push_back(N0.Val);
2122 // FIXME: If running after legalize, we probably can't do this.
2123 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2128 // Could not fold it.
2132 // SelectionDAG::Combine - This is the entry point for the file.
2134 void SelectionDAG::Combine(bool RunningAfterLegalize) {
2135 /// run - This is the main entry point to this class.
2137 DAGCombiner(*this).Run(RunningAfterLegalize);