1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: Should add a corresponding version of fold AND with
20 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
23 // FIXME: select C, pow2, pow2 -> something smart
24 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
25 // FIXME: Dead stores -> nuke
26 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
27 // FIXME: mul (x, const) -> shifts + adds
28 // FIXME: undef values
29 // FIXME: make truncate see through SIGN_EXTEND and AND
30 // FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
31 // FIXME: verify that getNode can't return extends with an operand whose type
32 // is >= to that of the extend.
33 // FIXME: divide by zero is currently left unfolded. do we want to turn this
35 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
36 // FIXME: reassociate (X+C)+Y into (X+Y)+C if the inner expression has one use
38 //===----------------------------------------------------------------------===//
40 #define DEBUG_TYPE "dagcombine"
41 #include "llvm/ADT/Statistic.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Target/TargetLowering.h"
51 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
58 // Worklist of all of the nodes that need to be simplified.
59 std::vector<SDNode*> WorkList;
61 /// AddUsersToWorkList - When an instruction is simplified, add all users of
62 /// the instruction to the work lists because they might get more simplified
65 void AddUsersToWorkList(SDNode *N) {
66 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
68 WorkList.push_back(*UI);
71 /// removeFromWorkList - remove all instances of N from the worklist.
72 void removeFromWorkList(SDNode *N) {
73 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
77 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
79 DEBUG(std::cerr << "\nReplacing "; N->dump();
80 std::cerr << "\nWith: "; To[0].Val->dump();
81 std::cerr << " and " << To.size()-1 << " other values\n");
82 std::vector<SDNode*> NowDead;
83 DAG.ReplaceAllUsesWith(N, To, &NowDead);
85 // Push the new nodes and any users onto the worklist
86 for (unsigned i = 0, e = To.size(); i != e; ++i) {
87 WorkList.push_back(To[i].Val);
88 AddUsersToWorkList(To[i].Val);
91 // Nodes can end up on the worklist more than once. Make sure we do
92 // not process a node that has been replaced.
93 removeFromWorkList(N);
94 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
95 removeFromWorkList(NowDead[i]);
97 // Finally, since the node is now dead, remove it from the graph.
99 return SDOperand(N, 0);
102 SDOperand CombineTo(SDNode *N, SDOperand Res) {
103 std::vector<SDOperand> To;
105 return CombineTo(N, To);
108 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
109 std::vector<SDOperand> To;
112 return CombineTo(N, To);
115 /// visit - call the node-specific routine that knows how to fold each
116 /// particular type of node.
117 SDOperand visit(SDNode *N);
119 // Visitation implementation - Implement dag node combining for different
120 // node types. The semantics are as follows:
122 // SDOperand.Val == 0 - No change was made
123 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
124 // otherwise - N should be replaced by the returned Operand.
126 SDOperand visitTokenFactor(SDNode *N);
127 SDOperand visitADD(SDNode *N);
128 SDOperand visitSUB(SDNode *N);
129 SDOperand visitMUL(SDNode *N);
130 SDOperand visitSDIV(SDNode *N);
131 SDOperand visitUDIV(SDNode *N);
132 SDOperand visitSREM(SDNode *N);
133 SDOperand visitUREM(SDNode *N);
134 SDOperand visitMULHU(SDNode *N);
135 SDOperand visitMULHS(SDNode *N);
136 SDOperand visitAND(SDNode *N);
137 SDOperand visitOR(SDNode *N);
138 SDOperand visitXOR(SDNode *N);
139 SDOperand visitSHL(SDNode *N);
140 SDOperand visitSRA(SDNode *N);
141 SDOperand visitSRL(SDNode *N);
142 SDOperand visitCTLZ(SDNode *N);
143 SDOperand visitCTTZ(SDNode *N);
144 SDOperand visitCTPOP(SDNode *N);
145 SDOperand visitSELECT(SDNode *N);
146 SDOperand visitSELECT_CC(SDNode *N);
147 SDOperand visitSETCC(SDNode *N);
148 SDOperand visitADD_PARTS(SDNode *N);
149 SDOperand visitSUB_PARTS(SDNode *N);
150 SDOperand visitSIGN_EXTEND(SDNode *N);
151 SDOperand visitZERO_EXTEND(SDNode *N);
152 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
153 SDOperand visitTRUNCATE(SDNode *N);
154 SDOperand visitBIT_CONVERT(SDNode *N);
156 SDOperand visitFADD(SDNode *N);
157 SDOperand visitFSUB(SDNode *N);
158 SDOperand visitFMUL(SDNode *N);
159 SDOperand visitFDIV(SDNode *N);
160 SDOperand visitFREM(SDNode *N);
161 SDOperand visitSINT_TO_FP(SDNode *N);
162 SDOperand visitUINT_TO_FP(SDNode *N);
163 SDOperand visitFP_TO_SINT(SDNode *N);
164 SDOperand visitFP_TO_UINT(SDNode *N);
165 SDOperand visitFP_ROUND(SDNode *N);
166 SDOperand visitFP_ROUND_INREG(SDNode *N);
167 SDOperand visitFP_EXTEND(SDNode *N);
168 SDOperand visitFNEG(SDNode *N);
169 SDOperand visitFABS(SDNode *N);
170 SDOperand visitBRCOND(SDNode *N);
171 SDOperand visitBRCONDTWOWAY(SDNode *N);
172 SDOperand visitBR_CC(SDNode *N);
173 SDOperand visitBRTWOWAY_CC(SDNode *N);
175 SDOperand visitLOAD(SDNode *N);
176 SDOperand visitSTORE(SDNode *N);
178 SDOperand visitLOCATION(SDNode *N);
179 SDOperand visitDEBUGLOC(SDNode *N);
181 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
182 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
183 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
184 SDOperand N3, ISD::CondCode CC);
185 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
186 ISD::CondCode Cond, bool foldBooleans = true);
188 SDOperand BuildSDIV(SDNode *N);
189 SDOperand BuildUDIV(SDNode *N);
191 DAGCombiner(SelectionDAG &D)
192 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
194 /// Run - runs the dag combiner on all nodes in the work list
195 void Run(bool RunningAfterLegalize);
200 int64_t m; // magic number
201 int64_t s; // shift amount
205 uint64_t m; // magic number
206 int64_t a; // add indicator
207 int64_t s; // shift amount
210 /// magic - calculate the magic numbers required to codegen an integer sdiv as
211 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
213 static ms magic32(int32_t d) {
215 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
216 const uint32_t two31 = 0x80000000U;
220 t = two31 + ((uint32_t)d >> 31);
221 anc = t - 1 - t%ad; // absolute value of nc
222 p = 31; // initialize p
223 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
224 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
225 q2 = two31/ad; // initialize q2 = 2p/abs(d)
226 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
229 q1 = 2*q1; // update q1 = 2p/abs(nc)
230 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
231 if (r1 >= anc) { // must be unsigned comparison
235 q2 = 2*q2; // update q2 = 2p/abs(d)
236 r2 = 2*r2; // update r2 = rem(2p/abs(d))
237 if (r2 >= ad) { // must be unsigned comparison
242 } while (q1 < delta || (q1 == delta && r1 == 0));
244 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
245 if (d < 0) mag.m = -mag.m; // resulting magic number
246 mag.s = p - 32; // resulting shift
250 /// magicu - calculate the magic numbers required to codegen an integer udiv as
251 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
252 static mu magicu32(uint32_t d) {
254 uint32_t nc, delta, q1, r1, q2, r2;
256 magu.a = 0; // initialize "add" indicator
258 p = 31; // initialize p
259 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
260 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
261 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
262 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
265 if (r1 >= nc - r1 ) {
266 q1 = 2*q1 + 1; // update q1
267 r1 = 2*r1 - nc; // update r1
270 q1 = 2*q1; // update q1
271 r1 = 2*r1; // update r1
273 if (r2 + 1 >= d - r2) {
274 if (q2 >= 0x7FFFFFFF) magu.a = 1;
275 q2 = 2*q2 + 1; // update q2
276 r2 = 2*r2 + 1 - d; // update r2
279 if (q2 >= 0x80000000) magu.a = 1;
280 q2 = 2*q2; // update q2
281 r2 = 2*r2 + 1; // update r2
284 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
285 magu.m = q2 + 1; // resulting magic number
286 magu.s = p - 32; // resulting shift
290 /// magic - calculate the magic numbers required to codegen an integer sdiv as
291 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
293 static ms magic64(int64_t d) {
295 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
296 const uint64_t two63 = 9223372036854775808ULL; // 2^63
299 ad = d >= 0 ? d : -d;
300 t = two63 + ((uint64_t)d >> 63);
301 anc = t - 1 - t%ad; // absolute value of nc
302 p = 63; // initialize p
303 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
304 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
305 q2 = two63/ad; // initialize q2 = 2p/abs(d)
306 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
309 q1 = 2*q1; // update q1 = 2p/abs(nc)
310 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
311 if (r1 >= anc) { // must be unsigned comparison
315 q2 = 2*q2; // update q2 = 2p/abs(d)
316 r2 = 2*r2; // update r2 = rem(2p/abs(d))
317 if (r2 >= ad) { // must be unsigned comparison
322 } while (q1 < delta || (q1 == delta && r1 == 0));
325 if (d < 0) mag.m = -mag.m; // resulting magic number
326 mag.s = p - 64; // resulting shift
330 /// magicu - calculate the magic numbers required to codegen an integer udiv as
331 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
332 static mu magicu64(uint64_t d)
335 uint64_t nc, delta, q1, r1, q2, r2;
337 magu.a = 0; // initialize "add" indicator
339 p = 63; // initialize p
340 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
341 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
342 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
343 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
346 if (r1 >= nc - r1 ) {
347 q1 = 2*q1 + 1; // update q1
348 r1 = 2*r1 - nc; // update r1
351 q1 = 2*q1; // update q1
352 r1 = 2*r1; // update r1
354 if (r2 + 1 >= d - r2) {
355 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
356 q2 = 2*q2 + 1; // update q2
357 r2 = 2*r2 + 1 - d; // update r2
360 if (q2 >= 0x8000000000000000ull) magu.a = 1;
361 q2 = 2*q2; // update q2
362 r2 = 2*r2 + 1; // update r2
365 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
366 magu.m = q2 + 1; // resulting magic number
367 magu.s = p - 64; // resulting shift
371 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use
372 /// this predicate to simplify operations downstream. Op and Mask are known to
373 /// be the same type.
374 static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
375 const TargetLowering &TLI) {
377 if (Mask == 0) return true;
379 // If we know the result of a setcc has the top bits zero, use this info.
380 switch (Op.getOpcode()) {
382 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
384 return ((Mask & 1) == 0) &&
385 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
387 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
388 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
389 case ISD::ZERO_EXTEND:
390 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
391 return MaskedValueIsZero(Op.getOperand(0),Mask & (~0ULL >> (64-SrcBits)),TLI);
392 case ISD::AssertZext:
393 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
394 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
396 // If either of the operands has zero bits, the result will too.
397 if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) ||
398 MaskedValueIsZero(Op.getOperand(0), Mask, TLI))
400 // (X & C1) & C2 == 0 iff C1 & C2 == 0.
401 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
402 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
406 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
407 MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
409 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
410 MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
412 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
413 MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
415 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
416 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
417 uint64_t NewVal = Mask << ShAmt->getValue();
418 SrcBits = MVT::getSizeInBits(Op.getValueType());
419 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
420 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
424 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
425 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
426 uint64_t NewVal = Mask >> ShAmt->getValue();
427 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
431 // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits.
432 if ((Mask&(Mask+1)) == 0) { // All low bits
433 if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
434 MaskedValueIsZero(Op.getOperand(1), Mask, TLI))
439 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
440 // We know that the top bits of C-X are clear if X contains less bits
441 // than C (i.e. no wrap-around can happen). For example, 20-X is
442 // positive if we can prove that X is >= 0 and < 16.
443 unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0));
444 if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear
445 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
446 uint64_t MaskV = (1ULL << (63-NLZ))-1;
447 if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) {
448 // High bits are clear this value is known to be >= C.
449 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
450 if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0)
459 // Bit counting instructions can not set the high bits of the result
460 // register. The max number of bits sets depends on the input.
461 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
463 if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
464 return TLI.isMaskedValueZeroForTargetNode(Op, Mask);
470 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
471 // that selects between the values 1 and 0, making it equivalent to a setcc.
472 // Also, set the incoming LHS, RHS, and CC references to the appropriate
473 // nodes based on the type of node we are checking. This simplifies life a
474 // bit for the callers.
475 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
477 if (N.getOpcode() == ISD::SETCC) {
478 LHS = N.getOperand(0);
479 RHS = N.getOperand(1);
480 CC = N.getOperand(2);
483 if (N.getOpcode() == ISD::SELECT_CC &&
484 N.getOperand(2).getOpcode() == ISD::Constant &&
485 N.getOperand(3).getOpcode() == ISD::Constant &&
486 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
487 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
488 LHS = N.getOperand(0);
489 RHS = N.getOperand(1);
490 CC = N.getOperand(4);
496 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
497 // one use. If this is true, it allows the users to invert the operation for
498 // free when it is profitable to do so.
499 static bool isOneUseSetCC(SDOperand N) {
500 SDOperand N0, N1, N2;
501 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
506 // FIXME: This should probably go in the ISD class rather than being duplicated
508 static bool isCommutativeBinOp(unsigned Opcode) {
514 case ISD::XOR: return true;
515 default: return false; // FIXME: Need commutative info for user ops!
519 void DAGCombiner::Run(bool RunningAfterLegalize) {
520 // set the instance variable, so that the various visit routines may use it.
521 AfterLegalize = RunningAfterLegalize;
523 // Add all the dag nodes to the worklist.
524 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
525 E = DAG.allnodes_end(); I != E; ++I)
526 WorkList.push_back(I);
528 // Create a dummy node (which is not added to allnodes), that adds a reference
529 // to the root node, preventing it from being deleted, and tracking any
530 // changes of the root.
531 HandleSDNode Dummy(DAG.getRoot());
533 // while the worklist isn't empty, inspect the node on the end of it and
534 // try and combine it.
535 while (!WorkList.empty()) {
536 SDNode *N = WorkList.back();
539 // If N has no uses, it is dead. Make sure to revisit all N's operands once
540 // N is deleted from the DAG, since they too may now be dead or may have a
541 // reduced number of uses, allowing other xforms.
542 if (N->use_empty() && N != &Dummy) {
543 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
544 WorkList.push_back(N->getOperand(i).Val);
546 removeFromWorkList(N);
551 SDOperand RV = visit(N);
554 // If we get back the same node we passed in, rather than a new node or
555 // zero, we know that the node must have defined multiple values and
556 // CombineTo was used. Since CombineTo takes care of the worklist
557 // mechanics for us, we have no work to do in this case.
559 DEBUG(std::cerr << "\nReplacing "; N->dump();
560 std::cerr << "\nWith: "; RV.Val->dump();
562 std::vector<SDNode*> NowDead;
563 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
565 // Push the new node and any users onto the worklist
566 WorkList.push_back(RV.Val);
567 AddUsersToWorkList(RV.Val);
569 // Nodes can end up on the worklist more than once. Make sure we do
570 // not process a node that has been replaced.
571 removeFromWorkList(N);
572 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
573 removeFromWorkList(NowDead[i]);
575 // Finally, since the node is now dead, remove it from the graph.
581 // If the root changed (e.g. it was a dead load, update the root).
582 DAG.setRoot(Dummy.getValue());
585 SDOperand DAGCombiner::visit(SDNode *N) {
586 switch(N->getOpcode()) {
588 case ISD::TokenFactor: return visitTokenFactor(N);
589 case ISD::ADD: return visitADD(N);
590 case ISD::SUB: return visitSUB(N);
591 case ISD::MUL: return visitMUL(N);
592 case ISD::SDIV: return visitSDIV(N);
593 case ISD::UDIV: return visitUDIV(N);
594 case ISD::SREM: return visitSREM(N);
595 case ISD::UREM: return visitUREM(N);
596 case ISD::MULHU: return visitMULHU(N);
597 case ISD::MULHS: return visitMULHS(N);
598 case ISD::AND: return visitAND(N);
599 case ISD::OR: return visitOR(N);
600 case ISD::XOR: return visitXOR(N);
601 case ISD::SHL: return visitSHL(N);
602 case ISD::SRA: return visitSRA(N);
603 case ISD::SRL: return visitSRL(N);
604 case ISD::CTLZ: return visitCTLZ(N);
605 case ISD::CTTZ: return visitCTTZ(N);
606 case ISD::CTPOP: return visitCTPOP(N);
607 case ISD::SELECT: return visitSELECT(N);
608 case ISD::SELECT_CC: return visitSELECT_CC(N);
609 case ISD::SETCC: return visitSETCC(N);
610 case ISD::ADD_PARTS: return visitADD_PARTS(N);
611 case ISD::SUB_PARTS: return visitSUB_PARTS(N);
612 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
613 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
614 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
615 case ISD::TRUNCATE: return visitTRUNCATE(N);
616 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
617 case ISD::FADD: return visitFADD(N);
618 case ISD::FSUB: return visitFSUB(N);
619 case ISD::FMUL: return visitFMUL(N);
620 case ISD::FDIV: return visitFDIV(N);
621 case ISD::FREM: return visitFREM(N);
622 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
623 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
624 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
625 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
626 case ISD::FP_ROUND: return visitFP_ROUND(N);
627 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
628 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
629 case ISD::FNEG: return visitFNEG(N);
630 case ISD::FABS: return visitFABS(N);
631 case ISD::BRCOND: return visitBRCOND(N);
632 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
633 case ISD::BR_CC: return visitBR_CC(N);
634 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
635 case ISD::LOAD: return visitLOAD(N);
636 case ISD::STORE: return visitSTORE(N);
637 case ISD::LOCATION: return visitLOCATION(N);
638 case ISD::DEBUG_LOC: return visitDEBUGLOC(N);
643 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
644 std::vector<SDOperand> Ops;
645 bool Changed = false;
647 // If the token factor has two operands and one is the entry token, replace
648 // the token factor with the other operand.
649 if (N->getNumOperands() == 2) {
650 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
651 return N->getOperand(1);
652 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
653 return N->getOperand(0);
656 // fold (tokenfactor (tokenfactor)) -> tokenfactor
657 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
658 SDOperand Op = N->getOperand(i);
659 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
661 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
662 Ops.push_back(Op.getOperand(j));
668 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
672 SDOperand DAGCombiner::visitADD(SDNode *N) {
673 SDOperand N0 = N->getOperand(0);
674 SDOperand N1 = N->getOperand(1);
675 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
676 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
677 MVT::ValueType VT = N0.getValueType();
679 // fold (add c1, c2) -> c1+c2
681 return DAG.getNode(ISD::ADD, VT, N0, N1);
682 // canonicalize constant to RHS
684 return DAG.getNode(ISD::ADD, VT, N1, N0);
685 // fold (add x, 0) -> x
686 if (N1C && N1C->isNullValue())
688 // fold (add (add x, c1), c2) -> (add x, c1+c2)
689 if (N1C && N0.getOpcode() == ISD::ADD) {
690 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
691 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
693 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1),
694 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT));
696 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0),
697 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT));
700 // fold ((c1-A)+c2) -> (c1+c2)-A
701 if (N1C && N0.getOpcode() == ISD::SUB)
702 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
703 return DAG.getNode(ISD::SUB, VT,
704 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
707 // fold ((0-A) + B) -> B-A
708 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
709 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
710 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
711 // fold (A + (0-B)) -> A-B
712 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
713 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
714 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
715 // fold (A+(B-A)) -> B
716 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
717 return N1.getOperand(0);
721 SDOperand DAGCombiner::visitSUB(SDNode *N) {
722 SDOperand N0 = N->getOperand(0);
723 SDOperand N1 = N->getOperand(1);
724 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
725 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
726 MVT::ValueType VT = N0.getValueType();
728 // fold (sub x, x) -> 0
730 return DAG.getConstant(0, N->getValueType(0));
731 // fold (sub c1, c2) -> c1-c2
733 return DAG.getNode(ISD::SUB, VT, N0, N1);
734 // fold (sub x, c) -> (add x, -c)
736 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
738 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
739 return N0.getOperand(1);
741 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
742 return N0.getOperand(0);
746 SDOperand DAGCombiner::visitMUL(SDNode *N) {
747 SDOperand N0 = N->getOperand(0);
748 SDOperand N1 = N->getOperand(1);
749 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
750 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
751 MVT::ValueType VT = N0.getValueType();
753 // fold (mul c1, c2) -> c1*c2
755 return DAG.getNode(ISD::MUL, VT, N0, N1);
756 // canonicalize constant to RHS
758 return DAG.getNode(ISD::MUL, VT, N1, N0);
759 // fold (mul x, 0) -> 0
760 if (N1C && N1C->isNullValue())
762 // fold (mul x, -1) -> 0-x
763 if (N1C && N1C->isAllOnesValue())
764 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
765 // fold (mul x, (1 << c)) -> x << c
766 if (N1C && isPowerOf2_64(N1C->getValue()))
767 return DAG.getNode(ISD::SHL, VT, N0,
768 DAG.getConstant(Log2_64(N1C->getValue()),
769 TLI.getShiftAmountTy()));
770 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
771 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
772 // FIXME: If the input is something that is easily negated (e.g. a
773 // single-use add), we should put the negate there.
774 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
775 DAG.getNode(ISD::SHL, VT, N0,
776 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
777 TLI.getShiftAmountTy())));
781 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2)
782 if (N1C && N0.getOpcode() == ISD::MUL) {
783 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
784 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
786 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1),
787 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT));
789 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0),
790 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT));
795 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
796 SDOperand N0 = N->getOperand(0);
797 SDOperand N1 = N->getOperand(1);
798 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
799 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
800 MVT::ValueType VT = N->getValueType(0);
802 // fold (sdiv c1, c2) -> c1/c2
803 if (N0C && N1C && !N1C->isNullValue())
804 return DAG.getNode(ISD::SDIV, VT, N0, N1);
805 // fold (sdiv X, 1) -> X
806 if (N1C && N1C->getSignExtended() == 1LL)
808 // fold (sdiv X, -1) -> 0-X
809 if (N1C && N1C->isAllOnesValue())
810 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
811 // If we know the sign bits of both operands are zero, strength reduce to a
812 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
813 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
814 if (MaskedValueIsZero(N1, SignBit, TLI) &&
815 MaskedValueIsZero(N0, SignBit, TLI))
816 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
817 // fold (sdiv X, pow2) -> (add (sra X, log(pow2)), (srl X, sizeof(X)-1))
818 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
819 (isPowerOf2_64(N1C->getSignExtended()) ||
820 isPowerOf2_64(-N1C->getSignExtended()))) {
821 // If dividing by powers of two is cheap, then don't perform the following
823 if (TLI.isPow2DivCheap())
825 int64_t pow2 = N1C->getSignExtended();
826 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
827 SDOperand SRL = DAG.getNode(ISD::SRL, VT, N0,
828 DAG.getConstant(MVT::getSizeInBits(VT)-1,
829 TLI.getShiftAmountTy()));
830 WorkList.push_back(SRL.Val);
831 SDOperand SGN = DAG.getNode(ISD::ADD, VT, N0, SRL);
832 WorkList.push_back(SGN.Val);
833 SDOperand SRA = DAG.getNode(ISD::SRA, VT, SGN,
834 DAG.getConstant(Log2_64(abs2),
835 TLI.getShiftAmountTy()));
836 // If we're dividing by a positive value, we're done. Otherwise, we must
837 // negate the result.
840 WorkList.push_back(SRA.Val);
841 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
843 // if integer divide is expensive and we satisfy the requirements, emit an
844 // alternate sequence.
845 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
846 !TLI.isIntDivCheap()) {
847 SDOperand Op = BuildSDIV(N);
848 if (Op.Val) return Op;
853 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
854 SDOperand N0 = N->getOperand(0);
855 SDOperand N1 = N->getOperand(1);
856 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
857 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
858 MVT::ValueType VT = N->getValueType(0);
860 // fold (udiv c1, c2) -> c1/c2
861 if (N0C && N1C && !N1C->isNullValue())
862 return DAG.getNode(ISD::UDIV, VT, N0, N1);
863 // fold (udiv x, (1 << c)) -> x >>u c
864 if (N1C && isPowerOf2_64(N1C->getValue()))
865 return DAG.getNode(ISD::SRL, N->getValueType(0), N0,
866 DAG.getConstant(Log2_64(N1C->getValue()),
867 TLI.getShiftAmountTy()));
868 // fold (udiv x, c) -> alternate
869 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
870 SDOperand Op = BuildUDIV(N);
871 if (Op.Val) return Op;
877 SDOperand DAGCombiner::visitSREM(SDNode *N) {
878 SDOperand N0 = N->getOperand(0);
879 SDOperand N1 = N->getOperand(1);
880 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
881 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
882 MVT::ValueType VT = N->getValueType(0);
884 // fold (srem c1, c2) -> c1%c2
885 if (N0C && N1C && !N1C->isNullValue())
886 return DAG.getNode(ISD::SREM, VT, N0, N1);
887 // If we know the sign bits of both operands are zero, strength reduce to a
888 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
889 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
890 if (MaskedValueIsZero(N1, SignBit, TLI) &&
891 MaskedValueIsZero(N0, SignBit, TLI))
892 return DAG.getNode(ISD::UREM, VT, N0, N1);
896 SDOperand DAGCombiner::visitUREM(SDNode *N) {
897 SDOperand N0 = N->getOperand(0);
898 SDOperand N1 = N->getOperand(1);
899 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
900 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
901 MVT::ValueType VT = N->getValueType(0);
903 // fold (urem c1, c2) -> c1%c2
904 if (N0C && N1C && !N1C->isNullValue())
905 return DAG.getNode(ISD::UREM, VT, N0, N1);
906 // fold (urem x, pow2) -> (and x, pow2-1)
907 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
908 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
912 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
913 SDOperand N0 = N->getOperand(0);
914 SDOperand N1 = N->getOperand(1);
915 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
917 // fold (mulhs x, 0) -> 0
918 if (N1C && N1C->isNullValue())
920 // fold (mulhs x, 1) -> (sra x, size(x)-1)
921 if (N1C && N1C->getValue() == 1)
922 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
923 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
924 TLI.getShiftAmountTy()));
928 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
929 SDOperand N0 = N->getOperand(0);
930 SDOperand N1 = N->getOperand(1);
931 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
933 // fold (mulhu x, 0) -> 0
934 if (N1C && N1C->isNullValue())
936 // fold (mulhu x, 1) -> 0
937 if (N1C && N1C->getValue() == 1)
938 return DAG.getConstant(0, N0.getValueType());
942 SDOperand DAGCombiner::visitAND(SDNode *N) {
943 SDOperand N0 = N->getOperand(0);
944 SDOperand N1 = N->getOperand(1);
945 SDOperand LL, LR, RL, RR, CC0, CC1;
946 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
947 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
948 MVT::ValueType VT = N1.getValueType();
949 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
951 // fold (and c1, c2) -> c1&c2
953 return DAG.getNode(ISD::AND, VT, N0, N1);
954 // canonicalize constant to RHS
956 return DAG.getNode(ISD::AND, VT, N1, N0);
957 // fold (and x, -1) -> x
958 if (N1C && N1C->isAllOnesValue())
960 // if (and x, c) is known to be zero, return 0
961 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
962 return DAG.getConstant(0, VT);
963 // fold (and x, c) -> x iff (x & ~c) == 0
964 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
967 // fold (and (and x, c1), c2) -> (and x, c1^c2)
968 if (N1C && N0.getOpcode() == ISD::AND) {
969 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
970 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
972 return DAG.getNode(ISD::AND, VT, N0.getOperand(1),
973 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT));
975 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
976 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT));
978 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
979 if (N1C && N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
980 unsigned ExtendBits =
981 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
982 if (ExtendBits == 64 || ((N1C->getValue() & (~0ULL << ExtendBits)) == 0))
983 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
985 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
986 if (N1C && N0.getOpcode() == ISD::OR)
987 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
988 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
990 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
991 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
992 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
993 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
995 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
996 MVT::isInteger(LL.getValueType())) {
997 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
998 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
999 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1000 WorkList.push_back(ORNode.Val);
1001 return DAG.getSetCC(VT, ORNode, LR, Op1);
1003 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1004 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1005 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1006 WorkList.push_back(ANDNode.Val);
1007 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1009 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1010 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1011 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1012 WorkList.push_back(ORNode.Val);
1013 return DAG.getSetCC(VT, ORNode, LR, Op1);
1016 // canonicalize equivalent to ll == rl
1017 if (LL == RR && LR == RL) {
1018 Op1 = ISD::getSetCCSwappedOperands(Op1);
1021 if (LL == RL && LR == RR) {
1022 bool isInteger = MVT::isInteger(LL.getValueType());
1023 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1024 if (Result != ISD::SETCC_INVALID)
1025 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1028 // fold (and (zext x), (zext y)) -> (zext (and x, y))
1029 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1030 N1.getOpcode() == ISD::ZERO_EXTEND &&
1031 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1032 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
1033 N0.getOperand(0), N1.getOperand(0));
1034 WorkList.push_back(ANDNode.Val);
1035 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
1037 // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y))
1038 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1039 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) &&
1040 N0.getOperand(1) == N1.getOperand(1)) {
1041 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
1042 N0.getOperand(0), N1.getOperand(0));
1043 WorkList.push_back(ANDNode.Val);
1044 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
1046 // fold (and (sra)) -> (and (srl)) when possible.
1047 if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse()) {
1048 if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1049 // If the RHS of the AND has zeros where the sign bits of the SRA will
1050 // land, turn the SRA into an SRL.
1051 if (MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) &
1052 (~0ULL>>(64-OpSizeInBits)), TLI)) {
1053 WorkList.push_back(N);
1054 CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1060 // fold (zext_inreg (extload x)) -> (zextload x)
1061 if (N0.getOpcode() == ISD::EXTLOAD) {
1062 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1063 // If we zero all the possible extended bits, then we can turn this into
1064 // a zextload if we are running before legalize or the operation is legal.
1065 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) &&
1066 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1067 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1068 N0.getOperand(1), N0.getOperand(2),
1070 WorkList.push_back(N);
1071 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1075 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1076 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) {
1077 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1078 // If we zero all the possible extended bits, then we can turn this into
1079 // a zextload if we are running before legalize or the operation is legal.
1080 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) &&
1081 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1082 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1083 N0.getOperand(1), N0.getOperand(2),
1085 WorkList.push_back(N);
1086 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1093 SDOperand DAGCombiner::visitOR(SDNode *N) {
1094 SDOperand N0 = N->getOperand(0);
1095 SDOperand N1 = N->getOperand(1);
1096 SDOperand LL, LR, RL, RR, CC0, CC1;
1097 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1098 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1099 MVT::ValueType VT = N1.getValueType();
1100 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1102 // fold (or c1, c2) -> c1|c2
1104 return DAG.getNode(ISD::OR, VT, N0, N1);
1105 // canonicalize constant to RHS
1107 return DAG.getNode(ISD::OR, VT, N1, N0);
1108 // fold (or x, 0) -> x
1109 if (N1C && N1C->isNullValue())
1111 // fold (or x, -1) -> -1
1112 if (N1C && N1C->isAllOnesValue())
1114 // fold (or x, c) -> c iff (x & ~c) == 0
1115 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
1118 // fold (or (or x, c1), c2) -> (or x, c1|c2)
1119 if (N1C && N0.getOpcode() == ISD::OR) {
1120 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1121 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1123 return DAG.getNode(ISD::OR, VT, N0.getOperand(1),
1124 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT));
1126 return DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1127 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT));
1128 } else if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1129 isa<ConstantSDNode>(N0.getOperand(1))) {
1130 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1131 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1132 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1134 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1136 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1137 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1138 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1139 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1141 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1142 MVT::isInteger(LL.getValueType())) {
1143 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1144 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1145 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1146 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1147 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1148 WorkList.push_back(ORNode.Val);
1149 return DAG.getSetCC(VT, ORNode, LR, Op1);
1151 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1152 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1153 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1154 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1155 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1156 WorkList.push_back(ANDNode.Val);
1157 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1160 // canonicalize equivalent to ll == rl
1161 if (LL == RR && LR == RL) {
1162 Op1 = ISD::getSetCCSwappedOperands(Op1);
1165 if (LL == RL && LR == RR) {
1166 bool isInteger = MVT::isInteger(LL.getValueType());
1167 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1168 if (Result != ISD::SETCC_INVALID)
1169 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1172 // fold (or (zext x), (zext y)) -> (zext (or x, y))
1173 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1174 N1.getOpcode() == ISD::ZERO_EXTEND &&
1175 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1176 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
1177 N0.getOperand(0), N1.getOperand(0));
1178 WorkList.push_back(ORNode.Val);
1179 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
1181 // canonicalize shl to left side in a shl/srl pair, to match rotate
1182 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
1184 // check for rotl, rotr
1185 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
1186 N0.getOperand(0) == N1.getOperand(0) &&
1187 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) {
1188 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1189 if (N0.getOperand(1).getOpcode() == ISD::Constant &&
1190 N1.getOperand(1).getOpcode() == ISD::Constant) {
1191 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1192 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1193 if ((c1val + c2val) == OpSizeInBits)
1194 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1196 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1197 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
1198 N0.getOperand(1) == N1.getOperand(1).getOperand(1))
1199 if (ConstantSDNode *SUBC =
1200 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0)))
1201 if (SUBC->getValue() == OpSizeInBits)
1202 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1203 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1204 if (N0.getOperand(1).getOpcode() == ISD::SUB &&
1205 N1.getOperand(1) == N0.getOperand(1).getOperand(1))
1206 if (ConstantSDNode *SUBC =
1207 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
1208 if (SUBC->getValue() == OpSizeInBits) {
1209 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT))
1210 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
1213 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
1220 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1221 SDOperand N0 = N->getOperand(0);
1222 SDOperand N1 = N->getOperand(1);
1223 SDOperand LHS, RHS, CC;
1224 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1225 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1226 MVT::ValueType VT = N0.getValueType();
1228 // fold (xor c1, c2) -> c1^c2
1230 return DAG.getNode(ISD::XOR, VT, N0, N1);
1231 // canonicalize constant to RHS
1233 return DAG.getNode(ISD::XOR, VT, N1, N0);
1234 // fold (xor x, 0) -> x
1235 if (N1C && N1C->isNullValue())
1237 // fold !(x cc y) -> (x !cc y)
1238 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1239 bool isInt = MVT::isInteger(LHS.getValueType());
1240 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1242 if (N0.getOpcode() == ISD::SETCC)
1243 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1244 if (N0.getOpcode() == ISD::SELECT_CC)
1245 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1246 assert(0 && "Unhandled SetCC Equivalent!");
1249 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1250 if (N1C && N1C->getValue() == 1 &&
1251 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1252 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1253 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1254 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1255 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1256 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1257 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
1258 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1261 // fold !(x or y) -> (!x and !y) iff x or y are constants
1262 if (N1C && N1C->isAllOnesValue() &&
1263 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1264 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1265 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1266 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1267 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1268 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1269 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
1270 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1273 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1274 if (N1C && N0.getOpcode() == ISD::XOR) {
1275 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1276 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1278 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1279 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1281 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1282 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1284 // fold (xor x, x) -> 0
1286 return DAG.getConstant(0, VT);
1287 // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
1288 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1289 N1.getOpcode() == ISD::ZERO_EXTEND &&
1290 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1291 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1292 N0.getOperand(0), N1.getOperand(0));
1293 WorkList.push_back(XORNode.Val);
1294 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
1299 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1300 SDOperand N0 = N->getOperand(0);
1301 SDOperand N1 = N->getOperand(1);
1302 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1303 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1304 MVT::ValueType VT = N0.getValueType();
1305 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1307 // fold (shl c1, c2) -> c1<<c2
1309 return DAG.getNode(ISD::SHL, VT, N0, N1);
1310 // fold (shl 0, x) -> 0
1311 if (N0C && N0C->isNullValue())
1313 // fold (shl x, c >= size(x)) -> undef
1314 if (N1C && N1C->getValue() >= OpSizeInBits)
1315 return DAG.getNode(ISD::UNDEF, VT);
1316 // fold (shl x, 0) -> x
1317 if (N1C && N1C->isNullValue())
1319 // if (shl x, c) is known to be zero, return 0
1320 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
1321 return DAG.getConstant(0, VT);
1322 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1323 if (N1C && N0.getOpcode() == ISD::SHL &&
1324 N0.getOperand(1).getOpcode() == ISD::Constant) {
1325 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1326 uint64_t c2 = N1C->getValue();
1327 if (c1 + c2 > OpSizeInBits)
1328 return DAG.getConstant(0, VT);
1329 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1330 DAG.getConstant(c1 + c2, N1.getValueType()));
1332 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1333 // (srl (and x, -1 << c1), c1-c2)
1334 if (N1C && N0.getOpcode() == ISD::SRL &&
1335 N0.getOperand(1).getOpcode() == ISD::Constant) {
1336 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1337 uint64_t c2 = N1C->getValue();
1338 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1339 DAG.getConstant(~0ULL << c1, VT));
1341 return DAG.getNode(ISD::SHL, VT, Mask,
1342 DAG.getConstant(c2-c1, N1.getValueType()));
1344 return DAG.getNode(ISD::SRL, VT, Mask,
1345 DAG.getConstant(c1-c2, N1.getValueType()));
1347 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1348 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1349 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1350 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1354 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1355 SDOperand N0 = N->getOperand(0);
1356 SDOperand N1 = N->getOperand(1);
1357 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1358 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1359 MVT::ValueType VT = N0.getValueType();
1360 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1362 // fold (sra c1, c2) -> c1>>c2
1364 return DAG.getNode(ISD::SRA, VT, N0, N1);
1365 // fold (sra 0, x) -> 0
1366 if (N0C && N0C->isNullValue())
1368 // fold (sra -1, x) -> -1
1369 if (N0C && N0C->isAllOnesValue())
1371 // fold (sra x, c >= size(x)) -> undef
1372 if (N1C && N1C->getValue() >= OpSizeInBits)
1373 return DAG.getNode(ISD::UNDEF, VT);
1374 // fold (sra x, 0) -> x
1375 if (N1C && N1C->isNullValue())
1377 // If the sign bit is known to be zero, switch this to a SRL.
1378 if (MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI))
1379 return DAG.getNode(ISD::SRL, VT, N0, N1);
1383 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1384 SDOperand N0 = N->getOperand(0);
1385 SDOperand N1 = N->getOperand(1);
1386 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1387 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1388 MVT::ValueType VT = N0.getValueType();
1389 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1391 // fold (srl c1, c2) -> c1 >>u c2
1393 return DAG.getNode(ISD::SRL, VT, N0, N1);
1394 // fold (srl 0, x) -> 0
1395 if (N0C && N0C->isNullValue())
1397 // fold (srl x, c >= size(x)) -> undef
1398 if (N1C && N1C->getValue() >= OpSizeInBits)
1399 return DAG.getNode(ISD::UNDEF, VT);
1400 // fold (srl x, 0) -> x
1401 if (N1C && N1C->isNullValue())
1403 // if (srl x, c) is known to be zero, return 0
1404 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
1405 return DAG.getConstant(0, VT);
1406 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1407 if (N1C && N0.getOpcode() == ISD::SRL &&
1408 N0.getOperand(1).getOpcode() == ISD::Constant) {
1409 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1410 uint64_t c2 = N1C->getValue();
1411 if (c1 + c2 > OpSizeInBits)
1412 return DAG.getConstant(0, VT);
1413 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1414 DAG.getConstant(c1 + c2, N1.getValueType()));
1419 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1420 SDOperand N0 = N->getOperand(0);
1421 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1422 MVT::ValueType VT = N->getValueType(0);
1424 // fold (ctlz c1) -> c2
1426 return DAG.getNode(ISD::CTLZ, VT, N0);
1430 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1431 SDOperand N0 = N->getOperand(0);
1432 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1433 MVT::ValueType VT = N->getValueType(0);
1435 // fold (cttz c1) -> c2
1437 return DAG.getNode(ISD::CTTZ, VT, N0);
1441 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1442 SDOperand N0 = N->getOperand(0);
1443 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1444 MVT::ValueType VT = N->getValueType(0);
1446 // fold (ctpop c1) -> c2
1448 return DAG.getNode(ISD::CTPOP, VT, N0);
1452 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1453 SDOperand N0 = N->getOperand(0);
1454 SDOperand N1 = N->getOperand(1);
1455 SDOperand N2 = N->getOperand(2);
1456 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1457 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1458 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1459 MVT::ValueType VT = N->getValueType(0);
1461 // fold select C, X, X -> X
1464 // fold select true, X, Y -> X
1465 if (N0C && !N0C->isNullValue())
1467 // fold select false, X, Y -> Y
1468 if (N0C && N0C->isNullValue())
1470 // fold select C, 1, X -> C | X
1471 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1472 return DAG.getNode(ISD::OR, VT, N0, N2);
1473 // fold select C, 0, X -> ~C & X
1474 // FIXME: this should check for C type == X type, not i1?
1475 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1476 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1477 WorkList.push_back(XORNode.Val);
1478 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1480 // fold select C, X, 1 -> ~C | X
1481 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1482 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1483 WorkList.push_back(XORNode.Val);
1484 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1486 // fold select C, X, 0 -> C & X
1487 // FIXME: this should check for C type == X type, not i1?
1488 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1489 return DAG.getNode(ISD::AND, VT, N0, N1);
1490 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1491 if (MVT::i1 == VT && N0 == N1)
1492 return DAG.getNode(ISD::OR, VT, N0, N2);
1493 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1494 if (MVT::i1 == VT && N0 == N2)
1495 return DAG.getNode(ISD::AND, VT, N0, N1);
1497 // If we can fold this based on the true/false value, do so.
1498 if (SimplifySelectOps(N, N1, N2))
1501 // fold selects based on a setcc into other things, such as min/max/abs
1502 if (N0.getOpcode() == ISD::SETCC)
1503 return SimplifySelect(N0, N1, N2);
1507 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1508 SDOperand N0 = N->getOperand(0);
1509 SDOperand N1 = N->getOperand(1);
1510 SDOperand N2 = N->getOperand(2);
1511 SDOperand N3 = N->getOperand(3);
1512 SDOperand N4 = N->getOperand(4);
1513 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1514 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1515 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1516 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1518 // Determine if the condition we're dealing with is constant
1519 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1520 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1522 // fold select_cc lhs, rhs, x, x, cc -> x
1526 // If we can fold this based on the true/false value, do so.
1527 if (SimplifySelectOps(N, N2, N3))
1530 // fold select_cc into other things, such as min/max/abs
1531 return SimplifySelectCC(N0, N1, N2, N3, CC);
1534 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1535 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1536 cast<CondCodeSDNode>(N->getOperand(2))->get());
1539 SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) {
1540 SDOperand LHSLo = N->getOperand(0);
1541 SDOperand RHSLo = N->getOperand(2);
1542 MVT::ValueType VT = LHSLo.getValueType();
1544 // fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo)
1545 if (MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1546 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
1548 WorkList.push_back(Hi.Val);
1549 CombineTo(N, RHSLo, Hi);
1552 // fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo)
1553 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1554 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
1556 WorkList.push_back(Hi.Val);
1557 CombineTo(N, LHSLo, Hi);
1563 SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) {
1564 SDOperand LHSLo = N->getOperand(0);
1565 SDOperand RHSLo = N->getOperand(2);
1566 MVT::ValueType VT = LHSLo.getValueType();
1568 // fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo)
1569 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1570 SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1),
1572 WorkList.push_back(Hi.Val);
1573 CombineTo(N, LHSLo, Hi);
1579 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1580 SDOperand N0 = N->getOperand(0);
1581 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1582 MVT::ValueType VT = N->getValueType(0);
1584 // fold (sext c1) -> c1
1586 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1587 // fold (sext (sext x)) -> (sext x)
1588 if (N0.getOpcode() == ISD::SIGN_EXTEND)
1589 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1590 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
1591 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1593 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())))
1594 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1595 DAG.getValueType(N0.getValueType()));
1596 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1597 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1598 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){
1599 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1600 N0.getOperand(1), N0.getOperand(2),
1602 CombineTo(N, ExtLoad);
1603 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1604 ExtLoad.getValue(1));
1608 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1609 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1610 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1612 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0),
1613 N0.getOperand(1), N0.getOperand(2),
1615 CombineTo(N, ExtLoad);
1616 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1617 ExtLoad.getValue(1));
1624 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1625 SDOperand N0 = N->getOperand(0);
1626 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1627 MVT::ValueType VT = N->getValueType(0);
1629 // fold (zext c1) -> c1
1631 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1632 // fold (zext (zext x)) -> (zext x)
1633 if (N0.getOpcode() == ISD::ZERO_EXTEND)
1634 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1635 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size.
1636 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1637 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType())))
1638 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType());
1639 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1640 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1641 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){
1642 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1643 N0.getOperand(1), N0.getOperand(2),
1645 CombineTo(N, ExtLoad);
1646 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1647 ExtLoad.getValue(1));
1651 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1652 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1653 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1655 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1656 N0.getOperand(1), N0.getOperand(2),
1658 CombineTo(N, ExtLoad);
1659 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1660 ExtLoad.getValue(1));
1666 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1667 SDOperand N0 = N->getOperand(0);
1668 SDOperand N1 = N->getOperand(1);
1669 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1670 MVT::ValueType VT = N->getValueType(0);
1671 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1672 unsigned EVTBits = MVT::getSizeInBits(EVT);
1674 // fold (sext_in_reg c1) -> c1
1676 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1677 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1679 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1680 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1681 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1684 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1685 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1686 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1687 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1689 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1690 if (N0.getOpcode() == ISD::AssertSext &&
1691 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1694 // fold (sext_in_reg (sextload x)) -> (sextload x)
1695 if (N0.getOpcode() == ISD::SEXTLOAD &&
1696 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1699 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1700 if (N0.getOpcode() == ISD::SETCC &&
1701 TLI.getSetCCResultContents() ==
1702 TargetLowering::ZeroOrNegativeOneSetCCResult)
1704 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1705 if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI))
1706 return DAG.getNode(ISD::AND, N0.getValueType(), N0,
1707 DAG.getConstant(~0ULL >> (64-EVTBits), VT));
1708 // fold (sext_in_reg (srl x)) -> sra x
1709 if (N0.getOpcode() == ISD::SRL &&
1710 N0.getOperand(1).getOpcode() == ISD::Constant &&
1711 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
1712 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
1715 // fold (sext_inreg (extload x)) -> (sextload x)
1716 if (N0.getOpcode() == ISD::EXTLOAD &&
1717 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1718 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1719 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1720 N0.getOperand(1), N0.getOperand(2),
1722 CombineTo(N, ExtLoad);
1723 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1726 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1727 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
1728 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1729 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1730 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1731 N0.getOperand(1), N0.getOperand(2),
1733 CombineTo(N, ExtLoad);
1734 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1740 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1741 SDOperand N0 = N->getOperand(0);
1742 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1743 MVT::ValueType VT = N->getValueType(0);
1746 if (N0.getValueType() == N->getValueType(0))
1748 // fold (truncate c1) -> c1
1750 return DAG.getNode(ISD::TRUNCATE, VT, N0);
1751 // fold (truncate (truncate x)) -> (truncate x)
1752 if (N0.getOpcode() == ISD::TRUNCATE)
1753 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1754 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1755 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
1756 if (N0.getValueType() < VT)
1757 // if the source is smaller than the dest, we still need an extend
1758 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1759 else if (N0.getValueType() > VT)
1760 // if the source is larger than the dest, than we just need the truncate
1761 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1763 // if the source and dest are the same type, we can drop both the extend
1765 return N0.getOperand(0);
1767 // fold (truncate (load x)) -> (smaller load x)
1768 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1769 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
1770 "Cannot truncate to larger type!");
1771 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1772 // For big endian targets, we need to add an offset to the pointer to load
1773 // the correct bytes. For little endian systems, we merely need to read
1774 // fewer bytes from the same pointer.
1776 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
1777 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
1778 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
1779 DAG.getConstant(PtrOff, PtrType));
1780 WorkList.push_back(NewPtr.Val);
1781 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
1782 WorkList.push_back(N);
1783 CombineTo(N0.Val, Load, Load.getValue(1));
1789 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
1790 SDOperand N0 = N->getOperand(0);
1791 MVT::ValueType VT = N->getValueType(0);
1793 // If the input is a constant, let getNode() fold it.
1794 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
1795 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
1796 if (Res.Val != N) return Res;
1799 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
1800 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
1802 // fold (conv (load x)) -> (load (conv*)x)
1803 // FIXME: These xforms need to know that the resultant load doesn't need a
1804 // higher alignment than the original!
1805 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1806 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1),
1808 WorkList.push_back(N);
1809 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
1817 SDOperand DAGCombiner::visitFADD(SDNode *N) {
1818 SDOperand N0 = N->getOperand(0);
1819 SDOperand N1 = N->getOperand(1);
1820 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1821 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1822 MVT::ValueType VT = N->getValueType(0);
1824 // fold (fadd c1, c2) -> c1+c2
1826 return DAG.getNode(ISD::FADD, VT, N0, N1);
1827 // canonicalize constant to RHS
1828 if (N0CFP && !N1CFP)
1829 return DAG.getNode(ISD::FADD, VT, N1, N0);
1830 // fold (A + (-B)) -> A-B
1831 if (N1.getOpcode() == ISD::FNEG)
1832 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
1833 // fold ((-A) + B) -> B-A
1834 if (N0.getOpcode() == ISD::FNEG)
1835 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
1839 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
1840 SDOperand N0 = N->getOperand(0);
1841 SDOperand N1 = N->getOperand(1);
1842 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1843 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1844 MVT::ValueType VT = N->getValueType(0);
1846 // fold (fsub c1, c2) -> c1-c2
1848 return DAG.getNode(ISD::FSUB, VT, N0, N1);
1849 // fold (A-(-B)) -> A+B
1850 if (N1.getOpcode() == ISD::FNEG)
1851 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
1855 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
1856 SDOperand N0 = N->getOperand(0);
1857 SDOperand N1 = N->getOperand(1);
1858 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1859 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1860 MVT::ValueType VT = N->getValueType(0);
1862 // fold (fmul c1, c2) -> c1*c2
1864 return DAG.getNode(ISD::FMUL, VT, N0, N1);
1865 // canonicalize constant to RHS
1866 if (N0CFP && !N1CFP)
1867 return DAG.getNode(ISD::FMUL, VT, N1, N0);
1868 // fold (fmul X, 2.0) -> (fadd X, X)
1869 if (N1CFP && N1CFP->isExactlyValue(+2.0))
1870 return DAG.getNode(ISD::FADD, VT, N0, N0);
1874 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
1875 SDOperand N0 = N->getOperand(0);
1876 SDOperand N1 = N->getOperand(1);
1877 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1878 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1879 MVT::ValueType VT = N->getValueType(0);
1881 // fold (fdiv c1, c2) -> c1/c2
1883 return DAG.getNode(ISD::FDIV, VT, N0, N1);
1887 SDOperand DAGCombiner::visitFREM(SDNode *N) {
1888 SDOperand N0 = N->getOperand(0);
1889 SDOperand N1 = N->getOperand(1);
1890 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1891 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1892 MVT::ValueType VT = N->getValueType(0);
1894 // fold (frem c1, c2) -> fmod(c1,c2)
1896 return DAG.getNode(ISD::FREM, VT, N0, N1);
1901 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
1902 SDOperand N0 = N->getOperand(0);
1903 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1904 MVT::ValueType VT = N->getValueType(0);
1906 // fold (sint_to_fp c1) -> c1fp
1908 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
1912 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
1913 SDOperand N0 = N->getOperand(0);
1914 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1915 MVT::ValueType VT = N->getValueType(0);
1917 // fold (uint_to_fp c1) -> c1fp
1919 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
1923 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
1924 SDOperand N0 = N->getOperand(0);
1925 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1926 MVT::ValueType VT = N->getValueType(0);
1928 // fold (fp_to_sint c1fp) -> c1
1930 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
1934 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1935 SDOperand N0 = N->getOperand(0);
1936 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1937 MVT::ValueType VT = N->getValueType(0);
1939 // fold (fp_to_uint c1fp) -> c1
1941 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
1945 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
1946 SDOperand N0 = N->getOperand(0);
1947 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1948 MVT::ValueType VT = N->getValueType(0);
1950 // fold (fp_round c1fp) -> c1fp
1952 return DAG.getNode(ISD::FP_ROUND, VT, N0);
1956 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
1957 SDOperand N0 = N->getOperand(0);
1958 MVT::ValueType VT = N->getValueType(0);
1959 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1960 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1962 // fold (fp_round_inreg c1fp) -> c1fp
1964 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
1965 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
1970 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
1971 SDOperand N0 = N->getOperand(0);
1972 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1973 MVT::ValueType VT = N->getValueType(0);
1975 // fold (fp_extend c1fp) -> c1fp
1977 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
1981 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
1982 SDOperand N0 = N->getOperand(0);
1983 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1984 MVT::ValueType VT = N->getValueType(0);
1986 // fold (fneg c1) -> -c1
1988 return DAG.getNode(ISD::FNEG, VT, N0);
1989 // fold (fneg (sub x, y)) -> (sub y, x)
1990 if (N->getOperand(0).getOpcode() == ISD::SUB)
1991 return DAG.getNode(ISD::SUB, VT, N->getOperand(1), N->getOperand(0));
1992 // fold (fneg (fneg x)) -> x
1993 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1994 return N->getOperand(0).getOperand(0);
1998 SDOperand DAGCombiner::visitFABS(SDNode *N) {
1999 SDOperand N0 = N->getOperand(0);
2000 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2001 MVT::ValueType VT = N->getValueType(0);
2003 // fold (fabs c1) -> fabs(c1)
2005 return DAG.getNode(ISD::FABS, VT, N0);
2006 // fold (fabs (fabs x)) -> (fabs x)
2007 if (N->getOperand(0).getOpcode() == ISD::FABS)
2008 return N->getOperand(0);
2009 // fold (fabs (fneg x)) -> (fabs x)
2010 if (N->getOperand(0).getOpcode() == ISD::FNEG)
2011 return DAG.getNode(ISD::FABS, VT, N->getOperand(0).getOperand(0));
2015 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2016 SDOperand Chain = N->getOperand(0);
2017 SDOperand N1 = N->getOperand(1);
2018 SDOperand N2 = N->getOperand(2);
2019 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2021 // never taken branch, fold to chain
2022 if (N1C && N1C->isNullValue())
2024 // unconditional branch
2025 if (N1C && N1C->getValue() == 1)
2026 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2030 SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
2031 SDOperand Chain = N->getOperand(0);
2032 SDOperand N1 = N->getOperand(1);
2033 SDOperand N2 = N->getOperand(2);
2034 SDOperand N3 = N->getOperand(3);
2035 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2037 // unconditional branch to true mbb
2038 if (N1C && N1C->getValue() == 1)
2039 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2040 // unconditional branch to false mbb
2041 if (N1C && N1C->isNullValue())
2042 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
2046 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2048 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2049 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2050 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2052 // Use SimplifySetCC to simplify SETCC's.
2053 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2054 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2056 // fold br_cc true, dest -> br dest (unconditional branch)
2057 if (SCCC && SCCC->getValue())
2058 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2060 // fold br_cc false, dest -> unconditional fall through
2061 if (SCCC && SCCC->isNullValue())
2062 return N->getOperand(0);
2063 // fold to a simpler setcc
2064 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2065 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2066 Simp.getOperand(2), Simp.getOperand(0),
2067 Simp.getOperand(1), N->getOperand(4));
2071 SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
2072 SDOperand Chain = N->getOperand(0);
2073 SDOperand CCN = N->getOperand(1);
2074 SDOperand LHS = N->getOperand(2);
2075 SDOperand RHS = N->getOperand(3);
2076 SDOperand N4 = N->getOperand(4);
2077 SDOperand N5 = N->getOperand(5);
2079 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
2080 cast<CondCodeSDNode>(CCN)->get(), false);
2081 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2083 // fold select_cc lhs, rhs, x, x, cc -> x
2085 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
2086 // fold select_cc true, x, y -> x
2087 if (SCCC && SCCC->getValue())
2088 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
2089 // fold select_cc false, x, y -> y
2090 if (SCCC && SCCC->isNullValue())
2091 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
2092 // fold to a simpler setcc
2093 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2094 return DAG.getBR2Way_CC(Chain, SCC.getOperand(2), SCC.getOperand(0),
2095 SCC.getOperand(1), N4, N5);
2099 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2100 SDOperand Chain = N->getOperand(0);
2101 SDOperand Ptr = N->getOperand(1);
2102 SDOperand SrcValue = N->getOperand(2);
2104 // If this load is directly stored, replace the load value with the stored
2106 // TODO: Handle store large -> read small portion.
2107 // TODO: Handle TRUNCSTORE/EXTLOAD
2108 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2109 Chain.getOperand(1).getValueType() == N->getValueType(0))
2110 return CombineTo(N, Chain.getOperand(1), Chain);
2115 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2116 SDOperand Chain = N->getOperand(0);
2117 SDOperand Value = N->getOperand(1);
2118 SDOperand Ptr = N->getOperand(2);
2119 SDOperand SrcValue = N->getOperand(3);
2121 // If this is a store that kills a previous store, remove the previous store.
2122 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2123 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2124 // Make sure that these stores are the same value type:
2125 // FIXME: we really care that the second store is >= size of the first.
2126 Value.getValueType() == Chain.getOperand(1).getValueType()) {
2127 // Create a new store of Value that replaces both stores.
2128 SDNode *PrevStore = Chain.Val;
2129 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
2131 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
2132 PrevStore->getOperand(0), Value, Ptr,
2134 CombineTo(N, NewStore); // Nuke this store.
2135 CombineTo(PrevStore, NewStore); // Nuke the previous store.
2136 return SDOperand(N, 0);
2139 // If this is a store of a bit convert, store the input value.
2140 // FIXME: This needs to know that the resultant store does not need a
2141 // higher alignment than the original.
2142 if (0 && Value.getOpcode() == ISD::BIT_CONVERT)
2143 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0),
2149 SDOperand DAGCombiner::visitLOCATION(SDNode *N) {
2150 SDOperand Chain = N->getOperand(0);
2152 // Remove redundant locations (last one holds)
2153 if (Chain.getOpcode() == ISD::LOCATION && Chain.hasOneUse()) {
2154 return DAG.getNode(ISD::LOCATION, MVT::Other, Chain.getOperand(0),
2164 SDOperand DAGCombiner::visitDEBUGLOC(SDNode *N) {
2165 SDOperand Chain = N->getOperand(0);
2167 // Remove redundant debug locations (last one holds)
2168 if (Chain.getOpcode() == ISD::DEBUG_LOC && Chain.hasOneUse()) {
2169 return DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Chain.getOperand(0),
2178 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
2179 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
2181 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
2182 cast<CondCodeSDNode>(N0.getOperand(2))->get());
2183 // If we got a simplified select_cc node back from SimplifySelectCC, then
2184 // break it down into a new SETCC node, and a new SELECT node, and then return
2185 // the SELECT node, since we were called with a SELECT node.
2187 // Check to see if we got a select_cc back (to turn into setcc/select).
2188 // Otherwise, just return whatever node we got back, like fabs.
2189 if (SCC.getOpcode() == ISD::SELECT_CC) {
2190 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
2191 SCC.getOperand(0), SCC.getOperand(1),
2193 WorkList.push_back(SETCC.Val);
2194 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
2195 SCC.getOperand(3), SETCC);
2202 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
2203 /// are the two values being selected between, see if we can simplify the
2206 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
2209 // If this is a select from two identical things, try to pull the operation
2210 // through the select.
2211 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
2213 std::cerr << "SELECT: ["; LHS.Val->dump();
2214 std::cerr << "] ["; RHS.Val->dump();
2218 // If this is a load and the token chain is identical, replace the select
2219 // of two loads with a load through a select of the address to load from.
2220 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
2221 // constants have been dropped into the constant pool.
2222 if ((LHS.getOpcode() == ISD::LOAD ||
2223 LHS.getOpcode() == ISD::EXTLOAD ||
2224 LHS.getOpcode() == ISD::ZEXTLOAD ||
2225 LHS.getOpcode() == ISD::SEXTLOAD) &&
2226 // Token chains must be identical.
2227 LHS.getOperand(0) == RHS.getOperand(0) &&
2228 // If this is an EXTLOAD, the VT's must match.
2229 (LHS.getOpcode() == ISD::LOAD ||
2230 LHS.getOperand(3) == RHS.getOperand(3))) {
2231 // FIXME: this conflates two src values, discarding one. This is not
2232 // the right thing to do, but nothing uses srcvalues now. When they do,
2233 // turn SrcValue into a list of locations.
2235 if (TheSelect->getOpcode() == ISD::SELECT)
2236 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
2237 TheSelect->getOperand(0), LHS.getOperand(1),
2240 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
2241 TheSelect->getOperand(0),
2242 TheSelect->getOperand(1),
2243 LHS.getOperand(1), RHS.getOperand(1),
2244 TheSelect->getOperand(4));
2247 if (LHS.getOpcode() == ISD::LOAD)
2248 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
2249 Addr, LHS.getOperand(2));
2251 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0),
2252 LHS.getOperand(0), Addr, LHS.getOperand(2),
2253 cast<VTSDNode>(LHS.getOperand(3))->getVT());
2254 // Users of the select now use the result of the load.
2255 CombineTo(TheSelect, Load);
2257 // Users of the old loads now use the new load's chain. We know the
2258 // old-load value is dead now.
2259 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
2260 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
2268 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
2269 SDOperand N2, SDOperand N3,
2272 MVT::ValueType VT = N2.getValueType();
2273 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
2274 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
2275 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
2276 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
2278 // Determine if the condition we're dealing with is constant
2279 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2280 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2282 // fold select_cc true, x, y -> x
2283 if (SCCC && SCCC->getValue())
2285 // fold select_cc false, x, y -> y
2286 if (SCCC && SCCC->getValue() == 0)
2289 // Check to see if we can simplify the select into an fabs node
2290 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
2291 // Allow either -0.0 or 0.0
2292 if (CFP->getValue() == 0.0) {
2293 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
2294 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
2295 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
2296 N2 == N3.getOperand(0))
2297 return DAG.getNode(ISD::FABS, VT, N0);
2299 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
2300 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
2301 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
2302 N2.getOperand(0) == N3)
2303 return DAG.getNode(ISD::FABS, VT, N3);
2307 // Check to see if we can perform the "gzip trick", transforming
2308 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
2309 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
2310 MVT::isInteger(N0.getValueType()) &&
2311 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
2312 MVT::ValueType XType = N0.getValueType();
2313 MVT::ValueType AType = N2.getValueType();
2314 if (XType >= AType) {
2315 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
2316 // single-bit constant.
2317 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
2318 unsigned ShCtV = Log2_64(N2C->getValue());
2319 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
2320 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
2321 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
2322 WorkList.push_back(Shift.Val);
2323 if (XType > AType) {
2324 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2325 WorkList.push_back(Shift.Val);
2327 return DAG.getNode(ISD::AND, AType, Shift, N2);
2329 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2330 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2331 TLI.getShiftAmountTy()));
2332 WorkList.push_back(Shift.Val);
2333 if (XType > AType) {
2334 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2335 WorkList.push_back(Shift.Val);
2337 return DAG.getNode(ISD::AND, AType, Shift, N2);
2341 // fold select C, 16, 0 -> shl C, 4
2342 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
2343 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
2344 // Get a SetCC of the condition
2345 // FIXME: Should probably make sure that setcc is legal if we ever have a
2346 // target where it isn't.
2347 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2348 WorkList.push_back(SCC.Val);
2349 // cast from setcc result type to select result type
2351 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
2353 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
2354 WorkList.push_back(Temp.Val);
2355 // shl setcc result by log2 n2c
2356 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
2357 DAG.getConstant(Log2_64(N2C->getValue()),
2358 TLI.getShiftAmountTy()));
2361 // Check to see if this is the equivalent of setcc
2362 // FIXME: Turn all of these into setcc if setcc if setcc is legal
2363 // otherwise, go ahead with the folds.
2364 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
2365 MVT::ValueType XType = N0.getValueType();
2366 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
2367 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2368 if (Res.getValueType() != VT)
2369 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
2373 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
2374 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
2375 TLI.isOperationLegal(ISD::CTLZ, XType)) {
2376 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
2377 return DAG.getNode(ISD::SRL, XType, Ctlz,
2378 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
2379 TLI.getShiftAmountTy()));
2381 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
2382 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
2383 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
2385 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
2386 DAG.getConstant(~0ULL, XType));
2387 return DAG.getNode(ISD::SRL, XType,
2388 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
2389 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2390 TLI.getShiftAmountTy()));
2392 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
2393 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
2394 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
2395 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2396 TLI.getShiftAmountTy()));
2397 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
2401 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
2402 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2403 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
2404 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
2405 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
2406 MVT::ValueType XType = N0.getValueType();
2407 if (SubC->isNullValue() && MVT::isInteger(XType)) {
2408 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2409 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2410 TLI.getShiftAmountTy()));
2411 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
2412 WorkList.push_back(Shift.Val);
2413 WorkList.push_back(Add.Val);
2414 return DAG.getNode(ISD::XOR, XType, Add, Shift);
2422 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
2423 SDOperand N1, ISD::CondCode Cond,
2424 bool foldBooleans) {
2425 // These setcc operations always fold.
2429 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
2431 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
2434 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
2435 uint64_t C1 = N1C->getValue();
2436 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
2437 uint64_t C0 = N0C->getValue();
2439 // Sign extend the operands if required
2440 if (ISD::isSignedIntSetCC(Cond)) {
2441 C0 = N0C->getSignExtended();
2442 C1 = N1C->getSignExtended();
2446 default: assert(0 && "Unknown integer setcc!");
2447 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2448 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2449 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
2450 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
2451 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
2452 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
2453 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
2454 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
2455 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
2456 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
2459 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2460 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2461 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
2463 // If the comparison constant has bits in the upper part, the
2464 // zero-extended value could never match.
2465 if (C1 & (~0ULL << InSize)) {
2466 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
2470 case ISD::SETEQ: return DAG.getConstant(0, VT);
2473 case ISD::SETNE: return DAG.getConstant(1, VT);
2476 // True if the sign bit of C1 is set.
2477 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
2480 // True if the sign bit of C1 isn't set.
2481 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
2487 // Otherwise, we can perform the comparison with the low bits.
2495 return DAG.getSetCC(VT, N0.getOperand(0),
2496 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
2499 break; // todo, be more careful with signed comparisons
2501 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2502 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2503 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2504 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
2505 MVT::ValueType ExtDstTy = N0.getValueType();
2506 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
2508 // If the extended part has any inconsistent bits, it cannot ever
2509 // compare equal. In other words, they have to be all ones or all
2512 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
2513 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
2514 return DAG.getConstant(Cond == ISD::SETNE, VT);
2517 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
2518 if (Op0Ty == ExtSrcTy) {
2519 ZextOp = N0.getOperand(0);
2521 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
2522 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
2523 DAG.getConstant(Imm, Op0Ty));
2525 WorkList.push_back(ZextOp.Val);
2526 // Otherwise, make this a use of a zext.
2527 return DAG.getSetCC(VT, ZextOp,
2528 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
2533 uint64_t MinVal, MaxVal;
2534 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
2535 if (ISD::isSignedIntSetCC(Cond)) {
2536 MinVal = 1ULL << (OperandBitSize-1);
2537 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
2538 MaxVal = ~0ULL >> (65-OperandBitSize);
2543 MaxVal = ~0ULL >> (64-OperandBitSize);
2546 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2547 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2548 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2549 --C1; // X >= C0 --> X > (C0-1)
2550 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2551 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2554 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2555 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2556 ++C1; // X <= C0 --> X < (C0+1)
2557 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2558 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2561 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2562 return DAG.getConstant(0, VT); // X < MIN --> false
2564 // Canonicalize setgt X, Min --> setne X, Min
2565 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2566 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2567 // Canonicalize setlt X, Max --> setne X, Max
2568 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2569 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2571 // If we have setult X, 1, turn it into seteq X, 0
2572 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2573 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
2575 // If we have setugt X, Max-1, turn it into seteq X, Max
2576 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2577 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
2580 // If we have "setcc X, C0", check to see if we can shrink the immediate
2583 // SETUGT X, SINTMAX -> SETLT X, 0
2584 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
2585 C1 == (~0ULL >> (65-OperandBitSize)))
2586 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
2589 // FIXME: Implement the rest of these.
2591 // Fold bit comparisons when we can.
2592 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2593 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
2594 if (ConstantSDNode *AndRHS =
2595 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2596 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2597 // Perform the xform if the AND RHS is a single bit.
2598 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
2599 return DAG.getNode(ISD::SRL, VT, N0,
2600 DAG.getConstant(Log2_64(AndRHS->getValue()),
2601 TLI.getShiftAmountTy()));
2603 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
2604 // (X & 8) == 8 --> (X & 8) >> 3
2605 // Perform the xform if C1 is a single bit.
2606 if ((C1 & (C1-1)) == 0) {
2607 return DAG.getNode(ISD::SRL, VT, N0,
2608 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
2613 } else if (isa<ConstantSDNode>(N0.Val)) {
2614 // Ensure that the constant occurs on the RHS.
2615 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2618 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
2619 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
2620 double C0 = N0C->getValue(), C1 = N1C->getValue();
2623 default: break; // FIXME: Implement the rest of these!
2624 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2625 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2626 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
2627 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
2628 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
2629 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
2632 // Ensure that the constant occurs on the RHS.
2633 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2637 // We can always fold X == Y for integer setcc's.
2638 if (MVT::isInteger(N0.getValueType()))
2639 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2640 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2641 if (UOF == 2) // FP operators that are undefined on NaNs.
2642 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2643 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2644 return DAG.getConstant(UOF, VT);
2645 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2646 // if it is not already.
2647 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2648 if (NewCond != Cond)
2649 return DAG.getSetCC(VT, N0, N1, NewCond);
2652 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2653 MVT::isInteger(N0.getValueType())) {
2654 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2655 N0.getOpcode() == ISD::XOR) {
2656 // Simplify (X+Y) == (X+Z) --> Y == Z
2657 if (N0.getOpcode() == N1.getOpcode()) {
2658 if (N0.getOperand(0) == N1.getOperand(0))
2659 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2660 if (N0.getOperand(1) == N1.getOperand(1))
2661 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
2662 if (isCommutativeBinOp(N0.getOpcode())) {
2663 // If X op Y == Y op X, try other combinations.
2664 if (N0.getOperand(0) == N1.getOperand(1))
2665 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
2666 if (N0.getOperand(1) == N1.getOperand(0))
2667 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
2671 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes.
2672 if (N0.getOpcode() == ISD::XOR)
2673 if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2674 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2675 // If we know that all of the inverted bits are zero, don't bother
2676 // performing the inversion.
2677 if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI))
2678 return DAG.getSetCC(VT, N0.getOperand(0),
2679 DAG.getConstant(XORC->getValue()^RHSC->getValue(),
2680 N0.getValueType()), Cond);
2683 // Simplify (X+Z) == X --> Z == 0
2684 if (N0.getOperand(0) == N1)
2685 return DAG.getSetCC(VT, N0.getOperand(1),
2686 DAG.getConstant(0, N0.getValueType()), Cond);
2687 if (N0.getOperand(1) == N1) {
2688 if (isCommutativeBinOp(N0.getOpcode()))
2689 return DAG.getSetCC(VT, N0.getOperand(0),
2690 DAG.getConstant(0, N0.getValueType()), Cond);
2692 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2693 // (Z-X) == X --> Z == X<<1
2694 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
2696 DAG.getConstant(1,TLI.getShiftAmountTy()));
2697 WorkList.push_back(SH.Val);
2698 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
2703 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2704 N1.getOpcode() == ISD::XOR) {
2705 // Simplify X == (X+Z) --> Z == 0
2706 if (N1.getOperand(0) == N0) {
2707 return DAG.getSetCC(VT, N1.getOperand(1),
2708 DAG.getConstant(0, N1.getValueType()), Cond);
2709 } else if (N1.getOperand(1) == N0) {
2710 if (isCommutativeBinOp(N1.getOpcode())) {
2711 return DAG.getSetCC(VT, N1.getOperand(0),
2712 DAG.getConstant(0, N1.getValueType()), Cond);
2714 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2715 // X == (Z-X) --> X<<1 == Z
2716 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
2717 DAG.getConstant(1,TLI.getShiftAmountTy()));
2718 WorkList.push_back(SH.Val);
2719 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
2725 // Fold away ALL boolean setcc's.
2727 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2729 default: assert(0 && "Unknown integer setcc!");
2730 case ISD::SETEQ: // X == Y -> (X^Y)^1
2731 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2732 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
2733 WorkList.push_back(Temp.Val);
2735 case ISD::SETNE: // X != Y --> (X^Y)
2736 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2738 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
2739 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
2740 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2741 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
2742 WorkList.push_back(Temp.Val);
2744 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
2745 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
2746 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2747 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
2748 WorkList.push_back(Temp.Val);
2750 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
2751 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
2752 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2753 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
2754 WorkList.push_back(Temp.Val);
2756 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
2757 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
2758 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2759 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
2762 if (VT != MVT::i1) {
2763 WorkList.push_back(N0.Val);
2764 // FIXME: If running after legalize, we probably can't do this.
2765 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2770 // Could not fold it.
2774 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2775 /// return a DAG expression to select that will generate the same value by
2776 /// multiplying by a magic number. See:
2777 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2778 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
2779 MVT::ValueType VT = N->getValueType(0);
2781 // Check to see if we can do this.
2782 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2783 return SDOperand(); // BuildSDIV only operates on i32 or i64
2784 if (!TLI.isOperationLegal(ISD::MULHS, VT))
2785 return SDOperand(); // Make sure the target supports MULHS.
2787 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
2788 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
2790 // Multiply the numerator (operand 0) by the magic value
2791 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
2792 DAG.getConstant(magics.m, VT));
2793 // If d > 0 and m < 0, add the numerator
2794 if (d > 0 && magics.m < 0) {
2795 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
2796 WorkList.push_back(Q.Val);
2798 // If d < 0 and m > 0, subtract the numerator.
2799 if (d < 0 && magics.m > 0) {
2800 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
2801 WorkList.push_back(Q.Val);
2803 // Shift right algebraic if shift value is nonzero
2805 Q = DAG.getNode(ISD::SRA, VT, Q,
2806 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2807 WorkList.push_back(Q.Val);
2809 // Extract the sign bit and add it to the quotient
2811 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
2812 TLI.getShiftAmountTy()));
2813 WorkList.push_back(T.Val);
2814 return DAG.getNode(ISD::ADD, VT, Q, T);
2817 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2818 /// return a DAG expression to select that will generate the same value by
2819 /// multiplying by a magic number. See:
2820 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2821 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
2822 MVT::ValueType VT = N->getValueType(0);
2824 // Check to see if we can do this.
2825 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2826 return SDOperand(); // BuildUDIV only operates on i32 or i64
2827 if (!TLI.isOperationLegal(ISD::MULHU, VT))
2828 return SDOperand(); // Make sure the target supports MULHU.
2830 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
2831 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
2833 // Multiply the numerator (operand 0) by the magic value
2834 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
2835 DAG.getConstant(magics.m, VT));
2836 WorkList.push_back(Q.Val);
2838 if (magics.a == 0) {
2839 return DAG.getNode(ISD::SRL, VT, Q,
2840 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2842 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
2843 WorkList.push_back(NPQ.Val);
2844 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
2845 DAG.getConstant(1, TLI.getShiftAmountTy()));
2846 WorkList.push_back(NPQ.Val);
2847 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
2848 WorkList.push_back(NPQ.Val);
2849 return DAG.getNode(ISD::SRL, VT, NPQ,
2850 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy()));
2854 // SelectionDAG::Combine - This is the entry point for the file.
2856 void SelectionDAG::Combine(bool RunningAfterLegalize) {
2857 /// run - This is the main entry point to this class.
2859 DAGCombiner(*this).Run(RunningAfterLegalize);