1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/Support/Compiler.h"
40 #include "llvm/Support/CommandLine.h"
44 STATISTIC(NodesCombined , "Number of dag nodes combined");
45 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
46 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
51 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
52 cl::desc("Pop up a window to show dags before the first "
55 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
56 cl::desc("Pop up a window to show dags before the second "
59 static const bool ViewDAGCombine1 = false;
60 static const bool ViewDAGCombine2 = false;
64 CombinerAA("combiner-alias-analysis", cl::Hidden,
65 cl::desc("Turn on alias analysis during testing"));
68 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
69 cl::desc("Include global information in alias analysis"));
71 //------------------------------ DAGCombiner ---------------------------------//
73 class VISIBILITY_HIDDEN DAGCombiner {
78 // Worklist of all of the nodes that need to be simplified.
79 std::vector<SDNode*> WorkList;
81 // AA - Used for DAG load/store alias analysis.
84 /// AddUsersToWorkList - When an instruction is simplified, add all users of
85 /// the instruction to the work lists because they might get more simplified
88 void AddUsersToWorkList(SDNode *N) {
89 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
94 /// removeFromWorkList - remove all instances of N from the worklist.
96 void removeFromWorkList(SDNode *N) {
97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
102 /// AddToWorkList - Add to the work list making sure it's instance is at the
103 /// the back (next to be processed.)
104 void AddToWorkList(SDNode *N) {
105 removeFromWorkList(N);
106 WorkList.push_back(N);
109 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
111 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
113 DOUT << "\nReplacing.1 "; DEBUG(N->dump());
114 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
115 DOUT << " and " << NumTo-1 << " other values\n";
116 std::vector<SDNode*> NowDead;
117 DAG.ReplaceAllUsesWith(N, To, &NowDead);
120 // Push the new nodes and any users onto the worklist
121 for (unsigned i = 0, e = NumTo; i != e; ++i) {
122 AddToWorkList(To[i].Val);
123 AddUsersToWorkList(To[i].Val);
127 // Nodes can be reintroduced into the worklist. Make sure we do not
128 // process a node that has been replaced.
129 removeFromWorkList(N);
130 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
131 removeFromWorkList(NowDead[i]);
133 // Finally, since the node is now dead, remove it from the graph.
135 return SDOperand(N, 0);
138 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
139 return CombineTo(N, &Res, 1, AddTo);
142 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
144 SDOperand To[] = { Res0, Res1 };
145 return CombineTo(N, To, 2, AddTo);
149 /// SimplifyDemandedBits - Check the specified integer node value to see if
150 /// it can be simplified or if things it uses can be simplified by bit
151 /// propagation. If so, return true.
152 bool SimplifyDemandedBits(SDOperand Op) {
153 TargetLowering::TargetLoweringOpt TLO(DAG);
154 uint64_t KnownZero, KnownOne;
155 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
156 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
160 AddToWorkList(Op.Val);
162 // Replace the old value with the new one.
164 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump());
165 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
168 std::vector<SDNode*> NowDead;
169 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
171 // Push the new node and any (possibly new) users onto the worklist.
172 AddToWorkList(TLO.New.Val);
173 AddUsersToWorkList(TLO.New.Val);
175 // Nodes can end up on the worklist more than once. Make sure we do
176 // not process a node that has been replaced.
177 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
178 removeFromWorkList(NowDead[i]);
180 // Finally, if the node is now dead, remove it from the graph. The node
181 // may not be dead if the replacement process recursively simplified to
182 // something else needing this node.
183 if (TLO.Old.Val->use_empty()) {
184 removeFromWorkList(TLO.Old.Val);
185 DAG.DeleteNode(TLO.Old.Val);
190 bool CombineToPreIndexedLoadStore(SDNode *N);
191 bool CombineToPostIndexedLoadStore(SDNode *N);
194 /// visit - call the node-specific routine that knows how to fold each
195 /// particular type of node.
196 SDOperand visit(SDNode *N);
198 // Visitation implementation - Implement dag node combining for different
199 // node types. The semantics are as follows:
201 // SDOperand.Val == 0 - No change was made
202 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
203 // otherwise - N should be replaced by the returned Operand.
205 SDOperand visitTokenFactor(SDNode *N);
206 SDOperand visitADD(SDNode *N);
207 SDOperand visitSUB(SDNode *N);
208 SDOperand visitADDC(SDNode *N);
209 SDOperand visitADDE(SDNode *N);
210 SDOperand visitMUL(SDNode *N);
211 SDOperand visitSDIV(SDNode *N);
212 SDOperand visitUDIV(SDNode *N);
213 SDOperand visitSREM(SDNode *N);
214 SDOperand visitUREM(SDNode *N);
215 SDOperand visitMULHU(SDNode *N);
216 SDOperand visitMULHS(SDNode *N);
217 SDOperand visitAND(SDNode *N);
218 SDOperand visitOR(SDNode *N);
219 SDOperand visitXOR(SDNode *N);
220 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
221 SDOperand visitSHL(SDNode *N);
222 SDOperand visitSRA(SDNode *N);
223 SDOperand visitSRL(SDNode *N);
224 SDOperand visitCTLZ(SDNode *N);
225 SDOperand visitCTTZ(SDNode *N);
226 SDOperand visitCTPOP(SDNode *N);
227 SDOperand visitSELECT(SDNode *N);
228 SDOperand visitSELECT_CC(SDNode *N);
229 SDOperand visitSETCC(SDNode *N);
230 SDOperand visitSIGN_EXTEND(SDNode *N);
231 SDOperand visitZERO_EXTEND(SDNode *N);
232 SDOperand visitANY_EXTEND(SDNode *N);
233 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
234 SDOperand visitTRUNCATE(SDNode *N);
235 SDOperand visitBIT_CONVERT(SDNode *N);
236 SDOperand visitVBIT_CONVERT(SDNode *N);
237 SDOperand visitFADD(SDNode *N);
238 SDOperand visitFSUB(SDNode *N);
239 SDOperand visitFMUL(SDNode *N);
240 SDOperand visitFDIV(SDNode *N);
241 SDOperand visitFREM(SDNode *N);
242 SDOperand visitFCOPYSIGN(SDNode *N);
243 SDOperand visitSINT_TO_FP(SDNode *N);
244 SDOperand visitUINT_TO_FP(SDNode *N);
245 SDOperand visitFP_TO_SINT(SDNode *N);
246 SDOperand visitFP_TO_UINT(SDNode *N);
247 SDOperand visitFP_ROUND(SDNode *N);
248 SDOperand visitFP_ROUND_INREG(SDNode *N);
249 SDOperand visitFP_EXTEND(SDNode *N);
250 SDOperand visitFNEG(SDNode *N);
251 SDOperand visitFABS(SDNode *N);
252 SDOperand visitBRCOND(SDNode *N);
253 SDOperand visitBR_CC(SDNode *N);
254 SDOperand visitLOAD(SDNode *N);
255 SDOperand visitSTORE(SDNode *N);
256 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
257 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
258 SDOperand visitVBUILD_VECTOR(SDNode *N);
259 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
260 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
262 SDOperand XformToShuffleWithZero(SDNode *N);
263 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
265 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
266 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
267 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
268 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
269 SDOperand N3, ISD::CondCode CC,
270 bool NotExtCompare = false);
271 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
272 ISD::CondCode Cond, bool foldBooleans = true);
273 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
274 SDOperand BuildSDIV(SDNode *N);
275 SDOperand BuildUDIV(SDNode *N);
276 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
277 SDOperand ReduceLoadWidth(SDNode *N);
279 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
280 /// looking for aliasing nodes and adding them to the Aliases vector.
281 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
282 SmallVector<SDOperand, 8> &Aliases);
284 /// isAlias - Return true if there is any possibility that the two addresses
286 bool isAlias(SDOperand Ptr1, int64_t Size1,
287 const Value *SrcValue1, int SrcValueOffset1,
288 SDOperand Ptr2, int64_t Size2,
289 const Value *SrcValue2, int SrcValueOffset2);
291 /// FindAliasInfo - Extracts the relevant alias information from the memory
292 /// node. Returns true if the operand was a load.
293 bool FindAliasInfo(SDNode *N,
294 SDOperand &Ptr, int64_t &Size,
295 const Value *&SrcValue, int &SrcValueOffset);
297 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
298 /// looking for a better chain (aliasing node.)
299 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
302 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
304 TLI(D.getTargetLoweringInfo()),
305 AfterLegalize(false),
308 /// Run - runs the dag combiner on all nodes in the work list
309 void Run(bool RunningAfterLegalize);
313 //===----------------------------------------------------------------------===//
314 // TargetLowering::DAGCombinerInfo implementation
315 //===----------------------------------------------------------------------===//
317 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
318 ((DAGCombiner*)DC)->AddToWorkList(N);
321 SDOperand TargetLowering::DAGCombinerInfo::
322 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
323 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
326 SDOperand TargetLowering::DAGCombinerInfo::
327 CombineTo(SDNode *N, SDOperand Res) {
328 return ((DAGCombiner*)DC)->CombineTo(N, Res);
332 SDOperand TargetLowering::DAGCombinerInfo::
333 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
334 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
340 //===----------------------------------------------------------------------===//
343 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
344 // that selects between the values 1 and 0, making it equivalent to a setcc.
345 // Also, set the incoming LHS, RHS, and CC references to the appropriate
346 // nodes based on the type of node we are checking. This simplifies life a
347 // bit for the callers.
348 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
350 if (N.getOpcode() == ISD::SETCC) {
351 LHS = N.getOperand(0);
352 RHS = N.getOperand(1);
353 CC = N.getOperand(2);
356 if (N.getOpcode() == ISD::SELECT_CC &&
357 N.getOperand(2).getOpcode() == ISD::Constant &&
358 N.getOperand(3).getOpcode() == ISD::Constant &&
359 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
360 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
361 LHS = N.getOperand(0);
362 RHS = N.getOperand(1);
363 CC = N.getOperand(4);
369 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
370 // one use. If this is true, it allows the users to invert the operation for
371 // free when it is profitable to do so.
372 static bool isOneUseSetCC(SDOperand N) {
373 SDOperand N0, N1, N2;
374 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
379 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
380 MVT::ValueType VT = N0.getValueType();
381 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
382 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
383 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
384 if (isa<ConstantSDNode>(N1)) {
385 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
386 AddToWorkList(OpNode.Val);
387 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
388 } else if (N0.hasOneUse()) {
389 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
390 AddToWorkList(OpNode.Val);
391 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
394 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
395 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
396 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
397 if (isa<ConstantSDNode>(N0)) {
398 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
399 AddToWorkList(OpNode.Val);
400 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
401 } else if (N1.hasOneUse()) {
402 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
403 AddToWorkList(OpNode.Val);
404 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
410 void DAGCombiner::Run(bool RunningAfterLegalize) {
411 // set the instance variable, so that the various visit routines may use it.
412 AfterLegalize = RunningAfterLegalize;
414 // Add all the dag nodes to the worklist.
415 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
416 E = DAG.allnodes_end(); I != E; ++I)
417 WorkList.push_back(I);
419 // Create a dummy node (which is not added to allnodes), that adds a reference
420 // to the root node, preventing it from being deleted, and tracking any
421 // changes of the root.
422 HandleSDNode Dummy(DAG.getRoot());
424 // The root of the dag may dangle to deleted nodes until the dag combiner is
425 // done. Set it to null to avoid confusion.
426 DAG.setRoot(SDOperand());
428 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
429 TargetLowering::DAGCombinerInfo
430 DagCombineInfo(DAG, !RunningAfterLegalize, false, this);
432 // while the worklist isn't empty, inspect the node on the end of it and
433 // try and combine it.
434 while (!WorkList.empty()) {
435 SDNode *N = WorkList.back();
438 // If N has no uses, it is dead. Make sure to revisit all N's operands once
439 // N is deleted from the DAG, since they too may now be dead or may have a
440 // reduced number of uses, allowing other xforms.
441 if (N->use_empty() && N != &Dummy) {
442 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
443 AddToWorkList(N->getOperand(i).Val);
449 SDOperand RV = visit(N);
451 // If nothing happened, try a target-specific DAG combine.
453 assert(N->getOpcode() != ISD::DELETED_NODE &&
454 "Node was deleted but visit returned NULL!");
455 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
456 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
457 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
462 // If we get back the same node we passed in, rather than a new node or
463 // zero, we know that the node must have defined multiple values and
464 // CombineTo was used. Since CombineTo takes care of the worklist
465 // mechanics for us, we have no work to do in this case.
467 assert(N->getOpcode() != ISD::DELETED_NODE &&
468 RV.Val->getOpcode() != ISD::DELETED_NODE &&
469 "Node was deleted but visit returned new node!");
471 DOUT << "\nReplacing.3 "; DEBUG(N->dump());
472 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
474 std::vector<SDNode*> NowDead;
475 if (N->getNumValues() == RV.Val->getNumValues())
476 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
478 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
480 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
483 // Push the new node and any users onto the worklist
484 AddToWorkList(RV.Val);
485 AddUsersToWorkList(RV.Val);
487 // Nodes can be reintroduced into the worklist. Make sure we do not
488 // process a node that has been replaced.
489 removeFromWorkList(N);
490 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
491 removeFromWorkList(NowDead[i]);
493 // Finally, since the node is now dead, remove it from the graph.
499 // If the root changed (e.g. it was a dead load, update the root).
500 DAG.setRoot(Dummy.getValue());
503 SDOperand DAGCombiner::visit(SDNode *N) {
504 switch(N->getOpcode()) {
506 case ISD::TokenFactor: return visitTokenFactor(N);
507 case ISD::ADD: return visitADD(N);
508 case ISD::SUB: return visitSUB(N);
509 case ISD::ADDC: return visitADDC(N);
510 case ISD::ADDE: return visitADDE(N);
511 case ISD::MUL: return visitMUL(N);
512 case ISD::SDIV: return visitSDIV(N);
513 case ISD::UDIV: return visitUDIV(N);
514 case ISD::SREM: return visitSREM(N);
515 case ISD::UREM: return visitUREM(N);
516 case ISD::MULHU: return visitMULHU(N);
517 case ISD::MULHS: return visitMULHS(N);
518 case ISD::AND: return visitAND(N);
519 case ISD::OR: return visitOR(N);
520 case ISD::XOR: return visitXOR(N);
521 case ISD::SHL: return visitSHL(N);
522 case ISD::SRA: return visitSRA(N);
523 case ISD::SRL: return visitSRL(N);
524 case ISD::CTLZ: return visitCTLZ(N);
525 case ISD::CTTZ: return visitCTTZ(N);
526 case ISD::CTPOP: return visitCTPOP(N);
527 case ISD::SELECT: return visitSELECT(N);
528 case ISD::SELECT_CC: return visitSELECT_CC(N);
529 case ISD::SETCC: return visitSETCC(N);
530 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
531 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
532 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
533 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
534 case ISD::TRUNCATE: return visitTRUNCATE(N);
535 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
536 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
537 case ISD::FADD: return visitFADD(N);
538 case ISD::FSUB: return visitFSUB(N);
539 case ISD::FMUL: return visitFMUL(N);
540 case ISD::FDIV: return visitFDIV(N);
541 case ISD::FREM: return visitFREM(N);
542 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
543 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
544 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
545 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
546 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
547 case ISD::FP_ROUND: return visitFP_ROUND(N);
548 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
549 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
550 case ISD::FNEG: return visitFNEG(N);
551 case ISD::FABS: return visitFABS(N);
552 case ISD::BRCOND: return visitBRCOND(N);
553 case ISD::BR_CC: return visitBR_CC(N);
554 case ISD::LOAD: return visitLOAD(N);
555 case ISD::STORE: return visitSTORE(N);
556 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
557 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
558 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
559 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
560 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
561 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
562 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
563 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
564 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
565 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
566 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
567 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
568 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
573 /// getInputChainForNode - Given a node, return its input chain if it has one,
574 /// otherwise return a null sd operand.
575 static SDOperand getInputChainForNode(SDNode *N) {
576 if (unsigned NumOps = N->getNumOperands()) {
577 if (N->getOperand(0).getValueType() == MVT::Other)
578 return N->getOperand(0);
579 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
580 return N->getOperand(NumOps-1);
581 for (unsigned i = 1; i < NumOps-1; ++i)
582 if (N->getOperand(i).getValueType() == MVT::Other)
583 return N->getOperand(i);
585 return SDOperand(0, 0);
588 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
589 // If N has two operands, where one has an input chain equal to the other,
590 // the 'other' chain is redundant.
591 if (N->getNumOperands() == 2) {
592 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
593 return N->getOperand(0);
594 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
595 return N->getOperand(1);
599 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
600 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
601 bool Changed = false; // If we should replace this token factor.
603 // Start out with this token factor.
606 // Iterate through token factors. The TFs grows when new token factors are
608 for (unsigned i = 0; i < TFs.size(); ++i) {
611 // Check each of the operands.
612 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
613 SDOperand Op = TF->getOperand(i);
615 switch (Op.getOpcode()) {
616 case ISD::EntryToken:
617 // Entry tokens don't need to be added to the list. They are
622 case ISD::TokenFactor:
623 if ((CombinerAA || Op.hasOneUse()) &&
624 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
625 // Queue up for processing.
626 TFs.push_back(Op.Val);
627 // Clean up in case the token factor is removed.
628 AddToWorkList(Op.Val);
635 // Only add if not there prior.
636 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end())
645 // If we've change things around then replace token factor.
647 if (Ops.size() == 0) {
648 // The entry token is the only possible outcome.
649 Result = DAG.getEntryNode();
651 // New and improved token factor.
652 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
655 // Don't add users to work list.
656 return CombineTo(N, Result, false);
663 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
664 MVT::ValueType VT = N0.getValueType();
665 SDOperand N00 = N0.getOperand(0);
666 SDOperand N01 = N0.getOperand(1);
667 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
668 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
669 isa<ConstantSDNode>(N00.getOperand(1))) {
670 N0 = DAG.getNode(ISD::ADD, VT,
671 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
672 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
673 return DAG.getNode(ISD::ADD, VT, N0, N1);
678 SDOperand DAGCombiner::visitADD(SDNode *N) {
679 SDOperand N0 = N->getOperand(0);
680 SDOperand N1 = N->getOperand(1);
681 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
682 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
683 MVT::ValueType VT = N0.getValueType();
685 // fold (add c1, c2) -> c1+c2
687 return DAG.getNode(ISD::ADD, VT, N0, N1);
688 // canonicalize constant to RHS
690 return DAG.getNode(ISD::ADD, VT, N1, N0);
691 // fold (add x, 0) -> x
692 if (N1C && N1C->isNullValue())
694 // fold ((c1-A)+c2) -> (c1+c2)-A
695 if (N1C && N0.getOpcode() == ISD::SUB)
696 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
697 return DAG.getNode(ISD::SUB, VT,
698 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
701 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
704 // fold ((0-A) + B) -> B-A
705 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
706 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
707 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
708 // fold (A + (0-B)) -> A-B
709 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
710 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
711 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
712 // fold (A+(B-A)) -> B
713 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
714 return N1.getOperand(0);
716 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
717 return SDOperand(N, 0);
719 // fold (a+b) -> (a|b) iff a and b share no bits.
720 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
721 uint64_t LHSZero, LHSOne;
722 uint64_t RHSZero, RHSOne;
723 uint64_t Mask = MVT::getIntVTBitMask(VT);
724 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
726 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
728 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
729 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
730 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
731 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
732 return DAG.getNode(ISD::OR, VT, N0, N1);
736 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
737 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
738 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
739 if (Result.Val) return Result;
741 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
742 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
743 if (Result.Val) return Result;
749 SDOperand DAGCombiner::visitADDC(SDNode *N) {
750 SDOperand N0 = N->getOperand(0);
751 SDOperand N1 = N->getOperand(1);
752 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
753 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
754 MVT::ValueType VT = N0.getValueType();
756 // If the flag result is dead, turn this into an ADD.
757 if (N->hasNUsesOfValue(0, 1))
758 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
759 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
761 // canonicalize constant to RHS.
763 SDOperand Ops[] = { N1, N0 };
764 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
767 // fold (addc x, 0) -> x + no carry out
768 if (N1C && N1C->isNullValue())
769 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
771 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
772 uint64_t LHSZero, LHSOne;
773 uint64_t RHSZero, RHSOne;
774 uint64_t Mask = MVT::getIntVTBitMask(VT);
775 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
777 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
779 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
780 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
781 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
782 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
783 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
784 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
790 SDOperand DAGCombiner::visitADDE(SDNode *N) {
791 SDOperand N0 = N->getOperand(0);
792 SDOperand N1 = N->getOperand(1);
793 SDOperand CarryIn = N->getOperand(2);
794 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
795 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
796 //MVT::ValueType VT = N0.getValueType();
798 // canonicalize constant to RHS
800 SDOperand Ops[] = { N1, N0, CarryIn };
801 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
804 // fold (adde x, y, false) -> (addc x, y)
805 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
806 SDOperand Ops[] = { N1, N0 };
807 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
815 SDOperand DAGCombiner::visitSUB(SDNode *N) {
816 SDOperand N0 = N->getOperand(0);
817 SDOperand N1 = N->getOperand(1);
818 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
819 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
820 MVT::ValueType VT = N0.getValueType();
822 // fold (sub x, x) -> 0
824 return DAG.getConstant(0, N->getValueType(0));
825 // fold (sub c1, c2) -> c1-c2
827 return DAG.getNode(ISD::SUB, VT, N0, N1);
828 // fold (sub x, c) -> (add x, -c)
830 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
832 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
833 return N0.getOperand(1);
835 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
836 return N0.getOperand(0);
840 SDOperand DAGCombiner::visitMUL(SDNode *N) {
841 SDOperand N0 = N->getOperand(0);
842 SDOperand N1 = N->getOperand(1);
843 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
844 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
845 MVT::ValueType VT = N0.getValueType();
847 // fold (mul c1, c2) -> c1*c2
849 return DAG.getNode(ISD::MUL, VT, N0, N1);
850 // canonicalize constant to RHS
852 return DAG.getNode(ISD::MUL, VT, N1, N0);
853 // fold (mul x, 0) -> 0
854 if (N1C && N1C->isNullValue())
856 // fold (mul x, -1) -> 0-x
857 if (N1C && N1C->isAllOnesValue())
858 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
859 // fold (mul x, (1 << c)) -> x << c
860 if (N1C && isPowerOf2_64(N1C->getValue()))
861 return DAG.getNode(ISD::SHL, VT, N0,
862 DAG.getConstant(Log2_64(N1C->getValue()),
863 TLI.getShiftAmountTy()));
864 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
865 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
866 // FIXME: If the input is something that is easily negated (e.g. a
867 // single-use add), we should put the negate there.
868 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
869 DAG.getNode(ISD::SHL, VT, N0,
870 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
871 TLI.getShiftAmountTy())));
874 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
875 if (N1C && N0.getOpcode() == ISD::SHL &&
876 isa<ConstantSDNode>(N0.getOperand(1))) {
877 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
878 AddToWorkList(C3.Val);
879 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
882 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
885 SDOperand Sh(0,0), Y(0,0);
886 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
887 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
888 N0.Val->hasOneUse()) {
890 } else if (N1.getOpcode() == ISD::SHL &&
891 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
895 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
896 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
899 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
900 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
901 isa<ConstantSDNode>(N0.getOperand(1))) {
902 return DAG.getNode(ISD::ADD, VT,
903 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
904 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
908 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
914 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
915 SDOperand N0 = N->getOperand(0);
916 SDOperand N1 = N->getOperand(1);
917 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
918 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
919 MVT::ValueType VT = N->getValueType(0);
921 // fold (sdiv c1, c2) -> c1/c2
922 if (N0C && N1C && !N1C->isNullValue())
923 return DAG.getNode(ISD::SDIV, VT, N0, N1);
924 // fold (sdiv X, 1) -> X
925 if (N1C && N1C->getSignExtended() == 1LL)
927 // fold (sdiv X, -1) -> 0-X
928 if (N1C && N1C->isAllOnesValue())
929 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
930 // If we know the sign bits of both operands are zero, strength reduce to a
931 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
932 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
933 if (TLI.MaskedValueIsZero(N1, SignBit) &&
934 TLI.MaskedValueIsZero(N0, SignBit))
935 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
936 // fold (sdiv X, pow2) -> simple ops after legalize
937 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
938 (isPowerOf2_64(N1C->getSignExtended()) ||
939 isPowerOf2_64(-N1C->getSignExtended()))) {
940 // If dividing by powers of two is cheap, then don't perform the following
942 if (TLI.isPow2DivCheap())
944 int64_t pow2 = N1C->getSignExtended();
945 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
946 unsigned lg2 = Log2_64(abs2);
947 // Splat the sign bit into the register
948 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
949 DAG.getConstant(MVT::getSizeInBits(VT)-1,
950 TLI.getShiftAmountTy()));
951 AddToWorkList(SGN.Val);
952 // Add (N0 < 0) ? abs2 - 1 : 0;
953 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
954 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
955 TLI.getShiftAmountTy()));
956 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
957 AddToWorkList(SRL.Val);
958 AddToWorkList(ADD.Val); // Divide by pow2
959 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
960 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
961 // If we're dividing by a positive value, we're done. Otherwise, we must
962 // negate the result.
965 AddToWorkList(SRA.Val);
966 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
968 // if integer divide is expensive and we satisfy the requirements, emit an
969 // alternate sequence.
970 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
971 !TLI.isIntDivCheap()) {
972 SDOperand Op = BuildSDIV(N);
973 if (Op.Val) return Op;
978 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
979 SDOperand N0 = N->getOperand(0);
980 SDOperand N1 = N->getOperand(1);
981 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
982 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
983 MVT::ValueType VT = N->getValueType(0);
985 // fold (udiv c1, c2) -> c1/c2
986 if (N0C && N1C && !N1C->isNullValue())
987 return DAG.getNode(ISD::UDIV, VT, N0, N1);
988 // fold (udiv x, (1 << c)) -> x >>u c
989 if (N1C && isPowerOf2_64(N1C->getValue()))
990 return DAG.getNode(ISD::SRL, VT, N0,
991 DAG.getConstant(Log2_64(N1C->getValue()),
992 TLI.getShiftAmountTy()));
993 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
994 if (N1.getOpcode() == ISD::SHL) {
995 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
996 if (isPowerOf2_64(SHC->getValue())) {
997 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
998 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
999 DAG.getConstant(Log2_64(SHC->getValue()),
1001 AddToWorkList(Add.Val);
1002 return DAG.getNode(ISD::SRL, VT, N0, Add);
1006 // fold (udiv x, c) -> alternate
1007 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1008 SDOperand Op = BuildUDIV(N);
1009 if (Op.Val) return Op;
1014 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1015 SDOperand N0 = N->getOperand(0);
1016 SDOperand N1 = N->getOperand(1);
1017 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1018 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1019 MVT::ValueType VT = N->getValueType(0);
1021 // fold (srem c1, c2) -> c1%c2
1022 if (N0C && N1C && !N1C->isNullValue())
1023 return DAG.getNode(ISD::SREM, VT, N0, N1);
1024 // If we know the sign bits of both operands are zero, strength reduce to a
1025 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1026 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1027 if (TLI.MaskedValueIsZero(N1, SignBit) &&
1028 TLI.MaskedValueIsZero(N0, SignBit))
1029 return DAG.getNode(ISD::UREM, VT, N0, N1);
1031 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1032 // the remainder operation.
1033 if (N1C && !N1C->isNullValue()) {
1034 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1035 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1036 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1037 AddToWorkList(Div.Val);
1038 AddToWorkList(Mul.Val);
1045 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1046 SDOperand N0 = N->getOperand(0);
1047 SDOperand N1 = N->getOperand(1);
1048 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1049 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1050 MVT::ValueType VT = N->getValueType(0);
1052 // fold (urem c1, c2) -> c1%c2
1053 if (N0C && N1C && !N1C->isNullValue())
1054 return DAG.getNode(ISD::UREM, VT, N0, N1);
1055 // fold (urem x, pow2) -> (and x, pow2-1)
1056 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1057 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1058 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1059 if (N1.getOpcode() == ISD::SHL) {
1060 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1061 if (isPowerOf2_64(SHC->getValue())) {
1062 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1063 AddToWorkList(Add.Val);
1064 return DAG.getNode(ISD::AND, VT, N0, Add);
1069 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1070 // the remainder operation.
1071 if (N1C && !N1C->isNullValue()) {
1072 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1073 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1074 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1075 AddToWorkList(Div.Val);
1076 AddToWorkList(Mul.Val);
1083 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1084 SDOperand N0 = N->getOperand(0);
1085 SDOperand N1 = N->getOperand(1);
1086 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1088 // fold (mulhs x, 0) -> 0
1089 if (N1C && N1C->isNullValue())
1091 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1092 if (N1C && N1C->getValue() == 1)
1093 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1094 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1095 TLI.getShiftAmountTy()));
1099 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1100 SDOperand N0 = N->getOperand(0);
1101 SDOperand N1 = N->getOperand(1);
1102 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1104 // fold (mulhu x, 0) -> 0
1105 if (N1C && N1C->isNullValue())
1107 // fold (mulhu x, 1) -> 0
1108 if (N1C && N1C->getValue() == 1)
1109 return DAG.getConstant(0, N0.getValueType());
1113 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1114 /// two operands of the same opcode, try to simplify it.
1115 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1116 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1117 MVT::ValueType VT = N0.getValueType();
1118 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1120 // For each of OP in AND/OR/XOR:
1121 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1122 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1123 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1124 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1125 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1126 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1127 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1128 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1129 N0.getOperand(0).getValueType(),
1130 N0.getOperand(0), N1.getOperand(0));
1131 AddToWorkList(ORNode.Val);
1132 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1135 // For each of OP in SHL/SRL/SRA/AND...
1136 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1137 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1138 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1139 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1140 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1141 N0.getOperand(1) == N1.getOperand(1)) {
1142 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1143 N0.getOperand(0).getValueType(),
1144 N0.getOperand(0), N1.getOperand(0));
1145 AddToWorkList(ORNode.Val);
1146 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1152 SDOperand DAGCombiner::visitAND(SDNode *N) {
1153 SDOperand N0 = N->getOperand(0);
1154 SDOperand N1 = N->getOperand(1);
1155 SDOperand LL, LR, RL, RR, CC0, CC1;
1156 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1157 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1158 MVT::ValueType VT = N1.getValueType();
1160 // fold (and c1, c2) -> c1&c2
1162 return DAG.getNode(ISD::AND, VT, N0, N1);
1163 // canonicalize constant to RHS
1165 return DAG.getNode(ISD::AND, VT, N1, N0);
1166 // fold (and x, -1) -> x
1167 if (N1C && N1C->isAllOnesValue())
1169 // if (and x, c) is known to be zero, return 0
1170 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1171 return DAG.getConstant(0, VT);
1173 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1176 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1177 if (N1C && N0.getOpcode() == ISD::OR)
1178 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1179 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1181 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1182 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1183 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1184 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1185 ~N1C->getValue() & InMask)) {
1186 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1189 // Replace uses of the AND with uses of the Zero extend node.
1192 // We actually want to replace all uses of the any_extend with the
1193 // zero_extend, to avoid duplicating things. This will later cause this
1194 // AND to be folded.
1195 CombineTo(N0.Val, Zext);
1196 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1199 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1200 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1201 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1202 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1204 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1205 MVT::isInteger(LL.getValueType())) {
1206 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1207 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1208 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1209 AddToWorkList(ORNode.Val);
1210 return DAG.getSetCC(VT, ORNode, LR, Op1);
1212 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1213 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1214 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1215 AddToWorkList(ANDNode.Val);
1216 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1218 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1219 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1220 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1221 AddToWorkList(ORNode.Val);
1222 return DAG.getSetCC(VT, ORNode, LR, Op1);
1225 // canonicalize equivalent to ll == rl
1226 if (LL == RR && LR == RL) {
1227 Op1 = ISD::getSetCCSwappedOperands(Op1);
1230 if (LL == RL && LR == RR) {
1231 bool isInteger = MVT::isInteger(LL.getValueType());
1232 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1233 if (Result != ISD::SETCC_INVALID)
1234 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1238 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1239 if (N0.getOpcode() == N1.getOpcode()) {
1240 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1241 if (Tmp.Val) return Tmp;
1244 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1245 // fold (and (sra)) -> (and (srl)) when possible.
1246 if (!MVT::isVector(VT) &&
1247 SimplifyDemandedBits(SDOperand(N, 0)))
1248 return SDOperand(N, 0);
1249 // fold (zext_inreg (extload x)) -> (zextload x)
1250 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
1251 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1252 MVT::ValueType EVT = LN0->getLoadedVT();
1253 // If we zero all the possible extended bits, then we can turn this into
1254 // a zextload if we are running before legalize or the operation is legal.
1255 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1256 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1257 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1258 LN0->getBasePtr(), LN0->getSrcValue(),
1259 LN0->getSrcValueOffset(), EVT);
1261 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1262 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1265 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1266 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
1268 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1269 MVT::ValueType EVT = LN0->getLoadedVT();
1270 // If we zero all the possible extended bits, then we can turn this into
1271 // a zextload if we are running before legalize or the operation is legal.
1272 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1273 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1274 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1275 LN0->getBasePtr(), LN0->getSrcValue(),
1276 LN0->getSrcValueOffset(), EVT);
1278 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1279 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1283 // fold (and (load x), 255) -> (zextload x, i8)
1284 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1285 if (N1C && N0.getOpcode() == ISD::LOAD) {
1286 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1287 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1288 LN0->getAddressingMode() == ISD::UNINDEXED &&
1290 MVT::ValueType EVT, LoadedVT;
1291 if (N1C->getValue() == 255)
1293 else if (N1C->getValue() == 65535)
1295 else if (N1C->getValue() == ~0U)
1300 LoadedVT = LN0->getLoadedVT();
1301 if (EVT != MVT::Other && LoadedVT > EVT &&
1302 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1303 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1304 // For big endian targets, we need to add an offset to the pointer to
1305 // load the correct bytes. For little endian systems, we merely need to
1306 // read fewer bytes from the same pointer.
1308 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1309 SDOperand NewPtr = LN0->getBasePtr();
1310 if (!TLI.isLittleEndian())
1311 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1312 DAG.getConstant(PtrOff, PtrType));
1313 AddToWorkList(NewPtr.Val);
1315 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1316 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
1318 CombineTo(N0.Val, Load, Load.getValue(1));
1319 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1327 SDOperand DAGCombiner::visitOR(SDNode *N) {
1328 SDOperand N0 = N->getOperand(0);
1329 SDOperand N1 = N->getOperand(1);
1330 SDOperand LL, LR, RL, RR, CC0, CC1;
1331 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1332 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1333 MVT::ValueType VT = N1.getValueType();
1334 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1336 // fold (or c1, c2) -> c1|c2
1338 return DAG.getNode(ISD::OR, VT, N0, N1);
1339 // canonicalize constant to RHS
1341 return DAG.getNode(ISD::OR, VT, N1, N0);
1342 // fold (or x, 0) -> x
1343 if (N1C && N1C->isNullValue())
1345 // fold (or x, -1) -> -1
1346 if (N1C && N1C->isAllOnesValue())
1348 // fold (or x, c) -> c iff (x & ~c) == 0
1350 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1353 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1356 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1357 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1358 isa<ConstantSDNode>(N0.getOperand(1))) {
1359 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1360 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1362 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1364 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1365 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1366 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1367 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1369 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1370 MVT::isInteger(LL.getValueType())) {
1371 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1372 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1373 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1374 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1375 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1376 AddToWorkList(ORNode.Val);
1377 return DAG.getSetCC(VT, ORNode, LR, Op1);
1379 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1380 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1381 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1382 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1383 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1384 AddToWorkList(ANDNode.Val);
1385 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1388 // canonicalize equivalent to ll == rl
1389 if (LL == RR && LR == RL) {
1390 Op1 = ISD::getSetCCSwappedOperands(Op1);
1393 if (LL == RL && LR == RR) {
1394 bool isInteger = MVT::isInteger(LL.getValueType());
1395 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1396 if (Result != ISD::SETCC_INVALID)
1397 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1401 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1402 if (N0.getOpcode() == N1.getOpcode()) {
1403 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1404 if (Tmp.Val) return Tmp;
1407 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1408 if (N0.getOpcode() == ISD::AND &&
1409 N1.getOpcode() == ISD::AND &&
1410 N0.getOperand(1).getOpcode() == ISD::Constant &&
1411 N1.getOperand(1).getOpcode() == ISD::Constant &&
1412 // Don't increase # computations.
1413 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1414 // We can only do this xform if we know that bits from X that are set in C2
1415 // but not in C1 are already zero. Likewise for Y.
1416 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1417 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1419 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1420 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1421 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1422 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1427 // See if this is some rotate idiom.
1428 if (SDNode *Rot = MatchRotate(N0, N1))
1429 return SDOperand(Rot, 0);
1435 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1436 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1437 if (Op.getOpcode() == ISD::AND) {
1438 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1439 Mask = Op.getOperand(1);
1440 Op = Op.getOperand(0);
1446 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1454 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1455 // idioms for rotate, and if the target supports rotation instructions, generate
1457 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1458 // Must be a legal type. Expanded an promoted things won't work with rotates.
1459 MVT::ValueType VT = LHS.getValueType();
1460 if (!TLI.isTypeLegal(VT)) return 0;
1462 // The target must have at least one rotate flavor.
1463 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1464 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1465 if (!HasROTL && !HasROTR) return 0;
1467 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1468 SDOperand LHSShift; // The shift.
1469 SDOperand LHSMask; // AND value if any.
1470 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1471 return 0; // Not part of a rotate.
1473 SDOperand RHSShift; // The shift.
1474 SDOperand RHSMask; // AND value if any.
1475 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1476 return 0; // Not part of a rotate.
1478 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1479 return 0; // Not shifting the same value.
1481 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1482 return 0; // Shifts must disagree.
1484 // Canonicalize shl to left side in a shl/srl pair.
1485 if (RHSShift.getOpcode() == ISD::SHL) {
1486 std::swap(LHS, RHS);
1487 std::swap(LHSShift, RHSShift);
1488 std::swap(LHSMask , RHSMask );
1491 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1492 SDOperand LHSShiftArg = LHSShift.getOperand(0);
1493 SDOperand LHSShiftAmt = LHSShift.getOperand(1);
1494 SDOperand RHSShiftAmt = RHSShift.getOperand(1);
1496 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1497 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1498 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
1499 RHSShiftAmt.getOpcode() == ISD::Constant) {
1500 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
1501 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
1502 if ((LShVal + RShVal) != OpSizeInBits)
1507 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
1509 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
1511 // If there is an AND of either shifted operand, apply it to the result.
1512 if (LHSMask.Val || RHSMask.Val) {
1513 uint64_t Mask = MVT::getIntVTBitMask(VT);
1516 uint64_t RHSBits = (1ULL << LShVal)-1;
1517 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1520 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1521 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1524 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1530 // If there is a mask here, and we have a variable shift, we can't be sure
1531 // that we're masking out the right stuff.
1532 if (LHSMask.Val || RHSMask.Val)
1535 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1536 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1537 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
1538 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
1539 if (ConstantSDNode *SUBC =
1540 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
1541 if (SUBC->getValue() == OpSizeInBits)
1543 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1545 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1549 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1550 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1551 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
1552 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
1553 if (ConstantSDNode *SUBC =
1554 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
1555 if (SUBC->getValue() == OpSizeInBits)
1557 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1559 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1563 // Look for sign/zext/any-extended cases:
1564 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1565 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1566 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
1567 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1568 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1569 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
1570 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
1571 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
1572 if (RExtOp0.getOpcode() == ISD::SUB &&
1573 RExtOp0.getOperand(1) == LExtOp0) {
1574 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1576 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1577 // (rotl x, (sub 32, y))
1578 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
1579 if (SUBC->getValue() == OpSizeInBits) {
1581 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1583 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1586 } else if (LExtOp0.getOpcode() == ISD::SUB &&
1587 RExtOp0 == LExtOp0.getOperand(1)) {
1588 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
1590 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
1591 // (rotr x, (sub 32, y))
1592 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
1593 if (SUBC->getValue() == OpSizeInBits) {
1595 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
1597 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1607 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1608 SDOperand N0 = N->getOperand(0);
1609 SDOperand N1 = N->getOperand(1);
1610 SDOperand LHS, RHS, CC;
1611 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1612 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1613 MVT::ValueType VT = N0.getValueType();
1615 // fold (xor c1, c2) -> c1^c2
1617 return DAG.getNode(ISD::XOR, VT, N0, N1);
1618 // canonicalize constant to RHS
1620 return DAG.getNode(ISD::XOR, VT, N1, N0);
1621 // fold (xor x, 0) -> x
1622 if (N1C && N1C->isNullValue())
1625 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1628 // fold !(x cc y) -> (x !cc y)
1629 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1630 bool isInt = MVT::isInteger(LHS.getValueType());
1631 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1633 if (N0.getOpcode() == ISD::SETCC)
1634 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1635 if (N0.getOpcode() == ISD::SELECT_CC)
1636 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1637 assert(0 && "Unhandled SetCC Equivalent!");
1640 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1641 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
1642 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1643 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1644 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1645 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1646 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1647 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1648 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1649 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1652 // fold !(x or y) -> (!x and !y) iff x or y are constants
1653 if (N1C && N1C->isAllOnesValue() &&
1654 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1655 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1656 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1657 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1658 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1659 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1660 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1661 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1664 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1665 if (N1C && N0.getOpcode() == ISD::XOR) {
1666 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1667 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1669 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1670 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1672 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1673 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1675 // fold (xor x, x) -> 0
1677 if (!MVT::isVector(VT)) {
1678 return DAG.getConstant(0, VT);
1679 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1680 // Produce a vector of zeros.
1681 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1682 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1683 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1687 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1688 if (N0.getOpcode() == N1.getOpcode()) {
1689 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1690 if (Tmp.Val) return Tmp;
1693 // Simplify the expression using non-local knowledge.
1694 if (!MVT::isVector(VT) &&
1695 SimplifyDemandedBits(SDOperand(N, 0)))
1696 return SDOperand(N, 0);
1701 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1702 SDOperand N0 = N->getOperand(0);
1703 SDOperand N1 = N->getOperand(1);
1704 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1705 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1706 MVT::ValueType VT = N0.getValueType();
1707 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1709 // fold (shl c1, c2) -> c1<<c2
1711 return DAG.getNode(ISD::SHL, VT, N0, N1);
1712 // fold (shl 0, x) -> 0
1713 if (N0C && N0C->isNullValue())
1715 // fold (shl x, c >= size(x)) -> undef
1716 if (N1C && N1C->getValue() >= OpSizeInBits)
1717 return DAG.getNode(ISD::UNDEF, VT);
1718 // fold (shl x, 0) -> x
1719 if (N1C && N1C->isNullValue())
1721 // if (shl x, c) is known to be zero, return 0
1722 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1723 return DAG.getConstant(0, VT);
1724 if (SimplifyDemandedBits(SDOperand(N, 0)))
1725 return SDOperand(N, 0);
1726 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1727 if (N1C && N0.getOpcode() == ISD::SHL &&
1728 N0.getOperand(1).getOpcode() == ISD::Constant) {
1729 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1730 uint64_t c2 = N1C->getValue();
1731 if (c1 + c2 > OpSizeInBits)
1732 return DAG.getConstant(0, VT);
1733 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1734 DAG.getConstant(c1 + c2, N1.getValueType()));
1736 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1737 // (srl (and x, -1 << c1), c1-c2)
1738 if (N1C && N0.getOpcode() == ISD::SRL &&
1739 N0.getOperand(1).getOpcode() == ISD::Constant) {
1740 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1741 uint64_t c2 = N1C->getValue();
1742 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1743 DAG.getConstant(~0ULL << c1, VT));
1745 return DAG.getNode(ISD::SHL, VT, Mask,
1746 DAG.getConstant(c2-c1, N1.getValueType()));
1748 return DAG.getNode(ISD::SRL, VT, Mask,
1749 DAG.getConstant(c1-c2, N1.getValueType()));
1751 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1752 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1753 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1754 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1758 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1759 SDOperand N0 = N->getOperand(0);
1760 SDOperand N1 = N->getOperand(1);
1761 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1762 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1763 MVT::ValueType VT = N0.getValueType();
1765 // fold (sra c1, c2) -> c1>>c2
1767 return DAG.getNode(ISD::SRA, VT, N0, N1);
1768 // fold (sra 0, x) -> 0
1769 if (N0C && N0C->isNullValue())
1771 // fold (sra -1, x) -> -1
1772 if (N0C && N0C->isAllOnesValue())
1774 // fold (sra x, c >= size(x)) -> undef
1775 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1776 return DAG.getNode(ISD::UNDEF, VT);
1777 // fold (sra x, 0) -> x
1778 if (N1C && N1C->isNullValue())
1780 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1782 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1783 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1786 default: EVT = MVT::Other; break;
1787 case 1: EVT = MVT::i1; break;
1788 case 8: EVT = MVT::i8; break;
1789 case 16: EVT = MVT::i16; break;
1790 case 32: EVT = MVT::i32; break;
1792 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1793 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1794 DAG.getValueType(EVT));
1797 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1798 if (N1C && N0.getOpcode() == ISD::SRA) {
1799 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1800 unsigned Sum = N1C->getValue() + C1->getValue();
1801 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1802 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1803 DAG.getConstant(Sum, N1C->getValueType(0)));
1807 // Simplify, based on bits shifted out of the LHS.
1808 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1809 return SDOperand(N, 0);
1812 // If the sign bit is known to be zero, switch this to a SRL.
1813 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1814 return DAG.getNode(ISD::SRL, VT, N0, N1);
1818 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1819 SDOperand N0 = N->getOperand(0);
1820 SDOperand N1 = N->getOperand(1);
1821 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1822 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1823 MVT::ValueType VT = N0.getValueType();
1824 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1826 // fold (srl c1, c2) -> c1 >>u c2
1828 return DAG.getNode(ISD::SRL, VT, N0, N1);
1829 // fold (srl 0, x) -> 0
1830 if (N0C && N0C->isNullValue())
1832 // fold (srl x, c >= size(x)) -> undef
1833 if (N1C && N1C->getValue() >= OpSizeInBits)
1834 return DAG.getNode(ISD::UNDEF, VT);
1835 // fold (srl x, 0) -> x
1836 if (N1C && N1C->isNullValue())
1838 // if (srl x, c) is known to be zero, return 0
1839 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1840 return DAG.getConstant(0, VT);
1841 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1842 if (N1C && N0.getOpcode() == ISD::SRL &&
1843 N0.getOperand(1).getOpcode() == ISD::Constant) {
1844 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1845 uint64_t c2 = N1C->getValue();
1846 if (c1 + c2 > OpSizeInBits)
1847 return DAG.getConstant(0, VT);
1848 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1849 DAG.getConstant(c1 + c2, N1.getValueType()));
1852 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1853 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1854 // Shifting in all undef bits?
1855 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1856 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1857 return DAG.getNode(ISD::UNDEF, VT);
1859 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1860 AddToWorkList(SmallShift.Val);
1861 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1864 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
1865 // bit, which is unmodified by sra.
1866 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
1867 if (N0.getOpcode() == ISD::SRA)
1868 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
1871 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1872 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1873 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1874 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1875 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1877 // If any of the input bits are KnownOne, then the input couldn't be all
1878 // zeros, thus the result of the srl will always be zero.
1879 if (KnownOne) return DAG.getConstant(0, VT);
1881 // If all of the bits input the to ctlz node are known to be zero, then
1882 // the result of the ctlz is "32" and the result of the shift is one.
1883 uint64_t UnknownBits = ~KnownZero & Mask;
1884 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1886 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1887 if ((UnknownBits & (UnknownBits-1)) == 0) {
1888 // Okay, we know that only that the single bit specified by UnknownBits
1889 // could be set on input to the CTLZ node. If this bit is set, the SRL
1890 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1891 // to an SRL,XOR pair, which is likely to simplify more.
1892 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1893 SDOperand Op = N0.getOperand(0);
1895 Op = DAG.getNode(ISD::SRL, VT, Op,
1896 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1897 AddToWorkList(Op.Val);
1899 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1906 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1907 SDOperand N0 = N->getOperand(0);
1908 MVT::ValueType VT = N->getValueType(0);
1910 // fold (ctlz c1) -> c2
1911 if (isa<ConstantSDNode>(N0))
1912 return DAG.getNode(ISD::CTLZ, VT, N0);
1916 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1917 SDOperand N0 = N->getOperand(0);
1918 MVT::ValueType VT = N->getValueType(0);
1920 // fold (cttz c1) -> c2
1921 if (isa<ConstantSDNode>(N0))
1922 return DAG.getNode(ISD::CTTZ, VT, N0);
1926 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1927 SDOperand N0 = N->getOperand(0);
1928 MVT::ValueType VT = N->getValueType(0);
1930 // fold (ctpop c1) -> c2
1931 if (isa<ConstantSDNode>(N0))
1932 return DAG.getNode(ISD::CTPOP, VT, N0);
1936 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1937 SDOperand N0 = N->getOperand(0);
1938 SDOperand N1 = N->getOperand(1);
1939 SDOperand N2 = N->getOperand(2);
1940 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1941 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1942 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1943 MVT::ValueType VT = N->getValueType(0);
1945 // fold select C, X, X -> X
1948 // fold select true, X, Y -> X
1949 if (N0C && !N0C->isNullValue())
1951 // fold select false, X, Y -> Y
1952 if (N0C && N0C->isNullValue())
1954 // fold select C, 1, X -> C | X
1955 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1956 return DAG.getNode(ISD::OR, VT, N0, N2);
1957 // fold select C, 0, X -> ~C & X
1958 // FIXME: this should check for C type == X type, not i1?
1959 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1960 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1961 AddToWorkList(XORNode.Val);
1962 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1964 // fold select C, X, 1 -> ~C | X
1965 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1966 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1967 AddToWorkList(XORNode.Val);
1968 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1970 // fold select C, X, 0 -> C & X
1971 // FIXME: this should check for C type == X type, not i1?
1972 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1973 return DAG.getNode(ISD::AND, VT, N0, N1);
1974 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1975 if (MVT::i1 == VT && N0 == N1)
1976 return DAG.getNode(ISD::OR, VT, N0, N2);
1977 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1978 if (MVT::i1 == VT && N0 == N2)
1979 return DAG.getNode(ISD::AND, VT, N0, N1);
1981 // If we can fold this based on the true/false value, do so.
1982 if (SimplifySelectOps(N, N1, N2))
1983 return SDOperand(N, 0); // Don't revisit N.
1985 // fold selects based on a setcc into other things, such as min/max/abs
1986 if (N0.getOpcode() == ISD::SETCC)
1988 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1989 // having to say they don't support SELECT_CC on every type the DAG knows
1990 // about, since there is no way to mark an opcode illegal at all value types
1991 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1992 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1993 N1, N2, N0.getOperand(2));
1995 return SimplifySelect(N0, N1, N2);
1999 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
2000 SDOperand N0 = N->getOperand(0);
2001 SDOperand N1 = N->getOperand(1);
2002 SDOperand N2 = N->getOperand(2);
2003 SDOperand N3 = N->getOperand(3);
2004 SDOperand N4 = N->getOperand(4);
2005 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2007 // fold select_cc lhs, rhs, x, x, cc -> x
2011 // Determine if the condition we're dealing with is constant
2012 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2013 if (SCC.Val) AddToWorkList(SCC.Val);
2015 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
2016 if (SCCC->getValue())
2017 return N2; // cond always true -> true val
2019 return N3; // cond always false -> false val
2022 // Fold to a simpler select_cc
2023 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2024 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
2025 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2028 // If we can fold this based on the true/false value, do so.
2029 if (SimplifySelectOps(N, N2, N3))
2030 return SDOperand(N, 0); // Don't revisit N.
2032 // fold select_cc into other things, such as min/max/abs
2033 return SimplifySelectCC(N0, N1, N2, N3, CC);
2036 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
2037 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2038 cast<CondCodeSDNode>(N->getOperand(2))->get());
2041 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2042 SDOperand N0 = N->getOperand(0);
2043 MVT::ValueType VT = N->getValueType(0);
2045 // fold (sext c1) -> c1
2046 if (isa<ConstantSDNode>(N0))
2047 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2049 // fold (sext (sext x)) -> (sext x)
2050 // fold (sext (aext x)) -> (sext x)
2051 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2052 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2054 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2055 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2056 if (N0.getOpcode() == ISD::TRUNCATE) {
2057 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2058 if (NarrowLoad.Val) {
2059 if (NarrowLoad.Val != N0.Val)
2060 CombineTo(N0.Val, NarrowLoad);
2061 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
2065 // See if the value being truncated is already sign extended. If so, just
2066 // eliminate the trunc/sext pair.
2067 if (N0.getOpcode() == ISD::TRUNCATE) {
2068 SDOperand Op = N0.getOperand(0);
2069 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2070 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2071 unsigned DestBits = MVT::getSizeInBits(VT);
2072 unsigned NumSignBits = TLI.ComputeNumSignBits(Op);
2074 if (OpBits == DestBits) {
2075 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2076 // bits, it is already ready.
2077 if (NumSignBits > DestBits-MidBits)
2079 } else if (OpBits < DestBits) {
2080 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2081 // bits, just sext from i32.
2082 if (NumSignBits > OpBits-MidBits)
2083 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2085 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2086 // bits, just truncate to i32.
2087 if (NumSignBits > OpBits-MidBits)
2088 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2091 // fold (sext (truncate x)) -> (sextinreg x).
2092 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2093 N0.getValueType())) {
2094 if (Op.getValueType() < VT)
2095 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2096 else if (Op.getValueType() > VT)
2097 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2098 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2099 DAG.getValueType(N0.getValueType()));
2103 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2104 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2105 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2106 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2107 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2108 LN0->getBasePtr(), LN0->getSrcValue(),
2109 LN0->getSrcValueOffset(),
2111 CombineTo(N, ExtLoad);
2112 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2113 ExtLoad.getValue(1));
2114 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2117 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2118 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2119 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2120 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2121 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2122 MVT::ValueType EVT = LN0->getLoadedVT();
2123 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2124 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2125 LN0->getBasePtr(), LN0->getSrcValue(),
2126 LN0->getSrcValueOffset(), EVT);
2127 CombineTo(N, ExtLoad);
2128 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2129 ExtLoad.getValue(1));
2130 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2134 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
2135 if (N0.getOpcode() == ISD::SETCC) {
2137 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2138 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
2139 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2140 if (SCC.Val) return SCC;
2146 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2147 SDOperand N0 = N->getOperand(0);
2148 MVT::ValueType VT = N->getValueType(0);
2150 // fold (zext c1) -> c1
2151 if (isa<ConstantSDNode>(N0))
2152 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2153 // fold (zext (zext x)) -> (zext x)
2154 // fold (zext (aext x)) -> (zext x)
2155 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2156 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2158 // fold (zext (truncate (load x))) -> (zext (smaller load x))
2159 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
2160 if (N0.getOpcode() == ISD::TRUNCATE) {
2161 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2162 if (NarrowLoad.Val) {
2163 if (NarrowLoad.Val != N0.Val)
2164 CombineTo(N0.Val, NarrowLoad);
2165 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
2169 // fold (zext (truncate x)) -> (and x, mask)
2170 if (N0.getOpcode() == ISD::TRUNCATE &&
2171 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2172 SDOperand Op = N0.getOperand(0);
2173 if (Op.getValueType() < VT) {
2174 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2175 } else if (Op.getValueType() > VT) {
2176 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2178 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2181 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2182 if (N0.getOpcode() == ISD::AND &&
2183 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2184 N0.getOperand(1).getOpcode() == ISD::Constant) {
2185 SDOperand X = N0.getOperand(0).getOperand(0);
2186 if (X.getValueType() < VT) {
2187 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2188 } else if (X.getValueType() > VT) {
2189 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2191 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2192 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2195 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2196 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2197 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2198 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2199 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2200 LN0->getBasePtr(), LN0->getSrcValue(),
2201 LN0->getSrcValueOffset(),
2203 CombineTo(N, ExtLoad);
2204 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2205 ExtLoad.getValue(1));
2206 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2209 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2210 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2211 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2212 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2213 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2214 MVT::ValueType EVT = LN0->getLoadedVT();
2215 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2216 LN0->getBasePtr(), LN0->getSrcValue(),
2217 LN0->getSrcValueOffset(), EVT);
2218 CombineTo(N, ExtLoad);
2219 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2220 ExtLoad.getValue(1));
2221 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2224 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2225 if (N0.getOpcode() == ISD::SETCC) {
2227 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2228 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2229 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2230 if (SCC.Val) return SCC;
2236 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2237 SDOperand N0 = N->getOperand(0);
2238 MVT::ValueType VT = N->getValueType(0);
2240 // fold (aext c1) -> c1
2241 if (isa<ConstantSDNode>(N0))
2242 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2243 // fold (aext (aext x)) -> (aext x)
2244 // fold (aext (zext x)) -> (zext x)
2245 // fold (aext (sext x)) -> (sext x)
2246 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2247 N0.getOpcode() == ISD::ZERO_EXTEND ||
2248 N0.getOpcode() == ISD::SIGN_EXTEND)
2249 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2251 // fold (aext (truncate (load x))) -> (aext (smaller load x))
2252 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
2253 if (N0.getOpcode() == ISD::TRUNCATE) {
2254 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2255 if (NarrowLoad.Val) {
2256 if (NarrowLoad.Val != N0.Val)
2257 CombineTo(N0.Val, NarrowLoad);
2258 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
2262 // fold (aext (truncate x))
2263 if (N0.getOpcode() == ISD::TRUNCATE) {
2264 SDOperand TruncOp = N0.getOperand(0);
2265 if (TruncOp.getValueType() == VT)
2266 return TruncOp; // x iff x size == zext size.
2267 if (TruncOp.getValueType() > VT)
2268 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2269 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2272 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2273 if (N0.getOpcode() == ISD::AND &&
2274 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2275 N0.getOperand(1).getOpcode() == ISD::Constant) {
2276 SDOperand X = N0.getOperand(0).getOperand(0);
2277 if (X.getValueType() < VT) {
2278 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2279 } else if (X.getValueType() > VT) {
2280 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2282 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2283 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2286 // fold (aext (load x)) -> (aext (truncate (extload x)))
2287 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2288 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2289 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2290 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2291 LN0->getBasePtr(), LN0->getSrcValue(),
2292 LN0->getSrcValueOffset(),
2294 CombineTo(N, ExtLoad);
2295 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2296 ExtLoad.getValue(1));
2297 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2300 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2301 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2302 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2303 if (N0.getOpcode() == ISD::LOAD &&
2304 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2306 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2307 MVT::ValueType EVT = LN0->getLoadedVT();
2308 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2309 LN0->getChain(), LN0->getBasePtr(),
2311 LN0->getSrcValueOffset(), EVT);
2312 CombineTo(N, ExtLoad);
2313 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2314 ExtLoad.getValue(1));
2315 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2318 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2319 if (N0.getOpcode() == ISD::SETCC) {
2321 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2322 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2323 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2331 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
2332 /// bits and then truncated to a narrower type and where N is a multiple
2333 /// of number of bits of the narrower type, transform it to a narrower load
2334 /// from address + N / num of bits of new type. If the result is to be
2335 /// extended, also fold the extension to form a extending load.
2336 SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
2337 unsigned Opc = N->getOpcode();
2338 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2339 SDOperand N0 = N->getOperand(0);
2340 MVT::ValueType VT = N->getValueType(0);
2341 MVT::ValueType EVT = N->getValueType(0);
2343 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
2345 if (Opc == ISD::SIGN_EXTEND_INREG) {
2346 ExtType = ISD::SEXTLOAD;
2347 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2348 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
2352 unsigned EVTBits = MVT::getSizeInBits(EVT);
2354 bool CombineSRL = false;
2355 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
2356 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2357 ShAmt = N01->getValue();
2358 // Is the shift amount a multiple of size of VT?
2359 if ((ShAmt & (EVTBits-1)) == 0) {
2360 N0 = N0.getOperand(0);
2361 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
2368 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2369 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
2370 // zero extended form: by shrinking the load, we lose track of the fact
2371 // that it is already zero extended.
2372 // FIXME: This should be reevaluated.
2374 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
2375 "Cannot truncate to larger type!");
2376 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2377 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2378 // For big endian targets, we need to adjust the offset to the pointer to
2379 // load the correct bytes.
2380 if (!TLI.isLittleEndian())
2381 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits;
2382 uint64_t PtrOff = ShAmt / 8;
2383 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2384 DAG.getConstant(PtrOff, PtrType));
2385 AddToWorkList(NewPtr.Val);
2386 SDOperand Load = (ExtType == ISD::NON_EXTLOAD)
2387 ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
2388 LN0->getSrcValue(), LN0->getSrcValueOffset())
2389 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
2390 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
2393 std::vector<SDNode*> NowDead;
2394 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead);
2395 CombineTo(N->getOperand(0).Val, Load);
2397 CombineTo(N0.Val, Load, Load.getValue(1));
2399 if (Opc == ISD::SIGN_EXTEND_INREG)
2400 return DAG.getNode(Opc, VT, Load, N->getOperand(1));
2402 return DAG.getNode(Opc, VT, Load);
2404 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2411 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2412 SDOperand N0 = N->getOperand(0);
2413 SDOperand N1 = N->getOperand(1);
2414 MVT::ValueType VT = N->getValueType(0);
2415 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2416 unsigned EVTBits = MVT::getSizeInBits(EVT);
2418 // fold (sext_in_reg c1) -> c1
2419 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2420 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2422 // If the input is already sign extended, just drop the extension.
2423 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2426 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2427 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2428 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2429 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2432 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
2433 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2434 return DAG.getZeroExtendInReg(N0, EVT);
2436 // fold operands of sext_in_reg based on knowledge that the top bits are not
2438 if (SimplifyDemandedBits(SDOperand(N, 0)))
2439 return SDOperand(N, 0);
2441 // fold (sext_in_reg (load x)) -> (smaller sextload x)
2442 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
2443 SDOperand NarrowLoad = ReduceLoadWidth(N);
2447 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2448 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2449 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2450 if (N0.getOpcode() == ISD::SRL) {
2451 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2452 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2453 // We can turn this into an SRA iff the input to the SRL is already sign
2455 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
2456 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2457 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2461 // fold (sext_inreg (extload x)) -> (sextload x)
2462 if (ISD::isEXTLoad(N0.Val) &&
2463 ISD::isUNINDEXEDLoad(N0.Val) &&
2464 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2465 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2466 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2467 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2468 LN0->getBasePtr(), LN0->getSrcValue(),
2469 LN0->getSrcValueOffset(), EVT);
2470 CombineTo(N, ExtLoad);
2471 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2472 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2474 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2475 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2477 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2478 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2479 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2480 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2481 LN0->getBasePtr(), LN0->getSrcValue(),
2482 LN0->getSrcValueOffset(), EVT);
2483 CombineTo(N, ExtLoad);
2484 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2485 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2490 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2491 SDOperand N0 = N->getOperand(0);
2492 MVT::ValueType VT = N->getValueType(0);
2495 if (N0.getValueType() == N->getValueType(0))
2497 // fold (truncate c1) -> c1
2498 if (isa<ConstantSDNode>(N0))
2499 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2500 // fold (truncate (truncate x)) -> (truncate x)
2501 if (N0.getOpcode() == ISD::TRUNCATE)
2502 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2503 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2504 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2505 N0.getOpcode() == ISD::ANY_EXTEND) {
2506 if (N0.getOperand(0).getValueType() < VT)
2507 // if the source is smaller than the dest, we still need an extend
2508 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2509 else if (N0.getOperand(0).getValueType() > VT)
2510 // if the source is larger than the dest, than we just need the truncate
2511 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2513 // if the source and dest are the same type, we can drop both the extend
2515 return N0.getOperand(0);
2518 // fold (truncate (load x)) -> (smaller load x)
2519 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
2520 return ReduceLoadWidth(N);
2523 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2524 SDOperand N0 = N->getOperand(0);
2525 MVT::ValueType VT = N->getValueType(0);
2527 // If the input is a constant, let getNode() fold it.
2528 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2529 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2530 if (Res.Val != N) return Res;
2533 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2534 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2536 // fold (conv (load x)) -> (load (conv*)x)
2537 // FIXME: These xforms need to know that the resultant load doesn't need a
2538 // higher alignment than the original!
2539 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2540 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2541 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2542 LN0->getSrcValue(), LN0->getSrcValueOffset());
2544 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2552 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2553 SDOperand N0 = N->getOperand(0);
2554 MVT::ValueType VT = N->getValueType(0);
2556 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2557 // First check to see if this is all constant.
2558 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2559 VT == MVT::Vector) {
2560 bool isSimple = true;
2561 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2562 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2563 N0.getOperand(i).getOpcode() != ISD::Constant &&
2564 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2569 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2570 if (isSimple && !MVT::isVector(DestEltVT)) {
2571 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2578 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2579 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2580 /// destination element value type.
2581 SDOperand DAGCombiner::
2582 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2583 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2585 // If this is already the right type, we're done.
2586 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2588 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2589 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2591 // If this is a conversion of N elements of one type to N elements of another
2592 // type, convert each element. This handles FP<->INT cases.
2593 if (SrcBitSize == DstBitSize) {
2594 SmallVector<SDOperand, 8> Ops;
2595 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2596 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2597 AddToWorkList(Ops.back().Val);
2599 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2600 Ops.push_back(DAG.getValueType(DstEltVT));
2601 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2604 // Otherwise, we're growing or shrinking the elements. To avoid having to
2605 // handle annoying details of growing/shrinking FP values, we convert them to
2607 if (MVT::isFloatingPoint(SrcEltVT)) {
2608 // Convert the input float vector to a int vector where the elements are the
2610 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2611 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2612 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2616 // Now we know the input is an integer vector. If the output is a FP type,
2617 // convert to integer first, then to FP of the right size.
2618 if (MVT::isFloatingPoint(DstEltVT)) {
2619 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2620 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2621 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2623 // Next, convert to FP elements of the same size.
2624 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2627 // Okay, we know the src/dst types are both integers of differing types.
2628 // Handling growing first.
2629 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2630 if (SrcBitSize < DstBitSize) {
2631 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2633 SmallVector<SDOperand, 8> Ops;
2634 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2635 i += NumInputsPerOutput) {
2636 bool isLE = TLI.isLittleEndian();
2637 uint64_t NewBits = 0;
2638 bool EltIsUndef = true;
2639 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2640 // Shift the previously computed bits over.
2641 NewBits <<= SrcBitSize;
2642 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2643 if (Op.getOpcode() == ISD::UNDEF) continue;
2646 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2650 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2652 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2655 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2656 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2657 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2660 // Finally, this must be the case where we are shrinking elements: each input
2661 // turns into multiple outputs.
2662 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2663 SmallVector<SDOperand, 8> Ops;
2664 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2665 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2666 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2667 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2670 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2672 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2673 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2674 OpVal >>= DstBitSize;
2675 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2678 // For big endian targets, swap the order of the pieces of each element.
2679 if (!TLI.isLittleEndian())
2680 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2682 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2683 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2684 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2689 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2690 SDOperand N0 = N->getOperand(0);
2691 SDOperand N1 = N->getOperand(1);
2692 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2693 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2694 MVT::ValueType VT = N->getValueType(0);
2696 // fold (fadd c1, c2) -> c1+c2
2698 return DAG.getNode(ISD::FADD, VT, N0, N1);
2699 // canonicalize constant to RHS
2700 if (N0CFP && !N1CFP)
2701 return DAG.getNode(ISD::FADD, VT, N1, N0);
2702 // fold (A + (-B)) -> A-B
2703 if (N1.getOpcode() == ISD::FNEG)
2704 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2705 // fold ((-A) + B) -> B-A
2706 if (N0.getOpcode() == ISD::FNEG)
2707 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2709 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
2710 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
2711 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
2712 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
2713 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
2718 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2719 SDOperand N0 = N->getOperand(0);
2720 SDOperand N1 = N->getOperand(1);
2721 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2722 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2723 MVT::ValueType VT = N->getValueType(0);
2725 // fold (fsub c1, c2) -> c1-c2
2727 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2728 // fold (A-(-B)) -> A+B
2729 if (N1.getOpcode() == ISD::FNEG)
2730 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2734 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2735 SDOperand N0 = N->getOperand(0);
2736 SDOperand N1 = N->getOperand(1);
2737 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2738 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2739 MVT::ValueType VT = N->getValueType(0);
2741 // fold (fmul c1, c2) -> c1*c2
2743 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2744 // canonicalize constant to RHS
2745 if (N0CFP && !N1CFP)
2746 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2747 // fold (fmul X, 2.0) -> (fadd X, X)
2748 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2749 return DAG.getNode(ISD::FADD, VT, N0, N0);
2751 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
2752 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
2753 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
2754 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
2755 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
2760 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2761 SDOperand N0 = N->getOperand(0);
2762 SDOperand N1 = N->getOperand(1);
2763 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2764 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2765 MVT::ValueType VT = N->getValueType(0);
2767 // fold (fdiv c1, c2) -> c1/c2
2769 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2773 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2774 SDOperand N0 = N->getOperand(0);
2775 SDOperand N1 = N->getOperand(1);
2776 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2777 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2778 MVT::ValueType VT = N->getValueType(0);
2780 // fold (frem c1, c2) -> fmod(c1,c2)
2782 return DAG.getNode(ISD::FREM, VT, N0, N1);
2786 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2787 SDOperand N0 = N->getOperand(0);
2788 SDOperand N1 = N->getOperand(1);
2789 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2790 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2791 MVT::ValueType VT = N->getValueType(0);
2793 if (N0CFP && N1CFP) // Constant fold
2794 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2797 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2798 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2803 u.d = N1CFP->getValue();
2805 return DAG.getNode(ISD::FABS, VT, N0);
2807 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2810 // copysign(fabs(x), y) -> copysign(x, y)
2811 // copysign(fneg(x), y) -> copysign(x, y)
2812 // copysign(copysign(x,z), y) -> copysign(x, y)
2813 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2814 N0.getOpcode() == ISD::FCOPYSIGN)
2815 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2817 // copysign(x, abs(y)) -> abs(x)
2818 if (N1.getOpcode() == ISD::FABS)
2819 return DAG.getNode(ISD::FABS, VT, N0);
2821 // copysign(x, copysign(y,z)) -> copysign(x, z)
2822 if (N1.getOpcode() == ISD::FCOPYSIGN)
2823 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2825 // copysign(x, fp_extend(y)) -> copysign(x, y)
2826 // copysign(x, fp_round(y)) -> copysign(x, y)
2827 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2828 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2835 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2836 SDOperand N0 = N->getOperand(0);
2837 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2838 MVT::ValueType VT = N->getValueType(0);
2840 // fold (sint_to_fp c1) -> c1fp
2842 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2846 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2847 SDOperand N0 = N->getOperand(0);
2848 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2849 MVT::ValueType VT = N->getValueType(0);
2851 // fold (uint_to_fp c1) -> c1fp
2853 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2857 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2858 SDOperand N0 = N->getOperand(0);
2859 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2860 MVT::ValueType VT = N->getValueType(0);
2862 // fold (fp_to_sint c1fp) -> c1
2864 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2868 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2869 SDOperand N0 = N->getOperand(0);
2870 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2871 MVT::ValueType VT = N->getValueType(0);
2873 // fold (fp_to_uint c1fp) -> c1
2875 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2879 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2880 SDOperand N0 = N->getOperand(0);
2881 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2882 MVT::ValueType VT = N->getValueType(0);
2884 // fold (fp_round c1fp) -> c1fp
2886 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2888 // fold (fp_round (fp_extend x)) -> x
2889 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2890 return N0.getOperand(0);
2892 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2893 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2894 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2895 AddToWorkList(Tmp.Val);
2896 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2902 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2903 SDOperand N0 = N->getOperand(0);
2904 MVT::ValueType VT = N->getValueType(0);
2905 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2906 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2908 // fold (fp_round_inreg c1fp) -> c1fp
2910 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2911 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2916 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2917 SDOperand N0 = N->getOperand(0);
2918 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2919 MVT::ValueType VT = N->getValueType(0);
2921 // fold (fp_extend c1fp) -> c1fp
2923 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2925 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2926 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2927 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2928 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2929 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2930 LN0->getBasePtr(), LN0->getSrcValue(),
2931 LN0->getSrcValueOffset(),
2933 CombineTo(N, ExtLoad);
2934 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2935 ExtLoad.getValue(1));
2936 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2943 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2944 SDOperand N0 = N->getOperand(0);
2945 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2946 MVT::ValueType VT = N->getValueType(0);
2948 // fold (fneg c1) -> -c1
2950 return DAG.getNode(ISD::FNEG, VT, N0);
2951 // fold (fneg (sub x, y)) -> (sub y, x)
2952 if (N0.getOpcode() == ISD::SUB)
2953 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2954 // fold (fneg (fneg x)) -> x
2955 if (N0.getOpcode() == ISD::FNEG)
2956 return N0.getOperand(0);
2960 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2961 SDOperand N0 = N->getOperand(0);
2962 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2963 MVT::ValueType VT = N->getValueType(0);
2965 // fold (fabs c1) -> fabs(c1)
2967 return DAG.getNode(ISD::FABS, VT, N0);
2968 // fold (fabs (fabs x)) -> (fabs x)
2969 if (N0.getOpcode() == ISD::FABS)
2970 return N->getOperand(0);
2971 // fold (fabs (fneg x)) -> (fabs x)
2972 // fold (fabs (fcopysign x, y)) -> (fabs x)
2973 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2974 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2979 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2980 SDOperand Chain = N->getOperand(0);
2981 SDOperand N1 = N->getOperand(1);
2982 SDOperand N2 = N->getOperand(2);
2983 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2985 // never taken branch, fold to chain
2986 if (N1C && N1C->isNullValue())
2988 // unconditional branch
2989 if (N1C && N1C->getValue() == 1)
2990 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2991 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2993 if (N1.getOpcode() == ISD::SETCC &&
2994 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2995 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2996 N1.getOperand(0), N1.getOperand(1), N2);
3001 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
3003 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
3004 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
3005 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
3007 // Use SimplifySetCC to simplify SETCC's.
3008 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
3009 if (Simp.Val) AddToWorkList(Simp.Val);
3011 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
3013 // fold br_cc true, dest -> br dest (unconditional branch)
3014 if (SCCC && SCCC->getValue())
3015 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
3017 // fold br_cc false, dest -> unconditional fall through
3018 if (SCCC && SCCC->isNullValue())
3019 return N->getOperand(0);
3021 // fold to a simpler setcc
3022 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
3023 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
3024 Simp.getOperand(2), Simp.getOperand(0),
3025 Simp.getOperand(1), N->getOperand(4));
3030 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
3031 /// pre-indexed load / store when the base pointer is a add or subtract
3032 /// and it has other uses besides the load / store. After the
3033 /// transformation, the new indexed load / store has effectively folded
3034 /// the add / subtract in and all of its other uses are redirected to the
3035 /// new load / store.
3036 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
3043 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3044 if (LD->getAddressingMode() != ISD::UNINDEXED)
3046 VT = LD->getLoadedVT();
3047 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
3048 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
3050 Ptr = LD->getBasePtr();
3051 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3052 if (ST->getAddressingMode() != ISD::UNINDEXED)
3054 VT = ST->getStoredVT();
3055 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
3056 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
3058 Ptr = ST->getBasePtr();
3063 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
3064 // out. There is no reason to make this a preinc/predec.
3065 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
3066 Ptr.Val->hasOneUse())
3069 // Ask the target to do addressing mode selection.
3072 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3073 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
3076 // Try turning it into a pre-indexed load / store except when:
3077 // 1) The base is a frame index.
3078 // 2) If N is a store and the ptr is either the same as or is a
3079 // predecessor of the value being stored.
3080 // 3) Another use of base ptr is a predecessor of N. If ptr is folded
3081 // that would create a cycle.
3082 // 4) All uses are load / store ops that use it as base ptr.
3084 // Check #1. Preinc'ing a frame index would require copying the stack pointer
3085 // (plus the implicit offset) to a register to preinc anyway.
3086 if (isa<FrameIndexSDNode>(BasePtr))
3091 SDOperand Val = cast<StoreSDNode>(N)->getValue();
3092 if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val))
3096 // Now check for #2 and #3.
3097 bool RealUse = false;
3098 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3099 E = Ptr.Val->use_end(); I != E; ++I) {
3103 if (Use->isPredecessor(N))
3106 if (!((Use->getOpcode() == ISD::LOAD &&
3107 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
3108 (Use->getOpcode() == ISD::STORE) &&
3109 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
3117 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
3119 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3122 DOUT << "\nReplacing.4 "; DEBUG(N->dump());
3123 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3125 std::vector<SDNode*> NowDead;
3127 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3129 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3132 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3136 // Nodes can end up on the worklist more than once. Make sure we do
3137 // not process a node that has been replaced.
3138 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3139 removeFromWorkList(NowDead[i]);
3140 // Finally, since the node is now dead, remove it from the graph.
3143 // Replace the uses of Ptr with uses of the updated base value.
3144 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
3146 removeFromWorkList(Ptr.Val);
3147 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3148 removeFromWorkList(NowDead[i]);
3149 DAG.DeleteNode(Ptr.Val);
3154 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
3155 /// add / sub of the base pointer node into a post-indexed load / store.
3156 /// The transformation folded the add / subtract into the new indexed
3157 /// load / store effectively and all of its uses are redirected to the
3158 /// new load / store.
3159 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
3166 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3167 if (LD->getAddressingMode() != ISD::UNINDEXED)
3169 VT = LD->getLoadedVT();
3170 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
3171 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
3173 Ptr = LD->getBasePtr();
3174 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3175 if (ST->getAddressingMode() != ISD::UNINDEXED)
3177 VT = ST->getStoredVT();
3178 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
3179 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
3181 Ptr = ST->getBasePtr();
3186 if (Ptr.Val->hasOneUse())
3189 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3190 E = Ptr.Val->use_end(); I != E; ++I) {
3193 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
3198 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3199 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
3201 std::swap(BasePtr, Offset);
3205 // Try turning it into a post-indexed load / store except when
3206 // 1) All uses are load / store ops that use it as base ptr.
3207 // 2) Op must be independent of N, i.e. Op is neither a predecessor
3208 // nor a successor of N. Otherwise, if Op is folded that would
3212 bool TryNext = false;
3213 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
3214 EE = BasePtr.Val->use_end(); II != EE; ++II) {
3219 // If all the uses are load / store addresses, then don't do the
3221 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
3222 bool RealUse = false;
3223 for (SDNode::use_iterator III = Use->use_begin(),
3224 EEE = Use->use_end(); III != EEE; ++III) {
3225 SDNode *UseUse = *III;
3226 if (!((UseUse->getOpcode() == ISD::LOAD &&
3227 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
3228 (UseUse->getOpcode() == ISD::STORE) &&
3229 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
3243 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
3244 SDOperand Result = isLoad
3245 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
3246 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3249 DOUT << "\nReplacing.5 "; DEBUG(N->dump());
3250 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3252 std::vector<SDNode*> NowDead;
3254 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3256 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3259 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3263 // Nodes can end up on the worklist more than once. Make sure we do
3264 // not process a node that has been replaced.
3265 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3266 removeFromWorkList(NowDead[i]);
3267 // Finally, since the node is now dead, remove it from the graph.
3270 // Replace the uses of Use with uses of the updated base value.
3271 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
3272 Result.getValue(isLoad ? 1 : 0),
3274 removeFromWorkList(Op);
3275 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3276 removeFromWorkList(NowDead[i]);
3287 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
3288 LoadSDNode *LD = cast<LoadSDNode>(N);
3289 SDOperand Chain = LD->getChain();
3290 SDOperand Ptr = LD->getBasePtr();
3292 // If there are no uses of the loaded value, change uses of the chain value
3293 // into uses of the chain input (i.e. delete the dead load).
3294 if (N->hasNUsesOfValue(0, 0))
3295 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
3297 // If this load is directly stored, replace the load value with the stored
3299 // TODO: Handle store large -> read small portion.
3300 // TODO: Handle TRUNCSTORE/LOADEXT
3301 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3302 if (ISD::isNON_TRUNCStore(Chain.Val)) {
3303 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
3304 if (PrevST->getBasePtr() == Ptr &&
3305 PrevST->getValue().getValueType() == N->getValueType(0))
3306 return CombineTo(N, Chain.getOperand(1), Chain);
3311 // Walk up chain skipping non-aliasing memory nodes.
3312 SDOperand BetterChain = FindBetterChain(N, Chain);
3314 // If there is a better chain.
3315 if (Chain != BetterChain) {
3318 // Replace the chain to void dependency.
3319 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3320 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
3321 LD->getSrcValue(), LD->getSrcValueOffset());
3323 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
3324 LD->getValueType(0),
3325 BetterChain, Ptr, LD->getSrcValue(),
3326 LD->getSrcValueOffset(),
3330 // Create token factor to keep old chain connected.
3331 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
3332 Chain, ReplLoad.getValue(1));
3334 // Replace uses with load result and token factor. Don't add users
3336 return CombineTo(N, ReplLoad.getValue(0), Token, false);
3340 // Try transforming N to an indexed load.
3341 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3342 return SDOperand(N, 0);
3347 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
3348 StoreSDNode *ST = cast<StoreSDNode>(N);
3349 SDOperand Chain = ST->getChain();
3350 SDOperand Value = ST->getValue();
3351 SDOperand Ptr = ST->getBasePtr();
3353 // If this is a store of a bit convert, store the input value.
3354 // FIXME: This needs to know that the resultant store does not need a
3355 // higher alignment than the original.
3356 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
3357 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
3358 ST->getSrcValueOffset());
3361 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
3362 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
3363 if (Value.getOpcode() != ISD::TargetConstantFP) {
3365 switch (CFP->getValueType(0)) {
3366 default: assert(0 && "Unknown FP type");
3368 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
3369 Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
3370 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3371 ST->getSrcValueOffset());
3375 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
3376 Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
3377 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3378 ST->getSrcValueOffset());
3379 } else if (TLI.isTypeLegal(MVT::i32)) {
3380 // Many FP stores are not make apparent until after legalize, e.g. for
3381 // argument passing. Since this is so common, custom legalize the
3382 // 64-bit integer store into two 32-bit stores.
3383 uint64_t Val = DoubleToBits(CFP->getValue());
3384 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
3385 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
3386 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
3388 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
3389 ST->getSrcValueOffset());
3390 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3391 DAG.getConstant(4, Ptr.getValueType()));
3392 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
3393 ST->getSrcValueOffset()+4);
3394 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
3402 // Walk up chain skipping non-aliasing memory nodes.
3403 SDOperand BetterChain = FindBetterChain(N, Chain);
3405 // If there is a better chain.
3406 if (Chain != BetterChain) {
3407 // Replace the chain to avoid dependency.
3408 SDOperand ReplStore;
3409 if (ST->isTruncatingStore()) {
3410 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
3411 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT());
3413 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
3414 ST->getSrcValue(), ST->getSrcValueOffset());
3417 // Create token to keep both nodes around.
3419 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
3421 // Don't add users to work list.
3422 return CombineTo(N, Token, false);
3426 // Try transforming N to an indexed store.
3427 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3428 return SDOperand(N, 0);
3433 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
3434 SDOperand InVec = N->getOperand(0);
3435 SDOperand InVal = N->getOperand(1);
3436 SDOperand EltNo = N->getOperand(2);
3438 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
3439 // vector with the inserted element.
3440 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
3441 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3442 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
3443 if (Elt < Ops.size())
3445 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
3446 &Ops[0], Ops.size());
3452 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
3453 SDOperand InVec = N->getOperand(0);
3454 SDOperand InVal = N->getOperand(1);
3455 SDOperand EltNo = N->getOperand(2);
3456 SDOperand NumElts = N->getOperand(3);
3457 SDOperand EltType = N->getOperand(4);
3459 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
3460 // vector with the inserted element.
3461 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
3462 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3463 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
3464 if (Elt < Ops.size()-2)
3466 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
3467 &Ops[0], Ops.size());
3473 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
3474 unsigned NumInScalars = N->getNumOperands()-2;
3475 SDOperand NumElts = N->getOperand(NumInScalars);
3476 SDOperand EltType = N->getOperand(NumInScalars+1);
3478 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
3479 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
3480 // two distinct vectors, turn this into a shuffle node.
3481 SDOperand VecIn1, VecIn2;
3482 for (unsigned i = 0; i != NumInScalars; ++i) {
3483 // Ignore undef inputs.
3484 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3486 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
3487 // constant index, bail out.
3488 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
3489 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
3490 VecIn1 = VecIn2 = SDOperand(0, 0);
3494 // If the input vector type disagrees with the result of the vbuild_vector,
3495 // we can't make a shuffle.
3496 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
3497 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
3498 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
3499 VecIn1 = VecIn2 = SDOperand(0, 0);
3503 // Otherwise, remember this. We allow up to two distinct input vectors.
3504 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
3507 if (VecIn1.Val == 0) {
3508 VecIn1 = ExtractedFromVec;
3509 } else if (VecIn2.Val == 0) {
3510 VecIn2 = ExtractedFromVec;
3513 VecIn1 = VecIn2 = SDOperand(0, 0);
3518 // If everything is good, we can make a shuffle operation.
3520 SmallVector<SDOperand, 8> BuildVecIndices;
3521 for (unsigned i = 0; i != NumInScalars; ++i) {
3522 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
3523 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
3527 SDOperand Extract = N->getOperand(i);
3529 // If extracting from the first vector, just use the index directly.
3530 if (Extract.getOperand(0) == VecIn1) {
3531 BuildVecIndices.push_back(Extract.getOperand(1));
3535 // Otherwise, use InIdx + VecSize
3536 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
3537 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars,
3538 TLI.getPointerTy()));
3541 // Add count and size info.
3542 BuildVecIndices.push_back(NumElts);
3543 BuildVecIndices.push_back(DAG.getValueType(TLI.getPointerTy()));
3545 // Return the new VVECTOR_SHUFFLE node.
3551 // Use an undef vbuild_vector as input for the second operand.
3552 std::vector<SDOperand> UnOps(NumInScalars,
3553 DAG.getNode(ISD::UNDEF,
3554 cast<VTSDNode>(EltType)->getVT()));
3555 UnOps.push_back(NumElts);
3556 UnOps.push_back(EltType);
3557 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3558 &UnOps[0], UnOps.size());
3559 AddToWorkList(Ops[1].Val);
3561 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3562 &BuildVecIndices[0], BuildVecIndices.size());
3565 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
3571 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
3572 SDOperand ShufMask = N->getOperand(2);
3573 unsigned NumElts = ShufMask.getNumOperands();
3575 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3576 bool isIdentity = true;
3577 for (unsigned i = 0; i != NumElts; ++i) {
3578 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3579 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3584 if (isIdentity) return N->getOperand(0);
3586 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3588 for (unsigned i = 0; i != NumElts; ++i) {
3589 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3590 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3595 if (isIdentity) return N->getOperand(1);
3597 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3599 bool isUnary = true;
3600 bool isSplat = true;
3602 unsigned BaseIdx = 0;
3603 for (unsigned i = 0; i != NumElts; ++i)
3604 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3605 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3606 int V = (Idx < NumElts) ? 0 : 1;
3620 SDOperand N0 = N->getOperand(0);
3621 SDOperand N1 = N->getOperand(1);
3622 // Normalize unary shuffle so the RHS is undef.
3623 if (isUnary && VecNum == 1)
3626 // If it is a splat, check if the argument vector is a build_vector with
3627 // all scalar elements the same.
3630 if (V->getOpcode() == ISD::BIT_CONVERT)
3631 V = V->getOperand(0).Val;
3632 if (V->getOpcode() == ISD::BUILD_VECTOR) {
3633 unsigned NumElems = V->getNumOperands()-2;
3634 if (NumElems > BaseIdx) {
3636 bool AllSame = true;
3637 for (unsigned i = 0; i != NumElems; ++i) {
3638 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3639 Base = V->getOperand(i);
3643 // Splat of <u, u, u, u>, return <u, u, u, u>
3646 for (unsigned i = 0; i != NumElems; ++i) {
3647 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3648 V->getOperand(i) != Base) {
3653 // Splat of <x, x, x, x>, return <x, x, x, x>
3660 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3662 if (isUnary || N0 == N1) {
3663 if (N0.getOpcode() == ISD::UNDEF)
3664 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
3665 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3667 SmallVector<SDOperand, 8> MappedOps;
3668 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
3669 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3670 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3671 MappedOps.push_back(ShufMask.getOperand(i));
3674 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3675 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3678 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
3679 &MappedOps[0], MappedOps.size());
3680 AddToWorkList(ShufMask.Val);
3681 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
3683 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
3690 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
3691 SDOperand ShufMask = N->getOperand(2);
3692 unsigned NumElts = ShufMask.getNumOperands()-2;
3694 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3695 bool isIdentity = true;
3696 for (unsigned i = 0; i != NumElts; ++i) {
3697 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3698 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3703 if (isIdentity) return N->getOperand(0);
3705 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3707 for (unsigned i = 0; i != NumElts; ++i) {
3708 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3709 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3714 if (isIdentity) return N->getOperand(1);
3716 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3718 bool isUnary = true;
3719 bool isSplat = true;
3721 unsigned BaseIdx = 0;
3722 for (unsigned i = 0; i != NumElts; ++i)
3723 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3724 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3725 int V = (Idx < NumElts) ? 0 : 1;
3739 SDOperand N0 = N->getOperand(0);
3740 SDOperand N1 = N->getOperand(1);
3741 // Normalize unary shuffle so the RHS is undef.
3742 if (isUnary && VecNum == 1)
3745 // If it is a splat, check if the argument vector is a build_vector with
3746 // all scalar elements the same.
3750 // If this is a vbit convert that changes the element type of the vector but
3751 // not the number of vector elements, look through it. Be careful not to
3752 // look though conversions that change things like v4f32 to v2f64.
3753 if (V->getOpcode() == ISD::VBIT_CONVERT) {
3754 SDOperand ConvInput = V->getOperand(0);
3755 if (ConvInput.getValueType() == MVT::Vector &&
3757 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2))
3761 if (V->getOpcode() == ISD::VBUILD_VECTOR) {
3762 unsigned NumElems = V->getNumOperands()-2;
3763 if (NumElems > BaseIdx) {
3765 bool AllSame = true;
3766 for (unsigned i = 0; i != NumElems; ++i) {
3767 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3768 Base = V->getOperand(i);
3772 // Splat of <u, u, u, u>, return <u, u, u, u>
3775 for (unsigned i = 0; i != NumElems; ++i) {
3776 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3777 V->getOperand(i) != Base) {
3782 // Splat of <x, x, x, x>, return <x, x, x, x>
3789 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3791 if (isUnary || N0 == N1) {
3792 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3794 SmallVector<SDOperand, 8> MappedOps;
3795 for (unsigned i = 0; i != NumElts; ++i) {
3796 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3797 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3798 MappedOps.push_back(ShufMask.getOperand(i));
3801 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3802 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3805 // Add the type/#elts values.
3806 MappedOps.push_back(ShufMask.getOperand(NumElts));
3807 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
3809 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
3810 &MappedOps[0], MappedOps.size());
3811 AddToWorkList(ShufMask.Val);
3813 // Build the undef vector.
3814 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
3815 for (unsigned i = 0; i != NumElts; ++i)
3816 MappedOps[i] = UDVal;
3817 MappedOps[NumElts ] = *(N0.Val->op_end()-2);
3818 MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
3819 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3820 &MappedOps[0], MappedOps.size());
3822 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3823 N0, UDVal, ShufMask,
3824 MappedOps[NumElts], MappedOps[NumElts+1]);
3830 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
3831 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
3832 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
3833 /// vector_shuffle V, Zero, <0, 4, 2, 4>
3834 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
3835 SDOperand LHS = N->getOperand(0);
3836 SDOperand RHS = N->getOperand(1);
3837 if (N->getOpcode() == ISD::VAND) {
3838 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
3839 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
3840 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
3841 RHS = RHS.getOperand(0);
3842 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3843 std::vector<SDOperand> IdxOps;
3844 unsigned NumOps = RHS.getNumOperands();
3845 unsigned NumElts = NumOps-2;
3846 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
3847 for (unsigned i = 0; i != NumElts; ++i) {
3848 SDOperand Elt = RHS.getOperand(i);
3849 if (!isa<ConstantSDNode>(Elt))
3851 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
3852 IdxOps.push_back(DAG.getConstant(i, EVT));
3853 else if (cast<ConstantSDNode>(Elt)->isNullValue())
3854 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
3859 // Let's see if the target supports this vector_shuffle.
3860 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
3863 // Return the new VVECTOR_SHUFFLE node.
3864 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
3865 SDOperand EVTNode = DAG.getValueType(EVT);
3866 std::vector<SDOperand> Ops;
3867 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode,
3870 AddToWorkList(LHS.Val);
3871 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
3872 ZeroOps.push_back(NumEltsNode);
3873 ZeroOps.push_back(EVTNode);
3874 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3875 &ZeroOps[0], ZeroOps.size()));
3876 IdxOps.push_back(NumEltsNode);
3877 IdxOps.push_back(EVTNode);
3878 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3879 &IdxOps[0], IdxOps.size()));
3880 Ops.push_back(NumEltsNode);
3881 Ops.push_back(EVTNode);
3882 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3883 &Ops[0], Ops.size());
3884 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
3885 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
3886 DstVecSize, DstVecEVT);
3894 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
3895 /// the scalar operation of the vop if it is operating on an integer vector
3896 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
3897 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
3898 ISD::NodeType FPOp) {
3899 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
3900 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
3901 SDOperand LHS = N->getOperand(0);
3902 SDOperand RHS = N->getOperand(1);
3903 SDOperand Shuffle = XformToShuffleWithZero(N);
3904 if (Shuffle.Val) return Shuffle;
3906 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
3908 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
3909 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3910 SmallVector<SDOperand, 8> Ops;
3911 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
3912 SDOperand LHSOp = LHS.getOperand(i);
3913 SDOperand RHSOp = RHS.getOperand(i);
3914 // If these two elements can't be folded, bail out.
3915 if ((LHSOp.getOpcode() != ISD::UNDEF &&
3916 LHSOp.getOpcode() != ISD::Constant &&
3917 LHSOp.getOpcode() != ISD::ConstantFP) ||
3918 (RHSOp.getOpcode() != ISD::UNDEF &&
3919 RHSOp.getOpcode() != ISD::Constant &&
3920 RHSOp.getOpcode() != ISD::ConstantFP))
3922 // Can't fold divide by zero.
3923 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
3924 if ((RHSOp.getOpcode() == ISD::Constant &&
3925 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
3926 (RHSOp.getOpcode() == ISD::ConstantFP &&
3927 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
3930 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
3931 AddToWorkList(Ops.back().Val);
3932 assert((Ops.back().getOpcode() == ISD::UNDEF ||
3933 Ops.back().getOpcode() == ISD::Constant ||
3934 Ops.back().getOpcode() == ISD::ConstantFP) &&
3935 "Scalar binop didn't fold!");
3938 if (Ops.size() == LHS.getNumOperands()-2) {
3939 Ops.push_back(*(LHS.Val->op_end()-2));
3940 Ops.push_back(*(LHS.Val->op_end()-1));
3941 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
3948 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
3949 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
3951 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
3952 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3953 // If we got a simplified select_cc node back from SimplifySelectCC, then
3954 // break it down into a new SETCC node, and a new SELECT node, and then return
3955 // the SELECT node, since we were called with a SELECT node.
3957 // Check to see if we got a select_cc back (to turn into setcc/select).
3958 // Otherwise, just return whatever node we got back, like fabs.
3959 if (SCC.getOpcode() == ISD::SELECT_CC) {
3960 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
3961 SCC.getOperand(0), SCC.getOperand(1),
3963 AddToWorkList(SETCC.Val);
3964 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
3965 SCC.getOperand(3), SETCC);
3972 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
3973 /// are the two values being selected between, see if we can simplify the
3974 /// select. Callers of this should assume that TheSelect is deleted if this
3975 /// returns true. As such, they should return the appropriate thing (e.g. the
3976 /// node) back to the top-level of the DAG combiner loop to avoid it being
3979 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
3982 // If this is a select from two identical things, try to pull the operation
3983 // through the select.
3984 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
3985 // If this is a load and the token chain is identical, replace the select
3986 // of two loads with a load through a select of the address to load from.
3987 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3988 // constants have been dropped into the constant pool.
3989 if (LHS.getOpcode() == ISD::LOAD &&
3990 // Token chains must be identical.
3991 LHS.getOperand(0) == RHS.getOperand(0)) {
3992 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
3993 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
3995 // If this is an EXTLOAD, the VT's must match.
3996 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
3997 // FIXME: this conflates two src values, discarding one. This is not
3998 // the right thing to do, but nothing uses srcvalues now. When they do,
3999 // turn SrcValue into a list of locations.
4001 if (TheSelect->getOpcode() == ISD::SELECT) {
4002 // Check that the condition doesn't reach either load. If so, folding
4003 // this will induce a cycle into the DAG.
4004 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4005 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
4006 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
4007 TheSelect->getOperand(0), LLD->getBasePtr(),
4011 // Check that the condition doesn't reach either load. If so, folding
4012 // this will induce a cycle into the DAG.
4013 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4014 !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4015 !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
4016 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
4017 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
4018 TheSelect->getOperand(0),
4019 TheSelect->getOperand(1),
4020 LLD->getBasePtr(), RLD->getBasePtr(),
4021 TheSelect->getOperand(4));
4027 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
4028 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
4029 Addr,LLD->getSrcValue(),
4030 LLD->getSrcValueOffset());
4032 Load = DAG.getExtLoad(LLD->getExtensionType(),
4033 TheSelect->getValueType(0),
4034 LLD->getChain(), Addr, LLD->getSrcValue(),
4035 LLD->getSrcValueOffset(),
4036 LLD->getLoadedVT());
4038 // Users of the select now use the result of the load.
4039 CombineTo(TheSelect, Load);
4041 // Users of the old loads now use the new load's chain. We know the
4042 // old-load value is dead now.
4043 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
4044 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
4054 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
4055 SDOperand N2, SDOperand N3,
4056 ISD::CondCode CC, bool NotExtCompare) {
4058 MVT::ValueType VT = N2.getValueType();
4059 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
4060 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
4061 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
4063 // Determine if the condition we're dealing with is constant
4064 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
4065 if (SCC.Val) AddToWorkList(SCC.Val);
4066 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
4068 // fold select_cc true, x, y -> x
4069 if (SCCC && SCCC->getValue())
4071 // fold select_cc false, x, y -> y
4072 if (SCCC && SCCC->getValue() == 0)
4075 // Check to see if we can simplify the select into an fabs node
4076 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
4077 // Allow either -0.0 or 0.0
4078 if (CFP->getValue() == 0.0) {
4079 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
4080 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
4081 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
4082 N2 == N3.getOperand(0))
4083 return DAG.getNode(ISD::FABS, VT, N0);
4085 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
4086 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
4087 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
4088 N2.getOperand(0) == N3)
4089 return DAG.getNode(ISD::FABS, VT, N3);
4093 // Check to see if we can perform the "gzip trick", transforming
4094 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
4095 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
4096 MVT::isInteger(N0.getValueType()) &&
4097 MVT::isInteger(N2.getValueType()) &&
4098 (N1C->isNullValue() || // (a < 0) ? b : 0
4099 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
4100 MVT::ValueType XType = N0.getValueType();
4101 MVT::ValueType AType = N2.getValueType();
4102 if (XType >= AType) {
4103 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
4104 // single-bit constant.
4105 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
4106 unsigned ShCtV = Log2_64(N2C->getValue());
4107 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
4108 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
4109 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
4110 AddToWorkList(Shift.Val);
4111 if (XType > AType) {
4112 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4113 AddToWorkList(Shift.Val);
4115 return DAG.getNode(ISD::AND, AType, Shift, N2);
4117 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4118 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4119 TLI.getShiftAmountTy()));
4120 AddToWorkList(Shift.Val);
4121 if (XType > AType) {
4122 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4123 AddToWorkList(Shift.Val);
4125 return DAG.getNode(ISD::AND, AType, Shift, N2);
4129 // fold select C, 16, 0 -> shl C, 4
4130 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
4131 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
4133 // If the caller doesn't want us to simplify this into a zext of a compare,
4135 if (NotExtCompare && N2C->getValue() == 1)
4138 // Get a SetCC of the condition
4139 // FIXME: Should probably make sure that setcc is legal if we ever have a
4140 // target where it isn't.
4141 SDOperand Temp, SCC;
4142 // cast from setcc result type to select result type
4143 if (AfterLegalize) {
4144 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4145 if (N2.getValueType() < SCC.getValueType())
4146 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
4148 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4150 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
4151 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4153 AddToWorkList(SCC.Val);
4154 AddToWorkList(Temp.Val);
4156 if (N2C->getValue() == 1)
4158 // shl setcc result by log2 n2c
4159 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
4160 DAG.getConstant(Log2_64(N2C->getValue()),
4161 TLI.getShiftAmountTy()));
4164 // Check to see if this is the equivalent of setcc
4165 // FIXME: Turn all of these into setcc if setcc if setcc is legal
4166 // otherwise, go ahead with the folds.
4167 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
4168 MVT::ValueType XType = N0.getValueType();
4169 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
4170 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4171 if (Res.getValueType() != VT)
4172 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
4176 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
4177 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
4178 TLI.isOperationLegal(ISD::CTLZ, XType)) {
4179 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
4180 return DAG.getNode(ISD::SRL, XType, Ctlz,
4181 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
4182 TLI.getShiftAmountTy()));
4184 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
4185 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
4186 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
4188 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
4189 DAG.getConstant(~0ULL, XType));
4190 return DAG.getNode(ISD::SRL, XType,
4191 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
4192 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4193 TLI.getShiftAmountTy()));
4195 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
4196 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
4197 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
4198 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4199 TLI.getShiftAmountTy()));
4200 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
4204 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
4205 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4206 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
4207 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
4208 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) {
4209 MVT::ValueType XType = N0.getValueType();
4210 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4211 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4212 TLI.getShiftAmountTy()));
4213 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4214 AddToWorkList(Shift.Val);
4215 AddToWorkList(Add.Val);
4216 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4218 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
4219 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4220 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
4221 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
4222 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
4223 MVT::ValueType XType = N0.getValueType();
4224 if (SubC->isNullValue() && MVT::isInteger(XType)) {
4225 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4226 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4227 TLI.getShiftAmountTy()));
4228 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4229 AddToWorkList(Shift.Val);
4230 AddToWorkList(Add.Val);
4231 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4239 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
4240 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
4241 SDOperand N1, ISD::CondCode Cond,
4242 bool foldBooleans) {
4243 TargetLowering::DAGCombinerInfo
4244 DagCombineInfo(DAG, !AfterLegalize, false, this);
4245 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
4248 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
4249 /// return a DAG expression to select that will generate the same value by
4250 /// multiplying by a magic number. See:
4251 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4252 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
4253 std::vector<SDNode*> Built;
4254 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
4256 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4262 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
4263 /// return a DAG expression to select that will generate the same value by
4264 /// multiplying by a magic number. See:
4265 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4266 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
4267 std::vector<SDNode*> Built;
4268 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
4270 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4276 /// FindBaseOffset - Return true if base is known not to alias with anything
4277 /// but itself. Provides base object and offset as results.
4278 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4279 // Assume it is a primitive operation.
4280 Base = Ptr; Offset = 0;
4282 // If it's an adding a simple constant then integrate the offset.
4283 if (Base.getOpcode() == ISD::ADD) {
4284 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4285 Base = Base.getOperand(0);
4286 Offset += C->getValue();
4290 // If it's any of the following then it can't alias with anything but itself.
4291 return isa<FrameIndexSDNode>(Base) ||
4292 isa<ConstantPoolSDNode>(Base) ||
4293 isa<GlobalAddressSDNode>(Base);
4296 /// isAlias - Return true if there is any possibility that the two addresses
4298 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4299 const Value *SrcValue1, int SrcValueOffset1,
4300 SDOperand Ptr2, int64_t Size2,
4301 const Value *SrcValue2, int SrcValueOffset2)
4303 // If they are the same then they must be aliases.
4304 if (Ptr1 == Ptr2) return true;
4306 // Gather base node and offset information.
4307 SDOperand Base1, Base2;
4308 int64_t Offset1, Offset2;
4309 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4310 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4312 // If they have a same base address then...
4313 if (Base1 == Base2) {
4314 // Check to see if the addresses overlap.
4315 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4318 // If we know both bases then they can't alias.
4319 if (KnownBase1 && KnownBase2) return false;
4321 if (CombinerGlobalAA) {
4322 // Use alias analysis information.
4323 int Overlap1 = Size1 + SrcValueOffset1 + Offset1;
4324 int Overlap2 = Size2 + SrcValueOffset2 + Offset2;
4325 AliasAnalysis::AliasResult AAResult =
4326 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
4327 if (AAResult == AliasAnalysis::NoAlias)
4331 // Otherwise we have to assume they alias.
4335 /// FindAliasInfo - Extracts the relevant alias information from the memory
4336 /// node. Returns true if the operand was a load.
4337 bool DAGCombiner::FindAliasInfo(SDNode *N,
4338 SDOperand &Ptr, int64_t &Size,
4339 const Value *&SrcValue, int &SrcValueOffset) {
4340 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4341 Ptr = LD->getBasePtr();
4342 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4343 SrcValue = LD->getSrcValue();
4344 SrcValueOffset = LD->getSrcValueOffset();
4346 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4347 Ptr = ST->getBasePtr();
4348 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4349 SrcValue = ST->getSrcValue();
4350 SrcValueOffset = ST->getSrcValueOffset();
4352 assert(0 && "FindAliasInfo expected a memory operand");
4358 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4359 /// looking for aliasing nodes and adding them to the Aliases vector.
4360 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4361 SmallVector<SDOperand, 8> &Aliases) {
4362 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4363 std::set<SDNode *> Visited; // Visited node set.
4365 // Get alias information for node.
4368 const Value *SrcValue;
4370 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
4373 Chains.push_back(OriginalChain);
4375 // Look at each chain and determine if it is an alias. If so, add it to the
4376 // aliases list. If not, then continue up the chain looking for the next
4378 while (!Chains.empty()) {
4379 SDOperand Chain = Chains.back();
4382 // Don't bother if we've been before.
4383 if (Visited.find(Chain.Val) != Visited.end()) continue;
4384 Visited.insert(Chain.Val);
4386 switch (Chain.getOpcode()) {
4387 case ISD::EntryToken:
4388 // Entry token is ideal chain operand, but handled in FindBetterChain.
4393 // Get alias information for Chain.
4396 const Value *OpSrcValue;
4397 int OpSrcValueOffset;
4398 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
4399 OpSrcValue, OpSrcValueOffset);
4401 // If chain is alias then stop here.
4402 if (!(IsLoad && IsOpLoad) &&
4403 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
4404 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
4405 Aliases.push_back(Chain);
4407 // Look further up the chain.
4408 Chains.push_back(Chain.getOperand(0));
4409 // Clean up old chain.
4410 AddToWorkList(Chain.Val);
4415 case ISD::TokenFactor:
4416 // We have to check each of the operands of the token factor, so we queue
4417 // then up. Adding the operands to the queue (stack) in reverse order
4418 // maintains the original order and increases the likelihood that getNode
4419 // will find a matching token factor (CSE.)
4420 for (unsigned n = Chain.getNumOperands(); n;)
4421 Chains.push_back(Chain.getOperand(--n));
4422 // Eliminate the token factor if we can.
4423 AddToWorkList(Chain.Val);
4427 // For all other instructions we will just have to take what we can get.
4428 Aliases.push_back(Chain);
4434 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4435 /// for a better chain (aliasing node.)
4436 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4437 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4439 // Accumulate all the aliases to this node.
4440 GatherAllAliases(N, OldChain, Aliases);
4442 if (Aliases.size() == 0) {
4443 // If no operands then chain to entry token.
4444 return DAG.getEntryNode();
4445 } else if (Aliases.size() == 1) {
4446 // If a single operand then chain to it. We don't need to revisit it.
4450 // Construct a custom tailored token factor.
4451 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4452 &Aliases[0], Aliases.size());
4454 // Make sure the old chain gets cleaned up.
4455 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4460 // SelectionDAG::Combine - This is the entry point for the file.
4462 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
4463 if (!RunningAfterLegalize && ViewDAGCombine1)
4465 if (RunningAfterLegalize && ViewDAGCombine2)
4467 /// run - This is the main entry point to this class.
4469 DAGCombiner(*this, AA).Run(RunningAfterLegalize);