1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/DataLayout.h"
27 #include "llvm/DerivedTypes.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetLowering.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
40 STATISTIC(NodesCombined , "Number of dag nodes combined");
41 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
42 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
43 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
44 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
48 CombinerAA("combiner-alias-analysis", cl::Hidden,
49 cl::desc("Turn on alias analysis during testing"));
52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
53 cl::desc("Include global information in alias analysis"));
55 //------------------------------ DAGCombiner ---------------------------------//
59 const TargetLowering &TLI;
61 CodeGenOpt::Level OptLevel;
65 // Worklist of all of the nodes that need to be simplified.
67 // This has the semantics that when adding to the worklist,
68 // the item added must be next to be processed. It should
69 // also only appear once. The naive approach to this takes
72 // To reduce the insert/remove time to logarithmic, we use
73 // a set and a vector to maintain our worklist.
75 // The set contains the items on the worklist, but does not
76 // maintain the order they should be visited.
78 // The vector maintains the order nodes should be visited, but may
79 // contain duplicate or removed nodes. When choosing a node to
80 // visit, we pop off the order stack until we find an item that is
81 // also in the contents set. All operations are O(log N).
82 SmallPtrSet<SDNode*, 64> WorkListContents;
83 SmallVector<SDNode*, 64> WorkListOrder;
85 // AA - Used for DAG load/store alias analysis.
88 /// AddUsersToWorkList - When an instruction is simplified, add all users of
89 /// the instruction to the work lists because they might get more simplified
92 void AddUsersToWorkList(SDNode *N) {
93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
98 /// visit - call the node-specific routine that knows how to fold each
99 /// particular type of node.
100 SDValue visit(SDNode *N);
103 /// AddToWorkList - Add to the work list making sure its instance is at the
104 /// back (next to be processed.)
105 void AddToWorkList(SDNode *N) {
106 WorkListContents.insert(N);
107 WorkListOrder.push_back(N);
110 /// removeFromWorkList - remove all instances of N from the worklist.
112 void removeFromWorkList(SDNode *N) {
113 WorkListContents.erase(N);
116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
120 return CombineTo(N, &Res, 1, AddTo);
123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
125 SDValue To[] = { Res0, Res1 };
126 return CombineTo(N, To, 2, AddTo);
129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
133 /// SimplifyDemandedBits - Check the specified integer node value to see if
134 /// it can be simplified or if things it uses can be simplified by bit
135 /// propagation. If so, return true.
136 bool SimplifyDemandedBits(SDValue Op) {
137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
138 APInt Demanded = APInt::getAllOnesValue(BitWidth);
139 return SimplifyDemandedBits(Op, Demanded);
142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
144 bool CombineToPreIndexedLoadStore(SDNode *N);
145 bool CombineToPostIndexedLoadStore(SDNode *N);
147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
151 SDValue PromoteIntBinOp(SDValue Op);
152 SDValue PromoteIntShiftOp(SDValue Op);
153 SDValue PromoteExtend(SDValue Op);
154 bool PromoteLoad(SDValue Op);
156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
158 ISD::NodeType ExtType);
160 /// combine - call the node-specific routine that knows how to fold each
161 /// particular type of node. If that doesn't do anything, try the
162 /// target-specific DAG combines.
163 SDValue combine(SDNode *N);
165 // Visitation implementation - Implement dag node combining for different
166 // node types. The semantics are as follows:
168 // SDValue.getNode() == 0 - No change was made
169 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
170 // otherwise - N should be replaced by the returned Operand.
172 SDValue visitTokenFactor(SDNode *N);
173 SDValue visitMERGE_VALUES(SDNode *N);
174 SDValue visitADD(SDNode *N);
175 SDValue visitSUB(SDNode *N);
176 SDValue visitADDC(SDNode *N);
177 SDValue visitSUBC(SDNode *N);
178 SDValue visitADDE(SDNode *N);
179 SDValue visitSUBE(SDNode *N);
180 SDValue visitMUL(SDNode *N);
181 SDValue visitSDIV(SDNode *N);
182 SDValue visitUDIV(SDNode *N);
183 SDValue visitSREM(SDNode *N);
184 SDValue visitUREM(SDNode *N);
185 SDValue visitMULHU(SDNode *N);
186 SDValue visitMULHS(SDNode *N);
187 SDValue visitSMUL_LOHI(SDNode *N);
188 SDValue visitUMUL_LOHI(SDNode *N);
189 SDValue visitSMULO(SDNode *N);
190 SDValue visitUMULO(SDNode *N);
191 SDValue visitSDIVREM(SDNode *N);
192 SDValue visitUDIVREM(SDNode *N);
193 SDValue visitAND(SDNode *N);
194 SDValue visitOR(SDNode *N);
195 SDValue visitXOR(SDNode *N);
196 SDValue SimplifyVBinOp(SDNode *N);
197 SDValue SimplifyVUnaryOp(SDNode *N);
198 SDValue visitSHL(SDNode *N);
199 SDValue visitSRA(SDNode *N);
200 SDValue visitSRL(SDNode *N);
201 SDValue visitCTLZ(SDNode *N);
202 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
203 SDValue visitCTTZ(SDNode *N);
204 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
205 SDValue visitCTPOP(SDNode *N);
206 SDValue visitSELECT(SDNode *N);
207 SDValue visitSELECT_CC(SDNode *N);
208 SDValue visitSETCC(SDNode *N);
209 SDValue visitSIGN_EXTEND(SDNode *N);
210 SDValue visitZERO_EXTEND(SDNode *N);
211 SDValue visitANY_EXTEND(SDNode *N);
212 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
213 SDValue visitTRUNCATE(SDNode *N);
214 SDValue visitBITCAST(SDNode *N);
215 SDValue visitBUILD_PAIR(SDNode *N);
216 SDValue visitFADD(SDNode *N);
217 SDValue visitFSUB(SDNode *N);
218 SDValue visitFMUL(SDNode *N);
219 SDValue visitFMA(SDNode *N);
220 SDValue visitFDIV(SDNode *N);
221 SDValue visitFREM(SDNode *N);
222 SDValue visitFCOPYSIGN(SDNode *N);
223 SDValue visitSINT_TO_FP(SDNode *N);
224 SDValue visitUINT_TO_FP(SDNode *N);
225 SDValue visitFP_TO_SINT(SDNode *N);
226 SDValue visitFP_TO_UINT(SDNode *N);
227 SDValue visitFP_ROUND(SDNode *N);
228 SDValue visitFP_ROUND_INREG(SDNode *N);
229 SDValue visitFP_EXTEND(SDNode *N);
230 SDValue visitFNEG(SDNode *N);
231 SDValue visitFABS(SDNode *N);
232 SDValue visitFCEIL(SDNode *N);
233 SDValue visitFTRUNC(SDNode *N);
234 SDValue visitFFLOOR(SDNode *N);
235 SDValue visitBRCOND(SDNode *N);
236 SDValue visitBR_CC(SDNode *N);
237 SDValue visitLOAD(SDNode *N);
238 SDValue visitSTORE(SDNode *N);
239 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
240 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
241 SDValue visitBUILD_VECTOR(SDNode *N);
242 SDValue visitCONCAT_VECTORS(SDNode *N);
243 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
244 SDValue visitVECTOR_SHUFFLE(SDNode *N);
245 SDValue visitMEMBARRIER(SDNode *N);
247 SDValue XformToShuffleWithZero(SDNode *N);
248 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
250 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
252 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
253 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
254 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
255 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
256 SDValue N3, ISD::CondCode CC,
257 bool NotExtCompare = false);
258 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
259 DebugLoc DL, bool foldBooleans = true);
260 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
262 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
263 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
264 SDValue BuildSDIV(SDNode *N);
265 SDValue BuildUDIV(SDNode *N);
266 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
267 bool DemandHighBits = true);
268 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
269 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
270 SDValue ReduceLoadWidth(SDNode *N);
271 SDValue ReduceLoadOpStoreWidth(SDNode *N);
272 SDValue TransformFPLoadStorePair(SDNode *N);
273 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
274 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N);
276 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
278 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
279 /// looking for aliasing nodes and adding them to the Aliases vector.
280 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
281 SmallVector<SDValue, 8> &Aliases);
283 /// isAlias - Return true if there is any possibility that the two addresses
285 bool isAlias(SDValue Ptr1, int64_t Size1,
286 const Value *SrcValue1, int SrcValueOffset1,
287 unsigned SrcValueAlign1,
288 const MDNode *TBAAInfo1,
289 SDValue Ptr2, int64_t Size2,
290 const Value *SrcValue2, int SrcValueOffset2,
291 unsigned SrcValueAlign2,
292 const MDNode *TBAAInfo2) const;
294 /// isAlias - Return true if there is any possibility that the two addresses
296 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1);
298 /// FindAliasInfo - Extracts the relevant alias information from the memory
299 /// node. Returns true if the operand was a load.
300 bool FindAliasInfo(SDNode *N,
301 SDValue &Ptr, int64_t &Size,
302 const Value *&SrcValue, int &SrcValueOffset,
303 unsigned &SrcValueAlignment,
304 const MDNode *&TBAAInfo) const;
306 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
307 /// looking for a better chain (aliasing node.)
308 SDValue FindBetterChain(SDNode *N, SDValue Chain);
310 /// Merge consecutive store operations into a wide store.
311 /// This optimization uses wide integers or vectors when possible.
312 /// \return True if some memory operations were changed.
313 bool MergeConsecutiveStores(StoreSDNode *N);
316 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
317 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
318 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
320 /// Run - runs the dag combiner on all nodes in the work list
321 void Run(CombineLevel AtLevel);
323 SelectionDAG &getDAG() const { return DAG; }
325 /// getShiftAmountTy - Returns a type large enough to hold any valid
326 /// shift amount - before type legalization these can be huge.
327 EVT getShiftAmountTy(EVT LHSTy) {
328 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
331 /// isTypeLegal - This method returns true if we are running before type
332 /// legalization or if the specified VT is legal.
333 bool isTypeLegal(const EVT &VT) {
334 if (!LegalTypes) return true;
335 return TLI.isTypeLegal(VT);
342 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
343 /// nodes from the worklist.
344 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
347 explicit WorkListRemover(DAGCombiner &dc)
348 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
350 virtual void NodeDeleted(SDNode *N, SDNode *E) {
351 DC.removeFromWorkList(N);
356 //===----------------------------------------------------------------------===//
357 // TargetLowering::DAGCombinerInfo implementation
358 //===----------------------------------------------------------------------===//
360 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
361 ((DAGCombiner*)DC)->AddToWorkList(N);
364 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
365 ((DAGCombiner*)DC)->removeFromWorkList(N);
368 SDValue TargetLowering::DAGCombinerInfo::
369 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
370 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
373 SDValue TargetLowering::DAGCombinerInfo::
374 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
375 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
379 SDValue TargetLowering::DAGCombinerInfo::
380 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
381 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
384 void TargetLowering::DAGCombinerInfo::
385 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
386 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
389 //===----------------------------------------------------------------------===//
391 //===----------------------------------------------------------------------===//
393 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
394 /// specified expression for the same cost as the expression itself, or 2 if we
395 /// can compute the negated form more cheaply than the expression itself.
396 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
397 const TargetLowering &TLI,
398 const TargetOptions *Options,
399 unsigned Depth = 0) {
400 // fneg is removable even if it has multiple uses.
401 if (Op.getOpcode() == ISD::FNEG) return 2;
403 // Don't allow anything with multiple uses.
404 if (!Op.hasOneUse()) return 0;
406 // Don't recurse exponentially.
407 if (Depth > 6) return 0;
409 switch (Op.getOpcode()) {
410 default: return false;
411 case ISD::ConstantFP:
412 // Don't invert constant FP values after legalize. The negated constant
413 // isn't necessarily legal.
414 return LegalOperations ? 0 : 1;
416 // FIXME: determine better conditions for this xform.
417 if (!Options->UnsafeFPMath) return 0;
419 // After operation legalization, it might not be legal to create new FSUBs.
420 if (LegalOperations &&
421 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
424 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
425 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
428 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
429 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
432 // We can't turn -(A-B) into B-A when we honor signed zeros.
433 if (!Options->UnsafeFPMath) return 0;
435 // fold (fneg (fsub A, B)) -> (fsub B, A)
440 if (Options->HonorSignDependentRoundingFPMath()) return 0;
442 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
443 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
447 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
453 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
458 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
459 /// returns the newly negated expression.
460 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
461 bool LegalOperations, unsigned Depth = 0) {
462 // fneg is removable even if it has multiple uses.
463 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
465 // Don't allow anything with multiple uses.
466 assert(Op.hasOneUse() && "Unknown reuse!");
468 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
469 switch (Op.getOpcode()) {
470 default: llvm_unreachable("Unknown code");
471 case ISD::ConstantFP: {
472 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
474 return DAG.getConstantFP(V, Op.getValueType());
477 // FIXME: determine better conditions for this xform.
478 assert(DAG.getTarget().Options.UnsafeFPMath);
480 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
481 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
482 DAG.getTargetLoweringInfo(),
483 &DAG.getTarget().Options, Depth+1))
484 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
485 GetNegatedExpression(Op.getOperand(0), DAG,
486 LegalOperations, Depth+1),
488 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
489 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
490 GetNegatedExpression(Op.getOperand(1), DAG,
491 LegalOperations, Depth+1),
494 // We can't turn -(A-B) into B-A when we honor signed zeros.
495 assert(DAG.getTarget().Options.UnsafeFPMath);
497 // fold (fneg (fsub 0, B)) -> B
498 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
499 if (N0CFP->getValueAPF().isZero())
500 return Op.getOperand(1);
502 // fold (fneg (fsub A, B)) -> (fsub B, A)
503 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
504 Op.getOperand(1), Op.getOperand(0));
508 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath());
510 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
511 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
512 DAG.getTargetLoweringInfo(),
513 &DAG.getTarget().Options, Depth+1))
514 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
515 GetNegatedExpression(Op.getOperand(0), DAG,
516 LegalOperations, Depth+1),
519 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
520 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
522 GetNegatedExpression(Op.getOperand(1), DAG,
523 LegalOperations, Depth+1));
527 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
528 GetNegatedExpression(Op.getOperand(0), DAG,
529 LegalOperations, Depth+1));
531 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
532 GetNegatedExpression(Op.getOperand(0), DAG,
533 LegalOperations, Depth+1),
539 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
540 // that selects between the values 1 and 0, making it equivalent to a setcc.
541 // Also, set the incoming LHS, RHS, and CC references to the appropriate
542 // nodes based on the type of node we are checking. This simplifies life a
543 // bit for the callers.
544 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
546 if (N.getOpcode() == ISD::SETCC) {
547 LHS = N.getOperand(0);
548 RHS = N.getOperand(1);
549 CC = N.getOperand(2);
552 if (N.getOpcode() == ISD::SELECT_CC &&
553 N.getOperand(2).getOpcode() == ISD::Constant &&
554 N.getOperand(3).getOpcode() == ISD::Constant &&
555 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
556 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
557 LHS = N.getOperand(0);
558 RHS = N.getOperand(1);
559 CC = N.getOperand(4);
565 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
566 // one use. If this is true, it allows the users to invert the operation for
567 // free when it is profitable to do so.
568 static bool isOneUseSetCC(SDValue N) {
570 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
575 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
576 SDValue N0, SDValue N1) {
577 EVT VT = N0.getValueType();
578 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
579 if (isa<ConstantSDNode>(N1)) {
580 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
582 DAG.FoldConstantArithmetic(Opc, VT,
583 cast<ConstantSDNode>(N0.getOperand(1)),
584 cast<ConstantSDNode>(N1));
585 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
587 if (N0.hasOneUse()) {
588 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
589 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
590 N0.getOperand(0), N1);
591 AddToWorkList(OpNode.getNode());
592 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
596 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
597 if (isa<ConstantSDNode>(N0)) {
598 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
600 DAG.FoldConstantArithmetic(Opc, VT,
601 cast<ConstantSDNode>(N1.getOperand(1)),
602 cast<ConstantSDNode>(N0));
603 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
605 if (N1.hasOneUse()) {
606 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
607 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
608 N1.getOperand(0), N0);
609 AddToWorkList(OpNode.getNode());
610 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
617 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
619 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
621 DEBUG(dbgs() << "\nReplacing.1 ";
623 dbgs() << "\nWith: ";
624 To[0].getNode()->dump(&DAG);
625 dbgs() << " and " << NumTo-1 << " other values\n";
626 for (unsigned i = 0, e = NumTo; i != e; ++i)
627 assert((!To[i].getNode() ||
628 N->getValueType(i) == To[i].getValueType()) &&
629 "Cannot combine value to value of different type!"));
630 WorkListRemover DeadNodes(*this);
631 DAG.ReplaceAllUsesWith(N, To);
633 // Push the new nodes and any users onto the worklist
634 for (unsigned i = 0, e = NumTo; i != e; ++i) {
635 if (To[i].getNode()) {
636 AddToWorkList(To[i].getNode());
637 AddUsersToWorkList(To[i].getNode());
642 // Finally, if the node is now dead, remove it from the graph. The node
643 // may not be dead if the replacement process recursively simplified to
644 // something else needing this node.
645 if (N->use_empty()) {
646 // Nodes can be reintroduced into the worklist. Make sure we do not
647 // process a node that has been replaced.
648 removeFromWorkList(N);
650 // Finally, since the node is now dead, remove it from the graph.
653 return SDValue(N, 0);
657 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
658 // Replace all uses. If any nodes become isomorphic to other nodes and
659 // are deleted, make sure to remove them from our worklist.
660 WorkListRemover DeadNodes(*this);
661 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
663 // Push the new node and any (possibly new) users onto the worklist.
664 AddToWorkList(TLO.New.getNode());
665 AddUsersToWorkList(TLO.New.getNode());
667 // Finally, if the node is now dead, remove it from the graph. The node
668 // may not be dead if the replacement process recursively simplified to
669 // something else needing this node.
670 if (TLO.Old.getNode()->use_empty()) {
671 removeFromWorkList(TLO.Old.getNode());
673 // If the operands of this node are only used by the node, they will now
674 // be dead. Make sure to visit them first to delete dead nodes early.
675 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
676 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
677 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
679 DAG.DeleteNode(TLO.Old.getNode());
683 /// SimplifyDemandedBits - Check the specified integer node value to see if
684 /// it can be simplified or if things it uses can be simplified by bit
685 /// propagation. If so, return true.
686 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
687 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
688 APInt KnownZero, KnownOne;
689 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
693 AddToWorkList(Op.getNode());
695 // Replace the old value with the new one.
697 DEBUG(dbgs() << "\nReplacing.2 ";
698 TLO.Old.getNode()->dump(&DAG);
699 dbgs() << "\nWith: ";
700 TLO.New.getNode()->dump(&DAG);
703 CommitTargetLoweringOpt(TLO);
707 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
708 DebugLoc dl = Load->getDebugLoc();
709 EVT VT = Load->getValueType(0);
710 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
712 DEBUG(dbgs() << "\nReplacing.9 ";
714 dbgs() << "\nWith: ";
715 Trunc.getNode()->dump(&DAG);
717 WorkListRemover DeadNodes(*this);
718 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
719 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
720 removeFromWorkList(Load);
721 DAG.DeleteNode(Load);
722 AddToWorkList(Trunc.getNode());
725 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
727 DebugLoc dl = Op.getDebugLoc();
728 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
729 EVT MemVT = LD->getMemoryVT();
730 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
731 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
733 : LD->getExtensionType();
735 return DAG.getExtLoad(ExtType, dl, PVT,
736 LD->getChain(), LD->getBasePtr(),
737 LD->getPointerInfo(),
738 MemVT, LD->isVolatile(),
739 LD->isNonTemporal(), LD->getAlignment());
742 unsigned Opc = Op.getOpcode();
745 case ISD::AssertSext:
746 return DAG.getNode(ISD::AssertSext, dl, PVT,
747 SExtPromoteOperand(Op.getOperand(0), PVT),
749 case ISD::AssertZext:
750 return DAG.getNode(ISD::AssertZext, dl, PVT,
751 ZExtPromoteOperand(Op.getOperand(0), PVT),
753 case ISD::Constant: {
755 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
756 return DAG.getNode(ExtOpc, dl, PVT, Op);
760 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
762 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
765 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
766 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
768 EVT OldVT = Op.getValueType();
769 DebugLoc dl = Op.getDebugLoc();
770 bool Replace = false;
771 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
772 if (NewOp.getNode() == 0)
774 AddToWorkList(NewOp.getNode());
777 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
778 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
779 DAG.getValueType(OldVT));
782 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
783 EVT OldVT = Op.getValueType();
784 DebugLoc dl = Op.getDebugLoc();
785 bool Replace = false;
786 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
787 if (NewOp.getNode() == 0)
789 AddToWorkList(NewOp.getNode());
792 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
793 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
796 /// PromoteIntBinOp - Promote the specified integer binary operation if the
797 /// target indicates it is beneficial. e.g. On x86, it's usually better to
798 /// promote i16 operations to i32 since i16 instructions are longer.
799 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
800 if (!LegalOperations)
803 EVT VT = Op.getValueType();
804 if (VT.isVector() || !VT.isInteger())
807 // If operation type is 'undesirable', e.g. i16 on x86, consider
809 unsigned Opc = Op.getOpcode();
810 if (TLI.isTypeDesirableForOp(Opc, VT))
814 // Consult target whether it is a good idea to promote this operation and
815 // what's the right type to promote it to.
816 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
817 assert(PVT != VT && "Don't know what type to promote to!");
819 bool Replace0 = false;
820 SDValue N0 = Op.getOperand(0);
821 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
822 if (NN0.getNode() == 0)
825 bool Replace1 = false;
826 SDValue N1 = Op.getOperand(1);
831 NN1 = PromoteOperand(N1, PVT, Replace1);
832 if (NN1.getNode() == 0)
836 AddToWorkList(NN0.getNode());
838 AddToWorkList(NN1.getNode());
841 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
843 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
845 DEBUG(dbgs() << "\nPromoting ";
846 Op.getNode()->dump(&DAG));
847 DebugLoc dl = Op.getDebugLoc();
848 return DAG.getNode(ISD::TRUNCATE, dl, VT,
849 DAG.getNode(Opc, dl, PVT, NN0, NN1));
854 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
855 /// target indicates it is beneficial. e.g. On x86, it's usually better to
856 /// promote i16 operations to i32 since i16 instructions are longer.
857 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
858 if (!LegalOperations)
861 EVT VT = Op.getValueType();
862 if (VT.isVector() || !VT.isInteger())
865 // If operation type is 'undesirable', e.g. i16 on x86, consider
867 unsigned Opc = Op.getOpcode();
868 if (TLI.isTypeDesirableForOp(Opc, VT))
872 // Consult target whether it is a good idea to promote this operation and
873 // what's the right type to promote it to.
874 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
875 assert(PVT != VT && "Don't know what type to promote to!");
877 bool Replace = false;
878 SDValue N0 = Op.getOperand(0);
880 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
881 else if (Opc == ISD::SRL)
882 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
884 N0 = PromoteOperand(N0, PVT, Replace);
885 if (N0.getNode() == 0)
888 AddToWorkList(N0.getNode());
890 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
892 DEBUG(dbgs() << "\nPromoting ";
893 Op.getNode()->dump(&DAG));
894 DebugLoc dl = Op.getDebugLoc();
895 return DAG.getNode(ISD::TRUNCATE, dl, VT,
896 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
901 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
902 if (!LegalOperations)
905 EVT VT = Op.getValueType();
906 if (VT.isVector() || !VT.isInteger())
909 // If operation type is 'undesirable', e.g. i16 on x86, consider
911 unsigned Opc = Op.getOpcode();
912 if (TLI.isTypeDesirableForOp(Opc, VT))
916 // Consult target whether it is a good idea to promote this operation and
917 // what's the right type to promote it to.
918 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
919 assert(PVT != VT && "Don't know what type to promote to!");
920 // fold (aext (aext x)) -> (aext x)
921 // fold (aext (zext x)) -> (zext x)
922 // fold (aext (sext x)) -> (sext x)
923 DEBUG(dbgs() << "\nPromoting ";
924 Op.getNode()->dump(&DAG));
925 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
930 bool DAGCombiner::PromoteLoad(SDValue Op) {
931 if (!LegalOperations)
934 EVT VT = Op.getValueType();
935 if (VT.isVector() || !VT.isInteger())
938 // If operation type is 'undesirable', e.g. i16 on x86, consider
940 unsigned Opc = Op.getOpcode();
941 if (TLI.isTypeDesirableForOp(Opc, VT))
945 // Consult target whether it is a good idea to promote this operation and
946 // what's the right type to promote it to.
947 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
948 assert(PVT != VT && "Don't know what type to promote to!");
950 DebugLoc dl = Op.getDebugLoc();
951 SDNode *N = Op.getNode();
952 LoadSDNode *LD = cast<LoadSDNode>(N);
953 EVT MemVT = LD->getMemoryVT();
954 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
955 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
957 : LD->getExtensionType();
958 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
959 LD->getChain(), LD->getBasePtr(),
960 LD->getPointerInfo(),
961 MemVT, LD->isVolatile(),
962 LD->isNonTemporal(), LD->getAlignment());
963 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
965 DEBUG(dbgs() << "\nPromoting ";
968 Result.getNode()->dump(&DAG);
970 WorkListRemover DeadNodes(*this);
971 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
972 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
973 removeFromWorkList(N);
975 AddToWorkList(Result.getNode());
982 //===----------------------------------------------------------------------===//
983 // Main DAG Combiner implementation
984 //===----------------------------------------------------------------------===//
986 void DAGCombiner::Run(CombineLevel AtLevel) {
987 // set the instance variables, so that the various visit routines may use it.
989 LegalOperations = Level >= AfterLegalizeVectorOps;
990 LegalTypes = Level >= AfterLegalizeTypes;
992 // Add all the dag nodes to the worklist.
993 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
994 E = DAG.allnodes_end(); I != E; ++I)
997 // Create a dummy node (which is not added to allnodes), that adds a reference
998 // to the root node, preventing it from being deleted, and tracking any
999 // changes of the root.
1000 HandleSDNode Dummy(DAG.getRoot());
1002 // The root of the dag may dangle to deleted nodes until the dag combiner is
1003 // done. Set it to null to avoid confusion.
1004 DAG.setRoot(SDValue());
1006 // while the worklist isn't empty, find a node and
1007 // try and combine it.
1008 while (!WorkListContents.empty()) {
1010 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates.
1011 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the
1012 // worklist *should* contain, and check the node we want to visit is should
1013 // actually be visited.
1015 N = WorkListOrder.pop_back_val();
1016 } while (!WorkListContents.erase(N));
1018 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1019 // N is deleted from the DAG, since they too may now be dead or may have a
1020 // reduced number of uses, allowing other xforms.
1021 if (N->use_empty() && N != &Dummy) {
1022 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1023 AddToWorkList(N->getOperand(i).getNode());
1029 SDValue RV = combine(N);
1031 if (RV.getNode() == 0)
1036 // If we get back the same node we passed in, rather than a new node or
1037 // zero, we know that the node must have defined multiple values and
1038 // CombineTo was used. Since CombineTo takes care of the worklist
1039 // mechanics for us, we have no work to do in this case.
1040 if (RV.getNode() == N)
1043 assert(N->getOpcode() != ISD::DELETED_NODE &&
1044 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1045 "Node was deleted but visit returned new node!");
1047 DEBUG(dbgs() << "\nReplacing.3 ";
1049 dbgs() << "\nWith: ";
1050 RV.getNode()->dump(&DAG);
1053 // Transfer debug value.
1054 DAG.TransferDbgValues(SDValue(N, 0), RV);
1055 WorkListRemover DeadNodes(*this);
1056 if (N->getNumValues() == RV.getNode()->getNumValues())
1057 DAG.ReplaceAllUsesWith(N, RV.getNode());
1059 assert(N->getValueType(0) == RV.getValueType() &&
1060 N->getNumValues() == 1 && "Type mismatch");
1062 DAG.ReplaceAllUsesWith(N, &OpV);
1065 // Push the new node and any users onto the worklist
1066 AddToWorkList(RV.getNode());
1067 AddUsersToWorkList(RV.getNode());
1069 // Add any uses of the old node to the worklist in case this node is the
1070 // last one that uses them. They may become dead after this node is
1072 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1073 AddToWorkList(N->getOperand(i).getNode());
1075 // Finally, if the node is now dead, remove it from the graph. The node
1076 // may not be dead if the replacement process recursively simplified to
1077 // something else needing this node.
1078 if (N->use_empty()) {
1079 // Nodes can be reintroduced into the worklist. Make sure we do not
1080 // process a node that has been replaced.
1081 removeFromWorkList(N);
1083 // Finally, since the node is now dead, remove it from the graph.
1088 // If the root changed (e.g. it was a dead load, update the root).
1089 DAG.setRoot(Dummy.getValue());
1090 DAG.RemoveDeadNodes();
1093 SDValue DAGCombiner::visit(SDNode *N) {
1094 switch (N->getOpcode()) {
1096 case ISD::TokenFactor: return visitTokenFactor(N);
1097 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1098 case ISD::ADD: return visitADD(N);
1099 case ISD::SUB: return visitSUB(N);
1100 case ISD::ADDC: return visitADDC(N);
1101 case ISD::SUBC: return visitSUBC(N);
1102 case ISD::ADDE: return visitADDE(N);
1103 case ISD::SUBE: return visitSUBE(N);
1104 case ISD::MUL: return visitMUL(N);
1105 case ISD::SDIV: return visitSDIV(N);
1106 case ISD::UDIV: return visitUDIV(N);
1107 case ISD::SREM: return visitSREM(N);
1108 case ISD::UREM: return visitUREM(N);
1109 case ISD::MULHU: return visitMULHU(N);
1110 case ISD::MULHS: return visitMULHS(N);
1111 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1112 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1113 case ISD::SMULO: return visitSMULO(N);
1114 case ISD::UMULO: return visitUMULO(N);
1115 case ISD::SDIVREM: return visitSDIVREM(N);
1116 case ISD::UDIVREM: return visitUDIVREM(N);
1117 case ISD::AND: return visitAND(N);
1118 case ISD::OR: return visitOR(N);
1119 case ISD::XOR: return visitXOR(N);
1120 case ISD::SHL: return visitSHL(N);
1121 case ISD::SRA: return visitSRA(N);
1122 case ISD::SRL: return visitSRL(N);
1123 case ISD::CTLZ: return visitCTLZ(N);
1124 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1125 case ISD::CTTZ: return visitCTTZ(N);
1126 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1127 case ISD::CTPOP: return visitCTPOP(N);
1128 case ISD::SELECT: return visitSELECT(N);
1129 case ISD::SELECT_CC: return visitSELECT_CC(N);
1130 case ISD::SETCC: return visitSETCC(N);
1131 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1132 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1133 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1134 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1135 case ISD::TRUNCATE: return visitTRUNCATE(N);
1136 case ISD::BITCAST: return visitBITCAST(N);
1137 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1138 case ISD::FADD: return visitFADD(N);
1139 case ISD::FSUB: return visitFSUB(N);
1140 case ISD::FMUL: return visitFMUL(N);
1141 case ISD::FMA: return visitFMA(N);
1142 case ISD::FDIV: return visitFDIV(N);
1143 case ISD::FREM: return visitFREM(N);
1144 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1145 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1146 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1147 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1148 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1149 case ISD::FP_ROUND: return visitFP_ROUND(N);
1150 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1151 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1152 case ISD::FNEG: return visitFNEG(N);
1153 case ISD::FABS: return visitFABS(N);
1154 case ISD::FFLOOR: return visitFFLOOR(N);
1155 case ISD::FCEIL: return visitFCEIL(N);
1156 case ISD::FTRUNC: return visitFTRUNC(N);
1157 case ISD::BRCOND: return visitBRCOND(N);
1158 case ISD::BR_CC: return visitBR_CC(N);
1159 case ISD::LOAD: return visitLOAD(N);
1160 case ISD::STORE: return visitSTORE(N);
1161 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1162 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1163 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1164 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1165 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1166 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1167 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1172 SDValue DAGCombiner::combine(SDNode *N) {
1173 SDValue RV = visit(N);
1175 // If nothing happened, try a target-specific DAG combine.
1176 if (RV.getNode() == 0) {
1177 assert(N->getOpcode() != ISD::DELETED_NODE &&
1178 "Node was deleted but visit returned NULL!");
1180 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1181 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1183 // Expose the DAG combiner to the target combiner impls.
1184 TargetLowering::DAGCombinerInfo
1185 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1187 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1191 // If nothing happened still, try promoting the operation.
1192 if (RV.getNode() == 0) {
1193 switch (N->getOpcode()) {
1201 RV = PromoteIntBinOp(SDValue(N, 0));
1206 RV = PromoteIntShiftOp(SDValue(N, 0));
1208 case ISD::SIGN_EXTEND:
1209 case ISD::ZERO_EXTEND:
1210 case ISD::ANY_EXTEND:
1211 RV = PromoteExtend(SDValue(N, 0));
1214 if (PromoteLoad(SDValue(N, 0)))
1220 // If N is a commutative binary node, try commuting it to enable more
1222 if (RV.getNode() == 0 &&
1223 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1224 N->getNumValues() == 1) {
1225 SDValue N0 = N->getOperand(0);
1226 SDValue N1 = N->getOperand(1);
1228 // Constant operands are canonicalized to RHS.
1229 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1230 SDValue Ops[] = { N1, N0 };
1231 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1234 return SDValue(CSENode, 0);
1241 /// getInputChainForNode - Given a node, return its input chain if it has one,
1242 /// otherwise return a null sd operand.
1243 static SDValue getInputChainForNode(SDNode *N) {
1244 if (unsigned NumOps = N->getNumOperands()) {
1245 if (N->getOperand(0).getValueType() == MVT::Other)
1246 return N->getOperand(0);
1247 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1248 return N->getOperand(NumOps-1);
1249 for (unsigned i = 1; i < NumOps-1; ++i)
1250 if (N->getOperand(i).getValueType() == MVT::Other)
1251 return N->getOperand(i);
1256 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1257 // If N has two operands, where one has an input chain equal to the other,
1258 // the 'other' chain is redundant.
1259 if (N->getNumOperands() == 2) {
1260 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1261 return N->getOperand(0);
1262 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1263 return N->getOperand(1);
1266 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1267 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1268 SmallPtrSet<SDNode*, 16> SeenOps;
1269 bool Changed = false; // If we should replace this token factor.
1271 // Start out with this token factor.
1274 // Iterate through token factors. The TFs grows when new token factors are
1276 for (unsigned i = 0; i < TFs.size(); ++i) {
1277 SDNode *TF = TFs[i];
1279 // Check each of the operands.
1280 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1281 SDValue Op = TF->getOperand(i);
1283 switch (Op.getOpcode()) {
1284 case ISD::EntryToken:
1285 // Entry tokens don't need to be added to the list. They are
1290 case ISD::TokenFactor:
1291 if (Op.hasOneUse() &&
1292 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1293 // Queue up for processing.
1294 TFs.push_back(Op.getNode());
1295 // Clean up in case the token factor is removed.
1296 AddToWorkList(Op.getNode());
1303 // Only add if it isn't already in the list.
1304 if (SeenOps.insert(Op.getNode()))
1315 // If we've change things around then replace token factor.
1318 // The entry token is the only possible outcome.
1319 Result = DAG.getEntryNode();
1321 // New and improved token factor.
1322 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1323 MVT::Other, &Ops[0], Ops.size());
1326 // Don't add users to work list.
1327 return CombineTo(N, Result, false);
1333 /// MERGE_VALUES can always be eliminated.
1334 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1335 WorkListRemover DeadNodes(*this);
1336 // Replacing results may cause a different MERGE_VALUES to suddenly
1337 // be CSE'd with N, and carry its uses with it. Iterate until no
1338 // uses remain, to ensure that the node can be safely deleted.
1339 // First add the users of this node to the work list so that they
1340 // can be tried again once they have new operands.
1341 AddUsersToWorkList(N);
1343 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1344 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1345 } while (!N->use_empty());
1346 removeFromWorkList(N);
1348 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1352 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1353 SelectionDAG &DAG) {
1354 EVT VT = N0.getValueType();
1355 SDValue N00 = N0.getOperand(0);
1356 SDValue N01 = N0.getOperand(1);
1357 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1359 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1360 isa<ConstantSDNode>(N00.getOperand(1))) {
1361 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1362 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1363 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1364 N00.getOperand(0), N01),
1365 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1366 N00.getOperand(1), N01));
1367 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1373 SDValue DAGCombiner::visitADD(SDNode *N) {
1374 SDValue N0 = N->getOperand(0);
1375 SDValue N1 = N->getOperand(1);
1376 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1377 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1378 EVT VT = N0.getValueType();
1381 if (VT.isVector()) {
1382 SDValue FoldedVOp = SimplifyVBinOp(N);
1383 if (FoldedVOp.getNode()) return FoldedVOp;
1386 // fold (add x, undef) -> undef
1387 if (N0.getOpcode() == ISD::UNDEF)
1389 if (N1.getOpcode() == ISD::UNDEF)
1391 // fold (add c1, c2) -> c1+c2
1393 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1394 // canonicalize constant to RHS
1396 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1397 // fold (add x, 0) -> x
1398 if (N1C && N1C->isNullValue())
1400 // fold (add Sym, c) -> Sym+c
1401 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1402 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1403 GA->getOpcode() == ISD::GlobalAddress)
1404 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1406 (uint64_t)N1C->getSExtValue());
1407 // fold ((c1-A)+c2) -> (c1+c2)-A
1408 if (N1C && N0.getOpcode() == ISD::SUB)
1409 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1410 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1411 DAG.getConstant(N1C->getAPIntValue()+
1412 N0C->getAPIntValue(), VT),
1415 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1416 if (RADD.getNode() != 0)
1418 // fold ((0-A) + B) -> B-A
1419 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1420 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1421 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1422 // fold (A + (0-B)) -> A-B
1423 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1424 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1425 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1426 // fold (A+(B-A)) -> B
1427 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1428 return N1.getOperand(0);
1429 // fold ((B-A)+A) -> B
1430 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1431 return N0.getOperand(0);
1432 // fold (A+(B-(A+C))) to (B-C)
1433 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1434 N0 == N1.getOperand(1).getOperand(0))
1435 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1436 N1.getOperand(1).getOperand(1));
1437 // fold (A+(B-(C+A))) to (B-C)
1438 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1439 N0 == N1.getOperand(1).getOperand(1))
1440 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1441 N1.getOperand(1).getOperand(0));
1442 // fold (A+((B-A)+or-C)) to (B+or-C)
1443 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1444 N1.getOperand(0).getOpcode() == ISD::SUB &&
1445 N0 == N1.getOperand(0).getOperand(1))
1446 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1447 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1449 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1450 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1451 SDValue N00 = N0.getOperand(0);
1452 SDValue N01 = N0.getOperand(1);
1453 SDValue N10 = N1.getOperand(0);
1454 SDValue N11 = N1.getOperand(1);
1456 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1457 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1458 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1459 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1462 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1463 return SDValue(N, 0);
1465 // fold (a+b) -> (a|b) iff a and b share no bits.
1466 if (VT.isInteger() && !VT.isVector()) {
1467 APInt LHSZero, LHSOne;
1468 APInt RHSZero, RHSOne;
1469 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1471 if (LHSZero.getBoolValue()) {
1472 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1474 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1475 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1476 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1477 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1481 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1482 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1483 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1484 if (Result.getNode()) return Result;
1486 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1487 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1488 if (Result.getNode()) return Result;
1491 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1492 if (N1.getOpcode() == ISD::SHL &&
1493 N1.getOperand(0).getOpcode() == ISD::SUB)
1494 if (ConstantSDNode *C =
1495 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1496 if (C->getAPIntValue() == 0)
1497 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1498 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1499 N1.getOperand(0).getOperand(1),
1501 if (N0.getOpcode() == ISD::SHL &&
1502 N0.getOperand(0).getOpcode() == ISD::SUB)
1503 if (ConstantSDNode *C =
1504 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1505 if (C->getAPIntValue() == 0)
1506 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1507 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1508 N0.getOperand(0).getOperand(1),
1511 if (N1.getOpcode() == ISD::AND) {
1512 SDValue AndOp0 = N1.getOperand(0);
1513 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1514 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1515 unsigned DestBits = VT.getScalarType().getSizeInBits();
1517 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1518 // and similar xforms where the inner op is either ~0 or 0.
1519 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1520 DebugLoc DL = N->getDebugLoc();
1521 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1525 // add (sext i1), X -> sub X, (zext i1)
1526 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1527 N0.getOperand(0).getValueType() == MVT::i1 &&
1528 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1529 DebugLoc DL = N->getDebugLoc();
1530 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1531 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1537 SDValue DAGCombiner::visitADDC(SDNode *N) {
1538 SDValue N0 = N->getOperand(0);
1539 SDValue N1 = N->getOperand(1);
1540 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1541 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1542 EVT VT = N0.getValueType();
1544 // If the flag result is dead, turn this into an ADD.
1545 if (!N->hasAnyUseOfValue(1))
1546 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1),
1547 DAG.getNode(ISD::CARRY_FALSE,
1548 N->getDebugLoc(), MVT::Glue));
1550 // canonicalize constant to RHS.
1552 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1554 // fold (addc x, 0) -> x + no carry out
1555 if (N1C && N1C->isNullValue())
1556 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1557 N->getDebugLoc(), MVT::Glue));
1559 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1560 APInt LHSZero, LHSOne;
1561 APInt RHSZero, RHSOne;
1562 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1564 if (LHSZero.getBoolValue()) {
1565 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1567 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1568 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1569 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1570 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1571 DAG.getNode(ISD::CARRY_FALSE,
1572 N->getDebugLoc(), MVT::Glue));
1578 SDValue DAGCombiner::visitADDE(SDNode *N) {
1579 SDValue N0 = N->getOperand(0);
1580 SDValue N1 = N->getOperand(1);
1581 SDValue CarryIn = N->getOperand(2);
1582 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1583 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1585 // canonicalize constant to RHS
1587 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1590 // fold (adde x, y, false) -> (addc x, y)
1591 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1592 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1);
1597 // Since it may not be valid to emit a fold to zero for vector initializers
1598 // check if we can before folding.
1599 static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1600 SelectionDAG &DAG, bool LegalOperations) {
1601 if (!VT.isVector()) {
1602 return DAG.getConstant(0, VT);
1604 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1605 // Produce a vector of zeros.
1606 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1607 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1608 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1609 &Ops[0], Ops.size());
1614 SDValue DAGCombiner::visitSUB(SDNode *N) {
1615 SDValue N0 = N->getOperand(0);
1616 SDValue N1 = N->getOperand(1);
1617 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1618 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1619 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1620 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1621 EVT VT = N0.getValueType();
1624 if (VT.isVector()) {
1625 SDValue FoldedVOp = SimplifyVBinOp(N);
1626 if (FoldedVOp.getNode()) return FoldedVOp;
1629 // fold (sub x, x) -> 0
1630 // FIXME: Refactor this and xor and other similar operations together.
1632 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1633 // fold (sub c1, c2) -> c1-c2
1635 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1636 // fold (sub x, c) -> (add x, -c)
1638 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1639 DAG.getConstant(-N1C->getAPIntValue(), VT));
1640 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1641 if (N0C && N0C->isAllOnesValue())
1642 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1643 // fold A-(A-B) -> B
1644 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1645 return N1.getOperand(1);
1646 // fold (A+B)-A -> B
1647 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1648 return N0.getOperand(1);
1649 // fold (A+B)-B -> A
1650 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1651 return N0.getOperand(0);
1652 // fold C2-(A+C1) -> (C2-C1)-A
1653 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1654 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
1656 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
1659 // fold ((A+(B+or-C))-B) -> A+or-C
1660 if (N0.getOpcode() == ISD::ADD &&
1661 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1662 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1663 N0.getOperand(1).getOperand(0) == N1)
1664 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1665 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1666 // fold ((A+(C+B))-B) -> A+C
1667 if (N0.getOpcode() == ISD::ADD &&
1668 N0.getOperand(1).getOpcode() == ISD::ADD &&
1669 N0.getOperand(1).getOperand(1) == N1)
1670 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1671 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1672 // fold ((A-(B-C))-C) -> A-B
1673 if (N0.getOpcode() == ISD::SUB &&
1674 N0.getOperand(1).getOpcode() == ISD::SUB &&
1675 N0.getOperand(1).getOperand(1) == N1)
1676 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1677 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1679 // If either operand of a sub is undef, the result is undef
1680 if (N0.getOpcode() == ISD::UNDEF)
1682 if (N1.getOpcode() == ISD::UNDEF)
1685 // If the relocation model supports it, consider symbol offsets.
1686 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1687 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1688 // fold (sub Sym, c) -> Sym-c
1689 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1690 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1692 (uint64_t)N1C->getSExtValue());
1693 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1694 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1695 if (GA->getGlobal() == GB->getGlobal())
1696 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1703 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1704 SDValue N0 = N->getOperand(0);
1705 SDValue N1 = N->getOperand(1);
1706 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1707 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1708 EVT VT = N0.getValueType();
1710 // If the flag result is dead, turn this into an SUB.
1711 if (!N->hasAnyUseOfValue(1))
1712 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1),
1713 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1716 // fold (subc x, x) -> 0 + no borrow
1718 return CombineTo(N, DAG.getConstant(0, VT),
1719 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1722 // fold (subc x, 0) -> x + no borrow
1723 if (N1C && N1C->isNullValue())
1724 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1727 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1728 if (N0C && N0C->isAllOnesValue())
1729 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0),
1730 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1736 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1737 SDValue N0 = N->getOperand(0);
1738 SDValue N1 = N->getOperand(1);
1739 SDValue CarryIn = N->getOperand(2);
1741 // fold (sube x, y, false) -> (subc x, y)
1742 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1743 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1);
1748 SDValue DAGCombiner::visitMUL(SDNode *N) {
1749 SDValue N0 = N->getOperand(0);
1750 SDValue N1 = N->getOperand(1);
1751 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1752 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1753 EVT VT = N0.getValueType();
1756 if (VT.isVector()) {
1757 SDValue FoldedVOp = SimplifyVBinOp(N);
1758 if (FoldedVOp.getNode()) return FoldedVOp;
1761 // fold (mul x, undef) -> 0
1762 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1763 return DAG.getConstant(0, VT);
1764 // fold (mul c1, c2) -> c1*c2
1766 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1767 // canonicalize constant to RHS
1769 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1770 // fold (mul x, 0) -> 0
1771 if (N1C && N1C->isNullValue())
1773 // fold (mul x, -1) -> 0-x
1774 if (N1C && N1C->isAllOnesValue())
1775 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1776 DAG.getConstant(0, VT), N0);
1777 // fold (mul x, (1 << c)) -> x << c
1778 if (N1C && N1C->getAPIntValue().isPowerOf2())
1779 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1780 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1781 getShiftAmountTy(N0.getValueType())));
1782 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1783 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1784 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1785 // FIXME: If the input is something that is easily negated (e.g. a
1786 // single-use add), we should put the negate there.
1787 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1788 DAG.getConstant(0, VT),
1789 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1790 DAG.getConstant(Log2Val,
1791 getShiftAmountTy(N0.getValueType()))));
1793 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1794 if (N1C && N0.getOpcode() == ISD::SHL &&
1795 isa<ConstantSDNode>(N0.getOperand(1))) {
1796 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1797 N1, N0.getOperand(1));
1798 AddToWorkList(C3.getNode());
1799 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1800 N0.getOperand(0), C3);
1803 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1806 SDValue Sh(0,0), Y(0,0);
1807 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1808 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1809 N0.getNode()->hasOneUse()) {
1811 } else if (N1.getOpcode() == ISD::SHL &&
1812 isa<ConstantSDNode>(N1.getOperand(1)) &&
1813 N1.getNode()->hasOneUse()) {
1818 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1819 Sh.getOperand(0), Y);
1820 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1821 Mul, Sh.getOperand(1));
1825 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1826 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1827 isa<ConstantSDNode>(N0.getOperand(1)))
1828 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1829 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1830 N0.getOperand(0), N1),
1831 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1832 N0.getOperand(1), N1));
1835 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1836 if (RMUL.getNode() != 0)
1842 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1843 SDValue N0 = N->getOperand(0);
1844 SDValue N1 = N->getOperand(1);
1845 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1846 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1847 EVT VT = N->getValueType(0);
1850 if (VT.isVector()) {
1851 SDValue FoldedVOp = SimplifyVBinOp(N);
1852 if (FoldedVOp.getNode()) return FoldedVOp;
1855 // fold (sdiv c1, c2) -> c1/c2
1856 if (N0C && N1C && !N1C->isNullValue())
1857 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1858 // fold (sdiv X, 1) -> X
1859 if (N1C && N1C->getAPIntValue() == 1LL)
1861 // fold (sdiv X, -1) -> 0-X
1862 if (N1C && N1C->isAllOnesValue())
1863 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1864 DAG.getConstant(0, VT), N0);
1865 // If we know the sign bits of both operands are zero, strength reduce to a
1866 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1867 if (!VT.isVector()) {
1868 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1869 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1872 // fold (sdiv X, pow2) -> simple ops after legalize
1873 if (N1C && !N1C->isNullValue() &&
1874 (N1C->getAPIntValue().isPowerOf2() ||
1875 (-N1C->getAPIntValue()).isPowerOf2())) {
1876 // If dividing by powers of two is cheap, then don't perform the following
1878 if (TLI.isPow2DivCheap())
1881 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
1883 // Splat the sign bit into the register
1884 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1885 DAG.getConstant(VT.getSizeInBits()-1,
1886 getShiftAmountTy(N0.getValueType())));
1887 AddToWorkList(SGN.getNode());
1889 // Add (N0 < 0) ? abs2 - 1 : 0;
1890 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1891 DAG.getConstant(VT.getSizeInBits() - lg2,
1892 getShiftAmountTy(SGN.getValueType())));
1893 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1894 AddToWorkList(SRL.getNode());
1895 AddToWorkList(ADD.getNode()); // Divide by pow2
1896 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1897 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1899 // If we're dividing by a positive value, we're done. Otherwise, we must
1900 // negate the result.
1901 if (N1C->getAPIntValue().isNonNegative())
1904 AddToWorkList(SRA.getNode());
1905 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1906 DAG.getConstant(0, VT), SRA);
1909 // if integer divide is expensive and we satisfy the requirements, emit an
1910 // alternate sequence.
1911 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1912 SDValue Op = BuildSDIV(N);
1913 if (Op.getNode()) return Op;
1917 if (N0.getOpcode() == ISD::UNDEF)
1918 return DAG.getConstant(0, VT);
1919 // X / undef -> undef
1920 if (N1.getOpcode() == ISD::UNDEF)
1926 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1927 SDValue N0 = N->getOperand(0);
1928 SDValue N1 = N->getOperand(1);
1929 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1930 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1931 EVT VT = N->getValueType(0);
1934 if (VT.isVector()) {
1935 SDValue FoldedVOp = SimplifyVBinOp(N);
1936 if (FoldedVOp.getNode()) return FoldedVOp;
1939 // fold (udiv c1, c2) -> c1/c2
1940 if (N0C && N1C && !N1C->isNullValue())
1941 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1942 // fold (udiv x, (1 << c)) -> x >>u c
1943 if (N1C && N1C->getAPIntValue().isPowerOf2())
1944 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1945 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1946 getShiftAmountTy(N0.getValueType())));
1947 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1948 if (N1.getOpcode() == ISD::SHL) {
1949 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1950 if (SHC->getAPIntValue().isPowerOf2()) {
1951 EVT ADDVT = N1.getOperand(1).getValueType();
1952 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1954 DAG.getConstant(SHC->getAPIntValue()
1957 AddToWorkList(Add.getNode());
1958 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1962 // fold (udiv x, c) -> alternate
1963 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1964 SDValue Op = BuildUDIV(N);
1965 if (Op.getNode()) return Op;
1969 if (N0.getOpcode() == ISD::UNDEF)
1970 return DAG.getConstant(0, VT);
1971 // X / undef -> undef
1972 if (N1.getOpcode() == ISD::UNDEF)
1978 SDValue DAGCombiner::visitSREM(SDNode *N) {
1979 SDValue N0 = N->getOperand(0);
1980 SDValue N1 = N->getOperand(1);
1981 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1982 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1983 EVT VT = N->getValueType(0);
1985 // fold (srem c1, c2) -> c1%c2
1986 if (N0C && N1C && !N1C->isNullValue())
1987 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1988 // If we know the sign bits of both operands are zero, strength reduce to a
1989 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1990 if (!VT.isVector()) {
1991 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1992 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1995 // If X/C can be simplified by the division-by-constant logic, lower
1996 // X%C to the equivalent of X-X/C*C.
1997 if (N1C && !N1C->isNullValue()) {
1998 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1999 AddToWorkList(Div.getNode());
2000 SDValue OptimizedDiv = combine(Div.getNode());
2001 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2002 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2004 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2005 AddToWorkList(Mul.getNode());
2011 if (N0.getOpcode() == ISD::UNDEF)
2012 return DAG.getConstant(0, VT);
2013 // X % undef -> undef
2014 if (N1.getOpcode() == ISD::UNDEF)
2020 SDValue DAGCombiner::visitUREM(SDNode *N) {
2021 SDValue N0 = N->getOperand(0);
2022 SDValue N1 = N->getOperand(1);
2023 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2024 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2025 EVT VT = N->getValueType(0);
2027 // fold (urem c1, c2) -> c1%c2
2028 if (N0C && N1C && !N1C->isNullValue())
2029 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2030 // fold (urem x, pow2) -> (and x, pow2-1)
2031 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2032 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
2033 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2034 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2035 if (N1.getOpcode() == ISD::SHL) {
2036 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2037 if (SHC->getAPIntValue().isPowerOf2()) {
2039 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
2040 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2042 AddToWorkList(Add.getNode());
2043 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
2048 // If X/C can be simplified by the division-by-constant logic, lower
2049 // X%C to the equivalent of X-X/C*C.
2050 if (N1C && !N1C->isNullValue()) {
2051 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
2052 AddToWorkList(Div.getNode());
2053 SDValue OptimizedDiv = combine(Div.getNode());
2054 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2055 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2057 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2058 AddToWorkList(Mul.getNode());
2064 if (N0.getOpcode() == ISD::UNDEF)
2065 return DAG.getConstant(0, VT);
2066 // X % undef -> undef
2067 if (N1.getOpcode() == ISD::UNDEF)
2073 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2074 SDValue N0 = N->getOperand(0);
2075 SDValue N1 = N->getOperand(1);
2076 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2077 EVT VT = N->getValueType(0);
2078 DebugLoc DL = N->getDebugLoc();
2080 // fold (mulhs x, 0) -> 0
2081 if (N1C && N1C->isNullValue())
2083 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2084 if (N1C && N1C->getAPIntValue() == 1)
2085 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
2086 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2087 getShiftAmountTy(N0.getValueType())));
2088 // fold (mulhs x, undef) -> 0
2089 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2090 return DAG.getConstant(0, VT);
2092 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2094 if (VT.isSimple() && !VT.isVector()) {
2095 MVT Simple = VT.getSimpleVT();
2096 unsigned SimpleSize = Simple.getSizeInBits();
2097 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2098 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2099 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2100 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2101 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2102 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2103 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2104 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2111 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2112 SDValue N0 = N->getOperand(0);
2113 SDValue N1 = N->getOperand(1);
2114 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2115 EVT VT = N->getValueType(0);
2116 DebugLoc DL = N->getDebugLoc();
2118 // fold (mulhu x, 0) -> 0
2119 if (N1C && N1C->isNullValue())
2121 // fold (mulhu x, 1) -> 0
2122 if (N1C && N1C->getAPIntValue() == 1)
2123 return DAG.getConstant(0, N0.getValueType());
2124 // fold (mulhu x, undef) -> 0
2125 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2126 return DAG.getConstant(0, VT);
2128 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2130 if (VT.isSimple() && !VT.isVector()) {
2131 MVT Simple = VT.getSimpleVT();
2132 unsigned SimpleSize = Simple.getSizeInBits();
2133 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2134 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2135 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2136 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2137 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2138 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2139 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2140 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2147 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2148 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2149 /// that are being performed. Return true if a simplification was made.
2151 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2153 // If the high half is not needed, just compute the low half.
2154 bool HiExists = N->hasAnyUseOfValue(1);
2156 (!LegalOperations ||
2157 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2158 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2159 N->op_begin(), N->getNumOperands());
2160 return CombineTo(N, Res, Res);
2163 // If the low half is not needed, just compute the high half.
2164 bool LoExists = N->hasAnyUseOfValue(0);
2166 (!LegalOperations ||
2167 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2168 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2169 N->op_begin(), N->getNumOperands());
2170 return CombineTo(N, Res, Res);
2173 // If both halves are used, return as it is.
2174 if (LoExists && HiExists)
2177 // If the two computed results can be simplified separately, separate them.
2179 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2180 N->op_begin(), N->getNumOperands());
2181 AddToWorkList(Lo.getNode());
2182 SDValue LoOpt = combine(Lo.getNode());
2183 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2184 (!LegalOperations ||
2185 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2186 return CombineTo(N, LoOpt, LoOpt);
2190 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2191 N->op_begin(), N->getNumOperands());
2192 AddToWorkList(Hi.getNode());
2193 SDValue HiOpt = combine(Hi.getNode());
2194 if (HiOpt.getNode() && HiOpt != Hi &&
2195 (!LegalOperations ||
2196 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2197 return CombineTo(N, HiOpt, HiOpt);
2203 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2204 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2205 if (Res.getNode()) return Res;
2207 EVT VT = N->getValueType(0);
2208 DebugLoc DL = N->getDebugLoc();
2210 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2212 if (VT.isSimple() && !VT.isVector()) {
2213 MVT Simple = VT.getSimpleVT();
2214 unsigned SimpleSize = Simple.getSizeInBits();
2215 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2216 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2217 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2218 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2219 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2220 // Compute the high part as N1.
2221 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2222 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2223 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2224 // Compute the low part as N0.
2225 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2226 return CombineTo(N, Lo, Hi);
2233 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2234 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2235 if (Res.getNode()) return Res;
2237 EVT VT = N->getValueType(0);
2238 DebugLoc DL = N->getDebugLoc();
2240 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2242 if (VT.isSimple() && !VT.isVector()) {
2243 MVT Simple = VT.getSimpleVT();
2244 unsigned SimpleSize = Simple.getSizeInBits();
2245 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2246 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2247 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2248 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2249 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2250 // Compute the high part as N1.
2251 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2252 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2253 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2254 // Compute the low part as N0.
2255 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2256 return CombineTo(N, Lo, Hi);
2263 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2264 // (smulo x, 2) -> (saddo x, x)
2265 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2266 if (C2->getAPIntValue() == 2)
2267 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2268 N->getOperand(0), N->getOperand(0));
2273 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2274 // (umulo x, 2) -> (uaddo x, x)
2275 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2276 if (C2->getAPIntValue() == 2)
2277 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2278 N->getOperand(0), N->getOperand(0));
2283 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2284 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2285 if (Res.getNode()) return Res;
2290 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2291 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2292 if (Res.getNode()) return Res;
2297 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2298 /// two operands of the same opcode, try to simplify it.
2299 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2300 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2301 EVT VT = N0.getValueType();
2302 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2304 // Bail early if none of these transforms apply.
2305 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2307 // For each of OP in AND/OR/XOR:
2308 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2309 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2310 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2311 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2313 // do not sink logical op inside of a vector extend, since it may combine
2315 EVT Op0VT = N0.getOperand(0).getValueType();
2316 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2317 N0.getOpcode() == ISD::SIGN_EXTEND ||
2318 // Avoid infinite looping with PromoteIntBinOp.
2319 (N0.getOpcode() == ISD::ANY_EXTEND &&
2320 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2321 (N0.getOpcode() == ISD::TRUNCATE &&
2322 (!TLI.isZExtFree(VT, Op0VT) ||
2323 !TLI.isTruncateFree(Op0VT, VT)) &&
2324 TLI.isTypeLegal(Op0VT))) &&
2326 Op0VT == N1.getOperand(0).getValueType() &&
2327 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2328 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2329 N0.getOperand(0).getValueType(),
2330 N0.getOperand(0), N1.getOperand(0));
2331 AddToWorkList(ORNode.getNode());
2332 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2335 // For each of OP in SHL/SRL/SRA/AND...
2336 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2337 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2338 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2339 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2340 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2341 N0.getOperand(1) == N1.getOperand(1)) {
2342 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2343 N0.getOperand(0).getValueType(),
2344 N0.getOperand(0), N1.getOperand(0));
2345 AddToWorkList(ORNode.getNode());
2346 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2347 ORNode, N0.getOperand(1));
2350 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2351 // Only perform this optimization after type legalization and before
2352 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2353 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2354 // we don't want to undo this promotion.
2355 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2357 if ((N0.getOpcode() == ISD::BITCAST ||
2358 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2359 Level == AfterLegalizeTypes) {
2360 SDValue In0 = N0.getOperand(0);
2361 SDValue In1 = N1.getOperand(0);
2362 EVT In0Ty = In0.getValueType();
2363 EVT In1Ty = In1.getValueType();
2364 DebugLoc DL = N->getDebugLoc();
2365 // If both incoming values are integers, and the original types are the
2367 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2368 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2369 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2370 AddToWorkList(Op.getNode());
2375 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2376 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2377 // If both shuffles use the same mask, and both shuffle within a single
2378 // vector, then it is worthwhile to move the swizzle after the operation.
2379 // The type-legalizer generates this pattern when loading illegal
2380 // vector types from memory. In many cases this allows additional shuffle
2382 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
2383 N0.getOperand(1).getOpcode() == ISD::UNDEF &&
2384 N1.getOperand(1).getOpcode() == ISD::UNDEF) {
2385 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2386 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2388 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() &&
2389 "Inputs to shuffles are not the same type");
2391 unsigned NumElts = VT.getVectorNumElements();
2393 // Check that both shuffles use the same mask. The masks are known to be of
2394 // the same length because the result vector type is the same.
2395 bool SameMask = true;
2396 for (unsigned i = 0; i != NumElts; ++i) {
2397 int Idx0 = SVN0->getMaskElt(i);
2398 int Idx1 = SVN1->getMaskElt(i);
2406 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT,
2407 N0.getOperand(0), N1.getOperand(0));
2408 AddToWorkList(Op.getNode());
2409 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op,
2410 DAG.getUNDEF(VT), &SVN0->getMask()[0]);
2417 SDValue DAGCombiner::visitAND(SDNode *N) {
2418 SDValue N0 = N->getOperand(0);
2419 SDValue N1 = N->getOperand(1);
2420 SDValue LL, LR, RL, RR, CC0, CC1;
2421 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2422 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2423 EVT VT = N1.getValueType();
2424 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2427 if (VT.isVector()) {
2428 SDValue FoldedVOp = SimplifyVBinOp(N);
2429 if (FoldedVOp.getNode()) return FoldedVOp;
2431 // fold (and x, 0) -> 0, vector edition
2432 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2434 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2437 // fold (and x, -1) -> x, vector edition
2438 if (ISD::isBuildVectorAllOnes(N0.getNode()))
2440 if (ISD::isBuildVectorAllOnes(N1.getNode()))
2444 // fold (and x, undef) -> 0
2445 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2446 return DAG.getConstant(0, VT);
2447 // fold (and c1, c2) -> c1&c2
2449 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2450 // canonicalize constant to RHS
2452 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2453 // fold (and x, -1) -> x
2454 if (N1C && N1C->isAllOnesValue())
2456 // if (and x, c) is known to be zero, return 0
2457 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2458 APInt::getAllOnesValue(BitWidth)))
2459 return DAG.getConstant(0, VT);
2461 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2462 if (RAND.getNode() != 0)
2464 // fold (and (or x, C), D) -> D if (C & D) == D
2465 if (N1C && N0.getOpcode() == ISD::OR)
2466 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2467 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2469 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2470 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2471 SDValue N0Op0 = N0.getOperand(0);
2472 APInt Mask = ~N1C->getAPIntValue();
2473 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2474 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2475 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2476 N0.getValueType(), N0Op0);
2478 // Replace uses of the AND with uses of the Zero extend node.
2481 // We actually want to replace all uses of the any_extend with the
2482 // zero_extend, to avoid duplicating things. This will later cause this
2483 // AND to be folded.
2484 CombineTo(N0.getNode(), Zext);
2485 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2488 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2489 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2490 // already be zero by virtue of the width of the base type of the load.
2492 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2494 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2495 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2496 N0.getOpcode() == ISD::LOAD) {
2497 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2498 N0 : N0.getOperand(0) );
2500 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2501 // This can be a pure constant or a vector splat, in which case we treat the
2502 // vector as a scalar and use the splat value.
2503 APInt Constant = APInt::getNullValue(1);
2504 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2505 Constant = C->getAPIntValue();
2506 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2507 APInt SplatValue, SplatUndef;
2508 unsigned SplatBitSize;
2510 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2511 SplatBitSize, HasAnyUndefs);
2513 // Undef bits can contribute to a possible optimisation if set, so
2515 SplatValue |= SplatUndef;
2517 // The splat value may be something like "0x00FFFFFF", which means 0 for
2518 // the first vector value and FF for the rest, repeating. We need a mask
2519 // that will apply equally to all members of the vector, so AND all the
2520 // lanes of the constant together.
2521 EVT VT = Vector->getValueType(0);
2522 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2524 // If the splat value has been compressed to a bitlength lower
2525 // than the size of the vector lane, we need to re-expand it to
2527 if (BitWidth > SplatBitSize)
2528 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
2529 SplatBitSize < BitWidth;
2530 SplatBitSize = SplatBitSize * 2)
2531 SplatValue |= SplatValue.shl(SplatBitSize);
2533 Constant = APInt::getAllOnesValue(BitWidth);
2534 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
2535 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2539 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2540 // actually legal and isn't going to get expanded, else this is a false
2542 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2543 Load->getMemoryVT());
2545 // Resize the constant to the same size as the original memory access before
2546 // extension. If it is still the AllOnesValue then this AND is completely
2549 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2552 switch (Load->getExtensionType()) {
2553 default: B = false; break;
2554 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2556 case ISD::NON_EXTLOAD: B = true; break;
2559 if (B && Constant.isAllOnesValue()) {
2560 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2561 // preserve semantics once we get rid of the AND.
2562 SDValue NewLoad(Load, 0);
2563 if (Load->getExtensionType() == ISD::EXTLOAD) {
2564 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2565 Load->getValueType(0), Load->getDebugLoc(),
2566 Load->getChain(), Load->getBasePtr(),
2567 Load->getOffset(), Load->getMemoryVT(),
2568 Load->getMemOperand());
2569 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2570 if (Load->getNumValues() == 3) {
2571 // PRE/POST_INC loads have 3 values.
2572 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
2573 NewLoad.getValue(2) };
2574 CombineTo(Load, To, 3, true);
2576 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2580 // Fold the AND away, taking care not to fold to the old load node if we
2582 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2584 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2587 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2588 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2589 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2590 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2592 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2593 LL.getValueType().isInteger()) {
2594 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2595 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2596 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2597 LR.getValueType(), LL, RL);
2598 AddToWorkList(ORNode.getNode());
2599 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2601 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2602 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2603 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2604 LR.getValueType(), LL, RL);
2605 AddToWorkList(ANDNode.getNode());
2606 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2608 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2609 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2610 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2611 LR.getValueType(), LL, RL);
2612 AddToWorkList(ORNode.getNode());
2613 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2616 // canonicalize equivalent to ll == rl
2617 if (LL == RR && LR == RL) {
2618 Op1 = ISD::getSetCCSwappedOperands(Op1);
2621 if (LL == RL && LR == RR) {
2622 bool isInteger = LL.getValueType().isInteger();
2623 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2624 if (Result != ISD::SETCC_INVALID &&
2625 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2626 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2631 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2632 if (N0.getOpcode() == N1.getOpcode()) {
2633 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2634 if (Tmp.getNode()) return Tmp;
2637 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2638 // fold (and (sra)) -> (and (srl)) when possible.
2639 if (!VT.isVector() &&
2640 SimplifyDemandedBits(SDValue(N, 0)))
2641 return SDValue(N, 0);
2643 // fold (zext_inreg (extload x)) -> (zextload x)
2644 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2645 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2646 EVT MemVT = LN0->getMemoryVT();
2647 // If we zero all the possible extended bits, then we can turn this into
2648 // a zextload if we are running before legalize or the operation is legal.
2649 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2650 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2651 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2652 ((!LegalOperations && !LN0->isVolatile()) ||
2653 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2654 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2655 LN0->getChain(), LN0->getBasePtr(),
2656 LN0->getPointerInfo(), MemVT,
2657 LN0->isVolatile(), LN0->isNonTemporal(),
2658 LN0->getAlignment());
2660 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2661 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2664 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2665 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2667 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2668 EVT MemVT = LN0->getMemoryVT();
2669 // If we zero all the possible extended bits, then we can turn this into
2670 // a zextload if we are running before legalize or the operation is legal.
2671 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2672 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2673 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2674 ((!LegalOperations && !LN0->isVolatile()) ||
2675 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2676 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2678 LN0->getBasePtr(), LN0->getPointerInfo(),
2680 LN0->isVolatile(), LN0->isNonTemporal(),
2681 LN0->getAlignment());
2683 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2684 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2688 // fold (and (load x), 255) -> (zextload x, i8)
2689 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2690 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2691 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2692 (N0.getOpcode() == ISD::ANY_EXTEND &&
2693 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2694 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2695 LoadSDNode *LN0 = HasAnyExt
2696 ? cast<LoadSDNode>(N0.getOperand(0))
2697 : cast<LoadSDNode>(N0);
2698 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2699 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2700 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2701 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2702 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2703 EVT LoadedVT = LN0->getMemoryVT();
2705 if (ExtVT == LoadedVT &&
2706 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2707 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2710 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2711 LN0->getChain(), LN0->getBasePtr(),
2712 LN0->getPointerInfo(),
2713 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2714 LN0->getAlignment());
2716 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2717 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2720 // Do not change the width of a volatile load.
2721 // Do not generate loads of non-round integer types since these can
2722 // be expensive (and would be wrong if the type is not byte sized).
2723 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2724 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2725 EVT PtrType = LN0->getOperand(1).getValueType();
2727 unsigned Alignment = LN0->getAlignment();
2728 SDValue NewPtr = LN0->getBasePtr();
2730 // For big endian targets, we need to add an offset to the pointer
2731 // to load the correct bytes. For little endian systems, we merely
2732 // need to read fewer bytes from the same pointer.
2733 if (TLI.isBigEndian()) {
2734 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2735 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2736 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2737 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2738 NewPtr, DAG.getConstant(PtrOff, PtrType));
2739 Alignment = MinAlign(Alignment, PtrOff);
2742 AddToWorkList(NewPtr.getNode());
2744 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2746 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2747 LN0->getChain(), NewPtr,
2748 LN0->getPointerInfo(),
2749 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2752 CombineTo(LN0, Load, Load.getValue(1));
2753 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2759 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2760 VT.getSizeInBits() <= 64) {
2761 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2762 APInt ADDC = ADDI->getAPIntValue();
2763 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2764 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
2765 // immediate for an add, but it is legal if its top c2 bits are set,
2766 // transform the ADD so the immediate doesn't need to be materialized
2768 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
2769 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
2770 SRLI->getZExtValue());
2771 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
2773 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2775 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
2776 N0.getOperand(0), DAG.getConstant(ADDC, VT));
2777 CombineTo(N0.getNode(), NewAdd);
2778 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2790 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2792 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2793 bool DemandHighBits) {
2794 if (!LegalOperations)
2797 EVT VT = N->getValueType(0);
2798 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2800 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2803 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2804 bool LookPassAnd0 = false;
2805 bool LookPassAnd1 = false;
2806 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2808 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2810 if (N0.getOpcode() == ISD::AND) {
2811 if (!N0.getNode()->hasOneUse())
2813 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2814 if (!N01C || N01C->getZExtValue() != 0xFF00)
2816 N0 = N0.getOperand(0);
2817 LookPassAnd0 = true;
2820 if (N1.getOpcode() == ISD::AND) {
2821 if (!N1.getNode()->hasOneUse())
2823 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2824 if (!N11C || N11C->getZExtValue() != 0xFF)
2826 N1 = N1.getOperand(0);
2827 LookPassAnd1 = true;
2830 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2832 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2834 if (!N0.getNode()->hasOneUse() ||
2835 !N1.getNode()->hasOneUse())
2838 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2839 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2842 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2845 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2846 SDValue N00 = N0->getOperand(0);
2847 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2848 if (!N00.getNode()->hasOneUse())
2850 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2851 if (!N001C || N001C->getZExtValue() != 0xFF)
2853 N00 = N00.getOperand(0);
2854 LookPassAnd0 = true;
2857 SDValue N10 = N1->getOperand(0);
2858 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2859 if (!N10.getNode()->hasOneUse())
2861 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2862 if (!N101C || N101C->getZExtValue() != 0xFF00)
2864 N10 = N10.getOperand(0);
2865 LookPassAnd1 = true;
2871 // Make sure everything beyond the low halfword is zero since the SRL 16
2872 // will clear the top bits.
2873 unsigned OpSizeInBits = VT.getSizeInBits();
2874 if (DemandHighBits && OpSizeInBits > 16 &&
2875 (!LookPassAnd0 || !LookPassAnd1) &&
2876 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
2879 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
2880 if (OpSizeInBits > 16)
2881 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2882 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2886 /// isBSwapHWordElement - Return true if the specified node is an element
2887 /// that makes up a 32-bit packed halfword byteswap. i.e.
2888 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2889 static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
2890 if (!N.getNode()->hasOneUse())
2893 unsigned Opc = N.getOpcode();
2894 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2897 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2902 switch (N1C->getZExtValue()) {
2905 case 0xFF: Num = 0; break;
2906 case 0xFF00: Num = 1; break;
2907 case 0xFF0000: Num = 2; break;
2908 case 0xFF000000: Num = 3; break;
2911 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
2912 SDValue N0 = N.getOperand(0);
2913 if (Opc == ISD::AND) {
2914 if (Num == 0 || Num == 2) {
2916 // (x >> 8) & 0xff0000
2917 if (N0.getOpcode() != ISD::SRL)
2919 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2920 if (!C || C->getZExtValue() != 8)
2923 // (x << 8) & 0xff00
2924 // (x << 8) & 0xff000000
2925 if (N0.getOpcode() != ISD::SHL)
2927 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2928 if (!C || C->getZExtValue() != 8)
2931 } else if (Opc == ISD::SHL) {
2933 // (x & 0xff0000) << 8
2934 if (Num != 0 && Num != 2)
2936 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2937 if (!C || C->getZExtValue() != 8)
2939 } else { // Opc == ISD::SRL
2940 // (x & 0xff00) >> 8
2941 // (x & 0xff000000) >> 8
2942 if (Num != 1 && Num != 3)
2944 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2945 if (!C || C->getZExtValue() != 8)
2952 Parts[Num] = N0.getOperand(0).getNode();
2956 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
2957 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2958 /// => (rotl (bswap x), 16)
2959 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2960 if (!LegalOperations)
2963 EVT VT = N->getValueType(0);
2966 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2969 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
2971 // (or (or (and), (and)), (or (and), (and)))
2972 // (or (or (or (and), (and)), (and)), (and))
2973 if (N0.getOpcode() != ISD::OR)
2975 SDValue N00 = N0.getOperand(0);
2976 SDValue N01 = N0.getOperand(1);
2978 if (N1.getOpcode() == ISD::OR) {
2979 // (or (or (and), (and)), (or (and), (and)))
2980 SDValue N000 = N00.getOperand(0);
2981 if (!isBSwapHWordElement(N000, Parts))
2984 SDValue N001 = N00.getOperand(1);
2985 if (!isBSwapHWordElement(N001, Parts))
2987 SDValue N010 = N01.getOperand(0);
2988 if (!isBSwapHWordElement(N010, Parts))
2990 SDValue N011 = N01.getOperand(1);
2991 if (!isBSwapHWordElement(N011, Parts))
2994 // (or (or (or (and), (and)), (and)), (and))
2995 if (!isBSwapHWordElement(N1, Parts))
2997 if (!isBSwapHWordElement(N01, Parts))
2999 if (N00.getOpcode() != ISD::OR)
3001 SDValue N000 = N00.getOperand(0);
3002 if (!isBSwapHWordElement(N000, Parts))
3004 SDValue N001 = N00.getOperand(1);
3005 if (!isBSwapHWordElement(N001, Parts))
3009 // Make sure the parts are all coming from the same node.
3010 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
3013 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
3014 SDValue(Parts[0],0));
3016 // Result of the bswap should be rotated by 16. If it's not legal, than
3017 // do (x << 16) | (x >> 16).
3018 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
3019 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3020 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
3021 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3022 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
3023 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
3024 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
3025 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
3028 SDValue DAGCombiner::visitOR(SDNode *N) {
3029 SDValue N0 = N->getOperand(0);
3030 SDValue N1 = N->getOperand(1);
3031 SDValue LL, LR, RL, RR, CC0, CC1;
3032 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3033 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3034 EVT VT = N1.getValueType();
3037 if (VT.isVector()) {
3038 SDValue FoldedVOp = SimplifyVBinOp(N);
3039 if (FoldedVOp.getNode()) return FoldedVOp;
3041 // fold (or x, 0) -> x, vector edition
3042 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3044 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3047 // fold (or x, -1) -> -1, vector edition
3048 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3050 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3054 // fold (or x, undef) -> -1
3055 if (!LegalOperations &&
3056 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3057 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3058 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
3060 // fold (or c1, c2) -> c1|c2
3062 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
3063 // canonicalize constant to RHS
3065 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
3066 // fold (or x, 0) -> x
3067 if (N1C && N1C->isNullValue())
3069 // fold (or x, -1) -> -1
3070 if (N1C && N1C->isAllOnesValue())
3072 // fold (or x, c) -> c iff (x & ~c) == 0
3073 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3076 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3077 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3078 if (BSwap.getNode() != 0)
3080 BSwap = MatchBSwapHWordLow(N, N0, N1);
3081 if (BSwap.getNode() != 0)
3085 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
3086 if (ROR.getNode() != 0)
3088 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3089 // iff (c1 & c2) == 0.
3090 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3091 isa<ConstantSDNode>(N0.getOperand(1))) {
3092 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3093 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
3094 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3095 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3096 N0.getOperand(0), N1),
3097 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
3099 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3100 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3101 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3102 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3104 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3105 LL.getValueType().isInteger()) {
3106 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3107 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3108 if (cast<ConstantSDNode>(LR)->isNullValue() &&
3109 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3110 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
3111 LR.getValueType(), LL, RL);
3112 AddToWorkList(ORNode.getNode());
3113 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
3115 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3116 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3117 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
3118 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3119 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
3120 LR.getValueType(), LL, RL);
3121 AddToWorkList(ANDNode.getNode());
3122 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
3125 // canonicalize equivalent to ll == rl
3126 if (LL == RR && LR == RL) {
3127 Op1 = ISD::getSetCCSwappedOperands(Op1);
3130 if (LL == RL && LR == RR) {
3131 bool isInteger = LL.getValueType().isInteger();
3132 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3133 if (Result != ISD::SETCC_INVALID &&
3134 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
3135 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
3140 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3141 if (N0.getOpcode() == N1.getOpcode()) {
3142 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3143 if (Tmp.getNode()) return Tmp;
3146 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3147 if (N0.getOpcode() == ISD::AND &&
3148 N1.getOpcode() == ISD::AND &&
3149 N0.getOperand(1).getOpcode() == ISD::Constant &&
3150 N1.getOperand(1).getOpcode() == ISD::Constant &&
3151 // Don't increase # computations.
3152 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3153 // We can only do this xform if we know that bits from X that are set in C2
3154 // but not in C1 are already zero. Likewise for Y.
3155 const APInt &LHSMask =
3156 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3157 const APInt &RHSMask =
3158 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3160 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3161 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3162 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3163 N0.getOperand(0), N1.getOperand(0));
3164 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
3165 DAG.getConstant(LHSMask | RHSMask, VT));
3169 // See if this is some rotate idiom.
3170 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
3171 return SDValue(Rot, 0);
3173 // Simplify the operands using demanded-bits information.
3174 if (!VT.isVector() &&
3175 SimplifyDemandedBits(SDValue(N, 0)))
3176 return SDValue(N, 0);
3181 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
3182 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3183 if (Op.getOpcode() == ISD::AND) {
3184 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3185 Mask = Op.getOperand(1);
3186 Op = Op.getOperand(0);
3192 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3200 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3201 // idioms for rotate, and if the target supports rotation instructions, generate
3203 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
3204 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3205 EVT VT = LHS.getValueType();
3206 if (!TLI.isTypeLegal(VT)) return 0;
3208 // The target must have at least one rotate flavor.
3209 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3210 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3211 if (!HasROTL && !HasROTR) return 0;
3213 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3214 SDValue LHSShift; // The shift.
3215 SDValue LHSMask; // AND value if any.
3216 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3217 return 0; // Not part of a rotate.
3219 SDValue RHSShift; // The shift.
3220 SDValue RHSMask; // AND value if any.
3221 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3222 return 0; // Not part of a rotate.
3224 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3225 return 0; // Not shifting the same value.
3227 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3228 return 0; // Shifts must disagree.
3230 // Canonicalize shl to left side in a shl/srl pair.
3231 if (RHSShift.getOpcode() == ISD::SHL) {
3232 std::swap(LHS, RHS);
3233 std::swap(LHSShift, RHSShift);
3234 std::swap(LHSMask , RHSMask );
3237 unsigned OpSizeInBits = VT.getSizeInBits();
3238 SDValue LHSShiftArg = LHSShift.getOperand(0);
3239 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3240 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3242 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3243 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3244 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3245 RHSShiftAmt.getOpcode() == ISD::Constant) {
3246 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3247 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3248 if ((LShVal + RShVal) != OpSizeInBits)
3251 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3252 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
3254 // If there is an AND of either shifted operand, apply it to the result.
3255 if (LHSMask.getNode() || RHSMask.getNode()) {
3256 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3258 if (LHSMask.getNode()) {
3259 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3260 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3262 if (RHSMask.getNode()) {
3263 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3264 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3267 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3270 return Rot.getNode();
3273 // If there is a mask here, and we have a variable shift, we can't be sure
3274 // that we're masking out the right stuff.
3275 if (LHSMask.getNode() || RHSMask.getNode())
3278 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
3279 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
3280 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
3281 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
3282 if (ConstantSDNode *SUBC =
3283 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
3284 if (SUBC->getAPIntValue() == OpSizeInBits) {
3285 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg,
3286 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3291 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
3292 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
3293 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
3294 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
3295 if (ConstantSDNode *SUBC =
3296 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
3297 if (SUBC->getAPIntValue() == OpSizeInBits) {
3298 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg,
3299 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3304 // Look for sign/zext/any-extended or truncate cases:
3305 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3306 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3307 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3308 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3309 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3310 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3311 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3312 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3313 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
3314 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
3315 if (RExtOp0.getOpcode() == ISD::SUB &&
3316 RExtOp0.getOperand(1) == LExtOp0) {
3317 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3319 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3320 // (rotr x, (sub 32, y))
3321 if (ConstantSDNode *SUBC =
3322 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3323 if (SUBC->getAPIntValue() == OpSizeInBits) {
3324 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3326 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3329 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3330 RExtOp0 == LExtOp0.getOperand(1)) {
3331 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3333 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3334 // (rotl x, (sub 32, y))
3335 if (ConstantSDNode *SUBC =
3336 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3337 if (SUBC->getAPIntValue() == OpSizeInBits) {
3338 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3340 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3349 SDValue DAGCombiner::visitXOR(SDNode *N) {
3350 SDValue N0 = N->getOperand(0);
3351 SDValue N1 = N->getOperand(1);
3352 SDValue LHS, RHS, CC;
3353 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3354 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3355 EVT VT = N0.getValueType();
3358 if (VT.isVector()) {
3359 SDValue FoldedVOp = SimplifyVBinOp(N);
3360 if (FoldedVOp.getNode()) return FoldedVOp;
3362 // fold (xor x, 0) -> x, vector edition
3363 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3365 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3369 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3370 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3371 return DAG.getConstant(0, VT);
3372 // fold (xor x, undef) -> undef
3373 if (N0.getOpcode() == ISD::UNDEF)
3375 if (N1.getOpcode() == ISD::UNDEF)
3377 // fold (xor c1, c2) -> c1^c2
3379 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3380 // canonicalize constant to RHS
3382 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3383 // fold (xor x, 0) -> x
3384 if (N1C && N1C->isNullValue())
3387 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3388 if (RXOR.getNode() != 0)
3391 // fold !(x cc y) -> (x !cc y)
3392 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3393 bool isInt = LHS.getValueType().isInteger();
3394 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3397 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
3398 switch (N0.getOpcode()) {
3400 llvm_unreachable("Unhandled SetCC Equivalent!");
3402 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
3403 case ISD::SELECT_CC:
3404 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
3405 N0.getOperand(3), NotCC);
3410 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3411 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3412 N0.getNode()->hasOneUse() &&
3413 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3414 SDValue V = N0.getOperand(0);
3415 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3416 DAG.getConstant(1, V.getValueType()));
3417 AddToWorkList(V.getNode());
3418 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
3421 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3422 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3423 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3424 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3425 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3426 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3427 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3428 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3429 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3430 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3433 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3434 if (N1C && N1C->isAllOnesValue() &&
3435 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3436 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3437 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3438 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3439 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3440 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3441 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3442 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3445 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3446 if (N1C && N0.getOpcode() == ISD::XOR) {
3447 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3448 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3450 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3451 DAG.getConstant(N1C->getAPIntValue() ^
3452 N00C->getAPIntValue(), VT));
3454 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3455 DAG.getConstant(N1C->getAPIntValue() ^
3456 N01C->getAPIntValue(), VT));
3458 // fold (xor x, x) -> 0
3460 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
3462 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3463 if (N0.getOpcode() == N1.getOpcode()) {
3464 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3465 if (Tmp.getNode()) return Tmp;
3468 // Simplify the expression using non-local knowledge.
3469 if (!VT.isVector() &&
3470 SimplifyDemandedBits(SDValue(N, 0)))
3471 return SDValue(N, 0);
3476 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3477 /// the shift amount is a constant.
3478 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3479 SDNode *LHS = N->getOperand(0).getNode();
3480 if (!LHS->hasOneUse()) return SDValue();
3482 // We want to pull some binops through shifts, so that we have (and (shift))
3483 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3484 // thing happens with address calculations, so it's important to canonicalize
3486 bool HighBitSet = false; // Can we transform this if the high bit is set?
3488 switch (LHS->getOpcode()) {
3489 default: return SDValue();
3492 HighBitSet = false; // We can only transform sra if the high bit is clear.
3495 HighBitSet = true; // We can only transform sra if the high bit is set.
3498 if (N->getOpcode() != ISD::SHL)
3499 return SDValue(); // only shl(add) not sr[al](add).
3500 HighBitSet = false; // We can only transform sra if the high bit is clear.
3504 // We require the RHS of the binop to be a constant as well.
3505 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3506 if (!BinOpCst) return SDValue();
3508 // FIXME: disable this unless the input to the binop is a shift by a constant.
3509 // If it is not a shift, it pessimizes some common cases like:
3511 // void foo(int *X, int i) { X[i & 1235] = 1; }
3512 // int bar(int *X, int i) { return X[i & 255]; }
3513 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3514 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3515 BinOpLHSVal->getOpcode() != ISD::SRA &&
3516 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3517 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3520 EVT VT = N->getValueType(0);
3522 // If this is a signed shift right, and the high bit is modified by the
3523 // logical operation, do not perform the transformation. The highBitSet
3524 // boolean indicates the value of the high bit of the constant which would
3525 // cause it to be modified for this operation.
3526 if (N->getOpcode() == ISD::SRA) {
3527 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3528 if (BinOpRHSSignSet != HighBitSet)
3532 // Fold the constants, shifting the binop RHS by the shift amount.
3533 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
3535 LHS->getOperand(1), N->getOperand(1));
3537 // Create the new shift.
3538 SDValue NewShift = DAG.getNode(N->getOpcode(),
3539 LHS->getOperand(0).getDebugLoc(),
3540 VT, LHS->getOperand(0), N->getOperand(1));
3542 // Create the new binop.
3543 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
3546 SDValue DAGCombiner::visitSHL(SDNode *N) {
3547 SDValue N0 = N->getOperand(0);
3548 SDValue N1 = N->getOperand(1);
3549 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3550 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3551 EVT VT = N0.getValueType();
3552 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3554 // fold (shl c1, c2) -> c1<<c2
3556 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3557 // fold (shl 0, x) -> 0
3558 if (N0C && N0C->isNullValue())
3560 // fold (shl x, c >= size(x)) -> undef
3561 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3562 return DAG.getUNDEF(VT);
3563 // fold (shl x, 0) -> x
3564 if (N1C && N1C->isNullValue())
3566 // fold (shl undef, x) -> 0
3567 if (N0.getOpcode() == ISD::UNDEF)
3568 return DAG.getConstant(0, VT);
3569 // if (shl x, c) is known to be zero, return 0
3570 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3571 APInt::getAllOnesValue(OpSizeInBits)))
3572 return DAG.getConstant(0, VT);
3573 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3574 if (N1.getOpcode() == ISD::TRUNCATE &&
3575 N1.getOperand(0).getOpcode() == ISD::AND &&
3576 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3577 SDValue N101 = N1.getOperand(0).getOperand(1);
3578 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3579 EVT TruncVT = N1.getValueType();
3580 SDValue N100 = N1.getOperand(0).getOperand(0);
3581 APInt TruncC = N101C->getAPIntValue();
3582 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3583 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3584 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3585 DAG.getNode(ISD::TRUNCATE,
3588 DAG.getConstant(TruncC, TruncVT)));
3592 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3593 return SDValue(N, 0);
3595 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3596 if (N1C && N0.getOpcode() == ISD::SHL &&
3597 N0.getOperand(1).getOpcode() == ISD::Constant) {
3598 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3599 uint64_t c2 = N1C->getZExtValue();
3600 if (c1 + c2 >= OpSizeInBits)
3601 return DAG.getConstant(0, VT);
3602 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3603 DAG.getConstant(c1 + c2, N1.getValueType()));
3606 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3607 // For this to be valid, the second form must not preserve any of the bits
3608 // that are shifted out by the inner shift in the first form. This means
3609 // the outer shift size must be >= the number of bits added by the ext.
3610 // As a corollary, we don't care what kind of ext it is.
3611 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3612 N0.getOpcode() == ISD::ANY_EXTEND ||
3613 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3614 N0.getOperand(0).getOpcode() == ISD::SHL &&
3615 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3617 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3618 uint64_t c2 = N1C->getZExtValue();
3619 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3620 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3621 if (c2 >= OpSizeInBits - InnerShiftSize) {
3622 if (c1 + c2 >= OpSizeInBits)
3623 return DAG.getConstant(0, VT);
3624 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3625 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3626 N0.getOperand(0)->getOperand(0)),
3627 DAG.getConstant(c1 + c2, N1.getValueType()));
3631 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3632 // (and (srl x, (sub c1, c2), MASK)
3633 // Only fold this if the inner shift has no other uses -- if it does, folding
3634 // this will increase the total number of instructions.
3635 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3636 N0.getOperand(1).getOpcode() == ISD::Constant) {
3637 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3638 if (c1 < VT.getSizeInBits()) {
3639 uint64_t c2 = N1C->getZExtValue();
3640 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3641 VT.getSizeInBits() - c1);
3644 Mask = Mask.shl(c2-c1);
3645 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3646 DAG.getConstant(c2-c1, N1.getValueType()));
3648 Mask = Mask.lshr(c1-c2);
3649 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3650 DAG.getConstant(c1-c2, N1.getValueType()));
3652 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3653 DAG.getConstant(Mask, VT));
3656 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3657 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3658 SDValue HiBitsMask =
3659 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3660 VT.getSizeInBits() -
3661 N1C->getZExtValue()),
3663 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3668 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3669 if (NewSHL.getNode())
3676 SDValue DAGCombiner::visitSRA(SDNode *N) {
3677 SDValue N0 = N->getOperand(0);
3678 SDValue N1 = N->getOperand(1);
3679 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3680 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3681 EVT VT = N0.getValueType();
3682 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3684 // fold (sra c1, c2) -> (sra c1, c2)
3686 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3687 // fold (sra 0, x) -> 0
3688 if (N0C && N0C->isNullValue())
3690 // fold (sra -1, x) -> -1
3691 if (N0C && N0C->isAllOnesValue())
3693 // fold (sra x, (setge c, size(x))) -> undef
3694 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3695 return DAG.getUNDEF(VT);
3696 // fold (sra x, 0) -> x
3697 if (N1C && N1C->isNullValue())
3699 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3701 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3702 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3703 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3705 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3706 ExtVT, VT.getVectorNumElements());
3707 if ((!LegalOperations ||
3708 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3709 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3710 N0.getOperand(0), DAG.getValueType(ExtVT));
3713 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3714 if (N1C && N0.getOpcode() == ISD::SRA) {
3715 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3716 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3717 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3718 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3719 DAG.getConstant(Sum, N1C->getValueType(0)));
3723 // fold (sra (shl X, m), (sub result_size, n))
3724 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3725 // result_size - n != m.
3726 // If truncate is free for the target sext(shl) is likely to result in better
3728 if (N0.getOpcode() == ISD::SHL) {
3729 // Get the two constanst of the shifts, CN0 = m, CN = n.
3730 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3732 // Determine what the truncate's result bitsize and type would be.
3734 EVT::getIntegerVT(*DAG.getContext(),
3735 OpSizeInBits - N1C->getZExtValue());
3736 // Determine the residual right-shift amount.
3737 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3739 // If the shift is not a no-op (in which case this should be just a sign
3740 // extend already), the truncated to type is legal, sign_extend is legal
3741 // on that type, and the truncate to that type is both legal and free,
3742 // perform the transform.
3743 if ((ShiftAmt > 0) &&
3744 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3745 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3746 TLI.isTruncateFree(VT, TruncVT)) {
3748 SDValue Amt = DAG.getConstant(ShiftAmt,
3749 getShiftAmountTy(N0.getOperand(0).getValueType()));
3750 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3751 N0.getOperand(0), Amt);
3752 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3754 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3755 N->getValueType(0), Trunc);
3760 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3761 if (N1.getOpcode() == ISD::TRUNCATE &&
3762 N1.getOperand(0).getOpcode() == ISD::AND &&
3763 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3764 SDValue N101 = N1.getOperand(0).getOperand(1);
3765 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3766 EVT TruncVT = N1.getValueType();
3767 SDValue N100 = N1.getOperand(0).getOperand(0);
3768 APInt TruncC = N101C->getAPIntValue();
3769 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3770 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3771 DAG.getNode(ISD::AND, N->getDebugLoc(),
3773 DAG.getNode(ISD::TRUNCATE,
3776 DAG.getConstant(TruncC, TruncVT)));
3780 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3781 // if c1 is equal to the number of bits the trunc removes
3782 if (N0.getOpcode() == ISD::TRUNCATE &&
3783 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3784 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3785 N0.getOperand(0).hasOneUse() &&
3786 N0.getOperand(0).getOperand(1).hasOneUse() &&
3787 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3788 EVT LargeVT = N0.getOperand(0).getValueType();
3789 ConstantSDNode *LargeShiftAmt =
3790 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3792 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3793 LargeShiftAmt->getZExtValue()) {
3795 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3796 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3797 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3798 N0.getOperand(0).getOperand(0), Amt);
3799 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3803 // Simplify, based on bits shifted out of the LHS.
3804 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3805 return SDValue(N, 0);
3808 // If the sign bit is known to be zero, switch this to a SRL.
3809 if (DAG.SignBitIsZero(N0))
3810 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3813 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3814 if (NewSRA.getNode())
3821 SDValue DAGCombiner::visitSRL(SDNode *N) {
3822 SDValue N0 = N->getOperand(0);
3823 SDValue N1 = N->getOperand(1);
3824 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3825 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3826 EVT VT = N0.getValueType();
3827 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3829 // fold (srl c1, c2) -> c1 >>u c2
3831 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3832 // fold (srl 0, x) -> 0
3833 if (N0C && N0C->isNullValue())
3835 // fold (srl x, c >= size(x)) -> undef
3836 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3837 return DAG.getUNDEF(VT);
3838 // fold (srl x, 0) -> x
3839 if (N1C && N1C->isNullValue())
3841 // if (srl x, c) is known to be zero, return 0
3842 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3843 APInt::getAllOnesValue(OpSizeInBits)))
3844 return DAG.getConstant(0, VT);
3846 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3847 if (N1C && N0.getOpcode() == ISD::SRL &&
3848 N0.getOperand(1).getOpcode() == ISD::Constant) {
3849 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3850 uint64_t c2 = N1C->getZExtValue();
3851 if (c1 + c2 >= OpSizeInBits)
3852 return DAG.getConstant(0, VT);
3853 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3854 DAG.getConstant(c1 + c2, N1.getValueType()));
3857 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3858 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3859 N0.getOperand(0).getOpcode() == ISD::SRL &&
3860 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3862 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3863 uint64_t c2 = N1C->getZExtValue();
3864 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3865 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3866 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3867 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3868 if (c1 + OpSizeInBits == InnerShiftSize) {
3869 if (c1 + c2 >= InnerShiftSize)
3870 return DAG.getConstant(0, VT);
3871 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3872 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3873 N0.getOperand(0)->getOperand(0),
3874 DAG.getConstant(c1 + c2, ShiftCountVT)));
3878 // fold (srl (shl x, c), c) -> (and x, cst2)
3879 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3880 N0.getValueSizeInBits() <= 64) {
3881 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3882 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3883 DAG.getConstant(~0ULL >> ShAmt, VT));
3887 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3888 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3889 // Shifting in all undef bits?
3890 EVT SmallVT = N0.getOperand(0).getValueType();
3891 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3892 return DAG.getUNDEF(VT);
3894 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3895 uint64_t ShiftAmt = N1C->getZExtValue();
3896 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3898 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3899 AddToWorkList(SmallShift.getNode());
3900 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3904 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3905 // bit, which is unmodified by sra.
3906 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3907 if (N0.getOpcode() == ISD::SRA)
3908 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3911 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3912 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3913 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3914 APInt KnownZero, KnownOne;
3915 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne);
3917 // If any of the input bits are KnownOne, then the input couldn't be all
3918 // zeros, thus the result of the srl will always be zero.
3919 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3921 // If all of the bits input the to ctlz node are known to be zero, then
3922 // the result of the ctlz is "32" and the result of the shift is one.
3923 APInt UnknownBits = ~KnownZero;
3924 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3926 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3927 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3928 // Okay, we know that only that the single bit specified by UnknownBits
3929 // could be set on input to the CTLZ node. If this bit is set, the SRL
3930 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3931 // to an SRL/XOR pair, which is likely to simplify more.
3932 unsigned ShAmt = UnknownBits.countTrailingZeros();
3933 SDValue Op = N0.getOperand(0);
3936 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3937 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3938 AddToWorkList(Op.getNode());
3941 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3942 Op, DAG.getConstant(1, VT));
3946 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3947 if (N1.getOpcode() == ISD::TRUNCATE &&
3948 N1.getOperand(0).getOpcode() == ISD::AND &&
3949 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3950 SDValue N101 = N1.getOperand(0).getOperand(1);
3951 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3952 EVT TruncVT = N1.getValueType();
3953 SDValue N100 = N1.getOperand(0).getOperand(0);
3954 APInt TruncC = N101C->getAPIntValue();
3955 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3956 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3957 DAG.getNode(ISD::AND, N->getDebugLoc(),
3959 DAG.getNode(ISD::TRUNCATE,
3962 DAG.getConstant(TruncC, TruncVT)));
3966 // fold operands of srl based on knowledge that the low bits are not
3968 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3969 return SDValue(N, 0);
3972 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3973 if (NewSRL.getNode())
3977 // Attempt to convert a srl of a load into a narrower zero-extending load.
3978 SDValue NarrowLoad = ReduceLoadWidth(N);
3979 if (NarrowLoad.getNode())
3982 // Here is a common situation. We want to optimize:
3985 // %b = and i32 %a, 2
3986 // %c = srl i32 %b, 1
3987 // brcond i32 %c ...
3993 // %c = setcc eq %b, 0
3996 // However when after the source operand of SRL is optimized into AND, the SRL
3997 // itself may not be optimized further. Look for it and add the BRCOND into
3999 if (N->hasOneUse()) {
4000 SDNode *Use = *N->use_begin();
4001 if (Use->getOpcode() == ISD::BRCOND)
4003 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
4004 // Also look pass the truncate.
4005 Use = *Use->use_begin();
4006 if (Use->getOpcode() == ISD::BRCOND)
4014 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
4015 SDValue N0 = N->getOperand(0);
4016 EVT VT = N->getValueType(0);
4018 // fold (ctlz c1) -> c2
4019 if (isa<ConstantSDNode>(N0))
4020 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
4024 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
4025 SDValue N0 = N->getOperand(0);
4026 EVT VT = N->getValueType(0);
4028 // fold (ctlz_zero_undef c1) -> c2
4029 if (isa<ConstantSDNode>(N0))
4030 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
4034 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
4035 SDValue N0 = N->getOperand(0);
4036 EVT VT = N->getValueType(0);
4038 // fold (cttz c1) -> c2
4039 if (isa<ConstantSDNode>(N0))
4040 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
4044 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
4045 SDValue N0 = N->getOperand(0);
4046 EVT VT = N->getValueType(0);
4048 // fold (cttz_zero_undef c1) -> c2
4049 if (isa<ConstantSDNode>(N0))
4050 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
4054 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4055 SDValue N0 = N->getOperand(0);
4056 EVT VT = N->getValueType(0);
4058 // fold (ctpop c1) -> c2
4059 if (isa<ConstantSDNode>(N0))
4060 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
4064 SDValue DAGCombiner::visitSELECT(SDNode *N) {
4065 SDValue N0 = N->getOperand(0);
4066 SDValue N1 = N->getOperand(1);
4067 SDValue N2 = N->getOperand(2);
4068 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4069 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4070 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
4071 EVT VT = N->getValueType(0);
4072 EVT VT0 = N0.getValueType();
4074 // fold (select C, X, X) -> X
4077 // fold (select true, X, Y) -> X
4078 if (N0C && !N0C->isNullValue())
4080 // fold (select false, X, Y) -> Y
4081 if (N0C && N0C->isNullValue())
4083 // fold (select C, 1, X) -> (or C, X)
4084 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
4085 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4086 // fold (select C, 0, 1) -> (xor C, 1)
4087 if (VT.isInteger() &&
4090 TLI.getBooleanContents(false) ==
4091 TargetLowering::ZeroOrOneBooleanContent)) &&
4092 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
4095 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
4096 N0, DAG.getConstant(1, VT0));
4097 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
4098 N0, DAG.getConstant(1, VT0));
4099 AddToWorkList(XORNode.getNode());
4101 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
4102 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
4104 // fold (select C, 0, X) -> (and (not C), X)
4105 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
4106 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
4107 AddToWorkList(NOTNode.getNode());
4108 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
4110 // fold (select C, X, 1) -> (or (not C), X)
4111 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
4112 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
4113 AddToWorkList(NOTNode.getNode());
4114 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
4116 // fold (select C, X, 0) -> (and C, X)
4117 if (VT == MVT::i1 && N2C && N2C->isNullValue())
4118 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4119 // fold (select X, X, Y) -> (or X, Y)
4120 // fold (select X, 1, Y) -> (or X, Y)
4121 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4122 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4123 // fold (select X, Y, X) -> (and X, Y)
4124 // fold (select X, Y, 0) -> (and X, Y)
4125 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4126 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4128 // If we can fold this based on the true/false value, do so.
4129 if (SimplifySelectOps(N, N1, N2))
4130 return SDValue(N, 0); // Don't revisit N.
4132 // fold selects based on a setcc into other things, such as min/max/abs
4133 if (N0.getOpcode() == ISD::SETCC) {
4135 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
4136 // having to say they don't support SELECT_CC on every type the DAG knows
4137 // about, since there is no way to mark an opcode illegal at all value types
4138 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
4139 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
4140 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
4141 N0.getOperand(0), N0.getOperand(1),
4142 N1, N2, N0.getOperand(2));
4143 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
4149 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
4150 SDValue N0 = N->getOperand(0);
4151 SDValue N1 = N->getOperand(1);
4152 SDValue N2 = N->getOperand(2);
4153 SDValue N3 = N->getOperand(3);
4154 SDValue N4 = N->getOperand(4);
4155 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
4157 // fold select_cc lhs, rhs, x, x, cc -> x
4161 // Determine if the condition we're dealing with is constant
4162 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
4163 N0, N1, CC, N->getDebugLoc(), false);
4164 if (SCC.getNode()) AddToWorkList(SCC.getNode());
4166 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
4167 if (!SCCC->isNullValue())
4168 return N2; // cond always true -> true val
4170 return N3; // cond always false -> false val
4173 // Fold to a simpler select_cc
4174 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
4175 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
4176 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
4179 // If we can fold this based on the true/false value, do so.
4180 if (SimplifySelectOps(N, N2, N3))
4181 return SDValue(N, 0); // Don't revisit N.
4183 // fold select_cc into other things, such as min/max/abs
4184 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
4187 SDValue DAGCombiner::visitSETCC(SDNode *N) {
4188 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
4189 cast<CondCodeSDNode>(N->getOperand(2))->get(),
4193 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
4194 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
4195 // transformation. Returns true if extension are possible and the above
4196 // mentioned transformation is profitable.
4197 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
4199 SmallVector<SDNode*, 4> &ExtendNodes,
4200 const TargetLowering &TLI) {
4201 bool HasCopyToRegUses = false;
4202 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
4203 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4204 UE = N0.getNode()->use_end();
4209 if (UI.getUse().getResNo() != N0.getResNo())
4211 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
4212 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4213 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
4214 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
4215 // Sign bits will be lost after a zext.
4218 for (unsigned i = 0; i != 2; ++i) {
4219 SDValue UseOp = User->getOperand(i);
4222 if (!isa<ConstantSDNode>(UseOp))
4227 ExtendNodes.push_back(User);
4230 // If truncates aren't free and there are users we can't
4231 // extend, it isn't worthwhile.
4234 // Remember if this value is live-out.
4235 if (User->getOpcode() == ISD::CopyToReg)
4236 HasCopyToRegUses = true;
4239 if (HasCopyToRegUses) {
4240 bool BothLiveOut = false;
4241 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4243 SDUse &Use = UI.getUse();
4244 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4250 // Both unextended and extended values are live out. There had better be
4251 // a good reason for the transformation.
4252 return ExtendNodes.size();
4257 void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
4258 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
4259 ISD::NodeType ExtType) {
4260 // Extend SetCC uses if necessary.
4261 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4262 SDNode *SetCC = SetCCs[i];
4263 SmallVector<SDValue, 4> Ops;
4265 for (unsigned j = 0; j != 2; ++j) {
4266 SDValue SOp = SetCC->getOperand(j);
4268 Ops.push_back(ExtLoad);
4270 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
4273 Ops.push_back(SetCC->getOperand(2));
4274 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
4275 &Ops[0], Ops.size()));
4279 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
4280 SDValue N0 = N->getOperand(0);
4281 EVT VT = N->getValueType(0);
4283 // fold (sext c1) -> c1
4284 if (isa<ConstantSDNode>(N0))
4285 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
4287 // fold (sext (sext x)) -> (sext x)
4288 // fold (sext (aext x)) -> (sext x)
4289 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4290 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
4293 if (N0.getOpcode() == ISD::TRUNCATE) {
4294 // fold (sext (truncate (load x))) -> (sext (smaller load x))
4295 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
4296 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4297 if (NarrowLoad.getNode()) {
4298 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4299 if (NarrowLoad.getNode() != N0.getNode()) {
4300 CombineTo(N0.getNode(), NarrowLoad);
4301 // CombineTo deleted the truncate, if needed, but not what's under it.
4304 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4307 // See if the value being truncated is already sign extended. If so, just
4308 // eliminate the trunc/sext pair.
4309 SDValue Op = N0.getOperand(0);
4310 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
4311 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
4312 unsigned DestBits = VT.getScalarType().getSizeInBits();
4313 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
4315 if (OpBits == DestBits) {
4316 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
4317 // bits, it is already ready.
4318 if (NumSignBits > DestBits-MidBits)
4320 } else if (OpBits < DestBits) {
4321 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
4322 // bits, just sext from i32.
4323 if (NumSignBits > OpBits-MidBits)
4324 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
4326 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
4327 // bits, just truncate to i32.
4328 if (NumSignBits > OpBits-MidBits)
4329 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4332 // fold (sext (truncate x)) -> (sextinreg x).
4333 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4334 N0.getValueType())) {
4335 if (OpBits < DestBits)
4336 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4337 else if (OpBits > DestBits)
4338 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4339 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
4340 DAG.getValueType(N0.getValueType()));
4344 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4345 // None of the supported targets knows how to perform load and sign extend
4346 // on vectors in one instruction. We only perform this transformation on
4348 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4349 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4350 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4351 bool DoXform = true;
4352 SmallVector<SDNode*, 4> SetCCs;
4353 if (!N0.hasOneUse())
4354 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4356 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4357 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4359 LN0->getBasePtr(), LN0->getPointerInfo(),
4361 LN0->isVolatile(), LN0->isNonTemporal(),
4362 LN0->getAlignment());
4363 CombineTo(N, ExtLoad);
4364 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4365 N0.getValueType(), ExtLoad);
4366 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4367 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4369 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4373 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4374 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4375 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4376 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4377 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4378 EVT MemVT = LN0->getMemoryVT();
4379 if ((!LegalOperations && !LN0->isVolatile()) ||
4380 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4381 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4383 LN0->getBasePtr(), LN0->getPointerInfo(),
4385 LN0->isVolatile(), LN0->isNonTemporal(),
4386 LN0->getAlignment());
4387 CombineTo(N, ExtLoad);
4388 CombineTo(N0.getNode(),
4389 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4390 N0.getValueType(), ExtLoad),
4391 ExtLoad.getValue(1));
4392 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4396 // fold (sext (and/or/xor (load x), cst)) ->
4397 // (and/or/xor (sextload x), (sext cst))
4398 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4399 N0.getOpcode() == ISD::XOR) &&
4400 isa<LoadSDNode>(N0.getOperand(0)) &&
4401 N0.getOperand(1).getOpcode() == ISD::Constant &&
4402 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4403 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4404 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4405 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4406 bool DoXform = true;
4407 SmallVector<SDNode*, 4> SetCCs;
4408 if (!N0.hasOneUse())
4409 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4412 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4413 LN0->getChain(), LN0->getBasePtr(),
4414 LN0->getPointerInfo(),
4417 LN0->isNonTemporal(),
4418 LN0->getAlignment());
4419 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4420 Mask = Mask.sext(VT.getSizeInBits());
4421 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4422 ExtLoad, DAG.getConstant(Mask, VT));
4423 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4424 N0.getOperand(0).getDebugLoc(),
4425 N0.getOperand(0).getValueType(), ExtLoad);
4427 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4428 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4430 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4435 if (N0.getOpcode() == ISD::SETCC) {
4436 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4437 // Only do this before legalize for now.
4438 if (VT.isVector() && !LegalOperations) {
4439 EVT N0VT = N0.getOperand(0).getValueType();
4440 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
4441 // of the same size as the compared operands. Only optimize sext(setcc())
4442 // if this is the case.
4443 EVT SVT = TLI.getSetCCResultType(N0VT);
4445 // We know that the # elements of the results is the same as the
4446 // # elements of the compare (and the # elements of the compare result
4447 // for that matter). Check to see that they are the same size. If so,
4448 // we know that the element size of the sext'd result matches the
4449 // element size of the compare operands.
4450 if (VT.getSizeInBits() == SVT.getSizeInBits())
4451 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4453 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4454 // If the desired elements are smaller or larger than the source
4455 // elements we can use a matching integer vector type and then
4456 // truncate/sign extend
4457 EVT MatchingElementType =
4458 EVT::getIntegerVT(*DAG.getContext(),
4459 N0VT.getScalarType().getSizeInBits());
4460 EVT MatchingVectorType =
4461 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4462 N0VT.getVectorNumElements());
4464 if (SVT == MatchingVectorType) {
4465 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType,
4466 N0.getOperand(0), N0.getOperand(1),
4467 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4468 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4472 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4473 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4475 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4477 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4478 NegOne, DAG.getConstant(0, VT),
4479 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4480 if (SCC.getNode()) return SCC;
4481 if (!LegalOperations ||
4482 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
4483 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4484 DAG.getSetCC(N->getDebugLoc(),
4485 TLI.getSetCCResultType(VT),
4486 N0.getOperand(0), N0.getOperand(1),
4487 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4488 NegOne, DAG.getConstant(0, VT));
4491 // fold (sext x) -> (zext x) if the sign bit is known zero.
4492 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4493 DAG.SignBitIsZero(N0))
4494 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4499 // isTruncateOf - If N is a truncate of some other value, return true, record
4500 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
4501 // This function computes KnownZero to avoid a duplicated call to
4502 // ComputeMaskedBits in the caller.
4503 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
4506 if (N->getOpcode() == ISD::TRUNCATE) {
4507 Op = N->getOperand(0);
4508 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4512 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
4513 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
4516 SDValue Op0 = N->getOperand(0);
4517 SDValue Op1 = N->getOperand(1);
4518 assert(Op0.getValueType() == Op1.getValueType());
4520 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0);
4521 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
4522 if (COp0 && COp0->isNullValue())
4524 else if (COp1 && COp1->isNullValue())
4529 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4531 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
4537 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4538 SDValue N0 = N->getOperand(0);
4539 EVT VT = N->getValueType(0);
4541 // fold (zext c1) -> c1
4542 if (isa<ConstantSDNode>(N0))
4543 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4544 // fold (zext (zext x)) -> (zext x)
4545 // fold (zext (aext x)) -> (zext x)
4546 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4547 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
4550 // fold (zext (truncate x)) -> (zext x) or
4551 // (zext (truncate x)) -> (truncate x)
4552 // This is valid when the truncated bits of x are already zero.
4553 // FIXME: We should extend this to work for vectors too.
4556 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
4557 APInt TruncatedBits =
4558 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
4559 APInt(Op.getValueSizeInBits(), 0) :
4560 APInt::getBitsSet(Op.getValueSizeInBits(),
4561 N0.getValueSizeInBits(),
4562 std::min(Op.getValueSizeInBits(),
4563 VT.getSizeInBits()));
4564 if (TruncatedBits == (KnownZero & TruncatedBits)) {
4565 if (VT.bitsGT(Op.getValueType()))
4566 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op);
4567 if (VT.bitsLT(Op.getValueType()))
4568 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4574 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4575 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4576 if (N0.getOpcode() == ISD::TRUNCATE) {
4577 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4578 if (NarrowLoad.getNode()) {
4579 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4580 if (NarrowLoad.getNode() != N0.getNode()) {
4581 CombineTo(N0.getNode(), NarrowLoad);
4582 // CombineTo deleted the truncate, if needed, but not what's under it.
4585 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4589 // fold (zext (truncate x)) -> (and x, mask)
4590 if (N0.getOpcode() == ISD::TRUNCATE &&
4591 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4593 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4594 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4595 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4596 if (NarrowLoad.getNode()) {
4597 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4598 if (NarrowLoad.getNode() != N0.getNode()) {
4599 CombineTo(N0.getNode(), NarrowLoad);
4600 // CombineTo deleted the truncate, if needed, but not what's under it.
4603 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4606 SDValue Op = N0.getOperand(0);
4607 if (Op.getValueType().bitsLT(VT)) {
4608 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
4609 AddToWorkList(Op.getNode());
4610 } else if (Op.getValueType().bitsGT(VT)) {
4611 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4612 AddToWorkList(Op.getNode());
4614 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
4615 N0.getValueType().getScalarType());
4618 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4619 // if either of the casts is not free.
4620 if (N0.getOpcode() == ISD::AND &&
4621 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4622 N0.getOperand(1).getOpcode() == ISD::Constant &&
4623 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4624 N0.getValueType()) ||
4625 !TLI.isZExtFree(N0.getValueType(), VT))) {
4626 SDValue X = N0.getOperand(0).getOperand(0);
4627 if (X.getValueType().bitsLT(VT)) {
4628 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
4629 } else if (X.getValueType().bitsGT(VT)) {
4630 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4632 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4633 Mask = Mask.zext(VT.getSizeInBits());
4634 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4635 X, DAG.getConstant(Mask, VT));
4638 // fold (zext (load x)) -> (zext (truncate (zextload x)))
4639 // None of the supported targets knows how to perform load and vector_zext
4640 // on vectors in one instruction. We only perform this transformation on
4642 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4643 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4644 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4645 bool DoXform = true;
4646 SmallVector<SDNode*, 4> SetCCs;
4647 if (!N0.hasOneUse())
4648 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4650 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4651 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4653 LN0->getBasePtr(), LN0->getPointerInfo(),
4655 LN0->isVolatile(), LN0->isNonTemporal(),
4656 LN0->getAlignment());
4657 CombineTo(N, ExtLoad);
4658 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4659 N0.getValueType(), ExtLoad);
4660 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4662 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4664 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4668 // fold (zext (and/or/xor (load x), cst)) ->
4669 // (and/or/xor (zextload x), (zext cst))
4670 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4671 N0.getOpcode() == ISD::XOR) &&
4672 isa<LoadSDNode>(N0.getOperand(0)) &&
4673 N0.getOperand(1).getOpcode() == ISD::Constant &&
4674 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4675 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4676 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4677 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4678 bool DoXform = true;
4679 SmallVector<SDNode*, 4> SetCCs;
4680 if (!N0.hasOneUse())
4681 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4684 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
4685 LN0->getChain(), LN0->getBasePtr(),
4686 LN0->getPointerInfo(),
4689 LN0->isNonTemporal(),
4690 LN0->getAlignment());
4691 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4692 Mask = Mask.zext(VT.getSizeInBits());
4693 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4694 ExtLoad, DAG.getConstant(Mask, VT));
4695 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4696 N0.getOperand(0).getDebugLoc(),
4697 N0.getOperand(0).getValueType(), ExtLoad);
4699 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4700 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4702 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4707 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4708 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4709 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4710 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4711 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4712 EVT MemVT = LN0->getMemoryVT();
4713 if ((!LegalOperations && !LN0->isVolatile()) ||
4714 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4715 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4717 LN0->getBasePtr(), LN0->getPointerInfo(),
4719 LN0->isVolatile(), LN0->isNonTemporal(),
4720 LN0->getAlignment());
4721 CombineTo(N, ExtLoad);
4722 CombineTo(N0.getNode(),
4723 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4725 ExtLoad.getValue(1));
4726 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4730 if (N0.getOpcode() == ISD::SETCC) {
4731 if (!LegalOperations && VT.isVector()) {
4732 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4733 // Only do this before legalize for now.
4734 EVT N0VT = N0.getOperand(0).getValueType();
4735 EVT EltVT = VT.getVectorElementType();
4736 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4737 DAG.getConstant(1, EltVT));
4738 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4739 // We know that the # elements of the results is the same as the
4740 // # elements of the compare (and the # elements of the compare result
4741 // for that matter). Check to see that they are the same size. If so,
4742 // we know that the element size of the sext'd result matches the
4743 // element size of the compare operands.
4744 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4745 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4747 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4748 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4749 &OneOps[0], OneOps.size()));
4751 // If the desired elements are smaller or larger than the source
4752 // elements we can use a matching integer vector type and then
4753 // truncate/sign extend
4754 EVT MatchingElementType =
4755 EVT::getIntegerVT(*DAG.getContext(),
4756 N0VT.getScalarType().getSizeInBits());
4757 EVT MatchingVectorType =
4758 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4759 N0VT.getVectorNumElements());
4761 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4763 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4764 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4765 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4766 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4767 &OneOps[0], OneOps.size()));
4770 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4772 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4773 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4774 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4775 if (SCC.getNode()) return SCC;
4778 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4779 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4780 isa<ConstantSDNode>(N0.getOperand(1)) &&
4781 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4783 SDValue ShAmt = N0.getOperand(1);
4784 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4785 if (N0.getOpcode() == ISD::SHL) {
4786 SDValue InnerZExt = N0.getOperand(0);
4787 // If the original shl may be shifting out bits, do not perform this
4789 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4790 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4791 if (ShAmtVal > KnownZeroBits)
4795 DebugLoc DL = N->getDebugLoc();
4797 // Ensure that the shift amount is wide enough for the shifted value.
4798 if (VT.getSizeInBits() >= 256)
4799 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4801 return DAG.getNode(N0.getOpcode(), DL, VT,
4802 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4809 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4810 SDValue N0 = N->getOperand(0);
4811 EVT VT = N->getValueType(0);
4813 // fold (aext c1) -> c1
4814 if (isa<ConstantSDNode>(N0))
4815 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4816 // fold (aext (aext x)) -> (aext x)
4817 // fold (aext (zext x)) -> (zext x)
4818 // fold (aext (sext x)) -> (sext x)
4819 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4820 N0.getOpcode() == ISD::ZERO_EXTEND ||
4821 N0.getOpcode() == ISD::SIGN_EXTEND)
4822 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4824 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4825 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4826 if (N0.getOpcode() == ISD::TRUNCATE) {
4827 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4828 if (NarrowLoad.getNode()) {
4829 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4830 if (NarrowLoad.getNode() != N0.getNode()) {
4831 CombineTo(N0.getNode(), NarrowLoad);
4832 // CombineTo deleted the truncate, if needed, but not what's under it.
4835 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4839 // fold (aext (truncate x))
4840 if (N0.getOpcode() == ISD::TRUNCATE) {
4841 SDValue TruncOp = N0.getOperand(0);
4842 if (TruncOp.getValueType() == VT)
4843 return TruncOp; // x iff x size == zext size.
4844 if (TruncOp.getValueType().bitsGT(VT))
4845 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4846 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4849 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4850 // if the trunc is not free.
4851 if (N0.getOpcode() == ISD::AND &&
4852 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4853 N0.getOperand(1).getOpcode() == ISD::Constant &&
4854 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4855 N0.getValueType())) {
4856 SDValue X = N0.getOperand(0).getOperand(0);
4857 if (X.getValueType().bitsLT(VT)) {
4858 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4859 } else if (X.getValueType().bitsGT(VT)) {
4860 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4862 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4863 Mask = Mask.zext(VT.getSizeInBits());
4864 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4865 X, DAG.getConstant(Mask, VT));
4868 // fold (aext (load x)) -> (aext (truncate (extload x)))
4869 // None of the supported targets knows how to perform load and any_ext
4870 // on vectors in one instruction. We only perform this transformation on
4872 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4873 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4874 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4875 bool DoXform = true;
4876 SmallVector<SDNode*, 4> SetCCs;
4877 if (!N0.hasOneUse())
4878 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4880 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4881 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4883 LN0->getBasePtr(), LN0->getPointerInfo(),
4885 LN0->isVolatile(), LN0->isNonTemporal(),
4886 LN0->getAlignment());
4887 CombineTo(N, ExtLoad);
4888 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4889 N0.getValueType(), ExtLoad);
4890 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4891 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4893 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4897 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4898 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4899 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4900 if (N0.getOpcode() == ISD::LOAD &&
4901 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4903 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4904 EVT MemVT = LN0->getMemoryVT();
4905 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4906 VT, LN0->getChain(), LN0->getBasePtr(),
4907 LN0->getPointerInfo(), MemVT,
4908 LN0->isVolatile(), LN0->isNonTemporal(),
4909 LN0->getAlignment());
4910 CombineTo(N, ExtLoad);
4911 CombineTo(N0.getNode(),
4912 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4913 N0.getValueType(), ExtLoad),
4914 ExtLoad.getValue(1));
4915 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4918 if (N0.getOpcode() == ISD::SETCC) {
4919 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4920 // Only do this before legalize for now.
4921 if (VT.isVector() && !LegalOperations) {
4922 EVT N0VT = N0.getOperand(0).getValueType();
4923 // We know that the # elements of the results is the same as the
4924 // # elements of the compare (and the # elements of the compare result
4925 // for that matter). Check to see that they are the same size. If so,
4926 // we know that the element size of the sext'd result matches the
4927 // element size of the compare operands.
4928 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4929 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4931 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4932 // If the desired elements are smaller or larger than the source
4933 // elements we can use a matching integer vector type and then
4934 // truncate/sign extend
4936 EVT MatchingElementType =
4937 EVT::getIntegerVT(*DAG.getContext(),
4938 N0VT.getScalarType().getSizeInBits());
4939 EVT MatchingVectorType =
4940 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4941 N0VT.getVectorNumElements());
4943 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4945 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4946 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4950 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4952 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4953 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4954 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4962 /// GetDemandedBits - See if the specified operand can be simplified with the
4963 /// knowledge that only the bits specified by Mask are used. If so, return the
4964 /// simpler operand, otherwise return a null SDValue.
4965 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4966 switch (V.getOpcode()) {
4968 case ISD::Constant: {
4969 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
4970 assert(CV != 0 && "Const value should be ConstSDNode.");
4971 const APInt &CVal = CV->getAPIntValue();
4972 APInt NewVal = CVal & Mask;
4973 if (NewVal != CVal) {
4974 return DAG.getConstant(NewVal, V.getValueType());
4980 // If the LHS or RHS don't contribute bits to the or, drop them.
4981 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4982 return V.getOperand(1);
4983 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4984 return V.getOperand(0);
4987 // Only look at single-use SRLs.
4988 if (!V.getNode()->hasOneUse())
4990 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4991 // See if we can recursively simplify the LHS.
4992 unsigned Amt = RHSC->getZExtValue();
4994 // Watch out for shift count overflow though.
4995 if (Amt >= Mask.getBitWidth()) break;
4996 APInt NewMask = Mask << Amt;
4997 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4998 if (SimplifyLHS.getNode())
4999 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
5000 SimplifyLHS, V.getOperand(1));
5006 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
5007 /// bits and then truncated to a narrower type and where N is a multiple
5008 /// of number of bits of the narrower type, transform it to a narrower load
5009 /// from address + N / num of bits of new type. If the result is to be
5010 /// extended, also fold the extension to form a extending load.
5011 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
5012 unsigned Opc = N->getOpcode();
5014 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
5015 SDValue N0 = N->getOperand(0);
5016 EVT VT = N->getValueType(0);
5019 // This transformation isn't valid for vector loads.
5023 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
5025 if (Opc == ISD::SIGN_EXTEND_INREG) {
5026 ExtType = ISD::SEXTLOAD;
5027 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5028 } else if (Opc == ISD::SRL) {
5029 // Another special-case: SRL is basically zero-extending a narrower value.
5030 ExtType = ISD::ZEXTLOAD;
5032 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5033 if (!N01) return SDValue();
5034 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
5035 VT.getSizeInBits() - N01->getZExtValue());
5037 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
5040 unsigned EVTBits = ExtVT.getSizeInBits();
5042 // Do not generate loads of non-round integer types since these can
5043 // be expensive (and would be wrong if the type is not byte sized).
5044 if (!ExtVT.isRound())
5048 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5049 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5050 ShAmt = N01->getZExtValue();
5051 // Is the shift amount a multiple of size of VT?
5052 if ((ShAmt & (EVTBits-1)) == 0) {
5053 N0 = N0.getOperand(0);
5054 // Is the load width a multiple of size of VT?
5055 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
5059 // At this point, we must have a load or else we can't do the transform.
5060 if (!isa<LoadSDNode>(N0)) return SDValue();
5062 // If the shift amount is larger than the input type then we're not
5063 // accessing any of the loaded bytes. If the load was a zextload/extload
5064 // then the result of the shift+trunc is zero/undef (handled elsewhere).
5065 // If the load was a sextload then the result is a splat of the sign bit
5066 // of the extended byte. This is not worth optimizing for.
5067 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
5072 // If the load is shifted left (and the result isn't shifted back right),
5073 // we can fold the truncate through the shift.
5074 unsigned ShLeftAmt = 0;
5075 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
5076 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
5077 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5078 ShLeftAmt = N01->getZExtValue();
5079 N0 = N0.getOperand(0);
5083 // If we haven't found a load, we can't narrow it. Don't transform one with
5084 // multiple uses, this would require adding a new load.
5085 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
5086 // Don't change the width of a volatile load.
5087 cast<LoadSDNode>(N0)->isVolatile())
5090 // Verify that we are actually reducing a load width here.
5091 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
5094 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5095 EVT PtrType = N0.getOperand(1).getValueType();
5097 if (PtrType == MVT::Untyped || PtrType.isExtended())
5098 // It's not possible to generate a constant of extended or untyped type.
5101 // For big endian targets, we need to adjust the offset to the pointer to
5102 // load the correct bytes.
5103 if (TLI.isBigEndian()) {
5104 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
5105 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
5106 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
5109 uint64_t PtrOff = ShAmt / 8;
5110 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
5111 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
5112 PtrType, LN0->getBasePtr(),
5113 DAG.getConstant(PtrOff, PtrType));
5114 AddToWorkList(NewPtr.getNode());
5117 if (ExtType == ISD::NON_EXTLOAD)
5118 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
5119 LN0->getPointerInfo().getWithOffset(PtrOff),
5120 LN0->isVolatile(), LN0->isNonTemporal(),
5121 LN0->isInvariant(), NewAlign);
5123 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
5124 LN0->getPointerInfo().getWithOffset(PtrOff),
5125 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
5128 // Replace the old load's chain with the new load's chain.
5129 WorkListRemover DeadNodes(*this);
5130 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
5132 // Shift the result left, if we've swallowed a left shift.
5133 SDValue Result = Load;
5134 if (ShLeftAmt != 0) {
5135 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
5136 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
5138 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
5139 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
5142 // Return the new loaded value.
5146 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
5147 SDValue N0 = N->getOperand(0);
5148 SDValue N1 = N->getOperand(1);
5149 EVT VT = N->getValueType(0);
5150 EVT EVT = cast<VTSDNode>(N1)->getVT();
5151 unsigned VTBits = VT.getScalarType().getSizeInBits();
5152 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
5154 // fold (sext_in_reg c1) -> c1
5155 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
5156 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
5158 // If the input is already sign extended, just drop the extension.
5159 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
5162 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
5163 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5164 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
5165 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5166 N0.getOperand(0), N1);
5169 // fold (sext_in_reg (sext x)) -> (sext x)
5170 // fold (sext_in_reg (aext x)) -> (sext x)
5171 // if x is small enough.
5172 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
5173 SDValue N00 = N0.getOperand(0);
5174 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
5175 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
5176 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
5179 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
5180 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
5181 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
5183 // fold operands of sext_in_reg based on knowledge that the top bits are not
5185 if (SimplifyDemandedBits(SDValue(N, 0)))
5186 return SDValue(N, 0);
5188 // fold (sext_in_reg (load x)) -> (smaller sextload x)
5189 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
5190 SDValue NarrowLoad = ReduceLoadWidth(N);
5191 if (NarrowLoad.getNode())
5194 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
5195 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
5196 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
5197 if (N0.getOpcode() == ISD::SRL) {
5198 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
5199 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
5200 // We can turn this into an SRA iff the input to the SRL is already sign
5202 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
5203 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
5204 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
5205 N0.getOperand(0), N0.getOperand(1));
5209 // fold (sext_inreg (extload x)) -> (sextload x)
5210 if (ISD::isEXTLoad(N0.getNode()) &&
5211 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5212 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5213 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5214 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5215 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5216 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5218 LN0->getBasePtr(), LN0->getPointerInfo(),
5220 LN0->isVolatile(), LN0->isNonTemporal(),
5221 LN0->getAlignment());
5222 CombineTo(N, ExtLoad);
5223 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5224 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5226 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
5227 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5229 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5230 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5231 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5232 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5233 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5235 LN0->getBasePtr(), LN0->getPointerInfo(),
5237 LN0->isVolatile(), LN0->isNonTemporal(),
5238 LN0->getAlignment());
5239 CombineTo(N, ExtLoad);
5240 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5241 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5244 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
5245 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5246 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5247 N0.getOperand(1), false);
5248 if (BSwap.getNode() != 0)
5249 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5256 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
5257 SDValue N0 = N->getOperand(0);
5258 EVT VT = N->getValueType(0);
5259 bool isLE = TLI.isLittleEndian();
5262 if (N0.getValueType() == N->getValueType(0))
5264 // fold (truncate c1) -> c1
5265 if (isa<ConstantSDNode>(N0))
5266 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
5267 // fold (truncate (truncate x)) -> (truncate x)
5268 if (N0.getOpcode() == ISD::TRUNCATE)
5269 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5270 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
5271 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
5272 N0.getOpcode() == ISD::SIGN_EXTEND ||
5273 N0.getOpcode() == ISD::ANY_EXTEND) {
5274 if (N0.getOperand(0).getValueType().bitsLT(VT))
5275 // if the source is smaller than the dest, we still need an extend
5276 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
5278 if (N0.getOperand(0).getValueType().bitsGT(VT))
5279 // if the source is larger than the dest, than we just need the truncate
5280 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5281 // if the source and dest are the same type, we can drop both the extend
5282 // and the truncate.
5283 return N0.getOperand(0);
5286 // Fold extract-and-trunc into a narrow extract. For example:
5287 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
5288 // i32 y = TRUNCATE(i64 x)
5290 // v16i8 b = BITCAST (v2i64 val)
5291 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
5293 // Note: We only run this optimization after type legalization (which often
5294 // creates this pattern) and before operation legalization after which
5295 // we need to be more careful about the vector instructions that we generate.
5296 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5297 LegalTypes && !LegalOperations && N0->hasOneUse()) {
5299 EVT VecTy = N0.getOperand(0).getValueType();
5300 EVT ExTy = N0.getValueType();
5301 EVT TrTy = N->getValueType(0);
5303 unsigned NumElem = VecTy.getVectorNumElements();
5304 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
5306 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
5307 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
5309 SDValue EltNo = N0->getOperand(1);
5310 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
5311 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5312 EVT IndexTy = N0->getOperand(1).getValueType();
5313 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
5315 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5316 NVT, N0.getOperand(0));
5318 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
5319 N->getDebugLoc(), TrTy, V,
5320 DAG.getConstant(Index, IndexTy));
5324 // See if we can simplify the input to this truncate through knowledge that
5325 // only the low bits are being used.
5326 // For example "trunc (or (shl x, 8), y)" // -> trunc y
5327 // Currently we only perform this optimization on scalars because vectors
5328 // may have different active low bits.
5329 if (!VT.isVector()) {
5331 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
5332 VT.getSizeInBits()));
5333 if (Shorter.getNode())
5334 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
5336 // fold (truncate (load x)) -> (smaller load x)
5337 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
5338 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
5339 SDValue Reduced = ReduceLoadWidth(N);
5340 if (Reduced.getNode())
5343 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)),
5344 // where ... are all 'undef'.
5345 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
5346 SmallVector<EVT, 8> VTs;
5349 unsigned NumDefs = 0;
5351 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
5352 SDValue X = N0.getOperand(i);
5353 if (X.getOpcode() != ISD::UNDEF) {
5358 // Stop if more than one members are non-undef.
5361 VTs.push_back(EVT::getVectorVT(*DAG.getContext(),
5362 VT.getVectorElementType(),
5363 X.getValueType().getVectorNumElements()));
5367 return DAG.getUNDEF(VT);
5370 assert(V.getNode() && "The single defined operand is empty!");
5371 SmallVector<SDValue, 8> Opnds;
5372 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
5374 Opnds.push_back(DAG.getUNDEF(VTs[i]));
5377 SDValue NV = DAG.getNode(ISD::TRUNCATE, V.getDebugLoc(), VTs[i], V);
5378 AddToWorkList(NV.getNode());
5379 Opnds.push_back(NV);
5381 return DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
5382 &Opnds[0], Opnds.size());
5386 // Simplify the operands using demanded-bits information.
5387 if (!VT.isVector() &&
5388 SimplifyDemandedBits(SDValue(N, 0)))
5389 return SDValue(N, 0);
5394 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
5395 SDValue Elt = N->getOperand(i);
5396 if (Elt.getOpcode() != ISD::MERGE_VALUES)
5397 return Elt.getNode();
5398 return Elt.getOperand(Elt.getResNo()).getNode();
5401 /// CombineConsecutiveLoads - build_pair (load, load) -> load
5402 /// if load locations are consecutive.
5403 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
5404 assert(N->getOpcode() == ISD::BUILD_PAIR);
5406 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
5407 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
5408 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
5409 LD1->getPointerInfo().getAddrSpace() !=
5410 LD2->getPointerInfo().getAddrSpace())
5412 EVT LD1VT = LD1->getValueType(0);
5414 if (ISD::isNON_EXTLoad(LD2) &&
5416 // If both are volatile this would reduce the number of volatile loads.
5417 // If one is volatile it might be ok, but play conservative and bail out.
5418 !LD1->isVolatile() &&
5419 !LD2->isVolatile() &&
5420 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
5421 unsigned Align = LD1->getAlignment();
5422 unsigned NewAlign = TLI.getDataLayout()->
5423 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5425 if (NewAlign <= Align &&
5426 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
5427 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
5428 LD1->getBasePtr(), LD1->getPointerInfo(),
5429 false, false, false, Align);
5435 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
5436 SDValue N0 = N->getOperand(0);
5437 EVT VT = N->getValueType(0);
5439 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
5440 // Only do this before legalize, since afterward the target may be depending
5441 // on the bitconvert.
5442 // First check to see if this is all constant.
5444 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
5446 bool isSimple = true;
5447 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
5448 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
5449 N0.getOperand(i).getOpcode() != ISD::Constant &&
5450 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
5455 EVT DestEltVT = N->getValueType(0).getVectorElementType();
5456 assert(!DestEltVT.isVector() &&
5457 "Element type of vector ValueType must not be vector!");
5459 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
5462 // If the input is a constant, let getNode fold it.
5463 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
5464 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
5465 if (Res.getNode() != N) {
5466 if (!LegalOperations ||
5467 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
5470 // Folding it resulted in an illegal node, and it's too late to
5471 // do that. Clean up the old node and forego the transformation.
5472 // Ideally this won't happen very often, because instcombine
5473 // and the earlier dagcombine runs (where illegal nodes are
5474 // permitted) should have folded most of them already.
5475 DAG.DeleteNode(Res.getNode());
5479 // (conv (conv x, t1), t2) -> (conv x, t2)
5480 if (N0.getOpcode() == ISD::BITCAST)
5481 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
5484 // fold (conv (load x)) -> (load (conv*)x)
5485 // If the resultant load doesn't need a higher alignment than the original!
5486 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5487 // Do not change the width of a volatile load.
5488 !cast<LoadSDNode>(N0)->isVolatile() &&
5489 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
5490 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5491 unsigned Align = TLI.getDataLayout()->
5492 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5493 unsigned OrigAlign = LN0->getAlignment();
5495 if (Align <= OrigAlign) {
5496 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
5497 LN0->getBasePtr(), LN0->getPointerInfo(),
5498 LN0->isVolatile(), LN0->isNonTemporal(),
5499 LN0->isInvariant(), OrigAlign);
5501 CombineTo(N0.getNode(),
5502 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5503 N0.getValueType(), Load),
5509 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5510 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5511 // This often reduces constant pool loads.
5512 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) ||
5513 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) &&
5514 N0.getNode()->hasOneUse() && VT.isInteger() &&
5515 !VT.isVector() && !N0.getValueType().isVector()) {
5516 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5518 AddToWorkList(NewConv.getNode());
5520 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5521 if (N0.getOpcode() == ISD::FNEG)
5522 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
5523 NewConv, DAG.getConstant(SignBit, VT));
5524 assert(N0.getOpcode() == ISD::FABS);
5525 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
5526 NewConv, DAG.getConstant(~SignBit, VT));
5529 // fold (bitconvert (fcopysign cst, x)) ->
5530 // (or (and (bitconvert x), sign), (and cst, (not sign)))
5531 // Note that we don't handle (copysign x, cst) because this can always be
5532 // folded to an fneg or fabs.
5533 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5534 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5535 VT.isInteger() && !VT.isVector()) {
5536 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5537 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5538 if (isTypeLegal(IntXVT)) {
5539 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5540 IntXVT, N0.getOperand(1));
5541 AddToWorkList(X.getNode());
5543 // If X has a different width than the result/lhs, sext it or truncate it.
5544 unsigned VTWidth = VT.getSizeInBits();
5545 if (OrigXWidth < VTWidth) {
5546 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
5547 AddToWorkList(X.getNode());
5548 } else if (OrigXWidth > VTWidth) {
5549 // To get the sign bit in the right place, we have to shift it right
5550 // before truncating.
5551 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5552 X.getValueType(), X,
5553 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5554 AddToWorkList(X.getNode());
5555 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
5556 AddToWorkList(X.getNode());
5559 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5560 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
5561 X, DAG.getConstant(SignBit, VT));
5562 AddToWorkList(X.getNode());
5564 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5565 VT, N0.getOperand(0));
5566 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
5567 Cst, DAG.getConstant(~SignBit, VT));
5568 AddToWorkList(Cst.getNode());
5570 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
5574 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5575 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5576 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5577 if (CombineLD.getNode())
5584 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5585 EVT VT = N->getValueType(0);
5586 return CombineConsecutiveLoads(N, VT);
5589 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5590 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
5591 /// destination element value type.
5592 SDValue DAGCombiner::
5593 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5594 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5596 // If this is already the right type, we're done.
5597 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5599 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5600 unsigned DstBitSize = DstEltVT.getSizeInBits();
5602 // If this is a conversion of N elements of one type to N elements of another
5603 // type, convert each element. This handles FP<->INT cases.
5604 if (SrcBitSize == DstBitSize) {
5605 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5606 BV->getValueType(0).getVectorNumElements());
5608 // Due to the FP element handling below calling this routine recursively,
5609 // we can end up with a scalar-to-vector node here.
5610 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5611 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5612 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5613 DstEltVT, BV->getOperand(0)));
5615 SmallVector<SDValue, 8> Ops;
5616 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5617 SDValue Op = BV->getOperand(i);
5618 // If the vector element type is not legal, the BUILD_VECTOR operands
5619 // are promoted and implicitly truncated. Make that explicit here.
5620 if (Op.getValueType() != SrcEltVT)
5621 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
5622 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5624 AddToWorkList(Ops.back().getNode());
5626 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5627 &Ops[0], Ops.size());
5630 // Otherwise, we're growing or shrinking the elements. To avoid having to
5631 // handle annoying details of growing/shrinking FP values, we convert them to
5633 if (SrcEltVT.isFloatingPoint()) {
5634 // Convert the input float vector to a int vector where the elements are the
5636 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5637 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5638 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5642 // Now we know the input is an integer vector. If the output is a FP type,
5643 // convert to integer first, then to FP of the right size.
5644 if (DstEltVT.isFloatingPoint()) {
5645 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5646 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5647 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5649 // Next, convert to FP elements of the same size.
5650 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5653 // Okay, we know the src/dst types are both integers of differing types.
5654 // Handling growing first.
5655 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5656 if (SrcBitSize < DstBitSize) {
5657 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5659 SmallVector<SDValue, 8> Ops;
5660 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5661 i += NumInputsPerOutput) {
5662 bool isLE = TLI.isLittleEndian();
5663 APInt NewBits = APInt(DstBitSize, 0);
5664 bool EltIsUndef = true;
5665 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5666 // Shift the previously computed bits over.
5667 NewBits <<= SrcBitSize;
5668 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
5669 if (Op.getOpcode() == ISD::UNDEF) continue;
5672 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
5673 zextOrTrunc(SrcBitSize).zext(DstBitSize);
5677 Ops.push_back(DAG.getUNDEF(DstEltVT));
5679 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
5682 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
5683 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5684 &Ops[0], Ops.size());
5687 // Finally, this must be the case where we are shrinking elements: each input
5688 // turns into multiple outputs.
5689 bool isS2V = ISD::isScalarToVector(BV);
5690 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
5691 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5692 NumOutputsPerInput*BV->getNumOperands());
5693 SmallVector<SDValue, 8> Ops;
5695 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5696 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5697 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
5698 Ops.push_back(DAG.getUNDEF(DstEltVT));
5702 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
5703 getAPIntValue().zextOrTrunc(SrcBitSize);
5705 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
5706 APInt ThisVal = OpVal.trunc(DstBitSize);
5707 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
5708 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
5709 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
5710 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5712 OpVal = OpVal.lshr(DstBitSize);
5715 // For big endian targets, swap the order of the pieces of each element.
5716 if (TLI.isBigEndian())
5717 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
5720 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5721 &Ops[0], Ops.size());
5724 SDValue DAGCombiner::visitFADD(SDNode *N) {
5725 SDValue N0 = N->getOperand(0);
5726 SDValue N1 = N->getOperand(1);
5727 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5728 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5729 EVT VT = N->getValueType(0);
5732 if (VT.isVector()) {
5733 SDValue FoldedVOp = SimplifyVBinOp(N);
5734 if (FoldedVOp.getNode()) return FoldedVOp;
5737 // fold (fadd c1, c2) -> c1 + c2
5739 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5740 // canonicalize constant to RHS
5741 if (N0CFP && !N1CFP)
5742 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5743 // fold (fadd A, 0) -> A
5744 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5745 N1CFP->getValueAPF().isZero())
5747 // fold (fadd A, (fneg B)) -> (fsub A, B)
5748 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5749 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5750 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5751 GetNegatedExpression(N1, DAG, LegalOperations));
5752 // fold (fadd (fneg A), B) -> (fsub B, A)
5753 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5754 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5755 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
5756 GetNegatedExpression(N0, DAG, LegalOperations));
5758 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5759 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5760 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
5761 isa<ConstantFPSDNode>(N0.getOperand(1)))
5762 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5763 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5764 N0.getOperand(1), N1));
5766 // If allow, fold (fadd (fneg x), x) -> 0.0
5767 if (DAG.getTarget().Options.UnsafeFPMath &&
5768 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) {
5769 return DAG.getConstantFP(0.0, VT);
5772 // If allow, fold (fadd x, (fneg x)) -> 0.0
5773 if (DAG.getTarget().Options.UnsafeFPMath &&
5774 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) {
5775 return DAG.getConstantFP(0.0, VT);
5778 // In unsafe math mode, we can fold chains of FADD's of the same value
5779 // into multiplications. This transform is not safe in general because
5780 // we are reducing the number of rounding steps.
5781 if (DAG.getTarget().Options.UnsafeFPMath &&
5782 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) &&
5784 if (N0.getOpcode() == ISD::FMUL) {
5785 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
5786 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
5788 // (fadd (fmul c, x), x) -> (fmul c+1, x)
5789 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) {
5790 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5792 DAG.getConstantFP(1.0, VT));
5793 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5797 // (fadd (fmul x, c), x) -> (fmul c+1, x)
5798 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
5799 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5801 DAG.getConstantFP(1.0, VT));
5802 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5806 // (fadd (fadd x, x), x) -> (fmul 3.0, x)
5807 if (!CFP00 && !CFP01 && N0.getOperand(0) == N0.getOperand(1) &&
5808 N0.getOperand(0) == N1) {
5809 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5810 N1, DAG.getConstantFP(3.0, VT));
5813 // (fadd (fmul c, x), (fadd x, x)) -> (fmul c+2, x)
5814 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD &&
5815 N1.getOperand(0) == N1.getOperand(1) &&
5816 N0.getOperand(1) == N1.getOperand(0)) {
5817 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5819 DAG.getConstantFP(2.0, VT));
5820 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5821 N0.getOperand(1), NewCFP);
5824 // (fadd (fmul x, c), (fadd x, x)) -> (fmul c+2, x)
5825 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
5826 N1.getOperand(0) == N1.getOperand(1) &&
5827 N0.getOperand(0) == N1.getOperand(0)) {
5828 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5830 DAG.getConstantFP(2.0, VT));
5831 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5832 N0.getOperand(0), NewCFP);
5836 if (N1.getOpcode() == ISD::FMUL) {
5837 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
5838 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1));
5840 // (fadd x, (fmul c, x)) -> (fmul c+1, x)
5841 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) {
5842 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5844 DAG.getConstantFP(1.0, VT));
5845 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5849 // (fadd x, (fmul x, c)) -> (fmul c+1, x)
5850 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
5851 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5853 DAG.getConstantFP(1.0, VT));
5854 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5858 // (fadd x, (fadd x, x)) -> (fmul 3.0, x)
5859 if (!CFP10 && !CFP11 && N1.getOperand(0) == N1.getOperand(1) &&
5860 N1.getOperand(0) == N0) {
5861 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5862 N0, DAG.getConstantFP(3.0, VT));
5865 // (fadd (fadd x, x), (fmul c, x)) -> (fmul c+2, x)
5866 if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD &&
5867 N1.getOperand(0) == N1.getOperand(1) &&
5868 N0.getOperand(1) == N1.getOperand(0)) {
5869 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5871 DAG.getConstantFP(2.0, VT));
5872 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5873 N0.getOperand(1), NewCFP);
5876 // (fadd (fadd x, x), (fmul x, c)) -> (fmul c+2, x)
5877 if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD &&
5878 N1.getOperand(0) == N1.getOperand(1) &&
5879 N0.getOperand(0) == N1.getOperand(0)) {
5880 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5882 DAG.getConstantFP(2.0, VT));
5883 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5884 N0.getOperand(0), NewCFP);
5888 // (fadd (fadd x, x), (fadd x, x)) -> (fmul 4.0, x)
5889 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
5890 N0.getOperand(0) == N0.getOperand(1) &&
5891 N1.getOperand(0) == N1.getOperand(1) &&
5892 N0.getOperand(0) == N1.getOperand(0)) {
5893 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5895 DAG.getConstantFP(4.0, VT));
5899 // FADD -> FMA combines:
5900 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
5901 DAG.getTarget().Options.UnsafeFPMath) &&
5902 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) &&
5903 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) {
5905 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
5906 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) {
5907 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT,
5908 N0.getOperand(0), N0.getOperand(1), N1);
5911 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
5912 // Note: Commutes FADD operands.
5913 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) {
5914 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT,
5915 N1.getOperand(0), N1.getOperand(1), N0);
5922 SDValue DAGCombiner::visitFSUB(SDNode *N) {
5923 SDValue N0 = N->getOperand(0);
5924 SDValue N1 = N->getOperand(1);
5925 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5926 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5927 EVT VT = N->getValueType(0);
5928 DebugLoc dl = N->getDebugLoc();
5931 if (VT.isVector()) {
5932 SDValue FoldedVOp = SimplifyVBinOp(N);
5933 if (FoldedVOp.getNode()) return FoldedVOp;
5936 // fold (fsub c1, c2) -> c1-c2
5938 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5939 // fold (fsub A, 0) -> A
5940 if (DAG.getTarget().Options.UnsafeFPMath &&
5941 N1CFP && N1CFP->getValueAPF().isZero())
5943 // fold (fsub 0, B) -> -B
5944 if (DAG.getTarget().Options.UnsafeFPMath &&
5945 N0CFP && N0CFP->getValueAPF().isZero()) {
5946 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
5947 return GetNegatedExpression(N1, DAG, LegalOperations);
5948 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5949 return DAG.getNode(ISD::FNEG, dl, VT, N1);
5951 // fold (fsub A, (fneg B)) -> (fadd A, B)
5952 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
5953 return DAG.getNode(ISD::FADD, dl, VT, N0,
5954 GetNegatedExpression(N1, DAG, LegalOperations));
5956 // If 'unsafe math' is enabled, fold
5957 // (fsub x, x) -> 0.0 &
5958 // (fsub x, (fadd x, y)) -> (fneg y) &
5959 // (fsub x, (fadd y, x)) -> (fneg y)
5960 if (DAG.getTarget().Options.UnsafeFPMath) {
5962 return DAG.getConstantFP(0.0f, VT);
5964 if (N1.getOpcode() == ISD::FADD) {
5965 SDValue N10 = N1->getOperand(0);
5966 SDValue N11 = N1->getOperand(1);
5968 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI,
5969 &DAG.getTarget().Options))
5970 return GetNegatedExpression(N11, DAG, LegalOperations);
5971 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI,
5972 &DAG.getTarget().Options))
5973 return GetNegatedExpression(N10, DAG, LegalOperations);
5977 // FSUB -> FMA combines:
5978 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
5979 DAG.getTarget().Options.UnsafeFPMath) &&
5980 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) &&
5981 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) {
5983 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
5984 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) {
5985 return DAG.getNode(ISD::FMA, dl, VT,
5986 N0.getOperand(0), N0.getOperand(1),
5987 DAG.getNode(ISD::FNEG, dl, VT, N1));
5990 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
5991 // Note: Commutes FSUB operands.
5992 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) {
5993 return DAG.getNode(ISD::FMA, dl, VT,
5994 DAG.getNode(ISD::FNEG, dl, VT,
5996 N1.getOperand(1), N0);
5999 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
6000 if (N0.getOpcode() == ISD::FNEG &&
6001 N0.getOperand(0).getOpcode() == ISD::FMUL &&
6002 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) {
6003 SDValue N00 = N0.getOperand(0).getOperand(0);
6004 SDValue N01 = N0.getOperand(0).getOperand(1);
6005 return DAG.getNode(ISD::FMA, dl, VT,
6006 DAG.getNode(ISD::FNEG, dl, VT, N00), N01,
6007 DAG.getNode(ISD::FNEG, dl, VT, N1));
6014 SDValue DAGCombiner::visitFMUL(SDNode *N) {
6015 SDValue N0 = N->getOperand(0);
6016 SDValue N1 = N->getOperand(1);
6017 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6018 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6019 EVT VT = N->getValueType(0);
6020 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6023 if (VT.isVector()) {
6024 SDValue FoldedVOp = SimplifyVBinOp(N);
6025 if (FoldedVOp.getNode()) return FoldedVOp;
6028 // fold (fmul c1, c2) -> c1*c2
6030 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
6031 // canonicalize constant to RHS
6032 if (N0CFP && !N1CFP)
6033 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
6034 // fold (fmul A, 0) -> 0
6035 if (DAG.getTarget().Options.UnsafeFPMath &&
6036 N1CFP && N1CFP->getValueAPF().isZero())
6038 // fold (fmul A, 0) -> 0, vector edition.
6039 if (DAG.getTarget().Options.UnsafeFPMath &&
6040 ISD::isBuildVectorAllZeros(N1.getNode()))
6042 // fold (fmul A, 1.0) -> A
6043 if (N1CFP && N1CFP->isExactlyValue(1.0))
6045 // fold (fmul X, 2.0) -> (fadd X, X)
6046 if (N1CFP && N1CFP->isExactlyValue(+2.0))
6047 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
6048 // fold (fmul X, -1.0) -> (fneg X)
6049 if (N1CFP && N1CFP->isExactlyValue(-1.0))
6050 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6051 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
6053 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
6054 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6055 &DAG.getTarget().Options)) {
6056 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
6057 &DAG.getTarget().Options)) {
6058 // Both can be negated for free, check to see if at least one is cheaper
6060 if (LHSNeg == 2 || RHSNeg == 2)
6061 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
6062 GetNegatedExpression(N0, DAG, LegalOperations),
6063 GetNegatedExpression(N1, DAG, LegalOperations));
6067 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
6068 if (DAG.getTarget().Options.UnsafeFPMath &&
6069 N1CFP && N0.getOpcode() == ISD::FMUL &&
6070 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
6071 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
6072 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
6073 N0.getOperand(1), N1));
6078 SDValue DAGCombiner::visitFMA(SDNode *N) {
6079 SDValue N0 = N->getOperand(0);
6080 SDValue N1 = N->getOperand(1);
6081 SDValue N2 = N->getOperand(2);
6082 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6083 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6084 EVT VT = N->getValueType(0);
6085 DebugLoc dl = N->getDebugLoc();
6087 if (DAG.getTarget().Options.UnsafeFPMath) {
6088 if (N0CFP && N0CFP->isZero())
6090 if (N1CFP && N1CFP->isZero())
6093 if (N0CFP && N0CFP->isExactlyValue(1.0))
6094 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2);
6095 if (N1CFP && N1CFP->isExactlyValue(1.0))
6096 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2);
6098 // Canonicalize (fma c, x, y) -> (fma x, c, y)
6099 if (N0CFP && !N1CFP)
6100 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2);
6102 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
6103 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6104 N2.getOpcode() == ISD::FMUL &&
6105 N0 == N2.getOperand(0) &&
6106 N2.getOperand(1).getOpcode() == ISD::ConstantFP) {
6107 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6108 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1)));
6112 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
6113 if (DAG.getTarget().Options.UnsafeFPMath &&
6114 N0.getOpcode() == ISD::FMUL && N1CFP &&
6115 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
6116 return DAG.getNode(ISD::FMA, dl, VT,
6118 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
6122 // (fma x, 1, y) -> (fadd x, y)
6123 // (fma x, -1, y) -> (fadd (fneg x), y)
6125 if (N1CFP->isExactlyValue(1.0))
6126 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
6128 if (N1CFP->isExactlyValue(-1.0) &&
6129 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
6130 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
6131 AddToWorkList(RHSNeg.getNode());
6132 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
6136 // (fma x, c, x) -> (fmul x, (c+1))
6137 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) {
6138 return DAG.getNode(ISD::FMUL, dl, VT,
6140 DAG.getNode(ISD::FADD, dl, VT,
6141 N1, DAG.getConstantFP(1.0, VT)));
6144 // (fma x, c, (fneg x)) -> (fmul x, (c-1))
6145 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6146 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) {
6147 return DAG.getNode(ISD::FMUL, dl, VT,
6149 DAG.getNode(ISD::FADD, dl, VT,
6150 N1, DAG.getConstantFP(-1.0, VT)));
6157 SDValue DAGCombiner::visitFDIV(SDNode *N) {
6158 SDValue N0 = N->getOperand(0);
6159 SDValue N1 = N->getOperand(1);
6160 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6161 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6162 EVT VT = N->getValueType(0);
6163 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6166 if (VT.isVector()) {
6167 SDValue FoldedVOp = SimplifyVBinOp(N);
6168 if (FoldedVOp.getNode()) return FoldedVOp;
6171 // fold (fdiv c1, c2) -> c1/c2
6173 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
6175 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
6176 if (N1CFP && DAG.getTarget().Options.UnsafeFPMath) {
6177 // Compute the reciprocal 1.0 / c2.
6178 APFloat N1APF = N1CFP->getValueAPF();
6179 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
6180 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
6181 // Only do the transform if the reciprocal is a legal fp immediate that
6182 // isn't too nasty (eg NaN, denormal, ...).
6183 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
6184 (!LegalOperations ||
6185 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
6186 // backend)... we should handle this gracefully after Legalize.
6187 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
6188 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
6189 TLI.isFPImmLegal(Recip, VT)))
6190 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0,
6191 DAG.getConstantFP(Recip, VT));
6194 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
6195 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6196 &DAG.getTarget().Options)) {
6197 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
6198 &DAG.getTarget().Options)) {
6199 // Both can be negated for free, check to see if at least one is cheaper
6201 if (LHSNeg == 2 || RHSNeg == 2)
6202 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
6203 GetNegatedExpression(N0, DAG, LegalOperations),
6204 GetNegatedExpression(N1, DAG, LegalOperations));
6211 SDValue DAGCombiner::visitFREM(SDNode *N) {
6212 SDValue N0 = N->getOperand(0);
6213 SDValue N1 = N->getOperand(1);
6214 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6215 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6216 EVT VT = N->getValueType(0);
6218 // fold (frem c1, c2) -> fmod(c1,c2)
6220 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
6225 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
6226 SDValue N0 = N->getOperand(0);
6227 SDValue N1 = N->getOperand(1);
6228 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6229 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6230 EVT VT = N->getValueType(0);
6232 if (N0CFP && N1CFP) // Constant fold
6233 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
6236 const APFloat& V = N1CFP->getValueAPF();
6237 // copysign(x, c1) -> fabs(x) iff ispos(c1)
6238 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
6239 if (!V.isNegative()) {
6240 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
6241 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6243 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6244 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
6245 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
6249 // copysign(fabs(x), y) -> copysign(x, y)
6250 // copysign(fneg(x), y) -> copysign(x, y)
6251 // copysign(copysign(x,z), y) -> copysign(x, y)
6252 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
6253 N0.getOpcode() == ISD::FCOPYSIGN)
6254 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6255 N0.getOperand(0), N1);
6257 // copysign(x, abs(y)) -> abs(x)
6258 if (N1.getOpcode() == ISD::FABS)
6259 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6261 // copysign(x, copysign(y,z)) -> copysign(x, z)
6262 if (N1.getOpcode() == ISD::FCOPYSIGN)
6263 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6264 N0, N1.getOperand(1));
6266 // copysign(x, fp_extend(y)) -> copysign(x, y)
6267 // copysign(x, fp_round(y)) -> copysign(x, y)
6268 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
6269 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6270 N0, N1.getOperand(0));
6275 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
6276 SDValue N0 = N->getOperand(0);
6277 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6278 EVT VT = N->getValueType(0);
6279 EVT OpVT = N0.getValueType();
6281 // fold (sint_to_fp c1) -> c1fp
6283 // ...but only if the target supports immediate floating-point values
6284 (!LegalOperations ||
6285 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6286 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
6288 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
6289 // but UINT_TO_FP is legal on this target, try to convert.
6290 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
6291 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
6292 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
6293 if (DAG.SignBitIsZero(N0))
6294 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
6297 // The next optimizations are desireable only if SELECT_CC can be lowered.
6298 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
6299 // having to say they don't support SELECT_CC on every type the DAG knows
6300 // about, since there is no way to mark an opcode illegal at all value types
6301 // (See also visitSELECT)
6302 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
6303 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6304 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
6306 (!LegalOperations ||
6307 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6309 { N0.getOperand(0), N0.getOperand(1),
6310 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT),
6312 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6315 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
6316 // (select_cc x, y, 1.0, 0.0,, cc)
6317 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
6318 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
6319 (!LegalOperations ||
6320 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6322 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
6323 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT),
6324 N0.getOperand(0).getOperand(2) };
6325 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6332 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
6333 SDValue N0 = N->getOperand(0);
6334 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6335 EVT VT = N->getValueType(0);
6336 EVT OpVT = N0.getValueType();
6338 // fold (uint_to_fp c1) -> c1fp
6340 // ...but only if the target supports immediate floating-point values
6341 (!LegalOperations ||
6342 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6343 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
6345 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
6346 // but SINT_TO_FP is legal on this target, try to convert.
6347 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
6348 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
6349 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
6350 if (DAG.SignBitIsZero(N0))
6351 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
6354 // The next optimizations are desireable only if SELECT_CC can be lowered.
6355 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
6356 // having to say they don't support SELECT_CC on every type the DAG knows
6357 // about, since there is no way to mark an opcode illegal at all value types
6358 // (See also visitSELECT)
6359 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
6360 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6362 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
6363 (!LegalOperations ||
6364 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6366 { N0.getOperand(0), N0.getOperand(1),
6367 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT),
6369 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6376 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
6377 SDValue N0 = N->getOperand(0);
6378 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6379 EVT VT = N->getValueType(0);
6381 // fold (fp_to_sint c1fp) -> c1
6383 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
6388 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
6389 SDValue N0 = N->getOperand(0);
6390 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6391 EVT VT = N->getValueType(0);
6393 // fold (fp_to_uint c1fp) -> c1
6395 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
6400 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
6401 SDValue N0 = N->getOperand(0);
6402 SDValue N1 = N->getOperand(1);
6403 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6404 EVT VT = N->getValueType(0);
6406 // fold (fp_round c1fp) -> c1fp
6408 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
6410 // fold (fp_round (fp_extend x)) -> x
6411 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
6412 return N0.getOperand(0);
6414 // fold (fp_round (fp_round x)) -> (fp_round x)
6415 if (N0.getOpcode() == ISD::FP_ROUND) {
6416 // This is a value preserving truncation if both round's are.
6417 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
6418 N0.getNode()->getConstantOperandVal(1) == 1;
6419 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
6420 DAG.getIntPtrConstant(IsTrunc));
6423 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
6424 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
6425 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
6426 N0.getOperand(0), N1);
6427 AddToWorkList(Tmp.getNode());
6428 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6429 Tmp, N0.getOperand(1));
6435 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
6436 SDValue N0 = N->getOperand(0);
6437 EVT VT = N->getValueType(0);
6438 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
6439 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6441 // fold (fp_round_inreg c1fp) -> c1fp
6442 if (N0CFP && isTypeLegal(EVT)) {
6443 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
6444 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
6450 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
6451 SDValue N0 = N->getOperand(0);
6452 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6453 EVT VT = N->getValueType(0);
6455 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
6456 if (N->hasOneUse() &&
6457 N->use_begin()->getOpcode() == ISD::FP_ROUND)
6460 // fold (fp_extend c1fp) -> c1fp
6462 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
6464 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
6466 if (N0.getOpcode() == ISD::FP_ROUND
6467 && N0.getNode()->getConstantOperandVal(1) == 1) {
6468 SDValue In = N0.getOperand(0);
6469 if (In.getValueType() == VT) return In;
6470 if (VT.bitsLT(In.getValueType()))
6471 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
6472 In, N0.getOperand(1));
6473 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
6476 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
6477 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
6478 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6479 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
6480 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6481 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
6483 LN0->getBasePtr(), LN0->getPointerInfo(),
6485 LN0->isVolatile(), LN0->isNonTemporal(),
6486 LN0->getAlignment());
6487 CombineTo(N, ExtLoad);
6488 CombineTo(N0.getNode(),
6489 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
6490 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
6491 ExtLoad.getValue(1));
6492 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6498 SDValue DAGCombiner::visitFNEG(SDNode *N) {
6499 SDValue N0 = N->getOperand(0);
6500 EVT VT = N->getValueType(0);
6502 if (VT.isVector()) {
6503 SDValue FoldedVOp = SimplifyVUnaryOp(N);
6504 if (FoldedVOp.getNode()) return FoldedVOp;
6507 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
6508 &DAG.getTarget().Options))
6509 return GetNegatedExpression(N0, DAG, LegalOperations);
6511 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
6512 // constant pool values.
6513 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST &&
6515 N0.getNode()->hasOneUse() &&
6516 N0.getOperand(0).getValueType().isInteger()) {
6517 SDValue Int = N0.getOperand(0);
6518 EVT IntVT = Int.getValueType();
6519 if (IntVT.isInteger() && !IntVT.isVector()) {
6520 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
6521 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6522 AddToWorkList(Int.getNode());
6523 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6528 // (fneg (fmul c, x)) -> (fmul -c, x)
6529 if (N0.getOpcode() == ISD::FMUL) {
6530 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
6532 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
6534 DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
6542 SDValue DAGCombiner::visitFCEIL(SDNode *N) {
6543 SDValue N0 = N->getOperand(0);
6544 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6545 EVT VT = N->getValueType(0);
6547 // fold (fceil c1) -> fceil(c1)
6549 return DAG.getNode(ISD::FCEIL, N->getDebugLoc(), VT, N0);
6554 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
6555 SDValue N0 = N->getOperand(0);
6556 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6557 EVT VT = N->getValueType(0);
6559 // fold (ftrunc c1) -> ftrunc(c1)
6561 return DAG.getNode(ISD::FTRUNC, N->getDebugLoc(), VT, N0);
6566 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
6567 SDValue N0 = N->getOperand(0);
6568 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6569 EVT VT = N->getValueType(0);
6571 // fold (ffloor c1) -> ffloor(c1)
6573 return DAG.getNode(ISD::FFLOOR, N->getDebugLoc(), VT, N0);
6578 SDValue DAGCombiner::visitFABS(SDNode *N) {
6579 SDValue N0 = N->getOperand(0);
6580 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6581 EVT VT = N->getValueType(0);
6583 if (VT.isVector()) {
6584 SDValue FoldedVOp = SimplifyVUnaryOp(N);
6585 if (FoldedVOp.getNode()) return FoldedVOp;
6588 // fold (fabs c1) -> fabs(c1)
6590 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6591 // fold (fabs (fabs x)) -> (fabs x)
6592 if (N0.getOpcode() == ISD::FABS)
6593 return N->getOperand(0);
6594 // fold (fabs (fneg x)) -> (fabs x)
6595 // fold (fabs (fcopysign x, y)) -> (fabs x)
6596 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
6597 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
6599 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
6600 // constant pool values.
6601 if (!TLI.isFAbsFree(VT) &&
6602 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
6603 N0.getOperand(0).getValueType().isInteger() &&
6604 !N0.getOperand(0).getValueType().isVector()) {
6605 SDValue Int = N0.getOperand(0);
6606 EVT IntVT = Int.getValueType();
6607 if (IntVT.isInteger() && !IntVT.isVector()) {
6608 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
6609 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6610 AddToWorkList(Int.getNode());
6611 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6612 N->getValueType(0), Int);
6619 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
6620 SDValue Chain = N->getOperand(0);
6621 SDValue N1 = N->getOperand(1);
6622 SDValue N2 = N->getOperand(2);
6624 // If N is a constant we could fold this into a fallthrough or unconditional
6625 // branch. However that doesn't happen very often in normal code, because
6626 // Instcombine/SimplifyCFG should have handled the available opportunities.
6627 // If we did this folding here, it would be necessary to update the
6628 // MachineBasicBlock CFG, which is awkward.
6630 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
6632 if (N1.getOpcode() == ISD::SETCC &&
6633 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
6634 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6635 Chain, N1.getOperand(2),
6636 N1.getOperand(0), N1.getOperand(1), N2);
6639 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
6640 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
6641 (N1.getOperand(0).hasOneUse() &&
6642 N1.getOperand(0).getOpcode() == ISD::SRL))) {
6644 if (N1.getOpcode() == ISD::TRUNCATE) {
6645 // Look pass the truncate.
6646 Trunc = N1.getNode();
6647 N1 = N1.getOperand(0);
6650 // Match this pattern so that we can generate simpler code:
6653 // %b = and i32 %a, 2
6654 // %c = srl i32 %b, 1
6655 // brcond i32 %c ...
6660 // %b = and i32 %a, 2
6661 // %c = setcc eq %b, 0
6664 // This applies only when the AND constant value has one bit set and the
6665 // SRL constant is equal to the log2 of the AND constant. The back-end is
6666 // smart enough to convert the result into a TEST/JMP sequence.
6667 SDValue Op0 = N1.getOperand(0);
6668 SDValue Op1 = N1.getOperand(1);
6670 if (Op0.getOpcode() == ISD::AND &&
6671 Op1.getOpcode() == ISD::Constant) {
6672 SDValue AndOp1 = Op0.getOperand(1);
6674 if (AndOp1.getOpcode() == ISD::Constant) {
6675 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
6677 if (AndConst.isPowerOf2() &&
6678 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
6680 DAG.getSetCC(N->getDebugLoc(),
6681 TLI.getSetCCResultType(Op0.getValueType()),
6682 Op0, DAG.getConstant(0, Op0.getValueType()),
6685 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6686 MVT::Other, Chain, SetCC, N2);
6687 // Don't add the new BRCond into the worklist or else SimplifySelectCC
6688 // will convert it back to (X & C1) >> C2.
6689 CombineTo(N, NewBRCond, false);
6690 // Truncate is dead.
6692 removeFromWorkList(Trunc);
6693 DAG.DeleteNode(Trunc);
6695 // Replace the uses of SRL with SETCC
6696 WorkListRemover DeadNodes(*this);
6697 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6698 removeFromWorkList(N1.getNode());
6699 DAG.DeleteNode(N1.getNode());
6700 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6706 // Restore N1 if the above transformation doesn't match.
6707 N1 = N->getOperand(1);
6710 // Transform br(xor(x, y)) -> br(x != y)
6711 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
6712 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
6713 SDNode *TheXor = N1.getNode();
6714 SDValue Op0 = TheXor->getOperand(0);
6715 SDValue Op1 = TheXor->getOperand(1);
6716 if (Op0.getOpcode() == Op1.getOpcode()) {
6717 // Avoid missing important xor optimizations.
6718 SDValue Tmp = visitXOR(TheXor);
6719 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
6720 DEBUG(dbgs() << "\nReplacing.8 ";
6722 dbgs() << "\nWith: ";
6723 Tmp.getNode()->dump(&DAG);
6725 WorkListRemover DeadNodes(*this);
6726 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
6727 removeFromWorkList(TheXor);
6728 DAG.DeleteNode(TheXor);
6729 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6730 MVT::Other, Chain, Tmp, N2);
6734 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
6736 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
6737 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
6738 Op0.getOpcode() == ISD::XOR) {
6739 TheXor = Op0.getNode();
6743 EVT SetCCVT = N1.getValueType();
6745 SetCCVT = TLI.getSetCCResultType(SetCCVT);
6746 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
6749 Equal ? ISD::SETEQ : ISD::SETNE);
6750 // Replace the uses of XOR with SETCC
6751 WorkListRemover DeadNodes(*this);
6752 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6753 removeFromWorkList(N1.getNode());
6754 DAG.DeleteNode(N1.getNode());
6755 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6756 MVT::Other, Chain, SetCC, N2);
6763 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
6765 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
6766 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
6767 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
6769 // If N is a constant we could fold this into a fallthrough or unconditional
6770 // branch. However that doesn't happen very often in normal code, because
6771 // Instcombine/SimplifyCFG should have handled the available opportunities.
6772 // If we did this folding here, it would be necessary to update the
6773 // MachineBasicBlock CFG, which is awkward.
6775 // Use SimplifySetCC to simplify SETCC's.
6776 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
6777 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
6779 if (Simp.getNode()) AddToWorkList(Simp.getNode());
6781 // fold to a simpler setcc
6782 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
6783 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6784 N->getOperand(0), Simp.getOperand(2),
6785 Simp.getOperand(0), Simp.getOperand(1),
6791 /// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
6792 /// uses N as its base pointer and that N may be folded in the load / store
6793 /// addressing mode.
6794 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
6796 const TargetLowering &TLI) {
6798 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
6799 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
6801 VT = Use->getValueType(0);
6802 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
6803 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
6805 VT = ST->getValue().getValueType();
6810 if (N->getOpcode() == ISD::ADD) {
6811 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6814 AM.BaseOffs = Offset->getSExtValue();
6818 } else if (N->getOpcode() == ISD::SUB) {
6819 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6822 AM.BaseOffs = -Offset->getSExtValue();
6829 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
6832 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
6833 /// pre-indexed load / store when the base pointer is an add or subtract
6834 /// and it has other uses besides the load / store. After the
6835 /// transformation, the new indexed load / store has effectively folded
6836 /// the add / subtract in and all of its other uses are redirected to the
6837 /// new load / store.
6838 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
6839 if (Level < AfterLegalizeDAG)
6845 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6846 if (LD->isIndexed())
6848 VT = LD->getMemoryVT();
6849 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
6850 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
6852 Ptr = LD->getBasePtr();
6853 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6854 if (ST->isIndexed())
6856 VT = ST->getMemoryVT();
6857 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
6858 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
6860 Ptr = ST->getBasePtr();
6866 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
6867 // out. There is no reason to make this a preinc/predec.
6868 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
6869 Ptr.getNode()->hasOneUse())
6872 // Ask the target to do addressing mode selection.
6875 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6876 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
6878 // Don't create a indexed load / store with zero offset.
6879 if (isa<ConstantSDNode>(Offset) &&
6880 cast<ConstantSDNode>(Offset)->isNullValue())
6883 // Try turning it into a pre-indexed load / store except when:
6884 // 1) The new base ptr is a frame index.
6885 // 2) If N is a store and the new base ptr is either the same as or is a
6886 // predecessor of the value being stored.
6887 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
6888 // that would create a cycle.
6889 // 4) All uses are load / store ops that use it as old base ptr.
6891 // Check #1. Preinc'ing a frame index would require copying the stack pointer
6892 // (plus the implicit offset) to a register to preinc anyway.
6893 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6898 SDValue Val = cast<StoreSDNode>(N)->getValue();
6899 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
6903 // Now check for #3 and #4.
6904 bool RealUse = false;
6906 // Caches for hasPredecessorHelper
6907 SmallPtrSet<const SDNode *, 32> Visited;
6908 SmallVector<const SDNode *, 16> Worklist;
6910 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6911 E = Ptr.getNode()->use_end(); I != E; ++I) {
6915 if (N->hasPredecessorHelper(Use, Visited, Worklist))
6918 // If Ptr may be folded in addressing mode of other use, then it's
6919 // not profitable to do this transformation.
6920 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
6929 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6930 BasePtr, Offset, AM);
6932 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6933 BasePtr, Offset, AM);
6936 DEBUG(dbgs() << "\nReplacing.4 ";
6938 dbgs() << "\nWith: ";
6939 Result.getNode()->dump(&DAG);
6941 WorkListRemover DeadNodes(*this);
6943 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
6944 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
6946 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
6949 // Finally, since the node is now dead, remove it from the graph.
6952 // Replace the uses of Ptr with uses of the updated base value.
6953 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
6954 removeFromWorkList(Ptr.getNode());
6955 DAG.DeleteNode(Ptr.getNode());
6960 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
6961 /// add / sub of the base pointer node into a post-indexed load / store.
6962 /// The transformation folded the add / subtract into the new indexed
6963 /// load / store effectively and all of its uses are redirected to the
6964 /// new load / store.
6965 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
6966 if (Level < AfterLegalizeDAG)
6972 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6973 if (LD->isIndexed())
6975 VT = LD->getMemoryVT();
6976 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
6977 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
6979 Ptr = LD->getBasePtr();
6980 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6981 if (ST->isIndexed())
6983 VT = ST->getMemoryVT();
6984 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
6985 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
6987 Ptr = ST->getBasePtr();
6993 if (Ptr.getNode()->hasOneUse())
6996 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6997 E = Ptr.getNode()->use_end(); I != E; ++I) {
7000 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
7005 ISD::MemIndexedMode AM = ISD::UNINDEXED;
7006 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
7007 // Don't create a indexed load / store with zero offset.
7008 if (isa<ConstantSDNode>(Offset) &&
7009 cast<ConstantSDNode>(Offset)->isNullValue())
7012 // Try turning it into a post-indexed load / store except when
7013 // 1) All uses are load / store ops that use it as base ptr (and
7014 // it may be folded as addressing mmode).
7015 // 2) Op must be independent of N, i.e. Op is neither a predecessor
7016 // nor a successor of N. Otherwise, if Op is folded that would
7019 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
7023 bool TryNext = false;
7024 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
7025 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
7027 if (Use == Ptr.getNode())
7030 // If all the uses are load / store addresses, then don't do the
7032 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
7033 bool RealUse = false;
7034 for (SDNode::use_iterator III = Use->use_begin(),
7035 EEE = Use->use_end(); III != EEE; ++III) {
7036 SDNode *UseUse = *III;
7037 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
7052 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
7053 SDValue Result = isLoad
7054 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
7055 BasePtr, Offset, AM)
7056 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
7057 BasePtr, Offset, AM);
7060 DEBUG(dbgs() << "\nReplacing.5 ";
7062 dbgs() << "\nWith: ";
7063 Result.getNode()->dump(&DAG);
7065 WorkListRemover DeadNodes(*this);
7067 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
7068 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
7070 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
7073 // Finally, since the node is now dead, remove it from the graph.
7076 // Replace the uses of Use with uses of the updated base value.
7077 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
7078 Result.getValue(isLoad ? 1 : 0));
7079 removeFromWorkList(Op);
7089 SDValue DAGCombiner::visitLOAD(SDNode *N) {
7090 LoadSDNode *LD = cast<LoadSDNode>(N);
7091 SDValue Chain = LD->getChain();
7092 SDValue Ptr = LD->getBasePtr();
7094 // If load is not volatile and there are no uses of the loaded value (and
7095 // the updated indexed value in case of indexed loads), change uses of the
7096 // chain value into uses of the chain input (i.e. delete the dead load).
7097 if (!LD->isVolatile()) {
7098 if (N->getValueType(1) == MVT::Other) {
7100 if (!N->hasAnyUseOfValue(0)) {
7101 // It's not safe to use the two value CombineTo variant here. e.g.
7102 // v1, chain2 = load chain1, loc
7103 // v2, chain3 = load chain2, loc
7105 // Now we replace use of chain2 with chain1. This makes the second load
7106 // isomorphic to the one we are deleting, and thus makes this load live.
7107 DEBUG(dbgs() << "\nReplacing.6 ";
7109 dbgs() << "\nWith chain: ";
7110 Chain.getNode()->dump(&DAG);
7112 WorkListRemover DeadNodes(*this);
7113 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
7115 if (N->use_empty()) {
7116 removeFromWorkList(N);
7120 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7124 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
7125 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) {
7126 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
7127 DEBUG(dbgs() << "\nReplacing.7 ";
7129 dbgs() << "\nWith: ";
7130 Undef.getNode()->dump(&DAG);
7131 dbgs() << " and 2 other values\n");
7132 WorkListRemover DeadNodes(*this);
7133 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
7134 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
7135 DAG.getUNDEF(N->getValueType(1)));
7136 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
7137 removeFromWorkList(N);
7139 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7144 // If this load is directly stored, replace the load value with the stored
7146 // TODO: Handle store large -> read small portion.
7147 // TODO: Handle TRUNCSTORE/LOADEXT
7148 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
7149 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
7150 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
7151 if (PrevST->getBasePtr() == Ptr &&
7152 PrevST->getValue().getValueType() == N->getValueType(0))
7153 return CombineTo(N, Chain.getOperand(1), Chain);
7157 // Try to infer better alignment information than the load already has.
7158 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
7159 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
7160 if (Align > LD->getAlignment())
7161 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
7162 LD->getValueType(0),
7163 Chain, Ptr, LD->getPointerInfo(),
7165 LD->isVolatile(), LD->isNonTemporal(), Align);
7170 // Walk up chain skipping non-aliasing memory nodes.
7171 SDValue BetterChain = FindBetterChain(N, Chain);
7173 // If there is a better chain.
7174 if (Chain != BetterChain) {
7177 // Replace the chain to void dependency.
7178 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
7179 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
7180 BetterChain, Ptr, LD->getPointerInfo(),
7181 LD->isVolatile(), LD->isNonTemporal(),
7182 LD->isInvariant(), LD->getAlignment());
7184 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
7185 LD->getValueType(0),
7186 BetterChain, Ptr, LD->getPointerInfo(),
7189 LD->isNonTemporal(),
7190 LD->getAlignment());
7193 // Create token factor to keep old chain connected.
7194 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
7195 MVT::Other, Chain, ReplLoad.getValue(1));
7197 // Make sure the new and old chains are cleaned up.
7198 AddToWorkList(Token.getNode());
7200 // Replace uses with load result and token factor. Don't add users
7202 return CombineTo(N, ReplLoad.getValue(0), Token, false);
7206 // Try transforming N to an indexed load.
7207 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
7208 return SDValue(N, 0);
7213 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
7214 /// load is having specific bytes cleared out. If so, return the byte size
7215 /// being masked out and the shift amount.
7216 static std::pair<unsigned, unsigned>
7217 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
7218 std::pair<unsigned, unsigned> Result(0, 0);
7220 // Check for the structure we're looking for.
7221 if (V->getOpcode() != ISD::AND ||
7222 !isa<ConstantSDNode>(V->getOperand(1)) ||
7223 !ISD::isNormalLoad(V->getOperand(0).getNode()))
7226 // Check the chain and pointer.
7227 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
7228 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
7230 // The store should be chained directly to the load or be an operand of a
7232 if (LD == Chain.getNode())
7234 else if (Chain->getOpcode() != ISD::TokenFactor)
7235 return Result; // Fail.
7238 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
7239 if (Chain->getOperand(i).getNode() == LD) {
7243 if (!isOk) return Result;
7246 // This only handles simple types.
7247 if (V.getValueType() != MVT::i16 &&
7248 V.getValueType() != MVT::i32 &&
7249 V.getValueType() != MVT::i64)
7252 // Check the constant mask. Invert it so that the bits being masked out are
7253 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
7254 // follow the sign bit for uniformity.
7255 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
7256 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
7257 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
7258 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
7259 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
7260 if (NotMaskLZ == 64) return Result; // All zero mask.
7262 // See if we have a continuous run of bits. If so, we have 0*1+0*
7263 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
7266 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
7267 if (V.getValueType() != MVT::i64 && NotMaskLZ)
7268 NotMaskLZ -= 64-V.getValueSizeInBits();
7270 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
7271 switch (MaskedBytes) {
7275 default: return Result; // All one mask, or 5-byte mask.
7278 // Verify that the first bit starts at a multiple of mask so that the access
7279 // is aligned the same as the access width.
7280 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
7282 Result.first = MaskedBytes;
7283 Result.second = NotMaskTZ/8;
7288 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
7289 /// provides a value as specified by MaskInfo. If so, replace the specified
7290 /// store with a narrower store of truncated IVal.
7292 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
7293 SDValue IVal, StoreSDNode *St,
7295 unsigned NumBytes = MaskInfo.first;
7296 unsigned ByteShift = MaskInfo.second;
7297 SelectionDAG &DAG = DC->getDAG();
7299 // Check to see if IVal is all zeros in the part being masked in by the 'or'
7300 // that uses this. If not, this is not a replacement.
7301 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
7302 ByteShift*8, (ByteShift+NumBytes)*8);
7303 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
7305 // Check that it is legal on the target to do this. It is legal if the new
7306 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
7308 MVT VT = MVT::getIntegerVT(NumBytes*8);
7309 if (!DC->isTypeLegal(VT))
7312 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
7313 // shifted by ByteShift and truncated down to NumBytes.
7315 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
7316 DAG.getConstant(ByteShift*8,
7317 DC->getShiftAmountTy(IVal.getValueType())));
7319 // Figure out the offset for the store and the alignment of the access.
7321 unsigned NewAlign = St->getAlignment();
7323 if (DAG.getTargetLoweringInfo().isLittleEndian())
7324 StOffset = ByteShift;
7326 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
7328 SDValue Ptr = St->getBasePtr();
7330 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
7331 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
7332 NewAlign = MinAlign(NewAlign, StOffset);
7335 // Truncate down to the new size.
7336 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
7339 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
7340 St->getPointerInfo().getWithOffset(StOffset),
7341 false, false, NewAlign).getNode();
7345 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
7346 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
7347 /// of the loaded bits, try narrowing the load and store if it would end up
7348 /// being a win for performance or code size.
7349 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
7350 StoreSDNode *ST = cast<StoreSDNode>(N);
7351 if (ST->isVolatile())
7354 SDValue Chain = ST->getChain();
7355 SDValue Value = ST->getValue();
7356 SDValue Ptr = ST->getBasePtr();
7357 EVT VT = Value.getValueType();
7359 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
7362 unsigned Opc = Value.getOpcode();
7364 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
7365 // is a byte mask indicating a consecutive number of bytes, check to see if
7366 // Y is known to provide just those bytes. If so, we try to replace the
7367 // load + replace + store sequence with a single (narrower) store, which makes
7369 if (Opc == ISD::OR) {
7370 std::pair<unsigned, unsigned> MaskedLoad;
7371 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
7372 if (MaskedLoad.first)
7373 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
7374 Value.getOperand(1), ST,this))
7375 return SDValue(NewST, 0);
7377 // Or is commutative, so try swapping X and Y.
7378 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
7379 if (MaskedLoad.first)
7380 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
7381 Value.getOperand(0), ST,this))
7382 return SDValue(NewST, 0);
7385 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
7386 Value.getOperand(1).getOpcode() != ISD::Constant)
7389 SDValue N0 = Value.getOperand(0);
7390 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7391 Chain == SDValue(N0.getNode(), 1)) {
7392 LoadSDNode *LD = cast<LoadSDNode>(N0);
7393 if (LD->getBasePtr() != Ptr ||
7394 LD->getPointerInfo().getAddrSpace() !=
7395 ST->getPointerInfo().getAddrSpace())
7398 // Find the type to narrow it the load / op / store to.
7399 SDValue N1 = Value.getOperand(1);
7400 unsigned BitWidth = N1.getValueSizeInBits();
7401 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
7402 if (Opc == ISD::AND)
7403 Imm ^= APInt::getAllOnesValue(BitWidth);
7404 if (Imm == 0 || Imm.isAllOnesValue())
7406 unsigned ShAmt = Imm.countTrailingZeros();
7407 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
7408 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
7409 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
7410 while (NewBW < BitWidth &&
7411 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
7412 TLI.isNarrowingProfitable(VT, NewVT))) {
7413 NewBW = NextPowerOf2(NewBW);
7414 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
7416 if (NewBW >= BitWidth)
7419 // If the lsb changed does not start at the type bitwidth boundary,
7420 // start at the previous one.
7422 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
7423 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
7424 if ((Imm & Mask) == Imm) {
7425 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
7426 if (Opc == ISD::AND)
7427 NewImm ^= APInt::getAllOnesValue(NewBW);
7428 uint64_t PtrOff = ShAmt / 8;
7429 // For big endian targets, we need to adjust the offset to the pointer to
7430 // load the correct bytes.
7431 if (TLI.isBigEndian())
7432 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
7434 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
7435 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
7436 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy))
7439 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
7440 Ptr.getValueType(), Ptr,
7441 DAG.getConstant(PtrOff, Ptr.getValueType()));
7442 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
7443 LD->getChain(), NewPtr,
7444 LD->getPointerInfo().getWithOffset(PtrOff),
7445 LD->isVolatile(), LD->isNonTemporal(),
7446 LD->isInvariant(), NewAlign);
7447 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
7448 DAG.getConstant(NewImm, NewVT));
7449 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
7451 ST->getPointerInfo().getWithOffset(PtrOff),
7452 false, false, NewAlign);
7454 AddToWorkList(NewPtr.getNode());
7455 AddToWorkList(NewLD.getNode());
7456 AddToWorkList(NewVal.getNode());
7457 WorkListRemover DeadNodes(*this);
7458 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
7467 /// TransformFPLoadStorePair - For a given floating point load / store pair,
7468 /// if the load value isn't used by any other operations, then consider
7469 /// transforming the pair to integer load / store operations if the target
7470 /// deems the transformation profitable.
7471 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
7472 StoreSDNode *ST = cast<StoreSDNode>(N);
7473 SDValue Chain = ST->getChain();
7474 SDValue Value = ST->getValue();
7475 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
7476 Value.hasOneUse() &&
7477 Chain == SDValue(Value.getNode(), 1)) {
7478 LoadSDNode *LD = cast<LoadSDNode>(Value);
7479 EVT VT = LD->getMemoryVT();
7480 if (!VT.isFloatingPoint() ||
7481 VT != ST->getMemoryVT() ||
7482 LD->isNonTemporal() ||
7483 ST->isNonTemporal() ||
7484 LD->getPointerInfo().getAddrSpace() != 0 ||
7485 ST->getPointerInfo().getAddrSpace() != 0)
7488 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
7489 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
7490 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
7491 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
7492 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
7495 unsigned LDAlign = LD->getAlignment();
7496 unsigned STAlign = ST->getAlignment();
7497 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
7498 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy);
7499 if (LDAlign < ABIAlign || STAlign < ABIAlign)
7502 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
7503 LD->getChain(), LD->getBasePtr(),
7504 LD->getPointerInfo(),
7505 false, false, false, LDAlign);
7507 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
7508 NewLD, ST->getBasePtr(),
7509 ST->getPointerInfo(),
7510 false, false, STAlign);
7512 AddToWorkList(NewLD.getNode());
7513 AddToWorkList(NewST.getNode());
7514 WorkListRemover DeadNodes(*this);
7515 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
7523 /// Returns the base pointer and an integer offset from that object.
7524 static std::pair<SDValue, int64_t> GetPointerBaseAndOffset(SDValue Ptr) {
7525 if (Ptr->getOpcode() == ISD::ADD && isa<ConstantSDNode>(Ptr->getOperand(1))) {
7526 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
7527 SDValue Base = Ptr->getOperand(0);
7528 return std::make_pair(Base, Offset);
7531 return std::make_pair(Ptr, 0);
7534 /// Holds a pointer to an LSBaseSDNode as well as information on where it
7535 /// is located in a sequence of memory operations connected by a chain.
7537 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq):
7538 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { }
7539 // Ptr to the mem node.
7540 LSBaseSDNode *MemNode;
7541 // Offset from the base ptr.
7542 int64_t OffsetFromBase;
7543 // What is the sequence number of this mem node.
7544 // Lowest mem operand in the DAG starts at zero.
7545 unsigned SequenceNum;
7548 /// Sorts store nodes in a link according to their offset from a shared
7550 struct ConsecutiveMemoryChainSorter {
7551 bool operator()(MemOpLink LHS, MemOpLink RHS) {
7552 return LHS.OffsetFromBase < RHS.OffsetFromBase;
7556 bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
7557 EVT MemVT = St->getMemoryVT();
7558 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8;
7560 // Don't merge vectors into wider inputs.
7561 if (MemVT.isVector() || !MemVT.isSimple())
7564 // Perform an early exit check. Do not bother looking at stored values that
7565 // are not constants or loads.
7566 SDValue StoredVal = St->getValue();
7567 bool IsLoadSrc = isa<LoadSDNode>(StoredVal);
7568 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) &&
7572 // Only look at ends of store sequences.
7573 SDValue Chain = SDValue(St, 1);
7574 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
7577 // This holds the base pointer and the offset in bytes from the base pointer.
7578 std::pair<SDValue, int64_t> BasePtr =
7579 GetPointerBaseAndOffset(St->getBasePtr());
7581 // We must have a base and an offset.
7582 if (!BasePtr.first.getNode())
7585 // Do not handle stores to undef base pointers.
7586 if (BasePtr.first.getOpcode() == ISD::UNDEF)
7589 // Save the LoadSDNodes that we find in the chain.
7590 // We need to make sure that these nodes do not interfere with
7591 // any of the store nodes.
7592 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
7594 // Save the StoreSDNodes that we find in the chain.
7595 SmallVector<MemOpLink, 8> StoreNodes;
7597 // Walk up the chain and look for nodes with offsets from the same
7598 // base pointer. Stop when reaching an instruction with a different kind
7599 // or instruction which has a different base pointer.
7601 StoreSDNode *Index = St;
7603 // If the chain has more than one use, then we can't reorder the mem ops.
7604 if (Index != St && !SDValue(Index, 1)->hasOneUse())
7607 // Find the base pointer and offset for this memory node.
7608 std::pair<SDValue, int64_t> Ptr =
7609 GetPointerBaseAndOffset(Index->getBasePtr());
7611 // Check that the base pointer is the same as the original one.
7612 if (Ptr.first.getNode() != BasePtr.first.getNode())
7615 // Check that the alignment is the same.
7616 if (Index->getAlignment() != St->getAlignment())
7619 // The memory operands must not be volatile.
7620 if (Index->isVolatile() || Index->isIndexed())
7624 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index))
7625 if (St->isTruncatingStore())
7628 // The stored memory type must be the same.
7629 if (Index->getMemoryVT() != MemVT)
7632 // We do not allow unaligned stores because we want to prevent overriding
7634 if (Index->getAlignment()*8 != MemVT.getSizeInBits())
7637 // We found a potential memory operand to merge.
7638 StoreNodes.push_back(MemOpLink(Index, Ptr.second, Seq++));
7640 // Find the next memory operand in the chain. If the next operand in the
7641 // chain is a store then move up and continue the scan with the next
7642 // memory operand. If the next operand is a load save it and use alias
7643 // information to check if it interferes with anything.
7644 SDNode *NextInChain = Index->getChain().getNode();
7646 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) {
7647 // We found a store node. Use it for the next iteration.
7650 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) {
7651 // Save the load node for later. Continue the scan.
7652 AliasLoadNodes.push_back(Ldn);
7653 NextInChain = Ldn->getChain().getNode();
7662 // Check if there is anything to merge.
7663 if (StoreNodes.size() < 2)
7666 // Sort the memory operands according to their distance from the base pointer.
7667 std::sort(StoreNodes.begin(), StoreNodes.end(),
7668 ConsecutiveMemoryChainSorter());
7670 // Scan the memory operations on the chain and find the first non-consecutive
7671 // store memory address.
7672 unsigned LastConsecutiveStore = 0;
7673 int64_t StartAddress = StoreNodes[0].OffsetFromBase;
7674 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) {
7676 // Check that the addresses are consecutive starting from the second
7677 // element in the list of stores.
7679 int64_t CurrAddress = StoreNodes[i].OffsetFromBase;
7680 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
7685 // Check if this store interferes with any of the loads that we found.
7686 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld)
7687 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) {
7691 // We found a load that alias with this store. Stop the sequence.
7695 // Mark this node as useful.
7696 LastConsecutiveStore = i;
7699 // The node with the lowest store address.
7700 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
7702 // Store the constants into memory as one consecutive store.
7704 unsigned LastLegalType = 0;
7705 unsigned LastLegalVectorType = 0;
7706 bool NonZero = false;
7707 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
7708 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7709 SDValue StoredVal = St->getValue();
7711 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) {
7712 NonZero |= !C->isNullValue();
7713 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
7714 NonZero |= !C->getConstantFPValue()->isNullValue();
7720 // Find a legal type for the constant store.
7721 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
7722 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7723 if (TLI.isTypeLegal(StoreTy))
7724 LastLegalType = i+1;
7726 // Find a legal type for the vector store.
7727 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
7728 if (TLI.isTypeLegal(Ty))
7729 LastLegalVectorType = i + 1;
7732 // We only use vectors if the constant is known to be zero.
7734 LastLegalVectorType = 0;
7736 // Check if we found a legal integer type to store.
7737 if (LastLegalType == 0 && LastLegalVectorType == 0)
7740 bool UseVector = LastLegalVectorType > LastLegalType;
7741 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType;
7743 // Make sure we have something to merge.
7747 unsigned EarliestNodeUsed = 0;
7748 for (unsigned i=0; i < NumElem; ++i) {
7749 // Find a chain for the new wide-store operand. Notice that some
7750 // of the store nodes that we found may not be selected for inclusion
7751 // in the wide store. The chain we use needs to be the chain of the
7752 // earliest store node which is *used* and replaced by the wide store.
7753 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
7754 EarliestNodeUsed = i;
7757 // The earliest Node in the DAG.
7758 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
7759 DebugLoc DL = StoreNodes[0].MemNode->getDebugLoc();
7763 // Find a legal type for the vector store.
7764 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
7765 assert(TLI.isTypeLegal(Ty) && "Illegal vector store");
7766 StoredVal = DAG.getConstant(0, Ty);
7768 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
7769 APInt StoreInt(StoreBW, 0);
7771 // Construct a single integer constant which is made of the smaller
7773 bool IsLE = TLI.isLittleEndian();
7774 for (unsigned i = 0; i < NumElem ; ++i) {
7775 unsigned Idx = IsLE ?(NumElem - 1 - i) : i;
7776 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode);
7777 SDValue Val = St->getValue();
7778 StoreInt<<=ElementSizeBytes*8;
7779 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) {
7780 StoreInt|=C->getAPIntValue().zext(StoreBW);
7781 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
7782 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW);
7784 assert(false && "Invalid constant element type");
7788 // Create the new Load and Store operations.
7789 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7790 StoredVal = DAG.getConstant(StoreInt, StoreTy);
7793 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal,
7794 FirstInChain->getBasePtr(),
7795 FirstInChain->getPointerInfo(),
7797 FirstInChain->getAlignment());
7799 // Replace the first store with the new store
7800 CombineTo(EarliestOp, NewStore);
7801 // Erase all other stores.
7802 for (unsigned i = 0; i < NumElem ; ++i) {
7803 if (StoreNodes[i].MemNode == EarliestOp)
7805 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7806 // ReplaceAllUsesWith will replace all uses that existed when it was
7807 // called, but graph optimizations may cause new ones to appear. For
7808 // example, the case in pr14333 looks like
7810 // St's chain -> St -> another store -> X
7812 // And the only difference from St to the other store is the chain.
7813 // When we change it's chain to be St's chain they become identical,
7814 // get CSEed and the net result is that X is now a use of St.
7815 // Since we know that St is redundant, just iterate.
7816 while (!St->use_empty())
7817 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain());
7818 removeFromWorkList(St);
7825 // Below we handle the case of multiple consecutive stores that
7826 // come from multiple consecutive loads. We merge them into a single
7827 // wide load and a single wide store.
7829 // Look for load nodes which are used by the stored values.
7830 SmallVector<MemOpLink, 8> LoadNodes;
7832 // Find acceptable loads. Loads need to have the same chain (token factor),
7833 // must not be zext, volatile, indexed, and they must be consecutive.
7835 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
7836 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7837 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
7840 // Loads must only have one use.
7841 if (!Ld->hasNUsesOfValue(1, 0))
7844 // Check that the alignment is the same as the stores.
7845 if (Ld->getAlignment() != St->getAlignment())
7848 // The memory operands must not be volatile.
7849 if (Ld->isVolatile() || Ld->isIndexed())
7852 // We do not accept ext loads.
7853 if (Ld->getExtensionType() != ISD::NON_EXTLOAD)
7856 // The stored memory type must be the same.
7857 if (Ld->getMemoryVT() != MemVT)
7860 std::pair<SDValue, int64_t> LdPtr =
7861 GetPointerBaseAndOffset(Ld->getBasePtr());
7863 // If this is not the first ptr that we check.
7864 if (LdBasePtr.getNode()) {
7865 // The base ptr must be the same.
7866 if (LdPtr.first != LdBasePtr)
7869 // Check that all other base pointers are the same as this one.
7870 LdBasePtr = LdPtr.first;
7873 // We found a potential memory operand to merge.
7874 LoadNodes.push_back(MemOpLink(Ld, LdPtr.second, 0));
7877 if (LoadNodes.size() < 2)
7880 // Scan the memory operations on the chain and find the first non-consecutive
7881 // load memory address. These variables hold the index in the store node
7883 unsigned LastConsecutiveLoad = 0;
7884 // This variable refers to the size and not index in the array.
7885 unsigned LastLegalVectorType = 0;
7886 unsigned LastLegalIntegerType = 0;
7887 StartAddress = LoadNodes[0].OffsetFromBase;
7888 SDValue FirstChain = LoadNodes[0].MemNode->getChain();
7889 for (unsigned i = 1; i < LoadNodes.size(); ++i) {
7890 // All loads much share the same chain.
7891 if (LoadNodes[i].MemNode->getChain() != FirstChain)
7894 int64_t CurrAddress = LoadNodes[i].OffsetFromBase;
7895 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
7897 LastConsecutiveLoad = i;
7899 // Find a legal type for the vector store.
7900 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
7901 if (TLI.isTypeLegal(StoreTy))
7902 LastLegalVectorType = i + 1;
7904 // Find a legal type for the integer store.
7905 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
7906 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7907 if (TLI.isTypeLegal(StoreTy))
7908 LastLegalIntegerType = i + 1;
7911 // Only use vector types if the vector type is larger than the integer type.
7912 // If they are the same, use integers.
7913 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType;
7914 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType);
7916 // We add +1 here because the LastXXX variables refer to location while
7917 // the NumElem refers to array/index size.
7918 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1;
7919 NumElem = std::min(LastLegalType, NumElem);
7924 // The earliest Node in the DAG.
7925 unsigned EarliestNodeUsed = 0;
7926 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
7927 for (unsigned i=1; i<NumElem; ++i) {
7928 // Find a chain for the new wide-store operand. Notice that some
7929 // of the store nodes that we found may not be selected for inclusion
7930 // in the wide store. The chain we use needs to be the chain of the
7931 // earliest store node which is *used* and replaced by the wide store.
7932 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
7933 EarliestNodeUsed = i;
7936 // Find if it is better to use vectors or integers to load and store
7940 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
7942 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
7943 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7946 DebugLoc LoadDL = LoadNodes[0].MemNode->getDebugLoc();
7947 DebugLoc StoreDL = StoreNodes[0].MemNode->getDebugLoc();
7949 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode);
7950 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL,
7951 FirstLoad->getChain(),
7952 FirstLoad->getBasePtr(),
7953 FirstLoad->getPointerInfo(),
7954 false, false, false,
7955 FirstLoad->getAlignment());
7957 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad,
7958 FirstInChain->getBasePtr(),
7959 FirstInChain->getPointerInfo(), false, false,
7960 FirstInChain->getAlignment());
7962 // Replace one of the loads with the new load.
7963 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode);
7964 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1),
7965 SDValue(NewLoad.getNode(), 1));
7967 // Remove the rest of the load chains.
7968 for (unsigned i = 1; i < NumElem ; ++i) {
7969 // Replace all chain users of the old load nodes with the chain of the new
7971 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode);
7972 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain());
7975 // Replace the first store with the new store.
7976 CombineTo(EarliestOp, NewStore);
7977 // Erase all other stores.
7978 for (unsigned i = 0; i < NumElem ; ++i) {
7979 // Remove all Store nodes.
7980 if (StoreNodes[i].MemNode == EarliestOp)
7982 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7983 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
7984 removeFromWorkList(St);
7991 SDValue DAGCombiner::visitSTORE(SDNode *N) {
7992 StoreSDNode *ST = cast<StoreSDNode>(N);
7993 SDValue Chain = ST->getChain();
7994 SDValue Value = ST->getValue();
7995 SDValue Ptr = ST->getBasePtr();
7997 // If this is a store of a bit convert, store the input value if the
7998 // resultant store does not need a higher alignment than the original.
7999 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
8000 ST->isUnindexed()) {
8001 unsigned OrigAlign = ST->getAlignment();
8002 EVT SVT = Value.getOperand(0).getValueType();
8003 unsigned Align = TLI.getDataLayout()->
8004 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
8005 if (Align <= OrigAlign &&
8006 ((!LegalOperations && !ST->isVolatile()) ||
8007 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
8008 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
8009 Ptr, ST->getPointerInfo(), ST->isVolatile(),
8010 ST->isNonTemporal(), OrigAlign);
8013 // Turn 'store undef, Ptr' -> nothing.
8014 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
8017 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
8018 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
8019 // NOTE: If the original store is volatile, this transform must not increase
8020 // the number of stores. For example, on x86-32 an f64 can be stored in one
8021 // processor operation but an i64 (which is not legal) requires two. So the
8022 // transform should not be done in this case.
8023 if (Value.getOpcode() != ISD::TargetConstantFP) {
8025 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
8026 default: llvm_unreachable("Unknown FP type");
8027 case MVT::f16: // We don't do this for these yet.
8033 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
8034 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
8035 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
8036 bitcastToAPInt().getZExtValue(), MVT::i32);
8037 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
8038 Ptr, ST->getPointerInfo(), ST->isVolatile(),
8039 ST->isNonTemporal(), ST->getAlignment());
8043 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
8044 !ST->isVolatile()) ||
8045 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
8046 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
8047 getZExtValue(), MVT::i64);
8048 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
8049 Ptr, ST->getPointerInfo(), ST->isVolatile(),
8050 ST->isNonTemporal(), ST->getAlignment());
8053 if (!ST->isVolatile() &&
8054 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
8055 // Many FP stores are not made apparent until after legalize, e.g. for
8056 // argument passing. Since this is so common, custom legalize the
8057 // 64-bit integer store into two 32-bit stores.
8058 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
8059 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
8060 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
8061 if (TLI.isBigEndian()) std::swap(Lo, Hi);
8063 unsigned Alignment = ST->getAlignment();
8064 bool isVolatile = ST->isVolatile();
8065 bool isNonTemporal = ST->isNonTemporal();
8067 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
8068 Ptr, ST->getPointerInfo(),
8069 isVolatile, isNonTemporal,
8070 ST->getAlignment());
8071 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
8072 DAG.getConstant(4, Ptr.getValueType()));
8073 Alignment = MinAlign(Alignment, 4U);
8074 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
8075 Ptr, ST->getPointerInfo().getWithOffset(4),
8076 isVolatile, isNonTemporal,
8078 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
8087 // Try to infer better alignment information than the store already has.
8088 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
8089 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
8090 if (Align > ST->getAlignment())
8091 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
8092 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8093 ST->isVolatile(), ST->isNonTemporal(), Align);
8097 // Try transforming a pair floating point load / store ops to integer
8098 // load / store ops.
8099 SDValue NewST = TransformFPLoadStorePair(N);
8100 if (NewST.getNode())
8104 // Walk up chain skipping non-aliasing memory nodes.
8105 SDValue BetterChain = FindBetterChain(N, Chain);
8107 // If there is a better chain.
8108 if (Chain != BetterChain) {
8111 // Replace the chain to avoid dependency.
8112 if (ST->isTruncatingStore()) {
8113 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
8114 ST->getPointerInfo(),
8115 ST->getMemoryVT(), ST->isVolatile(),
8116 ST->isNonTemporal(), ST->getAlignment());
8118 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
8119 ST->getPointerInfo(),
8120 ST->isVolatile(), ST->isNonTemporal(),
8121 ST->getAlignment());
8124 // Create token to keep both nodes around.
8125 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
8126 MVT::Other, Chain, ReplStore);
8128 // Make sure the new and old chains are cleaned up.
8129 AddToWorkList(Token.getNode());
8131 // Don't add users to work list.
8132 return CombineTo(N, Token, false);
8136 // Try transforming N to an indexed store.
8137 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
8138 return SDValue(N, 0);
8140 // FIXME: is there such a thing as a truncating indexed store?
8141 if (ST->isTruncatingStore() && ST->isUnindexed() &&
8142 Value.getValueType().isInteger()) {
8143 // See if we can simplify the input to this truncstore with knowledge that
8144 // only the low bits are being used. For example:
8145 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
8147 GetDemandedBits(Value,
8148 APInt::getLowBitsSet(
8149 Value.getValueType().getScalarType().getSizeInBits(),
8150 ST->getMemoryVT().getScalarType().getSizeInBits()));
8151 AddToWorkList(Value.getNode());
8152 if (Shorter.getNode())
8153 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
8154 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8155 ST->isVolatile(), ST->isNonTemporal(),
8156 ST->getAlignment());
8158 // Otherwise, see if we can simplify the operation with
8159 // SimplifyDemandedBits, which only works if the value has a single use.
8160 if (SimplifyDemandedBits(Value,
8161 APInt::getLowBitsSet(
8162 Value.getValueType().getScalarType().getSizeInBits(),
8163 ST->getMemoryVT().getScalarType().getSizeInBits())))
8164 return SDValue(N, 0);
8167 // If this is a load followed by a store to the same location, then the store
8169 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
8170 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
8171 ST->isUnindexed() && !ST->isVolatile() &&
8172 // There can't be any side effects between the load and store, such as
8174 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
8175 // The store is dead, remove it.
8180 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
8181 // truncating store. We can do this even if this is already a truncstore.
8182 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
8183 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
8184 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
8185 ST->getMemoryVT())) {
8186 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
8187 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8188 ST->isVolatile(), ST->isNonTemporal(),
8189 ST->getAlignment());
8192 // Only perform this optimization before the types are legal, because we
8193 // don't want to perform this optimization on every DAGCombine invocation.
8195 bool EverChanged = false;
8198 // There can be multiple store sequences on the same chain.
8199 // Keep trying to merge store sequences until we are unable to do so
8200 // or until we merge the last store on the chain.
8201 bool Changed = MergeConsecutiveStores(ST);
8202 EverChanged |= Changed;
8203 if (!Changed) break;
8204 } while (ST->getOpcode() != ISD::DELETED_NODE);
8207 return SDValue(N, 0);
8210 return ReduceLoadOpStoreWidth(N);
8213 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
8214 SDValue InVec = N->getOperand(0);
8215 SDValue InVal = N->getOperand(1);
8216 SDValue EltNo = N->getOperand(2);
8217 DebugLoc dl = N->getDebugLoc();
8219 // If the inserted element is an UNDEF, just use the input vector.
8220 if (InVal.getOpcode() == ISD::UNDEF)
8223 EVT VT = InVec.getValueType();
8225 // If we can't generate a legal BUILD_VECTOR, exit
8226 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
8229 // Check that we know which element is being inserted
8230 if (!isa<ConstantSDNode>(EltNo))
8232 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8234 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
8235 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
8237 SmallVector<SDValue, 8> Ops;
8238 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
8239 Ops.append(InVec.getNode()->op_begin(),
8240 InVec.getNode()->op_end());
8241 } else if (InVec.getOpcode() == ISD::UNDEF) {
8242 unsigned NElts = VT.getVectorNumElements();
8243 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
8248 // Insert the element
8249 if (Elt < Ops.size()) {
8250 // All the operands of BUILD_VECTOR must have the same type;
8251 // we enforce that here.
8252 EVT OpVT = Ops[0].getValueType();
8253 if (InVal.getValueType() != OpVT)
8254 InVal = OpVT.bitsGT(InVal.getValueType()) ?
8255 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
8256 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
8260 // Return the new vector
8261 return DAG.getNode(ISD::BUILD_VECTOR, dl,
8262 VT, &Ops[0], Ops.size());
8265 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
8266 // (vextract (scalar_to_vector val, 0) -> val
8267 SDValue InVec = N->getOperand(0);
8268 EVT VT = InVec.getValueType();
8269 EVT NVT = N->getValueType(0);
8271 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
8272 // Check if the result type doesn't match the inserted element type. A
8273 // SCALAR_TO_VECTOR may truncate the inserted element and the
8274 // EXTRACT_VECTOR_ELT may widen the extracted vector.
8275 SDValue InOp = InVec.getOperand(0);
8276 if (InOp.getValueType() != NVT) {
8277 assert(InOp.getValueType().isInteger() && NVT.isInteger());
8278 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
8283 SDValue EltNo = N->getOperand(1);
8284 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
8286 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
8287 // We only perform this optimization before the op legalization phase because
8288 // we may introduce new vector instructions which are not backed by TD
8289 // patterns. For example on AVX, extracting elements from a wide vector
8290 // without using extract_subvector.
8291 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
8292 && ConstEltNo && !LegalOperations) {
8293 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8294 int NumElem = VT.getVectorNumElements();
8295 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
8296 // Find the new index to extract from.
8297 int OrigElt = SVOp->getMaskElt(Elt);
8299 // Extracting an undef index is undef.
8301 return DAG.getUNDEF(NVT);
8303 // Select the right vector half to extract from.
8304 if (OrigElt < NumElem) {
8305 InVec = InVec->getOperand(0);
8307 InVec = InVec->getOperand(1);
8311 EVT IndexTy = N->getOperand(1).getValueType();
8312 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT,
8313 InVec, DAG.getConstant(OrigElt, IndexTy));
8316 // Perform only after legalization to ensure build_vector / vector_shuffle
8317 // optimizations have already been done.
8318 if (!LegalOperations) return SDValue();
8320 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
8321 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
8322 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
8325 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8326 bool NewLoad = false;
8327 bool BCNumEltsChanged = false;
8328 EVT ExtVT = VT.getVectorElementType();
8331 // If the result of load has to be truncated, then it's not necessarily
8333 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
8336 if (InVec.getOpcode() == ISD::BITCAST) {
8337 // Don't duplicate a load with other uses.
8338 if (!InVec.hasOneUse())
8341 EVT BCVT = InVec.getOperand(0).getValueType();
8342 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
8344 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
8345 BCNumEltsChanged = true;
8346 InVec = InVec.getOperand(0);
8347 ExtVT = BCVT.getVectorElementType();
8351 LoadSDNode *LN0 = NULL;
8352 const ShuffleVectorSDNode *SVN = NULL;
8353 if (ISD::isNormalLoad(InVec.getNode())) {
8354 LN0 = cast<LoadSDNode>(InVec);
8355 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
8356 InVec.getOperand(0).getValueType() == ExtVT &&
8357 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
8358 // Don't duplicate a load with other uses.
8359 if (!InVec.hasOneUse())
8362 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
8363 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
8364 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
8366 // (load $addr+1*size)
8368 // Don't duplicate a load with other uses.
8369 if (!InVec.hasOneUse())
8372 // If the bit convert changed the number of elements, it is unsafe
8373 // to examine the mask.
8374 if (BCNumEltsChanged)
8377 // Select the input vector, guarding against out of range extract vector.
8378 unsigned NumElems = VT.getVectorNumElements();
8379 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
8380 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
8382 if (InVec.getOpcode() == ISD::BITCAST) {
8383 // Don't duplicate a load with other uses.
8384 if (!InVec.hasOneUse())
8387 InVec = InVec.getOperand(0);
8389 if (ISD::isNormalLoad(InVec.getNode())) {
8390 LN0 = cast<LoadSDNode>(InVec);
8391 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
8395 // Make sure we found a non-volatile load and the extractelement is
8397 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
8400 // If Idx was -1 above, Elt is going to be -1, so just return undef.
8402 return DAG.getUNDEF(LVT);
8404 unsigned Align = LN0->getAlignment();
8406 // Check the resultant load doesn't need a higher alignment than the
8410 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
8412 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
8418 SDValue NewPtr = LN0->getBasePtr();
8419 unsigned PtrOff = 0;
8422 PtrOff = LVT.getSizeInBits() * Elt / 8;
8423 EVT PtrType = NewPtr.getValueType();
8424 if (TLI.isBigEndian())
8425 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
8426 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
8427 DAG.getConstant(PtrOff, PtrType));
8430 // The replacement we need to do here is a little tricky: we need to
8431 // replace an extractelement of a load with a load.
8432 // Use ReplaceAllUsesOfValuesWith to do the replacement.
8433 // Note that this replacement assumes that the extractvalue is the only
8434 // use of the load; that's okay because we don't want to perform this
8435 // transformation in other cases anyway.
8438 if (NVT.bitsGT(LVT)) {
8439 // If the result type of vextract is wider than the load, then issue an
8440 // extending load instead.
8441 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT)
8442 ? ISD::ZEXTLOAD : ISD::EXTLOAD;
8443 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(),
8444 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff),
8445 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align);
8446 Chain = Load.getValue(1);
8448 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
8449 LN0->getPointerInfo().getWithOffset(PtrOff),
8450 LN0->isVolatile(), LN0->isNonTemporal(),
8451 LN0->isInvariant(), Align);
8452 Chain = Load.getValue(1);
8453 if (NVT.bitsLT(LVT))
8454 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load);
8456 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load);
8458 WorkListRemover DeadNodes(*this);
8459 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) };
8460 SDValue To[] = { Load, Chain };
8461 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
8462 // Since we're explcitly calling ReplaceAllUses, add the new node to the
8463 // worklist explicitly as well.
8464 AddToWorkList(Load.getNode());
8465 AddUsersToWorkList(Load.getNode()); // Add users too
8466 // Make sure to revisit this node to clean it up; it will usually be dead.
8468 return SDValue(N, 0);
8474 // Simplify (build_vec (ext )) to (bitcast (build_vec ))
8475 SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) {
8476 // We perform this optimization post type-legalization because
8477 // the type-legalizer often scalarizes integer-promoted vectors.
8478 // Performing this optimization before may create bit-casts which
8479 // will be type-legalized to complex code sequences.
8480 // We perform this optimization only before the operation legalizer because we
8481 // may introduce illegal operations.
8482 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes)
8485 unsigned NumInScalars = N->getNumOperands();
8486 DebugLoc dl = N->getDebugLoc();
8487 EVT VT = N->getValueType(0);
8489 // Check to see if this is a BUILD_VECTOR of a bunch of values
8490 // which come from any_extend or zero_extend nodes. If so, we can create
8491 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
8492 // optimizations. We do not handle sign-extend because we can't fill the sign
8494 EVT SourceType = MVT::Other;
8495 bool AllAnyExt = true;
8497 for (unsigned i = 0; i != NumInScalars; ++i) {
8498 SDValue In = N->getOperand(i);
8499 // Ignore undef inputs.
8500 if (In.getOpcode() == ISD::UNDEF) continue;
8502 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
8503 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
8505 // Abort if the element is not an extension.
8506 if (!ZeroExt && !AnyExt) {
8507 SourceType = MVT::Other;
8511 // The input is a ZeroExt or AnyExt. Check the original type.
8512 EVT InTy = In.getOperand(0).getValueType();
8514 // Check that all of the widened source types are the same.
8515 if (SourceType == MVT::Other)
8518 else if (InTy != SourceType) {
8519 // Multiple income types. Abort.
8520 SourceType = MVT::Other;
8524 // Check if all of the extends are ANY_EXTENDs.
8525 AllAnyExt &= AnyExt;
8528 // In order to have valid types, all of the inputs must be extended from the
8529 // same source type and all of the inputs must be any or zero extend.
8530 // Scalar sizes must be a power of two.
8531 EVT OutScalarTy = VT.getScalarType();
8532 bool ValidTypes = SourceType != MVT::Other &&
8533 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
8534 isPowerOf2_32(SourceType.getSizeInBits());
8536 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
8537 // turn into a single shuffle instruction.
8541 bool isLE = TLI.isLittleEndian();
8542 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
8543 assert(ElemRatio > 1 && "Invalid element size ratio");
8544 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
8545 DAG.getConstant(0, SourceType);
8547 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements();
8548 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
8550 // Populate the new build_vector
8551 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
8552 SDValue Cast = N->getOperand(i);
8553 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
8554 Cast.getOpcode() == ISD::ZERO_EXTEND ||
8555 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
8557 if (Cast.getOpcode() == ISD::UNDEF)
8558 In = DAG.getUNDEF(SourceType);
8560 In = Cast->getOperand(0);
8561 unsigned Index = isLE ? (i * ElemRatio) :
8562 (i * ElemRatio + (ElemRatio - 1));
8564 assert(Index < Ops.size() && "Invalid index");
8568 // The type of the new BUILD_VECTOR node.
8569 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
8570 assert(VecVT.getSizeInBits() == VT.getSizeInBits() &&
8571 "Invalid vector size");
8572 // Check if the new vector type is legal.
8573 if (!isTypeLegal(VecVT)) return SDValue();
8575 // Make the new BUILD_VECTOR.
8576 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], Ops.size());
8578 // The new BUILD_VECTOR node has the potential to be further optimized.
8579 AddToWorkList(BV.getNode());
8580 // Bitcast to the desired type.
8581 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8584 SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
8585 EVT VT = N->getValueType(0);
8587 unsigned NumInScalars = N->getNumOperands();
8588 DebugLoc dl = N->getDebugLoc();
8590 EVT SrcVT = MVT::Other;
8591 unsigned Opcode = ISD::DELETED_NODE;
8592 unsigned NumDefs = 0;
8594 for (unsigned i = 0; i != NumInScalars; ++i) {
8595 SDValue In = N->getOperand(i);
8596 unsigned Opc = In.getOpcode();
8598 if (Opc == ISD::UNDEF)
8601 // If all scalar values are floats and converted from integers.
8602 if (Opcode == ISD::DELETED_NODE &&
8603 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
8605 // If not supported by target, bail out.
8606 if (TLI.getOperationAction(Opcode, VT) != TargetLowering::Legal &&
8607 TLI.getOperationAction(Opcode, VT) != TargetLowering::Custom)
8613 EVT InVT = In.getOperand(0).getValueType();
8615 // If all scalar values are typed differently, bail out. It's chosen to
8616 // simplify BUILD_VECTOR of integer types.
8617 if (SrcVT == MVT::Other)
8624 // If the vector has just one element defined, it's not worth to fold it into
8625 // a vectorized one.
8629 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP)
8630 && "Should only handle conversion from integer to float.");
8631 assert(SrcVT != MVT::Other && "Cannot determine source type!");
8633 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
8634 SmallVector<SDValue, 8> Opnds;
8635 for (unsigned i = 0; i != NumInScalars; ++i) {
8636 SDValue In = N->getOperand(i);
8638 if (In.getOpcode() == ISD::UNDEF)
8639 Opnds.push_back(DAG.getUNDEF(SrcVT));
8641 Opnds.push_back(In.getOperand(0));
8643 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT,
8644 &Opnds[0], Opnds.size());
8645 AddToWorkList(BV.getNode());
8647 return DAG.getNode(Opcode, dl, VT, BV);
8650 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
8651 unsigned NumInScalars = N->getNumOperands();
8652 DebugLoc dl = N->getDebugLoc();
8653 EVT VT = N->getValueType(0);
8655 // A vector built entirely of undefs is undef.
8656 if (ISD::allOperandsUndef(N))
8657 return DAG.getUNDEF(VT);
8659 SDValue V = reduceBuildVecExtToExtBuildVec(N);
8663 V = reduceBuildVecConvertToConvertBuildVec(N);
8667 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
8668 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
8669 // at most two distinct vectors, turn this into a shuffle node.
8671 // May only combine to shuffle after legalize if shuffle is legal.
8672 if (LegalOperations &&
8673 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))
8676 SDValue VecIn1, VecIn2;
8677 for (unsigned i = 0; i != NumInScalars; ++i) {
8678 // Ignore undef inputs.
8679 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
8681 // If this input is something other than a EXTRACT_VECTOR_ELT with a
8682 // constant index, bail out.
8683 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8684 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
8685 VecIn1 = VecIn2 = SDValue(0, 0);
8689 // We allow up to two distinct input vectors.
8690 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
8691 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
8694 if (VecIn1.getNode() == 0) {
8695 VecIn1 = ExtractedFromVec;
8696 } else if (VecIn2.getNode() == 0) {
8697 VecIn2 = ExtractedFromVec;
8700 VecIn1 = VecIn2 = SDValue(0, 0);
8705 // If everything is good, we can make a shuffle operation.
8706 if (VecIn1.getNode()) {
8707 SmallVector<int, 8> Mask;
8708 for (unsigned i = 0; i != NumInScalars; ++i) {
8709 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
8714 // If extracting from the first vector, just use the index directly.
8715 SDValue Extract = N->getOperand(i);
8716 SDValue ExtVal = Extract.getOperand(1);
8717 if (Extract.getOperand(0) == VecIn1) {
8718 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
8719 if (ExtIndex > VT.getVectorNumElements())
8722 Mask.push_back(ExtIndex);
8726 // Otherwise, use InIdx + VecSize
8727 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
8728 Mask.push_back(Idx+NumInScalars);
8731 // We can't generate a shuffle node with mismatched input and output types.
8732 // Attempt to transform a single input vector to the correct type.
8733 if ((VT != VecIn1.getValueType())) {
8734 // We don't support shuffeling between TWO values of different types.
8735 if (VecIn2.getNode() != 0)
8738 // We only support widening of vectors which are half the size of the
8739 // output registers. For example XMM->YMM widening on X86 with AVX.
8740 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
8743 // If the input vector type has a different base type to the output
8744 // vector type, bail out.
8745 if (VecIn1.getValueType().getVectorElementType() !=
8746 VT.getVectorElementType())
8749 // Widen the input vector by adding undef values.
8750 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8751 VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
8754 // If VecIn2 is unused then change it to undef.
8755 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
8757 // Check that we were able to transform all incoming values to the same
8759 if (VecIn2.getValueType() != VecIn1.getValueType() ||
8760 VecIn1.getValueType() != VT)
8763 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
8764 if (!isTypeLegal(VT))
8767 // Return the new VECTOR_SHUFFLE node.
8771 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]);
8777 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
8778 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
8779 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
8780 // inputs come from at most two distinct vectors, turn this into a shuffle
8783 // If we only have one input vector, we don't need to do any concatenation.
8784 if (N->getNumOperands() == 1)
8785 return N->getOperand(0);
8787 // Check if all of the operands are undefs.
8788 if (ISD::allOperandsUndef(N))
8789 return DAG.getUNDEF(N->getValueType(0));
8794 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
8795 EVT NVT = N->getValueType(0);
8796 SDValue V = N->getOperand(0);
8798 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
8799 // Handle only simple case where vector being inserted and vector
8800 // being extracted are of same type, and are half size of larger vectors.
8801 EVT BigVT = V->getOperand(0).getValueType();
8802 EVT SmallVT = V->getOperand(1).getValueType();
8803 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
8806 // Only handle cases where both indexes are constants with the same type.
8807 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
8808 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
8810 if (InsIdx && ExtIdx &&
8811 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
8812 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
8814 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
8816 // indices are equal => V1
8817 // otherwise => (extract_subvec V1, ExtIdx)
8818 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue())
8819 return V->getOperand(1);
8820 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT,
8821 V->getOperand(0), N->getOperand(1));
8825 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
8827 // (extract_subvec (concat V1, V2, ...), i)
8830 // Only operand 0 is checked as 'concat' assumes all inputs of the same type.
8831 if (V->getOperand(0).getValueType() != NVT)
8833 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8834 unsigned NumElems = NVT.getVectorNumElements();
8835 assert((Idx % NumElems) == 0 &&
8836 "IDX in concat is not a multiple of the result vector length.");
8837 return V->getOperand(Idx / NumElems);
8843 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
8844 EVT VT = N->getValueType(0);
8845 unsigned NumElts = VT.getVectorNumElements();
8847 SDValue N0 = N->getOperand(0);
8848 SDValue N1 = N->getOperand(1);
8850 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
8852 // Canonicalize shuffle undef, undef -> undef
8853 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
8854 return DAG.getUNDEF(VT);
8856 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8858 // Canonicalize shuffle v, v -> v, undef
8860 SmallVector<int, 8> NewMask;
8861 for (unsigned i = 0; i != NumElts; ++i) {
8862 int Idx = SVN->getMaskElt(i);
8863 if (Idx >= (int)NumElts) Idx -= NumElts;
8864 NewMask.push_back(Idx);
8866 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT),
8870 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
8871 if (N0.getOpcode() == ISD::UNDEF) {
8872 SmallVector<int, 8> NewMask;
8873 for (unsigned i = 0; i != NumElts; ++i) {
8874 int Idx = SVN->getMaskElt(i);
8876 if (Idx < (int)NumElts)
8881 NewMask.push_back(Idx);
8883 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT),
8887 // Remove references to rhs if it is undef
8888 if (N1.getOpcode() == ISD::UNDEF) {
8889 bool Changed = false;
8890 SmallVector<int, 8> NewMask;
8891 for (unsigned i = 0; i != NumElts; ++i) {
8892 int Idx = SVN->getMaskElt(i);
8893 if (Idx >= (int)NumElts) {
8897 NewMask.push_back(Idx);
8900 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]);
8903 // If it is a splat, check if the argument vector is another splat or a
8904 // build_vector with all scalar elements the same.
8905 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
8906 SDNode *V = N0.getNode();
8908 // If this is a bit convert that changes the element type of the vector but
8909 // not the number of vector elements, look through it. Be careful not to
8910 // look though conversions that change things like v4f32 to v2f64.
8911 if (V->getOpcode() == ISD::BITCAST) {
8912 SDValue ConvInput = V->getOperand(0);
8913 if (ConvInput.getValueType().isVector() &&
8914 ConvInput.getValueType().getVectorNumElements() == NumElts)
8915 V = ConvInput.getNode();
8918 if (V->getOpcode() == ISD::BUILD_VECTOR) {
8919 assert(V->getNumOperands() == NumElts &&
8920 "BUILD_VECTOR has wrong number of operands");
8922 bool AllSame = true;
8923 for (unsigned i = 0; i != NumElts; ++i) {
8924 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
8925 Base = V->getOperand(i);
8929 // Splat of <u, u, u, u>, return <u, u, u, u>
8930 if (!Base.getNode())
8932 for (unsigned i = 0; i != NumElts; ++i) {
8933 if (V->getOperand(i) != Base) {
8938 // Splat of <x, x, x, x>, return <x, x, x, x>
8944 // If this shuffle node is simply a swizzle of another shuffle node,
8945 // and it reverses the swizzle of the previous shuffle then we can
8946 // optimize shuffle(shuffle(x, undef), undef) -> x.
8947 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
8948 N1.getOpcode() == ISD::UNDEF) {
8950 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
8952 // Shuffle nodes can only reverse shuffles with a single non-undef value.
8953 if (N0.getOperand(1).getOpcode() != ISD::UNDEF)
8956 // The incoming shuffle must be of the same type as the result of the
8958 assert(OtherSV->getOperand(0).getValueType() == VT &&
8959 "Shuffle types don't match");
8961 for (unsigned i = 0; i != NumElts; ++i) {
8962 int Idx = SVN->getMaskElt(i);
8963 assert(Idx < (int)NumElts && "Index references undef operand");
8964 // Next, this index comes from the first value, which is the incoming
8965 // shuffle. Adopt the incoming index.
8967 Idx = OtherSV->getMaskElt(Idx);
8969 // The combined shuffle must map each index to itself.
8970 if (Idx >= 0 && (unsigned)Idx != i)
8974 return OtherSV->getOperand(0);
8980 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
8981 if (!TLI.getShouldFoldAtomicFences())
8984 SDValue atomic = N->getOperand(0);
8985 switch (atomic.getOpcode()) {
8986 case ISD::ATOMIC_CMP_SWAP:
8987 case ISD::ATOMIC_SWAP:
8988 case ISD::ATOMIC_LOAD_ADD:
8989 case ISD::ATOMIC_LOAD_SUB:
8990 case ISD::ATOMIC_LOAD_AND:
8991 case ISD::ATOMIC_LOAD_OR:
8992 case ISD::ATOMIC_LOAD_XOR:
8993 case ISD::ATOMIC_LOAD_NAND:
8994 case ISD::ATOMIC_LOAD_MIN:
8995 case ISD::ATOMIC_LOAD_MAX:
8996 case ISD::ATOMIC_LOAD_UMIN:
8997 case ISD::ATOMIC_LOAD_UMAX:
9003 SDValue fence = atomic.getOperand(0);
9004 if (fence.getOpcode() != ISD::MEMBARRIER)
9007 switch (atomic.getOpcode()) {
9008 case ISD::ATOMIC_CMP_SWAP:
9009 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
9010 fence.getOperand(0),
9011 atomic.getOperand(1), atomic.getOperand(2),
9012 atomic.getOperand(3)), atomic.getResNo());
9013 case ISD::ATOMIC_SWAP:
9014 case ISD::ATOMIC_LOAD_ADD:
9015 case ISD::ATOMIC_LOAD_SUB:
9016 case ISD::ATOMIC_LOAD_AND:
9017 case ISD::ATOMIC_LOAD_OR:
9018 case ISD::ATOMIC_LOAD_XOR:
9019 case ISD::ATOMIC_LOAD_NAND:
9020 case ISD::ATOMIC_LOAD_MIN:
9021 case ISD::ATOMIC_LOAD_MAX:
9022 case ISD::ATOMIC_LOAD_UMIN:
9023 case ISD::ATOMIC_LOAD_UMAX:
9024 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
9025 fence.getOperand(0),
9026 atomic.getOperand(1), atomic.getOperand(2)),
9033 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
9034 /// an AND to a vector_shuffle with the destination vector and a zero vector.
9035 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
9036 /// vector_shuffle V, Zero, <0, 4, 2, 4>
9037 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
9038 EVT VT = N->getValueType(0);
9039 DebugLoc dl = N->getDebugLoc();
9040 SDValue LHS = N->getOperand(0);
9041 SDValue RHS = N->getOperand(1);
9042 if (N->getOpcode() == ISD::AND) {
9043 if (RHS.getOpcode() == ISD::BITCAST)
9044 RHS = RHS.getOperand(0);
9045 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
9046 SmallVector<int, 8> Indices;
9047 unsigned NumElts = RHS.getNumOperands();
9048 for (unsigned i = 0; i != NumElts; ++i) {
9049 SDValue Elt = RHS.getOperand(i);
9050 if (!isa<ConstantSDNode>(Elt))
9053 if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
9054 Indices.push_back(i);
9055 else if (cast<ConstantSDNode>(Elt)->isNullValue())
9056 Indices.push_back(NumElts);
9061 // Let's see if the target supports this vector_shuffle.
9062 EVT RVT = RHS.getValueType();
9063 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
9066 // Return the new VECTOR_SHUFFLE node.
9067 EVT EltVT = RVT.getVectorElementType();
9068 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
9069 DAG.getConstant(0, EltVT));
9070 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
9071 RVT, &ZeroOps[0], ZeroOps.size());
9072 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
9073 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
9074 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
9081 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
9082 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
9083 // After legalize, the target may be depending on adds and other
9084 // binary ops to provide legal ways to construct constants or other
9085 // things. Simplifying them may result in a loss of legality.
9086 if (LegalOperations) return SDValue();
9088 assert(N->getValueType(0).isVector() &&
9089 "SimplifyVBinOp only works on vectors!");
9091 SDValue LHS = N->getOperand(0);
9092 SDValue RHS = N->getOperand(1);
9093 SDValue Shuffle = XformToShuffleWithZero(N);
9094 if (Shuffle.getNode()) return Shuffle;
9096 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
9098 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
9099 RHS.getOpcode() == ISD::BUILD_VECTOR) {
9100 SmallVector<SDValue, 8> Ops;
9101 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
9102 SDValue LHSOp = LHS.getOperand(i);
9103 SDValue RHSOp = RHS.getOperand(i);
9104 // If these two elements can't be folded, bail out.
9105 if ((LHSOp.getOpcode() != ISD::UNDEF &&
9106 LHSOp.getOpcode() != ISD::Constant &&
9107 LHSOp.getOpcode() != ISD::ConstantFP) ||
9108 (RHSOp.getOpcode() != ISD::UNDEF &&
9109 RHSOp.getOpcode() != ISD::Constant &&
9110 RHSOp.getOpcode() != ISD::ConstantFP))
9113 // Can't fold divide by zero.
9114 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
9115 N->getOpcode() == ISD::FDIV) {
9116 if ((RHSOp.getOpcode() == ISD::Constant &&
9117 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
9118 (RHSOp.getOpcode() == ISD::ConstantFP &&
9119 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
9123 EVT VT = LHSOp.getValueType();
9124 EVT RVT = RHSOp.getValueType();
9126 // Integer BUILD_VECTOR operands may have types larger than the element
9127 // size (e.g., when the element type is not legal). Prior to type
9128 // legalization, the types may not match between the two BUILD_VECTORS.
9129 // Truncate one of the operands to make them match.
9130 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
9131 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp);
9133 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp);
9137 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
9139 if (FoldOp.getOpcode() != ISD::UNDEF &&
9140 FoldOp.getOpcode() != ISD::Constant &&
9141 FoldOp.getOpcode() != ISD::ConstantFP)
9143 Ops.push_back(FoldOp);
9144 AddToWorkList(FoldOp.getNode());
9147 if (Ops.size() == LHS.getNumOperands())
9148 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
9149 LHS.getValueType(), &Ops[0], Ops.size());
9155 /// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG.
9156 SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) {
9157 // After legalize, the target may be depending on adds and other
9158 // binary ops to provide legal ways to construct constants or other
9159 // things. Simplifying them may result in a loss of legality.
9160 if (LegalOperations) return SDValue();
9162 assert(N->getValueType(0).isVector() &&
9163 "SimplifyVUnaryOp only works on vectors!");
9165 SDValue N0 = N->getOperand(0);
9167 if (N0.getOpcode() != ISD::BUILD_VECTOR)
9170 // Operand is a BUILD_VECTOR node, see if we can constant fold it.
9171 SmallVector<SDValue, 8> Ops;
9172 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
9173 SDValue Op = N0.getOperand(i);
9174 if (Op.getOpcode() != ISD::UNDEF &&
9175 Op.getOpcode() != ISD::ConstantFP)
9177 EVT EltVT = Op.getValueType();
9178 SDValue FoldOp = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), EltVT, Op);
9179 if (FoldOp.getOpcode() != ISD::UNDEF &&
9180 FoldOp.getOpcode() != ISD::ConstantFP)
9182 Ops.push_back(FoldOp);
9183 AddToWorkList(FoldOp.getNode());
9186 if (Ops.size() != N0.getNumOperands())
9189 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
9190 N0.getValueType(), &Ops[0], Ops.size());
9193 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
9194 SDValue N1, SDValue N2){
9195 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
9197 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
9198 cast<CondCodeSDNode>(N0.getOperand(2))->get());
9200 // If we got a simplified select_cc node back from SimplifySelectCC, then
9201 // break it down into a new SETCC node, and a new SELECT node, and then return
9202 // the SELECT node, since we were called with a SELECT node.
9203 if (SCC.getNode()) {
9204 // Check to see if we got a select_cc back (to turn into setcc/select).
9205 // Otherwise, just return whatever node we got back, like fabs.
9206 if (SCC.getOpcode() == ISD::SELECT_CC) {
9207 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
9209 SCC.getOperand(0), SCC.getOperand(1),
9211 AddToWorkList(SETCC.getNode());
9212 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
9213 SCC.getOperand(2), SCC.getOperand(3), SETCC);
9221 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
9222 /// are the two values being selected between, see if we can simplify the
9223 /// select. Callers of this should assume that TheSelect is deleted if this
9224 /// returns true. As such, they should return the appropriate thing (e.g. the
9225 /// node) back to the top-level of the DAG combiner loop to avoid it being
9227 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
9230 // Cannot simplify select with vector condition
9231 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
9233 // If this is a select from two identical things, try to pull the operation
9234 // through the select.
9235 if (LHS.getOpcode() != RHS.getOpcode() ||
9236 !LHS.hasOneUse() || !RHS.hasOneUse())
9239 // If this is a load and the token chain is identical, replace the select
9240 // of two loads with a load through a select of the address to load from.
9241 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
9242 // constants have been dropped into the constant pool.
9243 if (LHS.getOpcode() == ISD::LOAD) {
9244 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
9245 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
9247 // Token chains must be identical.
9248 if (LHS.getOperand(0) != RHS.getOperand(0) ||
9249 // Do not let this transformation reduce the number of volatile loads.
9250 LLD->isVolatile() || RLD->isVolatile() ||
9251 // If this is an EXTLOAD, the VT's must match.
9252 LLD->getMemoryVT() != RLD->getMemoryVT() ||
9253 // If this is an EXTLOAD, the kind of extension must match.
9254 (LLD->getExtensionType() != RLD->getExtensionType() &&
9255 // The only exception is if one of the extensions is anyext.
9256 LLD->getExtensionType() != ISD::EXTLOAD &&
9257 RLD->getExtensionType() != ISD::EXTLOAD) ||
9258 // FIXME: this discards src value information. This is
9259 // over-conservative. It would be beneficial to be able to remember
9260 // both potential memory locations. Since we are discarding
9261 // src value info, don't do the transformation if the memory
9262 // locations are not in the default address space.
9263 LLD->getPointerInfo().getAddrSpace() != 0 ||
9264 RLD->getPointerInfo().getAddrSpace() != 0)
9267 // Check that the select condition doesn't reach either load. If so,
9268 // folding this will induce a cycle into the DAG. If not, this is safe to
9269 // xform, so create a select of the addresses.
9271 if (TheSelect->getOpcode() == ISD::SELECT) {
9272 SDNode *CondNode = TheSelect->getOperand(0).getNode();
9273 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
9274 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
9276 // The loads must not depend on one another.
9277 if (LLD->isPredecessorOf(RLD) ||
9278 RLD->isPredecessorOf(LLD))
9280 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
9281 LLD->getBasePtr().getValueType(),
9282 TheSelect->getOperand(0), LLD->getBasePtr(),
9284 } else { // Otherwise SELECT_CC
9285 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
9286 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
9288 if ((LLD->hasAnyUseOfValue(1) &&
9289 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
9290 (RLD->hasAnyUseOfValue(1) &&
9291 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
9294 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
9295 LLD->getBasePtr().getValueType(),
9296 TheSelect->getOperand(0),
9297 TheSelect->getOperand(1),
9298 LLD->getBasePtr(), RLD->getBasePtr(),
9299 TheSelect->getOperand(4));
9303 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
9304 Load = DAG.getLoad(TheSelect->getValueType(0),
9305 TheSelect->getDebugLoc(),
9306 // FIXME: Discards pointer info.
9307 LLD->getChain(), Addr, MachinePointerInfo(),
9308 LLD->isVolatile(), LLD->isNonTemporal(),
9309 LLD->isInvariant(), LLD->getAlignment());
9311 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
9312 RLD->getExtensionType() : LLD->getExtensionType(),
9313 TheSelect->getDebugLoc(),
9314 TheSelect->getValueType(0),
9315 // FIXME: Discards pointer info.
9316 LLD->getChain(), Addr, MachinePointerInfo(),
9317 LLD->getMemoryVT(), LLD->isVolatile(),
9318 LLD->isNonTemporal(), LLD->getAlignment());
9321 // Users of the select now use the result of the load.
9322 CombineTo(TheSelect, Load);
9324 // Users of the old loads now use the new load's chain. We know the
9325 // old-load value is dead now.
9326 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
9327 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
9334 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
9335 /// where 'cond' is the comparison specified by CC.
9336 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
9337 SDValue N2, SDValue N3,
9338 ISD::CondCode CC, bool NotExtCompare) {
9339 // (x ? y : y) -> y.
9340 if (N2 == N3) return N2;
9342 EVT VT = N2.getValueType();
9343 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
9344 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
9345 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
9347 // Determine if the condition we're dealing with is constant
9348 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
9349 N0, N1, CC, DL, false);
9350 if (SCC.getNode()) AddToWorkList(SCC.getNode());
9351 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
9353 // fold select_cc true, x, y -> x
9354 if (SCCC && !SCCC->isNullValue())
9356 // fold select_cc false, x, y -> y
9357 if (SCCC && SCCC->isNullValue())
9360 // Check to see if we can simplify the select into an fabs node
9361 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
9362 // Allow either -0.0 or 0.0
9363 if (CFP->getValueAPF().isZero()) {
9364 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
9365 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
9366 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
9367 N2 == N3.getOperand(0))
9368 return DAG.getNode(ISD::FABS, DL, VT, N0);
9370 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
9371 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
9372 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
9373 N2.getOperand(0) == N3)
9374 return DAG.getNode(ISD::FABS, DL, VT, N3);
9378 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
9379 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
9380 // in it. This is a win when the constant is not otherwise available because
9381 // it replaces two constant pool loads with one. We only do this if the FP
9382 // type is known to be legal, because if it isn't, then we are before legalize
9383 // types an we want the other legalization to happen first (e.g. to avoid
9384 // messing with soft float) and if the ConstantFP is not legal, because if
9385 // it is legal, we may not need to store the FP constant in a constant pool.
9386 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
9387 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
9388 if (TLI.isTypeLegal(N2.getValueType()) &&
9389 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
9390 TargetLowering::Legal) &&
9391 // If both constants have multiple uses, then we won't need to do an
9392 // extra load, they are likely around in registers for other users.
9393 (TV->hasOneUse() || FV->hasOneUse())) {
9394 Constant *Elts[] = {
9395 const_cast<ConstantFP*>(FV->getConstantFPValue()),
9396 const_cast<ConstantFP*>(TV->getConstantFPValue())
9398 Type *FPTy = Elts[0]->getType();
9399 const DataLayout &TD = *TLI.getDataLayout();
9401 // Create a ConstantArray of the two constants.
9402 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
9403 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
9404 TD.getPrefTypeAlignment(FPTy));
9405 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9407 // Get the offsets to the 0 and 1 element of the array so that we can
9408 // select between them.
9409 SDValue Zero = DAG.getIntPtrConstant(0);
9410 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
9411 SDValue One = DAG.getIntPtrConstant(EltSize);
9413 SDValue Cond = DAG.getSetCC(DL,
9414 TLI.getSetCCResultType(N0.getValueType()),
9416 AddToWorkList(Cond.getNode());
9417 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
9419 AddToWorkList(CstOffset.getNode());
9420 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
9422 AddToWorkList(CPIdx.getNode());
9423 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
9424 MachinePointerInfo::getConstantPool(), false,
9425 false, false, Alignment);
9430 // Check to see if we can perform the "gzip trick", transforming
9431 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
9432 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
9433 (N1C->isNullValue() || // (a < 0) ? b : 0
9434 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
9435 EVT XType = N0.getValueType();
9436 EVT AType = N2.getValueType();
9437 if (XType.bitsGE(AType)) {
9438 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
9439 // single-bit constant.
9440 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
9441 unsigned ShCtV = N2C->getAPIntValue().logBase2();
9442 ShCtV = XType.getSizeInBits()-ShCtV-1;
9443 SDValue ShCt = DAG.getConstant(ShCtV,
9444 getShiftAmountTy(N0.getValueType()));
9445 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
9447 AddToWorkList(Shift.getNode());
9449 if (XType.bitsGT(AType)) {
9450 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
9451 AddToWorkList(Shift.getNode());
9454 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
9457 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
9459 DAG.getConstant(XType.getSizeInBits()-1,
9460 getShiftAmountTy(N0.getValueType())));
9461 AddToWorkList(Shift.getNode());
9463 if (XType.bitsGT(AType)) {
9464 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
9465 AddToWorkList(Shift.getNode());
9468 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
9472 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
9473 // where y is has a single bit set.
9474 // A plaintext description would be, we can turn the SELECT_CC into an AND
9475 // when the condition can be materialized as an all-ones register. Any
9476 // single bit-test can be materialized as an all-ones register with
9477 // shift-left and shift-right-arith.
9478 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
9479 N0->getValueType(0) == VT &&
9480 N1C && N1C->isNullValue() &&
9481 N2C && N2C->isNullValue()) {
9482 SDValue AndLHS = N0->getOperand(0);
9483 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
9484 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
9485 // Shift the tested bit over the sign bit.
9486 APInt AndMask = ConstAndRHS->getAPIntValue();
9488 DAG.getConstant(AndMask.countLeadingZeros(),
9489 getShiftAmountTy(AndLHS.getValueType()));
9490 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
9492 // Now arithmetic right shift it all the way over, so the result is either
9493 // all-ones, or zero.
9495 DAG.getConstant(AndMask.getBitWidth()-1,
9496 getShiftAmountTy(Shl.getValueType()));
9497 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
9499 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
9503 // fold select C, 16, 0 -> shl C, 4
9504 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
9505 TLI.getBooleanContents(N0.getValueType().isVector()) ==
9506 TargetLowering::ZeroOrOneBooleanContent) {
9508 // If the caller doesn't want us to simplify this into a zext of a compare,
9510 if (NotExtCompare && N2C->getAPIntValue() == 1)
9513 // Get a SetCC of the condition
9514 // NOTE: Don't create a SETCC if it's not legal on this target.
9515 if (!LegalOperations ||
9516 TLI.isOperationLegal(ISD::SETCC,
9517 LegalTypes ? TLI.getSetCCResultType(N0.getValueType()) : MVT::i1)) {
9519 // cast from setcc result type to select result type
9521 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
9523 if (N2.getValueType().bitsLT(SCC.getValueType()))
9524 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(),
9527 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
9528 N2.getValueType(), SCC);
9530 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
9531 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
9532 N2.getValueType(), SCC);
9535 AddToWorkList(SCC.getNode());
9536 AddToWorkList(Temp.getNode());
9538 if (N2C->getAPIntValue() == 1)
9541 // shl setcc result by log2 n2c
9542 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
9543 DAG.getConstant(N2C->getAPIntValue().logBase2(),
9544 getShiftAmountTy(Temp.getValueType())));
9548 // Check to see if this is the equivalent of setcc
9549 // FIXME: Turn all of these into setcc if setcc if setcc is legal
9550 // otherwise, go ahead with the folds.
9551 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
9552 EVT XType = N0.getValueType();
9553 if (!LegalOperations ||
9554 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
9555 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
9556 if (Res.getValueType() != VT)
9557 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
9561 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
9562 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
9563 (!LegalOperations ||
9564 TLI.isOperationLegal(ISD::CTLZ, XType))) {
9565 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
9566 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
9567 DAG.getConstant(Log2_32(XType.getSizeInBits()),
9568 getShiftAmountTy(Ctlz.getValueType())));
9570 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
9571 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
9572 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
9573 XType, DAG.getConstant(0, XType), N0);
9574 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
9575 return DAG.getNode(ISD::SRL, DL, XType,
9576 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
9577 DAG.getConstant(XType.getSizeInBits()-1,
9578 getShiftAmountTy(XType)));
9580 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
9581 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
9582 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
9583 DAG.getConstant(XType.getSizeInBits()-1,
9584 getShiftAmountTy(N0.getValueType())));
9585 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
9589 // Check to see if this is an integer abs.
9590 // select_cc setg[te] X, 0, X, -X ->
9591 // select_cc setgt X, -1, X, -X ->
9592 // select_cc setl[te] X, 0, -X, X ->
9593 // select_cc setlt X, 1, -X, X ->
9594 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
9596 ConstantSDNode *SubC = NULL;
9597 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
9598 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
9599 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
9600 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
9601 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
9602 (N1C->isOne() && CC == ISD::SETLT)) &&
9603 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
9604 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
9606 EVT XType = N0.getValueType();
9607 if (SubC && SubC->isNullValue() && XType.isInteger()) {
9608 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
9610 DAG.getConstant(XType.getSizeInBits()-1,
9611 getShiftAmountTy(N0.getValueType())));
9612 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
9614 AddToWorkList(Shift.getNode());
9615 AddToWorkList(Add.getNode());
9616 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
9623 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
9624 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
9625 SDValue N1, ISD::CondCode Cond,
9626 DebugLoc DL, bool foldBooleans) {
9627 TargetLowering::DAGCombinerInfo
9628 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
9629 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
9632 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
9633 /// return a DAG expression to select that will generate the same value by
9634 /// multiplying by a magic number. See:
9635 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
9636 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
9637 std::vector<SDNode*> Built;
9638 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built);
9640 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
9646 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
9647 /// return a DAG expression to select that will generate the same value by
9648 /// multiplying by a magic number. See:
9649 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
9650 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
9651 std::vector<SDNode*> Built;
9652 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built);
9654 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
9660 /// FindBaseOffset - Return true if base is a frame index, which is known not
9661 // to alias with anything but itself. Provides base object and offset as
9663 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
9664 const GlobalValue *&GV, const void *&CV) {
9665 // Assume it is a primitive operation.
9666 Base = Ptr; Offset = 0; GV = 0; CV = 0;
9668 // If it's an adding a simple constant then integrate the offset.
9669 if (Base.getOpcode() == ISD::ADD) {
9670 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
9671 Base = Base.getOperand(0);
9672 Offset += C->getZExtValue();
9676 // Return the underlying GlobalValue, and update the Offset. Return false
9677 // for GlobalAddressSDNode since the same GlobalAddress may be represented
9678 // by multiple nodes with different offsets.
9679 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
9680 GV = G->getGlobal();
9681 Offset += G->getOffset();
9685 // Return the underlying Constant value, and update the Offset. Return false
9686 // for ConstantSDNodes since the same constant pool entry may be represented
9687 // by multiple nodes with different offsets.
9688 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
9689 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
9690 : (const void *)C->getConstVal();
9691 Offset += C->getOffset();
9694 // If it's any of the following then it can't alias with anything but itself.
9695 return isa<FrameIndexSDNode>(Base);
9698 /// isAlias - Return true if there is any possibility that the two addresses
9700 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
9701 const Value *SrcValue1, int SrcValueOffset1,
9702 unsigned SrcValueAlign1,
9703 const MDNode *TBAAInfo1,
9704 SDValue Ptr2, int64_t Size2,
9705 const Value *SrcValue2, int SrcValueOffset2,
9706 unsigned SrcValueAlign2,
9707 const MDNode *TBAAInfo2) const {
9708 // If they are the same then they must be aliases.
9709 if (Ptr1 == Ptr2) return true;
9711 // Gather base node and offset information.
9712 SDValue Base1, Base2;
9713 int64_t Offset1, Offset2;
9714 const GlobalValue *GV1, *GV2;
9715 const void *CV1, *CV2;
9716 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
9717 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
9719 // If they have a same base address then check to see if they overlap.
9720 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
9721 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
9723 // It is possible for different frame indices to alias each other, mostly
9724 // when tail call optimization reuses return address slots for arguments.
9725 // To catch this case, look up the actual index of frame indices to compute
9726 // the real alias relationship.
9727 if (isFrameIndex1 && isFrameIndex2) {
9728 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9729 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
9730 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
9731 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
9734 // Otherwise, if we know what the bases are, and they aren't identical, then
9735 // we know they cannot alias.
9736 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
9739 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
9740 // compared to the size and offset of the access, we may be able to prove they
9741 // do not alias. This check is conservative for now to catch cases created by
9742 // splitting vector types.
9743 if ((SrcValueAlign1 == SrcValueAlign2) &&
9744 (SrcValueOffset1 != SrcValueOffset2) &&
9745 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
9746 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
9747 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
9749 // There is no overlap between these relatively aligned accesses of similar
9750 // size, return no alias.
9751 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
9755 if (CombinerGlobalAA) {
9756 // Use alias analysis information.
9757 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
9758 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
9759 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
9760 AliasAnalysis::AliasResult AAResult =
9761 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
9762 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
9763 if (AAResult == AliasAnalysis::NoAlias)
9767 // Otherwise we have to assume they alias.
9771 bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) {
9773 int64_t Size0, Size1;
9774 const Value *SrcValue0, *SrcValue1;
9775 int SrcValueOffset0, SrcValueOffset1;
9776 unsigned SrcValueAlign0, SrcValueAlign1;
9777 const MDNode *SrcTBAAInfo0, *SrcTBAAInfo1;
9778 FindAliasInfo(Op0, Ptr0, Size0, SrcValue0, SrcValueOffset0,
9779 SrcValueAlign0, SrcTBAAInfo0);
9780 FindAliasInfo(Op1, Ptr1, Size1, SrcValue1, SrcValueOffset1,
9781 SrcValueAlign1, SrcTBAAInfo1);
9782 return isAlias(Ptr0, Size0, SrcValue0, SrcValueOffset0,
9783 SrcValueAlign0, SrcTBAAInfo0,
9784 Ptr1, Size1, SrcValue1, SrcValueOffset1,
9785 SrcValueAlign1, SrcTBAAInfo1);
9788 /// FindAliasInfo - Extracts the relevant alias information from the memory
9789 /// node. Returns true if the operand was a load.
9790 bool DAGCombiner::FindAliasInfo(SDNode *N,
9791 SDValue &Ptr, int64_t &Size,
9792 const Value *&SrcValue,
9793 int &SrcValueOffset,
9794 unsigned &SrcValueAlign,
9795 const MDNode *&TBAAInfo) const {
9796 LSBaseSDNode *LS = cast<LSBaseSDNode>(N);
9798 Ptr = LS->getBasePtr();
9799 Size = LS->getMemoryVT().getSizeInBits() >> 3;
9800 SrcValue = LS->getSrcValue();
9801 SrcValueOffset = LS->getSrcValueOffset();
9802 SrcValueAlign = LS->getOriginalAlignment();
9803 TBAAInfo = LS->getTBAAInfo();
9804 return isa<LoadSDNode>(LS);
9807 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
9808 /// looking for aliasing nodes and adding them to the Aliases vector.
9809 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
9810 SmallVector<SDValue, 8> &Aliases) {
9811 SmallVector<SDValue, 8> Chains; // List of chains to visit.
9812 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
9814 // Get alias information for node.
9817 const Value *SrcValue;
9819 unsigned SrcValueAlign;
9820 const MDNode *SrcTBAAInfo;
9821 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
9822 SrcValueAlign, SrcTBAAInfo);
9825 Chains.push_back(OriginalChain);
9828 // Look at each chain and determine if it is an alias. If so, add it to the
9829 // aliases list. If not, then continue up the chain looking for the next
9831 while (!Chains.empty()) {
9832 SDValue Chain = Chains.back();
9835 // For TokenFactor nodes, look at each operand and only continue up the
9836 // chain until we find two aliases. If we've seen two aliases, assume we'll
9837 // find more and revert to original chain since the xform is unlikely to be
9840 // FIXME: The depth check could be made to return the last non-aliasing
9841 // chain we found before we hit a tokenfactor rather than the original
9843 if (Depth > 6 || Aliases.size() == 2) {
9845 Aliases.push_back(OriginalChain);
9849 // Don't bother if we've been before.
9850 if (!Visited.insert(Chain.getNode()))
9853 switch (Chain.getOpcode()) {
9854 case ISD::EntryToken:
9855 // Entry token is ideal chain operand, but handled in FindBetterChain.
9860 // Get alias information for Chain.
9863 const Value *OpSrcValue;
9864 int OpSrcValueOffset;
9865 unsigned OpSrcValueAlign;
9866 const MDNode *OpSrcTBAAInfo;
9867 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
9868 OpSrcValue, OpSrcValueOffset,
9872 // If chain is alias then stop here.
9873 if (!(IsLoad && IsOpLoad) &&
9874 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
9876 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
9877 OpSrcValueAlign, OpSrcTBAAInfo)) {
9878 Aliases.push_back(Chain);
9880 // Look further up the chain.
9881 Chains.push_back(Chain.getOperand(0));
9887 case ISD::TokenFactor:
9888 // We have to check each of the operands of the token factor for "small"
9889 // token factors, so we queue them up. Adding the operands to the queue
9890 // (stack) in reverse order maintains the original order and increases the
9891 // likelihood that getNode will find a matching token factor (CSE.)
9892 if (Chain.getNumOperands() > 16) {
9893 Aliases.push_back(Chain);
9896 for (unsigned n = Chain.getNumOperands(); n;)
9897 Chains.push_back(Chain.getOperand(--n));
9902 // For all other instructions we will just have to take what we can get.
9903 Aliases.push_back(Chain);
9909 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
9910 /// for a better chain (aliasing node.)
9911 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
9912 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
9914 // Accumulate all the aliases to this node.
9915 GatherAllAliases(N, OldChain, Aliases);
9917 // If no operands then chain to entry token.
9918 if (Aliases.size() == 0)
9919 return DAG.getEntryNode();
9921 // If a single operand then chain to it. We don't need to revisit it.
9922 if (Aliases.size() == 1)
9925 // Construct a custom tailored token factor.
9926 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
9927 &Aliases[0], Aliases.size());
9930 // SelectionDAG::Combine - This is the entry point for the file.
9932 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
9933 CodeGenOpt::Level OptLevel) {
9934 /// run - This is the main entry point to this class.
9936 DAGCombiner(*this, AA, OptLevel).Run(Level);