1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: Should add a corresponding version of fold AND with
20 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
23 // FIXME: select C, pow2, pow2 -> something smart
24 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
25 // FIXME: (select C, load A, load B) -> load (select C, A, B)
26 // FIXME: Dead stores -> nuke
27 // FIXME: shr X, (and Y,31) -> shr X, Y
28 // FIXME: TRUNC (LOAD) -> EXT_LOAD/LOAD(smaller)
29 // FIXME: mul (x, const) -> shifts + adds
30 // FIXME: undef values
31 // FIXME: make truncate see through SIGN_EXTEND and AND
32 // FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
33 // FIXME: verify that getNode can't return extends with an operand whose type
34 // is >= to that of the extend.
35 // FIXME: divide by zero is currently left unfolded. do we want to turn this
37 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
38 // FIXME: reassociate (X+C)+Y into (X+Y)+C if the inner expression has one use
40 //===----------------------------------------------------------------------===//
42 #define DEBUG_TYPE "dagcombine"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/MathExtras.h"
47 #include "llvm/Target/TargetLowering.h"
53 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
60 // Worklist of all of the nodes that need to be simplified.
61 std::vector<SDNode*> WorkList;
63 /// AddUsersToWorkList - When an instruction is simplified, add all users of
64 /// the instruction to the work lists because they might get more simplified
67 void AddUsersToWorkList(SDNode *N) {
68 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
70 WorkList.push_back(*UI);
73 /// removeFromWorkList - remove all instances of N from the worklist.
74 void removeFromWorkList(SDNode *N) {
75 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
79 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
81 DEBUG(std::cerr << "\nReplacing "; N->dump();
82 std::cerr << "\nWith: "; To[0].Val->dump();
83 std::cerr << " and " << To.size()-1 << " other values\n");
84 std::vector<SDNode*> NowDead;
85 DAG.ReplaceAllUsesWith(N, To, &NowDead);
87 // Push the new nodes and any users onto the worklist
88 for (unsigned i = 0, e = To.size(); i != e; ++i) {
89 WorkList.push_back(To[i].Val);
90 AddUsersToWorkList(To[i].Val);
93 // Nodes can end up on the worklist more than once. Make sure we do
94 // not process a node that has been replaced.
95 removeFromWorkList(N);
96 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
97 removeFromWorkList(NowDead[i]);
99 // Finally, since the node is now dead, remove it from the graph.
101 return SDOperand(N, 0);
104 SDOperand CombineTo(SDNode *N, SDOperand Res) {
105 std::vector<SDOperand> To;
107 return CombineTo(N, To);
110 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
111 std::vector<SDOperand> To;
114 return CombineTo(N, To);
117 /// visit - call the node-specific routine that knows how to fold each
118 /// particular type of node.
119 SDOperand visit(SDNode *N);
121 // Visitation implementation - Implement dag node combining for different
122 // node types. The semantics are as follows:
124 // SDOperand.Val == 0 - No change was made
125 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
126 // otherwise - N should be replaced by the returned Operand.
128 SDOperand visitTokenFactor(SDNode *N);
129 SDOperand visitADD(SDNode *N);
130 SDOperand visitSUB(SDNode *N);
131 SDOperand visitMUL(SDNode *N);
132 SDOperand visitSDIV(SDNode *N);
133 SDOperand visitUDIV(SDNode *N);
134 SDOperand visitSREM(SDNode *N);
135 SDOperand visitUREM(SDNode *N);
136 SDOperand visitMULHU(SDNode *N);
137 SDOperand visitMULHS(SDNode *N);
138 SDOperand visitAND(SDNode *N);
139 SDOperand visitOR(SDNode *N);
140 SDOperand visitXOR(SDNode *N);
141 SDOperand visitSHL(SDNode *N);
142 SDOperand visitSRA(SDNode *N);
143 SDOperand visitSRL(SDNode *N);
144 SDOperand visitCTLZ(SDNode *N);
145 SDOperand visitCTTZ(SDNode *N);
146 SDOperand visitCTPOP(SDNode *N);
147 SDOperand visitSELECT(SDNode *N);
148 SDOperand visitSELECT_CC(SDNode *N);
149 SDOperand visitSETCC(SDNode *N);
150 SDOperand visitADD_PARTS(SDNode *N);
151 SDOperand visitSUB_PARTS(SDNode *N);
152 SDOperand visitSIGN_EXTEND(SDNode *N);
153 SDOperand visitZERO_EXTEND(SDNode *N);
154 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
155 SDOperand visitTRUNCATE(SDNode *N);
157 SDOperand visitFADD(SDNode *N);
158 SDOperand visitFSUB(SDNode *N);
159 SDOperand visitFMUL(SDNode *N);
160 SDOperand visitFDIV(SDNode *N);
161 SDOperand visitFREM(SDNode *N);
162 SDOperand visitSINT_TO_FP(SDNode *N);
163 SDOperand visitUINT_TO_FP(SDNode *N);
164 SDOperand visitFP_TO_SINT(SDNode *N);
165 SDOperand visitFP_TO_UINT(SDNode *N);
166 SDOperand visitFP_ROUND(SDNode *N);
167 SDOperand visitFP_ROUND_INREG(SDNode *N);
168 SDOperand visitFP_EXTEND(SDNode *N);
169 SDOperand visitFNEG(SDNode *N);
170 SDOperand visitFABS(SDNode *N);
171 SDOperand visitBRCOND(SDNode *N);
172 SDOperand visitBRCONDTWOWAY(SDNode *N);
173 SDOperand visitBR_CC(SDNode *N);
174 SDOperand visitBRTWOWAY_CC(SDNode *N);
176 SDOperand visitLOAD(SDNode *N);
177 SDOperand visitSTORE(SDNode *N);
179 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
180 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
181 SDOperand N3, ISD::CondCode CC);
182 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
183 ISD::CondCode Cond, bool foldBooleans = true);
185 DAGCombiner(SelectionDAG &D)
186 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
188 /// Run - runs the dag combiner on all nodes in the work list
189 void Run(bool RunningAfterLegalize);
193 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use
194 /// this predicate to simplify operations downstream. Op and Mask are known to
195 /// be the same type.
196 static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
197 const TargetLowering &TLI) {
199 if (Mask == 0) return true;
201 // If we know the result of a setcc has the top bits zero, use this info.
202 switch (Op.getOpcode()) {
204 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
206 return ((Mask & 1) == 0) &&
207 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
209 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
210 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
211 case ISD::ZERO_EXTEND:
212 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
213 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
214 case ISD::AssertZext:
215 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
216 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
218 // If either of the operands has zero bits, the result will too.
219 if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) ||
220 MaskedValueIsZero(Op.getOperand(0), Mask, TLI))
222 // (X & C1) & C2 == 0 iff C1 & C2 == 0.
223 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
224 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
228 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
229 MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
231 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
232 MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
234 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
235 MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
237 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
238 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
239 uint64_t NewVal = Mask << ShAmt->getValue();
240 SrcBits = MVT::getSizeInBits(Op.getValueType());
241 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
242 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
246 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
247 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
248 uint64_t NewVal = Mask >> ShAmt->getValue();
249 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
253 // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits.
254 if ((Mask&(Mask+1)) == 0) { // All low bits
255 if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
256 MaskedValueIsZero(Op.getOperand(1), Mask, TLI))
261 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
262 // We know that the top bits of C-X are clear if X contains less bits
263 // than C (i.e. no wrap-around can happen). For example, 20-X is
264 // positive if we can prove that X is >= 0 and < 16.
265 unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0));
266 if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear
267 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
268 uint64_t MaskV = (1ULL << (63-NLZ))-1;
269 if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) {
270 // High bits are clear this value is known to be >= C.
271 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
272 if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0)
281 // Bit counting instructions can not set the high bits of the result
282 // register. The max number of bits sets depends on the input.
283 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
289 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
290 // that selects between the values 1 and 0, making it equivalent to a setcc.
291 // Also, set the incoming LHS, RHS, and CC references to the appropriate
292 // nodes based on the type of node we are checking. This simplifies life a
293 // bit for the callers.
294 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
296 if (N.getOpcode() == ISD::SETCC) {
297 LHS = N.getOperand(0);
298 RHS = N.getOperand(1);
299 CC = N.getOperand(2);
302 if (N.getOpcode() == ISD::SELECT_CC &&
303 N.getOperand(2).getOpcode() == ISD::Constant &&
304 N.getOperand(3).getOpcode() == ISD::Constant &&
305 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
306 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
307 LHS = N.getOperand(0);
308 RHS = N.getOperand(1);
309 CC = N.getOperand(4);
315 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
316 // one use. If this is true, it allows the users to invert the operation for
317 // free when it is profitable to do so.
318 static bool isOneUseSetCC(SDOperand N) {
319 SDOperand N0, N1, N2;
320 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
325 // FIXME: This should probably go in the ISD class rather than being duplicated
327 static bool isCommutativeBinOp(unsigned Opcode) {
333 case ISD::XOR: return true;
334 default: return false; // FIXME: Need commutative info for user ops!
338 void DAGCombiner::Run(bool RunningAfterLegalize) {
339 // set the instance variable, so that the various visit routines may use it.
340 AfterLegalize = RunningAfterLegalize;
342 // Add all the dag nodes to the worklist.
343 WorkList.insert(WorkList.end(), DAG.allnodes_begin(), DAG.allnodes_end());
345 // Create a dummy node (which is not added to allnodes), that adds a reference
346 // to the root node, preventing it from being deleted, and tracking any
347 // changes of the root.
348 HandleSDNode Dummy(DAG.getRoot());
350 // while the worklist isn't empty, inspect the node on the end of it and
351 // try and combine it.
352 while (!WorkList.empty()) {
353 SDNode *N = WorkList.back();
356 // If N has no uses, it is dead. Make sure to revisit all N's operands once
357 // N is deleted from the DAG, since they too may now be dead or may have a
358 // reduced number of uses, allowing other xforms.
359 if (N->use_empty() && N != &Dummy) {
360 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
361 WorkList.push_back(N->getOperand(i).Val);
363 removeFromWorkList(N);
368 SDOperand RV = visit(N);
371 // If we get back the same node we passed in, rather than a new node or
372 // zero, we know that the node must have defined multiple values and
373 // CombineTo was used. Since CombineTo takes care of the worklist
374 // mechanics for us, we have no work to do in this case.
376 DEBUG(std::cerr << "\nReplacing "; N->dump();
377 std::cerr << "\nWith: "; RV.Val->dump();
379 std::vector<SDNode*> NowDead;
380 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
382 // Push the new node and any users onto the worklist
383 WorkList.push_back(RV.Val);
384 AddUsersToWorkList(RV.Val);
386 // Nodes can end up on the worklist more than once. Make sure we do
387 // not process a node that has been replaced.
388 removeFromWorkList(N);
389 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
390 removeFromWorkList(NowDead[i]);
392 // Finally, since the node is now dead, remove it from the graph.
398 // If the root changed (e.g. it was a dead load, update the root).
399 DAG.setRoot(Dummy.getValue());
402 SDOperand DAGCombiner::visit(SDNode *N) {
403 switch(N->getOpcode()) {
405 case ISD::TokenFactor: return visitTokenFactor(N);
406 case ISD::ADD: return visitADD(N);
407 case ISD::SUB: return visitSUB(N);
408 case ISD::MUL: return visitMUL(N);
409 case ISD::SDIV: return visitSDIV(N);
410 case ISD::UDIV: return visitUDIV(N);
411 case ISD::SREM: return visitSREM(N);
412 case ISD::UREM: return visitUREM(N);
413 case ISD::MULHU: return visitMULHU(N);
414 case ISD::MULHS: return visitMULHS(N);
415 case ISD::AND: return visitAND(N);
416 case ISD::OR: return visitOR(N);
417 case ISD::XOR: return visitXOR(N);
418 case ISD::SHL: return visitSHL(N);
419 case ISD::SRA: return visitSRA(N);
420 case ISD::SRL: return visitSRL(N);
421 case ISD::CTLZ: return visitCTLZ(N);
422 case ISD::CTTZ: return visitCTTZ(N);
423 case ISD::CTPOP: return visitCTPOP(N);
424 case ISD::SELECT: return visitSELECT(N);
425 case ISD::SELECT_CC: return visitSELECT_CC(N);
426 case ISD::SETCC: return visitSETCC(N);
427 case ISD::ADD_PARTS: return visitADD_PARTS(N);
428 case ISD::SUB_PARTS: return visitSUB_PARTS(N);
429 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
430 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
431 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
432 case ISD::TRUNCATE: return visitTRUNCATE(N);
433 case ISD::FADD: return visitFADD(N);
434 case ISD::FSUB: return visitFSUB(N);
435 case ISD::FMUL: return visitFMUL(N);
436 case ISD::FDIV: return visitFDIV(N);
437 case ISD::FREM: return visitFREM(N);
438 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
439 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
440 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
441 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
442 case ISD::FP_ROUND: return visitFP_ROUND(N);
443 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
444 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
445 case ISD::FNEG: return visitFNEG(N);
446 case ISD::FABS: return visitFABS(N);
447 case ISD::BRCOND: return visitBRCOND(N);
448 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
449 case ISD::BR_CC: return visitBR_CC(N);
450 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
451 case ISD::LOAD: return visitLOAD(N);
452 case ISD::STORE: return visitSTORE(N);
457 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
458 std::vector<SDOperand> Ops;
459 bool Changed = false;
461 // If the token factor has two operands and one is the entry token, replace
462 // the token factor with the other operand.
463 if (N->getNumOperands() == 2) {
464 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
465 return N->getOperand(1);
466 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
467 return N->getOperand(0);
470 // fold (tokenfactor (tokenfactor)) -> tokenfactor
471 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
472 SDOperand Op = N->getOperand(i);
473 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
475 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
476 Ops.push_back(Op.getOperand(j));
482 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
486 SDOperand DAGCombiner::visitADD(SDNode *N) {
487 SDOperand N0 = N->getOperand(0);
488 SDOperand N1 = N->getOperand(1);
489 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
490 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
491 MVT::ValueType VT = N0.getValueType();
493 // fold (add c1, c2) -> c1+c2
495 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT);
496 // canonicalize constant to RHS
501 // fold (add x, 0) -> x
502 if (N1C && N1C->isNullValue())
504 // fold (add (add x, c1), c2) -> (add x, c1+c2)
505 if (N1C && N0.getOpcode() == ISD::ADD) {
506 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
507 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
509 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1),
510 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT));
512 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0),
513 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT));
515 // fold ((0-A) + B) -> B-A
516 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
517 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
518 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
519 // fold (A + (0-B)) -> A-B
520 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
521 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
522 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
523 // fold (A+(B-A)) -> B
524 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
525 return N1.getOperand(0);
529 SDOperand DAGCombiner::visitSUB(SDNode *N) {
530 SDOperand N0 = N->getOperand(0);
531 SDOperand N1 = N->getOperand(1);
532 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
533 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
535 // fold (sub x, x) -> 0
537 return DAG.getConstant(0, N->getValueType(0));
539 // fold (sub c1, c2) -> c1-c2
541 return DAG.getConstant(N0C->getValue() - N1C->getValue(),
543 // fold (sub x, c) -> (add x, -c)
545 return DAG.getNode(ISD::ADD, N0.getValueType(), N0,
546 DAG.getConstant(-N1C->getValue(), N0.getValueType()));
549 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
550 return N0.getOperand(1);
552 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
553 return N0.getOperand(0);
557 SDOperand DAGCombiner::visitMUL(SDNode *N) {
558 SDOperand N0 = N->getOperand(0);
559 SDOperand N1 = N->getOperand(1);
560 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
561 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
562 MVT::ValueType VT = N0.getValueType();
564 // fold (mul c1, c2) -> c1*c2
566 return DAG.getConstant(N0C->getValue() * N1C->getValue(),
568 // canonicalize constant to RHS
573 // fold (mul x, 0) -> 0
574 if (N1C && N1C->isNullValue())
576 // fold (mul x, -1) -> 0-x
577 if (N1C && N1C->isAllOnesValue())
578 return DAG.getNode(ISD::SUB, N->getValueType(0),
579 DAG.getConstant(0, N->getValueType(0)), N0);
580 // fold (mul x, (1 << c)) -> x << c
581 if (N1C && isPowerOf2_64(N1C->getValue()))
582 return DAG.getNode(ISD::SHL, N->getValueType(0), N0,
583 DAG.getConstant(Log2_64(N1C->getValue()),
584 TLI.getShiftAmountTy()));
585 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2)
586 if (N1C && N0.getOpcode() == ISD::MUL) {
587 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
588 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
590 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1),
591 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT));
593 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0),
594 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT));
599 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
600 SDOperand N0 = N->getOperand(0);
601 SDOperand N1 = N->getOperand(1);
602 MVT::ValueType VT = N->getValueType(0);
603 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
604 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
606 // fold (sdiv c1, c2) -> c1/c2
607 if (N0C && N1C && !N1C->isNullValue())
608 return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(),
610 // If we know the sign bits of both operands are zero, strength reduce to a
611 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
612 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
613 if (MaskedValueIsZero(N1, SignBit, TLI) &&
614 MaskedValueIsZero(N0, SignBit, TLI))
615 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
619 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
620 SDOperand N0 = N->getOperand(0);
621 SDOperand N1 = N->getOperand(1);
622 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
623 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
625 // fold (udiv c1, c2) -> c1/c2
626 if (N0C && N1C && !N1C->isNullValue())
627 return DAG.getConstant(N0C->getValue() / N1C->getValue(),
629 // fold (udiv x, (1 << c)) -> x >>u c
630 if (N1C && isPowerOf2_64(N1C->getValue()))
631 return DAG.getNode(ISD::SRL, N->getValueType(0), N0,
632 DAG.getConstant(Log2_64(N1C->getValue()),
633 TLI.getShiftAmountTy()));
637 SDOperand DAGCombiner::visitSREM(SDNode *N) {
638 SDOperand N0 = N->getOperand(0);
639 SDOperand N1 = N->getOperand(1);
640 MVT::ValueType VT = N->getValueType(0);
641 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
642 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
644 // fold (srem c1, c2) -> c1%c2
645 if (N0C && N1C && !N1C->isNullValue())
646 return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(),
648 // If we know the sign bits of both operands are zero, strength reduce to a
649 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
650 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
651 if (MaskedValueIsZero(N1, SignBit, TLI) &&
652 MaskedValueIsZero(N0, SignBit, TLI))
653 return DAG.getNode(ISD::UREM, N1.getValueType(), N0, N1);
657 SDOperand DAGCombiner::visitUREM(SDNode *N) {
658 SDOperand N0 = N->getOperand(0);
659 SDOperand N1 = N->getOperand(1);
660 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
661 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
663 // fold (urem c1, c2) -> c1%c2
664 if (N0C && N1C && !N1C->isNullValue())
665 return DAG.getConstant(N0C->getValue() % N1C->getValue(),
667 // fold (urem x, pow2) -> (and x, pow2-1)
668 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
669 return DAG.getNode(ISD::AND, N0.getValueType(), N0,
670 DAG.getConstant(N1C->getValue()-1, N1.getValueType()));
674 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
675 SDOperand N0 = N->getOperand(0);
676 SDOperand N1 = N->getOperand(1);
677 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
679 // fold (mulhs x, 0) -> 0
680 if (N1C && N1C->isNullValue())
682 // fold (mulhs x, 1) -> (sra x, size(x)-1)
683 if (N1C && N1C->getValue() == 1)
684 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
685 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
686 TLI.getShiftAmountTy()));
690 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
691 SDOperand N0 = N->getOperand(0);
692 SDOperand N1 = N->getOperand(1);
693 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
695 // fold (mulhu x, 0) -> 0
696 if (N1C && N1C->isNullValue())
698 // fold (mulhu x, 1) -> 0
699 if (N1C && N1C->getValue() == 1)
700 return DAG.getConstant(0, N0.getValueType());
704 SDOperand DAGCombiner::visitAND(SDNode *N) {
705 SDOperand N0 = N->getOperand(0);
706 SDOperand N1 = N->getOperand(1);
707 SDOperand LL, LR, RL, RR, CC0, CC1;
708 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
709 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
710 MVT::ValueType VT = N1.getValueType();
711 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
713 // fold (and c1, c2) -> c1&c2
715 return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT);
716 // canonicalize constant to RHS
721 // fold (and x, -1) -> x
722 if (N1C && N1C->isAllOnesValue())
724 // if (and x, c) is known to be zero, return 0
725 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
726 return DAG.getConstant(0, VT);
727 // fold (and x, c) -> x iff (x & ~c) == 0
728 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
731 // fold (and (and x, c1), c2) -> (and x, c1^c2)
732 if (N1C && N0.getOpcode() == ISD::AND) {
733 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
734 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
736 return DAG.getNode(ISD::AND, VT, N0.getOperand(1),
737 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT));
739 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
740 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT));
742 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
743 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
744 unsigned ExtendBits =
745 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
746 if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0)
747 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
749 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
750 if (N0.getOpcode() == ISD::OR && N1C)
751 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
752 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
754 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
755 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
756 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
757 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
759 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
760 MVT::isInteger(LL.getValueType())) {
761 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
762 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
763 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
764 WorkList.push_back(ORNode.Val);
765 return DAG.getSetCC(VT, ORNode, LR, Op1);
767 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
768 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
769 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
770 WorkList.push_back(ANDNode.Val);
771 return DAG.getSetCC(VT, ANDNode, LR, Op1);
773 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
774 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
775 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
776 WorkList.push_back(ORNode.Val);
777 return DAG.getSetCC(VT, ORNode, LR, Op1);
780 // canonicalize equivalent to ll == rl
781 if (LL == RR && LR == RL) {
782 Op1 = ISD::getSetCCSwappedOperands(Op1);
785 if (LL == RL && LR == RR) {
786 bool isInteger = MVT::isInteger(LL.getValueType());
787 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
788 if (Result != ISD::SETCC_INVALID)
789 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
792 // fold (and (zext x), (zext y)) -> (zext (and x, y))
793 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
794 N1.getOpcode() == ISD::ZERO_EXTEND &&
795 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
796 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
797 N0.getOperand(0), N1.getOperand(0));
798 WorkList.push_back(ANDNode.Val);
799 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
801 // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y))
802 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
803 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) &&
804 N0.getOperand(1) == N1.getOperand(1)) {
805 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
806 N0.getOperand(0), N1.getOperand(0));
807 WorkList.push_back(ANDNode.Val);
808 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
810 // fold (and (sra)) -> (and (srl)) when possible.
811 if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse())
812 if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
813 // If the RHS of the AND has zeros where the sign bits of the SRA will
814 // land, turn the SRA into an SRL.
815 if (MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) &
816 (~0ULL>>(64-OpSizeInBits)), TLI)) {
817 WorkList.push_back(N);
818 CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
824 // fold (zext_inreg (extload x)) -> (zextload x)
825 if (N0.getOpcode() == ISD::EXTLOAD) {
826 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
827 // If we zero all the possible extended bits, then we can turn this into
828 // a zextload if we are running before legalize or the operation is legal.
829 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) &&
830 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
831 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
832 N0.getOperand(1), N0.getOperand(2),
834 WorkList.push_back(N);
835 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
839 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
840 if (N0.getOpcode() == ISD::SEXTLOAD && N0.Val->hasNUsesOfValue(1, 0)) {
841 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
842 // If we zero all the possible extended bits, then we can turn this into
843 // a zextload if we are running before legalize or the operation is legal.
844 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) &&
845 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
846 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
847 N0.getOperand(1), N0.getOperand(2),
849 WorkList.push_back(N);
850 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
857 SDOperand DAGCombiner::visitOR(SDNode *N) {
858 SDOperand N0 = N->getOperand(0);
859 SDOperand N1 = N->getOperand(1);
860 SDOperand LL, LR, RL, RR, CC0, CC1;
861 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
862 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
863 MVT::ValueType VT = N1.getValueType();
864 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
866 // fold (or c1, c2) -> c1|c2
868 return DAG.getConstant(N0C->getValue() | N1C->getValue(),
870 // canonicalize constant to RHS
875 // fold (or x, 0) -> x
876 if (N1C && N1C->isNullValue())
878 // fold (or x, -1) -> -1
879 if (N1C && N1C->isAllOnesValue())
881 // fold (or x, c) -> c iff (x & ~c) == 0
882 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
885 // fold (or (or x, c1), c2) -> (or x, c1|c2)
886 if (N1C && N0.getOpcode() == ISD::OR) {
887 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
888 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
890 return DAG.getNode(ISD::OR, VT, N0.getOperand(1),
891 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT));
893 return DAG.getNode(ISD::OR, VT, N0.getOperand(0),
894 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT));
896 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
897 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
898 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
899 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
901 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
902 MVT::isInteger(LL.getValueType())) {
903 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
904 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
905 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
906 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
907 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
908 WorkList.push_back(ORNode.Val);
909 return DAG.getSetCC(VT, ORNode, LR, Op1);
911 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
912 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
913 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
914 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
915 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
916 WorkList.push_back(ANDNode.Val);
917 return DAG.getSetCC(VT, ANDNode, LR, Op1);
920 // canonicalize equivalent to ll == rl
921 if (LL == RR && LR == RL) {
922 Op1 = ISD::getSetCCSwappedOperands(Op1);
925 if (LL == RL && LR == RR) {
926 bool isInteger = MVT::isInteger(LL.getValueType());
927 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
928 if (Result != ISD::SETCC_INVALID)
929 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
932 // fold (or (zext x), (zext y)) -> (zext (or x, y))
933 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
934 N1.getOpcode() == ISD::ZERO_EXTEND &&
935 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
936 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
937 N0.getOperand(0), N1.getOperand(0));
938 WorkList.push_back(ORNode.Val);
939 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
944 SDOperand DAGCombiner::visitXOR(SDNode *N) {
945 SDOperand N0 = N->getOperand(0);
946 SDOperand N1 = N->getOperand(1);
947 SDOperand LHS, RHS, CC;
948 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
949 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
950 MVT::ValueType VT = N0.getValueType();
952 // fold (xor c1, c2) -> c1^c2
954 return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT);
955 // canonicalize constant to RHS
960 // fold (xor x, 0) -> x
961 if (N1C && N1C->isNullValue())
963 // fold !(x cc y) -> (x !cc y)
964 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
965 bool isInt = MVT::isInteger(LHS.getValueType());
966 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
968 if (N0.getOpcode() == ISD::SETCC)
969 return DAG.getSetCC(VT, LHS, RHS, NotCC);
970 if (N0.getOpcode() == ISD::SELECT_CC)
971 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
972 assert(0 && "Unhandled SetCC Equivalent!");
975 // fold !(x or y) -> (!x and !y) iff x or y are setcc
976 if (N1C && N1C->getValue() == 1 &&
977 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
978 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
979 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
980 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
981 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
982 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
983 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
984 return DAG.getNode(NewOpcode, VT, LHS, RHS);
987 // fold !(x or y) -> (!x and !y) iff x or y are constants
988 if (N1C && N1C->isAllOnesValue() &&
989 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
990 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
991 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
992 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
993 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
994 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
995 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
996 return DAG.getNode(NewOpcode, VT, LHS, RHS);
999 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1000 if (N1C && N0.getOpcode() == ISD::XOR) {
1001 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1002 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1004 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1005 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1007 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1008 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1010 // fold (xor x, x) -> 0
1012 return DAG.getConstant(0, VT);
1013 // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
1014 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1015 N1.getOpcode() == ISD::ZERO_EXTEND &&
1016 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1017 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1018 N0.getOperand(0), N1.getOperand(0));
1019 WorkList.push_back(XORNode.Val);
1020 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
1025 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1026 SDOperand N0 = N->getOperand(0);
1027 SDOperand N1 = N->getOperand(1);
1028 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1029 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1030 MVT::ValueType VT = N0.getValueType();
1031 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1033 // fold (shl c1, c2) -> c1<<c2
1035 return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT);
1036 // fold (shl 0, x) -> 0
1037 if (N0C && N0C->isNullValue())
1039 // fold (shl x, c >= size(x)) -> undef
1040 if (N1C && N1C->getValue() >= OpSizeInBits)
1041 return DAG.getNode(ISD::UNDEF, VT);
1042 // fold (shl x, 0) -> x
1043 if (N1C && N1C->isNullValue())
1045 // if (shl x, c) is known to be zero, return 0
1046 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
1047 return DAG.getConstant(0, VT);
1048 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1049 if (N1C && N0.getOpcode() == ISD::SHL &&
1050 N0.getOperand(1).getOpcode() == ISD::Constant) {
1051 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1052 uint64_t c2 = N1C->getValue();
1053 if (c1 + c2 > OpSizeInBits)
1054 return DAG.getConstant(0, VT);
1055 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1056 DAG.getConstant(c1 + c2, N1.getValueType()));
1058 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1059 // (srl (and x, -1 << c1), c1-c2)
1060 if (N1C && N0.getOpcode() == ISD::SRL &&
1061 N0.getOperand(1).getOpcode() == ISD::Constant) {
1062 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1063 uint64_t c2 = N1C->getValue();
1064 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1065 DAG.getConstant(~0ULL << c1, VT));
1067 return DAG.getNode(ISD::SHL, VT, Mask,
1068 DAG.getConstant(c2-c1, N1.getValueType()));
1070 return DAG.getNode(ISD::SRL, VT, Mask,
1071 DAG.getConstant(c1-c2, N1.getValueType()));
1073 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1074 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1075 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1076 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1080 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1081 SDOperand N0 = N->getOperand(0);
1082 SDOperand N1 = N->getOperand(1);
1083 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1084 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1085 MVT::ValueType VT = N0.getValueType();
1086 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1088 // fold (sra c1, c2) -> c1>>c2
1090 return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT);
1091 // fold (sra 0, x) -> 0
1092 if (N0C && N0C->isNullValue())
1094 // fold (sra -1, x) -> -1
1095 if (N0C && N0C->isAllOnesValue())
1097 // fold (sra x, c >= size(x)) -> undef
1098 if (N1C && N1C->getValue() >= OpSizeInBits)
1099 return DAG.getNode(ISD::UNDEF, VT);
1100 // fold (sra x, 0) -> x
1101 if (N1C && N1C->isNullValue())
1103 // If the sign bit is known to be zero, switch this to a SRL.
1104 if (MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI))
1105 return DAG.getNode(ISD::SRL, VT, N0, N1);
1109 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1110 SDOperand N0 = N->getOperand(0);
1111 SDOperand N1 = N->getOperand(1);
1112 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1113 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1114 MVT::ValueType VT = N0.getValueType();
1115 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1117 // fold (srl c1, c2) -> c1 >>u c2
1119 return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT);
1120 // fold (srl 0, x) -> 0
1121 if (N0C && N0C->isNullValue())
1123 // fold (srl x, c >= size(x)) -> undef
1124 if (N1C && N1C->getValue() >= OpSizeInBits)
1125 return DAG.getNode(ISD::UNDEF, VT);
1126 // fold (srl x, 0) -> x
1127 if (N1C && N1C->isNullValue())
1129 // if (srl x, c) is known to be zero, return 0
1130 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
1131 return DAG.getConstant(0, VT);
1132 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1133 if (N1C && N0.getOpcode() == ISD::SRL &&
1134 N0.getOperand(1).getOpcode() == ISD::Constant) {
1135 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1136 uint64_t c2 = N1C->getValue();
1137 if (c1 + c2 > OpSizeInBits)
1138 return DAG.getConstant(0, VT);
1139 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1140 DAG.getConstant(c1 + c2, N1.getValueType()));
1145 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1146 SDOperand N0 = N->getOperand(0);
1147 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1149 // fold (ctlz c1) -> c2
1151 return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()),
1156 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1157 SDOperand N0 = N->getOperand(0);
1158 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1160 // fold (cttz c1) -> c2
1162 return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()),
1167 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1168 SDOperand N0 = N->getOperand(0);
1169 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1171 // fold (ctpop c1) -> c2
1173 return DAG.getConstant(CountPopulation_64(N0C->getValue()),
1178 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1179 SDOperand N0 = N->getOperand(0);
1180 SDOperand N1 = N->getOperand(1);
1181 SDOperand N2 = N->getOperand(2);
1182 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1183 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1184 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1185 MVT::ValueType VT = N->getValueType(0);
1187 // fold select C, X, X -> X
1190 // fold select true, X, Y -> X
1191 if (N0C && !N0C->isNullValue())
1193 // fold select false, X, Y -> Y
1194 if (N0C && N0C->isNullValue())
1196 // fold select C, 1, X -> C | X
1197 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1198 return DAG.getNode(ISD::OR, VT, N0, N2);
1199 // fold select C, 0, X -> ~C & X
1200 // FIXME: this should check for C type == X type, not i1?
1201 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1202 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1203 WorkList.push_back(XORNode.Val);
1204 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1206 // fold select C, X, 1 -> ~C | X
1207 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1208 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1209 WorkList.push_back(XORNode.Val);
1210 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1212 // fold select C, X, 0 -> C & X
1213 // FIXME: this should check for C type == X type, not i1?
1214 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1215 return DAG.getNode(ISD::AND, VT, N0, N1);
1216 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1217 if (MVT::i1 == VT && N0 == N1)
1218 return DAG.getNode(ISD::OR, VT, N0, N2);
1219 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1220 if (MVT::i1 == VT && N0 == N2)
1221 return DAG.getNode(ISD::AND, VT, N0, N1);
1222 // fold selects based on a setcc into other things, such as min/max/abs
1223 if (N0.getOpcode() == ISD::SETCC)
1224 return SimplifySelect(N0, N1, N2);
1228 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1229 SDOperand N0 = N->getOperand(0);
1230 SDOperand N1 = N->getOperand(1);
1231 SDOperand N2 = N->getOperand(2);
1232 SDOperand N3 = N->getOperand(3);
1233 SDOperand N4 = N->getOperand(4);
1234 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1235 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1236 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1237 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1239 // Determine if the condition we're dealing with is constant
1240 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1241 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1243 // fold select_cc lhs, rhs, x, x, cc -> x
1246 // fold select_cc into other things, such as min/max/abs
1247 return SimplifySelectCC(N0, N1, N2, N3, CC);
1250 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1251 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1252 cast<CondCodeSDNode>(N->getOperand(2))->get());
1255 SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) {
1256 SDOperand LHSLo = N->getOperand(0);
1257 SDOperand RHSLo = N->getOperand(2);
1258 MVT::ValueType VT = LHSLo.getValueType();
1260 // fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo)
1261 if (MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1262 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
1264 WorkList.push_back(Hi.Val);
1265 CombineTo(N, RHSLo, Hi);
1268 // fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo)
1269 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1270 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
1272 WorkList.push_back(Hi.Val);
1273 CombineTo(N, LHSLo, Hi);
1279 SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) {
1280 SDOperand LHSLo = N->getOperand(0);
1281 SDOperand RHSLo = N->getOperand(2);
1282 MVT::ValueType VT = LHSLo.getValueType();
1284 // fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo)
1285 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1286 SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1),
1288 WorkList.push_back(Hi.Val);
1289 CombineTo(N, LHSLo, Hi);
1295 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1296 SDOperand N0 = N->getOperand(0);
1297 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1298 MVT::ValueType VT = N->getValueType(0);
1300 // fold (sext c1) -> c1
1302 return DAG.getConstant(N0C->getSignExtended(), VT);
1303 // fold (sext (sext x)) -> (sext x)
1304 if (N0.getOpcode() == ISD::SIGN_EXTEND)
1305 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1306 // fold (sext (sextload x)) -> (sextload x)
1307 if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType())
1309 // fold (sext (load x)) -> (sextload x)
1310 if (N0.getOpcode() == ISD::LOAD && N0.Val->hasNUsesOfValue(1, 0)) {
1311 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1312 N0.getOperand(1), N0.getOperand(2),
1314 WorkList.push_back(N);
1315 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1316 ExtLoad.getValue(1));
1322 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1323 SDOperand N0 = N->getOperand(0);
1324 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1325 MVT::ValueType VT = N->getValueType(0);
1327 // fold (zext c1) -> c1
1329 return DAG.getConstant(N0C->getValue(), VT);
1330 // fold (zext (zext x)) -> (zext x)
1331 if (N0.getOpcode() == ISD::ZERO_EXTEND)
1332 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1336 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1337 SDOperand N0 = N->getOperand(0);
1338 SDOperand N1 = N->getOperand(1);
1339 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1340 MVT::ValueType VT = N->getValueType(0);
1341 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1342 unsigned EVTBits = MVT::getSizeInBits(EVT);
1344 // fold (sext_in_reg c1) -> c1
1346 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1347 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1349 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1350 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1351 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1354 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1355 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1356 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1357 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1359 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1360 if (N0.getOpcode() == ISD::AssertSext &&
1361 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1364 // fold (sext_in_reg (sextload x)) -> (sextload x)
1365 if (N0.getOpcode() == ISD::SEXTLOAD &&
1366 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1369 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1370 if (N0.getOpcode() == ISD::SETCC &&
1371 TLI.getSetCCResultContents() ==
1372 TargetLowering::ZeroOrNegativeOneSetCCResult)
1374 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1375 if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI))
1376 return DAG.getNode(ISD::AND, N0.getValueType(), N0,
1377 DAG.getConstant(~0ULL >> (64-EVTBits), VT));
1378 // fold (sext_in_reg (srl x)) -> sra x
1379 if (N0.getOpcode() == ISD::SRL &&
1380 N0.getOperand(1).getOpcode() == ISD::Constant &&
1381 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
1382 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
1385 // fold (sext_inreg (extload x)) -> (sextload x)
1386 if (N0.getOpcode() == ISD::EXTLOAD &&
1387 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1388 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1389 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1390 N0.getOperand(1), N0.getOperand(2),
1392 WorkList.push_back(N);
1393 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1396 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1397 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.Val->hasNUsesOfValue(1, 0) &&
1398 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1399 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1400 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1401 N0.getOperand(1), N0.getOperand(2),
1403 WorkList.push_back(N);
1404 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1410 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1411 SDOperand N0 = N->getOperand(0);
1412 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1413 MVT::ValueType VT = N->getValueType(0);
1416 if (N0.getValueType() == N->getValueType(0))
1418 // fold (truncate c1) -> c1
1420 return DAG.getConstant(N0C->getValue(), VT);
1421 // fold (truncate (truncate x)) -> (truncate x)
1422 if (N0.getOpcode() == ISD::TRUNCATE)
1423 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1424 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1425 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
1426 if (N0.getValueType() < VT)
1427 // if the source is smaller than the dest, we still need an extend
1428 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1429 else if (N0.getValueType() > VT)
1430 // if the source is larger than the dest, than we just need the truncate
1431 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1433 // if the source and dest are the same type, we can drop both the extend
1435 return N0.getOperand(0);
1437 // fold (truncate (load x)) -> (smaller load x)
1438 if (N0.getOpcode() == ISD::LOAD && N0.Val->hasNUsesOfValue(1, 0)) {
1439 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
1440 "Cannot truncate to larger type!");
1441 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1442 // For big endian targets, we need to add an offset to the pointer to load
1443 // the correct bytes. For little endian systems, we merely need to read
1444 // fewer bytes from the same pointer.
1446 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
1447 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
1448 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
1449 DAG.getConstant(PtrOff, PtrType));
1450 WorkList.push_back(NewPtr.Val);
1451 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
1452 WorkList.push_back(N);
1453 CombineTo(N0.Val, Load, Load.getValue(1));
1459 SDOperand DAGCombiner::visitFADD(SDNode *N) {
1460 SDOperand N0 = N->getOperand(0);
1461 SDOperand N1 = N->getOperand(1);
1462 MVT::ValueType VT = N->getValueType(0);
1464 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1465 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1466 // fold floating point (fadd c1, c2)
1467 return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(),
1468 N->getValueType(0));
1470 // fold (A + (-B)) -> A-B
1471 if (N1.getOpcode() == ISD::FNEG)
1472 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
1474 // fold ((-A) + B) -> B-A
1475 if (N0.getOpcode() == ISD::FNEG)
1476 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
1481 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
1482 SDOperand N0 = N->getOperand(0);
1483 SDOperand N1 = N->getOperand(1);
1484 MVT::ValueType VT = N->getValueType(0);
1486 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1487 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1488 // fold floating point (fsub c1, c2)
1489 return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(),
1490 N->getValueType(0));
1492 // fold (A-(-B)) -> A+B
1493 if (N1.getOpcode() == ISD::FNEG)
1494 return DAG.getNode(ISD::FADD, N0.getValueType(), N0, N1.getOperand(0));
1499 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
1500 SDOperand N0 = N->getOperand(0);
1501 SDOperand N1 = N->getOperand(1);
1502 MVT::ValueType VT = N->getValueType(0);
1504 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1505 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1506 // fold floating point (fmul c1, c2)
1507 return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(),
1508 N->getValueType(0));
1513 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
1514 SDOperand N0 = N->getOperand(0);
1515 SDOperand N1 = N->getOperand(1);
1516 MVT::ValueType VT = N->getValueType(0);
1518 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1519 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1520 // fold floating point (fdiv c1, c2)
1521 return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(),
1522 N->getValueType(0));
1527 SDOperand DAGCombiner::visitFREM(SDNode *N) {
1528 SDOperand N0 = N->getOperand(0);
1529 SDOperand N1 = N->getOperand(1);
1530 MVT::ValueType VT = N->getValueType(0);
1532 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1533 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1534 // fold floating point (frem c1, c2) -> fmod(c1, c2)
1535 return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()),
1536 N->getValueType(0));
1542 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
1543 SDOperand N0 = N->getOperand(0);
1544 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1546 // fold (sint_to_fp c1) -> c1fp
1548 return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0));
1552 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
1553 SDOperand N0 = N->getOperand(0);
1554 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1556 // fold (uint_to_fp c1) -> c1fp
1558 return DAG.getConstantFP(N0C->getValue(), N->getValueType(0));
1562 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
1563 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1565 // fold (fp_to_sint c1fp) -> c1
1567 return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0));
1571 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1572 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1574 // fold (fp_to_uint c1fp) -> c1
1576 return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0));
1580 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
1581 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1583 // fold (fp_round c1fp) -> c1fp
1585 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
1589 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
1590 SDOperand N0 = N->getOperand(0);
1591 MVT::ValueType VT = N->getValueType(0);
1592 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1593 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1595 // fold (fp_round_inreg c1fp) -> c1fp
1597 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
1598 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
1603 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
1604 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1606 // fold (fp_extend c1fp) -> c1fp
1608 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
1612 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
1613 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1614 // fold (neg c1) -> -c1
1616 return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0));
1617 // fold (neg (sub x, y)) -> (sub y, x)
1618 if (N->getOperand(0).getOpcode() == ISD::SUB)
1619 return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1),
1621 // fold (neg (neg x)) -> x
1622 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1623 return N->getOperand(0).getOperand(0);
1627 SDOperand DAGCombiner::visitFABS(SDNode *N) {
1628 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1629 // fold (fabs c1) -> fabs(c1)
1631 return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0));
1632 // fold (fabs (fabs x)) -> (fabs x)
1633 if (N->getOperand(0).getOpcode() == ISD::FABS)
1634 return N->getOperand(0);
1635 // fold (fabs (fneg x)) -> (fabs x)
1636 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1637 return DAG.getNode(ISD::FABS, N->getValueType(0),
1638 N->getOperand(0).getOperand(0));
1642 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
1643 SDOperand Chain = N->getOperand(0);
1644 SDOperand N1 = N->getOperand(1);
1645 SDOperand N2 = N->getOperand(2);
1646 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1648 // never taken branch, fold to chain
1649 if (N1C && N1C->isNullValue())
1651 // unconditional branch
1652 if (N1C && N1C->getValue() == 1)
1653 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1657 SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
1658 SDOperand Chain = N->getOperand(0);
1659 SDOperand N1 = N->getOperand(1);
1660 SDOperand N2 = N->getOperand(2);
1661 SDOperand N3 = N->getOperand(3);
1662 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1664 // unconditional branch to true mbb
1665 if (N1C && N1C->getValue() == 1)
1666 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1667 // unconditional branch to false mbb
1668 if (N1C && N1C->isNullValue())
1669 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
1673 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
1675 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
1676 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
1677 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
1679 // Use SimplifySetCC to simplify SETCC's.
1680 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
1681 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
1683 // fold br_cc true, dest -> br dest (unconditional branch)
1684 if (SCCC && SCCC->getValue())
1685 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
1687 // fold br_cc false, dest -> unconditional fall through
1688 if (SCCC && SCCC->isNullValue())
1689 return N->getOperand(0);
1690 // fold to a simpler setcc
1691 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
1692 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
1693 Simp.getOperand(2), Simp.getOperand(0),
1694 Simp.getOperand(1), N->getOperand(4));
1698 SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
1699 SDOperand Chain = N->getOperand(0);
1700 SDOperand CCN = N->getOperand(1);
1701 SDOperand LHS = N->getOperand(2);
1702 SDOperand RHS = N->getOperand(3);
1703 SDOperand N4 = N->getOperand(4);
1704 SDOperand N5 = N->getOperand(5);
1706 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
1707 cast<CondCodeSDNode>(CCN)->get(), false);
1708 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1710 // fold select_cc lhs, rhs, x, x, cc -> x
1712 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
1713 // fold select_cc true, x, y -> x
1714 if (SCCC && SCCC->getValue())
1715 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
1716 // fold select_cc false, x, y -> y
1717 if (SCCC && SCCC->isNullValue())
1718 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
1719 // fold to a simpler setcc
1720 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1721 return DAG.getBR2Way_CC(Chain, SCC.getOperand(2), SCC.getOperand(0),
1722 SCC.getOperand(1), N4, N5);
1726 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
1727 SDOperand Chain = N->getOperand(0);
1728 SDOperand Ptr = N->getOperand(1);
1729 SDOperand SrcValue = N->getOperand(2);
1731 // If this load is directly stored, replace the load value with the stored
1733 // TODO: Handle store large -> read small portion.
1734 // TODO: Handle TRUNCSTORE/EXTLOAD
1735 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
1736 Chain.getOperand(1).getValueType() == N->getValueType(0))
1737 return CombineTo(N, Chain.getOperand(1), Chain);
1742 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
1743 SDOperand Chain = N->getOperand(0);
1744 SDOperand Value = N->getOperand(1);
1745 SDOperand Ptr = N->getOperand(2);
1746 SDOperand SrcValue = N->getOperand(3);
1748 // If this is a store that kills a previous store, remove the previous store.
1749 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
1750 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */) {
1751 // Create a new store of Value that replaces both stores.
1752 SDNode *PrevStore = Chain.Val;
1753 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
1755 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
1756 PrevStore->getOperand(0), Value, Ptr,
1758 CombineTo(N, NewStore); // Nuke this store.
1759 CombineTo(PrevStore, NewStore); // Nuke the previous store.
1760 return SDOperand(N, 0);
1766 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
1767 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
1769 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
1770 cast<CondCodeSDNode>(N0.getOperand(2))->get());
1771 // If we got a simplified select_cc node back from SimplifySelectCC, then
1772 // break it down into a new SETCC node, and a new SELECT node, and then return
1773 // the SELECT node, since we were called with a SELECT node.
1775 // Check to see if we got a select_cc back (to turn into setcc/select).
1776 // Otherwise, just return whatever node we got back, like fabs.
1777 if (SCC.getOpcode() == ISD::SELECT_CC) {
1778 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
1779 SCC.getOperand(0), SCC.getOperand(1),
1781 WorkList.push_back(SETCC.Val);
1782 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
1783 SCC.getOperand(3), SETCC);
1790 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
1791 SDOperand N2, SDOperand N3,
1794 MVT::ValueType VT = N2.getValueType();
1795 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1796 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1797 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
1798 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
1800 // Determine if the condition we're dealing with is constant
1801 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1802 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1804 // fold select_cc true, x, y -> x
1805 if (SCCC && SCCC->getValue())
1807 // fold select_cc false, x, y -> y
1808 if (SCCC && SCCC->getValue() == 0)
1811 // Check to see if we can simplify the select into an fabs node
1812 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1813 // Allow either -0.0 or 0.0
1814 if (CFP->getValue() == 0.0) {
1815 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
1816 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
1817 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
1818 N2 == N3.getOperand(0))
1819 return DAG.getNode(ISD::FABS, VT, N0);
1821 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
1822 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
1823 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
1824 N2.getOperand(0) == N3)
1825 return DAG.getNode(ISD::FABS, VT, N3);
1829 // Check to see if we can perform the "gzip trick", transforming
1830 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
1831 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
1832 MVT::isInteger(N0.getValueType()) &&
1833 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
1834 MVT::ValueType XType = N0.getValueType();
1835 MVT::ValueType AType = N2.getValueType();
1836 if (XType >= AType) {
1837 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
1838 // single-bit constant.
1839 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
1840 unsigned ShCtV = Log2_64(N2C->getValue());
1841 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
1842 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
1843 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
1844 WorkList.push_back(Shift.Val);
1845 if (XType > AType) {
1846 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
1847 WorkList.push_back(Shift.Val);
1849 return DAG.getNode(ISD::AND, AType, Shift, N2);
1851 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
1852 DAG.getConstant(MVT::getSizeInBits(XType)-1,
1853 TLI.getShiftAmountTy()));
1854 WorkList.push_back(Shift.Val);
1855 if (XType > AType) {
1856 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
1857 WorkList.push_back(Shift.Val);
1859 return DAG.getNode(ISD::AND, AType, Shift, N2);
1863 // fold select C, 16, 0 -> shl C, 4
1864 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
1865 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
1866 // Get a SetCC of the condition
1867 // FIXME: Should probably make sure that setcc is legal if we ever have a
1868 // target where it isn't.
1869 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
1870 WorkList.push_back(SCC.Val);
1871 // cast from setcc result type to select result type
1873 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
1875 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
1876 WorkList.push_back(Temp.Val);
1877 // shl setcc result by log2 n2c
1878 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
1879 DAG.getConstant(Log2_64(N2C->getValue()),
1880 TLI.getShiftAmountTy()));
1883 // Check to see if this is the equivalent of setcc
1884 // FIXME: Turn all of these into setcc if setcc if setcc is legal
1885 // otherwise, go ahead with the folds.
1886 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
1887 MVT::ValueType XType = N0.getValueType();
1888 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
1889 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
1890 if (Res.getValueType() != VT)
1891 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
1895 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
1896 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
1897 TLI.isOperationLegal(ISD::CTLZ, XType)) {
1898 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
1899 return DAG.getNode(ISD::SRL, XType, Ctlz,
1900 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
1901 TLI.getShiftAmountTy()));
1903 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
1904 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
1905 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
1907 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
1908 DAG.getConstant(~0ULL, XType));
1909 return DAG.getNode(ISD::SRL, XType,
1910 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
1911 DAG.getConstant(MVT::getSizeInBits(XType)-1,
1912 TLI.getShiftAmountTy()));
1914 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
1915 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
1916 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
1917 DAG.getConstant(MVT::getSizeInBits(XType)-1,
1918 TLI.getShiftAmountTy()));
1919 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
1923 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
1924 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
1925 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
1926 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
1927 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
1928 MVT::ValueType XType = N0.getValueType();
1929 if (SubC->isNullValue() && MVT::isInteger(XType)) {
1930 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
1931 DAG.getConstant(MVT::getSizeInBits(XType)-1,
1932 TLI.getShiftAmountTy()));
1933 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
1934 WorkList.push_back(Shift.Val);
1935 WorkList.push_back(Add.Val);
1936 return DAG.getNode(ISD::XOR, XType, Add, Shift);
1944 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
1945 SDOperand N1, ISD::CondCode Cond,
1946 bool foldBooleans) {
1947 // These setcc operations always fold.
1951 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1953 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1956 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
1957 uint64_t C1 = N1C->getValue();
1958 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
1959 uint64_t C0 = N0C->getValue();
1961 // Sign extend the operands if required
1962 if (ISD::isSignedIntSetCC(Cond)) {
1963 C0 = N0C->getSignExtended();
1964 C1 = N1C->getSignExtended();
1968 default: assert(0 && "Unknown integer setcc!");
1969 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
1970 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
1971 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
1972 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
1973 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
1974 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
1975 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
1976 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
1977 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
1978 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
1981 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1982 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1983 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
1985 // If the comparison constant has bits in the upper part, the
1986 // zero-extended value could never match.
1987 if (C1 & (~0ULL << InSize)) {
1988 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
1992 case ISD::SETEQ: return DAG.getConstant(0, VT);
1995 case ISD::SETNE: return DAG.getConstant(1, VT);
1998 // True if the sign bit of C1 is set.
1999 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
2002 // True if the sign bit of C1 isn't set.
2003 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
2009 // Otherwise, we can perform the comparison with the low bits.
2017 return DAG.getSetCC(VT, N0.getOperand(0),
2018 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
2021 break; // todo, be more careful with signed comparisons
2023 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2024 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2025 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2026 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
2027 MVT::ValueType ExtDstTy = N0.getValueType();
2028 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
2030 // If the extended part has any inconsistent bits, it cannot ever
2031 // compare equal. In other words, they have to be all ones or all
2034 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
2035 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
2036 return DAG.getConstant(Cond == ISD::SETNE, VT);
2039 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
2040 if (Op0Ty == ExtSrcTy) {
2041 ZextOp = N0.getOperand(0);
2043 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
2044 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
2045 DAG.getConstant(Imm, Op0Ty));
2047 WorkList.push_back(ZextOp.Val);
2048 // Otherwise, make this a use of a zext.
2049 return DAG.getSetCC(VT, ZextOp,
2050 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
2055 uint64_t MinVal, MaxVal;
2056 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
2057 if (ISD::isSignedIntSetCC(Cond)) {
2058 MinVal = 1ULL << (OperandBitSize-1);
2059 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
2060 MaxVal = ~0ULL >> (65-OperandBitSize);
2065 MaxVal = ~0ULL >> (64-OperandBitSize);
2068 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2069 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2070 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2071 --C1; // X >= C0 --> X > (C0-1)
2072 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2073 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2076 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2077 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2078 ++C1; // X <= C0 --> X < (C0+1)
2079 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2080 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2083 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2084 return DAG.getConstant(0, VT); // X < MIN --> false
2086 // Canonicalize setgt X, Min --> setne X, Min
2087 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2088 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2090 // If we have setult X, 1, turn it into seteq X, 0
2091 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2092 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
2094 // If we have setugt X, Max-1, turn it into seteq X, Max
2095 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2096 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
2099 // If we have "setcc X, C0", check to see if we can shrink the immediate
2102 // SETUGT X, SINTMAX -> SETLT X, 0
2103 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
2104 C1 == (~0ULL >> (65-OperandBitSize)))
2105 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
2108 // FIXME: Implement the rest of these.
2110 // Fold bit comparisons when we can.
2111 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2112 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
2113 if (ConstantSDNode *AndRHS =
2114 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2115 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2116 // Perform the xform if the AND RHS is a single bit.
2117 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
2118 return DAG.getNode(ISD::SRL, VT, N0,
2119 DAG.getConstant(Log2_64(AndRHS->getValue()),
2120 TLI.getShiftAmountTy()));
2122 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
2123 // (X & 8) == 8 --> (X & 8) >> 3
2124 // Perform the xform if C1 is a single bit.
2125 if ((C1 & (C1-1)) == 0) {
2126 return DAG.getNode(ISD::SRL, VT, N0,
2127 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
2132 } else if (isa<ConstantSDNode>(N0.Val)) {
2133 // Ensure that the constant occurs on the RHS.
2134 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2137 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
2138 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
2139 double C0 = N0C->getValue(), C1 = N1C->getValue();
2142 default: break; // FIXME: Implement the rest of these!
2143 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2144 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2145 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
2146 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
2147 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
2148 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
2151 // Ensure that the constant occurs on the RHS.
2152 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2156 // We can always fold X == Y for integer setcc's.
2157 if (MVT::isInteger(N0.getValueType()))
2158 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2159 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2160 if (UOF == 2) // FP operators that are undefined on NaNs.
2161 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2162 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2163 return DAG.getConstant(UOF, VT);
2164 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2165 // if it is not already.
2166 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO;
2167 if (NewCond != Cond)
2168 return DAG.getSetCC(VT, N0, N1, NewCond);
2171 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2172 MVT::isInteger(N0.getValueType())) {
2173 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2174 N0.getOpcode() == ISD::XOR) {
2175 // Simplify (X+Y) == (X+Z) --> Y == Z
2176 if (N0.getOpcode() == N1.getOpcode()) {
2177 if (N0.getOperand(0) == N1.getOperand(0))
2178 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2179 if (N0.getOperand(1) == N1.getOperand(1))
2180 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
2181 if (isCommutativeBinOp(N0.getOpcode())) {
2182 // If X op Y == Y op X, try other combinations.
2183 if (N0.getOperand(0) == N1.getOperand(1))
2184 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
2185 if (N0.getOperand(1) == N1.getOperand(0))
2186 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2190 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes.
2191 if (N0.getOpcode() == ISD::XOR)
2192 if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2193 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2194 // If we know that all of the inverted bits are zero, don't bother
2195 // performing the inversion.
2196 if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI))
2197 return DAG.getSetCC(VT, N0.getOperand(0),
2198 DAG.getConstant(XORC->getValue()^RHSC->getValue(),
2199 N0.getValueType()), Cond);
2202 // Simplify (X+Z) == X --> Z == 0
2203 if (N0.getOperand(0) == N1)
2204 return DAG.getSetCC(VT, N0.getOperand(1),
2205 DAG.getConstant(0, N0.getValueType()), Cond);
2206 if (N0.getOperand(1) == N1) {
2207 if (isCommutativeBinOp(N0.getOpcode()))
2208 return DAG.getSetCC(VT, N0.getOperand(0),
2209 DAG.getConstant(0, N0.getValueType()), Cond);
2211 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2212 // (Z-X) == X --> Z == X<<1
2213 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
2215 DAG.getConstant(1,TLI.getShiftAmountTy()));
2216 WorkList.push_back(SH.Val);
2217 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
2222 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2223 N1.getOpcode() == ISD::XOR) {
2224 // Simplify X == (X+Z) --> Z == 0
2225 if (N1.getOperand(0) == N0) {
2226 return DAG.getSetCC(VT, N1.getOperand(1),
2227 DAG.getConstant(0, N1.getValueType()), Cond);
2228 } else if (N1.getOperand(1) == N0) {
2229 if (isCommutativeBinOp(N1.getOpcode())) {
2230 return DAG.getSetCC(VT, N1.getOperand(0),
2231 DAG.getConstant(0, N1.getValueType()), Cond);
2233 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2234 // X == (Z-X) --> X<<1 == Z
2235 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
2236 DAG.getConstant(1,TLI.getShiftAmountTy()));
2237 WorkList.push_back(SH.Val);
2238 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
2244 // Fold away ALL boolean setcc's.
2246 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2248 default: assert(0 && "Unknown integer setcc!");
2249 case ISD::SETEQ: // X == Y -> (X^Y)^1
2250 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2251 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
2252 WorkList.push_back(Temp.Val);
2254 case ISD::SETNE: // X != Y --> (X^Y)
2255 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2257 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
2258 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
2259 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2260 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
2261 WorkList.push_back(Temp.Val);
2263 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
2264 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
2265 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2266 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
2267 WorkList.push_back(Temp.Val);
2269 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
2270 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
2271 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2272 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
2273 WorkList.push_back(Temp.Val);
2275 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
2276 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
2277 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2278 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
2281 if (VT != MVT::i1) {
2282 WorkList.push_back(N0.Val);
2283 // FIXME: If running after legalize, we probably can't do this.
2284 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2289 // Could not fold it.
2293 // SelectionDAG::Combine - This is the entry point for the file.
2295 void SelectionDAG::Combine(bool RunningAfterLegalize) {
2296 /// run - This is the main entry point to this class.
2298 DAGCombiner(*this).Run(RunningAfterLegalize);