1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: Should add a corresponding version of fold AND with
20 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
23 // FIXME: select C, pow2, pow2 -> something smart
24 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
25 // FIXME: Dead stores -> nuke
26 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
27 // FIXME: mul (x, const) -> shifts + adds
28 // FIXME: undef values
29 // FIXME: make truncate see through SIGN_EXTEND and AND
30 // FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
31 // FIXME: verify that getNode can't return extends with an operand whose type
32 // is >= to that of the extend.
33 // FIXME: divide by zero is currently left unfolded. do we want to turn this
35 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
36 // FIXME: reassociate (X+C)+Y into (X+Y)+C if the inner expression has one use
38 //===----------------------------------------------------------------------===//
40 #define DEBUG_TYPE "dagcombine"
41 #include "llvm/ADT/Statistic.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Target/TargetLowering.h"
52 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
59 // Worklist of all of the nodes that need to be simplified.
60 std::vector<SDNode*> WorkList;
62 /// AddUsersToWorkList - When an instruction is simplified, add all users of
63 /// the instruction to the work lists because they might get more simplified
66 void AddUsersToWorkList(SDNode *N) {
67 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
69 WorkList.push_back(*UI);
72 /// removeFromWorkList - remove all instances of N from the worklist.
73 void removeFromWorkList(SDNode *N) {
74 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
78 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
80 DEBUG(std::cerr << "\nReplacing "; N->dump();
81 std::cerr << "\nWith: "; To[0].Val->dump();
82 std::cerr << " and " << To.size()-1 << " other values\n");
83 std::vector<SDNode*> NowDead;
84 DAG.ReplaceAllUsesWith(N, To, &NowDead);
86 // Push the new nodes and any users onto the worklist
87 for (unsigned i = 0, e = To.size(); i != e; ++i) {
88 WorkList.push_back(To[i].Val);
89 AddUsersToWorkList(To[i].Val);
92 // Nodes can end up on the worklist more than once. Make sure we do
93 // not process a node that has been replaced.
94 removeFromWorkList(N);
95 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
96 removeFromWorkList(NowDead[i]);
98 // Finally, since the node is now dead, remove it from the graph.
100 return SDOperand(N, 0);
103 SDOperand CombineTo(SDNode *N, SDOperand Res) {
104 std::vector<SDOperand> To;
106 return CombineTo(N, To);
109 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
110 std::vector<SDOperand> To;
113 return CombineTo(N, To);
116 /// visit - call the node-specific routine that knows how to fold each
117 /// particular type of node.
118 SDOperand visit(SDNode *N);
120 // Visitation implementation - Implement dag node combining for different
121 // node types. The semantics are as follows:
123 // SDOperand.Val == 0 - No change was made
124 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
125 // otherwise - N should be replaced by the returned Operand.
127 SDOperand visitTokenFactor(SDNode *N);
128 SDOperand visitADD(SDNode *N);
129 SDOperand visitSUB(SDNode *N);
130 SDOperand visitMUL(SDNode *N);
131 SDOperand visitSDIV(SDNode *N);
132 SDOperand visitUDIV(SDNode *N);
133 SDOperand visitSREM(SDNode *N);
134 SDOperand visitUREM(SDNode *N);
135 SDOperand visitMULHU(SDNode *N);
136 SDOperand visitMULHS(SDNode *N);
137 SDOperand visitAND(SDNode *N);
138 SDOperand visitOR(SDNode *N);
139 SDOperand visitXOR(SDNode *N);
140 SDOperand visitSHL(SDNode *N);
141 SDOperand visitSRA(SDNode *N);
142 SDOperand visitSRL(SDNode *N);
143 SDOperand visitCTLZ(SDNode *N);
144 SDOperand visitCTTZ(SDNode *N);
145 SDOperand visitCTPOP(SDNode *N);
146 SDOperand visitSELECT(SDNode *N);
147 SDOperand visitSELECT_CC(SDNode *N);
148 SDOperand visitSETCC(SDNode *N);
149 SDOperand visitADD_PARTS(SDNode *N);
150 SDOperand visitSUB_PARTS(SDNode *N);
151 SDOperand visitSIGN_EXTEND(SDNode *N);
152 SDOperand visitZERO_EXTEND(SDNode *N);
153 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
154 SDOperand visitTRUNCATE(SDNode *N);
155 SDOperand visitBIT_CONVERT(SDNode *N);
157 SDOperand visitFADD(SDNode *N);
158 SDOperand visitFSUB(SDNode *N);
159 SDOperand visitFMUL(SDNode *N);
160 SDOperand visitFDIV(SDNode *N);
161 SDOperand visitFREM(SDNode *N);
162 SDOperand visitSINT_TO_FP(SDNode *N);
163 SDOperand visitUINT_TO_FP(SDNode *N);
164 SDOperand visitFP_TO_SINT(SDNode *N);
165 SDOperand visitFP_TO_UINT(SDNode *N);
166 SDOperand visitFP_ROUND(SDNode *N);
167 SDOperand visitFP_ROUND_INREG(SDNode *N);
168 SDOperand visitFP_EXTEND(SDNode *N);
169 SDOperand visitFNEG(SDNode *N);
170 SDOperand visitFABS(SDNode *N);
171 SDOperand visitBRCOND(SDNode *N);
172 SDOperand visitBRCONDTWOWAY(SDNode *N);
173 SDOperand visitBR_CC(SDNode *N);
174 SDOperand visitBRTWOWAY_CC(SDNode *N);
176 SDOperand visitLOAD(SDNode *N);
177 SDOperand visitSTORE(SDNode *N);
179 SDOperand visitLOCATION(SDNode *N);
180 SDOperand visitDEBUGLOC(SDNode *N);
182 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
183 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
184 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
185 SDOperand N3, ISD::CondCode CC);
186 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
187 ISD::CondCode Cond, bool foldBooleans = true);
189 SDOperand BuildSDIV(SDNode *N);
190 SDOperand BuildUDIV(SDNode *N);
192 DAGCombiner(SelectionDAG &D)
193 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
195 /// Run - runs the dag combiner on all nodes in the work list
196 void Run(bool RunningAfterLegalize);
201 int64_t m; // magic number
202 int64_t s; // shift amount
206 uint64_t m; // magic number
207 int64_t a; // add indicator
208 int64_t s; // shift amount
211 /// magic - calculate the magic numbers required to codegen an integer sdiv as
212 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
214 static ms magic32(int32_t d) {
216 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
217 const uint32_t two31 = 0x80000000U;
221 t = two31 + ((uint32_t)d >> 31);
222 anc = t - 1 - t%ad; // absolute value of nc
223 p = 31; // initialize p
224 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
225 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
226 q2 = two31/ad; // initialize q2 = 2p/abs(d)
227 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
230 q1 = 2*q1; // update q1 = 2p/abs(nc)
231 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
232 if (r1 >= anc) { // must be unsigned comparison
236 q2 = 2*q2; // update q2 = 2p/abs(d)
237 r2 = 2*r2; // update r2 = rem(2p/abs(d))
238 if (r2 >= ad) { // must be unsigned comparison
243 } while (q1 < delta || (q1 == delta && r1 == 0));
245 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
246 if (d < 0) mag.m = -mag.m; // resulting magic number
247 mag.s = p - 32; // resulting shift
251 /// magicu - calculate the magic numbers required to codegen an integer udiv as
252 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
253 static mu magicu32(uint32_t d) {
255 uint32_t nc, delta, q1, r1, q2, r2;
257 magu.a = 0; // initialize "add" indicator
259 p = 31; // initialize p
260 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
261 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
262 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
263 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
266 if (r1 >= nc - r1 ) {
267 q1 = 2*q1 + 1; // update q1
268 r1 = 2*r1 - nc; // update r1
271 q1 = 2*q1; // update q1
272 r1 = 2*r1; // update r1
274 if (r2 + 1 >= d - r2) {
275 if (q2 >= 0x7FFFFFFF) magu.a = 1;
276 q2 = 2*q2 + 1; // update q2
277 r2 = 2*r2 + 1 - d; // update r2
280 if (q2 >= 0x80000000) magu.a = 1;
281 q2 = 2*q2; // update q2
282 r2 = 2*r2 + 1; // update r2
285 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
286 magu.m = q2 + 1; // resulting magic number
287 magu.s = p - 32; // resulting shift
291 /// magic - calculate the magic numbers required to codegen an integer sdiv as
292 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
294 static ms magic64(int64_t d) {
296 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
297 const uint64_t two63 = 9223372036854775808ULL; // 2^63
300 ad = d >= 0 ? d : -d;
301 t = two63 + ((uint64_t)d >> 63);
302 anc = t - 1 - t%ad; // absolute value of nc
303 p = 63; // initialize p
304 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
305 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
306 q2 = two63/ad; // initialize q2 = 2p/abs(d)
307 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
310 q1 = 2*q1; // update q1 = 2p/abs(nc)
311 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
312 if (r1 >= anc) { // must be unsigned comparison
316 q2 = 2*q2; // update q2 = 2p/abs(d)
317 r2 = 2*r2; // update r2 = rem(2p/abs(d))
318 if (r2 >= ad) { // must be unsigned comparison
323 } while (q1 < delta || (q1 == delta && r1 == 0));
326 if (d < 0) mag.m = -mag.m; // resulting magic number
327 mag.s = p - 64; // resulting shift
331 /// magicu - calculate the magic numbers required to codegen an integer udiv as
332 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
333 static mu magicu64(uint64_t d)
336 uint64_t nc, delta, q1, r1, q2, r2;
338 magu.a = 0; // initialize "add" indicator
340 p = 63; // initialize p
341 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
342 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
343 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
344 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
347 if (r1 >= nc - r1 ) {
348 q1 = 2*q1 + 1; // update q1
349 r1 = 2*r1 - nc; // update r1
352 q1 = 2*q1; // update q1
353 r1 = 2*r1; // update r1
355 if (r2 + 1 >= d - r2) {
356 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
357 q2 = 2*q2 + 1; // update q2
358 r2 = 2*r2 + 1 - d; // update r2
361 if (q2 >= 0x8000000000000000ull) magu.a = 1;
362 q2 = 2*q2; // update q2
363 r2 = 2*r2 + 1; // update r2
366 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
367 magu.m = q2 + 1; // resulting magic number
368 magu.s = p - 64; // resulting shift
372 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use
373 /// this predicate to simplify operations downstream. Op and Mask are known to
374 /// be the same type.
375 static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
376 const TargetLowering &TLI) {
378 if (Mask == 0) return true;
380 // If we know the result of a setcc has the top bits zero, use this info.
381 switch (Op.getOpcode()) {
383 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
385 return ((Mask & 1) == 0) &&
386 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
388 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
389 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
390 case ISD::ZERO_EXTEND:
391 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
392 return MaskedValueIsZero(Op.getOperand(0),Mask & (~0ULL >> (64-SrcBits)),TLI);
393 case ISD::AssertZext:
394 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
395 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
397 // If either of the operands has zero bits, the result will too.
398 if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) ||
399 MaskedValueIsZero(Op.getOperand(0), Mask, TLI))
401 // (X & C1) & C2 == 0 iff C1 & C2 == 0.
402 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
403 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
407 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
408 MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
410 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
411 MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
413 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
414 MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
416 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
417 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
418 uint64_t NewVal = Mask << ShAmt->getValue();
419 SrcBits = MVT::getSizeInBits(Op.getValueType());
420 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
421 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
425 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
426 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
427 uint64_t NewVal = Mask >> ShAmt->getValue();
428 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
432 // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits.
433 if ((Mask&(Mask+1)) == 0) { // All low bits
434 if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
435 MaskedValueIsZero(Op.getOperand(1), Mask, TLI))
440 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
441 // We know that the top bits of C-X are clear if X contains less bits
442 // than C (i.e. no wrap-around can happen). For example, 20-X is
443 // positive if we can prove that X is >= 0 and < 16.
444 unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0));
445 if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear
446 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
447 uint64_t MaskV = (1ULL << (63-NLZ))-1;
448 if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) {
449 // High bits are clear this value is known to be >= C.
450 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
451 if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0)
460 // Bit counting instructions can not set the high bits of the result
461 // register. The max number of bits sets depends on the input.
462 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
464 if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
465 return TLI.isMaskedValueZeroForTargetNode(Op, Mask);
471 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
472 // that selects between the values 1 and 0, making it equivalent to a setcc.
473 // Also, set the incoming LHS, RHS, and CC references to the appropriate
474 // nodes based on the type of node we are checking. This simplifies life a
475 // bit for the callers.
476 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
478 if (N.getOpcode() == ISD::SETCC) {
479 LHS = N.getOperand(0);
480 RHS = N.getOperand(1);
481 CC = N.getOperand(2);
484 if (N.getOpcode() == ISD::SELECT_CC &&
485 N.getOperand(2).getOpcode() == ISD::Constant &&
486 N.getOperand(3).getOpcode() == ISD::Constant &&
487 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
488 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
489 LHS = N.getOperand(0);
490 RHS = N.getOperand(1);
491 CC = N.getOperand(4);
497 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
498 // one use. If this is true, it allows the users to invert the operation for
499 // free when it is profitable to do so.
500 static bool isOneUseSetCC(SDOperand N) {
501 SDOperand N0, N1, N2;
502 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
507 // FIXME: This should probably go in the ISD class rather than being duplicated
509 static bool isCommutativeBinOp(unsigned Opcode) {
515 case ISD::XOR: return true;
516 default: return false; // FIXME: Need commutative info for user ops!
520 void DAGCombiner::Run(bool RunningAfterLegalize) {
521 // set the instance variable, so that the various visit routines may use it.
522 AfterLegalize = RunningAfterLegalize;
524 // Add all the dag nodes to the worklist.
525 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
526 E = DAG.allnodes_end(); I != E; ++I)
527 WorkList.push_back(I);
529 // Create a dummy node (which is not added to allnodes), that adds a reference
530 // to the root node, preventing it from being deleted, and tracking any
531 // changes of the root.
532 HandleSDNode Dummy(DAG.getRoot());
534 // while the worklist isn't empty, inspect the node on the end of it and
535 // try and combine it.
536 while (!WorkList.empty()) {
537 SDNode *N = WorkList.back();
540 // If N has no uses, it is dead. Make sure to revisit all N's operands once
541 // N is deleted from the DAG, since they too may now be dead or may have a
542 // reduced number of uses, allowing other xforms.
543 if (N->use_empty() && N != &Dummy) {
544 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
545 WorkList.push_back(N->getOperand(i).Val);
547 removeFromWorkList(N);
552 SDOperand RV = visit(N);
555 // If we get back the same node we passed in, rather than a new node or
556 // zero, we know that the node must have defined multiple values and
557 // CombineTo was used. Since CombineTo takes care of the worklist
558 // mechanics for us, we have no work to do in this case.
560 DEBUG(std::cerr << "\nReplacing "; N->dump();
561 std::cerr << "\nWith: "; RV.Val->dump();
563 std::vector<SDNode*> NowDead;
564 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
566 // Push the new node and any users onto the worklist
567 WorkList.push_back(RV.Val);
568 AddUsersToWorkList(RV.Val);
570 // Nodes can end up on the worklist more than once. Make sure we do
571 // not process a node that has been replaced.
572 removeFromWorkList(N);
573 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
574 removeFromWorkList(NowDead[i]);
576 // Finally, since the node is now dead, remove it from the graph.
582 // If the root changed (e.g. it was a dead load, update the root).
583 DAG.setRoot(Dummy.getValue());
586 SDOperand DAGCombiner::visit(SDNode *N) {
587 switch(N->getOpcode()) {
589 case ISD::TokenFactor: return visitTokenFactor(N);
590 case ISD::ADD: return visitADD(N);
591 case ISD::SUB: return visitSUB(N);
592 case ISD::MUL: return visitMUL(N);
593 case ISD::SDIV: return visitSDIV(N);
594 case ISD::UDIV: return visitUDIV(N);
595 case ISD::SREM: return visitSREM(N);
596 case ISD::UREM: return visitUREM(N);
597 case ISD::MULHU: return visitMULHU(N);
598 case ISD::MULHS: return visitMULHS(N);
599 case ISD::AND: return visitAND(N);
600 case ISD::OR: return visitOR(N);
601 case ISD::XOR: return visitXOR(N);
602 case ISD::SHL: return visitSHL(N);
603 case ISD::SRA: return visitSRA(N);
604 case ISD::SRL: return visitSRL(N);
605 case ISD::CTLZ: return visitCTLZ(N);
606 case ISD::CTTZ: return visitCTTZ(N);
607 case ISD::CTPOP: return visitCTPOP(N);
608 case ISD::SELECT: return visitSELECT(N);
609 case ISD::SELECT_CC: return visitSELECT_CC(N);
610 case ISD::SETCC: return visitSETCC(N);
611 case ISD::ADD_PARTS: return visitADD_PARTS(N);
612 case ISD::SUB_PARTS: return visitSUB_PARTS(N);
613 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
614 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
615 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
616 case ISD::TRUNCATE: return visitTRUNCATE(N);
617 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
618 case ISD::FADD: return visitFADD(N);
619 case ISD::FSUB: return visitFSUB(N);
620 case ISD::FMUL: return visitFMUL(N);
621 case ISD::FDIV: return visitFDIV(N);
622 case ISD::FREM: return visitFREM(N);
623 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
624 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
625 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
626 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
627 case ISD::FP_ROUND: return visitFP_ROUND(N);
628 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
629 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
630 case ISD::FNEG: return visitFNEG(N);
631 case ISD::FABS: return visitFABS(N);
632 case ISD::BRCOND: return visitBRCOND(N);
633 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
634 case ISD::BR_CC: return visitBR_CC(N);
635 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
636 case ISD::LOAD: return visitLOAD(N);
637 case ISD::STORE: return visitSTORE(N);
638 case ISD::LOCATION: return visitLOCATION(N);
639 case ISD::DEBUG_LOC: return visitDEBUGLOC(N);
644 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
645 std::vector<SDOperand> Ops;
646 bool Changed = false;
648 // If the token factor has two operands and one is the entry token, replace
649 // the token factor with the other operand.
650 if (N->getNumOperands() == 2) {
651 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
652 return N->getOperand(1);
653 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
654 return N->getOperand(0);
657 // fold (tokenfactor (tokenfactor)) -> tokenfactor
658 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
659 SDOperand Op = N->getOperand(i);
660 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
662 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
663 Ops.push_back(Op.getOperand(j));
669 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
673 SDOperand DAGCombiner::visitADD(SDNode *N) {
674 SDOperand N0 = N->getOperand(0);
675 SDOperand N1 = N->getOperand(1);
676 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
677 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
678 MVT::ValueType VT = N0.getValueType();
680 // fold (add c1, c2) -> c1+c2
682 return DAG.getNode(ISD::ADD, VT, N0, N1);
683 // canonicalize constant to RHS
685 return DAG.getNode(ISD::ADD, VT, N1, N0);
686 // fold (add x, 0) -> x
687 if (N1C && N1C->isNullValue())
689 // fold (add (add x, c1), c2) -> (add x, c1+c2)
690 if (N1C && N0.getOpcode() == ISD::ADD) {
691 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
692 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
694 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1),
695 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT));
697 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0),
698 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT));
701 // fold ((c1-A)+c2) -> (c1+c2)-A
702 if (N1C && N0.getOpcode() == ISD::SUB)
703 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
704 return DAG.getNode(ISD::SUB, VT,
705 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
708 // fold ((0-A) + B) -> B-A
709 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
710 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
711 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
712 // fold (A + (0-B)) -> A-B
713 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
714 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
715 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
716 // fold (A+(B-A)) -> B
717 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
718 return N1.getOperand(0);
722 SDOperand DAGCombiner::visitSUB(SDNode *N) {
723 SDOperand N0 = N->getOperand(0);
724 SDOperand N1 = N->getOperand(1);
725 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
726 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
727 MVT::ValueType VT = N0.getValueType();
729 // fold (sub x, x) -> 0
731 return DAG.getConstant(0, N->getValueType(0));
732 // fold (sub c1, c2) -> c1-c2
734 return DAG.getNode(ISD::SUB, VT, N0, N1);
735 // fold (sub x, c) -> (add x, -c)
737 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
739 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
740 return N0.getOperand(1);
742 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
743 return N0.getOperand(0);
747 SDOperand DAGCombiner::visitMUL(SDNode *N) {
748 SDOperand N0 = N->getOperand(0);
749 SDOperand N1 = N->getOperand(1);
750 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
751 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
752 MVT::ValueType VT = N0.getValueType();
754 // fold (mul c1, c2) -> c1*c2
756 return DAG.getNode(ISD::MUL, VT, N0, N1);
757 // canonicalize constant to RHS
759 return DAG.getNode(ISD::MUL, VT, N1, N0);
760 // fold (mul x, 0) -> 0
761 if (N1C && N1C->isNullValue())
763 // fold (mul x, -1) -> 0-x
764 if (N1C && N1C->isAllOnesValue())
765 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
766 // fold (mul x, (1 << c)) -> x << c
767 if (N1C && isPowerOf2_64(N1C->getValue()))
768 return DAG.getNode(ISD::SHL, VT, N0,
769 DAG.getConstant(Log2_64(N1C->getValue()),
770 TLI.getShiftAmountTy()));
771 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
772 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
773 // FIXME: If the input is something that is easily negated (e.g. a
774 // single-use add), we should put the negate there.
775 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
776 DAG.getNode(ISD::SHL, VT, N0,
777 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
778 TLI.getShiftAmountTy())));
782 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2)
783 if (N1C && N0.getOpcode() == ISD::MUL) {
784 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
785 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
787 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1),
788 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT));
790 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0),
791 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT));
796 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
797 SDOperand N0 = N->getOperand(0);
798 SDOperand N1 = N->getOperand(1);
799 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
800 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
801 MVT::ValueType VT = N->getValueType(0);
803 // fold (sdiv c1, c2) -> c1/c2
804 if (N0C && N1C && !N1C->isNullValue())
805 return DAG.getNode(ISD::SDIV, VT, N0, N1);
806 // fold (sdiv X, 1) -> X
807 if (N1C && N1C->getSignExtended() == 1LL)
809 // fold (sdiv X, -1) -> 0-X
810 if (N1C && N1C->isAllOnesValue())
811 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
812 // If we know the sign bits of both operands are zero, strength reduce to a
813 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
814 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
815 if (MaskedValueIsZero(N1, SignBit, TLI) &&
816 MaskedValueIsZero(N0, SignBit, TLI))
817 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
818 // fold (sdiv X, pow2) -> (add (sra X, log(pow2)), (srl X, sizeof(X)-1))
819 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
820 (isPowerOf2_64(N1C->getSignExtended()) ||
821 isPowerOf2_64(-N1C->getSignExtended()))) {
822 // If dividing by powers of two is cheap, then don't perform the following
824 if (TLI.isPow2DivCheap())
826 int64_t pow2 = N1C->getSignExtended();
827 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
828 SDOperand SRL = DAG.getNode(ISD::SRL, VT, N0,
829 DAG.getConstant(MVT::getSizeInBits(VT)-1,
830 TLI.getShiftAmountTy()));
831 WorkList.push_back(SRL.Val);
832 SDOperand SGN = DAG.getNode(ISD::ADD, VT, N0, SRL);
833 WorkList.push_back(SGN.Val);
834 SDOperand SRA = DAG.getNode(ISD::SRA, VT, SGN,
835 DAG.getConstant(Log2_64(abs2),
836 TLI.getShiftAmountTy()));
837 // If we're dividing by a positive value, we're done. Otherwise, we must
838 // negate the result.
841 WorkList.push_back(SRA.Val);
842 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
844 // if integer divide is expensive and we satisfy the requirements, emit an
845 // alternate sequence.
846 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
847 !TLI.isIntDivCheap()) {
848 SDOperand Op = BuildSDIV(N);
849 if (Op.Val) return Op;
854 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
855 SDOperand N0 = N->getOperand(0);
856 SDOperand N1 = N->getOperand(1);
857 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
858 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
859 MVT::ValueType VT = N->getValueType(0);
861 // fold (udiv c1, c2) -> c1/c2
862 if (N0C && N1C && !N1C->isNullValue())
863 return DAG.getNode(ISD::UDIV, VT, N0, N1);
864 // fold (udiv x, (1 << c)) -> x >>u c
865 if (N1C && isPowerOf2_64(N1C->getValue()))
866 return DAG.getNode(ISD::SRL, N->getValueType(0), N0,
867 DAG.getConstant(Log2_64(N1C->getValue()),
868 TLI.getShiftAmountTy()));
869 // fold (udiv x, c) -> alternate
870 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
871 SDOperand Op = BuildUDIV(N);
872 if (Op.Val) return Op;
878 SDOperand DAGCombiner::visitSREM(SDNode *N) {
879 SDOperand N0 = N->getOperand(0);
880 SDOperand N1 = N->getOperand(1);
881 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
882 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
883 MVT::ValueType VT = N->getValueType(0);
885 // fold (srem c1, c2) -> c1%c2
886 if (N0C && N1C && !N1C->isNullValue())
887 return DAG.getNode(ISD::SREM, VT, N0, N1);
888 // If we know the sign bits of both operands are zero, strength reduce to a
889 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
890 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
891 if (MaskedValueIsZero(N1, SignBit, TLI) &&
892 MaskedValueIsZero(N0, SignBit, TLI))
893 return DAG.getNode(ISD::UREM, VT, N0, N1);
897 SDOperand DAGCombiner::visitUREM(SDNode *N) {
898 SDOperand N0 = N->getOperand(0);
899 SDOperand N1 = N->getOperand(1);
900 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
901 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
902 MVT::ValueType VT = N->getValueType(0);
904 // fold (urem c1, c2) -> c1%c2
905 if (N0C && N1C && !N1C->isNullValue())
906 return DAG.getNode(ISD::UREM, VT, N0, N1);
907 // fold (urem x, pow2) -> (and x, pow2-1)
908 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
909 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
913 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
914 SDOperand N0 = N->getOperand(0);
915 SDOperand N1 = N->getOperand(1);
916 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
918 // fold (mulhs x, 0) -> 0
919 if (N1C && N1C->isNullValue())
921 // fold (mulhs x, 1) -> (sra x, size(x)-1)
922 if (N1C && N1C->getValue() == 1)
923 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
924 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
925 TLI.getShiftAmountTy()));
929 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
930 SDOperand N0 = N->getOperand(0);
931 SDOperand N1 = N->getOperand(1);
932 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
934 // fold (mulhu x, 0) -> 0
935 if (N1C && N1C->isNullValue())
937 // fold (mulhu x, 1) -> 0
938 if (N1C && N1C->getValue() == 1)
939 return DAG.getConstant(0, N0.getValueType());
943 SDOperand DAGCombiner::visitAND(SDNode *N) {
944 SDOperand N0 = N->getOperand(0);
945 SDOperand N1 = N->getOperand(1);
946 SDOperand LL, LR, RL, RR, CC0, CC1;
947 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
948 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
949 MVT::ValueType VT = N1.getValueType();
950 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
952 // fold (and c1, c2) -> c1&c2
954 return DAG.getNode(ISD::AND, VT, N0, N1);
955 // canonicalize constant to RHS
957 return DAG.getNode(ISD::AND, VT, N1, N0);
958 // fold (and x, -1) -> x
959 if (N1C && N1C->isAllOnesValue())
961 // if (and x, c) is known to be zero, return 0
962 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
963 return DAG.getConstant(0, VT);
964 // fold (and x, c) -> x iff (x & ~c) == 0
965 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
968 // fold (and (and x, c1), c2) -> (and x, c1^c2)
969 if (N1C && N0.getOpcode() == ISD::AND) {
970 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
971 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
973 return DAG.getNode(ISD::AND, VT, N0.getOperand(1),
974 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT));
976 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
977 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT));
979 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
980 if (N1C && N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
981 unsigned ExtendBits =
982 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
983 if (ExtendBits == 64 || ((N1C->getValue() & (~0ULL << ExtendBits)) == 0))
984 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
986 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
987 if (N1C && N0.getOpcode() == ISD::OR)
988 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
989 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
991 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
992 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
993 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
994 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
996 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
997 MVT::isInteger(LL.getValueType())) {
998 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
999 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1000 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1001 WorkList.push_back(ORNode.Val);
1002 return DAG.getSetCC(VT, ORNode, LR, Op1);
1004 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1005 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1006 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1007 WorkList.push_back(ANDNode.Val);
1008 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1010 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1011 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1012 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1013 WorkList.push_back(ORNode.Val);
1014 return DAG.getSetCC(VT, ORNode, LR, Op1);
1017 // canonicalize equivalent to ll == rl
1018 if (LL == RR && LR == RL) {
1019 Op1 = ISD::getSetCCSwappedOperands(Op1);
1022 if (LL == RL && LR == RR) {
1023 bool isInteger = MVT::isInteger(LL.getValueType());
1024 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1025 if (Result != ISD::SETCC_INVALID)
1026 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1029 // fold (and (zext x), (zext y)) -> (zext (and x, y))
1030 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1031 N1.getOpcode() == ISD::ZERO_EXTEND &&
1032 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1033 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
1034 N0.getOperand(0), N1.getOperand(0));
1035 WorkList.push_back(ANDNode.Val);
1036 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
1038 // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y))
1039 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1040 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
1041 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
1042 N0.getOperand(1) == N1.getOperand(1)) {
1043 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
1044 N0.getOperand(0), N1.getOperand(0));
1045 WorkList.push_back(ANDNode.Val);
1046 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
1048 // fold (and (sra)) -> (and (srl)) when possible.
1049 if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse()) {
1050 if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1051 // If the RHS of the AND has zeros where the sign bits of the SRA will
1052 // land, turn the SRA into an SRL.
1053 if (MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) &
1054 (~0ULL>>(64-OpSizeInBits)), TLI)) {
1055 WorkList.push_back(N);
1056 CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1062 // fold (zext_inreg (extload x)) -> (zextload x)
1063 if (N0.getOpcode() == ISD::EXTLOAD) {
1064 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1065 // If we zero all the possible extended bits, then we can turn this into
1066 // a zextload if we are running before legalize or the operation is legal.
1067 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) &&
1068 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1069 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1070 N0.getOperand(1), N0.getOperand(2),
1072 WorkList.push_back(N);
1073 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1077 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1078 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) {
1079 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1080 // If we zero all the possible extended bits, then we can turn this into
1081 // a zextload if we are running before legalize or the operation is legal.
1082 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) &&
1083 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1084 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1085 N0.getOperand(1), N0.getOperand(2),
1087 WorkList.push_back(N);
1088 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1095 SDOperand DAGCombiner::visitOR(SDNode *N) {
1096 SDOperand N0 = N->getOperand(0);
1097 SDOperand N1 = N->getOperand(1);
1098 SDOperand LL, LR, RL, RR, CC0, CC1;
1099 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1100 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1101 MVT::ValueType VT = N1.getValueType();
1102 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1104 // fold (or c1, c2) -> c1|c2
1106 return DAG.getNode(ISD::OR, VT, N0, N1);
1107 // canonicalize constant to RHS
1109 return DAG.getNode(ISD::OR, VT, N1, N0);
1110 // fold (or x, 0) -> x
1111 if (N1C && N1C->isNullValue())
1113 // fold (or x, -1) -> -1
1114 if (N1C && N1C->isAllOnesValue())
1116 // fold (or x, c) -> c iff (x & ~c) == 0
1117 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
1120 // fold (or (or x, c1), c2) -> (or x, c1|c2)
1121 if (N1C && N0.getOpcode() == ISD::OR) {
1122 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1123 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1125 return DAG.getNode(ISD::OR, VT, N0.getOperand(1),
1126 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT));
1128 return DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1129 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT));
1130 } else if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1131 isa<ConstantSDNode>(N0.getOperand(1))) {
1132 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1133 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1134 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1136 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1138 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1139 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1140 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1141 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1143 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1144 MVT::isInteger(LL.getValueType())) {
1145 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1146 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1147 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1148 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1149 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1150 WorkList.push_back(ORNode.Val);
1151 return DAG.getSetCC(VT, ORNode, LR, Op1);
1153 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1154 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1155 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1156 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1157 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1158 WorkList.push_back(ANDNode.Val);
1159 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1162 // canonicalize equivalent to ll == rl
1163 if (LL == RR && LR == RL) {
1164 Op1 = ISD::getSetCCSwappedOperands(Op1);
1167 if (LL == RL && LR == RR) {
1168 bool isInteger = MVT::isInteger(LL.getValueType());
1169 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1170 if (Result != ISD::SETCC_INVALID)
1171 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1174 // fold (or (zext x), (zext y)) -> (zext (or x, y))
1175 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1176 N1.getOpcode() == ISD::ZERO_EXTEND &&
1177 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1178 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
1179 N0.getOperand(0), N1.getOperand(0));
1180 WorkList.push_back(ORNode.Val);
1181 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
1183 // canonicalize shl to left side in a shl/srl pair, to match rotate
1184 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
1186 // check for rotl, rotr
1187 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
1188 N0.getOperand(0) == N1.getOperand(0) &&
1189 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) {
1190 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1191 if (N0.getOperand(1).getOpcode() == ISD::Constant &&
1192 N1.getOperand(1).getOpcode() == ISD::Constant) {
1193 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1194 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1195 if ((c1val + c2val) == OpSizeInBits)
1196 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1198 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1199 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
1200 N0.getOperand(1) == N1.getOperand(1).getOperand(1))
1201 if (ConstantSDNode *SUBC =
1202 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0)))
1203 if (SUBC->getValue() == OpSizeInBits)
1204 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1205 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1206 if (N0.getOperand(1).getOpcode() == ISD::SUB &&
1207 N1.getOperand(1) == N0.getOperand(1).getOperand(1))
1208 if (ConstantSDNode *SUBC =
1209 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
1210 if (SUBC->getValue() == OpSizeInBits) {
1211 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT))
1212 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
1215 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
1222 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1223 SDOperand N0 = N->getOperand(0);
1224 SDOperand N1 = N->getOperand(1);
1225 SDOperand LHS, RHS, CC;
1226 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1227 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1228 MVT::ValueType VT = N0.getValueType();
1230 // fold (xor c1, c2) -> c1^c2
1232 return DAG.getNode(ISD::XOR, VT, N0, N1);
1233 // canonicalize constant to RHS
1235 return DAG.getNode(ISD::XOR, VT, N1, N0);
1236 // fold (xor x, 0) -> x
1237 if (N1C && N1C->isNullValue())
1239 // fold !(x cc y) -> (x !cc y)
1240 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1241 bool isInt = MVT::isInteger(LHS.getValueType());
1242 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1244 if (N0.getOpcode() == ISD::SETCC)
1245 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1246 if (N0.getOpcode() == ISD::SELECT_CC)
1247 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1248 assert(0 && "Unhandled SetCC Equivalent!");
1251 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1252 if (N1C && N1C->getValue() == 1 &&
1253 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1254 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1255 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1256 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1257 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1258 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1259 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
1260 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1263 // fold !(x or y) -> (!x and !y) iff x or y are constants
1264 if (N1C && N1C->isAllOnesValue() &&
1265 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1266 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1267 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1268 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1269 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1270 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1271 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
1272 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1275 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1276 if (N1C && N0.getOpcode() == ISD::XOR) {
1277 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1278 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1280 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1281 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1283 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1284 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1286 // fold (xor x, x) -> 0
1288 return DAG.getConstant(0, VT);
1289 // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
1290 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1291 N1.getOpcode() == ISD::ZERO_EXTEND &&
1292 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1293 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1294 N0.getOperand(0), N1.getOperand(0));
1295 WorkList.push_back(XORNode.Val);
1296 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
1301 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1302 SDOperand N0 = N->getOperand(0);
1303 SDOperand N1 = N->getOperand(1);
1304 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1305 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1306 MVT::ValueType VT = N0.getValueType();
1307 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1309 // fold (shl c1, c2) -> c1<<c2
1311 return DAG.getNode(ISD::SHL, VT, N0, N1);
1312 // fold (shl 0, x) -> 0
1313 if (N0C && N0C->isNullValue())
1315 // fold (shl x, c >= size(x)) -> undef
1316 if (N1C && N1C->getValue() >= OpSizeInBits)
1317 return DAG.getNode(ISD::UNDEF, VT);
1318 // fold (shl x, 0) -> x
1319 if (N1C && N1C->isNullValue())
1321 // if (shl x, c) is known to be zero, return 0
1322 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
1323 return DAG.getConstant(0, VT);
1324 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1325 if (N1C && N0.getOpcode() == ISD::SHL &&
1326 N0.getOperand(1).getOpcode() == ISD::Constant) {
1327 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1328 uint64_t c2 = N1C->getValue();
1329 if (c1 + c2 > OpSizeInBits)
1330 return DAG.getConstant(0, VT);
1331 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1332 DAG.getConstant(c1 + c2, N1.getValueType()));
1334 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1335 // (srl (and x, -1 << c1), c1-c2)
1336 if (N1C && N0.getOpcode() == ISD::SRL &&
1337 N0.getOperand(1).getOpcode() == ISD::Constant) {
1338 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1339 uint64_t c2 = N1C->getValue();
1340 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1341 DAG.getConstant(~0ULL << c1, VT));
1343 return DAG.getNode(ISD::SHL, VT, Mask,
1344 DAG.getConstant(c2-c1, N1.getValueType()));
1346 return DAG.getNode(ISD::SRL, VT, Mask,
1347 DAG.getConstant(c1-c2, N1.getValueType()));
1349 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1350 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1351 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1352 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1356 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1357 SDOperand N0 = N->getOperand(0);
1358 SDOperand N1 = N->getOperand(1);
1359 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1360 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1361 MVT::ValueType VT = N0.getValueType();
1362 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1364 // fold (sra c1, c2) -> c1>>c2
1366 return DAG.getNode(ISD::SRA, VT, N0, N1);
1367 // fold (sra 0, x) -> 0
1368 if (N0C && N0C->isNullValue())
1370 // fold (sra -1, x) -> -1
1371 if (N0C && N0C->isAllOnesValue())
1373 // fold (sra x, c >= size(x)) -> undef
1374 if (N1C && N1C->getValue() >= OpSizeInBits)
1375 return DAG.getNode(ISD::UNDEF, VT);
1376 // fold (sra x, 0) -> x
1377 if (N1C && N1C->isNullValue())
1379 // If the sign bit is known to be zero, switch this to a SRL.
1380 if (MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI))
1381 return DAG.getNode(ISD::SRL, VT, N0, N1);
1385 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1386 SDOperand N0 = N->getOperand(0);
1387 SDOperand N1 = N->getOperand(1);
1388 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1389 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1390 MVT::ValueType VT = N0.getValueType();
1391 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1393 // fold (srl c1, c2) -> c1 >>u c2
1395 return DAG.getNode(ISD::SRL, VT, N0, N1);
1396 // fold (srl 0, x) -> 0
1397 if (N0C && N0C->isNullValue())
1399 // fold (srl x, c >= size(x)) -> undef
1400 if (N1C && N1C->getValue() >= OpSizeInBits)
1401 return DAG.getNode(ISD::UNDEF, VT);
1402 // fold (srl x, 0) -> x
1403 if (N1C && N1C->isNullValue())
1405 // if (srl x, c) is known to be zero, return 0
1406 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
1407 return DAG.getConstant(0, VT);
1408 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1409 if (N1C && N0.getOpcode() == ISD::SRL &&
1410 N0.getOperand(1).getOpcode() == ISD::Constant) {
1411 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1412 uint64_t c2 = N1C->getValue();
1413 if (c1 + c2 > OpSizeInBits)
1414 return DAG.getConstant(0, VT);
1415 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1416 DAG.getConstant(c1 + c2, N1.getValueType()));
1421 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1422 SDOperand N0 = N->getOperand(0);
1423 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1424 MVT::ValueType VT = N->getValueType(0);
1426 // fold (ctlz c1) -> c2
1428 return DAG.getNode(ISD::CTLZ, VT, N0);
1432 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1433 SDOperand N0 = N->getOperand(0);
1434 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1435 MVT::ValueType VT = N->getValueType(0);
1437 // fold (cttz c1) -> c2
1439 return DAG.getNode(ISD::CTTZ, VT, N0);
1443 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1444 SDOperand N0 = N->getOperand(0);
1445 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1446 MVT::ValueType VT = N->getValueType(0);
1448 // fold (ctpop c1) -> c2
1450 return DAG.getNode(ISD::CTPOP, VT, N0);
1454 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1455 SDOperand N0 = N->getOperand(0);
1456 SDOperand N1 = N->getOperand(1);
1457 SDOperand N2 = N->getOperand(2);
1458 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1459 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1460 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1461 MVT::ValueType VT = N->getValueType(0);
1463 // fold select C, X, X -> X
1466 // fold select true, X, Y -> X
1467 if (N0C && !N0C->isNullValue())
1469 // fold select false, X, Y -> Y
1470 if (N0C && N0C->isNullValue())
1472 // fold select C, 1, X -> C | X
1473 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1474 return DAG.getNode(ISD::OR, VT, N0, N2);
1475 // fold select C, 0, X -> ~C & X
1476 // FIXME: this should check for C type == X type, not i1?
1477 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1478 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1479 WorkList.push_back(XORNode.Val);
1480 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1482 // fold select C, X, 1 -> ~C | X
1483 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1484 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1485 WorkList.push_back(XORNode.Val);
1486 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1488 // fold select C, X, 0 -> C & X
1489 // FIXME: this should check for C type == X type, not i1?
1490 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1491 return DAG.getNode(ISD::AND, VT, N0, N1);
1492 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1493 if (MVT::i1 == VT && N0 == N1)
1494 return DAG.getNode(ISD::OR, VT, N0, N2);
1495 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1496 if (MVT::i1 == VT && N0 == N2)
1497 return DAG.getNode(ISD::AND, VT, N0, N1);
1499 // If we can fold this based on the true/false value, do so.
1500 if (SimplifySelectOps(N, N1, N2))
1503 // fold selects based on a setcc into other things, such as min/max/abs
1504 if (N0.getOpcode() == ISD::SETCC)
1505 return SimplifySelect(N0, N1, N2);
1509 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1510 SDOperand N0 = N->getOperand(0);
1511 SDOperand N1 = N->getOperand(1);
1512 SDOperand N2 = N->getOperand(2);
1513 SDOperand N3 = N->getOperand(3);
1514 SDOperand N4 = N->getOperand(4);
1515 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1516 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1517 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1518 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1520 // Determine if the condition we're dealing with is constant
1521 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1522 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1524 // fold select_cc lhs, rhs, x, x, cc -> x
1528 // If we can fold this based on the true/false value, do so.
1529 if (SimplifySelectOps(N, N2, N3))
1532 // fold select_cc into other things, such as min/max/abs
1533 return SimplifySelectCC(N0, N1, N2, N3, CC);
1536 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1537 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1538 cast<CondCodeSDNode>(N->getOperand(2))->get());
1541 SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) {
1542 SDOperand LHSLo = N->getOperand(0);
1543 SDOperand RHSLo = N->getOperand(2);
1544 MVT::ValueType VT = LHSLo.getValueType();
1546 // fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo)
1547 if (MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1548 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
1550 WorkList.push_back(Hi.Val);
1551 CombineTo(N, RHSLo, Hi);
1554 // fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo)
1555 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1556 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
1558 WorkList.push_back(Hi.Val);
1559 CombineTo(N, LHSLo, Hi);
1565 SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) {
1566 SDOperand LHSLo = N->getOperand(0);
1567 SDOperand RHSLo = N->getOperand(2);
1568 MVT::ValueType VT = LHSLo.getValueType();
1570 // fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo)
1571 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1572 SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1),
1574 WorkList.push_back(Hi.Val);
1575 CombineTo(N, LHSLo, Hi);
1581 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1582 SDOperand N0 = N->getOperand(0);
1583 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1584 MVT::ValueType VT = N->getValueType(0);
1586 // fold (sext c1) -> c1
1588 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1589 // fold (sext (sext x)) -> (sext x)
1590 if (N0.getOpcode() == ISD::SIGN_EXTEND)
1591 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1592 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
1593 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1595 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())))
1596 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1597 DAG.getValueType(N0.getValueType()));
1598 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1599 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1600 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){
1601 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1602 N0.getOperand(1), N0.getOperand(2),
1604 CombineTo(N, ExtLoad);
1605 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1606 ExtLoad.getValue(1));
1610 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1611 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1612 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1614 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0),
1615 N0.getOperand(1), N0.getOperand(2),
1617 CombineTo(N, ExtLoad);
1618 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1619 ExtLoad.getValue(1));
1626 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1627 SDOperand N0 = N->getOperand(0);
1628 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1629 MVT::ValueType VT = N->getValueType(0);
1631 // fold (zext c1) -> c1
1633 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1634 // fold (zext (zext x)) -> (zext x)
1635 if (N0.getOpcode() == ISD::ZERO_EXTEND)
1636 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1637 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size.
1638 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1639 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType())))
1640 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType());
1641 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1642 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1643 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){
1644 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1645 N0.getOperand(1), N0.getOperand(2),
1647 CombineTo(N, ExtLoad);
1648 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1649 ExtLoad.getValue(1));
1653 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1654 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1655 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1657 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1658 N0.getOperand(1), N0.getOperand(2),
1660 CombineTo(N, ExtLoad);
1661 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1662 ExtLoad.getValue(1));
1668 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1669 SDOperand N0 = N->getOperand(0);
1670 SDOperand N1 = N->getOperand(1);
1671 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1672 MVT::ValueType VT = N->getValueType(0);
1673 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1674 unsigned EVTBits = MVT::getSizeInBits(EVT);
1676 // fold (sext_in_reg c1) -> c1
1678 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1679 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1681 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1682 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1683 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1686 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1687 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1688 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1689 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1691 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1692 if (N0.getOpcode() == ISD::AssertSext &&
1693 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1696 // fold (sext_in_reg (sextload x)) -> (sextload x)
1697 if (N0.getOpcode() == ISD::SEXTLOAD &&
1698 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1701 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1702 if (N0.getOpcode() == ISD::SETCC &&
1703 TLI.getSetCCResultContents() ==
1704 TargetLowering::ZeroOrNegativeOneSetCCResult)
1706 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1707 if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI))
1708 return DAG.getNode(ISD::AND, N0.getValueType(), N0,
1709 DAG.getConstant(~0ULL >> (64-EVTBits), VT));
1710 // fold (sext_in_reg (srl x)) -> sra x
1711 if (N0.getOpcode() == ISD::SRL &&
1712 N0.getOperand(1).getOpcode() == ISD::Constant &&
1713 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
1714 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
1717 // fold (sext_inreg (extload x)) -> (sextload x)
1718 if (N0.getOpcode() == ISD::EXTLOAD &&
1719 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1720 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1721 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1722 N0.getOperand(1), N0.getOperand(2),
1724 CombineTo(N, ExtLoad);
1725 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1728 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1729 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
1730 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1731 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1732 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1733 N0.getOperand(1), N0.getOperand(2),
1735 CombineTo(N, ExtLoad);
1736 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1742 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1743 SDOperand N0 = N->getOperand(0);
1744 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1745 MVT::ValueType VT = N->getValueType(0);
1748 if (N0.getValueType() == N->getValueType(0))
1750 // fold (truncate c1) -> c1
1752 return DAG.getNode(ISD::TRUNCATE, VT, N0);
1753 // fold (truncate (truncate x)) -> (truncate x)
1754 if (N0.getOpcode() == ISD::TRUNCATE)
1755 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1756 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1757 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
1758 if (N0.getValueType() < VT)
1759 // if the source is smaller than the dest, we still need an extend
1760 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1761 else if (N0.getValueType() > VT)
1762 // if the source is larger than the dest, than we just need the truncate
1763 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1765 // if the source and dest are the same type, we can drop both the extend
1767 return N0.getOperand(0);
1769 // fold (truncate (load x)) -> (smaller load x)
1770 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1771 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
1772 "Cannot truncate to larger type!");
1773 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1774 // For big endian targets, we need to add an offset to the pointer to load
1775 // the correct bytes. For little endian systems, we merely need to read
1776 // fewer bytes from the same pointer.
1778 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
1779 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
1780 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
1781 DAG.getConstant(PtrOff, PtrType));
1782 WorkList.push_back(NewPtr.Val);
1783 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
1784 WorkList.push_back(N);
1785 CombineTo(N0.Val, Load, Load.getValue(1));
1791 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
1792 SDOperand N0 = N->getOperand(0);
1793 MVT::ValueType VT = N->getValueType(0);
1795 // If the input is a constant, let getNode() fold it.
1796 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
1797 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
1798 if (Res.Val != N) return Res;
1801 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
1802 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
1804 // fold (conv (load x)) -> (load (conv*)x)
1805 // FIXME: These xforms need to know that the resultant load doesn't need a
1806 // higher alignment than the original!
1807 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1808 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1),
1810 WorkList.push_back(N);
1811 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
1819 SDOperand DAGCombiner::visitFADD(SDNode *N) {
1820 SDOperand N0 = N->getOperand(0);
1821 SDOperand N1 = N->getOperand(1);
1822 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1823 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1824 MVT::ValueType VT = N->getValueType(0);
1826 // fold (fadd c1, c2) -> c1+c2
1828 return DAG.getNode(ISD::FADD, VT, N0, N1);
1829 // canonicalize constant to RHS
1830 if (N0CFP && !N1CFP)
1831 return DAG.getNode(ISD::FADD, VT, N1, N0);
1832 // fold (A + (-B)) -> A-B
1833 if (N1.getOpcode() == ISD::FNEG)
1834 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
1835 // fold ((-A) + B) -> B-A
1836 if (N0.getOpcode() == ISD::FNEG)
1837 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
1841 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
1842 SDOperand N0 = N->getOperand(0);
1843 SDOperand N1 = N->getOperand(1);
1844 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1845 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1846 MVT::ValueType VT = N->getValueType(0);
1848 // fold (fsub c1, c2) -> c1-c2
1850 return DAG.getNode(ISD::FSUB, VT, N0, N1);
1851 // fold (A-(-B)) -> A+B
1852 if (N1.getOpcode() == ISD::FNEG)
1853 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
1857 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
1858 SDOperand N0 = N->getOperand(0);
1859 SDOperand N1 = N->getOperand(1);
1860 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1861 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1862 MVT::ValueType VT = N->getValueType(0);
1864 // fold (fmul c1, c2) -> c1*c2
1866 return DAG.getNode(ISD::FMUL, VT, N0, N1);
1867 // canonicalize constant to RHS
1868 if (N0CFP && !N1CFP)
1869 return DAG.getNode(ISD::FMUL, VT, N1, N0);
1870 // fold (fmul X, 2.0) -> (fadd X, X)
1871 if (N1CFP && N1CFP->isExactlyValue(+2.0))
1872 return DAG.getNode(ISD::FADD, VT, N0, N0);
1876 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
1877 SDOperand N0 = N->getOperand(0);
1878 SDOperand N1 = N->getOperand(1);
1879 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1880 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1881 MVT::ValueType VT = N->getValueType(0);
1883 // fold (fdiv c1, c2) -> c1/c2
1885 return DAG.getNode(ISD::FDIV, VT, N0, N1);
1889 SDOperand DAGCombiner::visitFREM(SDNode *N) {
1890 SDOperand N0 = N->getOperand(0);
1891 SDOperand N1 = N->getOperand(1);
1892 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1893 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1894 MVT::ValueType VT = N->getValueType(0);
1896 // fold (frem c1, c2) -> fmod(c1,c2)
1898 return DAG.getNode(ISD::FREM, VT, N0, N1);
1903 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
1904 SDOperand N0 = N->getOperand(0);
1905 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1906 MVT::ValueType VT = N->getValueType(0);
1908 // fold (sint_to_fp c1) -> c1fp
1910 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
1914 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
1915 SDOperand N0 = N->getOperand(0);
1916 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1917 MVT::ValueType VT = N->getValueType(0);
1919 // fold (uint_to_fp c1) -> c1fp
1921 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
1925 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
1926 SDOperand N0 = N->getOperand(0);
1927 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1928 MVT::ValueType VT = N->getValueType(0);
1930 // fold (fp_to_sint c1fp) -> c1
1932 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
1936 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1937 SDOperand N0 = N->getOperand(0);
1938 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1939 MVT::ValueType VT = N->getValueType(0);
1941 // fold (fp_to_uint c1fp) -> c1
1943 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
1947 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
1948 SDOperand N0 = N->getOperand(0);
1949 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1950 MVT::ValueType VT = N->getValueType(0);
1952 // fold (fp_round c1fp) -> c1fp
1954 return DAG.getNode(ISD::FP_ROUND, VT, N0);
1958 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
1959 SDOperand N0 = N->getOperand(0);
1960 MVT::ValueType VT = N->getValueType(0);
1961 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1962 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1964 // fold (fp_round_inreg c1fp) -> c1fp
1966 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
1967 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
1972 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
1973 SDOperand N0 = N->getOperand(0);
1974 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1975 MVT::ValueType VT = N->getValueType(0);
1977 // fold (fp_extend c1fp) -> c1fp
1979 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
1983 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
1984 SDOperand N0 = N->getOperand(0);
1985 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1986 MVT::ValueType VT = N->getValueType(0);
1988 // fold (fneg c1) -> -c1
1990 return DAG.getNode(ISD::FNEG, VT, N0);
1991 // fold (fneg (sub x, y)) -> (sub y, x)
1992 if (N->getOperand(0).getOpcode() == ISD::SUB)
1993 return DAG.getNode(ISD::SUB, VT, N->getOperand(1), N->getOperand(0));
1994 // fold (fneg (fneg x)) -> x
1995 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1996 return N->getOperand(0).getOperand(0);
2000 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2001 SDOperand N0 = N->getOperand(0);
2002 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2003 MVT::ValueType VT = N->getValueType(0);
2005 // fold (fabs c1) -> fabs(c1)
2007 return DAG.getNode(ISD::FABS, VT, N0);
2008 // fold (fabs (fabs x)) -> (fabs x)
2009 if (N->getOperand(0).getOpcode() == ISD::FABS)
2010 return N->getOperand(0);
2011 // fold (fabs (fneg x)) -> (fabs x)
2012 if (N->getOperand(0).getOpcode() == ISD::FNEG)
2013 return DAG.getNode(ISD::FABS, VT, N->getOperand(0).getOperand(0));
2017 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2018 SDOperand Chain = N->getOperand(0);
2019 SDOperand N1 = N->getOperand(1);
2020 SDOperand N2 = N->getOperand(2);
2021 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2023 // never taken branch, fold to chain
2024 if (N1C && N1C->isNullValue())
2026 // unconditional branch
2027 if (N1C && N1C->getValue() == 1)
2028 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2032 SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
2033 SDOperand Chain = N->getOperand(0);
2034 SDOperand N1 = N->getOperand(1);
2035 SDOperand N2 = N->getOperand(2);
2036 SDOperand N3 = N->getOperand(3);
2037 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2039 // unconditional branch to true mbb
2040 if (N1C && N1C->getValue() == 1)
2041 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2042 // unconditional branch to false mbb
2043 if (N1C && N1C->isNullValue())
2044 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
2048 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2050 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2051 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2052 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2054 // Use SimplifySetCC to simplify SETCC's.
2055 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2056 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2058 // fold br_cc true, dest -> br dest (unconditional branch)
2059 if (SCCC && SCCC->getValue())
2060 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2062 // fold br_cc false, dest -> unconditional fall through
2063 if (SCCC && SCCC->isNullValue())
2064 return N->getOperand(0);
2065 // fold to a simpler setcc
2066 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2067 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2068 Simp.getOperand(2), Simp.getOperand(0),
2069 Simp.getOperand(1), N->getOperand(4));
2073 SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
2074 SDOperand Chain = N->getOperand(0);
2075 SDOperand CCN = N->getOperand(1);
2076 SDOperand LHS = N->getOperand(2);
2077 SDOperand RHS = N->getOperand(3);
2078 SDOperand N4 = N->getOperand(4);
2079 SDOperand N5 = N->getOperand(5);
2081 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
2082 cast<CondCodeSDNode>(CCN)->get(), false);
2083 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2085 // fold select_cc lhs, rhs, x, x, cc -> x
2087 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
2088 // fold select_cc true, x, y -> x
2089 if (SCCC && SCCC->getValue())
2090 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
2091 // fold select_cc false, x, y -> y
2092 if (SCCC && SCCC->isNullValue())
2093 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
2094 // fold to a simpler setcc
2095 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2096 return DAG.getBR2Way_CC(Chain, SCC.getOperand(2), SCC.getOperand(0),
2097 SCC.getOperand(1), N4, N5);
2101 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2102 SDOperand Chain = N->getOperand(0);
2103 SDOperand Ptr = N->getOperand(1);
2104 SDOperand SrcValue = N->getOperand(2);
2106 // If this load is directly stored, replace the load value with the stored
2108 // TODO: Handle store large -> read small portion.
2109 // TODO: Handle TRUNCSTORE/EXTLOAD
2110 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2111 Chain.getOperand(1).getValueType() == N->getValueType(0))
2112 return CombineTo(N, Chain.getOperand(1), Chain);
2117 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2118 SDOperand Chain = N->getOperand(0);
2119 SDOperand Value = N->getOperand(1);
2120 SDOperand Ptr = N->getOperand(2);
2121 SDOperand SrcValue = N->getOperand(3);
2123 // If this is a store that kills a previous store, remove the previous store.
2124 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2125 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2126 // Make sure that these stores are the same value type:
2127 // FIXME: we really care that the second store is >= size of the first.
2128 Value.getValueType() == Chain.getOperand(1).getValueType()) {
2129 // Create a new store of Value that replaces both stores.
2130 SDNode *PrevStore = Chain.Val;
2131 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
2133 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
2134 PrevStore->getOperand(0), Value, Ptr,
2136 CombineTo(N, NewStore); // Nuke this store.
2137 CombineTo(PrevStore, NewStore); // Nuke the previous store.
2138 return SDOperand(N, 0);
2141 // If this is a store of a bit convert, store the input value.
2142 // FIXME: This needs to know that the resultant store does not need a
2143 // higher alignment than the original.
2144 if (0 && Value.getOpcode() == ISD::BIT_CONVERT)
2145 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0),
2151 SDOperand DAGCombiner::visitLOCATION(SDNode *N) {
2152 SDOperand Chain = N->getOperand(0);
2154 // Remove redundant locations (last one holds)
2155 if (Chain.getOpcode() == ISD::LOCATION && Chain.hasOneUse()) {
2156 return DAG.getNode(ISD::LOCATION, MVT::Other, Chain.getOperand(0),
2166 SDOperand DAGCombiner::visitDEBUGLOC(SDNode *N) {
2167 SDOperand Chain = N->getOperand(0);
2169 // Remove redundant debug locations (last one holds)
2170 if (Chain.getOpcode() == ISD::DEBUG_LOC && Chain.hasOneUse()) {
2171 return DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Chain.getOperand(0),
2180 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
2181 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
2183 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
2184 cast<CondCodeSDNode>(N0.getOperand(2))->get());
2185 // If we got a simplified select_cc node back from SimplifySelectCC, then
2186 // break it down into a new SETCC node, and a new SELECT node, and then return
2187 // the SELECT node, since we were called with a SELECT node.
2189 // Check to see if we got a select_cc back (to turn into setcc/select).
2190 // Otherwise, just return whatever node we got back, like fabs.
2191 if (SCC.getOpcode() == ISD::SELECT_CC) {
2192 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
2193 SCC.getOperand(0), SCC.getOperand(1),
2195 WorkList.push_back(SETCC.Val);
2196 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
2197 SCC.getOperand(3), SETCC);
2204 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
2205 /// are the two values being selected between, see if we can simplify the
2208 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
2211 // If this is a select from two identical things, try to pull the operation
2212 // through the select.
2213 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
2215 std::cerr << "SELECT: ["; LHS.Val->dump();
2216 std::cerr << "] ["; RHS.Val->dump();
2220 // If this is a load and the token chain is identical, replace the select
2221 // of two loads with a load through a select of the address to load from.
2222 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
2223 // constants have been dropped into the constant pool.
2224 if ((LHS.getOpcode() == ISD::LOAD ||
2225 LHS.getOpcode() == ISD::EXTLOAD ||
2226 LHS.getOpcode() == ISD::ZEXTLOAD ||
2227 LHS.getOpcode() == ISD::SEXTLOAD) &&
2228 // Token chains must be identical.
2229 LHS.getOperand(0) == RHS.getOperand(0) &&
2230 // If this is an EXTLOAD, the VT's must match.
2231 (LHS.getOpcode() == ISD::LOAD ||
2232 LHS.getOperand(3) == RHS.getOperand(3))) {
2233 // FIXME: this conflates two src values, discarding one. This is not
2234 // the right thing to do, but nothing uses srcvalues now. When they do,
2235 // turn SrcValue into a list of locations.
2237 if (TheSelect->getOpcode() == ISD::SELECT)
2238 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
2239 TheSelect->getOperand(0), LHS.getOperand(1),
2242 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
2243 TheSelect->getOperand(0),
2244 TheSelect->getOperand(1),
2245 LHS.getOperand(1), RHS.getOperand(1),
2246 TheSelect->getOperand(4));
2249 if (LHS.getOpcode() == ISD::LOAD)
2250 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
2251 Addr, LHS.getOperand(2));
2253 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0),
2254 LHS.getOperand(0), Addr, LHS.getOperand(2),
2255 cast<VTSDNode>(LHS.getOperand(3))->getVT());
2256 // Users of the select now use the result of the load.
2257 CombineTo(TheSelect, Load);
2259 // Users of the old loads now use the new load's chain. We know the
2260 // old-load value is dead now.
2261 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
2262 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
2270 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
2271 SDOperand N2, SDOperand N3,
2274 MVT::ValueType VT = N2.getValueType();
2275 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
2276 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
2277 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
2278 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
2280 // Determine if the condition we're dealing with is constant
2281 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2282 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2284 // fold select_cc true, x, y -> x
2285 if (SCCC && SCCC->getValue())
2287 // fold select_cc false, x, y -> y
2288 if (SCCC && SCCC->getValue() == 0)
2291 // Check to see if we can simplify the select into an fabs node
2292 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
2293 // Allow either -0.0 or 0.0
2294 if (CFP->getValue() == 0.0) {
2295 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
2296 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
2297 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
2298 N2 == N3.getOperand(0))
2299 return DAG.getNode(ISD::FABS, VT, N0);
2301 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
2302 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
2303 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
2304 N2.getOperand(0) == N3)
2305 return DAG.getNode(ISD::FABS, VT, N3);
2309 // Check to see if we can perform the "gzip trick", transforming
2310 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
2311 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
2312 MVT::isInteger(N0.getValueType()) &&
2313 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
2314 MVT::ValueType XType = N0.getValueType();
2315 MVT::ValueType AType = N2.getValueType();
2316 if (XType >= AType) {
2317 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
2318 // single-bit constant.
2319 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
2320 unsigned ShCtV = Log2_64(N2C->getValue());
2321 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
2322 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
2323 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
2324 WorkList.push_back(Shift.Val);
2325 if (XType > AType) {
2326 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2327 WorkList.push_back(Shift.Val);
2329 return DAG.getNode(ISD::AND, AType, Shift, N2);
2331 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2332 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2333 TLI.getShiftAmountTy()));
2334 WorkList.push_back(Shift.Val);
2335 if (XType > AType) {
2336 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2337 WorkList.push_back(Shift.Val);
2339 return DAG.getNode(ISD::AND, AType, Shift, N2);
2343 // fold select C, 16, 0 -> shl C, 4
2344 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
2345 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
2346 // Get a SetCC of the condition
2347 // FIXME: Should probably make sure that setcc is legal if we ever have a
2348 // target where it isn't.
2349 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2350 WorkList.push_back(SCC.Val);
2351 // cast from setcc result type to select result type
2353 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
2355 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
2356 WorkList.push_back(Temp.Val);
2357 // shl setcc result by log2 n2c
2358 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
2359 DAG.getConstant(Log2_64(N2C->getValue()),
2360 TLI.getShiftAmountTy()));
2363 // Check to see if this is the equivalent of setcc
2364 // FIXME: Turn all of these into setcc if setcc if setcc is legal
2365 // otherwise, go ahead with the folds.
2366 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
2367 MVT::ValueType XType = N0.getValueType();
2368 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
2369 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2370 if (Res.getValueType() != VT)
2371 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
2375 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
2376 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
2377 TLI.isOperationLegal(ISD::CTLZ, XType)) {
2378 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
2379 return DAG.getNode(ISD::SRL, XType, Ctlz,
2380 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
2381 TLI.getShiftAmountTy()));
2383 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
2384 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
2385 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
2387 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
2388 DAG.getConstant(~0ULL, XType));
2389 return DAG.getNode(ISD::SRL, XType,
2390 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
2391 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2392 TLI.getShiftAmountTy()));
2394 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
2395 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
2396 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
2397 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2398 TLI.getShiftAmountTy()));
2399 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
2403 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
2404 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2405 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
2406 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
2407 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
2408 MVT::ValueType XType = N0.getValueType();
2409 if (SubC->isNullValue() && MVT::isInteger(XType)) {
2410 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2411 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2412 TLI.getShiftAmountTy()));
2413 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
2414 WorkList.push_back(Shift.Val);
2415 WorkList.push_back(Add.Val);
2416 return DAG.getNode(ISD::XOR, XType, Add, Shift);
2424 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
2425 SDOperand N1, ISD::CondCode Cond,
2426 bool foldBooleans) {
2427 // These setcc operations always fold.
2431 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
2433 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
2436 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
2437 uint64_t C1 = N1C->getValue();
2438 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
2439 uint64_t C0 = N0C->getValue();
2441 // Sign extend the operands if required
2442 if (ISD::isSignedIntSetCC(Cond)) {
2443 C0 = N0C->getSignExtended();
2444 C1 = N1C->getSignExtended();
2448 default: assert(0 && "Unknown integer setcc!");
2449 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2450 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2451 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
2452 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
2453 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
2454 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
2455 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
2456 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
2457 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
2458 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
2461 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2462 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2463 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
2465 // If the comparison constant has bits in the upper part, the
2466 // zero-extended value could never match.
2467 if (C1 & (~0ULL << InSize)) {
2468 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
2472 case ISD::SETEQ: return DAG.getConstant(0, VT);
2475 case ISD::SETNE: return DAG.getConstant(1, VT);
2478 // True if the sign bit of C1 is set.
2479 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
2482 // True if the sign bit of C1 isn't set.
2483 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
2489 // Otherwise, we can perform the comparison with the low bits.
2497 return DAG.getSetCC(VT, N0.getOperand(0),
2498 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
2501 break; // todo, be more careful with signed comparisons
2503 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2504 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2505 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2506 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
2507 MVT::ValueType ExtDstTy = N0.getValueType();
2508 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
2510 // If the extended part has any inconsistent bits, it cannot ever
2511 // compare equal. In other words, they have to be all ones or all
2514 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
2515 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
2516 return DAG.getConstant(Cond == ISD::SETNE, VT);
2519 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
2520 if (Op0Ty == ExtSrcTy) {
2521 ZextOp = N0.getOperand(0);
2523 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
2524 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
2525 DAG.getConstant(Imm, Op0Ty));
2527 WorkList.push_back(ZextOp.Val);
2528 // Otherwise, make this a use of a zext.
2529 return DAG.getSetCC(VT, ZextOp,
2530 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
2535 uint64_t MinVal, MaxVal;
2536 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
2537 if (ISD::isSignedIntSetCC(Cond)) {
2538 MinVal = 1ULL << (OperandBitSize-1);
2539 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
2540 MaxVal = ~0ULL >> (65-OperandBitSize);
2545 MaxVal = ~0ULL >> (64-OperandBitSize);
2548 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2549 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2550 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2551 --C1; // X >= C0 --> X > (C0-1)
2552 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2553 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2556 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2557 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2558 ++C1; // X <= C0 --> X < (C0+1)
2559 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2560 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2563 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2564 return DAG.getConstant(0, VT); // X < MIN --> false
2566 // Canonicalize setgt X, Min --> setne X, Min
2567 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2568 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2569 // Canonicalize setlt X, Max --> setne X, Max
2570 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2571 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2573 // If we have setult X, 1, turn it into seteq X, 0
2574 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2575 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
2577 // If we have setugt X, Max-1, turn it into seteq X, Max
2578 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2579 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
2582 // If we have "setcc X, C0", check to see if we can shrink the immediate
2585 // SETUGT X, SINTMAX -> SETLT X, 0
2586 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
2587 C1 == (~0ULL >> (65-OperandBitSize)))
2588 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
2591 // FIXME: Implement the rest of these.
2593 // Fold bit comparisons when we can.
2594 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2595 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
2596 if (ConstantSDNode *AndRHS =
2597 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2598 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2599 // Perform the xform if the AND RHS is a single bit.
2600 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
2601 return DAG.getNode(ISD::SRL, VT, N0,
2602 DAG.getConstant(Log2_64(AndRHS->getValue()),
2603 TLI.getShiftAmountTy()));
2605 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
2606 // (X & 8) == 8 --> (X & 8) >> 3
2607 // Perform the xform if C1 is a single bit.
2608 if ((C1 & (C1-1)) == 0) {
2609 return DAG.getNode(ISD::SRL, VT, N0,
2610 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
2615 } else if (isa<ConstantSDNode>(N0.Val)) {
2616 // Ensure that the constant occurs on the RHS.
2617 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2620 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
2621 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
2622 double C0 = N0C->getValue(), C1 = N1C->getValue();
2625 default: break; // FIXME: Implement the rest of these!
2626 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2627 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2628 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
2629 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
2630 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
2631 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
2634 // Ensure that the constant occurs on the RHS.
2635 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2639 // We can always fold X == Y for integer setcc's.
2640 if (MVT::isInteger(N0.getValueType()))
2641 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2642 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2643 if (UOF == 2) // FP operators that are undefined on NaNs.
2644 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2645 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2646 return DAG.getConstant(UOF, VT);
2647 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2648 // if it is not already.
2649 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2650 if (NewCond != Cond)
2651 return DAG.getSetCC(VT, N0, N1, NewCond);
2654 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2655 MVT::isInteger(N0.getValueType())) {
2656 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2657 N0.getOpcode() == ISD::XOR) {
2658 // Simplify (X+Y) == (X+Z) --> Y == Z
2659 if (N0.getOpcode() == N1.getOpcode()) {
2660 if (N0.getOperand(0) == N1.getOperand(0))
2661 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2662 if (N0.getOperand(1) == N1.getOperand(1))
2663 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
2664 if (isCommutativeBinOp(N0.getOpcode())) {
2665 // If X op Y == Y op X, try other combinations.
2666 if (N0.getOperand(0) == N1.getOperand(1))
2667 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
2668 if (N0.getOperand(1) == N1.getOperand(0))
2669 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
2673 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes.
2674 if (N0.getOpcode() == ISD::XOR)
2675 if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2676 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2677 // If we know that all of the inverted bits are zero, don't bother
2678 // performing the inversion.
2679 if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI))
2680 return DAG.getSetCC(VT, N0.getOperand(0),
2681 DAG.getConstant(XORC->getValue()^RHSC->getValue(),
2682 N0.getValueType()), Cond);
2685 // Simplify (X+Z) == X --> Z == 0
2686 if (N0.getOperand(0) == N1)
2687 return DAG.getSetCC(VT, N0.getOperand(1),
2688 DAG.getConstant(0, N0.getValueType()), Cond);
2689 if (N0.getOperand(1) == N1) {
2690 if (isCommutativeBinOp(N0.getOpcode()))
2691 return DAG.getSetCC(VT, N0.getOperand(0),
2692 DAG.getConstant(0, N0.getValueType()), Cond);
2694 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2695 // (Z-X) == X --> Z == X<<1
2696 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
2698 DAG.getConstant(1,TLI.getShiftAmountTy()));
2699 WorkList.push_back(SH.Val);
2700 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
2705 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2706 N1.getOpcode() == ISD::XOR) {
2707 // Simplify X == (X+Z) --> Z == 0
2708 if (N1.getOperand(0) == N0) {
2709 return DAG.getSetCC(VT, N1.getOperand(1),
2710 DAG.getConstant(0, N1.getValueType()), Cond);
2711 } else if (N1.getOperand(1) == N0) {
2712 if (isCommutativeBinOp(N1.getOpcode())) {
2713 return DAG.getSetCC(VT, N1.getOperand(0),
2714 DAG.getConstant(0, N1.getValueType()), Cond);
2716 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2717 // X == (Z-X) --> X<<1 == Z
2718 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
2719 DAG.getConstant(1,TLI.getShiftAmountTy()));
2720 WorkList.push_back(SH.Val);
2721 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
2727 // Fold away ALL boolean setcc's.
2729 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2731 default: assert(0 && "Unknown integer setcc!");
2732 case ISD::SETEQ: // X == Y -> (X^Y)^1
2733 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2734 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
2735 WorkList.push_back(Temp.Val);
2737 case ISD::SETNE: // X != Y --> (X^Y)
2738 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2740 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
2741 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
2742 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2743 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
2744 WorkList.push_back(Temp.Val);
2746 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
2747 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
2748 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2749 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
2750 WorkList.push_back(Temp.Val);
2752 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
2753 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
2754 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2755 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
2756 WorkList.push_back(Temp.Val);
2758 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
2759 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
2760 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2761 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
2764 if (VT != MVT::i1) {
2765 WorkList.push_back(N0.Val);
2766 // FIXME: If running after legalize, we probably can't do this.
2767 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2772 // Could not fold it.
2776 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2777 /// return a DAG expression to select that will generate the same value by
2778 /// multiplying by a magic number. See:
2779 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2780 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
2781 MVT::ValueType VT = N->getValueType(0);
2783 // Check to see if we can do this.
2784 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2785 return SDOperand(); // BuildSDIV only operates on i32 or i64
2786 if (!TLI.isOperationLegal(ISD::MULHS, VT))
2787 return SDOperand(); // Make sure the target supports MULHS.
2789 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
2790 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
2792 // Multiply the numerator (operand 0) by the magic value
2793 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
2794 DAG.getConstant(magics.m, VT));
2795 // If d > 0 and m < 0, add the numerator
2796 if (d > 0 && magics.m < 0) {
2797 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
2798 WorkList.push_back(Q.Val);
2800 // If d < 0 and m > 0, subtract the numerator.
2801 if (d < 0 && magics.m > 0) {
2802 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
2803 WorkList.push_back(Q.Val);
2805 // Shift right algebraic if shift value is nonzero
2807 Q = DAG.getNode(ISD::SRA, VT, Q,
2808 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2809 WorkList.push_back(Q.Val);
2811 // Extract the sign bit and add it to the quotient
2813 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
2814 TLI.getShiftAmountTy()));
2815 WorkList.push_back(T.Val);
2816 return DAG.getNode(ISD::ADD, VT, Q, T);
2819 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2820 /// return a DAG expression to select that will generate the same value by
2821 /// multiplying by a magic number. See:
2822 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2823 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
2824 MVT::ValueType VT = N->getValueType(0);
2826 // Check to see if we can do this.
2827 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2828 return SDOperand(); // BuildUDIV only operates on i32 or i64
2829 if (!TLI.isOperationLegal(ISD::MULHU, VT))
2830 return SDOperand(); // Make sure the target supports MULHU.
2832 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
2833 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
2835 // Multiply the numerator (operand 0) by the magic value
2836 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
2837 DAG.getConstant(magics.m, VT));
2838 WorkList.push_back(Q.Val);
2840 if (magics.a == 0) {
2841 return DAG.getNode(ISD::SRL, VT, Q,
2842 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2844 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
2845 WorkList.push_back(NPQ.Val);
2846 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
2847 DAG.getConstant(1, TLI.getShiftAmountTy()));
2848 WorkList.push_back(NPQ.Val);
2849 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
2850 WorkList.push_back(NPQ.Val);
2851 return DAG.getNode(ISD::SRL, VT, NPQ,
2852 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy()));
2856 // SelectionDAG::Combine - This is the entry point for the file.
2858 void SelectionDAG::Combine(bool RunningAfterLegalize) {
2859 /// run - This is the main entry point to this class.
2861 DAGCombiner(*this).Run(RunningAfterLegalize);