1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/Target/TargetData.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/SmallPtrSet.h"
39 #include "llvm/ADT/Statistic.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/MathExtras.h"
47 STATISTIC(NodesCombined , "Number of dag nodes combined");
48 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
49 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
54 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
55 cl::desc("Pop up a window to show dags before the first "
58 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
59 cl::desc("Pop up a window to show dags before the second "
62 static const bool ViewDAGCombine1 = false;
63 static const bool ViewDAGCombine2 = false;
67 CombinerAA("combiner-alias-analysis", cl::Hidden,
68 cl::desc("Turn on alias analysis during testing"));
71 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
72 cl::desc("Include global information in alias analysis"));
74 //------------------------------ DAGCombiner ---------------------------------//
76 class VISIBILITY_HIDDEN DAGCombiner {
81 // Worklist of all of the nodes that need to be simplified.
82 std::vector<SDNode*> WorkList;
84 // AA - Used for DAG load/store alias analysis.
87 /// AddUsersToWorkList - When an instruction is simplified, add all users of
88 /// the instruction to the work lists because they might get more simplified
91 void AddUsersToWorkList(SDNode *N) {
92 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
97 /// removeFromWorkList - remove all instances of N from the worklist.
99 void removeFromWorkList(SDNode *N) {
100 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
105 /// AddToWorkList - Add to the work list making sure it's instance is at the
106 /// the back (next to be processed.)
107 void AddToWorkList(SDNode *N) {
108 removeFromWorkList(N);
109 WorkList.push_back(N);
112 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
114 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
116 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
117 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
118 DOUT << " and " << NumTo-1 << " other values\n";
119 std::vector<SDNode*> NowDead;
120 DAG.ReplaceAllUsesWith(N, To, &NowDead);
123 // Push the new nodes and any users onto the worklist
124 for (unsigned i = 0, e = NumTo; i != e; ++i) {
125 AddToWorkList(To[i].Val);
126 AddUsersToWorkList(To[i].Val);
130 // Nodes can be reintroduced into the worklist. Make sure we do not
131 // process a node that has been replaced.
132 removeFromWorkList(N);
133 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
134 removeFromWorkList(NowDead[i]);
136 // Finally, since the node is now dead, remove it from the graph.
138 return SDOperand(N, 0);
141 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
142 return CombineTo(N, &Res, 1, AddTo);
145 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
147 SDOperand To[] = { Res0, Res1 };
148 return CombineTo(N, To, 2, AddTo);
152 /// SimplifyDemandedBits - Check the specified integer node value to see if
153 /// it can be simplified or if things it uses can be simplified by bit
154 /// propagation. If so, return true.
155 bool SimplifyDemandedBits(SDOperand Op) {
156 TargetLowering::TargetLoweringOpt TLO(DAG);
157 uint64_t KnownZero, KnownOne;
158 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
159 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
163 AddToWorkList(Op.Val);
165 // Replace the old value with the new one.
167 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
168 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
171 std::vector<SDNode*> NowDead;
172 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
174 // Push the new node and any (possibly new) users onto the worklist.
175 AddToWorkList(TLO.New.Val);
176 AddUsersToWorkList(TLO.New.Val);
178 // Nodes can end up on the worklist more than once. Make sure we do
179 // not process a node that has been replaced.
180 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
181 removeFromWorkList(NowDead[i]);
183 // Finally, if the node is now dead, remove it from the graph. The node
184 // may not be dead if the replacement process recursively simplified to
185 // something else needing this node.
186 if (TLO.Old.Val->use_empty()) {
187 removeFromWorkList(TLO.Old.Val);
189 // If the operands of this node are only used by the node, they will now
190 // be dead. Make sure to visit them first to delete dead nodes early.
191 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i)
192 if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
193 AddToWorkList(TLO.Old.Val->getOperand(i).Val);
195 DAG.DeleteNode(TLO.Old.Val);
200 bool CombineToPreIndexedLoadStore(SDNode *N);
201 bool CombineToPostIndexedLoadStore(SDNode *N);
204 /// visit - call the node-specific routine that knows how to fold each
205 /// particular type of node.
206 SDOperand visit(SDNode *N);
208 // Visitation implementation - Implement dag node combining for different
209 // node types. The semantics are as follows:
211 // SDOperand.Val == 0 - No change was made
212 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
213 // otherwise - N should be replaced by the returned Operand.
215 SDOperand visitTokenFactor(SDNode *N);
216 SDOperand visitADD(SDNode *N);
217 SDOperand visitSUB(SDNode *N);
218 SDOperand visitADDC(SDNode *N);
219 SDOperand visitADDE(SDNode *N);
220 SDOperand visitMUL(SDNode *N);
221 SDOperand visitSDIV(SDNode *N);
222 SDOperand visitUDIV(SDNode *N);
223 SDOperand visitSREM(SDNode *N);
224 SDOperand visitUREM(SDNode *N);
225 SDOperand visitMULHU(SDNode *N);
226 SDOperand visitMULHS(SDNode *N);
227 SDOperand visitAND(SDNode *N);
228 SDOperand visitOR(SDNode *N);
229 SDOperand visitXOR(SDNode *N);
230 SDOperand SimplifyVBinOp(SDNode *N);
231 SDOperand visitSHL(SDNode *N);
232 SDOperand visitSRA(SDNode *N);
233 SDOperand visitSRL(SDNode *N);
234 SDOperand visitCTLZ(SDNode *N);
235 SDOperand visitCTTZ(SDNode *N);
236 SDOperand visitCTPOP(SDNode *N);
237 SDOperand visitSELECT(SDNode *N);
238 SDOperand visitSELECT_CC(SDNode *N);
239 SDOperand visitSETCC(SDNode *N);
240 SDOperand visitSIGN_EXTEND(SDNode *N);
241 SDOperand visitZERO_EXTEND(SDNode *N);
242 SDOperand visitANY_EXTEND(SDNode *N);
243 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
244 SDOperand visitTRUNCATE(SDNode *N);
245 SDOperand visitBIT_CONVERT(SDNode *N);
246 SDOperand visitFADD(SDNode *N);
247 SDOperand visitFSUB(SDNode *N);
248 SDOperand visitFMUL(SDNode *N);
249 SDOperand visitFDIV(SDNode *N);
250 SDOperand visitFREM(SDNode *N);
251 SDOperand visitFCOPYSIGN(SDNode *N);
252 SDOperand visitSINT_TO_FP(SDNode *N);
253 SDOperand visitUINT_TO_FP(SDNode *N);
254 SDOperand visitFP_TO_SINT(SDNode *N);
255 SDOperand visitFP_TO_UINT(SDNode *N);
256 SDOperand visitFP_ROUND(SDNode *N);
257 SDOperand visitFP_ROUND_INREG(SDNode *N);
258 SDOperand visitFP_EXTEND(SDNode *N);
259 SDOperand visitFNEG(SDNode *N);
260 SDOperand visitFABS(SDNode *N);
261 SDOperand visitBRCOND(SDNode *N);
262 SDOperand visitBR_CC(SDNode *N);
263 SDOperand visitLOAD(SDNode *N);
264 SDOperand visitSTORE(SDNode *N);
265 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
266 SDOperand visitBUILD_VECTOR(SDNode *N);
267 SDOperand visitCONCAT_VECTORS(SDNode *N);
268 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
270 SDOperand XformToShuffleWithZero(SDNode *N);
271 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
273 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
274 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
275 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
276 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
277 SDOperand N3, ISD::CondCode CC,
278 bool NotExtCompare = false);
279 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
280 ISD::CondCode Cond, bool foldBooleans = true);
281 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
282 SDOperand BuildSDIV(SDNode *N);
283 SDOperand BuildUDIV(SDNode *N);
284 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
285 SDOperand ReduceLoadWidth(SDNode *N);
287 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
288 /// looking for aliasing nodes and adding them to the Aliases vector.
289 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
290 SmallVector<SDOperand, 8> &Aliases);
292 /// isAlias - Return true if there is any possibility that the two addresses
294 bool isAlias(SDOperand Ptr1, int64_t Size1,
295 const Value *SrcValue1, int SrcValueOffset1,
296 SDOperand Ptr2, int64_t Size2,
297 const Value *SrcValue2, int SrcValueOffset2);
299 /// FindAliasInfo - Extracts the relevant alias information from the memory
300 /// node. Returns true if the operand was a load.
301 bool FindAliasInfo(SDNode *N,
302 SDOperand &Ptr, int64_t &Size,
303 const Value *&SrcValue, int &SrcValueOffset);
305 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
306 /// looking for a better chain (aliasing node.)
307 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
310 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
312 TLI(D.getTargetLoweringInfo()),
313 AfterLegalize(false),
316 /// Run - runs the dag combiner on all nodes in the work list
317 void Run(bool RunningAfterLegalize);
321 //===----------------------------------------------------------------------===//
322 // TargetLowering::DAGCombinerInfo implementation
323 //===----------------------------------------------------------------------===//
325 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
326 ((DAGCombiner*)DC)->AddToWorkList(N);
329 SDOperand TargetLowering::DAGCombinerInfo::
330 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
331 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
334 SDOperand TargetLowering::DAGCombinerInfo::
335 CombineTo(SDNode *N, SDOperand Res) {
336 return ((DAGCombiner*)DC)->CombineTo(N, Res);
340 SDOperand TargetLowering::DAGCombinerInfo::
341 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
342 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
346 //===----------------------------------------------------------------------===//
348 //===----------------------------------------------------------------------===//
350 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
351 /// specified expression for the same cost as the expression itself, or 2 if we
352 /// can compute the negated form more cheaply than the expression itself.
353 static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) {
354 // fneg is removable even if it has multiple uses.
355 if (Op.getOpcode() == ISD::FNEG) return 2;
357 // Don't allow anything with multiple uses.
358 if (!Op.hasOneUse()) return 0;
360 // Don't recurse exponentially.
361 if (Depth > 6) return 0;
363 switch (Op.getOpcode()) {
364 default: return false;
365 case ISD::ConstantFP:
368 // FIXME: determine better conditions for this xform.
369 if (!UnsafeFPMath) return 0;
372 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
375 return isNegatibleForFree(Op.getOperand(1), Depth+1);
377 // We can't turn -(A-B) into B-A when we honor signed zeros.
378 if (!UnsafeFPMath) return 0;
385 if (HonorSignDependentRoundingFPMath()) return 0;
387 // -(X*Y) -> (-X * Y) or (X*-Y)
388 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
391 return isNegatibleForFree(Op.getOperand(1), Depth+1);
396 return isNegatibleForFree(Op.getOperand(0), Depth+1);
400 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
401 /// returns the newly negated expression.
402 static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
403 unsigned Depth = 0) {
404 // fneg is removable even if it has multiple uses.
405 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
407 // Don't allow anything with multiple uses.
408 assert(Op.hasOneUse() && "Unknown reuse!");
410 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
411 switch (Op.getOpcode()) {
412 default: assert(0 && "Unknown code");
413 case ISD::ConstantFP:
414 return DAG.getConstantFP(-cast<ConstantFPSDNode>(Op)->getValue(),
417 // FIXME: determine better conditions for this xform.
418 assert(UnsafeFPMath);
421 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
422 return DAG.getNode(ISD::FSUB, Op.getValueType(),
423 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
426 return DAG.getNode(ISD::FSUB, Op.getValueType(),
427 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1),
430 // We can't turn -(A-B) into B-A when we honor signed zeros.
431 assert(UnsafeFPMath);
434 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
435 if (N0CFP->getValue() == 0.0)
436 return Op.getOperand(1);
439 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1),
444 assert(!HonorSignDependentRoundingFPMath());
447 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
448 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
449 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
453 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
455 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1));
460 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
461 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1));
466 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
467 // that selects between the values 1 and 0, making it equivalent to a setcc.
468 // Also, set the incoming LHS, RHS, and CC references to the appropriate
469 // nodes based on the type of node we are checking. This simplifies life a
470 // bit for the callers.
471 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
473 if (N.getOpcode() == ISD::SETCC) {
474 LHS = N.getOperand(0);
475 RHS = N.getOperand(1);
476 CC = N.getOperand(2);
479 if (N.getOpcode() == ISD::SELECT_CC &&
480 N.getOperand(2).getOpcode() == ISD::Constant &&
481 N.getOperand(3).getOpcode() == ISD::Constant &&
482 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
483 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
484 LHS = N.getOperand(0);
485 RHS = N.getOperand(1);
486 CC = N.getOperand(4);
492 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
493 // one use. If this is true, it allows the users to invert the operation for
494 // free when it is profitable to do so.
495 static bool isOneUseSetCC(SDOperand N) {
496 SDOperand N0, N1, N2;
497 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
502 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
503 MVT::ValueType VT = N0.getValueType();
504 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
505 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
506 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
507 if (isa<ConstantSDNode>(N1)) {
508 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
509 AddToWorkList(OpNode.Val);
510 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
511 } else if (N0.hasOneUse()) {
512 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
513 AddToWorkList(OpNode.Val);
514 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
517 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
518 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
519 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
520 if (isa<ConstantSDNode>(N0)) {
521 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
522 AddToWorkList(OpNode.Val);
523 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
524 } else if (N1.hasOneUse()) {
525 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
526 AddToWorkList(OpNode.Val);
527 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
533 //===----------------------------------------------------------------------===//
534 // Main DAG Combiner implementation
535 //===----------------------------------------------------------------------===//
537 void DAGCombiner::Run(bool RunningAfterLegalize) {
538 // set the instance variable, so that the various visit routines may use it.
539 AfterLegalize = RunningAfterLegalize;
541 // Add all the dag nodes to the worklist.
542 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
543 E = DAG.allnodes_end(); I != E; ++I)
544 WorkList.push_back(I);
546 // Create a dummy node (which is not added to allnodes), that adds a reference
547 // to the root node, preventing it from being deleted, and tracking any
548 // changes of the root.
549 HandleSDNode Dummy(DAG.getRoot());
551 // The root of the dag may dangle to deleted nodes until the dag combiner is
552 // done. Set it to null to avoid confusion.
553 DAG.setRoot(SDOperand());
555 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
556 TargetLowering::DAGCombinerInfo
557 DagCombineInfo(DAG, !RunningAfterLegalize, false, this);
559 // while the worklist isn't empty, inspect the node on the end of it and
560 // try and combine it.
561 while (!WorkList.empty()) {
562 SDNode *N = WorkList.back();
565 // If N has no uses, it is dead. Make sure to revisit all N's operands once
566 // N is deleted from the DAG, since they too may now be dead or may have a
567 // reduced number of uses, allowing other xforms.
568 if (N->use_empty() && N != &Dummy) {
569 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
570 AddToWorkList(N->getOperand(i).Val);
576 SDOperand RV = visit(N);
578 // If nothing happened, try a target-specific DAG combine.
580 assert(N->getOpcode() != ISD::DELETED_NODE &&
581 "Node was deleted but visit returned NULL!");
582 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
583 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
584 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
589 // If we get back the same node we passed in, rather than a new node or
590 // zero, we know that the node must have defined multiple values and
591 // CombineTo was used. Since CombineTo takes care of the worklist
592 // mechanics for us, we have no work to do in this case.
594 assert(N->getOpcode() != ISD::DELETED_NODE &&
595 RV.Val->getOpcode() != ISD::DELETED_NODE &&
596 "Node was deleted but visit returned new node!");
598 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
599 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
601 std::vector<SDNode*> NowDead;
602 if (N->getNumValues() == RV.Val->getNumValues())
603 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
605 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
607 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
610 // Push the new node and any users onto the worklist
611 AddToWorkList(RV.Val);
612 AddUsersToWorkList(RV.Val);
614 // Nodes can be reintroduced into the worklist. Make sure we do not
615 // process a node that has been replaced.
616 removeFromWorkList(N);
617 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
618 removeFromWorkList(NowDead[i]);
620 // Finally, since the node is now dead, remove it from the graph.
626 // If the root changed (e.g. it was a dead load, update the root).
627 DAG.setRoot(Dummy.getValue());
630 SDOperand DAGCombiner::visit(SDNode *N) {
631 switch(N->getOpcode()) {
633 case ISD::TokenFactor: return visitTokenFactor(N);
634 case ISD::ADD: return visitADD(N);
635 case ISD::SUB: return visitSUB(N);
636 case ISD::ADDC: return visitADDC(N);
637 case ISD::ADDE: return visitADDE(N);
638 case ISD::MUL: return visitMUL(N);
639 case ISD::SDIV: return visitSDIV(N);
640 case ISD::UDIV: return visitUDIV(N);
641 case ISD::SREM: return visitSREM(N);
642 case ISD::UREM: return visitUREM(N);
643 case ISD::MULHU: return visitMULHU(N);
644 case ISD::MULHS: return visitMULHS(N);
645 case ISD::AND: return visitAND(N);
646 case ISD::OR: return visitOR(N);
647 case ISD::XOR: return visitXOR(N);
648 case ISD::SHL: return visitSHL(N);
649 case ISD::SRA: return visitSRA(N);
650 case ISD::SRL: return visitSRL(N);
651 case ISD::CTLZ: return visitCTLZ(N);
652 case ISD::CTTZ: return visitCTTZ(N);
653 case ISD::CTPOP: return visitCTPOP(N);
654 case ISD::SELECT: return visitSELECT(N);
655 case ISD::SELECT_CC: return visitSELECT_CC(N);
656 case ISD::SETCC: return visitSETCC(N);
657 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
658 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
659 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
660 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
661 case ISD::TRUNCATE: return visitTRUNCATE(N);
662 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
663 case ISD::FADD: return visitFADD(N);
664 case ISD::FSUB: return visitFSUB(N);
665 case ISD::FMUL: return visitFMUL(N);
666 case ISD::FDIV: return visitFDIV(N);
667 case ISD::FREM: return visitFREM(N);
668 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
669 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
670 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
671 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
672 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
673 case ISD::FP_ROUND: return visitFP_ROUND(N);
674 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
675 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
676 case ISD::FNEG: return visitFNEG(N);
677 case ISD::FABS: return visitFABS(N);
678 case ISD::BRCOND: return visitBRCOND(N);
679 case ISD::BR_CC: return visitBR_CC(N);
680 case ISD::LOAD: return visitLOAD(N);
681 case ISD::STORE: return visitSTORE(N);
682 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
683 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
684 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
685 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
690 /// getInputChainForNode - Given a node, return its input chain if it has one,
691 /// otherwise return a null sd operand.
692 static SDOperand getInputChainForNode(SDNode *N) {
693 if (unsigned NumOps = N->getNumOperands()) {
694 if (N->getOperand(0).getValueType() == MVT::Other)
695 return N->getOperand(0);
696 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
697 return N->getOperand(NumOps-1);
698 for (unsigned i = 1; i < NumOps-1; ++i)
699 if (N->getOperand(i).getValueType() == MVT::Other)
700 return N->getOperand(i);
702 return SDOperand(0, 0);
705 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
706 // If N has two operands, where one has an input chain equal to the other,
707 // the 'other' chain is redundant.
708 if (N->getNumOperands() == 2) {
709 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
710 return N->getOperand(0);
711 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
712 return N->getOperand(1);
715 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
716 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
717 SmallPtrSet<SDNode*, 16> SeenOps;
718 bool Changed = false; // If we should replace this token factor.
720 // Start out with this token factor.
723 // Iterate through token factors. The TFs grows when new token factors are
725 for (unsigned i = 0; i < TFs.size(); ++i) {
728 // Check each of the operands.
729 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
730 SDOperand Op = TF->getOperand(i);
732 switch (Op.getOpcode()) {
733 case ISD::EntryToken:
734 // Entry tokens don't need to be added to the list. They are
739 case ISD::TokenFactor:
740 if ((CombinerAA || Op.hasOneUse()) &&
741 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
742 // Queue up for processing.
743 TFs.push_back(Op.Val);
744 // Clean up in case the token factor is removed.
745 AddToWorkList(Op.Val);
752 // Only add if it isn't already in the list.
753 if (SeenOps.insert(Op.Val))
764 // If we've change things around then replace token factor.
766 if (Ops.size() == 0) {
767 // The entry token is the only possible outcome.
768 Result = DAG.getEntryNode();
770 // New and improved token factor.
771 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
774 // Don't add users to work list.
775 return CombineTo(N, Result, false);
782 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
783 MVT::ValueType VT = N0.getValueType();
784 SDOperand N00 = N0.getOperand(0);
785 SDOperand N01 = N0.getOperand(1);
786 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
787 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
788 isa<ConstantSDNode>(N00.getOperand(1))) {
789 N0 = DAG.getNode(ISD::ADD, VT,
790 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
791 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
792 return DAG.getNode(ISD::ADD, VT, N0, N1);
798 SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
800 MVT::ValueType VT = N->getValueType(0);
801 unsigned Opc = N->getOpcode();
802 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
803 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
804 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
805 ISD::CondCode CC = ISD::SETCC_INVALID;
807 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
809 SDOperand CCOp = Slct.getOperand(0);
810 if (CCOp.getOpcode() == ISD::SETCC)
811 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
814 bool DoXform = false;
816 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
818 if (LHS.getOpcode() == ISD::Constant &&
819 cast<ConstantSDNode>(LHS)->isNullValue())
821 else if (CC != ISD::SETCC_INVALID &&
822 RHS.getOpcode() == ISD::Constant &&
823 cast<ConstantSDNode>(RHS)->isNullValue()) {
825 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType()
826 : Slct.getOperand(0).getOperand(0).getValueType());
827 CC = ISD::getSetCCInverse(CC, isInt);
833 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS);
835 return DAG.getSelectCC(OtherOp, Result,
836 Slct.getOperand(0), Slct.getOperand(1), CC);
837 SDOperand CCOp = Slct.getOperand(0);
839 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
840 CCOp.getOperand(1), CC);
841 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
846 SDOperand DAGCombiner::visitADD(SDNode *N) {
847 SDOperand N0 = N->getOperand(0);
848 SDOperand N1 = N->getOperand(1);
849 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
850 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
851 MVT::ValueType VT = N0.getValueType();
854 SDOperand FoldedVOp = SimplifyVBinOp(N);
855 if (FoldedVOp.Val) return FoldedVOp;
857 // fold (add x, undef) -> undef
858 if (N1.getOpcode() == ISD::UNDEF)
860 // fold (add c1, c2) -> c1+c2
862 return DAG.getNode(ISD::ADD, VT, N0, N1);
863 // canonicalize constant to RHS
865 return DAG.getNode(ISD::ADD, VT, N1, N0);
866 // fold (add x, 0) -> x
867 if (N1C && N1C->isNullValue())
869 // fold ((c1-A)+c2) -> (c1+c2)-A
870 if (N1C && N0.getOpcode() == ISD::SUB)
871 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
872 return DAG.getNode(ISD::SUB, VT,
873 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
876 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
879 // fold ((0-A) + B) -> B-A
880 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
881 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
882 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
883 // fold (A + (0-B)) -> A-B
884 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
885 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
886 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
887 // fold (A+(B-A)) -> B
888 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
889 return N1.getOperand(0);
891 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
892 return SDOperand(N, 0);
894 // fold (a+b) -> (a|b) iff a and b share no bits.
895 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
896 uint64_t LHSZero, LHSOne;
897 uint64_t RHSZero, RHSOne;
898 uint64_t Mask = MVT::getIntVTBitMask(VT);
899 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
901 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
903 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
904 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
905 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
906 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
907 return DAG.getNode(ISD::OR, VT, N0, N1);
911 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
912 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
913 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
914 if (Result.Val) return Result;
916 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
917 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
918 if (Result.Val) return Result;
921 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
922 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
923 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG);
924 if (Result.Val) return Result;
926 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
927 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
928 if (Result.Val) return Result;
934 SDOperand DAGCombiner::visitADDC(SDNode *N) {
935 SDOperand N0 = N->getOperand(0);
936 SDOperand N1 = N->getOperand(1);
937 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
938 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
939 MVT::ValueType VT = N0.getValueType();
941 // If the flag result is dead, turn this into an ADD.
942 if (N->hasNUsesOfValue(0, 1))
943 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
944 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
946 // canonicalize constant to RHS.
948 SDOperand Ops[] = { N1, N0 };
949 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
952 // fold (addc x, 0) -> x + no carry out
953 if (N1C && N1C->isNullValue())
954 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
956 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
957 uint64_t LHSZero, LHSOne;
958 uint64_t RHSZero, RHSOne;
959 uint64_t Mask = MVT::getIntVTBitMask(VT);
960 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
962 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
964 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
965 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
966 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
967 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
968 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
969 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
975 SDOperand DAGCombiner::visitADDE(SDNode *N) {
976 SDOperand N0 = N->getOperand(0);
977 SDOperand N1 = N->getOperand(1);
978 SDOperand CarryIn = N->getOperand(2);
979 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
980 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
981 //MVT::ValueType VT = N0.getValueType();
983 // canonicalize constant to RHS
985 SDOperand Ops[] = { N1, N0, CarryIn };
986 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
989 // fold (adde x, y, false) -> (addc x, y)
990 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
991 SDOperand Ops[] = { N1, N0 };
992 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
1000 SDOperand DAGCombiner::visitSUB(SDNode *N) {
1001 SDOperand N0 = N->getOperand(0);
1002 SDOperand N1 = N->getOperand(1);
1003 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1004 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1005 MVT::ValueType VT = N0.getValueType();
1008 SDOperand FoldedVOp = SimplifyVBinOp(N);
1009 if (FoldedVOp.Val) return FoldedVOp;
1011 // fold (sub x, x) -> 0
1013 return DAG.getConstant(0, N->getValueType(0));
1014 // fold (sub c1, c2) -> c1-c2
1016 return DAG.getNode(ISD::SUB, VT, N0, N1);
1017 // fold (sub x, c) -> (add x, -c)
1019 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
1020 // fold (A+B)-A -> B
1021 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1022 return N0.getOperand(1);
1023 // fold (A+B)-B -> A
1024 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1025 return N0.getOperand(0);
1026 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1027 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
1028 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
1029 if (Result.Val) return Result;
1031 // If either operand of a sub is undef, the result is undef
1032 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1033 return DAG.getNode(ISD::UNDEF, VT);
1038 SDOperand DAGCombiner::visitMUL(SDNode *N) {
1039 SDOperand N0 = N->getOperand(0);
1040 SDOperand N1 = N->getOperand(1);
1041 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1042 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1043 MVT::ValueType VT = N0.getValueType();
1046 SDOperand FoldedVOp = SimplifyVBinOp(N);
1047 if (FoldedVOp.Val) return FoldedVOp;
1049 // fold (mul x, undef) -> 0
1050 if (N1.getOpcode() == ISD::UNDEF)
1051 return DAG.getConstant(0, VT);
1052 // fold (mul c1, c2) -> c1*c2
1054 return DAG.getNode(ISD::MUL, VT, N0, N1);
1055 // canonicalize constant to RHS
1057 return DAG.getNode(ISD::MUL, VT, N1, N0);
1058 // fold (mul x, 0) -> 0
1059 if (N1C && N1C->isNullValue())
1061 // fold (mul x, -1) -> 0-x
1062 if (N1C && N1C->isAllOnesValue())
1063 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1064 // fold (mul x, (1 << c)) -> x << c
1065 if (N1C && isPowerOf2_64(N1C->getValue()))
1066 return DAG.getNode(ISD::SHL, VT, N0,
1067 DAG.getConstant(Log2_64(N1C->getValue()),
1068 TLI.getShiftAmountTy()));
1069 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1070 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
1071 // FIXME: If the input is something that is easily negated (e.g. a
1072 // single-use add), we should put the negate there.
1073 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
1074 DAG.getNode(ISD::SHL, VT, N0,
1075 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
1076 TLI.getShiftAmountTy())));
1079 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1080 if (N1C && N0.getOpcode() == ISD::SHL &&
1081 isa<ConstantSDNode>(N0.getOperand(1))) {
1082 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
1083 AddToWorkList(C3.Val);
1084 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
1087 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1090 SDOperand Sh(0,0), Y(0,0);
1091 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1092 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1093 N0.Val->hasOneUse()) {
1095 } else if (N1.getOpcode() == ISD::SHL &&
1096 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
1100 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
1101 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
1104 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1105 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1106 isa<ConstantSDNode>(N0.getOperand(1))) {
1107 return DAG.getNode(ISD::ADD, VT,
1108 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
1109 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
1113 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
1120 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
1121 SDOperand N0 = N->getOperand(0);
1122 SDOperand N1 = N->getOperand(1);
1123 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1124 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1125 MVT::ValueType VT = N->getValueType(0);
1128 SDOperand FoldedVOp = SimplifyVBinOp(N);
1129 if (FoldedVOp.Val) return FoldedVOp;
1131 // fold (sdiv c1, c2) -> c1/c2
1132 if (N0C && N1C && !N1C->isNullValue())
1133 return DAG.getNode(ISD::SDIV, VT, N0, N1);
1134 // fold (sdiv X, 1) -> X
1135 if (N1C && N1C->getSignExtended() == 1LL)
1137 // fold (sdiv X, -1) -> 0-X
1138 if (N1C && N1C->isAllOnesValue())
1139 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1140 // If we know the sign bits of both operands are zero, strength reduce to a
1141 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1142 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1143 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1144 DAG.MaskedValueIsZero(N0, SignBit))
1145 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
1146 // fold (sdiv X, pow2) -> simple ops after legalize
1147 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
1148 (isPowerOf2_64(N1C->getSignExtended()) ||
1149 isPowerOf2_64(-N1C->getSignExtended()))) {
1150 // If dividing by powers of two is cheap, then don't perform the following
1152 if (TLI.isPow2DivCheap())
1154 int64_t pow2 = N1C->getSignExtended();
1155 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1156 unsigned lg2 = Log2_64(abs2);
1157 // Splat the sign bit into the register
1158 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
1159 DAG.getConstant(MVT::getSizeInBits(VT)-1,
1160 TLI.getShiftAmountTy()));
1161 AddToWorkList(SGN.Val);
1162 // Add (N0 < 0) ? abs2 - 1 : 0;
1163 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
1164 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
1165 TLI.getShiftAmountTy()));
1166 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
1167 AddToWorkList(SRL.Val);
1168 AddToWorkList(ADD.Val); // Divide by pow2
1169 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
1170 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
1171 // If we're dividing by a positive value, we're done. Otherwise, we must
1172 // negate the result.
1175 AddToWorkList(SRA.Val);
1176 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
1178 // if integer divide is expensive and we satisfy the requirements, emit an
1179 // alternate sequence.
1180 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
1181 !TLI.isIntDivCheap()) {
1182 SDOperand Op = BuildSDIV(N);
1183 if (Op.Val) return Op;
1187 if (N0.getOpcode() == ISD::UNDEF)
1188 return DAG.getConstant(0, VT);
1189 // X / undef -> undef
1190 if (N1.getOpcode() == ISD::UNDEF)
1196 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
1197 SDOperand N0 = N->getOperand(0);
1198 SDOperand N1 = N->getOperand(1);
1199 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1200 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1201 MVT::ValueType VT = N->getValueType(0);
1204 SDOperand FoldedVOp = SimplifyVBinOp(N);
1205 if (FoldedVOp.Val) return FoldedVOp;
1207 // fold (udiv c1, c2) -> c1/c2
1208 if (N0C && N1C && !N1C->isNullValue())
1209 return DAG.getNode(ISD::UDIV, VT, N0, N1);
1210 // fold (udiv x, (1 << c)) -> x >>u c
1211 if (N1C && isPowerOf2_64(N1C->getValue()))
1212 return DAG.getNode(ISD::SRL, VT, N0,
1213 DAG.getConstant(Log2_64(N1C->getValue()),
1214 TLI.getShiftAmountTy()));
1215 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1216 if (N1.getOpcode() == ISD::SHL) {
1217 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1218 if (isPowerOf2_64(SHC->getValue())) {
1219 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
1220 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
1221 DAG.getConstant(Log2_64(SHC->getValue()),
1223 AddToWorkList(Add.Val);
1224 return DAG.getNode(ISD::SRL, VT, N0, Add);
1228 // fold (udiv x, c) -> alternate
1229 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1230 SDOperand Op = BuildUDIV(N);
1231 if (Op.Val) return Op;
1235 if (N0.getOpcode() == ISD::UNDEF)
1236 return DAG.getConstant(0, VT);
1237 // X / undef -> undef
1238 if (N1.getOpcode() == ISD::UNDEF)
1244 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1245 SDOperand N0 = N->getOperand(0);
1246 SDOperand N1 = N->getOperand(1);
1247 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1248 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1249 MVT::ValueType VT = N->getValueType(0);
1251 // fold (srem c1, c2) -> c1%c2
1252 if (N0C && N1C && !N1C->isNullValue())
1253 return DAG.getNode(ISD::SREM, VT, N0, N1);
1254 // If we know the sign bits of both operands are zero, strength reduce to a
1255 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1256 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1257 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1258 DAG.MaskedValueIsZero(N0, SignBit))
1259 return DAG.getNode(ISD::UREM, VT, N0, N1);
1261 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1262 // the remainder operation.
1263 if (N1C && !N1C->isNullValue()) {
1264 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1265 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1266 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1267 AddToWorkList(Div.Val);
1268 AddToWorkList(Mul.Val);
1273 if (N0.getOpcode() == ISD::UNDEF)
1274 return DAG.getConstant(0, VT);
1275 // X % undef -> undef
1276 if (N1.getOpcode() == ISD::UNDEF)
1282 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1283 SDOperand N0 = N->getOperand(0);
1284 SDOperand N1 = N->getOperand(1);
1285 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1286 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1287 MVT::ValueType VT = N->getValueType(0);
1289 // fold (urem c1, c2) -> c1%c2
1290 if (N0C && N1C && !N1C->isNullValue())
1291 return DAG.getNode(ISD::UREM, VT, N0, N1);
1292 // fold (urem x, pow2) -> (and x, pow2-1)
1293 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1294 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1295 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1296 if (N1.getOpcode() == ISD::SHL) {
1297 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1298 if (isPowerOf2_64(SHC->getValue())) {
1299 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1300 AddToWorkList(Add.Val);
1301 return DAG.getNode(ISD::AND, VT, N0, Add);
1306 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1307 // the remainder operation.
1308 if (N1C && !N1C->isNullValue()) {
1309 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1310 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1311 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1312 AddToWorkList(Div.Val);
1313 AddToWorkList(Mul.Val);
1318 if (N0.getOpcode() == ISD::UNDEF)
1319 return DAG.getConstant(0, VT);
1320 // X % undef -> undef
1321 if (N1.getOpcode() == ISD::UNDEF)
1327 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1328 SDOperand N0 = N->getOperand(0);
1329 SDOperand N1 = N->getOperand(1);
1330 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1331 MVT::ValueType VT = N->getValueType(0);
1333 // fold (mulhs x, 0) -> 0
1334 if (N1C && N1C->isNullValue())
1336 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1337 if (N1C && N1C->getValue() == 1)
1338 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1339 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1340 TLI.getShiftAmountTy()));
1341 // fold (mulhs x, undef) -> 0
1342 if (N1.getOpcode() == ISD::UNDEF)
1343 return DAG.getConstant(0, VT);
1348 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1349 SDOperand N0 = N->getOperand(0);
1350 SDOperand N1 = N->getOperand(1);
1351 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1352 MVT::ValueType VT = N->getValueType(0);
1354 // fold (mulhu x, 0) -> 0
1355 if (N1C && N1C->isNullValue())
1357 // fold (mulhu x, 1) -> 0
1358 if (N1C && N1C->getValue() == 1)
1359 return DAG.getConstant(0, N0.getValueType());
1360 // fold (mulhu x, undef) -> 0
1361 if (N1.getOpcode() == ISD::UNDEF)
1362 return DAG.getConstant(0, VT);
1367 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1368 /// two operands of the same opcode, try to simplify it.
1369 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1370 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1371 MVT::ValueType VT = N0.getValueType();
1372 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1374 // For each of OP in AND/OR/XOR:
1375 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1376 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1377 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1378 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1379 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1380 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1381 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1382 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1383 N0.getOperand(0).getValueType(),
1384 N0.getOperand(0), N1.getOperand(0));
1385 AddToWorkList(ORNode.Val);
1386 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1389 // For each of OP in SHL/SRL/SRA/AND...
1390 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1391 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1392 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1393 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1394 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1395 N0.getOperand(1) == N1.getOperand(1)) {
1396 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1397 N0.getOperand(0).getValueType(),
1398 N0.getOperand(0), N1.getOperand(0));
1399 AddToWorkList(ORNode.Val);
1400 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1406 SDOperand DAGCombiner::visitAND(SDNode *N) {
1407 SDOperand N0 = N->getOperand(0);
1408 SDOperand N1 = N->getOperand(1);
1409 SDOperand LL, LR, RL, RR, CC0, CC1;
1410 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1411 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1412 MVT::ValueType VT = N1.getValueType();
1415 SDOperand FoldedVOp = SimplifyVBinOp(N);
1416 if (FoldedVOp.Val) return FoldedVOp;
1418 // fold (and x, undef) -> 0
1419 if (N1.getOpcode() == ISD::UNDEF)
1420 return DAG.getConstant(0, VT);
1421 // fold (and c1, c2) -> c1&c2
1423 return DAG.getNode(ISD::AND, VT, N0, N1);
1424 // canonicalize constant to RHS
1426 return DAG.getNode(ISD::AND, VT, N1, N0);
1427 // fold (and x, -1) -> x
1428 if (N1C && N1C->isAllOnesValue())
1430 // if (and x, c) is known to be zero, return 0
1431 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1432 return DAG.getConstant(0, VT);
1434 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1437 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1438 if (N1C && N0.getOpcode() == ISD::OR)
1439 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1440 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1442 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1443 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1444 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1445 if (DAG.MaskedValueIsZero(N0.getOperand(0),
1446 ~N1C->getValue() & InMask)) {
1447 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1450 // Replace uses of the AND with uses of the Zero extend node.
1453 // We actually want to replace all uses of the any_extend with the
1454 // zero_extend, to avoid duplicating things. This will later cause this
1455 // AND to be folded.
1456 CombineTo(N0.Val, Zext);
1457 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1460 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1461 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1462 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1463 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1465 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1466 MVT::isInteger(LL.getValueType())) {
1467 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1468 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1469 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1470 AddToWorkList(ORNode.Val);
1471 return DAG.getSetCC(VT, ORNode, LR, Op1);
1473 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1474 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1475 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1476 AddToWorkList(ANDNode.Val);
1477 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1479 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1480 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1481 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1482 AddToWorkList(ORNode.Val);
1483 return DAG.getSetCC(VT, ORNode, LR, Op1);
1486 // canonicalize equivalent to ll == rl
1487 if (LL == RR && LR == RL) {
1488 Op1 = ISD::getSetCCSwappedOperands(Op1);
1491 if (LL == RL && LR == RR) {
1492 bool isInteger = MVT::isInteger(LL.getValueType());
1493 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1494 if (Result != ISD::SETCC_INVALID)
1495 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1499 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1500 if (N0.getOpcode() == N1.getOpcode()) {
1501 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1502 if (Tmp.Val) return Tmp;
1505 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1506 // fold (and (sra)) -> (and (srl)) when possible.
1507 if (!MVT::isVector(VT) &&
1508 SimplifyDemandedBits(SDOperand(N, 0)))
1509 return SDOperand(N, 0);
1510 // fold (zext_inreg (extload x)) -> (zextload x)
1511 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
1512 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1513 MVT::ValueType EVT = LN0->getLoadedVT();
1514 // If we zero all the possible extended bits, then we can turn this into
1515 // a zextload if we are running before legalize or the operation is legal.
1516 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1517 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1518 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1519 LN0->getBasePtr(), LN0->getSrcValue(),
1520 LN0->getSrcValueOffset(), EVT,
1522 LN0->getAlignment());
1524 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1525 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1528 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1529 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
1531 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1532 MVT::ValueType EVT = LN0->getLoadedVT();
1533 // If we zero all the possible extended bits, then we can turn this into
1534 // a zextload if we are running before legalize or the operation is legal.
1535 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1536 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1537 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1538 LN0->getBasePtr(), LN0->getSrcValue(),
1539 LN0->getSrcValueOffset(), EVT,
1541 LN0->getAlignment());
1543 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1544 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1548 // fold (and (load x), 255) -> (zextload x, i8)
1549 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1550 if (N1C && N0.getOpcode() == ISD::LOAD) {
1551 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1552 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1553 LN0->getAddressingMode() == ISD::UNINDEXED &&
1555 MVT::ValueType EVT, LoadedVT;
1556 if (N1C->getValue() == 255)
1558 else if (N1C->getValue() == 65535)
1560 else if (N1C->getValue() == ~0U)
1565 LoadedVT = LN0->getLoadedVT();
1566 if (EVT != MVT::Other && LoadedVT > EVT &&
1567 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1568 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1569 // For big endian targets, we need to add an offset to the pointer to
1570 // load the correct bytes. For little endian systems, we merely need to
1571 // read fewer bytes from the same pointer.
1573 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1574 SDOperand NewPtr = LN0->getBasePtr();
1575 if (!TLI.isLittleEndian())
1576 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1577 DAG.getConstant(PtrOff, PtrType));
1578 AddToWorkList(NewPtr.Val);
1580 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1581 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
1582 LN0->isVolatile(), LN0->getAlignment());
1584 CombineTo(N0.Val, Load, Load.getValue(1));
1585 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1593 SDOperand DAGCombiner::visitOR(SDNode *N) {
1594 SDOperand N0 = N->getOperand(0);
1595 SDOperand N1 = N->getOperand(1);
1596 SDOperand LL, LR, RL, RR, CC0, CC1;
1597 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1598 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1599 MVT::ValueType VT = N1.getValueType();
1600 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1603 SDOperand FoldedVOp = SimplifyVBinOp(N);
1604 if (FoldedVOp.Val) return FoldedVOp;
1606 // fold (or x, undef) -> -1
1607 if (N1.getOpcode() == ISD::UNDEF)
1608 return DAG.getConstant(-1, VT);
1609 // fold (or c1, c2) -> c1|c2
1611 return DAG.getNode(ISD::OR, VT, N0, N1);
1612 // canonicalize constant to RHS
1614 return DAG.getNode(ISD::OR, VT, N1, N0);
1615 // fold (or x, 0) -> x
1616 if (N1C && N1C->isNullValue())
1618 // fold (or x, -1) -> -1
1619 if (N1C && N1C->isAllOnesValue())
1621 // fold (or x, c) -> c iff (x & ~c) == 0
1623 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1626 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1629 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1630 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1631 isa<ConstantSDNode>(N0.getOperand(1))) {
1632 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1633 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1635 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1637 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1638 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1639 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1640 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1642 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1643 MVT::isInteger(LL.getValueType())) {
1644 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1645 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1646 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1647 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1648 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1649 AddToWorkList(ORNode.Val);
1650 return DAG.getSetCC(VT, ORNode, LR, Op1);
1652 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1653 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1654 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1655 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1656 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1657 AddToWorkList(ANDNode.Val);
1658 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1661 // canonicalize equivalent to ll == rl
1662 if (LL == RR && LR == RL) {
1663 Op1 = ISD::getSetCCSwappedOperands(Op1);
1666 if (LL == RL && LR == RR) {
1667 bool isInteger = MVT::isInteger(LL.getValueType());
1668 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1669 if (Result != ISD::SETCC_INVALID)
1670 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1674 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1675 if (N0.getOpcode() == N1.getOpcode()) {
1676 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1677 if (Tmp.Val) return Tmp;
1680 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1681 if (N0.getOpcode() == ISD::AND &&
1682 N1.getOpcode() == ISD::AND &&
1683 N0.getOperand(1).getOpcode() == ISD::Constant &&
1684 N1.getOperand(1).getOpcode() == ISD::Constant &&
1685 // Don't increase # computations.
1686 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1687 // We can only do this xform if we know that bits from X that are set in C2
1688 // but not in C1 are already zero. Likewise for Y.
1689 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1690 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1692 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1693 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1694 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1695 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1700 // See if this is some rotate idiom.
1701 if (SDNode *Rot = MatchRotate(N0, N1))
1702 return SDOperand(Rot, 0);
1708 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1709 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1710 if (Op.getOpcode() == ISD::AND) {
1711 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1712 Mask = Op.getOperand(1);
1713 Op = Op.getOperand(0);
1719 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1727 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1728 // idioms for rotate, and if the target supports rotation instructions, generate
1730 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1731 // Must be a legal type. Expanded an promoted things won't work with rotates.
1732 MVT::ValueType VT = LHS.getValueType();
1733 if (!TLI.isTypeLegal(VT)) return 0;
1735 // The target must have at least one rotate flavor.
1736 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1737 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1738 if (!HasROTL && !HasROTR) return 0;
1740 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1741 SDOperand LHSShift; // The shift.
1742 SDOperand LHSMask; // AND value if any.
1743 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1744 return 0; // Not part of a rotate.
1746 SDOperand RHSShift; // The shift.
1747 SDOperand RHSMask; // AND value if any.
1748 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1749 return 0; // Not part of a rotate.
1751 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1752 return 0; // Not shifting the same value.
1754 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1755 return 0; // Shifts must disagree.
1757 // Canonicalize shl to left side in a shl/srl pair.
1758 if (RHSShift.getOpcode() == ISD::SHL) {
1759 std::swap(LHS, RHS);
1760 std::swap(LHSShift, RHSShift);
1761 std::swap(LHSMask , RHSMask );
1764 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1765 SDOperand LHSShiftArg = LHSShift.getOperand(0);
1766 SDOperand LHSShiftAmt = LHSShift.getOperand(1);
1767 SDOperand RHSShiftAmt = RHSShift.getOperand(1);
1769 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1770 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1771 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
1772 RHSShiftAmt.getOpcode() == ISD::Constant) {
1773 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
1774 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
1775 if ((LShVal + RShVal) != OpSizeInBits)
1780 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
1782 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
1784 // If there is an AND of either shifted operand, apply it to the result.
1785 if (LHSMask.Val || RHSMask.Val) {
1786 uint64_t Mask = MVT::getIntVTBitMask(VT);
1789 uint64_t RHSBits = (1ULL << LShVal)-1;
1790 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1793 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1794 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1797 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1803 // If there is a mask here, and we have a variable shift, we can't be sure
1804 // that we're masking out the right stuff.
1805 if (LHSMask.Val || RHSMask.Val)
1808 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1809 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1810 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
1811 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
1812 if (ConstantSDNode *SUBC =
1813 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
1814 if (SUBC->getValue() == OpSizeInBits)
1816 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1818 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1822 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1823 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1824 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
1825 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
1826 if (ConstantSDNode *SUBC =
1827 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
1828 if (SUBC->getValue() == OpSizeInBits)
1830 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1832 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1836 // Look for sign/zext/any-extended cases:
1837 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1838 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1839 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
1840 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1841 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1842 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
1843 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
1844 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
1845 if (RExtOp0.getOpcode() == ISD::SUB &&
1846 RExtOp0.getOperand(1) == LExtOp0) {
1847 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1849 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1850 // (rotl x, (sub 32, y))
1851 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
1852 if (SUBC->getValue() == OpSizeInBits) {
1854 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1856 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1859 } else if (LExtOp0.getOpcode() == ISD::SUB &&
1860 RExtOp0 == LExtOp0.getOperand(1)) {
1861 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
1863 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
1864 // (rotr x, (sub 32, y))
1865 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
1866 if (SUBC->getValue() == OpSizeInBits) {
1868 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
1870 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1880 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1881 SDOperand N0 = N->getOperand(0);
1882 SDOperand N1 = N->getOperand(1);
1883 SDOperand LHS, RHS, CC;
1884 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1885 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1886 MVT::ValueType VT = N0.getValueType();
1889 SDOperand FoldedVOp = SimplifyVBinOp(N);
1890 if (FoldedVOp.Val) return FoldedVOp;
1892 // fold (xor x, undef) -> undef
1893 if (N1.getOpcode() == ISD::UNDEF)
1895 // fold (xor c1, c2) -> c1^c2
1897 return DAG.getNode(ISD::XOR, VT, N0, N1);
1898 // canonicalize constant to RHS
1900 return DAG.getNode(ISD::XOR, VT, N1, N0);
1901 // fold (xor x, 0) -> x
1902 if (N1C && N1C->isNullValue())
1905 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1908 // fold !(x cc y) -> (x !cc y)
1909 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1910 bool isInt = MVT::isInteger(LHS.getValueType());
1911 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1913 if (N0.getOpcode() == ISD::SETCC)
1914 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1915 if (N0.getOpcode() == ISD::SELECT_CC)
1916 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1917 assert(0 && "Unhandled SetCC Equivalent!");
1920 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1921 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
1922 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1923 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1924 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1925 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1926 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1927 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1928 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1929 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1932 // fold !(x or y) -> (!x and !y) iff x or y are constants
1933 if (N1C && N1C->isAllOnesValue() &&
1934 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1935 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1936 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1937 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1938 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1939 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1940 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1941 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1944 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1945 if (N1C && N0.getOpcode() == ISD::XOR) {
1946 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1947 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1949 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1950 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1952 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1953 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1955 // fold (xor x, x) -> 0
1957 if (!MVT::isVector(VT)) {
1958 return DAG.getConstant(0, VT);
1959 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1960 // Produce a vector of zeros.
1961 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
1962 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1963 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1967 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1968 if (N0.getOpcode() == N1.getOpcode()) {
1969 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1970 if (Tmp.Val) return Tmp;
1973 // Simplify the expression using non-local knowledge.
1974 if (!MVT::isVector(VT) &&
1975 SimplifyDemandedBits(SDOperand(N, 0)))
1976 return SDOperand(N, 0);
1981 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1982 SDOperand N0 = N->getOperand(0);
1983 SDOperand N1 = N->getOperand(1);
1984 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1985 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1986 MVT::ValueType VT = N0.getValueType();
1987 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1989 // fold (shl c1, c2) -> c1<<c2
1991 return DAG.getNode(ISD::SHL, VT, N0, N1);
1992 // fold (shl 0, x) -> 0
1993 if (N0C && N0C->isNullValue())
1995 // fold (shl x, c >= size(x)) -> undef
1996 if (N1C && N1C->getValue() >= OpSizeInBits)
1997 return DAG.getNode(ISD::UNDEF, VT);
1998 // fold (shl x, 0) -> x
1999 if (N1C && N1C->isNullValue())
2001 // if (shl x, c) is known to be zero, return 0
2002 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
2003 return DAG.getConstant(0, VT);
2004 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2005 return SDOperand(N, 0);
2006 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
2007 if (N1C && N0.getOpcode() == ISD::SHL &&
2008 N0.getOperand(1).getOpcode() == ISD::Constant) {
2009 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2010 uint64_t c2 = N1C->getValue();
2011 if (c1 + c2 > OpSizeInBits)
2012 return DAG.getConstant(0, VT);
2013 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
2014 DAG.getConstant(c1 + c2, N1.getValueType()));
2016 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
2017 // (srl (and x, -1 << c1), c1-c2)
2018 if (N1C && N0.getOpcode() == ISD::SRL &&
2019 N0.getOperand(1).getOpcode() == ISD::Constant) {
2020 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2021 uint64_t c2 = N1C->getValue();
2022 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2023 DAG.getConstant(~0ULL << c1, VT));
2025 return DAG.getNode(ISD::SHL, VT, Mask,
2026 DAG.getConstant(c2-c1, N1.getValueType()));
2028 return DAG.getNode(ISD::SRL, VT, Mask,
2029 DAG.getConstant(c1-c2, N1.getValueType()));
2031 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
2032 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2033 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2034 DAG.getConstant(~0ULL << N1C->getValue(), VT));
2038 SDOperand DAGCombiner::visitSRA(SDNode *N) {
2039 SDOperand N0 = N->getOperand(0);
2040 SDOperand N1 = N->getOperand(1);
2041 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2042 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2043 MVT::ValueType VT = N0.getValueType();
2045 // fold (sra c1, c2) -> c1>>c2
2047 return DAG.getNode(ISD::SRA, VT, N0, N1);
2048 // fold (sra 0, x) -> 0
2049 if (N0C && N0C->isNullValue())
2051 // fold (sra -1, x) -> -1
2052 if (N0C && N0C->isAllOnesValue())
2054 // fold (sra x, c >= size(x)) -> undef
2055 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
2056 return DAG.getNode(ISD::UNDEF, VT);
2057 // fold (sra x, 0) -> x
2058 if (N1C && N1C->isNullValue())
2060 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2062 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2063 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
2066 default: EVT = MVT::Other; break;
2067 case 1: EVT = MVT::i1; break;
2068 case 8: EVT = MVT::i8; break;
2069 case 16: EVT = MVT::i16; break;
2070 case 32: EVT = MVT::i32; break;
2072 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
2073 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
2074 DAG.getValueType(EVT));
2077 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
2078 if (N1C && N0.getOpcode() == ISD::SRA) {
2079 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2080 unsigned Sum = N1C->getValue() + C1->getValue();
2081 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
2082 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
2083 DAG.getConstant(Sum, N1C->getValueType(0)));
2087 // Simplify, based on bits shifted out of the LHS.
2088 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2089 return SDOperand(N, 0);
2092 // If the sign bit is known to be zero, switch this to a SRL.
2093 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
2094 return DAG.getNode(ISD::SRL, VT, N0, N1);
2098 SDOperand DAGCombiner::visitSRL(SDNode *N) {
2099 SDOperand N0 = N->getOperand(0);
2100 SDOperand N1 = N->getOperand(1);
2101 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2102 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2103 MVT::ValueType VT = N0.getValueType();
2104 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2106 // fold (srl c1, c2) -> c1 >>u c2
2108 return DAG.getNode(ISD::SRL, VT, N0, N1);
2109 // fold (srl 0, x) -> 0
2110 if (N0C && N0C->isNullValue())
2112 // fold (srl x, c >= size(x)) -> undef
2113 if (N1C && N1C->getValue() >= OpSizeInBits)
2114 return DAG.getNode(ISD::UNDEF, VT);
2115 // fold (srl x, 0) -> x
2116 if (N1C && N1C->isNullValue())
2118 // if (srl x, c) is known to be zero, return 0
2119 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
2120 return DAG.getConstant(0, VT);
2122 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
2123 if (N1C && N0.getOpcode() == ISD::SRL &&
2124 N0.getOperand(1).getOpcode() == ISD::Constant) {
2125 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2126 uint64_t c2 = N1C->getValue();
2127 if (c1 + c2 > OpSizeInBits)
2128 return DAG.getConstant(0, VT);
2129 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
2130 DAG.getConstant(c1 + c2, N1.getValueType()));
2133 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2134 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2135 // Shifting in all undef bits?
2136 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
2137 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
2138 return DAG.getNode(ISD::UNDEF, VT);
2140 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
2141 AddToWorkList(SmallShift.Val);
2142 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
2145 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2146 // bit, which is unmodified by sra.
2147 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
2148 if (N0.getOpcode() == ISD::SRA)
2149 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
2152 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2153 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2154 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
2155 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
2156 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2158 // If any of the input bits are KnownOne, then the input couldn't be all
2159 // zeros, thus the result of the srl will always be zero.
2160 if (KnownOne) return DAG.getConstant(0, VT);
2162 // If all of the bits input the to ctlz node are known to be zero, then
2163 // the result of the ctlz is "32" and the result of the shift is one.
2164 uint64_t UnknownBits = ~KnownZero & Mask;
2165 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2167 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2168 if ((UnknownBits & (UnknownBits-1)) == 0) {
2169 // Okay, we know that only that the single bit specified by UnknownBits
2170 // could be set on input to the CTLZ node. If this bit is set, the SRL
2171 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2172 // to an SRL,XOR pair, which is likely to simplify more.
2173 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
2174 SDOperand Op = N0.getOperand(0);
2176 Op = DAG.getNode(ISD::SRL, VT, Op,
2177 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
2178 AddToWorkList(Op.Val);
2180 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
2184 // fold operands of srl based on knowledge that the low bits are not
2186 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2187 return SDOperand(N, 0);
2192 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
2193 SDOperand N0 = N->getOperand(0);
2194 MVT::ValueType VT = N->getValueType(0);
2196 // fold (ctlz c1) -> c2
2197 if (isa<ConstantSDNode>(N0))
2198 return DAG.getNode(ISD::CTLZ, VT, N0);
2202 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
2203 SDOperand N0 = N->getOperand(0);
2204 MVT::ValueType VT = N->getValueType(0);
2206 // fold (cttz c1) -> c2
2207 if (isa<ConstantSDNode>(N0))
2208 return DAG.getNode(ISD::CTTZ, VT, N0);
2212 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
2213 SDOperand N0 = N->getOperand(0);
2214 MVT::ValueType VT = N->getValueType(0);
2216 // fold (ctpop c1) -> c2
2217 if (isa<ConstantSDNode>(N0))
2218 return DAG.getNode(ISD::CTPOP, VT, N0);
2222 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
2223 SDOperand N0 = N->getOperand(0);
2224 SDOperand N1 = N->getOperand(1);
2225 SDOperand N2 = N->getOperand(2);
2226 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2227 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2228 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2229 MVT::ValueType VT = N->getValueType(0);
2231 // fold select C, X, X -> X
2234 // fold select true, X, Y -> X
2235 if (N0C && !N0C->isNullValue())
2237 // fold select false, X, Y -> Y
2238 if (N0C && N0C->isNullValue())
2240 // fold select C, 1, X -> C | X
2241 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
2242 return DAG.getNode(ISD::OR, VT, N0, N2);
2243 // fold select C, 0, X -> ~C & X
2244 // FIXME: this should check for C type == X type, not i1?
2245 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
2246 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2247 AddToWorkList(XORNode.Val);
2248 return DAG.getNode(ISD::AND, VT, XORNode, N2);
2250 // fold select C, X, 1 -> ~C | X
2251 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
2252 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2253 AddToWorkList(XORNode.Val);
2254 return DAG.getNode(ISD::OR, VT, XORNode, N1);
2256 // fold select C, X, 0 -> C & X
2257 // FIXME: this should check for C type == X type, not i1?
2258 if (MVT::i1 == VT && N2C && N2C->isNullValue())
2259 return DAG.getNode(ISD::AND, VT, N0, N1);
2260 // fold X ? X : Y --> X ? 1 : Y --> X | Y
2261 if (MVT::i1 == VT && N0 == N1)
2262 return DAG.getNode(ISD::OR, VT, N0, N2);
2263 // fold X ? Y : X --> X ? Y : 0 --> X & Y
2264 if (MVT::i1 == VT && N0 == N2)
2265 return DAG.getNode(ISD::AND, VT, N0, N1);
2267 // If we can fold this based on the true/false value, do so.
2268 if (SimplifySelectOps(N, N1, N2))
2269 return SDOperand(N, 0); // Don't revisit N.
2271 // fold selects based on a setcc into other things, such as min/max/abs
2272 if (N0.getOpcode() == ISD::SETCC)
2274 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2275 // having to say they don't support SELECT_CC on every type the DAG knows
2276 // about, since there is no way to mark an opcode illegal at all value types
2277 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
2278 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
2279 N1, N2, N0.getOperand(2));
2281 return SimplifySelect(N0, N1, N2);
2285 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
2286 SDOperand N0 = N->getOperand(0);
2287 SDOperand N1 = N->getOperand(1);
2288 SDOperand N2 = N->getOperand(2);
2289 SDOperand N3 = N->getOperand(3);
2290 SDOperand N4 = N->getOperand(4);
2291 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2293 // fold select_cc lhs, rhs, x, x, cc -> x
2297 // Determine if the condition we're dealing with is constant
2298 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2299 if (SCC.Val) AddToWorkList(SCC.Val);
2301 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
2302 if (SCCC->getValue())
2303 return N2; // cond always true -> true val
2305 return N3; // cond always false -> false val
2308 // Fold to a simpler select_cc
2309 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2310 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
2311 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2314 // If we can fold this based on the true/false value, do so.
2315 if (SimplifySelectOps(N, N2, N3))
2316 return SDOperand(N, 0); // Don't revisit N.
2318 // fold select_cc into other things, such as min/max/abs
2319 return SimplifySelectCC(N0, N1, N2, N3, CC);
2322 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
2323 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2324 cast<CondCodeSDNode>(N->getOperand(2))->get());
2327 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2328 SDOperand N0 = N->getOperand(0);
2329 MVT::ValueType VT = N->getValueType(0);
2331 // fold (sext c1) -> c1
2332 if (isa<ConstantSDNode>(N0))
2333 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2335 // fold (sext (sext x)) -> (sext x)
2336 // fold (sext (aext x)) -> (sext x)
2337 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2338 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2340 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2341 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2342 if (N0.getOpcode() == ISD::TRUNCATE) {
2343 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2344 if (NarrowLoad.Val) {
2345 if (NarrowLoad.Val != N0.Val)
2346 CombineTo(N0.Val, NarrowLoad);
2347 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
2351 // See if the value being truncated is already sign extended. If so, just
2352 // eliminate the trunc/sext pair.
2353 if (N0.getOpcode() == ISD::TRUNCATE) {
2354 SDOperand Op = N0.getOperand(0);
2355 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2356 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2357 unsigned DestBits = MVT::getSizeInBits(VT);
2358 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2360 if (OpBits == DestBits) {
2361 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2362 // bits, it is already ready.
2363 if (NumSignBits > DestBits-MidBits)
2365 } else if (OpBits < DestBits) {
2366 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2367 // bits, just sext from i32.
2368 if (NumSignBits > OpBits-MidBits)
2369 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2371 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2372 // bits, just truncate to i32.
2373 if (NumSignBits > OpBits-MidBits)
2374 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2377 // fold (sext (truncate x)) -> (sextinreg x).
2378 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2379 N0.getValueType())) {
2380 if (Op.getValueType() < VT)
2381 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2382 else if (Op.getValueType() > VT)
2383 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2384 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2385 DAG.getValueType(N0.getValueType()));
2389 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2390 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2391 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2392 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2393 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2394 LN0->getBasePtr(), LN0->getSrcValue(),
2395 LN0->getSrcValueOffset(),
2398 CombineTo(N, ExtLoad);
2399 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2400 ExtLoad.getValue(1));
2401 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2404 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2405 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2406 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2407 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2408 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2409 MVT::ValueType EVT = LN0->getLoadedVT();
2410 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2411 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2412 LN0->getBasePtr(), LN0->getSrcValue(),
2413 LN0->getSrcValueOffset(), EVT,
2415 LN0->getAlignment());
2416 CombineTo(N, ExtLoad);
2417 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2418 ExtLoad.getValue(1));
2419 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2423 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
2424 if (N0.getOpcode() == ISD::SETCC) {
2426 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2427 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
2428 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2429 if (SCC.Val) return SCC;
2435 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2436 SDOperand N0 = N->getOperand(0);
2437 MVT::ValueType VT = N->getValueType(0);
2439 // fold (zext c1) -> c1
2440 if (isa<ConstantSDNode>(N0))
2441 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2442 // fold (zext (zext x)) -> (zext x)
2443 // fold (zext (aext x)) -> (zext x)
2444 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2445 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2447 // fold (zext (truncate (load x))) -> (zext (smaller load x))
2448 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
2449 if (N0.getOpcode() == ISD::TRUNCATE) {
2450 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2451 if (NarrowLoad.Val) {
2452 if (NarrowLoad.Val != N0.Val)
2453 CombineTo(N0.Val, NarrowLoad);
2454 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
2458 // fold (zext (truncate x)) -> (and x, mask)
2459 if (N0.getOpcode() == ISD::TRUNCATE &&
2460 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2461 SDOperand Op = N0.getOperand(0);
2462 if (Op.getValueType() < VT) {
2463 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2464 } else if (Op.getValueType() > VT) {
2465 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2467 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2470 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2471 if (N0.getOpcode() == ISD::AND &&
2472 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2473 N0.getOperand(1).getOpcode() == ISD::Constant) {
2474 SDOperand X = N0.getOperand(0).getOperand(0);
2475 if (X.getValueType() < VT) {
2476 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2477 } else if (X.getValueType() > VT) {
2478 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2480 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2481 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2484 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2485 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2486 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2487 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2488 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2489 LN0->getBasePtr(), LN0->getSrcValue(),
2490 LN0->getSrcValueOffset(),
2493 LN0->getAlignment());
2494 CombineTo(N, ExtLoad);
2495 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2496 ExtLoad.getValue(1));
2497 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2500 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2501 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2502 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2503 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2504 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2505 MVT::ValueType EVT = LN0->getLoadedVT();
2506 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2507 LN0->getBasePtr(), LN0->getSrcValue(),
2508 LN0->getSrcValueOffset(), EVT,
2510 LN0->getAlignment());
2511 CombineTo(N, ExtLoad);
2512 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2513 ExtLoad.getValue(1));
2514 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2517 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2518 if (N0.getOpcode() == ISD::SETCC) {
2520 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2521 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2522 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2523 if (SCC.Val) return SCC;
2529 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2530 SDOperand N0 = N->getOperand(0);
2531 MVT::ValueType VT = N->getValueType(0);
2533 // fold (aext c1) -> c1
2534 if (isa<ConstantSDNode>(N0))
2535 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2536 // fold (aext (aext x)) -> (aext x)
2537 // fold (aext (zext x)) -> (zext x)
2538 // fold (aext (sext x)) -> (sext x)
2539 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2540 N0.getOpcode() == ISD::ZERO_EXTEND ||
2541 N0.getOpcode() == ISD::SIGN_EXTEND)
2542 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2544 // fold (aext (truncate (load x))) -> (aext (smaller load x))
2545 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
2546 if (N0.getOpcode() == ISD::TRUNCATE) {
2547 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2548 if (NarrowLoad.Val) {
2549 if (NarrowLoad.Val != N0.Val)
2550 CombineTo(N0.Val, NarrowLoad);
2551 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
2555 // fold (aext (truncate x))
2556 if (N0.getOpcode() == ISD::TRUNCATE) {
2557 SDOperand TruncOp = N0.getOperand(0);
2558 if (TruncOp.getValueType() == VT)
2559 return TruncOp; // x iff x size == zext size.
2560 if (TruncOp.getValueType() > VT)
2561 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2562 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2565 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2566 if (N0.getOpcode() == ISD::AND &&
2567 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2568 N0.getOperand(1).getOpcode() == ISD::Constant) {
2569 SDOperand X = N0.getOperand(0).getOperand(0);
2570 if (X.getValueType() < VT) {
2571 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2572 } else if (X.getValueType() > VT) {
2573 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2575 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2576 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2579 // fold (aext (load x)) -> (aext (truncate (extload x)))
2580 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2581 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2582 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2583 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2584 LN0->getBasePtr(), LN0->getSrcValue(),
2585 LN0->getSrcValueOffset(),
2588 LN0->getAlignment());
2589 CombineTo(N, ExtLoad);
2590 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2591 ExtLoad.getValue(1));
2592 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2595 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2596 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2597 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2598 if (N0.getOpcode() == ISD::LOAD &&
2599 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2601 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2602 MVT::ValueType EVT = LN0->getLoadedVT();
2603 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2604 LN0->getChain(), LN0->getBasePtr(),
2606 LN0->getSrcValueOffset(), EVT,
2608 LN0->getAlignment());
2609 CombineTo(N, ExtLoad);
2610 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2611 ExtLoad.getValue(1));
2612 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2615 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2616 if (N0.getOpcode() == ISD::SETCC) {
2618 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2619 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2620 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2628 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
2629 /// bits and then truncated to a narrower type and where N is a multiple
2630 /// of number of bits of the narrower type, transform it to a narrower load
2631 /// from address + N / num of bits of new type. If the result is to be
2632 /// extended, also fold the extension to form a extending load.
2633 SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
2634 unsigned Opc = N->getOpcode();
2635 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2636 SDOperand N0 = N->getOperand(0);
2637 MVT::ValueType VT = N->getValueType(0);
2638 MVT::ValueType EVT = N->getValueType(0);
2640 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
2642 if (Opc == ISD::SIGN_EXTEND_INREG) {
2643 ExtType = ISD::SEXTLOAD;
2644 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2645 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
2649 unsigned EVTBits = MVT::getSizeInBits(EVT);
2651 bool CombineSRL = false;
2652 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
2653 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2654 ShAmt = N01->getValue();
2655 // Is the shift amount a multiple of size of VT?
2656 if ((ShAmt & (EVTBits-1)) == 0) {
2657 N0 = N0.getOperand(0);
2658 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
2665 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2666 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
2667 // zero extended form: by shrinking the load, we lose track of the fact
2668 // that it is already zero extended.
2669 // FIXME: This should be reevaluated.
2671 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
2672 "Cannot truncate to larger type!");
2673 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2674 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2675 // For big endian targets, we need to adjust the offset to the pointer to
2676 // load the correct bytes.
2677 if (!TLI.isLittleEndian())
2678 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits;
2679 uint64_t PtrOff = ShAmt / 8;
2680 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2681 DAG.getConstant(PtrOff, PtrType));
2682 AddToWorkList(NewPtr.Val);
2683 SDOperand Load = (ExtType == ISD::NON_EXTLOAD)
2684 ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
2685 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2686 LN0->isVolatile(), LN0->getAlignment())
2687 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
2688 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
2689 LN0->isVolatile(), LN0->getAlignment());
2692 std::vector<SDNode*> NowDead;
2693 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead);
2694 CombineTo(N->getOperand(0).Val, Load);
2696 CombineTo(N0.Val, Load, Load.getValue(1));
2698 if (Opc == ISD::SIGN_EXTEND_INREG)
2699 return DAG.getNode(Opc, VT, Load, N->getOperand(1));
2701 return DAG.getNode(Opc, VT, Load);
2703 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2710 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2711 SDOperand N0 = N->getOperand(0);
2712 SDOperand N1 = N->getOperand(1);
2713 MVT::ValueType VT = N->getValueType(0);
2714 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2715 unsigned EVTBits = MVT::getSizeInBits(EVT);
2717 // fold (sext_in_reg c1) -> c1
2718 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2719 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2721 // If the input is already sign extended, just drop the extension.
2722 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2725 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2726 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2727 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2728 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2731 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
2732 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2733 return DAG.getZeroExtendInReg(N0, EVT);
2735 // fold operands of sext_in_reg based on knowledge that the top bits are not
2737 if (SimplifyDemandedBits(SDOperand(N, 0)))
2738 return SDOperand(N, 0);
2740 // fold (sext_in_reg (load x)) -> (smaller sextload x)
2741 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
2742 SDOperand NarrowLoad = ReduceLoadWidth(N);
2746 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2747 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2748 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2749 if (N0.getOpcode() == ISD::SRL) {
2750 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2751 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2752 // We can turn this into an SRA iff the input to the SRL is already sign
2754 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
2755 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2756 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2760 // fold (sext_inreg (extload x)) -> (sextload x)
2761 if (ISD::isEXTLoad(N0.Val) &&
2762 ISD::isUNINDEXEDLoad(N0.Val) &&
2763 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2764 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2765 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2766 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2767 LN0->getBasePtr(), LN0->getSrcValue(),
2768 LN0->getSrcValueOffset(), EVT,
2770 LN0->getAlignment());
2771 CombineTo(N, ExtLoad);
2772 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2773 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2775 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2776 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2778 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2779 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2780 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2781 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2782 LN0->getBasePtr(), LN0->getSrcValue(),
2783 LN0->getSrcValueOffset(), EVT,
2785 LN0->getAlignment());
2786 CombineTo(N, ExtLoad);
2787 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2788 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2793 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2794 SDOperand N0 = N->getOperand(0);
2795 MVT::ValueType VT = N->getValueType(0);
2798 if (N0.getValueType() == N->getValueType(0))
2800 // fold (truncate c1) -> c1
2801 if (isa<ConstantSDNode>(N0))
2802 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2803 // fold (truncate (truncate x)) -> (truncate x)
2804 if (N0.getOpcode() == ISD::TRUNCATE)
2805 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2806 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2807 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2808 N0.getOpcode() == ISD::ANY_EXTEND) {
2809 if (N0.getOperand(0).getValueType() < VT)
2810 // if the source is smaller than the dest, we still need an extend
2811 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2812 else if (N0.getOperand(0).getValueType() > VT)
2813 // if the source is larger than the dest, than we just need the truncate
2814 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2816 // if the source and dest are the same type, we can drop both the extend
2818 return N0.getOperand(0);
2821 // fold (truncate (load x)) -> (smaller load x)
2822 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
2823 return ReduceLoadWidth(N);
2826 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2827 SDOperand N0 = N->getOperand(0);
2828 MVT::ValueType VT = N->getValueType(0);
2830 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
2831 // Only do this before legalize, since afterward the target may be depending
2832 // on the bitconvert.
2833 // First check to see if this is all constant.
2834 if (!AfterLegalize &&
2835 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
2836 MVT::isVector(VT)) {
2837 bool isSimple = true;
2838 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
2839 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2840 N0.getOperand(i).getOpcode() != ISD::Constant &&
2841 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2846 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0));
2847 assert(!MVT::isVector(DestEltVT) &&
2848 "Element type of vector ValueType must not be vector!");
2850 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
2854 // If the input is a constant, let getNode() fold it.
2855 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2856 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2857 if (Res.Val != N) return Res;
2860 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2861 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2863 // fold (conv (load x)) -> (load (conv*)x)
2864 // If the resultant load doesn't need a higher alignment than the original!
2865 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2866 ISD::isUNINDEXEDLoad(N0.Val) &&
2867 TLI.isOperationLegal(ISD::LOAD, VT)) {
2868 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2869 unsigned Align = TLI.getTargetMachine().getTargetData()->
2870 getABITypeAlignment(MVT::getTypeForValueType(VT));
2871 unsigned OrigAlign = LN0->getAlignment();
2872 if (Align <= OrigAlign) {
2873 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2874 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2875 LN0->isVolatile(), LN0->getAlignment());
2877 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2886 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
2887 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2888 /// destination element value type.
2889 SDOperand DAGCombiner::
2890 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2891 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2893 // If this is already the right type, we're done.
2894 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2896 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2897 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2899 // If this is a conversion of N elements of one type to N elements of another
2900 // type, convert each element. This handles FP<->INT cases.
2901 if (SrcBitSize == DstBitSize) {
2902 SmallVector<SDOperand, 8> Ops;
2903 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2904 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2905 AddToWorkList(Ops.back().Val);
2908 MVT::getVectorType(DstEltVT,
2909 MVT::getVectorNumElements(BV->getValueType(0)));
2910 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2913 // Otherwise, we're growing or shrinking the elements. To avoid having to
2914 // handle annoying details of growing/shrinking FP values, we convert them to
2916 if (MVT::isFloatingPoint(SrcEltVT)) {
2917 // Convert the input float vector to a int vector where the elements are the
2919 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2920 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2921 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
2925 // Now we know the input is an integer vector. If the output is a FP type,
2926 // convert to integer first, then to FP of the right size.
2927 if (MVT::isFloatingPoint(DstEltVT)) {
2928 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2929 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2930 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val;
2932 // Next, convert to FP elements of the same size.
2933 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
2936 // Okay, we know the src/dst types are both integers of differing types.
2937 // Handling growing first.
2938 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2939 if (SrcBitSize < DstBitSize) {
2940 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2942 SmallVector<SDOperand, 8> Ops;
2943 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
2944 i += NumInputsPerOutput) {
2945 bool isLE = TLI.isLittleEndian();
2946 uint64_t NewBits = 0;
2947 bool EltIsUndef = true;
2948 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2949 // Shift the previously computed bits over.
2950 NewBits <<= SrcBitSize;
2951 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2952 if (Op.getOpcode() == ISD::UNDEF) continue;
2955 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2959 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2961 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2964 MVT::ValueType VT = MVT::getVectorType(DstEltVT,
2966 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2969 // Finally, this must be the case where we are shrinking elements: each input
2970 // turns into multiple outputs.
2971 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2972 SmallVector<SDOperand, 8> Ops;
2973 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2974 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2975 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2976 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2979 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2981 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2982 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2983 OpVal >>= DstBitSize;
2984 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2987 // For big endian targets, swap the order of the pieces of each element.
2988 if (!TLI.isLittleEndian())
2989 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2991 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size());
2992 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2997 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2998 SDOperand N0 = N->getOperand(0);
2999 SDOperand N1 = N->getOperand(1);
3000 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3001 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3002 MVT::ValueType VT = N->getValueType(0);
3005 SDOperand FoldedVOp = SimplifyVBinOp(N);
3006 if (FoldedVOp.Val) return FoldedVOp;
3008 // fold (fadd c1, c2) -> c1+c2
3010 return DAG.getNode(ISD::FADD, VT, N0, N1);
3011 // canonicalize constant to RHS
3012 if (N0CFP && !N1CFP)
3013 return DAG.getNode(ISD::FADD, VT, N1, N0);
3014 // fold (A + (-B)) -> A-B
3015 if (isNegatibleForFree(N1) == 2)
3016 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG));
3017 // fold ((-A) + B) -> B-A
3018 if (isNegatibleForFree(N0) == 2)
3019 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG));
3021 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3022 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3023 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3024 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
3025 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
3030 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
3031 SDOperand N0 = N->getOperand(0);
3032 SDOperand N1 = N->getOperand(1);
3033 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3034 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3035 MVT::ValueType VT = N->getValueType(0);
3038 SDOperand FoldedVOp = SimplifyVBinOp(N);
3039 if (FoldedVOp.Val) return FoldedVOp;
3041 // fold (fsub c1, c2) -> c1-c2
3043 return DAG.getNode(ISD::FSUB, VT, N0, N1);
3045 if (UnsafeFPMath && N0CFP && N0CFP->getValue() == 0.0) {
3046 if (isNegatibleForFree(N1))
3047 return GetNegatedExpression(N1, DAG);
3048 return DAG.getNode(ISD::FNEG, VT, N1);
3050 // fold (A-(-B)) -> A+B
3051 if (isNegatibleForFree(N1))
3052 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG));
3057 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
3058 SDOperand N0 = N->getOperand(0);
3059 SDOperand N1 = N->getOperand(1);
3060 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3061 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3062 MVT::ValueType VT = N->getValueType(0);
3065 SDOperand FoldedVOp = SimplifyVBinOp(N);
3066 if (FoldedVOp.Val) return FoldedVOp;
3068 // fold (fmul c1, c2) -> c1*c2
3070 return DAG.getNode(ISD::FMUL, VT, N0, N1);
3071 // canonicalize constant to RHS
3072 if (N0CFP && !N1CFP)
3073 return DAG.getNode(ISD::FMUL, VT, N1, N0);
3074 // fold (fmul X, 2.0) -> (fadd X, X)
3075 if (N1CFP && N1CFP->isExactlyValue(+2.0))
3076 return DAG.getNode(ISD::FADD, VT, N0, N0);
3077 // fold (fmul X, -1.0) -> (fneg X)
3078 if (N1CFP && N1CFP->isExactlyValue(-1.0))
3079 return DAG.getNode(ISD::FNEG, VT, N0);
3082 if (char LHSNeg = isNegatibleForFree(N0)) {
3083 if (char RHSNeg = isNegatibleForFree(N1)) {
3084 // Both can be negated for free, check to see if at least one is cheaper
3086 if (LHSNeg == 2 || RHSNeg == 2)
3087 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG),
3088 GetNegatedExpression(N1, DAG));
3092 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
3093 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
3094 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3095 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
3096 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
3101 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
3102 SDOperand N0 = N->getOperand(0);
3103 SDOperand N1 = N->getOperand(1);
3104 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3105 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3106 MVT::ValueType VT = N->getValueType(0);
3109 SDOperand FoldedVOp = SimplifyVBinOp(N);
3110 if (FoldedVOp.Val) return FoldedVOp;
3112 // fold (fdiv c1, c2) -> c1/c2
3114 return DAG.getNode(ISD::FDIV, VT, N0, N1);
3118 if (char LHSNeg = isNegatibleForFree(N0)) {
3119 if (char RHSNeg = isNegatibleForFree(N1)) {
3120 // Both can be negated for free, check to see if at least one is cheaper
3122 if (LHSNeg == 2 || RHSNeg == 2)
3123 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG),
3124 GetNegatedExpression(N1, DAG));
3131 SDOperand DAGCombiner::visitFREM(SDNode *N) {
3132 SDOperand N0 = N->getOperand(0);
3133 SDOperand N1 = N->getOperand(1);
3134 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3135 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3136 MVT::ValueType VT = N->getValueType(0);
3138 // fold (frem c1, c2) -> fmod(c1,c2)
3140 return DAG.getNode(ISD::FREM, VT, N0, N1);
3145 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
3146 SDOperand N0 = N->getOperand(0);
3147 SDOperand N1 = N->getOperand(1);
3148 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3149 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3150 MVT::ValueType VT = N->getValueType(0);
3152 if (N0CFP && N1CFP) // Constant fold
3153 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
3156 // copysign(x, c1) -> fabs(x) iff ispos(c1)
3157 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
3162 u.d = N1CFP->getValue();
3164 return DAG.getNode(ISD::FABS, VT, N0);
3166 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
3169 // copysign(fabs(x), y) -> copysign(x, y)
3170 // copysign(fneg(x), y) -> copysign(x, y)
3171 // copysign(copysign(x,z), y) -> copysign(x, y)
3172 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
3173 N0.getOpcode() == ISD::FCOPYSIGN)
3174 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
3176 // copysign(x, abs(y)) -> abs(x)
3177 if (N1.getOpcode() == ISD::FABS)
3178 return DAG.getNode(ISD::FABS, VT, N0);
3180 // copysign(x, copysign(y,z)) -> copysign(x, z)
3181 if (N1.getOpcode() == ISD::FCOPYSIGN)
3182 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
3184 // copysign(x, fp_extend(y)) -> copysign(x, y)
3185 // copysign(x, fp_round(y)) -> copysign(x, y)
3186 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
3187 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
3194 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
3195 SDOperand N0 = N->getOperand(0);
3196 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3197 MVT::ValueType VT = N->getValueType(0);
3199 // fold (sint_to_fp c1) -> c1fp
3201 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
3205 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
3206 SDOperand N0 = N->getOperand(0);
3207 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3208 MVT::ValueType VT = N->getValueType(0);
3210 // fold (uint_to_fp c1) -> c1fp
3212 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
3216 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
3217 SDOperand N0 = N->getOperand(0);
3218 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3219 MVT::ValueType VT = N->getValueType(0);
3221 // fold (fp_to_sint c1fp) -> c1
3223 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
3227 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
3228 SDOperand N0 = N->getOperand(0);
3229 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3230 MVT::ValueType VT = N->getValueType(0);
3232 // fold (fp_to_uint c1fp) -> c1
3234 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
3238 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
3239 SDOperand N0 = N->getOperand(0);
3240 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3241 MVT::ValueType VT = N->getValueType(0);
3243 // fold (fp_round c1fp) -> c1fp
3245 return DAG.getNode(ISD::FP_ROUND, VT, N0);
3247 // fold (fp_round (fp_extend x)) -> x
3248 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
3249 return N0.getOperand(0);
3251 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
3252 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
3253 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
3254 AddToWorkList(Tmp.Val);
3255 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
3261 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
3262 SDOperand N0 = N->getOperand(0);
3263 MVT::ValueType VT = N->getValueType(0);
3264 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3265 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3267 // fold (fp_round_inreg c1fp) -> c1fp
3269 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
3270 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
3275 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
3276 SDOperand N0 = N->getOperand(0);
3277 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3278 MVT::ValueType VT = N->getValueType(0);
3280 // fold (fp_extend c1fp) -> c1fp
3282 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
3284 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
3285 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3286 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
3287 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3288 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
3289 LN0->getBasePtr(), LN0->getSrcValue(),
3290 LN0->getSrcValueOffset(),
3293 LN0->getAlignment());
3294 CombineTo(N, ExtLoad);
3295 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
3296 ExtLoad.getValue(1));
3297 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3304 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
3305 SDOperand N0 = N->getOperand(0);
3307 if (isNegatibleForFree(N0))
3308 return GetNegatedExpression(N0, DAG);
3313 SDOperand DAGCombiner::visitFABS(SDNode *N) {
3314 SDOperand N0 = N->getOperand(0);
3315 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3316 MVT::ValueType VT = N->getValueType(0);
3318 // fold (fabs c1) -> fabs(c1)
3320 return DAG.getNode(ISD::FABS, VT, N0);
3321 // fold (fabs (fabs x)) -> (fabs x)
3322 if (N0.getOpcode() == ISD::FABS)
3323 return N->getOperand(0);
3324 // fold (fabs (fneg x)) -> (fabs x)
3325 // fold (fabs (fcopysign x, y)) -> (fabs x)
3326 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
3327 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
3332 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
3333 SDOperand Chain = N->getOperand(0);
3334 SDOperand N1 = N->getOperand(1);
3335 SDOperand N2 = N->getOperand(2);
3336 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3338 // never taken branch, fold to chain
3339 if (N1C && N1C->isNullValue())
3341 // unconditional branch
3342 if (N1C && N1C->getValue() == 1)
3343 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
3344 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
3346 if (N1.getOpcode() == ISD::SETCC &&
3347 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
3348 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
3349 N1.getOperand(0), N1.getOperand(1), N2);
3354 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
3356 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
3357 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
3358 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
3360 // Use SimplifySetCC to simplify SETCC's.
3361 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
3362 if (Simp.Val) AddToWorkList(Simp.Val);
3364 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
3366 // fold br_cc true, dest -> br dest (unconditional branch)
3367 if (SCCC && SCCC->getValue())
3368 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
3370 // fold br_cc false, dest -> unconditional fall through
3371 if (SCCC && SCCC->isNullValue())
3372 return N->getOperand(0);
3374 // fold to a simpler setcc
3375 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
3376 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
3377 Simp.getOperand(2), Simp.getOperand(0),
3378 Simp.getOperand(1), N->getOperand(4));
3383 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
3384 /// pre-indexed load / store when the base pointer is a add or subtract
3385 /// and it has other uses besides the load / store. After the
3386 /// transformation, the new indexed load / store has effectively folded
3387 /// the add / subtract in and all of its other uses are redirected to the
3388 /// new load / store.
3389 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
3396 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3397 if (LD->getAddressingMode() != ISD::UNINDEXED)
3399 VT = LD->getLoadedVT();
3400 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
3401 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
3403 Ptr = LD->getBasePtr();
3404 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3405 if (ST->getAddressingMode() != ISD::UNINDEXED)
3407 VT = ST->getStoredVT();
3408 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
3409 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
3411 Ptr = ST->getBasePtr();
3416 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
3417 // out. There is no reason to make this a preinc/predec.
3418 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
3419 Ptr.Val->hasOneUse())
3422 // Ask the target to do addressing mode selection.
3425 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3426 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
3428 // Don't create a indexed load / store with zero offset.
3429 if (isa<ConstantSDNode>(Offset) &&
3430 cast<ConstantSDNode>(Offset)->getValue() == 0)
3433 // Try turning it into a pre-indexed load / store except when:
3434 // 1) The new base ptr is a frame index.
3435 // 2) If N is a store and the new base ptr is either the same as or is a
3436 // predecessor of the value being stored.
3437 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
3438 // that would create a cycle.
3439 // 4) All uses are load / store ops that use it as old base ptr.
3441 // Check #1. Preinc'ing a frame index would require copying the stack pointer
3442 // (plus the implicit offset) to a register to preinc anyway.
3443 if (isa<FrameIndexSDNode>(BasePtr))
3448 SDOperand Val = cast<StoreSDNode>(N)->getValue();
3449 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val))
3453 // Now check for #3 and #4.
3454 bool RealUse = false;
3455 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3456 E = Ptr.Val->use_end(); I != E; ++I) {
3460 if (Use->isPredecessor(N))
3463 if (!((Use->getOpcode() == ISD::LOAD &&
3464 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
3465 (Use->getOpcode() == ISD::STORE) &&
3466 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
3474 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
3476 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3479 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
3480 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3482 std::vector<SDNode*> NowDead;
3484 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3486 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3489 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3493 // Nodes can end up on the worklist more than once. Make sure we do
3494 // not process a node that has been replaced.
3495 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3496 removeFromWorkList(NowDead[i]);
3497 // Finally, since the node is now dead, remove it from the graph.
3500 // Replace the uses of Ptr with uses of the updated base value.
3501 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
3503 removeFromWorkList(Ptr.Val);
3504 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3505 removeFromWorkList(NowDead[i]);
3506 DAG.DeleteNode(Ptr.Val);
3511 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
3512 /// add / sub of the base pointer node into a post-indexed load / store.
3513 /// The transformation folded the add / subtract into the new indexed
3514 /// load / store effectively and all of its uses are redirected to the
3515 /// new load / store.
3516 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
3523 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3524 if (LD->getAddressingMode() != ISD::UNINDEXED)
3526 VT = LD->getLoadedVT();
3527 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
3528 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
3530 Ptr = LD->getBasePtr();
3531 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3532 if (ST->getAddressingMode() != ISD::UNINDEXED)
3534 VT = ST->getStoredVT();
3535 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
3536 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
3538 Ptr = ST->getBasePtr();
3543 if (Ptr.Val->hasOneUse())
3546 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3547 E = Ptr.Val->use_end(); I != E; ++I) {
3550 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
3555 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3556 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
3558 std::swap(BasePtr, Offset);
3561 // Don't create a indexed load / store with zero offset.
3562 if (isa<ConstantSDNode>(Offset) &&
3563 cast<ConstantSDNode>(Offset)->getValue() == 0)
3566 // Try turning it into a post-indexed load / store except when
3567 // 1) All uses are load / store ops that use it as base ptr.
3568 // 2) Op must be independent of N, i.e. Op is neither a predecessor
3569 // nor a successor of N. Otherwise, if Op is folded that would
3573 bool TryNext = false;
3574 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
3575 EE = BasePtr.Val->use_end(); II != EE; ++II) {
3580 // If all the uses are load / store addresses, then don't do the
3582 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
3583 bool RealUse = false;
3584 for (SDNode::use_iterator III = Use->use_begin(),
3585 EEE = Use->use_end(); III != EEE; ++III) {
3586 SDNode *UseUse = *III;
3587 if (!((UseUse->getOpcode() == ISD::LOAD &&
3588 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
3589 (UseUse->getOpcode() == ISD::STORE) &&
3590 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
3604 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
3605 SDOperand Result = isLoad
3606 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
3607 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3610 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
3611 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3613 std::vector<SDNode*> NowDead;
3615 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3617 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3620 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3624 // Nodes can end up on the worklist more than once. Make sure we do
3625 // not process a node that has been replaced.
3626 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3627 removeFromWorkList(NowDead[i]);
3628 // Finally, since the node is now dead, remove it from the graph.
3631 // Replace the uses of Use with uses of the updated base value.
3632 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
3633 Result.getValue(isLoad ? 1 : 0),
3635 removeFromWorkList(Op);
3636 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3637 removeFromWorkList(NowDead[i]);
3648 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
3649 LoadSDNode *LD = cast<LoadSDNode>(N);
3650 SDOperand Chain = LD->getChain();
3651 SDOperand Ptr = LD->getBasePtr();
3653 // If load is not volatile and there are no uses of the loaded value (and
3654 // the updated indexed value in case of indexed loads), change uses of the
3655 // chain value into uses of the chain input (i.e. delete the dead load).
3656 if (!LD->isVolatile()) {
3657 if (N->getValueType(1) == MVT::Other) {
3659 if (N->hasNUsesOfValue(0, 0))
3660 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
3663 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
3664 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
3665 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0));
3666 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1));
3667 SDOperand To[] = { Undef0, Undef1, Chain };
3668 return CombineTo(N, To, 3);
3673 // If this load is directly stored, replace the load value with the stored
3675 // TODO: Handle store large -> read small portion.
3676 // TODO: Handle TRUNCSTORE/LOADEXT
3677 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3678 if (ISD::isNON_TRUNCStore(Chain.Val)) {
3679 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
3680 if (PrevST->getBasePtr() == Ptr &&
3681 PrevST->getValue().getValueType() == N->getValueType(0))
3682 return CombineTo(N, Chain.getOperand(1), Chain);
3687 // Walk up chain skipping non-aliasing memory nodes.
3688 SDOperand BetterChain = FindBetterChain(N, Chain);
3690 // If there is a better chain.
3691 if (Chain != BetterChain) {
3694 // Replace the chain to void dependency.
3695 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3696 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
3697 LD->getSrcValue(), LD->getSrcValueOffset(),
3698 LD->isVolatile(), LD->getAlignment());
3700 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
3701 LD->getValueType(0),
3702 BetterChain, Ptr, LD->getSrcValue(),
3703 LD->getSrcValueOffset(),
3706 LD->getAlignment());
3709 // Create token factor to keep old chain connected.
3710 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
3711 Chain, ReplLoad.getValue(1));
3713 // Replace uses with load result and token factor. Don't add users
3715 return CombineTo(N, ReplLoad.getValue(0), Token, false);
3719 // Try transforming N to an indexed load.
3720 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3721 return SDOperand(N, 0);
3726 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
3727 StoreSDNode *ST = cast<StoreSDNode>(N);
3728 SDOperand Chain = ST->getChain();
3729 SDOperand Value = ST->getValue();
3730 SDOperand Ptr = ST->getBasePtr();
3732 // If this is a store of a bit convert, store the input value if the
3733 // resultant store does not need a higher alignment than the original.
3734 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
3735 ST->getAddressingMode() == ISD::UNINDEXED) {
3736 unsigned Align = ST->getAlignment();
3737 MVT::ValueType SVT = Value.getOperand(0).getValueType();
3738 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
3739 getABITypeAlignment(MVT::getTypeForValueType(SVT));
3740 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
3741 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
3742 ST->getSrcValueOffset());
3745 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
3746 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
3747 if (Value.getOpcode() != ISD::TargetConstantFP) {
3749 switch (CFP->getValueType(0)) {
3750 default: assert(0 && "Unknown FP type");
3752 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
3753 Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
3754 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3755 ST->getSrcValueOffset());
3759 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
3760 Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
3761 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3762 ST->getSrcValueOffset());
3763 } else if (TLI.isTypeLegal(MVT::i32)) {
3764 // Many FP stores are not make apparent until after legalize, e.g. for
3765 // argument passing. Since this is so common, custom legalize the
3766 // 64-bit integer store into two 32-bit stores.
3767 uint64_t Val = DoubleToBits(CFP->getValue());
3768 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
3769 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
3770 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
3772 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
3773 ST->getSrcValueOffset());
3774 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3775 DAG.getConstant(4, Ptr.getValueType()));
3776 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
3777 ST->getSrcValueOffset()+4);
3778 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
3786 // Walk up chain skipping non-aliasing memory nodes.
3787 SDOperand BetterChain = FindBetterChain(N, Chain);
3789 // If there is a better chain.
3790 if (Chain != BetterChain) {
3791 // Replace the chain to avoid dependency.
3792 SDOperand ReplStore;
3793 if (ST->isTruncatingStore()) {
3794 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
3795 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT());
3797 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
3798 ST->getSrcValue(), ST->getSrcValueOffset());
3801 // Create token to keep both nodes around.
3803 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
3805 // Don't add users to work list.
3806 return CombineTo(N, Token, false);
3810 // Try transforming N to an indexed store.
3811 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3812 return SDOperand(N, 0);
3817 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
3818 SDOperand InVec = N->getOperand(0);
3819 SDOperand InVal = N->getOperand(1);
3820 SDOperand EltNo = N->getOperand(2);
3822 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
3823 // vector with the inserted element.
3824 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
3825 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3826 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
3827 if (Elt < Ops.size())
3829 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
3830 &Ops[0], Ops.size());
3836 SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
3837 unsigned NumInScalars = N->getNumOperands();
3838 MVT::ValueType VT = N->getValueType(0);
3839 unsigned NumElts = MVT::getVectorNumElements(VT);
3840 MVT::ValueType EltType = MVT::getVectorElementType(VT);
3842 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
3843 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
3844 // at most two distinct vectors, turn this into a shuffle node.
3845 SDOperand VecIn1, VecIn2;
3846 for (unsigned i = 0; i != NumInScalars; ++i) {
3847 // Ignore undef inputs.
3848 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3850 // If this input is something other than a EXTRACT_VECTOR_ELT with a
3851 // constant index, bail out.
3852 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
3853 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
3854 VecIn1 = VecIn2 = SDOperand(0, 0);
3858 // If the input vector type disagrees with the result of the build_vector,
3859 // we can't make a shuffle.
3860 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
3861 if (ExtractedFromVec.getValueType() != VT) {
3862 VecIn1 = VecIn2 = SDOperand(0, 0);
3866 // Otherwise, remember this. We allow up to two distinct input vectors.
3867 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
3870 if (VecIn1.Val == 0) {
3871 VecIn1 = ExtractedFromVec;
3872 } else if (VecIn2.Val == 0) {
3873 VecIn2 = ExtractedFromVec;
3876 VecIn1 = VecIn2 = SDOperand(0, 0);
3881 // If everything is good, we can make a shuffle operation.
3883 SmallVector<SDOperand, 8> BuildVecIndices;
3884 for (unsigned i = 0; i != NumInScalars; ++i) {
3885 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
3886 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
3890 SDOperand Extract = N->getOperand(i);
3892 // If extracting from the first vector, just use the index directly.
3893 if (Extract.getOperand(0) == VecIn1) {
3894 BuildVecIndices.push_back(Extract.getOperand(1));
3898 // Otherwise, use InIdx + VecSize
3899 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
3900 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars,
3901 TLI.getPointerTy()));
3904 // Add count and size info.
3905 MVT::ValueType BuildVecVT =
3906 MVT::getVectorType(TLI.getPointerTy(), NumElts);
3908 // Return the new VECTOR_SHUFFLE node.
3914 // Use an undef build_vector as input for the second operand.
3915 std::vector<SDOperand> UnOps(NumInScalars,
3916 DAG.getNode(ISD::UNDEF,
3918 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
3919 &UnOps[0], UnOps.size());
3920 AddToWorkList(Ops[1].Val);
3922 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
3923 &BuildVecIndices[0], BuildVecIndices.size());
3924 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3);
3930 SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
3931 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
3932 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
3933 // inputs come from at most two distinct vectors, turn this into a shuffle
3936 // If we only have one input vector, we don't need to do any concatenation.
3937 if (N->getNumOperands() == 1) {
3938 return N->getOperand(0);
3944 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
3945 SDOperand ShufMask = N->getOperand(2);
3946 unsigned NumElts = ShufMask.getNumOperands();
3948 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3949 bool isIdentity = true;
3950 for (unsigned i = 0; i != NumElts; ++i) {
3951 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3952 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3957 if (isIdentity) return N->getOperand(0);
3959 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3961 for (unsigned i = 0; i != NumElts; ++i) {
3962 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3963 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3968 if (isIdentity) return N->getOperand(1);
3970 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3972 bool isUnary = true;
3973 bool isSplat = true;
3975 unsigned BaseIdx = 0;
3976 for (unsigned i = 0; i != NumElts; ++i)
3977 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3978 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3979 int V = (Idx < NumElts) ? 0 : 1;
3993 SDOperand N0 = N->getOperand(0);
3994 SDOperand N1 = N->getOperand(1);
3995 // Normalize unary shuffle so the RHS is undef.
3996 if (isUnary && VecNum == 1)
3999 // If it is a splat, check if the argument vector is a build_vector with
4000 // all scalar elements the same.
4004 // If this is a bit convert that changes the element type of the vector but
4005 // not the number of vector elements, look through it. Be careful not to
4006 // look though conversions that change things like v4f32 to v2f64.
4007 if (V->getOpcode() == ISD::BIT_CONVERT) {
4008 SDOperand ConvInput = V->getOperand(0);
4009 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts)
4013 if (V->getOpcode() == ISD::BUILD_VECTOR) {
4014 unsigned NumElems = V->getNumOperands();
4015 if (NumElems > BaseIdx) {
4017 bool AllSame = true;
4018 for (unsigned i = 0; i != NumElems; ++i) {
4019 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
4020 Base = V->getOperand(i);
4024 // Splat of <u, u, u, u>, return <u, u, u, u>
4027 for (unsigned i = 0; i != NumElems; ++i) {
4028 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
4029 V->getOperand(i) != Base) {
4034 // Splat of <x, x, x, x>, return <x, x, x, x>
4041 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
4043 if (isUnary || N0 == N1) {
4044 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
4046 SmallVector<SDOperand, 8> MappedOps;
4047 for (unsigned i = 0; i != NumElts; ++i) {
4048 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
4049 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
4050 MappedOps.push_back(ShufMask.getOperand(i));
4053 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
4054 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
4057 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
4058 &MappedOps[0], MappedOps.size());
4059 AddToWorkList(ShufMask.Val);
4060 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
4062 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
4069 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
4070 /// an AND to a vector_shuffle with the destination vector and a zero vector.
4071 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
4072 /// vector_shuffle V, Zero, <0, 4, 2, 4>
4073 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
4074 SDOperand LHS = N->getOperand(0);
4075 SDOperand RHS = N->getOperand(1);
4076 if (N->getOpcode() == ISD::AND) {
4077 if (RHS.getOpcode() == ISD::BIT_CONVERT)
4078 RHS = RHS.getOperand(0);
4079 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
4080 std::vector<SDOperand> IdxOps;
4081 unsigned NumOps = RHS.getNumOperands();
4082 unsigned NumElts = NumOps;
4083 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType());
4084 for (unsigned i = 0; i != NumElts; ++i) {
4085 SDOperand Elt = RHS.getOperand(i);
4086 if (!isa<ConstantSDNode>(Elt))
4088 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
4089 IdxOps.push_back(DAG.getConstant(i, EVT));
4090 else if (cast<ConstantSDNode>(Elt)->isNullValue())
4091 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
4096 // Let's see if the target supports this vector_shuffle.
4097 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
4100 // Return the new VECTOR_SHUFFLE node.
4101 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts);
4102 std::vector<SDOperand> Ops;
4103 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
4105 AddToWorkList(LHS.Val);
4106 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
4107 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4108 &ZeroOps[0], ZeroOps.size()));
4109 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4110 &IdxOps[0], IdxOps.size()));
4111 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
4112 &Ops[0], Ops.size());
4113 if (VT != LHS.getValueType()) {
4114 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result);
4122 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
4123 SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
4124 // After legalize, the target may be depending on adds and other
4125 // binary ops to provide legal ways to construct constants or other
4126 // things. Simplifying them may result in a loss of legality.
4127 if (AfterLegalize) return SDOperand();
4129 MVT::ValueType VT = N->getValueType(0);
4130 if (!MVT::isVector(VT)) return SDOperand();
4132 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4133 SDOperand LHS = N->getOperand(0);
4134 SDOperand RHS = N->getOperand(1);
4135 SDOperand Shuffle = XformToShuffleWithZero(N);
4136 if (Shuffle.Val) return Shuffle;
4138 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
4140 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
4141 RHS.getOpcode() == ISD::BUILD_VECTOR) {
4142 SmallVector<SDOperand, 8> Ops;
4143 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
4144 SDOperand LHSOp = LHS.getOperand(i);
4145 SDOperand RHSOp = RHS.getOperand(i);
4146 // If these two elements can't be folded, bail out.
4147 if ((LHSOp.getOpcode() != ISD::UNDEF &&
4148 LHSOp.getOpcode() != ISD::Constant &&
4149 LHSOp.getOpcode() != ISD::ConstantFP) ||
4150 (RHSOp.getOpcode() != ISD::UNDEF &&
4151 RHSOp.getOpcode() != ISD::Constant &&
4152 RHSOp.getOpcode() != ISD::ConstantFP))
4154 // Can't fold divide by zero.
4155 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
4156 N->getOpcode() == ISD::FDIV) {
4157 if ((RHSOp.getOpcode() == ISD::Constant &&
4158 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
4159 (RHSOp.getOpcode() == ISD::ConstantFP &&
4160 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
4163 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
4164 AddToWorkList(Ops.back().Val);
4165 assert((Ops.back().getOpcode() == ISD::UNDEF ||
4166 Ops.back().getOpcode() == ISD::Constant ||
4167 Ops.back().getOpcode() == ISD::ConstantFP) &&
4168 "Scalar binop didn't fold!");
4171 if (Ops.size() == LHS.getNumOperands()) {
4172 MVT::ValueType VT = LHS.getValueType();
4173 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
4180 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
4181 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
4183 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
4184 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4185 // If we got a simplified select_cc node back from SimplifySelectCC, then
4186 // break it down into a new SETCC node, and a new SELECT node, and then return
4187 // the SELECT node, since we were called with a SELECT node.
4189 // Check to see if we got a select_cc back (to turn into setcc/select).
4190 // Otherwise, just return whatever node we got back, like fabs.
4191 if (SCC.getOpcode() == ISD::SELECT_CC) {
4192 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
4193 SCC.getOperand(0), SCC.getOperand(1),
4195 AddToWorkList(SETCC.Val);
4196 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
4197 SCC.getOperand(3), SETCC);
4204 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
4205 /// are the two values being selected between, see if we can simplify the
4206 /// select. Callers of this should assume that TheSelect is deleted if this
4207 /// returns true. As such, they should return the appropriate thing (e.g. the
4208 /// node) back to the top-level of the DAG combiner loop to avoid it being
4211 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
4214 // If this is a select from two identical things, try to pull the operation
4215 // through the select.
4216 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
4217 // If this is a load and the token chain is identical, replace the select
4218 // of two loads with a load through a select of the address to load from.
4219 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
4220 // constants have been dropped into the constant pool.
4221 if (LHS.getOpcode() == ISD::LOAD &&
4222 // Token chains must be identical.
4223 LHS.getOperand(0) == RHS.getOperand(0)) {
4224 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
4225 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
4227 // If this is an EXTLOAD, the VT's must match.
4228 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
4229 // FIXME: this conflates two src values, discarding one. This is not
4230 // the right thing to do, but nothing uses srcvalues now. When they do,
4231 // turn SrcValue into a list of locations.
4233 if (TheSelect->getOpcode() == ISD::SELECT) {
4234 // Check that the condition doesn't reach either load. If so, folding
4235 // this will induce a cycle into the DAG.
4236 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4237 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
4238 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
4239 TheSelect->getOperand(0), LLD->getBasePtr(),
4243 // Check that the condition doesn't reach either load. If so, folding
4244 // this will induce a cycle into the DAG.
4245 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4246 !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4247 !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
4248 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
4249 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
4250 TheSelect->getOperand(0),
4251 TheSelect->getOperand(1),
4252 LLD->getBasePtr(), RLD->getBasePtr(),
4253 TheSelect->getOperand(4));
4259 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
4260 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
4261 Addr,LLD->getSrcValue(),
4262 LLD->getSrcValueOffset(),
4264 LLD->getAlignment());
4266 Load = DAG.getExtLoad(LLD->getExtensionType(),
4267 TheSelect->getValueType(0),
4268 LLD->getChain(), Addr, LLD->getSrcValue(),
4269 LLD->getSrcValueOffset(),
4272 LLD->getAlignment());
4274 // Users of the select now use the result of the load.
4275 CombineTo(TheSelect, Load);
4277 // Users of the old loads now use the new load's chain. We know the
4278 // old-load value is dead now.
4279 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
4280 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
4290 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
4291 SDOperand N2, SDOperand N3,
4292 ISD::CondCode CC, bool NotExtCompare) {
4294 MVT::ValueType VT = N2.getValueType();
4295 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
4296 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
4297 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
4299 // Determine if the condition we're dealing with is constant
4300 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
4301 if (SCC.Val) AddToWorkList(SCC.Val);
4302 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
4304 // fold select_cc true, x, y -> x
4305 if (SCCC && SCCC->getValue())
4307 // fold select_cc false, x, y -> y
4308 if (SCCC && SCCC->getValue() == 0)
4311 // Check to see if we can simplify the select into an fabs node
4312 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
4313 // Allow either -0.0 or 0.0
4314 if (CFP->getValue() == 0.0) {
4315 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
4316 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
4317 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
4318 N2 == N3.getOperand(0))
4319 return DAG.getNode(ISD::FABS, VT, N0);
4321 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
4322 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
4323 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
4324 N2.getOperand(0) == N3)
4325 return DAG.getNode(ISD::FABS, VT, N3);
4329 // Check to see if we can perform the "gzip trick", transforming
4330 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
4331 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
4332 MVT::isInteger(N0.getValueType()) &&
4333 MVT::isInteger(N2.getValueType()) &&
4334 (N1C->isNullValue() || // (a < 0) ? b : 0
4335 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
4336 MVT::ValueType XType = N0.getValueType();
4337 MVT::ValueType AType = N2.getValueType();
4338 if (XType >= AType) {
4339 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
4340 // single-bit constant.
4341 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
4342 unsigned ShCtV = Log2_64(N2C->getValue());
4343 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
4344 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
4345 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
4346 AddToWorkList(Shift.Val);
4347 if (XType > AType) {
4348 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4349 AddToWorkList(Shift.Val);
4351 return DAG.getNode(ISD::AND, AType, Shift, N2);
4353 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4354 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4355 TLI.getShiftAmountTy()));
4356 AddToWorkList(Shift.Val);
4357 if (XType > AType) {
4358 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4359 AddToWorkList(Shift.Val);
4361 return DAG.getNode(ISD::AND, AType, Shift, N2);
4365 // fold select C, 16, 0 -> shl C, 4
4366 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
4367 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
4369 // If the caller doesn't want us to simplify this into a zext of a compare,
4371 if (NotExtCompare && N2C->getValue() == 1)
4374 // Get a SetCC of the condition
4375 // FIXME: Should probably make sure that setcc is legal if we ever have a
4376 // target where it isn't.
4377 SDOperand Temp, SCC;
4378 // cast from setcc result type to select result type
4379 if (AfterLegalize) {
4380 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4381 if (N2.getValueType() < SCC.getValueType())
4382 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
4384 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4386 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
4387 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4389 AddToWorkList(SCC.Val);
4390 AddToWorkList(Temp.Val);
4392 if (N2C->getValue() == 1)
4394 // shl setcc result by log2 n2c
4395 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
4396 DAG.getConstant(Log2_64(N2C->getValue()),
4397 TLI.getShiftAmountTy()));
4400 // Check to see if this is the equivalent of setcc
4401 // FIXME: Turn all of these into setcc if setcc if setcc is legal
4402 // otherwise, go ahead with the folds.
4403 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
4404 MVT::ValueType XType = N0.getValueType();
4405 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
4406 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4407 if (Res.getValueType() != VT)
4408 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
4412 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
4413 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
4414 TLI.isOperationLegal(ISD::CTLZ, XType)) {
4415 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
4416 return DAG.getNode(ISD::SRL, XType, Ctlz,
4417 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
4418 TLI.getShiftAmountTy()));
4420 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
4421 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
4422 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
4424 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
4425 DAG.getConstant(~0ULL, XType));
4426 return DAG.getNode(ISD::SRL, XType,
4427 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
4428 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4429 TLI.getShiftAmountTy()));
4431 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
4432 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
4433 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
4434 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4435 TLI.getShiftAmountTy()));
4436 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
4440 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
4441 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4442 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
4443 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
4444 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) {
4445 MVT::ValueType XType = N0.getValueType();
4446 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4447 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4448 TLI.getShiftAmountTy()));
4449 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4450 AddToWorkList(Shift.Val);
4451 AddToWorkList(Add.Val);
4452 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4454 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
4455 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4456 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
4457 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
4458 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
4459 MVT::ValueType XType = N0.getValueType();
4460 if (SubC->isNullValue() && MVT::isInteger(XType)) {
4461 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4462 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4463 TLI.getShiftAmountTy()));
4464 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4465 AddToWorkList(Shift.Val);
4466 AddToWorkList(Add.Val);
4467 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4475 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
4476 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
4477 SDOperand N1, ISD::CondCode Cond,
4478 bool foldBooleans) {
4479 TargetLowering::DAGCombinerInfo
4480 DagCombineInfo(DAG, !AfterLegalize, false, this);
4481 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
4484 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
4485 /// return a DAG expression to select that will generate the same value by
4486 /// multiplying by a magic number. See:
4487 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4488 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
4489 std::vector<SDNode*> Built;
4490 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
4492 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4498 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
4499 /// return a DAG expression to select that will generate the same value by
4500 /// multiplying by a magic number. See:
4501 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4502 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
4503 std::vector<SDNode*> Built;
4504 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
4506 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4512 /// FindBaseOffset - Return true if base is known not to alias with anything
4513 /// but itself. Provides base object and offset as results.
4514 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4515 // Assume it is a primitive operation.
4516 Base = Ptr; Offset = 0;
4518 // If it's an adding a simple constant then integrate the offset.
4519 if (Base.getOpcode() == ISD::ADD) {
4520 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4521 Base = Base.getOperand(0);
4522 Offset += C->getValue();
4526 // If it's any of the following then it can't alias with anything but itself.
4527 return isa<FrameIndexSDNode>(Base) ||
4528 isa<ConstantPoolSDNode>(Base) ||
4529 isa<GlobalAddressSDNode>(Base);
4532 /// isAlias - Return true if there is any possibility that the two addresses
4534 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4535 const Value *SrcValue1, int SrcValueOffset1,
4536 SDOperand Ptr2, int64_t Size2,
4537 const Value *SrcValue2, int SrcValueOffset2)
4539 // If they are the same then they must be aliases.
4540 if (Ptr1 == Ptr2) return true;
4542 // Gather base node and offset information.
4543 SDOperand Base1, Base2;
4544 int64_t Offset1, Offset2;
4545 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4546 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4548 // If they have a same base address then...
4549 if (Base1 == Base2) {
4550 // Check to see if the addresses overlap.
4551 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4554 // If we know both bases then they can't alias.
4555 if (KnownBase1 && KnownBase2) return false;
4557 if (CombinerGlobalAA) {
4558 // Use alias analysis information.
4559 int Overlap1 = Size1 + SrcValueOffset1 + Offset1;
4560 int Overlap2 = Size2 + SrcValueOffset2 + Offset2;
4561 AliasAnalysis::AliasResult AAResult =
4562 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
4563 if (AAResult == AliasAnalysis::NoAlias)
4567 // Otherwise we have to assume they alias.
4571 /// FindAliasInfo - Extracts the relevant alias information from the memory
4572 /// node. Returns true if the operand was a load.
4573 bool DAGCombiner::FindAliasInfo(SDNode *N,
4574 SDOperand &Ptr, int64_t &Size,
4575 const Value *&SrcValue, int &SrcValueOffset) {
4576 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4577 Ptr = LD->getBasePtr();
4578 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4579 SrcValue = LD->getSrcValue();
4580 SrcValueOffset = LD->getSrcValueOffset();
4582 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4583 Ptr = ST->getBasePtr();
4584 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4585 SrcValue = ST->getSrcValue();
4586 SrcValueOffset = ST->getSrcValueOffset();
4588 assert(0 && "FindAliasInfo expected a memory operand");
4594 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4595 /// looking for aliasing nodes and adding them to the Aliases vector.
4596 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4597 SmallVector<SDOperand, 8> &Aliases) {
4598 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4599 std::set<SDNode *> Visited; // Visited node set.
4601 // Get alias information for node.
4604 const Value *SrcValue;
4606 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
4609 Chains.push_back(OriginalChain);
4611 // Look at each chain and determine if it is an alias. If so, add it to the
4612 // aliases list. If not, then continue up the chain looking for the next
4614 while (!Chains.empty()) {
4615 SDOperand Chain = Chains.back();
4618 // Don't bother if we've been before.
4619 if (Visited.find(Chain.Val) != Visited.end()) continue;
4620 Visited.insert(Chain.Val);
4622 switch (Chain.getOpcode()) {
4623 case ISD::EntryToken:
4624 // Entry token is ideal chain operand, but handled in FindBetterChain.
4629 // Get alias information for Chain.
4632 const Value *OpSrcValue;
4633 int OpSrcValueOffset;
4634 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
4635 OpSrcValue, OpSrcValueOffset);
4637 // If chain is alias then stop here.
4638 if (!(IsLoad && IsOpLoad) &&
4639 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
4640 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
4641 Aliases.push_back(Chain);
4643 // Look further up the chain.
4644 Chains.push_back(Chain.getOperand(0));
4645 // Clean up old chain.
4646 AddToWorkList(Chain.Val);
4651 case ISD::TokenFactor:
4652 // We have to check each of the operands of the token factor, so we queue
4653 // then up. Adding the operands to the queue (stack) in reverse order
4654 // maintains the original order and increases the likelihood that getNode
4655 // will find a matching token factor (CSE.)
4656 for (unsigned n = Chain.getNumOperands(); n;)
4657 Chains.push_back(Chain.getOperand(--n));
4658 // Eliminate the token factor if we can.
4659 AddToWorkList(Chain.Val);
4663 // For all other instructions we will just have to take what we can get.
4664 Aliases.push_back(Chain);
4670 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4671 /// for a better chain (aliasing node.)
4672 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4673 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4675 // Accumulate all the aliases to this node.
4676 GatherAllAliases(N, OldChain, Aliases);
4678 if (Aliases.size() == 0) {
4679 // If no operands then chain to entry token.
4680 return DAG.getEntryNode();
4681 } else if (Aliases.size() == 1) {
4682 // If a single operand then chain to it. We don't need to revisit it.
4686 // Construct a custom tailored token factor.
4687 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4688 &Aliases[0], Aliases.size());
4690 // Make sure the old chain gets cleaned up.
4691 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4696 // SelectionDAG::Combine - This is the entry point for the file.
4698 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
4699 if (!RunningAfterLegalize && ViewDAGCombine1)
4701 if (RunningAfterLegalize && ViewDAGCombine2)
4703 /// run - This is the main entry point to this class.
4705 DAGCombiner(*this, AA).Run(RunningAfterLegalize);