1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: Should add a corresponding version of fold AND with
20 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: zero extend when top bits are 0 -> drop it ?
26 // FIXME: make truncate see through SIGN_EXTEND and AND
27 // FIXME: sext_in_reg(setcc) on targets that return zero or one, and where
28 // EVT != MVT::i1 can drop the sext.
29 // FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
30 // FIXME: verify that getNode can't return extends with an operand whose type
31 // is >= to that of the extend.
32 // FIXME: divide by zero is currently left unfolded. do we want to turn this
35 //===----------------------------------------------------------------------===//
37 #define DEBUG_TYPE "dagcombine"
38 #include "llvm/ADT/Statistic.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/MathExtras.h"
42 #include "llvm/Target/TargetLowering.h"
48 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
55 // Worklist of all of the nodes that need to be simplified.
56 std::vector<SDNode*> WorkList;
58 /// AddUsersToWorkList - When an instruction is simplified, add all users of
59 /// the instruction to the work lists because they might get more simplified
62 void AddUsersToWorkList(SDNode *N) {
63 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
65 WorkList.push_back(*UI);
68 /// removeFromWorkList - remove all instances of N from the worklist.
69 void removeFromWorkList(SDNode *N) {
70 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
74 /// visit - call the node-specific routine that knows how to fold each
75 /// particular type of node.
76 SDOperand visit(SDNode *N);
78 // Visitation implementation - Implement dag node combining for different
79 // node types. The semantics are as follows:
81 // SDOperand.Val == 0 - No change was made
82 // otherwise - N should be replaced by the returned Operand.
84 SDOperand visitTokenFactor(SDNode *N);
85 SDOperand visitADD(SDNode *N);
86 SDOperand visitSUB(SDNode *N);
87 SDOperand visitMUL(SDNode *N);
88 SDOperand visitSDIV(SDNode *N);
89 SDOperand visitUDIV(SDNode *N);
90 SDOperand visitSREM(SDNode *N);
91 SDOperand visitUREM(SDNode *N);
92 SDOperand visitMULHU(SDNode *N);
93 SDOperand visitMULHS(SDNode *N);
94 SDOperand visitAND(SDNode *N);
95 SDOperand visitOR(SDNode *N);
96 SDOperand visitXOR(SDNode *N);
97 SDOperand visitSHL(SDNode *N);
98 SDOperand visitSRA(SDNode *N);
99 SDOperand visitSRL(SDNode *N);
100 SDOperand visitCTLZ(SDNode *N);
101 SDOperand visitCTTZ(SDNode *N);
102 SDOperand visitCTPOP(SDNode *N);
103 SDOperand visitSELECT(SDNode *N);
104 SDOperand visitSELECT_CC(SDNode *N);
105 SDOperand visitSETCC(SDNode *N);
106 SDOperand visitSIGN_EXTEND(SDNode *N);
107 SDOperand visitZERO_EXTEND(SDNode *N);
108 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
109 SDOperand visitTRUNCATE(SDNode *N);
110 SDOperand visitSINT_TO_FP(SDNode *N);
111 SDOperand visitUINT_TO_FP(SDNode *N);
112 SDOperand visitFP_TO_SINT(SDNode *N);
113 SDOperand visitFP_TO_UINT(SDNode *N);
114 SDOperand visitFP_ROUND(SDNode *N);
115 SDOperand visitFP_ROUND_INREG(SDNode *N);
116 SDOperand visitFP_EXTEND(SDNode *N);
117 SDOperand visitFNEG(SDNode *N);
118 SDOperand visitFABS(SDNode *N);
119 SDOperand visitBRCOND(SDNode *N);
124 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
127 DAGCombiner(SelectionDAG &D)
128 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
130 /// Run - runs the dag combiner on all nodes in the work list
131 void Run(bool RunningAfterLegalize);
135 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
136 /// this predicate to simplify operations downstream. V and Mask are known to
137 /// be the same type.
138 static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
139 const TargetLowering &TLI) {
141 if (Mask == 0) return true;
143 // If we know the result of a setcc has the top bits zero, use this info.
144 switch (Op.getOpcode()) {
146 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
148 // FIXME: teach this about non ZeroOrOne values, such as 0 or -1
149 return ((Mask & 1) == 0) &&
150 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
152 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
153 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
154 case ISD::ZERO_EXTEND:
155 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
156 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
157 case ISD::AssertZext:
158 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
159 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
161 // (X & C1) & C2 == 0 iff C1 & C2 == 0.
162 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
163 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
167 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
168 MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
170 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
171 MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
173 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
174 MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
176 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
177 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
178 uint64_t NewVal = Mask << ShAmt->getValue();
179 SrcBits = MVT::getSizeInBits(Op.getValueType());
180 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
181 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
185 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
186 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
187 uint64_t NewVal = Mask >> ShAmt->getValue();
188 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
194 // Bit counting instructions can not set the high bits of the result
195 // register. The max number of bits sets depends on the input.
196 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
198 // TODO we could handle some SRA cases here.
204 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
205 // that selects between the values 1 and 0, making it equivalent to a setcc.
206 // Also, set the incoming LHS, RHS, and CC references to the appropriate
207 // nodes based on the type of node we are checking. This simplifies life a
208 // bit for the callers.
209 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
211 if (N.getOpcode() == ISD::SETCC) {
212 LHS = N.getOperand(0);
213 RHS = N.getOperand(1);
214 CC = N.getOperand(2);
217 if (N.getOpcode() == ISD::SELECT_CC &&
218 N.getOperand(2).getOpcode() == ISD::Constant &&
219 N.getOperand(3).getOpcode() == ISD::Constant &&
220 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
221 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
222 LHS = N.getOperand(0);
223 RHS = N.getOperand(1);
224 CC = N.getOperand(4);
230 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
231 // one use. If this is true, it allows the users to invert the operation for
232 // free when it is profitable to do so.
233 static bool isOneUseSetCC(SDOperand N) {
234 SDOperand N0, N1, N2;
235 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
240 // FIXME: This should probably go in the ISD class rather than being duplicated
242 static bool isCommutativeBinOp(unsigned Opcode) {
248 case ISD::XOR: return true;
249 default: return false; // FIXME: Need commutative info for user ops!
253 void DAGCombiner::Run(bool RunningAfterLegalize) {
254 // set the instance variable, so that the various visit routines may use it.
255 AfterLegalize = RunningAfterLegalize;
257 // Add all the dag nodes to the worklist.
258 WorkList.insert(WorkList.end(), DAG.allnodes_begin(), DAG.allnodes_end());
260 // while the worklist isn't empty, inspect the node on the end of it and
261 // try and combine it.
262 while (!WorkList.empty()) {
263 SDNode *N = WorkList.back();
266 // If N has no uses, it is dead. Make sure to revisit all N's operands once
267 // N is deleted from the DAG, since they too may now be dead.
268 // FIXME: is there a better way to keep from deleting the dag root because
269 // we think it has no uses? This works for now...
270 if (N->use_empty() && N != DAG.getRoot().Val) {
271 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
272 WorkList.push_back(N->getOperand(i).Val);
275 removeFromWorkList(N);
279 SDOperand RV = visit(N);
282 // If we get back the same node we passed in, rather than a new node or
283 // zero, we know that the node must have defined multiple values and
284 // CombineTo was used. Since CombineTo takes care of the worklist
285 // mechanics for us, we have no work to do in this case.
287 DEBUG(std::cerr << "\nReplacing "; N->dump();
288 std::cerr << "\nWith: "; RV.Val->dump();
290 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV));
292 // Push the new node and any users onto the worklist
293 WorkList.push_back(RV.Val);
294 AddUsersToWorkList(RV.Val);
296 // Nodes can end up on the worklist more than once. Make sure we do
297 // not process a node that has been replaced.
298 removeFromWorkList(N);
304 SDOperand DAGCombiner::visit(SDNode *N) {
305 switch(N->getOpcode()) {
307 case ISD::TokenFactor: return visitTokenFactor(N);
308 case ISD::ADD: return visitADD(N);
309 case ISD::SUB: return visitSUB(N);
310 case ISD::MUL: return visitMUL(N);
311 case ISD::SDIV: return visitSDIV(N);
312 case ISD::UDIV: return visitUDIV(N);
313 case ISD::SREM: return visitSREM(N);
314 case ISD::UREM: return visitUREM(N);
315 case ISD::MULHU: return visitMULHU(N);
316 case ISD::MULHS: return visitMULHS(N);
317 case ISD::AND: return visitAND(N);
318 case ISD::OR: return visitOR(N);
319 case ISD::XOR: return visitXOR(N);
320 case ISD::SHL: return visitSHL(N);
321 case ISD::SRA: return visitSRA(N);
322 case ISD::SRL: return visitSRL(N);
323 case ISD::CTLZ: return visitCTLZ(N);
324 case ISD::CTTZ: return visitCTTZ(N);
325 case ISD::CTPOP: return visitCTPOP(N);
326 case ISD::SELECT: return visitSELECT(N);
327 case ISD::SELECT_CC: return visitSELECT_CC(N);
328 case ISD::SETCC: return visitSETCC(N);
329 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
330 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
331 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
332 case ISD::TRUNCATE: return visitTRUNCATE(N);
333 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
334 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
335 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
336 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
337 case ISD::FP_ROUND: return visitFP_ROUND(N);
338 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
339 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
340 case ISD::FNEG: return visitFNEG(N);
341 case ISD::FABS: return visitFABS(N);
346 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
347 // If the token factor has two operands and one is the entry token, replace
348 // the token factor with the other operand.
349 if (N->getNumOperands() == 2) {
350 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
351 return N->getOperand(1);
352 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
353 return N->getOperand(0);
358 SDOperand DAGCombiner::visitADD(SDNode *N) {
359 SDOperand N0 = N->getOperand(0);
360 SDOperand N1 = N->getOperand(1);
361 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
362 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
363 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
364 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
365 MVT::ValueType VT = N0.getValueType();
367 // fold (add c1, c2) -> c1+c2
369 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT);
370 // canonicalize constant to RHS
375 // fold (add x, 0) -> x
376 if (N1C && N1C->isNullValue())
378 // fold floating point (add c1, c2) -> c1+c2
380 return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(), VT);
381 // fold (add (add x, c1), c2) -> (add x, c1+c2)
382 if (N1C && N0.getOpcode() == ISD::ADD) {
383 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
384 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
386 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1),
387 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT));
389 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0),
390 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT));
392 // fold (A + (-B)) -> A-B
393 if (N1.getOpcode() == ISD::FNEG)
394 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(0));
395 // fold ((-A) + B) -> B-A
396 if (N0.getOpcode() == ISD::FNEG)
397 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(0));
398 // fold ((0-A) + B) -> B-A
399 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
400 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
401 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
402 // fold (A + (0-B)) -> A-B
403 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
404 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
405 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
406 // fold (A+(B-A)) -> B for non-fp types
407 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1) &&
408 !MVT::isFloatingPoint(N1.getValueType()))
409 return N1.getOperand(0);
413 SDOperand DAGCombiner::visitSUB(SDNode *N) {
414 SDOperand N0 = N->getOperand(0);
415 SDOperand N1 = N->getOperand(1);
416 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
417 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
418 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0.Val);
419 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val);
421 // fold (sub c1, c2) -> c1-c2
423 return DAG.getConstant(N0C->getValue() - N1C->getValue(),
425 // fold (sub x, 0) -> x
426 if (N1C && N1C->isNullValue())
428 // fold floating point (sub c1, c2) -> c1-c2
430 return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(),
433 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
434 !MVT::isFloatingPoint(N1.getValueType()))
435 return N0.getOperand(1);
437 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
438 !MVT::isFloatingPoint(N1.getValueType()))
439 return N0.getOperand(0);
440 // fold (A-(-B)) -> A+B
441 if (N1.getOpcode() == ISD::FNEG)
442 return DAG.getNode(ISD::ADD, N0.getValueType(), N0, N1.getOperand(0));
446 SDOperand DAGCombiner::visitMUL(SDNode *N) {
447 SDOperand N0 = N->getOperand(0);
448 SDOperand N1 = N->getOperand(1);
449 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
450 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
451 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
452 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
453 MVT::ValueType VT = N0.getValueType();
455 // fold (mul c1, c2) -> c1*c2
457 return DAG.getConstant(N0C->getValue() * N1C->getValue(),
459 // canonicalize constant to RHS
464 // fold (mul x, 0) -> 0
465 if (N1C && N1C->isNullValue())
467 // fold (mul x, -1) -> 0-x
468 if (N1C && N1C->isAllOnesValue())
469 return DAG.getNode(ISD::SUB, N->getValueType(0),
470 DAG.getConstant(0, N->getValueType(0)), N0);
471 // fold (mul x, (1 << c)) -> x << c
472 if (N1C && isPowerOf2_64(N1C->getValue()))
473 return DAG.getNode(ISD::SHL, N->getValueType(0), N0,
474 DAG.getConstant(Log2_64(N1C->getValue()),
475 TLI.getShiftAmountTy()));
476 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2)
477 if (N1C && N0.getOpcode() == ISD::MUL) {
478 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
479 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
481 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1),
482 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT));
484 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0),
485 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT));
487 // fold floating point (mul c1, c2) -> c1*c2
489 return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(),
494 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
495 SDOperand N0 = N->getOperand(0);
496 SDOperand N1 = N->getOperand(1);
497 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
498 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
499 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0.Val);
500 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val);
502 // fold (sdiv c1, c2) -> c1/c2
503 if (N0C && N1C && !N1C->isNullValue())
504 return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(),
506 // fold floating point (sdiv c1, c2) -> c1/c2
508 return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(),
513 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
514 SDOperand N0 = N->getOperand(0);
515 SDOperand N1 = N->getOperand(1);
516 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
517 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
519 // fold (udiv c1, c2) -> c1/c2
520 if (N0C && N1C && !N1C->isNullValue())
521 return DAG.getConstant(N0C->getValue() / N1C->getValue(),
523 // fold (udiv x, (1 << c)) -> x >>u c
524 if (N1C && isPowerOf2_64(N1C->getValue()))
525 return DAG.getNode(ISD::SRL, N->getValueType(0), N0,
526 DAG.getConstant(Log2_64(N1C->getValue()),
527 TLI.getShiftAmountTy()));
531 SDOperand DAGCombiner::visitSREM(SDNode *N) {
532 SDOperand N0 = N->getOperand(0);
533 SDOperand N1 = N->getOperand(1);
534 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
535 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
536 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
537 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
539 // fold (srem c1, c2) -> c1%c2
540 if (N0C && N1C && !N1C->isNullValue())
541 return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(),
543 // fold floating point (srem c1, c2) -> fmod(c1, c2)
545 return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()),
550 SDOperand DAGCombiner::visitUREM(SDNode *N) {
551 SDOperand N0 = N->getOperand(0);
552 SDOperand N1 = N->getOperand(1);
553 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
554 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
556 // fold (urem c1, c2) -> c1%c2
557 if (N0C && N1C && !N1C->isNullValue())
558 return DAG.getConstant(N0C->getValue() % N1C->getValue(),
560 // FIXME: c2 power of 2 -> mask?
564 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
565 SDOperand N0 = N->getOperand(0);
566 SDOperand N1 = N->getOperand(1);
567 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
569 // fold (mulhs x, 0) -> 0
570 if (N1C && N1C->isNullValue())
572 // fold (mulhs x, 1) -> (sra x, size(x)-1)
573 if (N1C && N1C->getValue() == 1)
574 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
575 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
576 TLI.getShiftAmountTy()));
580 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
581 SDOperand N0 = N->getOperand(0);
582 SDOperand N1 = N->getOperand(1);
583 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
585 // fold (mulhu x, 0) -> 0
586 if (N1C && N1C->isNullValue())
588 // fold (mulhu x, 1) -> 0
589 if (N1C && N1C->getValue() == 1)
590 return DAG.getConstant(0, N0.getValueType());
594 SDOperand DAGCombiner::visitAND(SDNode *N) {
595 SDOperand N0 = N->getOperand(0);
596 SDOperand N1 = N->getOperand(1);
597 SDOperand LL, LR, RL, RR, CC0, CC1;
598 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
599 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
600 MVT::ValueType VT = N1.getValueType();
601 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
603 // fold (and c1, c2) -> c1&c2
605 return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT);
606 // canonicalize constant to RHS
611 // fold (and x, -1) -> x
612 if (N1C && N1C->isAllOnesValue())
614 // if (and x, c) is known to be zero, return 0
615 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
616 return DAG.getConstant(0, VT);
617 // fold (and x, c) -> x iff (x & ~c) == 0
618 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
621 // fold (and (and x, c1), c2) -> (and x, c1^c2)
622 if (N1C && N0.getOpcode() == ISD::AND) {
623 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
624 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
626 return DAG.getNode(ISD::AND, VT, N0.getOperand(1),
627 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT));
629 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
630 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT));
632 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
633 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
634 unsigned ExtendBits =
635 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
636 if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0)
637 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
639 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
640 if (N0.getOpcode() == ISD::OR)
641 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
642 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
644 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
645 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
646 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
647 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
649 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
650 MVT::isInteger(LL.getValueType())) {
651 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
652 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
653 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
654 WorkList.push_back(ORNode.Val);
655 return DAG.getSetCC(VT, ORNode, LR, Op1);
657 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
658 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
659 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
660 WorkList.push_back(ANDNode.Val);
661 return DAG.getSetCC(VT, ANDNode, LR, Op1);
663 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
664 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
665 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
666 WorkList.push_back(ORNode.Val);
667 return DAG.getSetCC(VT, ORNode, LR, Op1);
670 // canonicalize equivalent to ll == rl
671 if (LL == RR && LR == RL) {
672 Op1 = ISD::getSetCCSwappedOperands(Op1);
675 if (LL == RL && LR == RR) {
676 bool isInteger = MVT::isInteger(LL.getValueType());
677 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
678 if (Result != ISD::SETCC_INVALID)
679 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
682 // fold (and (zext x), (zext y)) -> (zext (and x, y))
683 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
684 N1.getOpcode() == ISD::ZERO_EXTEND &&
685 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
686 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
687 N0.getOperand(0), N1.getOperand(0));
688 WorkList.push_back(ANDNode.Val);
689 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
691 // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y))
692 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
693 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) &&
694 N0.getOperand(1) == N1.getOperand(1)) {
695 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
696 N0.getOperand(0), N1.getOperand(0));
697 WorkList.push_back(ANDNode.Val);
698 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
703 SDOperand DAGCombiner::visitOR(SDNode *N) {
704 SDOperand N0 = N->getOperand(0);
705 SDOperand N1 = N->getOperand(1);
706 SDOperand LL, LR, RL, RR, CC0, CC1;
707 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
708 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
709 MVT::ValueType VT = N1.getValueType();
710 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
712 // fold (or c1, c2) -> c1|c2
714 return DAG.getConstant(N0C->getValue() | N1C->getValue(),
716 // canonicalize constant to RHS
721 // fold (or x, 0) -> x
722 if (N1C && N1C->isNullValue())
724 // fold (or x, -1) -> -1
725 if (N1C && N1C->isAllOnesValue())
727 // fold (or x, c) -> c iff (x & ~c) == 0
728 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
731 // fold (or (or x, c1), c2) -> (or x, c1|c2)
732 if (N1C && N0.getOpcode() == ISD::OR) {
733 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
734 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
736 return DAG.getNode(ISD::OR, VT, N0.getOperand(1),
737 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT));
739 return DAG.getNode(ISD::OR, VT, N0.getOperand(0),
740 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT));
742 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
743 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
744 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
745 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
747 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
748 MVT::isInteger(LL.getValueType())) {
749 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
750 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
751 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
752 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
753 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
754 WorkList.push_back(ORNode.Val);
755 return DAG.getSetCC(VT, ORNode, LR, Op1);
757 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
758 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
759 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
760 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
761 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
762 WorkList.push_back(ANDNode.Val);
763 return DAG.getSetCC(VT, ANDNode, LR, Op1);
766 // canonicalize equivalent to ll == rl
767 if (LL == RR && LR == RL) {
768 Op1 = ISD::getSetCCSwappedOperands(Op1);
771 if (LL == RL && LR == RR) {
772 bool isInteger = MVT::isInteger(LL.getValueType());
773 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
774 if (Result != ISD::SETCC_INVALID)
775 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
778 // fold (or (zext x), (zext y)) -> (zext (or x, y))
779 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
780 N1.getOpcode() == ISD::ZERO_EXTEND &&
781 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
782 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
783 N0.getOperand(0), N1.getOperand(0));
784 WorkList.push_back(ORNode.Val);
785 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
790 SDOperand DAGCombiner::visitXOR(SDNode *N) {
791 SDOperand N0 = N->getOperand(0);
792 SDOperand N1 = N->getOperand(1);
793 SDOperand LHS, RHS, CC;
794 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
795 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
796 MVT::ValueType VT = N0.getValueType();
798 // fold (xor c1, c2) -> c1^c2
800 return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT);
801 // canonicalize constant to RHS
806 // fold (xor x, 0) -> x
807 if (N1C && N1C->isNullValue())
809 // fold !(x cc y) -> (x !cc y)
810 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
811 bool isInt = MVT::isInteger(LHS.getValueType());
812 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
814 if (N0.getOpcode() == ISD::SETCC)
815 return DAG.getSetCC(VT, LHS, RHS, NotCC);
816 if (N0.getOpcode() == ISD::SELECT_CC)
817 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
818 assert(0 && "Unhandled SetCC Equivalent!");
821 // fold !(x or y) -> (!x and !y) iff x or y are setcc
822 if (N1C && N1C->getValue() == 1 &&
823 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
824 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
825 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
826 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
827 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
828 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
829 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
830 return DAG.getNode(NewOpcode, VT, LHS, RHS);
833 // fold !(x or y) -> (!x and !y) iff x or y are constants
834 if (N1C && N1C->isAllOnesValue() &&
835 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
836 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
837 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
838 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
839 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
840 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
841 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
842 return DAG.getNode(NewOpcode, VT, LHS, RHS);
845 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
846 if (N1C && N0.getOpcode() == ISD::XOR) {
847 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
848 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
850 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
851 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
853 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
854 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
856 // fold (xor x, x) -> 0
858 return DAG.getConstant(0, VT);
859 // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
860 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
861 N1.getOpcode() == ISD::ZERO_EXTEND &&
862 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
863 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
864 N0.getOperand(0), N1.getOperand(0));
865 WorkList.push_back(XORNode.Val);
866 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
871 SDOperand DAGCombiner::visitSHL(SDNode *N) {
872 SDOperand N0 = N->getOperand(0);
873 SDOperand N1 = N->getOperand(1);
874 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
875 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
876 MVT::ValueType VT = N0.getValueType();
877 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
879 // fold (shl c1, c2) -> c1<<c2
881 return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT);
882 // fold (shl 0, x) -> 0
883 if (N0C && N0C->isNullValue())
885 // fold (shl x, c >= size(x)) -> undef
886 if (N1C && N1C->getValue() >= OpSizeInBits)
887 return DAG.getNode(ISD::UNDEF, VT);
888 // fold (shl x, 0) -> x
889 if (N1C && N1C->isNullValue())
891 // if (shl x, c) is known to be zero, return 0
892 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
893 return DAG.getConstant(0, VT);
894 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
895 if (N1C && N0.getOpcode() == ISD::SHL &&
896 N0.getOperand(1).getOpcode() == ISD::Constant) {
897 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
898 uint64_t c2 = N1C->getValue();
899 if (c1 + c2 > OpSizeInBits)
900 return DAG.getConstant(0, VT);
901 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
902 DAG.getConstant(c1 + c2, N1.getValueType()));
904 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
905 // (srl (and x, -1 << c1), c1-c2)
906 if (N1C && N0.getOpcode() == ISD::SRL &&
907 N0.getOperand(1).getOpcode() == ISD::Constant) {
908 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
909 uint64_t c2 = N1C->getValue();
910 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
911 DAG.getConstant(~0ULL << c1, VT));
913 return DAG.getNode(ISD::SHL, VT, Mask,
914 DAG.getConstant(c2-c1, N1.getValueType()));
916 return DAG.getNode(ISD::SRL, VT, Mask,
917 DAG.getConstant(c1-c2, N1.getValueType()));
919 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
920 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
921 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
922 DAG.getConstant(~0ULL << N1C->getValue(), VT));
926 SDOperand DAGCombiner::visitSRA(SDNode *N) {
927 SDOperand N0 = N->getOperand(0);
928 SDOperand N1 = N->getOperand(1);
929 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
930 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
931 MVT::ValueType VT = N0.getValueType();
932 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
934 // fold (sra c1, c2) -> c1>>c2
936 return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT);
937 // fold (sra 0, x) -> 0
938 if (N0C && N0C->isNullValue())
940 // fold (sra -1, x) -> -1
941 if (N0C && N0C->isAllOnesValue())
943 // fold (sra x, c >= size(x)) -> undef
944 if (N1C && N1C->getValue() >= OpSizeInBits)
945 return DAG.getNode(ISD::UNDEF, VT);
946 // fold (sra x, 0) -> x
947 if (N1C && N1C->isNullValue())
949 // If the sign bit is known to be zero, switch this to a SRL.
950 if (N1C && MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI))
951 return DAG.getNode(ISD::SRL, VT, N0, N1);
955 SDOperand DAGCombiner::visitSRL(SDNode *N) {
956 SDOperand N0 = N->getOperand(0);
957 SDOperand N1 = N->getOperand(1);
958 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
959 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
960 MVT::ValueType VT = N0.getValueType();
961 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
963 // fold (srl c1, c2) -> c1 >>u c2
965 return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT);
966 // fold (srl 0, x) -> 0
967 if (N0C && N0C->isNullValue())
969 // fold (srl x, c >= size(x)) -> undef
970 if (N1C && N1C->getValue() >= OpSizeInBits)
971 return DAG.getNode(ISD::UNDEF, VT);
972 // fold (srl x, 0) -> x
973 if (N1C && N1C->isNullValue())
975 // if (srl x, c) is known to be zero, return 0
976 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
977 return DAG.getConstant(0, VT);
978 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
979 if (N1C && N0.getOpcode() == ISD::SRL &&
980 N0.getOperand(1).getOpcode() == ISD::Constant) {
981 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
982 uint64_t c2 = N1C->getValue();
983 if (c1 + c2 > OpSizeInBits)
984 return DAG.getConstant(0, VT);
985 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
986 DAG.getConstant(c1 + c2, N1.getValueType()));
991 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
992 SDOperand N0 = N->getOperand(0);
993 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
995 // fold (ctlz c1) -> c2
997 return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()),
1002 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1003 SDOperand N0 = N->getOperand(0);
1004 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1006 // fold (cttz c1) -> c2
1008 return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()),
1013 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1014 SDOperand N0 = N->getOperand(0);
1015 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1017 // fold (ctpop c1) -> c2
1019 return DAG.getConstant(CountPopulation_64(N0C->getValue()),
1024 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1025 SDOperand N0 = N->getOperand(0);
1026 SDOperand N1 = N->getOperand(1);
1027 SDOperand N2 = N->getOperand(2);
1028 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1029 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1030 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1031 MVT::ValueType VT = N->getValueType(0);
1033 // fold select C, X, X -> X
1036 // fold select true, X, Y -> X
1037 if (N0C && !N0C->isNullValue())
1039 // fold select false, X, Y -> Y
1040 if (N0C && N0C->isNullValue())
1042 // fold select C, 1, X -> C | X
1043 if (MVT::i1 == VT && N1C && !N1C->isNullValue())
1044 return DAG.getNode(ISD::OR, VT, N0, N2);
1045 // fold select C, 0, X -> ~C & X
1046 // FIXME: this should check for C type == X type, not i1?
1047 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1048 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1049 WorkList.push_back(XORNode.Val);
1050 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1052 // fold select C, X, 1 -> ~C | X
1053 if (MVT::i1 == VT && N2C && !N2C->isNullValue()) {
1054 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1055 WorkList.push_back(XORNode.Val);
1056 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1058 // fold select C, X, 0 -> C & X
1059 // FIXME: this should check for C type == X type, not i1?
1060 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1061 return DAG.getNode(ISD::AND, VT, N0, N1);
1062 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1063 if (MVT::i1 == VT && N0 == N1)
1064 return DAG.getNode(ISD::OR, VT, N0, N2);
1065 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1066 if (MVT::i1 == VT && N0 == N2)
1067 return DAG.getNode(ISD::AND, VT, N0, N1);
1072 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1076 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1077 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1078 cast<CondCodeSDNode>(N->getOperand(2))->get());
1081 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1082 SDOperand N0 = N->getOperand(0);
1083 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1084 MVT::ValueType VT = N->getValueType(0);
1086 // fold (sext c1) -> c1
1088 return DAG.getConstant(N0C->getSignExtended(), VT);
1089 // fold (sext (sext x)) -> (sext x)
1090 if (N0.getOpcode() == ISD::SIGN_EXTEND)
1091 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1095 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1096 SDOperand N0 = N->getOperand(0);
1097 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1098 MVT::ValueType VT = N->getValueType(0);
1100 // fold (zext c1) -> c1
1102 return DAG.getConstant(N0C->getValue(), VT);
1103 // fold (zext (zext x)) -> (zext x)
1104 if (N0.getOpcode() == ISD::ZERO_EXTEND)
1105 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1109 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1110 SDOperand N0 = N->getOperand(0);
1111 SDOperand N1 = N->getOperand(1);
1112 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1113 MVT::ValueType VT = N->getValueType(0);
1114 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1116 // fold (sext_in_reg c1) -> c1
1118 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1119 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1121 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1122 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1123 cast<VTSDNode>(N0.getOperand(1))->getVT() < EVT) {
1126 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1127 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1128 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1129 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1131 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1132 if (N0.getOpcode() == ISD::AssertSext &&
1133 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1136 // fold (sext_in_reg (sextload x)) -> (sextload x)
1137 if (N0.getOpcode() == ISD::SEXTLOAD &&
1138 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1141 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1142 // FIXME: teach isSetCCEquivalent about 0, -1 and then use it here
1143 if (N0.getOpcode() == ISD::SETCC &&
1144 TLI.getSetCCResultContents() ==
1145 TargetLowering::ZeroOrNegativeOneSetCCResult)
1147 // FIXME: this code is currently just ported over from SelectionDAG.cpp
1148 // we probably actually want to handle this in two pieces. Rather than
1149 // checking all the top bits for zero, just check the sign bit here and turn
1150 // it into a zero extend inreg (AND with constant).
1151 // then, let the code for AND figure out if the mask is superfluous rather
1152 // than doing so here.
1153 if (N0.getOpcode() == ISD::AND &&
1154 N0.getOperand(1).getOpcode() == ISD::Constant) {
1155 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1156 unsigned NumBits = MVT::getSizeInBits(EVT);
1157 if ((Mask & (~0ULL << (NumBits-1))) == 0)
1163 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1164 SDOperand N0 = N->getOperand(0);
1165 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1166 MVT::ValueType VT = N->getValueType(0);
1169 if (N0.getValueType() == N->getValueType(0))
1171 // fold (truncate c1) -> c1
1173 return DAG.getConstant(N0C->getValue(), VT);
1174 // fold (truncate (truncate x)) -> (truncate x)
1175 if (N0.getOpcode() == ISD::TRUNCATE)
1176 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1177 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1178 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
1179 if (N0.getValueType() < VT)
1180 // if the source is smaller than the dest, we still need an extend
1181 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1182 else if (N0.getValueType() > VT)
1183 // if the source is larger than the dest, than we just need the truncate
1184 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1186 // if the source and dest are the same type, we can drop both the extend
1188 return N0.getOperand(0);
1193 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
1194 SDOperand N0 = N->getOperand(0);
1195 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1197 // fold (sint_to_fp c1) -> c1fp
1199 return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0));
1203 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
1204 SDOperand N0 = N->getOperand(0);
1205 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1207 // fold (uint_to_fp c1) -> c1fp
1209 return DAG.getConstantFP(N0C->getValue(), N->getValueType(0));
1213 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
1214 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1216 // fold (fp_to_sint c1fp) -> c1
1218 return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0));
1222 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1223 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1225 // fold (fp_to_uint c1fp) -> c1
1227 return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0));
1231 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
1232 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1234 // fold (fp_round c1fp) -> c1fp
1236 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
1240 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
1241 SDOperand N0 = N->getOperand(0);
1242 MVT::ValueType VT = N->getValueType(0);
1243 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1244 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1246 // fold (fp_round_inreg c1fp) -> c1fp
1248 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
1249 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
1254 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
1255 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1257 // fold (fp_extend c1fp) -> c1fp
1259 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
1263 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
1264 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1265 // fold (neg c1) -> -c1
1267 return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0));
1268 // fold (neg (sub x, y)) -> (sub y, x)
1269 if (N->getOperand(0).getOpcode() == ISD::SUB)
1270 return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1),
1272 // fold (neg (neg x)) -> x
1273 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1274 return N->getOperand(0).getOperand(0);
1278 SDOperand DAGCombiner::visitFABS(SDNode *N) {
1279 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1280 // fold (fabs c1) -> fabs(c1)
1282 return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0));
1283 // fold (fabs (fabs x)) -> (fabs x)
1284 if (N->getOperand(0).getOpcode() == ISD::FABS)
1285 return N->getOperand(0);
1286 // fold (fabs (fneg x)) -> (fabs x)
1287 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1288 return DAG.getNode(ISD::FABS, N->getValueType(0),
1289 N->getOperand(0).getOperand(0));
1293 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
1294 SDOperand N1, ISD::CondCode Cond) {
1295 // These setcc operations always fold.
1299 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1301 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1304 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
1305 uint64_t C1 = N1C->getValue();
1306 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
1307 uint64_t C0 = N0C->getValue();
1309 // Sign extend the operands if required
1310 if (ISD::isSignedIntSetCC(Cond)) {
1311 C0 = N0C->getSignExtended();
1312 C1 = N1C->getSignExtended();
1316 default: assert(0 && "Unknown integer setcc!");
1317 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
1318 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
1319 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
1320 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
1321 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
1322 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
1323 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
1324 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
1325 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
1326 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
1329 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1330 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1331 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
1333 // If the comparison constant has bits in the upper part, the
1334 // zero-extended value could never match.
1335 if (C1 & (~0ULL << InSize)) {
1336 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
1340 case ISD::SETEQ: return DAG.getConstant(0, VT);
1343 case ISD::SETNE: return DAG.getConstant(1, VT);
1346 // True if the sign bit of C1 is set.
1347 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
1350 // True if the sign bit of C1 isn't set.
1351 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
1357 // Otherwise, we can perform the comparison with the low bits.
1365 return DAG.getSetCC(VT, N0.getOperand(0),
1366 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
1369 break; // todo, be more careful with signed comparisons
1371 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1372 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1373 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1374 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
1375 MVT::ValueType ExtDstTy = N0.getValueType();
1376 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
1378 // If the extended part has any inconsistent bits, it cannot ever
1379 // compare equal. In other words, they have to be all ones or all
1382 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
1383 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1384 return DAG.getConstant(Cond == ISD::SETNE, VT);
1387 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
1388 if (Op0Ty == ExtSrcTy) {
1389 ZextOp = N0.getOperand(0);
1391 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
1392 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
1393 DAG.getConstant(Imm, Op0Ty));
1395 WorkList.push_back(ZextOp.Val);
1396 // Otherwise, make this a use of a zext.
1397 return DAG.getSetCC(VT, ZextOp,
1398 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
1403 uint64_t MinVal, MaxVal;
1404 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
1405 if (ISD::isSignedIntSetCC(Cond)) {
1406 MinVal = 1ULL << (OperandBitSize-1);
1407 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
1408 MaxVal = ~0ULL >> (65-OperandBitSize);
1413 MaxVal = ~0ULL >> (64-OperandBitSize);
1416 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1417 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1418 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1419 --C1; // X >= C0 --> X > (C0-1)
1420 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1421 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1424 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1425 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1426 ++C1; // X <= C0 --> X < (C0+1)
1427 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1428 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1431 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1432 return DAG.getConstant(0, VT); // X < MIN --> false
1434 // Canonicalize setgt X, Min --> setne X, Min
1435 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1436 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1438 // If we have setult X, 1, turn it into seteq X, 0
1439 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1440 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
1442 // If we have setugt X, Max-1, turn it into seteq X, Max
1443 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1444 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
1447 // If we have "setcc X, C0", check to see if we can shrink the immediate
1450 // SETUGT X, SINTMAX -> SETLT X, 0
1451 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
1452 C1 == (~0ULL >> (65-OperandBitSize)))
1453 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
1456 // FIXME: Implement the rest of these.
1458 // Fold bit comparisons when we can.
1459 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1460 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1461 if (ConstantSDNode *AndRHS =
1462 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1463 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1464 // Perform the xform if the AND RHS is a single bit.
1465 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
1466 return DAG.getNode(ISD::SRL, VT, N0,
1467 DAG.getConstant(Log2_64(AndRHS->getValue()),
1468 TLI.getShiftAmountTy()));
1470 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
1471 // (X & 8) == 8 --> (X & 8) >> 3
1472 // Perform the xform if C1 is a single bit.
1473 if ((C1 & (C1-1)) == 0) {
1474 return DAG.getNode(ISD::SRL, VT, N0,
1475 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
1480 } else if (isa<ConstantSDNode>(N0.Val)) {
1481 // Ensure that the constant occurs on the RHS.
1482 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1485 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
1486 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
1487 double C0 = N0C->getValue(), C1 = N1C->getValue();
1490 default: break; // FIXME: Implement the rest of these!
1491 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
1492 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
1493 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
1494 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
1495 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
1496 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
1499 // Ensure that the constant occurs on the RHS.
1500 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1504 // We can always fold X == Y for integer setcc's.
1505 if (MVT::isInteger(N0.getValueType()))
1506 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1507 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1508 if (UOF == 2) // FP operators that are undefined on NaNs.
1509 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1510 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1511 return DAG.getConstant(UOF, VT);
1512 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1513 // if it is not already.
1514 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO;
1515 if (NewCond != Cond)
1516 return DAG.getSetCC(VT, N0, N1, NewCond);
1519 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1520 MVT::isInteger(N0.getValueType())) {
1521 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1522 N0.getOpcode() == ISD::XOR) {
1523 // Simplify (X+Y) == (X+Z) --> Y == Z
1524 if (N0.getOpcode() == N1.getOpcode()) {
1525 if (N0.getOperand(0) == N1.getOperand(0))
1526 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
1527 if (N0.getOperand(1) == N1.getOperand(1))
1528 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
1529 if (isCommutativeBinOp(N0.getOpcode())) {
1530 // If X op Y == Y op X, try other combinations.
1531 if (N0.getOperand(0) == N1.getOperand(1))
1532 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
1533 if (N0.getOperand(1) == N1.getOperand(0))
1534 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
1538 // Simplify (X+Z) == X --> Z == 0
1539 if (N0.getOperand(0) == N1)
1540 return DAG.getSetCC(VT, N0.getOperand(1),
1541 DAG.getConstant(0, N0.getValueType()), Cond);
1542 if (N0.getOperand(1) == N1) {
1543 if (isCommutativeBinOp(N0.getOpcode()))
1544 return DAG.getSetCC(VT, N0.getOperand(0),
1545 DAG.getConstant(0, N0.getValueType()), Cond);
1547 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1548 // (Z-X) == X --> Z == X<<1
1549 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
1551 DAG.getConstant(1,TLI.getShiftAmountTy()));
1552 WorkList.push_back(SH.Val);
1553 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
1558 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1559 N1.getOpcode() == ISD::XOR) {
1560 // Simplify X == (X+Z) --> Z == 0
1561 if (N1.getOperand(0) == N0) {
1562 return DAG.getSetCC(VT, N1.getOperand(1),
1563 DAG.getConstant(0, N1.getValueType()), Cond);
1564 } else if (N1.getOperand(1) == N0) {
1565 if (isCommutativeBinOp(N1.getOpcode())) {
1566 return DAG.getSetCC(VT, N1.getOperand(0),
1567 DAG.getConstant(0, N1.getValueType()), Cond);
1569 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1570 // X == (Z-X) --> X<<1 == Z
1571 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
1572 DAG.getConstant(1,TLI.getShiftAmountTy()));
1573 WorkList.push_back(SH.Val);
1574 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
1580 // Fold away ALL boolean setcc's.
1582 if (N0.getValueType() == MVT::i1) {
1584 default: assert(0 && "Unknown integer setcc!");
1585 case ISD::SETEQ: // X == Y -> (X^Y)^1
1586 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1587 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
1588 WorkList.push_back(Temp.Val);
1590 case ISD::SETNE: // X != Y --> (X^Y)
1591 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1593 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
1594 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
1595 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1596 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
1597 WorkList.push_back(Temp.Val);
1599 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
1600 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
1601 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1602 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
1603 WorkList.push_back(Temp.Val);
1605 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
1606 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
1607 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1608 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
1609 WorkList.push_back(Temp.Val);
1611 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
1612 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
1613 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1614 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
1617 if (VT != MVT::i1) {
1618 WorkList.push_back(N0.Val);
1619 // FIXME: If running after legalize, we probably can't do this.
1620 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1625 // Could not fold it.
1629 // SelectionDAG::Combine - This is the entry point for the file.
1631 void SelectionDAG::Combine(bool RunningAfterLegalize) {
1632 /// run - This is the main entry point to this class.
1634 DAGCombiner(*this).Run(RunningAfterLegalize);