1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: Should add a corresponding version of fold AND with
20 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
23 // FIXME: select C, 16, 0 -> shr C, 4
24 // FIXME: select C, pow2, pow2 -> something smart
25 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
26 // FIXME: (select C, load A, load B) -> load (select C, A, B)
27 // FIXME: store -> load -> forward substitute
28 // FIXME: Dead stores -> nuke
29 // FIXME: shr X, (and Y,31) -> shr X, Y
30 // FIXME: TRUNC (LOAD) -> EXT_LOAD/LOAD(smaller)
31 // FIXME: mul (x, const) -> shifts + adds
32 // FIXME: undef values
33 // FIXME: zero extend when top bits are 0 -> drop it ?
34 // FIXME: make truncate see through SIGN_EXTEND and AND
35 // FIXME: sext_in_reg(setcc) on targets that return zero or one, and where
36 // EVT != MVT::i1 can drop the sext.
37 // FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
38 // FIXME: verify that getNode can't return extends with an operand whose type
39 // is >= to that of the extend.
40 // FIXME: divide by zero is currently left unfolded. do we want to turn this
43 //===----------------------------------------------------------------------===//
45 #define DEBUG_TYPE "dagcombine"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/CodeGen/SelectionDAG.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetLowering.h"
56 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
63 // Worklist of all of the nodes that need to be simplified.
64 std::vector<SDNode*> WorkList;
66 /// AddUsersToWorkList - When an instruction is simplified, add all users of
67 /// the instruction to the work lists because they might get more simplified
70 void AddUsersToWorkList(SDNode *N) {
71 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
73 WorkList.push_back(*UI);
76 /// removeFromWorkList - remove all instances of N from the worklist.
77 void removeFromWorkList(SDNode *N) {
78 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
82 /// visit - call the node-specific routine that knows how to fold each
83 /// particular type of node.
84 SDOperand visit(SDNode *N);
86 // Visitation implementation - Implement dag node combining for different
87 // node types. The semantics are as follows:
89 // SDOperand.Val == 0 - No change was made
90 // otherwise - N should be replaced by the returned Operand.
92 SDOperand visitTokenFactor(SDNode *N);
93 SDOperand visitADD(SDNode *N);
94 SDOperand visitSUB(SDNode *N);
95 SDOperand visitMUL(SDNode *N);
96 SDOperand visitSDIV(SDNode *N);
97 SDOperand visitUDIV(SDNode *N);
98 SDOperand visitSREM(SDNode *N);
99 SDOperand visitUREM(SDNode *N);
100 SDOperand visitMULHU(SDNode *N);
101 SDOperand visitMULHS(SDNode *N);
102 SDOperand visitAND(SDNode *N);
103 SDOperand visitOR(SDNode *N);
104 SDOperand visitXOR(SDNode *N);
105 SDOperand visitSHL(SDNode *N);
106 SDOperand visitSRA(SDNode *N);
107 SDOperand visitSRL(SDNode *N);
108 SDOperand visitCTLZ(SDNode *N);
109 SDOperand visitCTTZ(SDNode *N);
110 SDOperand visitCTPOP(SDNode *N);
111 SDOperand visitSELECT(SDNode *N);
112 SDOperand visitSELECT_CC(SDNode *N);
113 SDOperand visitSETCC(SDNode *N);
114 SDOperand visitSIGN_EXTEND(SDNode *N);
115 SDOperand visitZERO_EXTEND(SDNode *N);
116 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
117 SDOperand visitTRUNCATE(SDNode *N);
118 SDOperand visitSINT_TO_FP(SDNode *N);
119 SDOperand visitUINT_TO_FP(SDNode *N);
120 SDOperand visitFP_TO_SINT(SDNode *N);
121 SDOperand visitFP_TO_UINT(SDNode *N);
122 SDOperand visitFP_ROUND(SDNode *N);
123 SDOperand visitFP_ROUND_INREG(SDNode *N);
124 SDOperand visitFP_EXTEND(SDNode *N);
125 SDOperand visitFNEG(SDNode *N);
126 SDOperand visitFABS(SDNode *N);
127 SDOperand visitBRCOND(SDNode *N);
128 SDOperand visitBRCONDTWOWAY(SDNode *N);
129 SDOperand visitBR_CC(SDNode *N);
130 SDOperand visitBRTWOWAY_CC(SDNode *N);
132 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
133 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
134 SDOperand N3, ISD::CondCode CC);
135 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
138 DAGCombiner(SelectionDAG &D)
139 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
141 /// Run - runs the dag combiner on all nodes in the work list
142 void Run(bool RunningAfterLegalize);
146 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
147 /// this predicate to simplify operations downstream. V and Mask are known to
148 /// be the same type.
149 static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
150 const TargetLowering &TLI) {
152 if (Mask == 0) return true;
154 // If we know the result of a setcc has the top bits zero, use this info.
155 switch (Op.getOpcode()) {
157 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
159 // FIXME: teach this about non ZeroOrOne values, such as 0 or -1
160 return ((Mask & 1) == 0) &&
161 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
163 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
164 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
165 case ISD::ZERO_EXTEND:
166 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
167 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
168 case ISD::AssertZext:
169 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
170 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
172 // (X & C1) & C2 == 0 iff C1 & C2 == 0.
173 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
174 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
178 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
179 MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
181 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
182 MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
184 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
185 MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
187 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
188 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
189 uint64_t NewVal = Mask << ShAmt->getValue();
190 SrcBits = MVT::getSizeInBits(Op.getValueType());
191 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
192 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
196 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
197 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
198 uint64_t NewVal = Mask >> ShAmt->getValue();
199 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
205 // Bit counting instructions can not set the high bits of the result
206 // register. The max number of bits sets depends on the input.
207 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
209 // TODO we could handle some SRA cases here.
215 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
216 // that selects between the values 1 and 0, making it equivalent to a setcc.
217 // Also, set the incoming LHS, RHS, and CC references to the appropriate
218 // nodes based on the type of node we are checking. This simplifies life a
219 // bit for the callers.
220 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
222 if (N.getOpcode() == ISD::SETCC) {
223 LHS = N.getOperand(0);
224 RHS = N.getOperand(1);
225 CC = N.getOperand(2);
228 if (N.getOpcode() == ISD::SELECT_CC &&
229 N.getOperand(2).getOpcode() == ISD::Constant &&
230 N.getOperand(3).getOpcode() == ISD::Constant &&
231 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
232 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
233 LHS = N.getOperand(0);
234 RHS = N.getOperand(1);
235 CC = N.getOperand(4);
241 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
242 // one use. If this is true, it allows the users to invert the operation for
243 // free when it is profitable to do so.
244 static bool isOneUseSetCC(SDOperand N) {
245 SDOperand N0, N1, N2;
246 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
251 // FIXME: This should probably go in the ISD class rather than being duplicated
253 static bool isCommutativeBinOp(unsigned Opcode) {
259 case ISD::XOR: return true;
260 default: return false; // FIXME: Need commutative info for user ops!
264 void DAGCombiner::Run(bool RunningAfterLegalize) {
265 // set the instance variable, so that the various visit routines may use it.
266 AfterLegalize = RunningAfterLegalize;
268 // Add all the dag nodes to the worklist.
269 WorkList.insert(WorkList.end(), DAG.allnodes_begin(), DAG.allnodes_end());
271 // while the worklist isn't empty, inspect the node on the end of it and
272 // try and combine it.
273 while (!WorkList.empty()) {
274 SDNode *N = WorkList.back();
277 // If N has no uses, it is dead. Make sure to revisit all N's operands once
278 // N is deleted from the DAG, since they too may now be dead.
279 // FIXME: is there a better way to keep from deleting the dag root because
280 // we think it has no uses? This works for now...
281 if (N->use_empty() && N != DAG.getRoot().Val) {
282 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
283 WorkList.push_back(N->getOperand(i).Val);
286 removeFromWorkList(N);
290 SDOperand RV = visit(N);
293 // If we get back the same node we passed in, rather than a new node or
294 // zero, we know that the node must have defined multiple values and
295 // CombineTo was used. Since CombineTo takes care of the worklist
296 // mechanics for us, we have no work to do in this case.
298 DEBUG(std::cerr << "\nReplacing "; N->dump();
299 std::cerr << "\nWith: "; RV.Val->dump();
301 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV));
303 // Push the new node and any users onto the worklist
304 WorkList.push_back(RV.Val);
305 AddUsersToWorkList(RV.Val);
307 // Nodes can end up on the worklist more than once. Make sure we do
308 // not process a node that has been replaced.
309 removeFromWorkList(N);
315 SDOperand DAGCombiner::visit(SDNode *N) {
316 switch(N->getOpcode()) {
318 case ISD::TokenFactor: return visitTokenFactor(N);
319 case ISD::ADD: return visitADD(N);
320 case ISD::SUB: return visitSUB(N);
321 case ISD::MUL: return visitMUL(N);
322 case ISD::SDIV: return visitSDIV(N);
323 case ISD::UDIV: return visitUDIV(N);
324 case ISD::SREM: return visitSREM(N);
325 case ISD::UREM: return visitUREM(N);
326 case ISD::MULHU: return visitMULHU(N);
327 case ISD::MULHS: return visitMULHS(N);
328 case ISD::AND: return visitAND(N);
329 case ISD::OR: return visitOR(N);
330 case ISD::XOR: return visitXOR(N);
331 case ISD::SHL: return visitSHL(N);
332 case ISD::SRA: return visitSRA(N);
333 case ISD::SRL: return visitSRL(N);
334 case ISD::CTLZ: return visitCTLZ(N);
335 case ISD::CTTZ: return visitCTTZ(N);
336 case ISD::CTPOP: return visitCTPOP(N);
337 case ISD::SELECT: return visitSELECT(N);
338 case ISD::SELECT_CC: return visitSELECT_CC(N);
339 case ISD::SETCC: return visitSETCC(N);
340 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
341 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
342 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
343 case ISD::TRUNCATE: return visitTRUNCATE(N);
344 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
345 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
346 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
347 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
348 case ISD::FP_ROUND: return visitFP_ROUND(N);
349 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
350 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
351 case ISD::FNEG: return visitFNEG(N);
352 case ISD::FABS: return visitFABS(N);
353 case ISD::BRCOND: return visitBRCOND(N);
354 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
355 case ISD::BR_CC: return visitBR_CC(N);
356 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
361 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
362 // If the token factor has two operands and one is the entry token, replace
363 // the token factor with the other operand.
364 if (N->getNumOperands() == 2) {
365 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
366 return N->getOperand(1);
367 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
368 return N->getOperand(0);
373 SDOperand DAGCombiner::visitADD(SDNode *N) {
374 SDOperand N0 = N->getOperand(0);
375 SDOperand N1 = N->getOperand(1);
376 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
377 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
378 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
379 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
380 MVT::ValueType VT = N0.getValueType();
382 // fold (add c1, c2) -> c1+c2
384 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT);
385 // canonicalize constant to RHS
390 // fold (add x, 0) -> x
391 if (N1C && N1C->isNullValue())
393 // fold floating point (add c1, c2) -> c1+c2
395 return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(), VT);
396 // fold (add (add x, c1), c2) -> (add x, c1+c2)
397 if (N1C && N0.getOpcode() == ISD::ADD) {
398 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
399 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
401 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1),
402 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT));
404 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0),
405 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT));
407 // fold (A + (-B)) -> A-B
408 if (N1.getOpcode() == ISD::FNEG)
409 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(0));
410 // fold ((-A) + B) -> B-A
411 if (N0.getOpcode() == ISD::FNEG)
412 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(0));
413 // fold ((0-A) + B) -> B-A
414 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
415 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
416 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
417 // fold (A + (0-B)) -> A-B
418 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
419 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
420 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
421 // fold (A+(B-A)) -> B for non-fp types
422 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1) &&
423 !MVT::isFloatingPoint(N1.getValueType()))
424 return N1.getOperand(0);
428 SDOperand DAGCombiner::visitSUB(SDNode *N) {
429 SDOperand N0 = N->getOperand(0);
430 SDOperand N1 = N->getOperand(1);
431 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
432 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
433 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0.Val);
434 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val);
436 // fold (sub c1, c2) -> c1-c2
438 return DAG.getConstant(N0C->getValue() - N1C->getValue(),
440 // fold (sub x, 0) -> x
441 if (N1C && N1C->isNullValue())
443 // fold floating point (sub c1, c2) -> c1-c2
445 return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(),
448 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
449 !MVT::isFloatingPoint(N1.getValueType()))
450 return N0.getOperand(1);
452 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
453 !MVT::isFloatingPoint(N1.getValueType()))
454 return N0.getOperand(0);
455 // fold (A-(-B)) -> A+B
456 if (N1.getOpcode() == ISD::FNEG)
457 return DAG.getNode(ISD::ADD, N0.getValueType(), N0, N1.getOperand(0));
461 SDOperand DAGCombiner::visitMUL(SDNode *N) {
462 SDOperand N0 = N->getOperand(0);
463 SDOperand N1 = N->getOperand(1);
464 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
465 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
466 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
467 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
468 MVT::ValueType VT = N0.getValueType();
470 // fold (mul c1, c2) -> c1*c2
472 return DAG.getConstant(N0C->getValue() * N1C->getValue(),
474 // canonicalize constant to RHS
479 // fold (mul x, 0) -> 0
480 if (N1C && N1C->isNullValue())
482 // fold (mul x, -1) -> 0-x
483 if (N1C && N1C->isAllOnesValue())
484 return DAG.getNode(ISD::SUB, N->getValueType(0),
485 DAG.getConstant(0, N->getValueType(0)), N0);
486 // fold (mul x, (1 << c)) -> x << c
487 if (N1C && isPowerOf2_64(N1C->getValue()))
488 return DAG.getNode(ISD::SHL, N->getValueType(0), N0,
489 DAG.getConstant(Log2_64(N1C->getValue()),
490 TLI.getShiftAmountTy()));
491 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2)
492 if (N1C && N0.getOpcode() == ISD::MUL) {
493 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
494 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
496 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1),
497 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT));
499 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0),
500 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT));
502 // fold floating point (mul c1, c2) -> c1*c2
504 return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(),
509 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
510 SDOperand N0 = N->getOperand(0);
511 SDOperand N1 = N->getOperand(1);
512 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
513 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
514 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0.Val);
515 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val);
517 // fold (sdiv c1, c2) -> c1/c2
518 if (N0C && N1C && !N1C->isNullValue())
519 return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(),
521 // fold floating point (sdiv c1, c2) -> c1/c2
523 return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(),
528 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
529 SDOperand N0 = N->getOperand(0);
530 SDOperand N1 = N->getOperand(1);
531 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
532 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
534 // fold (udiv c1, c2) -> c1/c2
535 if (N0C && N1C && !N1C->isNullValue())
536 return DAG.getConstant(N0C->getValue() / N1C->getValue(),
538 // fold (udiv x, (1 << c)) -> x >>u c
539 if (N1C && isPowerOf2_64(N1C->getValue()))
540 return DAG.getNode(ISD::SRL, N->getValueType(0), N0,
541 DAG.getConstant(Log2_64(N1C->getValue()),
542 TLI.getShiftAmountTy()));
546 SDOperand DAGCombiner::visitSREM(SDNode *N) {
547 SDOperand N0 = N->getOperand(0);
548 SDOperand N1 = N->getOperand(1);
549 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
550 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
551 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
552 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
554 // fold (srem c1, c2) -> c1%c2
555 if (N0C && N1C && !N1C->isNullValue())
556 return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(),
558 // fold floating point (srem c1, c2) -> fmod(c1, c2)
560 return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()),
565 SDOperand DAGCombiner::visitUREM(SDNode *N) {
566 SDOperand N0 = N->getOperand(0);
567 SDOperand N1 = N->getOperand(1);
568 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
569 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
571 // fold (urem c1, c2) -> c1%c2
572 if (N0C && N1C && !N1C->isNullValue())
573 return DAG.getConstant(N0C->getValue() % N1C->getValue(),
575 // FIXME: c2 power of 2 -> mask?
579 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
580 SDOperand N0 = N->getOperand(0);
581 SDOperand N1 = N->getOperand(1);
582 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
584 // fold (mulhs x, 0) -> 0
585 if (N1C && N1C->isNullValue())
587 // fold (mulhs x, 1) -> (sra x, size(x)-1)
588 if (N1C && N1C->getValue() == 1)
589 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
590 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
591 TLI.getShiftAmountTy()));
595 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
596 SDOperand N0 = N->getOperand(0);
597 SDOperand N1 = N->getOperand(1);
598 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
600 // fold (mulhu x, 0) -> 0
601 if (N1C && N1C->isNullValue())
603 // fold (mulhu x, 1) -> 0
604 if (N1C && N1C->getValue() == 1)
605 return DAG.getConstant(0, N0.getValueType());
609 SDOperand DAGCombiner::visitAND(SDNode *N) {
610 SDOperand N0 = N->getOperand(0);
611 SDOperand N1 = N->getOperand(1);
612 SDOperand LL, LR, RL, RR, CC0, CC1;
613 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
614 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
615 MVT::ValueType VT = N1.getValueType();
616 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
618 // fold (and c1, c2) -> c1&c2
620 return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT);
621 // canonicalize constant to RHS
626 // fold (and x, -1) -> x
627 if (N1C && N1C->isAllOnesValue())
629 // if (and x, c) is known to be zero, return 0
630 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
631 return DAG.getConstant(0, VT);
632 // fold (and x, c) -> x iff (x & ~c) == 0
633 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
636 // fold (and (and x, c1), c2) -> (and x, c1^c2)
637 if (N1C && N0.getOpcode() == ISD::AND) {
638 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
639 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
641 return DAG.getNode(ISD::AND, VT, N0.getOperand(1),
642 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT));
644 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
645 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT));
647 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
648 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
649 unsigned ExtendBits =
650 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
651 if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0)
652 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
654 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
655 if (N0.getOpcode() == ISD::OR)
656 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
657 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
659 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
660 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
661 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
662 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
664 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
665 MVT::isInteger(LL.getValueType())) {
666 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
667 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
668 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
669 WorkList.push_back(ORNode.Val);
670 return DAG.getSetCC(VT, ORNode, LR, Op1);
672 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
673 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
674 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
675 WorkList.push_back(ANDNode.Val);
676 return DAG.getSetCC(VT, ANDNode, LR, Op1);
678 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
679 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
680 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
681 WorkList.push_back(ORNode.Val);
682 return DAG.getSetCC(VT, ORNode, LR, Op1);
685 // canonicalize equivalent to ll == rl
686 if (LL == RR && LR == RL) {
687 Op1 = ISD::getSetCCSwappedOperands(Op1);
690 if (LL == RL && LR == RR) {
691 bool isInteger = MVT::isInteger(LL.getValueType());
692 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
693 if (Result != ISD::SETCC_INVALID)
694 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
697 // fold (and (zext x), (zext y)) -> (zext (and x, y))
698 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
699 N1.getOpcode() == ISD::ZERO_EXTEND &&
700 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
701 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
702 N0.getOperand(0), N1.getOperand(0));
703 WorkList.push_back(ANDNode.Val);
704 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
706 // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y))
707 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
708 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) &&
709 N0.getOperand(1) == N1.getOperand(1)) {
710 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
711 N0.getOperand(0), N1.getOperand(0));
712 WorkList.push_back(ANDNode.Val);
713 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
718 SDOperand DAGCombiner::visitOR(SDNode *N) {
719 SDOperand N0 = N->getOperand(0);
720 SDOperand N1 = N->getOperand(1);
721 SDOperand LL, LR, RL, RR, CC0, CC1;
722 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
723 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
724 MVT::ValueType VT = N1.getValueType();
725 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
727 // fold (or c1, c2) -> c1|c2
729 return DAG.getConstant(N0C->getValue() | N1C->getValue(),
731 // canonicalize constant to RHS
736 // fold (or x, 0) -> x
737 if (N1C && N1C->isNullValue())
739 // fold (or x, -1) -> -1
740 if (N1C && N1C->isAllOnesValue())
742 // fold (or x, c) -> c iff (x & ~c) == 0
743 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
746 // fold (or (or x, c1), c2) -> (or x, c1|c2)
747 if (N1C && N0.getOpcode() == ISD::OR) {
748 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
749 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
751 return DAG.getNode(ISD::OR, VT, N0.getOperand(1),
752 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT));
754 return DAG.getNode(ISD::OR, VT, N0.getOperand(0),
755 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT));
757 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
758 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
759 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
760 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
762 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
763 MVT::isInteger(LL.getValueType())) {
764 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
765 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
766 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
767 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
768 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
769 WorkList.push_back(ORNode.Val);
770 return DAG.getSetCC(VT, ORNode, LR, Op1);
772 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
773 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
774 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
775 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
776 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
777 WorkList.push_back(ANDNode.Val);
778 return DAG.getSetCC(VT, ANDNode, LR, Op1);
781 // canonicalize equivalent to ll == rl
782 if (LL == RR && LR == RL) {
783 Op1 = ISD::getSetCCSwappedOperands(Op1);
786 if (LL == RL && LR == RR) {
787 bool isInteger = MVT::isInteger(LL.getValueType());
788 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
789 if (Result != ISD::SETCC_INVALID)
790 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
793 // fold (or (zext x), (zext y)) -> (zext (or x, y))
794 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
795 N1.getOpcode() == ISD::ZERO_EXTEND &&
796 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
797 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
798 N0.getOperand(0), N1.getOperand(0));
799 WorkList.push_back(ORNode.Val);
800 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
805 SDOperand DAGCombiner::visitXOR(SDNode *N) {
806 SDOperand N0 = N->getOperand(0);
807 SDOperand N1 = N->getOperand(1);
808 SDOperand LHS, RHS, CC;
809 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
810 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
811 MVT::ValueType VT = N0.getValueType();
813 // fold (xor c1, c2) -> c1^c2
815 return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT);
816 // canonicalize constant to RHS
821 // fold (xor x, 0) -> x
822 if (N1C && N1C->isNullValue())
824 // fold !(x cc y) -> (x !cc y)
825 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
826 bool isInt = MVT::isInteger(LHS.getValueType());
827 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
829 if (N0.getOpcode() == ISD::SETCC)
830 return DAG.getSetCC(VT, LHS, RHS, NotCC);
831 if (N0.getOpcode() == ISD::SELECT_CC)
832 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
833 assert(0 && "Unhandled SetCC Equivalent!");
836 // fold !(x or y) -> (!x and !y) iff x or y are setcc
837 if (N1C && N1C->getValue() == 1 &&
838 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
839 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
840 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
841 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
842 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
843 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
844 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
845 return DAG.getNode(NewOpcode, VT, LHS, RHS);
848 // fold !(x or y) -> (!x and !y) iff x or y are constants
849 if (N1C && N1C->isAllOnesValue() &&
850 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
851 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
852 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
853 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
854 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
855 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
856 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
857 return DAG.getNode(NewOpcode, VT, LHS, RHS);
860 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
861 if (N1C && N0.getOpcode() == ISD::XOR) {
862 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
863 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
865 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
866 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
868 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
869 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
871 // fold (xor x, x) -> 0
873 return DAG.getConstant(0, VT);
874 // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
875 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
876 N1.getOpcode() == ISD::ZERO_EXTEND &&
877 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
878 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
879 N0.getOperand(0), N1.getOperand(0));
880 WorkList.push_back(XORNode.Val);
881 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
886 SDOperand DAGCombiner::visitSHL(SDNode *N) {
887 SDOperand N0 = N->getOperand(0);
888 SDOperand N1 = N->getOperand(1);
889 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
890 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
891 MVT::ValueType VT = N0.getValueType();
892 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
894 // fold (shl c1, c2) -> c1<<c2
896 return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT);
897 // fold (shl 0, x) -> 0
898 if (N0C && N0C->isNullValue())
900 // fold (shl x, c >= size(x)) -> undef
901 if (N1C && N1C->getValue() >= OpSizeInBits)
902 return DAG.getNode(ISD::UNDEF, VT);
903 // fold (shl x, 0) -> x
904 if (N1C && N1C->isNullValue())
906 // if (shl x, c) is known to be zero, return 0
907 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
908 return DAG.getConstant(0, VT);
909 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
910 if (N1C && N0.getOpcode() == ISD::SHL &&
911 N0.getOperand(1).getOpcode() == ISD::Constant) {
912 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
913 uint64_t c2 = N1C->getValue();
914 if (c1 + c2 > OpSizeInBits)
915 return DAG.getConstant(0, VT);
916 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
917 DAG.getConstant(c1 + c2, N1.getValueType()));
919 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
920 // (srl (and x, -1 << c1), c1-c2)
921 if (N1C && N0.getOpcode() == ISD::SRL &&
922 N0.getOperand(1).getOpcode() == ISD::Constant) {
923 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
924 uint64_t c2 = N1C->getValue();
925 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
926 DAG.getConstant(~0ULL << c1, VT));
928 return DAG.getNode(ISD::SHL, VT, Mask,
929 DAG.getConstant(c2-c1, N1.getValueType()));
931 return DAG.getNode(ISD::SRL, VT, Mask,
932 DAG.getConstant(c1-c2, N1.getValueType()));
934 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
935 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
936 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
937 DAG.getConstant(~0ULL << N1C->getValue(), VT));
941 SDOperand DAGCombiner::visitSRA(SDNode *N) {
942 SDOperand N0 = N->getOperand(0);
943 SDOperand N1 = N->getOperand(1);
944 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
945 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
946 MVT::ValueType VT = N0.getValueType();
947 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
949 // fold (sra c1, c2) -> c1>>c2
951 return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT);
952 // fold (sra 0, x) -> 0
953 if (N0C && N0C->isNullValue())
955 // fold (sra -1, x) -> -1
956 if (N0C && N0C->isAllOnesValue())
958 // fold (sra x, c >= size(x)) -> undef
959 if (N1C && N1C->getValue() >= OpSizeInBits)
960 return DAG.getNode(ISD::UNDEF, VT);
961 // fold (sra x, 0) -> x
962 if (N1C && N1C->isNullValue())
964 // If the sign bit is known to be zero, switch this to a SRL.
965 if (N1C && MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI))
966 return DAG.getNode(ISD::SRL, VT, N0, N1);
970 SDOperand DAGCombiner::visitSRL(SDNode *N) {
971 SDOperand N0 = N->getOperand(0);
972 SDOperand N1 = N->getOperand(1);
973 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
974 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
975 MVT::ValueType VT = N0.getValueType();
976 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
978 // fold (srl c1, c2) -> c1 >>u c2
980 return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT);
981 // fold (srl 0, x) -> 0
982 if (N0C && N0C->isNullValue())
984 // fold (srl x, c >= size(x)) -> undef
985 if (N1C && N1C->getValue() >= OpSizeInBits)
986 return DAG.getNode(ISD::UNDEF, VT);
987 // fold (srl x, 0) -> x
988 if (N1C && N1C->isNullValue())
990 // if (srl x, c) is known to be zero, return 0
991 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
992 return DAG.getConstant(0, VT);
993 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
994 if (N1C && N0.getOpcode() == ISD::SRL &&
995 N0.getOperand(1).getOpcode() == ISD::Constant) {
996 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
997 uint64_t c2 = N1C->getValue();
998 if (c1 + c2 > OpSizeInBits)
999 return DAG.getConstant(0, VT);
1000 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1001 DAG.getConstant(c1 + c2, N1.getValueType()));
1006 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1007 SDOperand N0 = N->getOperand(0);
1008 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1010 // fold (ctlz c1) -> c2
1012 return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()),
1017 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1018 SDOperand N0 = N->getOperand(0);
1019 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1021 // fold (cttz c1) -> c2
1023 return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()),
1028 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1029 SDOperand N0 = N->getOperand(0);
1030 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1032 // fold (ctpop c1) -> c2
1034 return DAG.getConstant(CountPopulation_64(N0C->getValue()),
1039 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1040 SDOperand N0 = N->getOperand(0);
1041 SDOperand N1 = N->getOperand(1);
1042 SDOperand N2 = N->getOperand(2);
1043 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1044 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1045 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1046 MVT::ValueType VT = N->getValueType(0);
1048 // fold select C, X, X -> X
1051 // fold select true, X, Y -> X
1052 if (N0C && !N0C->isNullValue())
1054 // fold select false, X, Y -> Y
1055 if (N0C && N0C->isNullValue())
1057 // fold select C, 1, X -> C | X
1058 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1059 return DAG.getNode(ISD::OR, VT, N0, N2);
1060 // fold select C, 0, X -> ~C & X
1061 // FIXME: this should check for C type == X type, not i1?
1062 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1063 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1064 WorkList.push_back(XORNode.Val);
1065 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1067 // fold select C, X, 1 -> ~C | X
1068 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1069 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1070 WorkList.push_back(XORNode.Val);
1071 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1073 // fold select C, X, 0 -> C & X
1074 // FIXME: this should check for C type == X type, not i1?
1075 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1076 return DAG.getNode(ISD::AND, VT, N0, N1);
1077 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1078 if (MVT::i1 == VT && N0 == N1)
1079 return DAG.getNode(ISD::OR, VT, N0, N2);
1080 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1081 if (MVT::i1 == VT && N0 == N2)
1082 return DAG.getNode(ISD::AND, VT, N0, N1);
1083 // fold selects based on a setcc into other things, such as min/max/abs
1084 if (N0.getOpcode() == ISD::SETCC)
1085 return SimplifySelect(N0, N1, N2);
1089 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1090 SDOperand N0 = N->getOperand(0);
1091 SDOperand N1 = N->getOperand(1);
1092 SDOperand N2 = N->getOperand(2);
1093 SDOperand N3 = N->getOperand(3);
1094 SDOperand N4 = N->getOperand(4);
1095 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1096 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1097 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1098 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1100 // Determine if the condition we're dealing with is constant
1101 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC);
1102 ConstantSDNode *SCCC = dyn_cast<ConstantSDNode>(SCC);
1103 bool constTrue = SCCC && SCCC->getValue() == 1;
1104 bool constFalse = SCCC && SCCC->isNullValue();
1106 // fold select_cc lhs, rhs, x, x, cc -> x
1109 // fold select_cc true, x, y -> x
1112 // fold select_cc false, x, y -> y
1115 // fold select_cc into other things, such as min/max/abs
1116 return SimplifySelectCC(N0, N1, N2, N3, CC);
1119 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1120 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1121 cast<CondCodeSDNode>(N->getOperand(2))->get());
1124 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1125 SDOperand N0 = N->getOperand(0);
1126 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1127 MVT::ValueType VT = N->getValueType(0);
1129 // fold (sext c1) -> c1
1131 return DAG.getConstant(N0C->getSignExtended(), VT);
1132 // fold (sext (sext x)) -> (sext x)
1133 if (N0.getOpcode() == ISD::SIGN_EXTEND)
1134 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1138 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1139 SDOperand N0 = N->getOperand(0);
1140 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1141 MVT::ValueType VT = N->getValueType(0);
1143 // fold (zext c1) -> c1
1145 return DAG.getConstant(N0C->getValue(), VT);
1146 // fold (zext (zext x)) -> (zext x)
1147 if (N0.getOpcode() == ISD::ZERO_EXTEND)
1148 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1152 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1153 SDOperand N0 = N->getOperand(0);
1154 SDOperand N1 = N->getOperand(1);
1155 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1156 MVT::ValueType VT = N->getValueType(0);
1157 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1159 // fold (sext_in_reg c1) -> c1
1161 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1162 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1164 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1165 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1166 cast<VTSDNode>(N0.getOperand(1))->getVT() < EVT) {
1169 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1170 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1171 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1172 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1174 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1175 if (N0.getOpcode() == ISD::AssertSext &&
1176 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1179 // fold (sext_in_reg (sextload x)) -> (sextload x)
1180 if (N0.getOpcode() == ISD::SEXTLOAD &&
1181 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1184 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1185 // FIXME: teach isSetCCEquivalent about 0, -1 and then use it here
1186 if (N0.getOpcode() == ISD::SETCC &&
1187 TLI.getSetCCResultContents() ==
1188 TargetLowering::ZeroOrNegativeOneSetCCResult)
1190 // FIXME: this code is currently just ported over from SelectionDAG.cpp
1191 // we probably actually want to handle this in two pieces. Rather than
1192 // checking all the top bits for zero, just check the sign bit here and turn
1193 // it into a zero extend inreg (AND with constant).
1194 // then, let the code for AND figure out if the mask is superfluous rather
1195 // than doing so here.
1196 if (N0.getOpcode() == ISD::AND &&
1197 N0.getOperand(1).getOpcode() == ISD::Constant) {
1198 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1199 unsigned NumBits = MVT::getSizeInBits(EVT);
1200 if ((Mask & (~0ULL << (NumBits-1))) == 0)
1206 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1207 SDOperand N0 = N->getOperand(0);
1208 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1209 MVT::ValueType VT = N->getValueType(0);
1212 if (N0.getValueType() == N->getValueType(0))
1214 // fold (truncate c1) -> c1
1216 return DAG.getConstant(N0C->getValue(), VT);
1217 // fold (truncate (truncate x)) -> (truncate x)
1218 if (N0.getOpcode() == ISD::TRUNCATE)
1219 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1220 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1221 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
1222 if (N0.getValueType() < VT)
1223 // if the source is smaller than the dest, we still need an extend
1224 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1225 else if (N0.getValueType() > VT)
1226 // if the source is larger than the dest, than we just need the truncate
1227 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1229 // if the source and dest are the same type, we can drop both the extend
1231 return N0.getOperand(0);
1236 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
1237 SDOperand N0 = N->getOperand(0);
1238 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1240 // fold (sint_to_fp c1) -> c1fp
1242 return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0));
1246 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
1247 SDOperand N0 = N->getOperand(0);
1248 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1250 // fold (uint_to_fp c1) -> c1fp
1252 return DAG.getConstantFP(N0C->getValue(), N->getValueType(0));
1256 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
1257 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1259 // fold (fp_to_sint c1fp) -> c1
1261 return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0));
1265 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1266 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1268 // fold (fp_to_uint c1fp) -> c1
1270 return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0));
1274 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
1275 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1277 // fold (fp_round c1fp) -> c1fp
1279 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
1283 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
1284 SDOperand N0 = N->getOperand(0);
1285 MVT::ValueType VT = N->getValueType(0);
1286 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1287 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1289 // fold (fp_round_inreg c1fp) -> c1fp
1291 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
1292 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
1297 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
1298 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1300 // fold (fp_extend c1fp) -> c1fp
1302 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
1306 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
1307 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1308 // fold (neg c1) -> -c1
1310 return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0));
1311 // fold (neg (sub x, y)) -> (sub y, x)
1312 if (N->getOperand(0).getOpcode() == ISD::SUB)
1313 return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1),
1315 // fold (neg (neg x)) -> x
1316 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1317 return N->getOperand(0).getOperand(0);
1321 SDOperand DAGCombiner::visitFABS(SDNode *N) {
1322 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1323 // fold (fabs c1) -> fabs(c1)
1325 return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0));
1326 // fold (fabs (fabs x)) -> (fabs x)
1327 if (N->getOperand(0).getOpcode() == ISD::FABS)
1328 return N->getOperand(0);
1329 // fold (fabs (fneg x)) -> (fabs x)
1330 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1331 return DAG.getNode(ISD::FABS, N->getValueType(0),
1332 N->getOperand(0).getOperand(0));
1336 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
1337 SDOperand Chain = N->getOperand(0);
1338 SDOperand N1 = N->getOperand(1);
1339 SDOperand N2 = N->getOperand(2);
1340 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1342 // never taken branch, fold to chain
1343 if (N1C && N1C->isNullValue())
1345 // unconditional branch
1346 if (N1C && !N1C->isNullValue())
1347 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1351 SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
1352 SDOperand Chain = N->getOperand(0);
1353 SDOperand N1 = N->getOperand(1);
1354 SDOperand N2 = N->getOperand(2);
1355 SDOperand N3 = N->getOperand(3);
1356 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1358 // unconditional branch to true mbb
1359 if (N1C && N1C->getValue() == 1)
1360 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1361 // unconditional branch to false mbb
1362 if (N1C && N1C->isNullValue())
1363 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
1367 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
1368 // FIXME: come up with a common way between br_cc, brtwoway_cc, and select_cc
1369 // to canonicalize the condition without calling getnode a bazillion times.
1373 SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
1374 // FIXME: come up with a common way between br_cc, brtwoway_cc, and select_cc
1375 // to canonicalize the condition without calling getnode a bazillion times.
1379 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
1383 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
1384 SDOperand N2, SDOperand N3,
1389 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
1390 SDOperand N1, ISD::CondCode Cond) {
1391 // These setcc operations always fold.
1395 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1397 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1400 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
1401 uint64_t C1 = N1C->getValue();
1402 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
1403 uint64_t C0 = N0C->getValue();
1405 // Sign extend the operands if required
1406 if (ISD::isSignedIntSetCC(Cond)) {
1407 C0 = N0C->getSignExtended();
1408 C1 = N1C->getSignExtended();
1412 default: assert(0 && "Unknown integer setcc!");
1413 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
1414 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
1415 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
1416 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
1417 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
1418 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
1419 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
1420 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
1421 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
1422 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
1425 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1426 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1427 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
1429 // If the comparison constant has bits in the upper part, the
1430 // zero-extended value could never match.
1431 if (C1 & (~0ULL << InSize)) {
1432 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
1436 case ISD::SETEQ: return DAG.getConstant(0, VT);
1439 case ISD::SETNE: return DAG.getConstant(1, VT);
1442 // True if the sign bit of C1 is set.
1443 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
1446 // True if the sign bit of C1 isn't set.
1447 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
1453 // Otherwise, we can perform the comparison with the low bits.
1461 return DAG.getSetCC(VT, N0.getOperand(0),
1462 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
1465 break; // todo, be more careful with signed comparisons
1467 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1468 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1469 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1470 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
1471 MVT::ValueType ExtDstTy = N0.getValueType();
1472 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
1474 // If the extended part has any inconsistent bits, it cannot ever
1475 // compare equal. In other words, they have to be all ones or all
1478 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
1479 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1480 return DAG.getConstant(Cond == ISD::SETNE, VT);
1483 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
1484 if (Op0Ty == ExtSrcTy) {
1485 ZextOp = N0.getOperand(0);
1487 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
1488 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
1489 DAG.getConstant(Imm, Op0Ty));
1491 WorkList.push_back(ZextOp.Val);
1492 // Otherwise, make this a use of a zext.
1493 return DAG.getSetCC(VT, ZextOp,
1494 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
1499 uint64_t MinVal, MaxVal;
1500 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
1501 if (ISD::isSignedIntSetCC(Cond)) {
1502 MinVal = 1ULL << (OperandBitSize-1);
1503 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
1504 MaxVal = ~0ULL >> (65-OperandBitSize);
1509 MaxVal = ~0ULL >> (64-OperandBitSize);
1512 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1513 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1514 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1515 --C1; // X >= C0 --> X > (C0-1)
1516 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1517 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1520 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1521 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1522 ++C1; // X <= C0 --> X < (C0+1)
1523 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1524 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1527 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1528 return DAG.getConstant(0, VT); // X < MIN --> false
1530 // Canonicalize setgt X, Min --> setne X, Min
1531 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1532 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1534 // If we have setult X, 1, turn it into seteq X, 0
1535 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1536 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
1538 // If we have setugt X, Max-1, turn it into seteq X, Max
1539 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1540 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
1543 // If we have "setcc X, C0", check to see if we can shrink the immediate
1546 // SETUGT X, SINTMAX -> SETLT X, 0
1547 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
1548 C1 == (~0ULL >> (65-OperandBitSize)))
1549 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
1552 // FIXME: Implement the rest of these.
1554 // Fold bit comparisons when we can.
1555 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1556 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1557 if (ConstantSDNode *AndRHS =
1558 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1559 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1560 // Perform the xform if the AND RHS is a single bit.
1561 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
1562 return DAG.getNode(ISD::SRL, VT, N0,
1563 DAG.getConstant(Log2_64(AndRHS->getValue()),
1564 TLI.getShiftAmountTy()));
1566 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
1567 // (X & 8) == 8 --> (X & 8) >> 3
1568 // Perform the xform if C1 is a single bit.
1569 if ((C1 & (C1-1)) == 0) {
1570 return DAG.getNode(ISD::SRL, VT, N0,
1571 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
1576 } else if (isa<ConstantSDNode>(N0.Val)) {
1577 // Ensure that the constant occurs on the RHS.
1578 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1581 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
1582 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
1583 double C0 = N0C->getValue(), C1 = N1C->getValue();
1586 default: break; // FIXME: Implement the rest of these!
1587 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
1588 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
1589 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
1590 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
1591 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
1592 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
1595 // Ensure that the constant occurs on the RHS.
1596 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1600 // We can always fold X == Y for integer setcc's.
1601 if (MVT::isInteger(N0.getValueType()))
1602 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1603 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1604 if (UOF == 2) // FP operators that are undefined on NaNs.
1605 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1606 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1607 return DAG.getConstant(UOF, VT);
1608 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1609 // if it is not already.
1610 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO;
1611 if (NewCond != Cond)
1612 return DAG.getSetCC(VT, N0, N1, NewCond);
1615 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1616 MVT::isInteger(N0.getValueType())) {
1617 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1618 N0.getOpcode() == ISD::XOR) {
1619 // Simplify (X+Y) == (X+Z) --> Y == Z
1620 if (N0.getOpcode() == N1.getOpcode()) {
1621 if (N0.getOperand(0) == N1.getOperand(0))
1622 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
1623 if (N0.getOperand(1) == N1.getOperand(1))
1624 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
1625 if (isCommutativeBinOp(N0.getOpcode())) {
1626 // If X op Y == Y op X, try other combinations.
1627 if (N0.getOperand(0) == N1.getOperand(1))
1628 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
1629 if (N0.getOperand(1) == N1.getOperand(0))
1630 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
1634 // Simplify (X+Z) == X --> Z == 0
1635 if (N0.getOperand(0) == N1)
1636 return DAG.getSetCC(VT, N0.getOperand(1),
1637 DAG.getConstant(0, N0.getValueType()), Cond);
1638 if (N0.getOperand(1) == N1) {
1639 if (isCommutativeBinOp(N0.getOpcode()))
1640 return DAG.getSetCC(VT, N0.getOperand(0),
1641 DAG.getConstant(0, N0.getValueType()), Cond);
1643 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1644 // (Z-X) == X --> Z == X<<1
1645 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
1647 DAG.getConstant(1,TLI.getShiftAmountTy()));
1648 WorkList.push_back(SH.Val);
1649 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
1654 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1655 N1.getOpcode() == ISD::XOR) {
1656 // Simplify X == (X+Z) --> Z == 0
1657 if (N1.getOperand(0) == N0) {
1658 return DAG.getSetCC(VT, N1.getOperand(1),
1659 DAG.getConstant(0, N1.getValueType()), Cond);
1660 } else if (N1.getOperand(1) == N0) {
1661 if (isCommutativeBinOp(N1.getOpcode())) {
1662 return DAG.getSetCC(VT, N1.getOperand(0),
1663 DAG.getConstant(0, N1.getValueType()), Cond);
1665 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1666 // X == (Z-X) --> X<<1 == Z
1667 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
1668 DAG.getConstant(1,TLI.getShiftAmountTy()));
1669 WorkList.push_back(SH.Val);
1670 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
1676 // Fold away ALL boolean setcc's.
1678 if (N0.getValueType() == MVT::i1) {
1680 default: assert(0 && "Unknown integer setcc!");
1681 case ISD::SETEQ: // X == Y -> (X^Y)^1
1682 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1683 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
1684 WorkList.push_back(Temp.Val);
1686 case ISD::SETNE: // X != Y --> (X^Y)
1687 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1689 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
1690 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
1691 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1692 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
1693 WorkList.push_back(Temp.Val);
1695 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
1696 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
1697 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1698 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
1699 WorkList.push_back(Temp.Val);
1701 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
1702 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
1703 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1704 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
1705 WorkList.push_back(Temp.Val);
1707 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
1708 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
1709 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1710 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
1713 if (VT != MVT::i1) {
1714 WorkList.push_back(N0.Val);
1715 // FIXME: If running after legalize, we probably can't do this.
1716 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1721 // Could not fold it.
1725 // SelectionDAG::Combine - This is the entry point for the file.
1727 void SelectionDAG::Combine(bool RunningAfterLegalize) {
1728 /// run - This is the main entry point to this class.
1730 DAGCombiner(*this).Run(RunningAfterLegalize);