1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/Target/TargetData.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/SmallPtrSet.h"
39 #include "llvm/ADT/Statistic.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/MathExtras.h"
47 STATISTIC(NodesCombined , "Number of dag nodes combined");
48 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
49 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
54 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
55 cl::desc("Pop up a window to show dags before the first "
58 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
59 cl::desc("Pop up a window to show dags before the second "
62 static const bool ViewDAGCombine1 = false;
63 static const bool ViewDAGCombine2 = false;
67 CombinerAA("combiner-alias-analysis", cl::Hidden,
68 cl::desc("Turn on alias analysis during testing"));
71 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
72 cl::desc("Include global information in alias analysis"));
74 //------------------------------ DAGCombiner ---------------------------------//
76 class VISIBILITY_HIDDEN DAGCombiner {
81 // Worklist of all of the nodes that need to be simplified.
82 std::vector<SDNode*> WorkList;
84 // AA - Used for DAG load/store alias analysis.
87 /// AddUsersToWorkList - When an instruction is simplified, add all users of
88 /// the instruction to the work lists because they might get more simplified
91 void AddUsersToWorkList(SDNode *N) {
92 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
97 /// removeFromWorkList - remove all instances of N from the worklist.
99 void removeFromWorkList(SDNode *N) {
100 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
104 /// visit - call the node-specific routine that knows how to fold each
105 /// particular type of node.
106 SDOperand visit(SDNode *N);
109 /// AddToWorkList - Add to the work list making sure it's instance is at the
110 /// the back (next to be processed.)
111 void AddToWorkList(SDNode *N) {
112 removeFromWorkList(N);
113 WorkList.push_back(N);
116 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
118 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
120 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
121 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
122 DOUT << " and " << NumTo-1 << " other values\n";
123 std::vector<SDNode*> NowDead;
124 DAG.ReplaceAllUsesWith(N, To, &NowDead);
127 // Push the new nodes and any users onto the worklist
128 for (unsigned i = 0, e = NumTo; i != e; ++i) {
129 AddToWorkList(To[i].Val);
130 AddUsersToWorkList(To[i].Val);
134 // Nodes can be reintroduced into the worklist. Make sure we do not
135 // process a node that has been replaced.
136 removeFromWorkList(N);
137 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
138 removeFromWorkList(NowDead[i]);
140 // Finally, since the node is now dead, remove it from the graph.
142 return SDOperand(N, 0);
145 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
146 return CombineTo(N, &Res, 1, AddTo);
149 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
151 SDOperand To[] = { Res0, Res1 };
152 return CombineTo(N, To, 2, AddTo);
156 /// SimplifyDemandedBits - Check the specified integer node value to see if
157 /// it can be simplified or if things it uses can be simplified by bit
158 /// propagation. If so, return true.
159 bool SimplifyDemandedBits(SDOperand Op) {
160 TargetLowering::TargetLoweringOpt TLO(DAG);
161 uint64_t KnownZero, KnownOne;
162 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
163 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
167 AddToWorkList(Op.Val);
169 // Replace the old value with the new one.
171 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
172 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
175 std::vector<SDNode*> NowDead;
176 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
178 // Push the new node and any (possibly new) users onto the worklist.
179 AddToWorkList(TLO.New.Val);
180 AddUsersToWorkList(TLO.New.Val);
182 // Nodes can end up on the worklist more than once. Make sure we do
183 // not process a node that has been replaced.
184 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
185 removeFromWorkList(NowDead[i]);
187 // Finally, if the node is now dead, remove it from the graph. The node
188 // may not be dead if the replacement process recursively simplified to
189 // something else needing this node.
190 if (TLO.Old.Val->use_empty()) {
191 removeFromWorkList(TLO.Old.Val);
193 // If the operands of this node are only used by the node, they will now
194 // be dead. Make sure to visit them first to delete dead nodes early.
195 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i)
196 if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
197 AddToWorkList(TLO.Old.Val->getOperand(i).Val);
199 DAG.DeleteNode(TLO.Old.Val);
204 bool CombineToPreIndexedLoadStore(SDNode *N);
205 bool CombineToPostIndexedLoadStore(SDNode *N);
208 /// combine - call the node-specific routine that knows how to fold each
209 /// particular type of node. If that doesn't do anything, try the
210 /// target-specific DAG combines.
211 SDOperand combine(SDNode *N);
213 // Visitation implementation - Implement dag node combining for different
214 // node types. The semantics are as follows:
216 // SDOperand.Val == 0 - No change was made
217 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
218 // otherwise - N should be replaced by the returned Operand.
220 SDOperand visitTokenFactor(SDNode *N);
221 SDOperand visitADD(SDNode *N);
222 SDOperand visitSUB(SDNode *N);
223 SDOperand visitADDC(SDNode *N);
224 SDOperand visitADDE(SDNode *N);
225 SDOperand visitMUL(SDNode *N);
226 SDOperand visitSDIV(SDNode *N);
227 SDOperand visitUDIV(SDNode *N);
228 SDOperand visitSREM(SDNode *N);
229 SDOperand visitUREM(SDNode *N);
230 SDOperand visitMULHU(SDNode *N);
231 SDOperand visitMULHS(SDNode *N);
232 SDOperand visitSMUL_LOHI(SDNode *N);
233 SDOperand visitUMUL_LOHI(SDNode *N);
234 SDOperand visitSDIVREM(SDNode *N);
235 SDOperand visitUDIVREM(SDNode *N);
236 SDOperand visitAND(SDNode *N);
237 SDOperand visitOR(SDNode *N);
238 SDOperand visitXOR(SDNode *N);
239 SDOperand SimplifyVBinOp(SDNode *N);
240 SDOperand visitSHL(SDNode *N);
241 SDOperand visitSRA(SDNode *N);
242 SDOperand visitSRL(SDNode *N);
243 SDOperand visitCTLZ(SDNode *N);
244 SDOperand visitCTTZ(SDNode *N);
245 SDOperand visitCTPOP(SDNode *N);
246 SDOperand visitSELECT(SDNode *N);
247 SDOperand visitSELECT_CC(SDNode *N);
248 SDOperand visitSETCC(SDNode *N);
249 SDOperand visitSIGN_EXTEND(SDNode *N);
250 SDOperand visitZERO_EXTEND(SDNode *N);
251 SDOperand visitANY_EXTEND(SDNode *N);
252 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
253 SDOperand visitTRUNCATE(SDNode *N);
254 SDOperand visitBIT_CONVERT(SDNode *N);
255 SDOperand visitFADD(SDNode *N);
256 SDOperand visitFSUB(SDNode *N);
257 SDOperand visitFMUL(SDNode *N);
258 SDOperand visitFDIV(SDNode *N);
259 SDOperand visitFREM(SDNode *N);
260 SDOperand visitFCOPYSIGN(SDNode *N);
261 SDOperand visitSINT_TO_FP(SDNode *N);
262 SDOperand visitUINT_TO_FP(SDNode *N);
263 SDOperand visitFP_TO_SINT(SDNode *N);
264 SDOperand visitFP_TO_UINT(SDNode *N);
265 SDOperand visitFP_ROUND(SDNode *N);
266 SDOperand visitFP_ROUND_INREG(SDNode *N);
267 SDOperand visitFP_EXTEND(SDNode *N);
268 SDOperand visitFNEG(SDNode *N);
269 SDOperand visitFABS(SDNode *N);
270 SDOperand visitBRCOND(SDNode *N);
271 SDOperand visitBR_CC(SDNode *N);
272 SDOperand visitLOAD(SDNode *N);
273 SDOperand visitSTORE(SDNode *N);
274 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
275 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N);
276 SDOperand visitBUILD_VECTOR(SDNode *N);
277 SDOperand visitCONCAT_VECTORS(SDNode *N);
278 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
280 SDOperand XformToShuffleWithZero(SDNode *N);
281 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
283 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
284 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
285 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
286 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
287 SDOperand N3, ISD::CondCode CC,
288 bool NotExtCompare = false);
289 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
290 ISD::CondCode Cond, bool foldBooleans = true);
291 bool SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp);
292 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
293 SDOperand BuildSDIV(SDNode *N);
294 SDOperand BuildUDIV(SDNode *N);
295 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
296 SDOperand ReduceLoadWidth(SDNode *N);
298 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
299 /// looking for aliasing nodes and adding them to the Aliases vector.
300 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
301 SmallVector<SDOperand, 8> &Aliases);
303 /// isAlias - Return true if there is any possibility that the two addresses
305 bool isAlias(SDOperand Ptr1, int64_t Size1,
306 const Value *SrcValue1, int SrcValueOffset1,
307 SDOperand Ptr2, int64_t Size2,
308 const Value *SrcValue2, int SrcValueOffset2);
310 /// FindAliasInfo - Extracts the relevant alias information from the memory
311 /// node. Returns true if the operand was a load.
312 bool FindAliasInfo(SDNode *N,
313 SDOperand &Ptr, int64_t &Size,
314 const Value *&SrcValue, int &SrcValueOffset);
316 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
317 /// looking for a better chain (aliasing node.)
318 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
321 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
323 TLI(D.getTargetLoweringInfo()),
324 AfterLegalize(false),
327 /// Run - runs the dag combiner on all nodes in the work list
328 void Run(bool RunningAfterLegalize);
332 //===----------------------------------------------------------------------===//
333 // TargetLowering::DAGCombinerInfo implementation
334 //===----------------------------------------------------------------------===//
336 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
337 ((DAGCombiner*)DC)->AddToWorkList(N);
340 SDOperand TargetLowering::DAGCombinerInfo::
341 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
342 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
345 SDOperand TargetLowering::DAGCombinerInfo::
346 CombineTo(SDNode *N, SDOperand Res) {
347 return ((DAGCombiner*)DC)->CombineTo(N, Res);
351 SDOperand TargetLowering::DAGCombinerInfo::
352 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
353 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
357 //===----------------------------------------------------------------------===//
359 //===----------------------------------------------------------------------===//
361 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
362 /// specified expression for the same cost as the expression itself, or 2 if we
363 /// can compute the negated form more cheaply than the expression itself.
364 static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) {
365 // fneg is removable even if it has multiple uses.
366 if (Op.getOpcode() == ISD::FNEG) return 2;
368 // Don't allow anything with multiple uses.
369 if (!Op.hasOneUse()) return 0;
371 // Don't recurse exponentially.
372 if (Depth > 6) return 0;
374 switch (Op.getOpcode()) {
375 default: return false;
376 case ISD::ConstantFP:
379 // FIXME: determine better conditions for this xform.
380 if (!UnsafeFPMath) return 0;
383 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
386 return isNegatibleForFree(Op.getOperand(1), Depth+1);
388 // We can't turn -(A-B) into B-A when we honor signed zeros.
389 if (!UnsafeFPMath) return 0;
396 if (HonorSignDependentRoundingFPMath()) return 0;
398 // -(X*Y) -> (-X * Y) or (X*-Y)
399 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
402 return isNegatibleForFree(Op.getOperand(1), Depth+1);
407 return isNegatibleForFree(Op.getOperand(0), Depth+1);
411 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
412 /// returns the newly negated expression.
413 static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
414 unsigned Depth = 0) {
415 // fneg is removable even if it has multiple uses.
416 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
418 // Don't allow anything with multiple uses.
419 assert(Op.hasOneUse() && "Unknown reuse!");
421 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
422 switch (Op.getOpcode()) {
423 default: assert(0 && "Unknown code");
424 case ISD::ConstantFP: {
425 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
427 return DAG.getConstantFP(V, Op.getValueType());
430 // FIXME: determine better conditions for this xform.
431 assert(UnsafeFPMath);
434 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
435 return DAG.getNode(ISD::FSUB, Op.getValueType(),
436 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
439 return DAG.getNode(ISD::FSUB, Op.getValueType(),
440 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1),
443 // We can't turn -(A-B) into B-A when we honor signed zeros.
444 assert(UnsafeFPMath);
447 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
448 if (N0CFP->getValueAPF().isZero())
449 return Op.getOperand(1);
452 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1),
457 assert(!HonorSignDependentRoundingFPMath());
460 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
461 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
462 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
466 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
468 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1));
473 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
474 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1));
479 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
480 // that selects between the values 1 and 0, making it equivalent to a setcc.
481 // Also, set the incoming LHS, RHS, and CC references to the appropriate
482 // nodes based on the type of node we are checking. This simplifies life a
483 // bit for the callers.
484 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
486 if (N.getOpcode() == ISD::SETCC) {
487 LHS = N.getOperand(0);
488 RHS = N.getOperand(1);
489 CC = N.getOperand(2);
492 if (N.getOpcode() == ISD::SELECT_CC &&
493 N.getOperand(2).getOpcode() == ISD::Constant &&
494 N.getOperand(3).getOpcode() == ISD::Constant &&
495 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
496 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
497 LHS = N.getOperand(0);
498 RHS = N.getOperand(1);
499 CC = N.getOperand(4);
505 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
506 // one use. If this is true, it allows the users to invert the operation for
507 // free when it is profitable to do so.
508 static bool isOneUseSetCC(SDOperand N) {
509 SDOperand N0, N1, N2;
510 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
515 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
516 MVT::ValueType VT = N0.getValueType();
517 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
518 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
519 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
520 if (isa<ConstantSDNode>(N1)) {
521 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
522 AddToWorkList(OpNode.Val);
523 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
524 } else if (N0.hasOneUse()) {
525 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
526 AddToWorkList(OpNode.Val);
527 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
530 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
531 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
532 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
533 if (isa<ConstantSDNode>(N0)) {
534 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
535 AddToWorkList(OpNode.Val);
536 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
537 } else if (N1.hasOneUse()) {
538 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
539 AddToWorkList(OpNode.Val);
540 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
546 //===----------------------------------------------------------------------===//
547 // Main DAG Combiner implementation
548 //===----------------------------------------------------------------------===//
550 void DAGCombiner::Run(bool RunningAfterLegalize) {
551 // set the instance variable, so that the various visit routines may use it.
552 AfterLegalize = RunningAfterLegalize;
554 // Add all the dag nodes to the worklist.
555 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
556 E = DAG.allnodes_end(); I != E; ++I)
557 WorkList.push_back(I);
559 // Create a dummy node (which is not added to allnodes), that adds a reference
560 // to the root node, preventing it from being deleted, and tracking any
561 // changes of the root.
562 HandleSDNode Dummy(DAG.getRoot());
564 // The root of the dag may dangle to deleted nodes until the dag combiner is
565 // done. Set it to null to avoid confusion.
566 DAG.setRoot(SDOperand());
568 // while the worklist isn't empty, inspect the node on the end of it and
569 // try and combine it.
570 while (!WorkList.empty()) {
571 SDNode *N = WorkList.back();
574 // If N has no uses, it is dead. Make sure to revisit all N's operands once
575 // N is deleted from the DAG, since they too may now be dead or may have a
576 // reduced number of uses, allowing other xforms.
577 if (N->use_empty() && N != &Dummy) {
578 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
579 AddToWorkList(N->getOperand(i).Val);
585 SDOperand RV = combine(N);
589 // If we get back the same node we passed in, rather than a new node or
590 // zero, we know that the node must have defined multiple values and
591 // CombineTo was used. Since CombineTo takes care of the worklist
592 // mechanics for us, we have no work to do in this case.
594 assert(N->getOpcode() != ISD::DELETED_NODE &&
595 RV.Val->getOpcode() != ISD::DELETED_NODE &&
596 "Node was deleted but visit returned new node!");
598 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
599 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
601 std::vector<SDNode*> NowDead;
602 if (N->getNumValues() == RV.Val->getNumValues())
603 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
605 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
607 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
610 // Push the new node and any users onto the worklist
611 AddToWorkList(RV.Val);
612 AddUsersToWorkList(RV.Val);
614 // Nodes can be reintroduced into the worklist. Make sure we do not
615 // process a node that has been replaced.
616 removeFromWorkList(N);
617 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
618 removeFromWorkList(NowDead[i]);
620 // Finally, since the node is now dead, remove it from the graph.
626 // If the root changed (e.g. it was a dead load, update the root).
627 DAG.setRoot(Dummy.getValue());
630 SDOperand DAGCombiner::visit(SDNode *N) {
631 switch(N->getOpcode()) {
633 case ISD::TokenFactor: return visitTokenFactor(N);
634 case ISD::ADD: return visitADD(N);
635 case ISD::SUB: return visitSUB(N);
636 case ISD::ADDC: return visitADDC(N);
637 case ISD::ADDE: return visitADDE(N);
638 case ISD::MUL: return visitMUL(N);
639 case ISD::SDIV: return visitSDIV(N);
640 case ISD::UDIV: return visitUDIV(N);
641 case ISD::SREM: return visitSREM(N);
642 case ISD::UREM: return visitUREM(N);
643 case ISD::MULHU: return visitMULHU(N);
644 case ISD::MULHS: return visitMULHS(N);
645 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
646 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
647 case ISD::SDIVREM: return visitSDIVREM(N);
648 case ISD::UDIVREM: return visitUDIVREM(N);
649 case ISD::AND: return visitAND(N);
650 case ISD::OR: return visitOR(N);
651 case ISD::XOR: return visitXOR(N);
652 case ISD::SHL: return visitSHL(N);
653 case ISD::SRA: return visitSRA(N);
654 case ISD::SRL: return visitSRL(N);
655 case ISD::CTLZ: return visitCTLZ(N);
656 case ISD::CTTZ: return visitCTTZ(N);
657 case ISD::CTPOP: return visitCTPOP(N);
658 case ISD::SELECT: return visitSELECT(N);
659 case ISD::SELECT_CC: return visitSELECT_CC(N);
660 case ISD::SETCC: return visitSETCC(N);
661 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
662 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
663 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
664 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
665 case ISD::TRUNCATE: return visitTRUNCATE(N);
666 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
667 case ISD::FADD: return visitFADD(N);
668 case ISD::FSUB: return visitFSUB(N);
669 case ISD::FMUL: return visitFMUL(N);
670 case ISD::FDIV: return visitFDIV(N);
671 case ISD::FREM: return visitFREM(N);
672 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
673 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
674 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
675 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
676 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
677 case ISD::FP_ROUND: return visitFP_ROUND(N);
678 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
679 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
680 case ISD::FNEG: return visitFNEG(N);
681 case ISD::FABS: return visitFABS(N);
682 case ISD::BRCOND: return visitBRCOND(N);
683 case ISD::BR_CC: return visitBR_CC(N);
684 case ISD::LOAD: return visitLOAD(N);
685 case ISD::STORE: return visitSTORE(N);
686 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
687 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
688 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
689 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
690 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
695 SDOperand DAGCombiner::combine(SDNode *N) {
697 SDOperand RV = visit(N);
699 // If nothing happened, try a target-specific DAG combine.
701 assert(N->getOpcode() != ISD::DELETED_NODE &&
702 "Node was deleted but visit returned NULL!");
704 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
705 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
707 // Expose the DAG combiner to the target combiner impls.
708 TargetLowering::DAGCombinerInfo
709 DagCombineInfo(DAG, !AfterLegalize, false, this);
711 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
718 /// getInputChainForNode - Given a node, return its input chain if it has one,
719 /// otherwise return a null sd operand.
720 static SDOperand getInputChainForNode(SDNode *N) {
721 if (unsigned NumOps = N->getNumOperands()) {
722 if (N->getOperand(0).getValueType() == MVT::Other)
723 return N->getOperand(0);
724 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
725 return N->getOperand(NumOps-1);
726 for (unsigned i = 1; i < NumOps-1; ++i)
727 if (N->getOperand(i).getValueType() == MVT::Other)
728 return N->getOperand(i);
730 return SDOperand(0, 0);
733 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
734 // If N has two operands, where one has an input chain equal to the other,
735 // the 'other' chain is redundant.
736 if (N->getNumOperands() == 2) {
737 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
738 return N->getOperand(0);
739 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
740 return N->getOperand(1);
743 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
744 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
745 SmallPtrSet<SDNode*, 16> SeenOps;
746 bool Changed = false; // If we should replace this token factor.
748 // Start out with this token factor.
751 // Iterate through token factors. The TFs grows when new token factors are
753 for (unsigned i = 0; i < TFs.size(); ++i) {
756 // Check each of the operands.
757 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
758 SDOperand Op = TF->getOperand(i);
760 switch (Op.getOpcode()) {
761 case ISD::EntryToken:
762 // Entry tokens don't need to be added to the list. They are
767 case ISD::TokenFactor:
768 if ((CombinerAA || Op.hasOneUse()) &&
769 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
770 // Queue up for processing.
771 TFs.push_back(Op.Val);
772 // Clean up in case the token factor is removed.
773 AddToWorkList(Op.Val);
780 // Only add if it isn't already in the list.
781 if (SeenOps.insert(Op.Val))
792 // If we've change things around then replace token factor.
794 if (Ops.size() == 0) {
795 // The entry token is the only possible outcome.
796 Result = DAG.getEntryNode();
798 // New and improved token factor.
799 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
802 // Don't add users to work list.
803 return CombineTo(N, Result, false);
810 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
811 MVT::ValueType VT = N0.getValueType();
812 SDOperand N00 = N0.getOperand(0);
813 SDOperand N01 = N0.getOperand(1);
814 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
815 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
816 isa<ConstantSDNode>(N00.getOperand(1))) {
817 N0 = DAG.getNode(ISD::ADD, VT,
818 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
819 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
820 return DAG.getNode(ISD::ADD, VT, N0, N1);
826 SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
828 MVT::ValueType VT = N->getValueType(0);
829 unsigned Opc = N->getOpcode();
830 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
831 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
832 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
833 ISD::CondCode CC = ISD::SETCC_INVALID;
835 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
837 SDOperand CCOp = Slct.getOperand(0);
838 if (CCOp.getOpcode() == ISD::SETCC)
839 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
842 bool DoXform = false;
844 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
846 if (LHS.getOpcode() == ISD::Constant &&
847 cast<ConstantSDNode>(LHS)->isNullValue())
849 else if (CC != ISD::SETCC_INVALID &&
850 RHS.getOpcode() == ISD::Constant &&
851 cast<ConstantSDNode>(RHS)->isNullValue()) {
853 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType()
854 : Slct.getOperand(0).getOperand(0).getValueType());
855 CC = ISD::getSetCCInverse(CC, isInt);
861 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS);
863 return DAG.getSelectCC(OtherOp, Result,
864 Slct.getOperand(0), Slct.getOperand(1), CC);
865 SDOperand CCOp = Slct.getOperand(0);
867 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
868 CCOp.getOperand(1), CC);
869 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
874 SDOperand DAGCombiner::visitADD(SDNode *N) {
875 SDOperand N0 = N->getOperand(0);
876 SDOperand N1 = N->getOperand(1);
877 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
878 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
879 MVT::ValueType VT = N0.getValueType();
882 if (MVT::isVector(VT)) {
883 SDOperand FoldedVOp = SimplifyVBinOp(N);
884 if (FoldedVOp.Val) return FoldedVOp;
887 // fold (add x, undef) -> undef
888 if (N0.getOpcode() == ISD::UNDEF)
890 if (N1.getOpcode() == ISD::UNDEF)
892 // fold (add c1, c2) -> c1+c2
894 return DAG.getNode(ISD::ADD, VT, N0, N1);
895 // canonicalize constant to RHS
897 return DAG.getNode(ISD::ADD, VT, N1, N0);
898 // fold (add x, 0) -> x
899 if (N1C && N1C->isNullValue())
901 // fold ((c1-A)+c2) -> (c1+c2)-A
902 if (N1C && N0.getOpcode() == ISD::SUB)
903 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
904 return DAG.getNode(ISD::SUB, VT,
905 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
908 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
911 // fold ((0-A) + B) -> B-A
912 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
913 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
914 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
915 // fold (A + (0-B)) -> A-B
916 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
917 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
918 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
919 // fold (A+(B-A)) -> B
920 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
921 return N1.getOperand(0);
923 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
924 return SDOperand(N, 0);
926 // fold (a+b) -> (a|b) iff a and b share no bits.
927 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
928 uint64_t LHSZero, LHSOne;
929 uint64_t RHSZero, RHSOne;
930 uint64_t Mask = MVT::getIntVTBitMask(VT);
931 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
933 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
935 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
936 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
937 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
938 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
939 return DAG.getNode(ISD::OR, VT, N0, N1);
943 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
944 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
945 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
946 if (Result.Val) return Result;
948 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
949 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
950 if (Result.Val) return Result;
953 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
954 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
955 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG);
956 if (Result.Val) return Result;
958 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
959 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
960 if (Result.Val) return Result;
966 SDOperand DAGCombiner::visitADDC(SDNode *N) {
967 SDOperand N0 = N->getOperand(0);
968 SDOperand N1 = N->getOperand(1);
969 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
970 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
971 MVT::ValueType VT = N0.getValueType();
973 // If the flag result is dead, turn this into an ADD.
974 if (N->hasNUsesOfValue(0, 1))
975 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
976 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
978 // canonicalize constant to RHS.
980 SDOperand Ops[] = { N1, N0 };
981 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
984 // fold (addc x, 0) -> x + no carry out
985 if (N1C && N1C->isNullValue())
986 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
988 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
989 uint64_t LHSZero, LHSOne;
990 uint64_t RHSZero, RHSOne;
991 uint64_t Mask = MVT::getIntVTBitMask(VT);
992 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
994 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
996 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
997 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
998 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
999 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1000 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
1001 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
1007 SDOperand DAGCombiner::visitADDE(SDNode *N) {
1008 SDOperand N0 = N->getOperand(0);
1009 SDOperand N1 = N->getOperand(1);
1010 SDOperand CarryIn = N->getOperand(2);
1011 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1012 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1013 //MVT::ValueType VT = N0.getValueType();
1015 // canonicalize constant to RHS
1017 SDOperand Ops[] = { N1, N0, CarryIn };
1018 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
1021 // fold (adde x, y, false) -> (addc x, y)
1022 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
1023 SDOperand Ops[] = { N1, N0 };
1024 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
1032 SDOperand DAGCombiner::visitSUB(SDNode *N) {
1033 SDOperand N0 = N->getOperand(0);
1034 SDOperand N1 = N->getOperand(1);
1035 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1036 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1037 MVT::ValueType VT = N0.getValueType();
1040 if (MVT::isVector(VT)) {
1041 SDOperand FoldedVOp = SimplifyVBinOp(N);
1042 if (FoldedVOp.Val) return FoldedVOp;
1045 // fold (sub x, x) -> 0
1047 return DAG.getConstant(0, N->getValueType(0));
1048 // fold (sub c1, c2) -> c1-c2
1050 return DAG.getNode(ISD::SUB, VT, N0, N1);
1051 // fold (sub x, c) -> (add x, -c)
1053 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
1054 // fold (A+B)-A -> B
1055 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1056 return N0.getOperand(1);
1057 // fold (A+B)-B -> A
1058 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1059 return N0.getOperand(0);
1060 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1061 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
1062 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
1063 if (Result.Val) return Result;
1065 // If either operand of a sub is undef, the result is undef
1066 if (N0.getOpcode() == ISD::UNDEF)
1068 if (N1.getOpcode() == ISD::UNDEF)
1074 SDOperand DAGCombiner::visitMUL(SDNode *N) {
1075 SDOperand N0 = N->getOperand(0);
1076 SDOperand N1 = N->getOperand(1);
1077 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1078 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1079 MVT::ValueType VT = N0.getValueType();
1082 if (MVT::isVector(VT)) {
1083 SDOperand FoldedVOp = SimplifyVBinOp(N);
1084 if (FoldedVOp.Val) return FoldedVOp;
1087 // fold (mul x, undef) -> 0
1088 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1089 return DAG.getConstant(0, VT);
1090 // fold (mul c1, c2) -> c1*c2
1092 return DAG.getNode(ISD::MUL, VT, N0, N1);
1093 // canonicalize constant to RHS
1095 return DAG.getNode(ISD::MUL, VT, N1, N0);
1096 // fold (mul x, 0) -> 0
1097 if (N1C && N1C->isNullValue())
1099 // fold (mul x, -1) -> 0-x
1100 if (N1C && N1C->isAllOnesValue())
1101 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1102 // fold (mul x, (1 << c)) -> x << c
1103 if (N1C && isPowerOf2_64(N1C->getValue()))
1104 return DAG.getNode(ISD::SHL, VT, N0,
1105 DAG.getConstant(Log2_64(N1C->getValue()),
1106 TLI.getShiftAmountTy()));
1107 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1108 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
1109 // FIXME: If the input is something that is easily negated (e.g. a
1110 // single-use add), we should put the negate there.
1111 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
1112 DAG.getNode(ISD::SHL, VT, N0,
1113 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
1114 TLI.getShiftAmountTy())));
1117 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1118 if (N1C && N0.getOpcode() == ISD::SHL &&
1119 isa<ConstantSDNode>(N0.getOperand(1))) {
1120 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
1121 AddToWorkList(C3.Val);
1122 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
1125 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1128 SDOperand Sh(0,0), Y(0,0);
1129 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1130 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1131 N0.Val->hasOneUse()) {
1133 } else if (N1.getOpcode() == ISD::SHL &&
1134 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
1138 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
1139 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
1142 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1143 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1144 isa<ConstantSDNode>(N0.getOperand(1))) {
1145 return DAG.getNode(ISD::ADD, VT,
1146 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
1147 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
1151 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
1158 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
1159 SDOperand N0 = N->getOperand(0);
1160 SDOperand N1 = N->getOperand(1);
1161 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1162 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1163 MVT::ValueType VT = N->getValueType(0);
1166 if (MVT::isVector(VT)) {
1167 SDOperand FoldedVOp = SimplifyVBinOp(N);
1168 if (FoldedVOp.Val) return FoldedVOp;
1171 // fold (sdiv c1, c2) -> c1/c2
1172 if (N0C && N1C && !N1C->isNullValue())
1173 return DAG.getNode(ISD::SDIV, VT, N0, N1);
1174 // fold (sdiv X, 1) -> X
1175 if (N1C && N1C->getSignExtended() == 1LL)
1177 // fold (sdiv X, -1) -> 0-X
1178 if (N1C && N1C->isAllOnesValue())
1179 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1180 // If we know the sign bits of both operands are zero, strength reduce to a
1181 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1182 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1183 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1184 DAG.MaskedValueIsZero(N0, SignBit))
1185 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
1186 // fold (sdiv X, pow2) -> simple ops after legalize
1187 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
1188 (isPowerOf2_64(N1C->getSignExtended()) ||
1189 isPowerOf2_64(-N1C->getSignExtended()))) {
1190 // If dividing by powers of two is cheap, then don't perform the following
1192 if (TLI.isPow2DivCheap())
1194 int64_t pow2 = N1C->getSignExtended();
1195 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1196 unsigned lg2 = Log2_64(abs2);
1197 // Splat the sign bit into the register
1198 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
1199 DAG.getConstant(MVT::getSizeInBits(VT)-1,
1200 TLI.getShiftAmountTy()));
1201 AddToWorkList(SGN.Val);
1202 // Add (N0 < 0) ? abs2 - 1 : 0;
1203 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
1204 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
1205 TLI.getShiftAmountTy()));
1206 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
1207 AddToWorkList(SRL.Val);
1208 AddToWorkList(ADD.Val); // Divide by pow2
1209 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
1210 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
1211 // If we're dividing by a positive value, we're done. Otherwise, we must
1212 // negate the result.
1215 AddToWorkList(SRA.Val);
1216 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
1218 // if integer divide is expensive and we satisfy the requirements, emit an
1219 // alternate sequence.
1220 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
1221 !TLI.isIntDivCheap()) {
1222 SDOperand Op = BuildSDIV(N);
1223 if (Op.Val) return Op;
1227 if (N0.getOpcode() == ISD::UNDEF)
1228 return DAG.getConstant(0, VT);
1229 // X / undef -> undef
1230 if (N1.getOpcode() == ISD::UNDEF)
1236 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
1237 SDOperand N0 = N->getOperand(0);
1238 SDOperand N1 = N->getOperand(1);
1239 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1240 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1241 MVT::ValueType VT = N->getValueType(0);
1244 if (MVT::isVector(VT)) {
1245 SDOperand FoldedVOp = SimplifyVBinOp(N);
1246 if (FoldedVOp.Val) return FoldedVOp;
1249 // fold (udiv c1, c2) -> c1/c2
1250 if (N0C && N1C && !N1C->isNullValue())
1251 return DAG.getNode(ISD::UDIV, VT, N0, N1);
1252 // fold (udiv x, (1 << c)) -> x >>u c
1253 if (N1C && isPowerOf2_64(N1C->getValue()))
1254 return DAG.getNode(ISD::SRL, VT, N0,
1255 DAG.getConstant(Log2_64(N1C->getValue()),
1256 TLI.getShiftAmountTy()));
1257 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1258 if (N1.getOpcode() == ISD::SHL) {
1259 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1260 if (isPowerOf2_64(SHC->getValue())) {
1261 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
1262 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
1263 DAG.getConstant(Log2_64(SHC->getValue()),
1265 AddToWorkList(Add.Val);
1266 return DAG.getNode(ISD::SRL, VT, N0, Add);
1270 // fold (udiv x, c) -> alternate
1271 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1272 SDOperand Op = BuildUDIV(N);
1273 if (Op.Val) return Op;
1277 if (N0.getOpcode() == ISD::UNDEF)
1278 return DAG.getConstant(0, VT);
1279 // X / undef -> undef
1280 if (N1.getOpcode() == ISD::UNDEF)
1286 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1287 SDOperand N0 = N->getOperand(0);
1288 SDOperand N1 = N->getOperand(1);
1289 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1290 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1291 MVT::ValueType VT = N->getValueType(0);
1293 // fold (srem c1, c2) -> c1%c2
1294 if (N0C && N1C && !N1C->isNullValue())
1295 return DAG.getNode(ISD::SREM, VT, N0, N1);
1296 // If we know the sign bits of both operands are zero, strength reduce to a
1297 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1298 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1299 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1300 DAG.MaskedValueIsZero(N0, SignBit))
1301 return DAG.getNode(ISD::UREM, VT, N0, N1);
1303 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1304 // the remainder operation.
1305 if (N1C && !N1C->isNullValue()) {
1306 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1307 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1308 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1309 AddToWorkList(Div.Val);
1310 AddToWorkList(Mul.Val);
1315 if (N0.getOpcode() == ISD::UNDEF)
1316 return DAG.getConstant(0, VT);
1317 // X % undef -> undef
1318 if (N1.getOpcode() == ISD::UNDEF)
1324 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1325 SDOperand N0 = N->getOperand(0);
1326 SDOperand N1 = N->getOperand(1);
1327 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1328 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1329 MVT::ValueType VT = N->getValueType(0);
1331 // fold (urem c1, c2) -> c1%c2
1332 if (N0C && N1C && !N1C->isNullValue())
1333 return DAG.getNode(ISD::UREM, VT, N0, N1);
1334 // fold (urem x, pow2) -> (and x, pow2-1)
1335 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1336 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1337 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1338 if (N1.getOpcode() == ISD::SHL) {
1339 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1340 if (isPowerOf2_64(SHC->getValue())) {
1341 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1342 AddToWorkList(Add.Val);
1343 return DAG.getNode(ISD::AND, VT, N0, Add);
1348 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1349 // the remainder operation.
1350 if (N1C && !N1C->isNullValue()) {
1351 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1352 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1353 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1354 AddToWorkList(Div.Val);
1355 AddToWorkList(Mul.Val);
1360 if (N0.getOpcode() == ISD::UNDEF)
1361 return DAG.getConstant(0, VT);
1362 // X % undef -> undef
1363 if (N1.getOpcode() == ISD::UNDEF)
1369 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1370 SDOperand N0 = N->getOperand(0);
1371 SDOperand N1 = N->getOperand(1);
1372 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1373 MVT::ValueType VT = N->getValueType(0);
1375 // fold (mulhs x, 0) -> 0
1376 if (N1C && N1C->isNullValue())
1378 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1379 if (N1C && N1C->getValue() == 1)
1380 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1381 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1382 TLI.getShiftAmountTy()));
1383 // fold (mulhs x, undef) -> 0
1384 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1385 return DAG.getConstant(0, VT);
1390 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1391 SDOperand N0 = N->getOperand(0);
1392 SDOperand N1 = N->getOperand(1);
1393 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1394 MVT::ValueType VT = N->getValueType(0);
1396 // fold (mulhu x, 0) -> 0
1397 if (N1C && N1C->isNullValue())
1399 // fold (mulhu x, 1) -> 0
1400 if (N1C && N1C->getValue() == 1)
1401 return DAG.getConstant(0, N0.getValueType());
1402 // fold (mulhu x, undef) -> 0
1403 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1404 return DAG.getConstant(0, VT);
1409 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1410 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1411 /// that are being performed. Return true if a simplification was made.
1413 bool DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N,
1414 unsigned LoOp, unsigned HiOp) {
1415 std::vector<SDNode*> NowDead;
1417 // If the high half is not needed, just compute the low half.
1418 if (!N->hasAnyUseOfValue(1) &&
1420 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1421 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0),
1422 DAG.getNode(LoOp, N->getValueType(0),
1424 N->getNumOperands()),
1429 // If the low half is not needed, just compute the high half.
1430 if (!N->hasAnyUseOfValue(0) &&
1432 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1433 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1),
1434 DAG.getNode(HiOp, N->getValueType(1),
1436 N->getNumOperands()),
1441 // If the two computed results can be siplified separately, separate them.
1442 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0),
1443 N->op_begin(), N->getNumOperands());
1444 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1),
1445 N->op_begin(), N->getNumOperands());
1446 unsigned LoExists = !Lo.use_empty();
1447 unsigned HiExists = !Hi.use_empty();
1448 SDOperand LoOpt = Lo;
1449 SDOperand HiOpt = Hi;
1450 if (!LoExists || !HiExists) {
1451 SDOperand Pair = DAG.getNode(ISD::BUILD_PAIR, MVT::Other, Lo, Hi);
1452 assert(Pair.use_empty() && "Pair with type MVT::Other already exists!");
1453 LoOpt = combine(Lo.Val);
1454 HiOpt = combine(Hi.Val);
1456 LoOpt = Pair.getOperand(0);
1458 HiOpt = Pair.getOperand(1);
1459 DAG.DeleteNode(Pair.Val);
1461 if ((LoExists || LoOpt != Lo) &&
1462 (HiExists || HiOpt != Hi) &&
1463 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()) &&
1464 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) {
1465 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), LoOpt, NowDead);
1466 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), HiOpt, NowDead);
1473 SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1475 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
1481 SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1483 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
1489 SDOperand DAGCombiner::visitSDIVREM(SDNode *N) {
1491 if (SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM))
1497 SDOperand DAGCombiner::visitUDIVREM(SDNode *N) {
1499 if (SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM))
1505 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1506 /// two operands of the same opcode, try to simplify it.
1507 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1508 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1509 MVT::ValueType VT = N0.getValueType();
1510 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1512 // For each of OP in AND/OR/XOR:
1513 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1514 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1515 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1516 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1517 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1518 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1519 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1520 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1521 N0.getOperand(0).getValueType(),
1522 N0.getOperand(0), N1.getOperand(0));
1523 AddToWorkList(ORNode.Val);
1524 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1527 // For each of OP in SHL/SRL/SRA/AND...
1528 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1529 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1530 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1531 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1532 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1533 N0.getOperand(1) == N1.getOperand(1)) {
1534 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1535 N0.getOperand(0).getValueType(),
1536 N0.getOperand(0), N1.getOperand(0));
1537 AddToWorkList(ORNode.Val);
1538 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1544 SDOperand DAGCombiner::visitAND(SDNode *N) {
1545 SDOperand N0 = N->getOperand(0);
1546 SDOperand N1 = N->getOperand(1);
1547 SDOperand LL, LR, RL, RR, CC0, CC1;
1548 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1549 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1550 MVT::ValueType VT = N1.getValueType();
1553 if (MVT::isVector(VT)) {
1554 SDOperand FoldedVOp = SimplifyVBinOp(N);
1555 if (FoldedVOp.Val) return FoldedVOp;
1558 // fold (and x, undef) -> 0
1559 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1560 return DAG.getConstant(0, VT);
1561 // fold (and c1, c2) -> c1&c2
1563 return DAG.getNode(ISD::AND, VT, N0, N1);
1564 // canonicalize constant to RHS
1566 return DAG.getNode(ISD::AND, VT, N1, N0);
1567 // fold (and x, -1) -> x
1568 if (N1C && N1C->isAllOnesValue())
1570 // if (and x, c) is known to be zero, return 0
1571 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1572 return DAG.getConstant(0, VT);
1574 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1577 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1578 if (N1C && N0.getOpcode() == ISD::OR)
1579 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1580 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1582 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1583 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1584 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1585 if (DAG.MaskedValueIsZero(N0.getOperand(0),
1586 ~N1C->getValue() & InMask)) {
1587 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1590 // Replace uses of the AND with uses of the Zero extend node.
1593 // We actually want to replace all uses of the any_extend with the
1594 // zero_extend, to avoid duplicating things. This will later cause this
1595 // AND to be folded.
1596 CombineTo(N0.Val, Zext);
1597 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1600 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1601 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1602 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1603 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1605 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1606 MVT::isInteger(LL.getValueType())) {
1607 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1608 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1609 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1610 AddToWorkList(ORNode.Val);
1611 return DAG.getSetCC(VT, ORNode, LR, Op1);
1613 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1614 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1615 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1616 AddToWorkList(ANDNode.Val);
1617 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1619 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1620 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1621 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1622 AddToWorkList(ORNode.Val);
1623 return DAG.getSetCC(VT, ORNode, LR, Op1);
1626 // canonicalize equivalent to ll == rl
1627 if (LL == RR && LR == RL) {
1628 Op1 = ISD::getSetCCSwappedOperands(Op1);
1631 if (LL == RL && LR == RR) {
1632 bool isInteger = MVT::isInteger(LL.getValueType());
1633 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1634 if (Result != ISD::SETCC_INVALID)
1635 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1639 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1640 if (N0.getOpcode() == N1.getOpcode()) {
1641 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1642 if (Tmp.Val) return Tmp;
1645 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1646 // fold (and (sra)) -> (and (srl)) when possible.
1647 if (!MVT::isVector(VT) &&
1648 SimplifyDemandedBits(SDOperand(N, 0)))
1649 return SDOperand(N, 0);
1650 // fold (zext_inreg (extload x)) -> (zextload x)
1651 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
1652 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1653 MVT::ValueType EVT = LN0->getLoadedVT();
1654 // If we zero all the possible extended bits, then we can turn this into
1655 // a zextload if we are running before legalize or the operation is legal.
1656 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1657 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1658 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1659 LN0->getBasePtr(), LN0->getSrcValue(),
1660 LN0->getSrcValueOffset(), EVT,
1662 LN0->getAlignment());
1664 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1665 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1668 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1669 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
1671 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1672 MVT::ValueType EVT = LN0->getLoadedVT();
1673 // If we zero all the possible extended bits, then we can turn this into
1674 // a zextload if we are running before legalize or the operation is legal.
1675 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1676 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1677 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1678 LN0->getBasePtr(), LN0->getSrcValue(),
1679 LN0->getSrcValueOffset(), EVT,
1681 LN0->getAlignment());
1683 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1684 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1688 // fold (and (load x), 255) -> (zextload x, i8)
1689 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1690 if (N1C && N0.getOpcode() == ISD::LOAD) {
1691 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1692 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1693 LN0->getAddressingMode() == ISD::UNINDEXED &&
1695 MVT::ValueType EVT, LoadedVT;
1696 if (N1C->getValue() == 255)
1698 else if (N1C->getValue() == 65535)
1700 else if (N1C->getValue() == ~0U)
1705 LoadedVT = LN0->getLoadedVT();
1706 if (EVT != MVT::Other && LoadedVT > EVT &&
1707 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1708 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1709 // For big endian targets, we need to add an offset to the pointer to
1710 // load the correct bytes. For little endian systems, we merely need to
1711 // read fewer bytes from the same pointer.
1713 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1714 SDOperand NewPtr = LN0->getBasePtr();
1715 if (!TLI.isLittleEndian())
1716 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1717 DAG.getConstant(PtrOff, PtrType));
1718 AddToWorkList(NewPtr.Val);
1720 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1721 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
1722 LN0->isVolatile(), LN0->getAlignment());
1724 CombineTo(N0.Val, Load, Load.getValue(1));
1725 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1733 SDOperand DAGCombiner::visitOR(SDNode *N) {
1734 SDOperand N0 = N->getOperand(0);
1735 SDOperand N1 = N->getOperand(1);
1736 SDOperand LL, LR, RL, RR, CC0, CC1;
1737 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1738 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1739 MVT::ValueType VT = N1.getValueType();
1740 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1743 if (MVT::isVector(VT)) {
1744 SDOperand FoldedVOp = SimplifyVBinOp(N);
1745 if (FoldedVOp.Val) return FoldedVOp;
1748 // fold (or x, undef) -> -1
1749 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1750 return DAG.getConstant(~0ULL, VT);
1751 // fold (or c1, c2) -> c1|c2
1753 return DAG.getNode(ISD::OR, VT, N0, N1);
1754 // canonicalize constant to RHS
1756 return DAG.getNode(ISD::OR, VT, N1, N0);
1757 // fold (or x, 0) -> x
1758 if (N1C && N1C->isNullValue())
1760 // fold (or x, -1) -> -1
1761 if (N1C && N1C->isAllOnesValue())
1763 // fold (or x, c) -> c iff (x & ~c) == 0
1765 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1768 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1771 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1772 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1773 isa<ConstantSDNode>(N0.getOperand(1))) {
1774 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1775 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1777 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1779 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1780 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1781 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1782 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1784 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1785 MVT::isInteger(LL.getValueType())) {
1786 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1787 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1788 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1789 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1790 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1791 AddToWorkList(ORNode.Val);
1792 return DAG.getSetCC(VT, ORNode, LR, Op1);
1794 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1795 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1796 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1797 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1798 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1799 AddToWorkList(ANDNode.Val);
1800 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1803 // canonicalize equivalent to ll == rl
1804 if (LL == RR && LR == RL) {
1805 Op1 = ISD::getSetCCSwappedOperands(Op1);
1808 if (LL == RL && LR == RR) {
1809 bool isInteger = MVT::isInteger(LL.getValueType());
1810 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1811 if (Result != ISD::SETCC_INVALID)
1812 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1816 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1817 if (N0.getOpcode() == N1.getOpcode()) {
1818 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1819 if (Tmp.Val) return Tmp;
1822 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1823 if (N0.getOpcode() == ISD::AND &&
1824 N1.getOpcode() == ISD::AND &&
1825 N0.getOperand(1).getOpcode() == ISD::Constant &&
1826 N1.getOperand(1).getOpcode() == ISD::Constant &&
1827 // Don't increase # computations.
1828 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1829 // We can only do this xform if we know that bits from X that are set in C2
1830 // but not in C1 are already zero. Likewise for Y.
1831 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1832 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1834 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1835 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1836 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1837 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1842 // See if this is some rotate idiom.
1843 if (SDNode *Rot = MatchRotate(N0, N1))
1844 return SDOperand(Rot, 0);
1850 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1851 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1852 if (Op.getOpcode() == ISD::AND) {
1853 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1854 Mask = Op.getOperand(1);
1855 Op = Op.getOperand(0);
1861 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1869 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1870 // idioms for rotate, and if the target supports rotation instructions, generate
1872 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1873 // Must be a legal type. Expanded an promoted things won't work with rotates.
1874 MVT::ValueType VT = LHS.getValueType();
1875 if (!TLI.isTypeLegal(VT)) return 0;
1877 // The target must have at least one rotate flavor.
1878 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1879 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1880 if (!HasROTL && !HasROTR) return 0;
1882 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1883 SDOperand LHSShift; // The shift.
1884 SDOperand LHSMask; // AND value if any.
1885 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1886 return 0; // Not part of a rotate.
1888 SDOperand RHSShift; // The shift.
1889 SDOperand RHSMask; // AND value if any.
1890 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1891 return 0; // Not part of a rotate.
1893 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1894 return 0; // Not shifting the same value.
1896 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1897 return 0; // Shifts must disagree.
1899 // Canonicalize shl to left side in a shl/srl pair.
1900 if (RHSShift.getOpcode() == ISD::SHL) {
1901 std::swap(LHS, RHS);
1902 std::swap(LHSShift, RHSShift);
1903 std::swap(LHSMask , RHSMask );
1906 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1907 SDOperand LHSShiftArg = LHSShift.getOperand(0);
1908 SDOperand LHSShiftAmt = LHSShift.getOperand(1);
1909 SDOperand RHSShiftAmt = RHSShift.getOperand(1);
1911 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1912 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1913 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
1914 RHSShiftAmt.getOpcode() == ISD::Constant) {
1915 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
1916 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
1917 if ((LShVal + RShVal) != OpSizeInBits)
1922 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
1924 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
1926 // If there is an AND of either shifted operand, apply it to the result.
1927 if (LHSMask.Val || RHSMask.Val) {
1928 uint64_t Mask = MVT::getIntVTBitMask(VT);
1931 uint64_t RHSBits = (1ULL << LShVal)-1;
1932 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1935 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1936 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1939 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1945 // If there is a mask here, and we have a variable shift, we can't be sure
1946 // that we're masking out the right stuff.
1947 if (LHSMask.Val || RHSMask.Val)
1950 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1951 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1952 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
1953 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
1954 if (ConstantSDNode *SUBC =
1955 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
1956 if (SUBC->getValue() == OpSizeInBits)
1958 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1960 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1964 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1965 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1966 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
1967 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
1968 if (ConstantSDNode *SUBC =
1969 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
1970 if (SUBC->getValue() == OpSizeInBits)
1972 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1974 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1978 // Look for sign/zext/any-extended cases:
1979 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1980 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1981 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
1982 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1983 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1984 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
1985 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
1986 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
1987 if (RExtOp0.getOpcode() == ISD::SUB &&
1988 RExtOp0.getOperand(1) == LExtOp0) {
1989 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1991 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1992 // (rotl x, (sub 32, y))
1993 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
1994 if (SUBC->getValue() == OpSizeInBits) {
1996 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1998 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
2001 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2002 RExtOp0 == LExtOp0.getOperand(1)) {
2003 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2005 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2006 // (rotr x, (sub 32, y))
2007 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2008 if (SUBC->getValue() == OpSizeInBits) {
2010 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
2012 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2022 SDOperand DAGCombiner::visitXOR(SDNode *N) {
2023 SDOperand N0 = N->getOperand(0);
2024 SDOperand N1 = N->getOperand(1);
2025 SDOperand LHS, RHS, CC;
2026 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2027 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2028 MVT::ValueType VT = N0.getValueType();
2031 if (MVT::isVector(VT)) {
2032 SDOperand FoldedVOp = SimplifyVBinOp(N);
2033 if (FoldedVOp.Val) return FoldedVOp;
2036 // fold (xor x, undef) -> undef
2037 if (N0.getOpcode() == ISD::UNDEF)
2039 if (N1.getOpcode() == ISD::UNDEF)
2041 // fold (xor c1, c2) -> c1^c2
2043 return DAG.getNode(ISD::XOR, VT, N0, N1);
2044 // canonicalize constant to RHS
2046 return DAG.getNode(ISD::XOR, VT, N1, N0);
2047 // fold (xor x, 0) -> x
2048 if (N1C && N1C->isNullValue())
2051 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
2054 // fold !(x cc y) -> (x !cc y)
2055 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2056 bool isInt = MVT::isInteger(LHS.getValueType());
2057 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2059 if (N0.getOpcode() == ISD::SETCC)
2060 return DAG.getSetCC(VT, LHS, RHS, NotCC);
2061 if (N0.getOpcode() == ISD::SELECT_CC)
2062 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
2063 assert(0 && "Unhandled SetCC Equivalent!");
2066 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2067 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2068 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2069 SDOperand V = N0.getOperand(0);
2070 V = DAG.getNode(ISD::XOR, V.getValueType(), V,
2071 DAG.getConstant(V.getValueType(), 1));
2072 AddToWorkList(V.Val);
2073 return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
2076 // fold !(x or y) -> (!x and !y) iff x or y are setcc
2077 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
2078 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2079 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2080 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2081 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2082 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2083 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2084 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2085 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2088 // fold !(x or y) -> (!x and !y) iff x or y are constants
2089 if (N1C && N1C->isAllOnesValue() &&
2090 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2091 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2092 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2093 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2094 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2095 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2096 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2097 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2100 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
2101 if (N1C && N0.getOpcode() == ISD::XOR) {
2102 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2103 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2105 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
2106 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
2108 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
2109 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
2111 // fold (xor x, x) -> 0
2113 if (!MVT::isVector(VT)) {
2114 return DAG.getConstant(0, VT);
2115 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
2116 // Produce a vector of zeros.
2117 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
2118 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
2119 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2123 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2124 if (N0.getOpcode() == N1.getOpcode()) {
2125 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2126 if (Tmp.Val) return Tmp;
2129 // Simplify the expression using non-local knowledge.
2130 if (!MVT::isVector(VT) &&
2131 SimplifyDemandedBits(SDOperand(N, 0)))
2132 return SDOperand(N, 0);
2137 SDOperand DAGCombiner::visitSHL(SDNode *N) {
2138 SDOperand N0 = N->getOperand(0);
2139 SDOperand N1 = N->getOperand(1);
2140 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2141 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2142 MVT::ValueType VT = N0.getValueType();
2143 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2145 // fold (shl c1, c2) -> c1<<c2
2147 return DAG.getNode(ISD::SHL, VT, N0, N1);
2148 // fold (shl 0, x) -> 0
2149 if (N0C && N0C->isNullValue())
2151 // fold (shl x, c >= size(x)) -> undef
2152 if (N1C && N1C->getValue() >= OpSizeInBits)
2153 return DAG.getNode(ISD::UNDEF, VT);
2154 // fold (shl x, 0) -> x
2155 if (N1C && N1C->isNullValue())
2157 // if (shl x, c) is known to be zero, return 0
2158 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
2159 return DAG.getConstant(0, VT);
2160 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2161 return SDOperand(N, 0);
2162 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
2163 if (N1C && N0.getOpcode() == ISD::SHL &&
2164 N0.getOperand(1).getOpcode() == ISD::Constant) {
2165 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2166 uint64_t c2 = N1C->getValue();
2167 if (c1 + c2 > OpSizeInBits)
2168 return DAG.getConstant(0, VT);
2169 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
2170 DAG.getConstant(c1 + c2, N1.getValueType()));
2172 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
2173 // (srl (and x, -1 << c1), c1-c2)
2174 if (N1C && N0.getOpcode() == ISD::SRL &&
2175 N0.getOperand(1).getOpcode() == ISD::Constant) {
2176 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2177 uint64_t c2 = N1C->getValue();
2178 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2179 DAG.getConstant(~0ULL << c1, VT));
2181 return DAG.getNode(ISD::SHL, VT, Mask,
2182 DAG.getConstant(c2-c1, N1.getValueType()));
2184 return DAG.getNode(ISD::SRL, VT, Mask,
2185 DAG.getConstant(c1-c2, N1.getValueType()));
2187 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
2188 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2189 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2190 DAG.getConstant(~0ULL << N1C->getValue(), VT));
2194 SDOperand DAGCombiner::visitSRA(SDNode *N) {
2195 SDOperand N0 = N->getOperand(0);
2196 SDOperand N1 = N->getOperand(1);
2197 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2198 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2199 MVT::ValueType VT = N0.getValueType();
2201 // fold (sra c1, c2) -> c1>>c2
2203 return DAG.getNode(ISD::SRA, VT, N0, N1);
2204 // fold (sra 0, x) -> 0
2205 if (N0C && N0C->isNullValue())
2207 // fold (sra -1, x) -> -1
2208 if (N0C && N0C->isAllOnesValue())
2210 // fold (sra x, c >= size(x)) -> undef
2211 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
2212 return DAG.getNode(ISD::UNDEF, VT);
2213 // fold (sra x, 0) -> x
2214 if (N1C && N1C->isNullValue())
2216 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2218 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2219 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
2222 default: EVT = MVT::Other; break;
2223 case 1: EVT = MVT::i1; break;
2224 case 8: EVT = MVT::i8; break;
2225 case 16: EVT = MVT::i16; break;
2226 case 32: EVT = MVT::i32; break;
2228 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
2229 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
2230 DAG.getValueType(EVT));
2233 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
2234 if (N1C && N0.getOpcode() == ISD::SRA) {
2235 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2236 unsigned Sum = N1C->getValue() + C1->getValue();
2237 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
2238 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
2239 DAG.getConstant(Sum, N1C->getValueType(0)));
2243 // Simplify, based on bits shifted out of the LHS.
2244 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2245 return SDOperand(N, 0);
2248 // If the sign bit is known to be zero, switch this to a SRL.
2249 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
2250 return DAG.getNode(ISD::SRL, VT, N0, N1);
2254 SDOperand DAGCombiner::visitSRL(SDNode *N) {
2255 SDOperand N0 = N->getOperand(0);
2256 SDOperand N1 = N->getOperand(1);
2257 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2258 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2259 MVT::ValueType VT = N0.getValueType();
2260 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2262 // fold (srl c1, c2) -> c1 >>u c2
2264 return DAG.getNode(ISD::SRL, VT, N0, N1);
2265 // fold (srl 0, x) -> 0
2266 if (N0C && N0C->isNullValue())
2268 // fold (srl x, c >= size(x)) -> undef
2269 if (N1C && N1C->getValue() >= OpSizeInBits)
2270 return DAG.getNode(ISD::UNDEF, VT);
2271 // fold (srl x, 0) -> x
2272 if (N1C && N1C->isNullValue())
2274 // if (srl x, c) is known to be zero, return 0
2275 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
2276 return DAG.getConstant(0, VT);
2278 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
2279 if (N1C && N0.getOpcode() == ISD::SRL &&
2280 N0.getOperand(1).getOpcode() == ISD::Constant) {
2281 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2282 uint64_t c2 = N1C->getValue();
2283 if (c1 + c2 > OpSizeInBits)
2284 return DAG.getConstant(0, VT);
2285 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
2286 DAG.getConstant(c1 + c2, N1.getValueType()));
2289 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2290 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2291 // Shifting in all undef bits?
2292 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
2293 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
2294 return DAG.getNode(ISD::UNDEF, VT);
2296 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
2297 AddToWorkList(SmallShift.Val);
2298 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
2301 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2302 // bit, which is unmodified by sra.
2303 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
2304 if (N0.getOpcode() == ISD::SRA)
2305 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
2308 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2309 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2310 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
2311 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
2312 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2314 // If any of the input bits are KnownOne, then the input couldn't be all
2315 // zeros, thus the result of the srl will always be zero.
2316 if (KnownOne) return DAG.getConstant(0, VT);
2318 // If all of the bits input the to ctlz node are known to be zero, then
2319 // the result of the ctlz is "32" and the result of the shift is one.
2320 uint64_t UnknownBits = ~KnownZero & Mask;
2321 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2323 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2324 if ((UnknownBits & (UnknownBits-1)) == 0) {
2325 // Okay, we know that only that the single bit specified by UnknownBits
2326 // could be set on input to the CTLZ node. If this bit is set, the SRL
2327 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2328 // to an SRL,XOR pair, which is likely to simplify more.
2329 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
2330 SDOperand Op = N0.getOperand(0);
2332 Op = DAG.getNode(ISD::SRL, VT, Op,
2333 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
2334 AddToWorkList(Op.Val);
2336 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
2340 // fold operands of srl based on knowledge that the low bits are not
2342 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2343 return SDOperand(N, 0);
2348 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
2349 SDOperand N0 = N->getOperand(0);
2350 MVT::ValueType VT = N->getValueType(0);
2352 // fold (ctlz c1) -> c2
2353 if (isa<ConstantSDNode>(N0))
2354 return DAG.getNode(ISD::CTLZ, VT, N0);
2358 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
2359 SDOperand N0 = N->getOperand(0);
2360 MVT::ValueType VT = N->getValueType(0);
2362 // fold (cttz c1) -> c2
2363 if (isa<ConstantSDNode>(N0))
2364 return DAG.getNode(ISD::CTTZ, VT, N0);
2368 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
2369 SDOperand N0 = N->getOperand(0);
2370 MVT::ValueType VT = N->getValueType(0);
2372 // fold (ctpop c1) -> c2
2373 if (isa<ConstantSDNode>(N0))
2374 return DAG.getNode(ISD::CTPOP, VT, N0);
2378 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
2379 SDOperand N0 = N->getOperand(0);
2380 SDOperand N1 = N->getOperand(1);
2381 SDOperand N2 = N->getOperand(2);
2382 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2383 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2384 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2385 MVT::ValueType VT = N->getValueType(0);
2386 MVT::ValueType VT0 = N0.getValueType();
2388 // fold select C, X, X -> X
2391 // fold select true, X, Y -> X
2392 if (N0C && !N0C->isNullValue())
2394 // fold select false, X, Y -> Y
2395 if (N0C && N0C->isNullValue())
2397 // fold select C, 1, X -> C | X
2398 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
2399 return DAG.getNode(ISD::OR, VT, N0, N2);
2400 // fold select C, 0, 1 -> ~C
2401 if (MVT::isInteger(VT) && MVT::isInteger(VT0) &&
2402 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) {
2403 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
2406 AddToWorkList(XORNode.Val);
2407 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0))
2408 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
2409 return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
2411 // fold select C, 0, X -> ~C & X
2412 if (VT == VT0 && N1C && N1C->isNullValue()) {
2413 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2414 AddToWorkList(XORNode.Val);
2415 return DAG.getNode(ISD::AND, VT, XORNode, N2);
2417 // fold select C, X, 1 -> ~C | X
2418 if (VT == VT0 && N2C && N2C->getValue() == 1) {
2419 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2420 AddToWorkList(XORNode.Val);
2421 return DAG.getNode(ISD::OR, VT, XORNode, N1);
2423 // fold select C, X, 0 -> C & X
2424 // FIXME: this should check for C type == X type, not i1?
2425 if (MVT::i1 == VT && N2C && N2C->isNullValue())
2426 return DAG.getNode(ISD::AND, VT, N0, N1);
2427 // fold X ? X : Y --> X ? 1 : Y --> X | Y
2428 if (MVT::i1 == VT && N0 == N1)
2429 return DAG.getNode(ISD::OR, VT, N0, N2);
2430 // fold X ? Y : X --> X ? Y : 0 --> X & Y
2431 if (MVT::i1 == VT && N0 == N2)
2432 return DAG.getNode(ISD::AND, VT, N0, N1);
2434 // If we can fold this based on the true/false value, do so.
2435 if (SimplifySelectOps(N, N1, N2))
2436 return SDOperand(N, 0); // Don't revisit N.
2438 // fold selects based on a setcc into other things, such as min/max/abs
2439 if (N0.getOpcode() == ISD::SETCC)
2441 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2442 // having to say they don't support SELECT_CC on every type the DAG knows
2443 // about, since there is no way to mark an opcode illegal at all value types
2444 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
2445 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
2446 N1, N2, N0.getOperand(2));
2448 return SimplifySelect(N0, N1, N2);
2452 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
2453 SDOperand N0 = N->getOperand(0);
2454 SDOperand N1 = N->getOperand(1);
2455 SDOperand N2 = N->getOperand(2);
2456 SDOperand N3 = N->getOperand(3);
2457 SDOperand N4 = N->getOperand(4);
2458 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2460 // fold select_cc lhs, rhs, x, x, cc -> x
2464 // Determine if the condition we're dealing with is constant
2465 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2466 if (SCC.Val) AddToWorkList(SCC.Val);
2468 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
2469 if (SCCC->getValue())
2470 return N2; // cond always true -> true val
2472 return N3; // cond always false -> false val
2475 // Fold to a simpler select_cc
2476 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2477 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
2478 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2481 // If we can fold this based on the true/false value, do so.
2482 if (SimplifySelectOps(N, N2, N3))
2483 return SDOperand(N, 0); // Don't revisit N.
2485 // fold select_cc into other things, such as min/max/abs
2486 return SimplifySelectCC(N0, N1, N2, N3, CC);
2489 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
2490 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2491 cast<CondCodeSDNode>(N->getOperand(2))->get());
2494 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2495 SDOperand N0 = N->getOperand(0);
2496 MVT::ValueType VT = N->getValueType(0);
2498 // fold (sext c1) -> c1
2499 if (isa<ConstantSDNode>(N0))
2500 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2502 // fold (sext (sext x)) -> (sext x)
2503 // fold (sext (aext x)) -> (sext x)
2504 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2505 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2507 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2508 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2509 if (N0.getOpcode() == ISD::TRUNCATE) {
2510 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2511 if (NarrowLoad.Val) {
2512 if (NarrowLoad.Val != N0.Val)
2513 CombineTo(N0.Val, NarrowLoad);
2514 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
2518 // See if the value being truncated is already sign extended. If so, just
2519 // eliminate the trunc/sext pair.
2520 if (N0.getOpcode() == ISD::TRUNCATE) {
2521 SDOperand Op = N0.getOperand(0);
2522 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2523 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2524 unsigned DestBits = MVT::getSizeInBits(VT);
2525 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2527 if (OpBits == DestBits) {
2528 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2529 // bits, it is already ready.
2530 if (NumSignBits > DestBits-MidBits)
2532 } else if (OpBits < DestBits) {
2533 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2534 // bits, just sext from i32.
2535 if (NumSignBits > OpBits-MidBits)
2536 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2538 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2539 // bits, just truncate to i32.
2540 if (NumSignBits > OpBits-MidBits)
2541 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2544 // fold (sext (truncate x)) -> (sextinreg x).
2545 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2546 N0.getValueType())) {
2547 if (Op.getValueType() < VT)
2548 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2549 else if (Op.getValueType() > VT)
2550 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2551 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2552 DAG.getValueType(N0.getValueType()));
2556 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2557 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2558 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2559 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2560 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2561 LN0->getBasePtr(), LN0->getSrcValue(),
2562 LN0->getSrcValueOffset(),
2565 LN0->getAlignment());
2566 CombineTo(N, ExtLoad);
2567 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2568 ExtLoad.getValue(1));
2569 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2572 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2573 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2574 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2575 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2576 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2577 MVT::ValueType EVT = LN0->getLoadedVT();
2578 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2579 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2580 LN0->getBasePtr(), LN0->getSrcValue(),
2581 LN0->getSrcValueOffset(), EVT,
2583 LN0->getAlignment());
2584 CombineTo(N, ExtLoad);
2585 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2586 ExtLoad.getValue(1));
2587 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2591 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
2592 if (N0.getOpcode() == ISD::SETCC) {
2594 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2595 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
2596 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2597 if (SCC.Val) return SCC;
2603 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2604 SDOperand N0 = N->getOperand(0);
2605 MVT::ValueType VT = N->getValueType(0);
2607 // fold (zext c1) -> c1
2608 if (isa<ConstantSDNode>(N0))
2609 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2610 // fold (zext (zext x)) -> (zext x)
2611 // fold (zext (aext x)) -> (zext x)
2612 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2613 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2615 // fold (zext (truncate (load x))) -> (zext (smaller load x))
2616 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
2617 if (N0.getOpcode() == ISD::TRUNCATE) {
2618 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2619 if (NarrowLoad.Val) {
2620 if (NarrowLoad.Val != N0.Val)
2621 CombineTo(N0.Val, NarrowLoad);
2622 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
2626 // fold (zext (truncate x)) -> (and x, mask)
2627 if (N0.getOpcode() == ISD::TRUNCATE &&
2628 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2629 SDOperand Op = N0.getOperand(0);
2630 if (Op.getValueType() < VT) {
2631 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2632 } else if (Op.getValueType() > VT) {
2633 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2635 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2638 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2639 if (N0.getOpcode() == ISD::AND &&
2640 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2641 N0.getOperand(1).getOpcode() == ISD::Constant) {
2642 SDOperand X = N0.getOperand(0).getOperand(0);
2643 if (X.getValueType() < VT) {
2644 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2645 } else if (X.getValueType() > VT) {
2646 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2648 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2649 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2652 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2653 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2654 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2655 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2656 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2657 LN0->getBasePtr(), LN0->getSrcValue(),
2658 LN0->getSrcValueOffset(),
2661 LN0->getAlignment());
2662 CombineTo(N, ExtLoad);
2663 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2664 ExtLoad.getValue(1));
2665 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2668 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2669 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2670 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2671 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2672 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2673 MVT::ValueType EVT = LN0->getLoadedVT();
2674 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2675 LN0->getBasePtr(), LN0->getSrcValue(),
2676 LN0->getSrcValueOffset(), EVT,
2678 LN0->getAlignment());
2679 CombineTo(N, ExtLoad);
2680 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2681 ExtLoad.getValue(1));
2682 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2685 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2686 if (N0.getOpcode() == ISD::SETCC) {
2688 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2689 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2690 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2691 if (SCC.Val) return SCC;
2697 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2698 SDOperand N0 = N->getOperand(0);
2699 MVT::ValueType VT = N->getValueType(0);
2701 // fold (aext c1) -> c1
2702 if (isa<ConstantSDNode>(N0))
2703 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2704 // fold (aext (aext x)) -> (aext x)
2705 // fold (aext (zext x)) -> (zext x)
2706 // fold (aext (sext x)) -> (sext x)
2707 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2708 N0.getOpcode() == ISD::ZERO_EXTEND ||
2709 N0.getOpcode() == ISD::SIGN_EXTEND)
2710 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2712 // fold (aext (truncate (load x))) -> (aext (smaller load x))
2713 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
2714 if (N0.getOpcode() == ISD::TRUNCATE) {
2715 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2716 if (NarrowLoad.Val) {
2717 if (NarrowLoad.Val != N0.Val)
2718 CombineTo(N0.Val, NarrowLoad);
2719 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
2723 // fold (aext (truncate x))
2724 if (N0.getOpcode() == ISD::TRUNCATE) {
2725 SDOperand TruncOp = N0.getOperand(0);
2726 if (TruncOp.getValueType() == VT)
2727 return TruncOp; // x iff x size == zext size.
2728 if (TruncOp.getValueType() > VT)
2729 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2730 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2733 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2734 if (N0.getOpcode() == ISD::AND &&
2735 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2736 N0.getOperand(1).getOpcode() == ISD::Constant) {
2737 SDOperand X = N0.getOperand(0).getOperand(0);
2738 if (X.getValueType() < VT) {
2739 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2740 } else if (X.getValueType() > VT) {
2741 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2743 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2744 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2747 // fold (aext (load x)) -> (aext (truncate (extload x)))
2748 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2749 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2750 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2751 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2752 LN0->getBasePtr(), LN0->getSrcValue(),
2753 LN0->getSrcValueOffset(),
2756 LN0->getAlignment());
2757 CombineTo(N, ExtLoad);
2758 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2759 ExtLoad.getValue(1));
2760 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2763 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2764 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2765 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2766 if (N0.getOpcode() == ISD::LOAD &&
2767 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2769 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2770 MVT::ValueType EVT = LN0->getLoadedVT();
2771 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2772 LN0->getChain(), LN0->getBasePtr(),
2774 LN0->getSrcValueOffset(), EVT,
2776 LN0->getAlignment());
2777 CombineTo(N, ExtLoad);
2778 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2779 ExtLoad.getValue(1));
2780 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2783 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2784 if (N0.getOpcode() == ISD::SETCC) {
2786 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2787 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2788 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2796 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
2797 /// bits and then truncated to a narrower type and where N is a multiple
2798 /// of number of bits of the narrower type, transform it to a narrower load
2799 /// from address + N / num of bits of new type. If the result is to be
2800 /// extended, also fold the extension to form a extending load.
2801 SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
2802 unsigned Opc = N->getOpcode();
2803 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2804 SDOperand N0 = N->getOperand(0);
2805 MVT::ValueType VT = N->getValueType(0);
2806 MVT::ValueType EVT = N->getValueType(0);
2808 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
2810 if (Opc == ISD::SIGN_EXTEND_INREG) {
2811 ExtType = ISD::SEXTLOAD;
2812 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2813 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
2817 unsigned EVTBits = MVT::getSizeInBits(EVT);
2819 bool CombineSRL = false;
2820 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
2821 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2822 ShAmt = N01->getValue();
2823 // Is the shift amount a multiple of size of VT?
2824 if ((ShAmt & (EVTBits-1)) == 0) {
2825 N0 = N0.getOperand(0);
2826 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
2833 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2834 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
2835 // zero extended form: by shrinking the load, we lose track of the fact
2836 // that it is already zero extended.
2837 // FIXME: This should be reevaluated.
2839 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
2840 "Cannot truncate to larger type!");
2841 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2842 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2843 // For big endian targets, we need to adjust the offset to the pointer to
2844 // load the correct bytes.
2845 if (!TLI.isLittleEndian())
2846 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits;
2847 uint64_t PtrOff = ShAmt / 8;
2848 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2849 DAG.getConstant(PtrOff, PtrType));
2850 AddToWorkList(NewPtr.Val);
2851 SDOperand Load = (ExtType == ISD::NON_EXTLOAD)
2852 ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
2853 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2854 LN0->isVolatile(), LN0->getAlignment())
2855 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
2856 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
2857 LN0->isVolatile(), LN0->getAlignment());
2860 std::vector<SDNode*> NowDead;
2861 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead);
2862 CombineTo(N->getOperand(0).Val, Load);
2864 CombineTo(N0.Val, Load, Load.getValue(1));
2866 if (Opc == ISD::SIGN_EXTEND_INREG)
2867 return DAG.getNode(Opc, VT, Load, N->getOperand(1));
2869 return DAG.getNode(Opc, VT, Load);
2871 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2878 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2879 SDOperand N0 = N->getOperand(0);
2880 SDOperand N1 = N->getOperand(1);
2881 MVT::ValueType VT = N->getValueType(0);
2882 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2883 unsigned EVTBits = MVT::getSizeInBits(EVT);
2885 // fold (sext_in_reg c1) -> c1
2886 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2887 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2889 // If the input is already sign extended, just drop the extension.
2890 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2893 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2894 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2895 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2896 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2899 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
2900 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2901 return DAG.getZeroExtendInReg(N0, EVT);
2903 // fold operands of sext_in_reg based on knowledge that the top bits are not
2905 if (SimplifyDemandedBits(SDOperand(N, 0)))
2906 return SDOperand(N, 0);
2908 // fold (sext_in_reg (load x)) -> (smaller sextload x)
2909 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
2910 SDOperand NarrowLoad = ReduceLoadWidth(N);
2914 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2915 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2916 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2917 if (N0.getOpcode() == ISD::SRL) {
2918 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2919 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2920 // We can turn this into an SRA iff the input to the SRL is already sign
2922 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
2923 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2924 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2928 // fold (sext_inreg (extload x)) -> (sextload x)
2929 if (ISD::isEXTLoad(N0.Val) &&
2930 ISD::isUNINDEXEDLoad(N0.Val) &&
2931 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2932 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2933 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2934 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2935 LN0->getBasePtr(), LN0->getSrcValue(),
2936 LN0->getSrcValueOffset(), EVT,
2938 LN0->getAlignment());
2939 CombineTo(N, ExtLoad);
2940 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2941 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2943 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2944 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2946 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2947 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2948 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2949 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2950 LN0->getBasePtr(), LN0->getSrcValue(),
2951 LN0->getSrcValueOffset(), EVT,
2953 LN0->getAlignment());
2954 CombineTo(N, ExtLoad);
2955 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2956 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2961 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2962 SDOperand N0 = N->getOperand(0);
2963 MVT::ValueType VT = N->getValueType(0);
2966 if (N0.getValueType() == N->getValueType(0))
2968 // fold (truncate c1) -> c1
2969 if (isa<ConstantSDNode>(N0))
2970 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2971 // fold (truncate (truncate x)) -> (truncate x)
2972 if (N0.getOpcode() == ISD::TRUNCATE)
2973 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2974 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2975 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2976 N0.getOpcode() == ISD::ANY_EXTEND) {
2977 if (N0.getOperand(0).getValueType() < VT)
2978 // if the source is smaller than the dest, we still need an extend
2979 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2980 else if (N0.getOperand(0).getValueType() > VT)
2981 // if the source is larger than the dest, than we just need the truncate
2982 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2984 // if the source and dest are the same type, we can drop both the extend
2986 return N0.getOperand(0);
2989 // fold (truncate (load x)) -> (smaller load x)
2990 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
2991 return ReduceLoadWidth(N);
2994 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2995 SDOperand N0 = N->getOperand(0);
2996 MVT::ValueType VT = N->getValueType(0);
2998 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
2999 // Only do this before legalize, since afterward the target may be depending
3000 // on the bitconvert.
3001 // First check to see if this is all constant.
3002 if (!AfterLegalize &&
3003 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
3004 MVT::isVector(VT)) {
3005 bool isSimple = true;
3006 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3007 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3008 N0.getOperand(i).getOpcode() != ISD::Constant &&
3009 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3014 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0));
3015 assert(!MVT::isVector(DestEltVT) &&
3016 "Element type of vector ValueType must not be vector!");
3018 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
3022 // If the input is a constant, let getNode() fold it.
3023 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3024 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3025 if (Res.Val != N) return Res;
3028 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
3029 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3031 // fold (conv (load x)) -> (load (conv*)x)
3032 // If the resultant load doesn't need a higher alignment than the original!
3033 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() &&
3034 TLI.isOperationLegal(ISD::LOAD, VT)) {
3035 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3036 unsigned Align = TLI.getTargetMachine().getTargetData()->
3037 getABITypeAlignment(MVT::getTypeForValueType(VT));
3038 unsigned OrigAlign = LN0->getAlignment();
3039 if (Align <= OrigAlign) {
3040 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
3041 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3042 LN0->isVolatile(), Align);
3044 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
3053 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3054 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3055 /// destination element value type.
3056 SDOperand DAGCombiner::
3057 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
3058 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
3060 // If this is already the right type, we're done.
3061 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
3063 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
3064 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
3066 // If this is a conversion of N elements of one type to N elements of another
3067 // type, convert each element. This handles FP<->INT cases.
3068 if (SrcBitSize == DstBitSize) {
3069 SmallVector<SDOperand, 8> Ops;
3070 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3071 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
3072 AddToWorkList(Ops.back().Val);
3075 MVT::getVectorType(DstEltVT,
3076 MVT::getVectorNumElements(BV->getValueType(0)));
3077 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3080 // Otherwise, we're growing or shrinking the elements. To avoid having to
3081 // handle annoying details of growing/shrinking FP values, we convert them to
3083 if (MVT::isFloatingPoint(SrcEltVT)) {
3084 // Convert the input float vector to a int vector where the elements are the
3086 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3087 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
3088 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
3092 // Now we know the input is an integer vector. If the output is a FP type,
3093 // convert to integer first, then to FP of the right size.
3094 if (MVT::isFloatingPoint(DstEltVT)) {
3095 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3096 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
3097 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val;
3099 // Next, convert to FP elements of the same size.
3100 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3103 // Okay, we know the src/dst types are both integers of differing types.
3104 // Handling growing first.
3105 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
3106 if (SrcBitSize < DstBitSize) {
3107 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3109 SmallVector<SDOperand, 8> Ops;
3110 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3111 i += NumInputsPerOutput) {
3112 bool isLE = TLI.isLittleEndian();
3113 uint64_t NewBits = 0;
3114 bool EltIsUndef = true;
3115 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3116 // Shift the previously computed bits over.
3117 NewBits <<= SrcBitSize;
3118 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3119 if (Op.getOpcode() == ISD::UNDEF) continue;
3122 NewBits |= cast<ConstantSDNode>(Op)->getValue();
3126 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3128 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3131 MVT::ValueType VT = MVT::getVectorType(DstEltVT,
3133 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3136 // Finally, this must be the case where we are shrinking elements: each input
3137 // turns into multiple outputs.
3138 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3139 SmallVector<SDOperand, 8> Ops;
3140 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3141 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3142 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3143 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3146 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
3148 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3149 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
3150 OpVal >>= DstBitSize;
3151 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3154 // For big endian targets, swap the order of the pieces of each element.
3155 if (!TLI.isLittleEndian())
3156 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3158 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size());
3159 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3164 SDOperand DAGCombiner::visitFADD(SDNode *N) {
3165 SDOperand N0 = N->getOperand(0);
3166 SDOperand N1 = N->getOperand(1);
3167 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3168 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3169 MVT::ValueType VT = N->getValueType(0);
3172 if (MVT::isVector(VT)) {
3173 SDOperand FoldedVOp = SimplifyVBinOp(N);
3174 if (FoldedVOp.Val) return FoldedVOp;
3177 // fold (fadd c1, c2) -> c1+c2
3179 return DAG.getNode(ISD::FADD, VT, N0, N1);
3180 // canonicalize constant to RHS
3181 if (N0CFP && !N1CFP)
3182 return DAG.getNode(ISD::FADD, VT, N1, N0);
3183 // fold (A + (-B)) -> A-B
3184 if (isNegatibleForFree(N1) == 2)
3185 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG));
3186 // fold ((-A) + B) -> B-A
3187 if (isNegatibleForFree(N0) == 2)
3188 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG));
3190 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3191 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3192 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3193 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
3194 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
3199 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
3200 SDOperand N0 = N->getOperand(0);
3201 SDOperand N1 = N->getOperand(1);
3202 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3203 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3204 MVT::ValueType VT = N->getValueType(0);
3207 if (MVT::isVector(VT)) {
3208 SDOperand FoldedVOp = SimplifyVBinOp(N);
3209 if (FoldedVOp.Val) return FoldedVOp;
3212 // fold (fsub c1, c2) -> c1-c2
3214 return DAG.getNode(ISD::FSUB, VT, N0, N1);
3216 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
3217 if (isNegatibleForFree(N1))
3218 return GetNegatedExpression(N1, DAG);
3219 return DAG.getNode(ISD::FNEG, VT, N1);
3221 // fold (A-(-B)) -> A+B
3222 if (isNegatibleForFree(N1))
3223 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG));
3228 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
3229 SDOperand N0 = N->getOperand(0);
3230 SDOperand N1 = N->getOperand(1);
3231 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3232 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3233 MVT::ValueType VT = N->getValueType(0);
3236 if (MVT::isVector(VT)) {
3237 SDOperand FoldedVOp = SimplifyVBinOp(N);
3238 if (FoldedVOp.Val) return FoldedVOp;
3241 // fold (fmul c1, c2) -> c1*c2
3243 return DAG.getNode(ISD::FMUL, VT, N0, N1);
3244 // canonicalize constant to RHS
3245 if (N0CFP && !N1CFP)
3246 return DAG.getNode(ISD::FMUL, VT, N1, N0);
3247 // fold (fmul X, 2.0) -> (fadd X, X)
3248 if (N1CFP && N1CFP->isExactlyValue(+2.0))
3249 return DAG.getNode(ISD::FADD, VT, N0, N0);
3250 // fold (fmul X, -1.0) -> (fneg X)
3251 if (N1CFP && N1CFP->isExactlyValue(-1.0))
3252 return DAG.getNode(ISD::FNEG, VT, N0);
3255 if (char LHSNeg = isNegatibleForFree(N0)) {
3256 if (char RHSNeg = isNegatibleForFree(N1)) {
3257 // Both can be negated for free, check to see if at least one is cheaper
3259 if (LHSNeg == 2 || RHSNeg == 2)
3260 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG),
3261 GetNegatedExpression(N1, DAG));
3265 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
3266 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
3267 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3268 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
3269 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
3274 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
3275 SDOperand N0 = N->getOperand(0);
3276 SDOperand N1 = N->getOperand(1);
3277 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3278 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3279 MVT::ValueType VT = N->getValueType(0);
3282 if (MVT::isVector(VT)) {
3283 SDOperand FoldedVOp = SimplifyVBinOp(N);
3284 if (FoldedVOp.Val) return FoldedVOp;
3287 // fold (fdiv c1, c2) -> c1/c2
3289 return DAG.getNode(ISD::FDIV, VT, N0, N1);
3293 if (char LHSNeg = isNegatibleForFree(N0)) {
3294 if (char RHSNeg = isNegatibleForFree(N1)) {
3295 // Both can be negated for free, check to see if at least one is cheaper
3297 if (LHSNeg == 2 || RHSNeg == 2)
3298 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG),
3299 GetNegatedExpression(N1, DAG));
3306 SDOperand DAGCombiner::visitFREM(SDNode *N) {
3307 SDOperand N0 = N->getOperand(0);
3308 SDOperand N1 = N->getOperand(1);
3309 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3310 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3311 MVT::ValueType VT = N->getValueType(0);
3313 // fold (frem c1, c2) -> fmod(c1,c2)
3315 return DAG.getNode(ISD::FREM, VT, N0, N1);
3320 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
3321 SDOperand N0 = N->getOperand(0);
3322 SDOperand N1 = N->getOperand(1);
3323 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3324 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3325 MVT::ValueType VT = N->getValueType(0);
3327 if (N0CFP && N1CFP) // Constant fold
3328 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
3331 const APFloat& V = N1CFP->getValueAPF();
3332 // copysign(x, c1) -> fabs(x) iff ispos(c1)
3333 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
3334 if (!V.isNegative())
3335 return DAG.getNode(ISD::FABS, VT, N0);
3337 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
3340 // copysign(fabs(x), y) -> copysign(x, y)
3341 // copysign(fneg(x), y) -> copysign(x, y)
3342 // copysign(copysign(x,z), y) -> copysign(x, y)
3343 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
3344 N0.getOpcode() == ISD::FCOPYSIGN)
3345 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
3347 // copysign(x, abs(y)) -> abs(x)
3348 if (N1.getOpcode() == ISD::FABS)
3349 return DAG.getNode(ISD::FABS, VT, N0);
3351 // copysign(x, copysign(y,z)) -> copysign(x, z)
3352 if (N1.getOpcode() == ISD::FCOPYSIGN)
3353 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
3355 // copysign(x, fp_extend(y)) -> copysign(x, y)
3356 // copysign(x, fp_round(y)) -> copysign(x, y)
3357 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
3358 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
3365 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
3366 SDOperand N0 = N->getOperand(0);
3367 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3368 MVT::ValueType VT = N->getValueType(0);
3370 // fold (sint_to_fp c1) -> c1fp
3372 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
3376 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
3377 SDOperand N0 = N->getOperand(0);
3378 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3379 MVT::ValueType VT = N->getValueType(0);
3381 // fold (uint_to_fp c1) -> c1fp
3383 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
3387 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
3388 SDOperand N0 = N->getOperand(0);
3389 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3390 MVT::ValueType VT = N->getValueType(0);
3392 // fold (fp_to_sint c1fp) -> c1
3394 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
3398 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
3399 SDOperand N0 = N->getOperand(0);
3400 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3401 MVT::ValueType VT = N->getValueType(0);
3403 // fold (fp_to_uint c1fp) -> c1
3405 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
3409 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
3410 SDOperand N0 = N->getOperand(0);
3411 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3412 MVT::ValueType VT = N->getValueType(0);
3414 // fold (fp_round c1fp) -> c1fp
3416 return DAG.getNode(ISD::FP_ROUND, VT, N0);
3418 // fold (fp_round (fp_extend x)) -> x
3419 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
3420 return N0.getOperand(0);
3422 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
3423 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
3424 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
3425 AddToWorkList(Tmp.Val);
3426 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
3432 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
3433 SDOperand N0 = N->getOperand(0);
3434 MVT::ValueType VT = N->getValueType(0);
3435 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3436 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3438 // fold (fp_round_inreg c1fp) -> c1fp
3440 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT);
3441 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
3446 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
3447 SDOperand N0 = N->getOperand(0);
3448 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3449 MVT::ValueType VT = N->getValueType(0);
3451 // fold (fp_extend c1fp) -> c1fp
3453 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
3455 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
3456 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3457 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
3458 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3459 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
3460 LN0->getBasePtr(), LN0->getSrcValue(),
3461 LN0->getSrcValueOffset(),
3464 LN0->getAlignment());
3465 CombineTo(N, ExtLoad);
3466 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
3467 ExtLoad.getValue(1));
3468 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3475 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
3476 SDOperand N0 = N->getOperand(0);
3478 if (isNegatibleForFree(N0))
3479 return GetNegatedExpression(N0, DAG);
3484 SDOperand DAGCombiner::visitFABS(SDNode *N) {
3485 SDOperand N0 = N->getOperand(0);
3486 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3487 MVT::ValueType VT = N->getValueType(0);
3489 // fold (fabs c1) -> fabs(c1)
3491 return DAG.getNode(ISD::FABS, VT, N0);
3492 // fold (fabs (fabs x)) -> (fabs x)
3493 if (N0.getOpcode() == ISD::FABS)
3494 return N->getOperand(0);
3495 // fold (fabs (fneg x)) -> (fabs x)
3496 // fold (fabs (fcopysign x, y)) -> (fabs x)
3497 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
3498 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
3503 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
3504 SDOperand Chain = N->getOperand(0);
3505 SDOperand N1 = N->getOperand(1);
3506 SDOperand N2 = N->getOperand(2);
3507 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3509 // never taken branch, fold to chain
3510 if (N1C && N1C->isNullValue())
3512 // unconditional branch
3513 if (N1C && N1C->getValue() == 1)
3514 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
3515 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
3517 if (N1.getOpcode() == ISD::SETCC &&
3518 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
3519 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
3520 N1.getOperand(0), N1.getOperand(1), N2);
3525 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
3527 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
3528 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
3529 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
3531 // Use SimplifySetCC to simplify SETCC's.
3532 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
3533 if (Simp.Val) AddToWorkList(Simp.Val);
3535 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
3537 // fold br_cc true, dest -> br dest (unconditional branch)
3538 if (SCCC && SCCC->getValue())
3539 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
3541 // fold br_cc false, dest -> unconditional fall through
3542 if (SCCC && SCCC->isNullValue())
3543 return N->getOperand(0);
3545 // fold to a simpler setcc
3546 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
3547 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
3548 Simp.getOperand(2), Simp.getOperand(0),
3549 Simp.getOperand(1), N->getOperand(4));
3554 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
3555 /// pre-indexed load / store when the base pointer is a add or subtract
3556 /// and it has other uses besides the load / store. After the
3557 /// transformation, the new indexed load / store has effectively folded
3558 /// the add / subtract in and all of its other uses are redirected to the
3559 /// new load / store.
3560 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
3567 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3568 if (LD->getAddressingMode() != ISD::UNINDEXED)
3570 VT = LD->getLoadedVT();
3571 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
3572 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
3574 Ptr = LD->getBasePtr();
3575 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3576 if (ST->getAddressingMode() != ISD::UNINDEXED)
3578 VT = ST->getStoredVT();
3579 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
3580 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
3582 Ptr = ST->getBasePtr();
3587 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
3588 // out. There is no reason to make this a preinc/predec.
3589 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
3590 Ptr.Val->hasOneUse())
3593 // Ask the target to do addressing mode selection.
3596 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3597 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
3599 // Don't create a indexed load / store with zero offset.
3600 if (isa<ConstantSDNode>(Offset) &&
3601 cast<ConstantSDNode>(Offset)->getValue() == 0)
3604 // Try turning it into a pre-indexed load / store except when:
3605 // 1) The new base ptr is a frame index.
3606 // 2) If N is a store and the new base ptr is either the same as or is a
3607 // predecessor of the value being stored.
3608 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
3609 // that would create a cycle.
3610 // 4) All uses are load / store ops that use it as old base ptr.
3612 // Check #1. Preinc'ing a frame index would require copying the stack pointer
3613 // (plus the implicit offset) to a register to preinc anyway.
3614 if (isa<FrameIndexSDNode>(BasePtr))
3619 SDOperand Val = cast<StoreSDNode>(N)->getValue();
3620 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val))
3624 // Now check for #3 and #4.
3625 bool RealUse = false;
3626 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3627 E = Ptr.Val->use_end(); I != E; ++I) {
3631 if (Use->isPredecessor(N))
3634 if (!((Use->getOpcode() == ISD::LOAD &&
3635 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
3636 (Use->getOpcode() == ISD::STORE) &&
3637 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
3645 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
3647 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3650 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
3651 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3653 std::vector<SDNode*> NowDead;
3655 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3657 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3660 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3664 // Nodes can end up on the worklist more than once. Make sure we do
3665 // not process a node that has been replaced.
3666 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3667 removeFromWorkList(NowDead[i]);
3668 // Finally, since the node is now dead, remove it from the graph.
3671 // Replace the uses of Ptr with uses of the updated base value.
3672 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
3674 removeFromWorkList(Ptr.Val);
3675 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3676 removeFromWorkList(NowDead[i]);
3677 DAG.DeleteNode(Ptr.Val);
3682 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
3683 /// add / sub of the base pointer node into a post-indexed load / store.
3684 /// The transformation folded the add / subtract into the new indexed
3685 /// load / store effectively and all of its uses are redirected to the
3686 /// new load / store.
3687 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
3694 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3695 if (LD->getAddressingMode() != ISD::UNINDEXED)
3697 VT = LD->getLoadedVT();
3698 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
3699 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
3701 Ptr = LD->getBasePtr();
3702 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3703 if (ST->getAddressingMode() != ISD::UNINDEXED)
3705 VT = ST->getStoredVT();
3706 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
3707 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
3709 Ptr = ST->getBasePtr();
3714 if (Ptr.Val->hasOneUse())
3717 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3718 E = Ptr.Val->use_end(); I != E; ++I) {
3721 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
3726 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3727 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
3729 std::swap(BasePtr, Offset);
3732 // Don't create a indexed load / store with zero offset.
3733 if (isa<ConstantSDNode>(Offset) &&
3734 cast<ConstantSDNode>(Offset)->getValue() == 0)
3737 // Try turning it into a post-indexed load / store except when
3738 // 1) All uses are load / store ops that use it as base ptr.
3739 // 2) Op must be independent of N, i.e. Op is neither a predecessor
3740 // nor a successor of N. Otherwise, if Op is folded that would
3744 bool TryNext = false;
3745 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
3746 EE = BasePtr.Val->use_end(); II != EE; ++II) {
3751 // If all the uses are load / store addresses, then don't do the
3753 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
3754 bool RealUse = false;
3755 for (SDNode::use_iterator III = Use->use_begin(),
3756 EEE = Use->use_end(); III != EEE; ++III) {
3757 SDNode *UseUse = *III;
3758 if (!((UseUse->getOpcode() == ISD::LOAD &&
3759 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
3760 (UseUse->getOpcode() == ISD::STORE) &&
3761 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
3775 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
3776 SDOperand Result = isLoad
3777 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
3778 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3781 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
3782 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3784 std::vector<SDNode*> NowDead;
3786 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3788 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3791 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3795 // Nodes can end up on the worklist more than once. Make sure we do
3796 // not process a node that has been replaced.
3797 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3798 removeFromWorkList(NowDead[i]);
3799 // Finally, since the node is now dead, remove it from the graph.
3802 // Replace the uses of Use with uses of the updated base value.
3803 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
3804 Result.getValue(isLoad ? 1 : 0),
3806 removeFromWorkList(Op);
3807 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3808 removeFromWorkList(NowDead[i]);
3819 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
3820 LoadSDNode *LD = cast<LoadSDNode>(N);
3821 SDOperand Chain = LD->getChain();
3822 SDOperand Ptr = LD->getBasePtr();
3824 // If load is not volatile and there are no uses of the loaded value (and
3825 // the updated indexed value in case of indexed loads), change uses of the
3826 // chain value into uses of the chain input (i.e. delete the dead load).
3827 if (!LD->isVolatile()) {
3828 if (N->getValueType(1) == MVT::Other) {
3830 if (N->hasNUsesOfValue(0, 0))
3831 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
3834 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
3835 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
3836 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0));
3837 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1));
3838 SDOperand To[] = { Undef0, Undef1, Chain };
3839 return CombineTo(N, To, 3);
3844 // If this load is directly stored, replace the load value with the stored
3846 // TODO: Handle store large -> read small portion.
3847 // TODO: Handle TRUNCSTORE/LOADEXT
3848 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3849 if (ISD::isNON_TRUNCStore(Chain.Val)) {
3850 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
3851 if (PrevST->getBasePtr() == Ptr &&
3852 PrevST->getValue().getValueType() == N->getValueType(0))
3853 return CombineTo(N, Chain.getOperand(1), Chain);
3858 // Walk up chain skipping non-aliasing memory nodes.
3859 SDOperand BetterChain = FindBetterChain(N, Chain);
3861 // If there is a better chain.
3862 if (Chain != BetterChain) {
3865 // Replace the chain to void dependency.
3866 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3867 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
3868 LD->getSrcValue(), LD->getSrcValueOffset(),
3869 LD->isVolatile(), LD->getAlignment());
3871 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
3872 LD->getValueType(0),
3873 BetterChain, Ptr, LD->getSrcValue(),
3874 LD->getSrcValueOffset(),
3877 LD->getAlignment());
3880 // Create token factor to keep old chain connected.
3881 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
3882 Chain, ReplLoad.getValue(1));
3884 // Replace uses with load result and token factor. Don't add users
3886 return CombineTo(N, ReplLoad.getValue(0), Token, false);
3890 // Try transforming N to an indexed load.
3891 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3892 return SDOperand(N, 0);
3897 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
3898 StoreSDNode *ST = cast<StoreSDNode>(N);
3899 SDOperand Chain = ST->getChain();
3900 SDOperand Value = ST->getValue();
3901 SDOperand Ptr = ST->getBasePtr();
3903 // If this is a store of a bit convert, store the input value if the
3904 // resultant store does not need a higher alignment than the original.
3905 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
3906 ST->getAddressingMode() == ISD::UNINDEXED) {
3907 unsigned Align = ST->getAlignment();
3908 MVT::ValueType SVT = Value.getOperand(0).getValueType();
3909 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
3910 getABITypeAlignment(MVT::getTypeForValueType(SVT));
3911 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
3912 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
3913 ST->getSrcValueOffset(), ST->isVolatile(), Align);
3916 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
3917 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
3918 if (Value.getOpcode() != ISD::TargetConstantFP) {
3920 switch (CFP->getValueType(0)) {
3921 default: assert(0 && "Unknown FP type");
3922 case MVT::f80: // We don't do this for these yet.
3927 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
3928 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
3929 convertToAPInt().getZExtValue(), MVT::i32);
3930 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3931 ST->getSrcValueOffset(), ST->isVolatile(),
3932 ST->getAlignment());
3936 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
3937 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
3938 getZExtValue(), MVT::i64);
3939 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3940 ST->getSrcValueOffset(), ST->isVolatile(),
3941 ST->getAlignment());
3942 } else if (TLI.isTypeLegal(MVT::i32)) {
3943 // Many FP stores are not make apparent until after legalize, e.g. for
3944 // argument passing. Since this is so common, custom legalize the
3945 // 64-bit integer store into two 32-bit stores.
3946 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue();
3947 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
3948 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
3949 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
3951 int SVOffset = ST->getSrcValueOffset();
3952 unsigned Alignment = ST->getAlignment();
3953 bool isVolatile = ST->isVolatile();
3955 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
3956 ST->getSrcValueOffset(),
3957 isVolatile, ST->getAlignment());
3958 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3959 DAG.getConstant(4, Ptr.getValueType()));
3963 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
3964 SVOffset, isVolatile, Alignment);
3965 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
3973 // Walk up chain skipping non-aliasing memory nodes.
3974 SDOperand BetterChain = FindBetterChain(N, Chain);
3976 // If there is a better chain.
3977 if (Chain != BetterChain) {
3978 // Replace the chain to avoid dependency.
3979 SDOperand ReplStore;
3980 if (ST->isTruncatingStore()) {
3981 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
3982 ST->getSrcValue(), ST->getSrcValueOffset(), ST->getStoredVT(),
3983 ST->isVolatile(), ST->getAlignment());
3985 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
3986 ST->getSrcValue(), ST->getSrcValueOffset(),
3987 ST->isVolatile(), ST->getAlignment());
3990 // Create token to keep both nodes around.
3992 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
3994 // Don't add users to work list.
3995 return CombineTo(N, Token, false);
3999 // Try transforming N to an indexed store.
4000 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4001 return SDOperand(N, 0);
4006 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
4007 SDOperand InVec = N->getOperand(0);
4008 SDOperand InVal = N->getOperand(1);
4009 SDOperand EltNo = N->getOperand(2);
4011 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
4012 // vector with the inserted element.
4013 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
4014 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4015 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
4016 if (Elt < Ops.size())
4018 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
4019 &Ops[0], Ops.size());
4025 SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
4026 SDOperand InVec = N->getOperand(0);
4027 SDOperand EltNo = N->getOperand(1);
4029 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr)
4030 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
4031 if (isa<ConstantSDNode>(EltNo)) {
4032 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4033 bool NewLoad = false;
4035 MVT::ValueType VT = InVec.getValueType();
4036 MVT::ValueType EVT = MVT::getVectorElementType(VT);
4037 MVT::ValueType LVT = EVT;
4038 unsigned NumElts = MVT::getVectorNumElements(VT);
4039 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
4040 MVT::ValueType BCVT = InVec.getOperand(0).getValueType();
4041 if (NumElts != MVT::getVectorNumElements(BCVT))
4043 InVec = InVec.getOperand(0);
4044 EVT = MVT::getVectorElementType(BCVT);
4047 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4048 InVec.getOperand(0).getValueType() == EVT &&
4049 ISD::isNormalLoad(InVec.getOperand(0).Val) &&
4050 InVec.getOperand(0).hasOneUse()) {
4051 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0));
4052 unsigned Align = LN0->getAlignment();
4054 // Check the resultant load doesn't need a higher alignment than the
4056 unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
4057 getABITypeAlignment(MVT::getTypeForValueType(LVT));
4058 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align)
4063 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(),
4064 LN0->getSrcValue(), LN0->getSrcValueOffset(),
4065 LN0->isVolatile(), Align);
4073 SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
4074 unsigned NumInScalars = N->getNumOperands();
4075 MVT::ValueType VT = N->getValueType(0);
4076 unsigned NumElts = MVT::getVectorNumElements(VT);
4077 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4079 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
4080 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
4081 // at most two distinct vectors, turn this into a shuffle node.
4082 SDOperand VecIn1, VecIn2;
4083 for (unsigned i = 0; i != NumInScalars; ++i) {
4084 // Ignore undef inputs.
4085 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4087 // If this input is something other than a EXTRACT_VECTOR_ELT with a
4088 // constant index, bail out.
4089 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4090 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
4091 VecIn1 = VecIn2 = SDOperand(0, 0);
4095 // If the input vector type disagrees with the result of the build_vector,
4096 // we can't make a shuffle.
4097 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
4098 if (ExtractedFromVec.getValueType() != VT) {
4099 VecIn1 = VecIn2 = SDOperand(0, 0);
4103 // Otherwise, remember this. We allow up to two distinct input vectors.
4104 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
4107 if (VecIn1.Val == 0) {
4108 VecIn1 = ExtractedFromVec;
4109 } else if (VecIn2.Val == 0) {
4110 VecIn2 = ExtractedFromVec;
4113 VecIn1 = VecIn2 = SDOperand(0, 0);
4118 // If everything is good, we can make a shuffle operation.
4120 SmallVector<SDOperand, 8> BuildVecIndices;
4121 for (unsigned i = 0; i != NumInScalars; ++i) {
4122 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
4123 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
4127 SDOperand Extract = N->getOperand(i);
4129 // If extracting from the first vector, just use the index directly.
4130 if (Extract.getOperand(0) == VecIn1) {
4131 BuildVecIndices.push_back(Extract.getOperand(1));
4135 // Otherwise, use InIdx + VecSize
4136 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
4137 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars,
4138 TLI.getPointerTy()));
4141 // Add count and size info.
4142 MVT::ValueType BuildVecVT =
4143 MVT::getVectorType(TLI.getPointerTy(), NumElts);
4145 // Return the new VECTOR_SHUFFLE node.
4151 // Use an undef build_vector as input for the second operand.
4152 std::vector<SDOperand> UnOps(NumInScalars,
4153 DAG.getNode(ISD::UNDEF,
4155 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
4156 &UnOps[0], UnOps.size());
4157 AddToWorkList(Ops[1].Val);
4159 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
4160 &BuildVecIndices[0], BuildVecIndices.size());
4161 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3);
4167 SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
4168 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
4169 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
4170 // inputs come from at most two distinct vectors, turn this into a shuffle
4173 // If we only have one input vector, we don't need to do any concatenation.
4174 if (N->getNumOperands() == 1) {
4175 return N->getOperand(0);
4181 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
4182 SDOperand ShufMask = N->getOperand(2);
4183 unsigned NumElts = ShufMask.getNumOperands();
4185 // If the shuffle mask is an identity operation on the LHS, return the LHS.
4186 bool isIdentity = true;
4187 for (unsigned i = 0; i != NumElts; ++i) {
4188 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4189 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
4194 if (isIdentity) return N->getOperand(0);
4196 // If the shuffle mask is an identity operation on the RHS, return the RHS.
4198 for (unsigned i = 0; i != NumElts; ++i) {
4199 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4200 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
4205 if (isIdentity) return N->getOperand(1);
4207 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
4209 bool isUnary = true;
4210 bool isSplat = true;
4212 unsigned BaseIdx = 0;
4213 for (unsigned i = 0; i != NumElts; ++i)
4214 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
4215 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
4216 int V = (Idx < NumElts) ? 0 : 1;
4230 SDOperand N0 = N->getOperand(0);
4231 SDOperand N1 = N->getOperand(1);
4232 // Normalize unary shuffle so the RHS is undef.
4233 if (isUnary && VecNum == 1)
4236 // If it is a splat, check if the argument vector is a build_vector with
4237 // all scalar elements the same.
4241 // If this is a bit convert that changes the element type of the vector but
4242 // not the number of vector elements, look through it. Be careful not to
4243 // look though conversions that change things like v4f32 to v2f64.
4244 if (V->getOpcode() == ISD::BIT_CONVERT) {
4245 SDOperand ConvInput = V->getOperand(0);
4246 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts)
4250 if (V->getOpcode() == ISD::BUILD_VECTOR) {
4251 unsigned NumElems = V->getNumOperands();
4252 if (NumElems > BaseIdx) {
4254 bool AllSame = true;
4255 for (unsigned i = 0; i != NumElems; ++i) {
4256 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
4257 Base = V->getOperand(i);
4261 // Splat of <u, u, u, u>, return <u, u, u, u>
4264 for (unsigned i = 0; i != NumElems; ++i) {
4265 if (V->getOperand(i) != Base) {
4270 // Splat of <x, x, x, x>, return <x, x, x, x>
4277 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
4279 if (isUnary || N0 == N1) {
4280 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
4282 SmallVector<SDOperand, 8> MappedOps;
4283 for (unsigned i = 0; i != NumElts; ++i) {
4284 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
4285 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
4286 MappedOps.push_back(ShufMask.getOperand(i));
4289 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
4290 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
4293 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
4294 &MappedOps[0], MappedOps.size());
4295 AddToWorkList(ShufMask.Val);
4296 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
4298 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
4305 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
4306 /// an AND to a vector_shuffle with the destination vector and a zero vector.
4307 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
4308 /// vector_shuffle V, Zero, <0, 4, 2, 4>
4309 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
4310 SDOperand LHS = N->getOperand(0);
4311 SDOperand RHS = N->getOperand(1);
4312 if (N->getOpcode() == ISD::AND) {
4313 if (RHS.getOpcode() == ISD::BIT_CONVERT)
4314 RHS = RHS.getOperand(0);
4315 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
4316 std::vector<SDOperand> IdxOps;
4317 unsigned NumOps = RHS.getNumOperands();
4318 unsigned NumElts = NumOps;
4319 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType());
4320 for (unsigned i = 0; i != NumElts; ++i) {
4321 SDOperand Elt = RHS.getOperand(i);
4322 if (!isa<ConstantSDNode>(Elt))
4324 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
4325 IdxOps.push_back(DAG.getConstant(i, EVT));
4326 else if (cast<ConstantSDNode>(Elt)->isNullValue())
4327 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
4332 // Let's see if the target supports this vector_shuffle.
4333 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
4336 // Return the new VECTOR_SHUFFLE node.
4337 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts);
4338 std::vector<SDOperand> Ops;
4339 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
4341 AddToWorkList(LHS.Val);
4342 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
4343 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4344 &ZeroOps[0], ZeroOps.size()));
4345 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4346 &IdxOps[0], IdxOps.size()));
4347 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
4348 &Ops[0], Ops.size());
4349 if (VT != LHS.getValueType()) {
4350 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result);
4358 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
4359 SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
4360 // After legalize, the target may be depending on adds and other
4361 // binary ops to provide legal ways to construct constants or other
4362 // things. Simplifying them may result in a loss of legality.
4363 if (AfterLegalize) return SDOperand();
4365 MVT::ValueType VT = N->getValueType(0);
4366 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!");
4368 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4369 SDOperand LHS = N->getOperand(0);
4370 SDOperand RHS = N->getOperand(1);
4371 SDOperand Shuffle = XformToShuffleWithZero(N);
4372 if (Shuffle.Val) return Shuffle;
4374 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
4376 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
4377 RHS.getOpcode() == ISD::BUILD_VECTOR) {
4378 SmallVector<SDOperand, 8> Ops;
4379 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
4380 SDOperand LHSOp = LHS.getOperand(i);
4381 SDOperand RHSOp = RHS.getOperand(i);
4382 // If these two elements can't be folded, bail out.
4383 if ((LHSOp.getOpcode() != ISD::UNDEF &&
4384 LHSOp.getOpcode() != ISD::Constant &&
4385 LHSOp.getOpcode() != ISD::ConstantFP) ||
4386 (RHSOp.getOpcode() != ISD::UNDEF &&
4387 RHSOp.getOpcode() != ISD::Constant &&
4388 RHSOp.getOpcode() != ISD::ConstantFP))
4390 // Can't fold divide by zero.
4391 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
4392 N->getOpcode() == ISD::FDIV) {
4393 if ((RHSOp.getOpcode() == ISD::Constant &&
4394 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
4395 (RHSOp.getOpcode() == ISD::ConstantFP &&
4396 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero()))
4399 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
4400 AddToWorkList(Ops.back().Val);
4401 assert((Ops.back().getOpcode() == ISD::UNDEF ||
4402 Ops.back().getOpcode() == ISD::Constant ||
4403 Ops.back().getOpcode() == ISD::ConstantFP) &&
4404 "Scalar binop didn't fold!");
4407 if (Ops.size() == LHS.getNumOperands()) {
4408 MVT::ValueType VT = LHS.getValueType();
4409 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
4416 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
4417 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
4419 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
4420 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4421 // If we got a simplified select_cc node back from SimplifySelectCC, then
4422 // break it down into a new SETCC node, and a new SELECT node, and then return
4423 // the SELECT node, since we were called with a SELECT node.
4425 // Check to see if we got a select_cc back (to turn into setcc/select).
4426 // Otherwise, just return whatever node we got back, like fabs.
4427 if (SCC.getOpcode() == ISD::SELECT_CC) {
4428 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
4429 SCC.getOperand(0), SCC.getOperand(1),
4431 AddToWorkList(SETCC.Val);
4432 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
4433 SCC.getOperand(3), SETCC);
4440 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
4441 /// are the two values being selected between, see if we can simplify the
4442 /// select. Callers of this should assume that TheSelect is deleted if this
4443 /// returns true. As such, they should return the appropriate thing (e.g. the
4444 /// node) back to the top-level of the DAG combiner loop to avoid it being
4447 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
4450 // If this is a select from two identical things, try to pull the operation
4451 // through the select.
4452 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
4453 // If this is a load and the token chain is identical, replace the select
4454 // of two loads with a load through a select of the address to load from.
4455 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
4456 // constants have been dropped into the constant pool.
4457 if (LHS.getOpcode() == ISD::LOAD &&
4458 // Token chains must be identical.
4459 LHS.getOperand(0) == RHS.getOperand(0)) {
4460 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
4461 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
4463 // If this is an EXTLOAD, the VT's must match.
4464 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
4465 // FIXME: this conflates two src values, discarding one. This is not
4466 // the right thing to do, but nothing uses srcvalues now. When they do,
4467 // turn SrcValue into a list of locations.
4469 if (TheSelect->getOpcode() == ISD::SELECT) {
4470 // Check that the condition doesn't reach either load. If so, folding
4471 // this will induce a cycle into the DAG.
4472 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4473 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
4474 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
4475 TheSelect->getOperand(0), LLD->getBasePtr(),
4479 // Check that the condition doesn't reach either load. If so, folding
4480 // this will induce a cycle into the DAG.
4481 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4482 !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4483 !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
4484 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
4485 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
4486 TheSelect->getOperand(0),
4487 TheSelect->getOperand(1),
4488 LLD->getBasePtr(), RLD->getBasePtr(),
4489 TheSelect->getOperand(4));
4495 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
4496 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
4497 Addr,LLD->getSrcValue(),
4498 LLD->getSrcValueOffset(),
4500 LLD->getAlignment());
4502 Load = DAG.getExtLoad(LLD->getExtensionType(),
4503 TheSelect->getValueType(0),
4504 LLD->getChain(), Addr, LLD->getSrcValue(),
4505 LLD->getSrcValueOffset(),
4508 LLD->getAlignment());
4510 // Users of the select now use the result of the load.
4511 CombineTo(TheSelect, Load);
4513 // Users of the old loads now use the new load's chain. We know the
4514 // old-load value is dead now.
4515 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
4516 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
4526 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
4527 SDOperand N2, SDOperand N3,
4528 ISD::CondCode CC, bool NotExtCompare) {
4530 MVT::ValueType VT = N2.getValueType();
4531 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
4532 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
4533 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
4535 // Determine if the condition we're dealing with is constant
4536 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
4537 if (SCC.Val) AddToWorkList(SCC.Val);
4538 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
4540 // fold select_cc true, x, y -> x
4541 if (SCCC && SCCC->getValue())
4543 // fold select_cc false, x, y -> y
4544 if (SCCC && SCCC->getValue() == 0)
4547 // Check to see if we can simplify the select into an fabs node
4548 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
4549 // Allow either -0.0 or 0.0
4550 if (CFP->getValueAPF().isZero()) {
4551 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
4552 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
4553 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
4554 N2 == N3.getOperand(0))
4555 return DAG.getNode(ISD::FABS, VT, N0);
4557 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
4558 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
4559 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
4560 N2.getOperand(0) == N3)
4561 return DAG.getNode(ISD::FABS, VT, N3);
4565 // Check to see if we can perform the "gzip trick", transforming
4566 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
4567 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
4568 MVT::isInteger(N0.getValueType()) &&
4569 MVT::isInteger(N2.getValueType()) &&
4570 (N1C->isNullValue() || // (a < 0) ? b : 0
4571 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
4572 MVT::ValueType XType = N0.getValueType();
4573 MVT::ValueType AType = N2.getValueType();
4574 if (XType >= AType) {
4575 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
4576 // single-bit constant.
4577 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
4578 unsigned ShCtV = Log2_64(N2C->getValue());
4579 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
4580 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
4581 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
4582 AddToWorkList(Shift.Val);
4583 if (XType > AType) {
4584 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4585 AddToWorkList(Shift.Val);
4587 return DAG.getNode(ISD::AND, AType, Shift, N2);
4589 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4590 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4591 TLI.getShiftAmountTy()));
4592 AddToWorkList(Shift.Val);
4593 if (XType > AType) {
4594 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4595 AddToWorkList(Shift.Val);
4597 return DAG.getNode(ISD::AND, AType, Shift, N2);
4601 // fold select C, 16, 0 -> shl C, 4
4602 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
4603 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
4605 // If the caller doesn't want us to simplify this into a zext of a compare,
4607 if (NotExtCompare && N2C->getValue() == 1)
4610 // Get a SetCC of the condition
4611 // FIXME: Should probably make sure that setcc is legal if we ever have a
4612 // target where it isn't.
4613 SDOperand Temp, SCC;
4614 // cast from setcc result type to select result type
4615 if (AfterLegalize) {
4616 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4617 if (N2.getValueType() < SCC.getValueType())
4618 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
4620 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4622 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
4623 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4625 AddToWorkList(SCC.Val);
4626 AddToWorkList(Temp.Val);
4628 if (N2C->getValue() == 1)
4630 // shl setcc result by log2 n2c
4631 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
4632 DAG.getConstant(Log2_64(N2C->getValue()),
4633 TLI.getShiftAmountTy()));
4636 // Check to see if this is the equivalent of setcc
4637 // FIXME: Turn all of these into setcc if setcc if setcc is legal
4638 // otherwise, go ahead with the folds.
4639 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
4640 MVT::ValueType XType = N0.getValueType();
4641 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
4642 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4643 if (Res.getValueType() != VT)
4644 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
4648 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
4649 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
4650 TLI.isOperationLegal(ISD::CTLZ, XType)) {
4651 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
4652 return DAG.getNode(ISD::SRL, XType, Ctlz,
4653 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
4654 TLI.getShiftAmountTy()));
4656 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
4657 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
4658 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
4660 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
4661 DAG.getConstant(~0ULL, XType));
4662 return DAG.getNode(ISD::SRL, XType,
4663 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
4664 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4665 TLI.getShiftAmountTy()));
4667 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
4668 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
4669 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
4670 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4671 TLI.getShiftAmountTy()));
4672 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
4676 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
4677 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4678 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
4679 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
4680 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) {
4681 MVT::ValueType XType = N0.getValueType();
4682 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4683 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4684 TLI.getShiftAmountTy()));
4685 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4686 AddToWorkList(Shift.Val);
4687 AddToWorkList(Add.Val);
4688 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4690 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
4691 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4692 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
4693 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
4694 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
4695 MVT::ValueType XType = N0.getValueType();
4696 if (SubC->isNullValue() && MVT::isInteger(XType)) {
4697 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4698 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4699 TLI.getShiftAmountTy()));
4700 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4701 AddToWorkList(Shift.Val);
4702 AddToWorkList(Add.Val);
4703 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4711 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
4712 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
4713 SDOperand N1, ISD::CondCode Cond,
4714 bool foldBooleans) {
4715 TargetLowering::DAGCombinerInfo
4716 DagCombineInfo(DAG, !AfterLegalize, false, this);
4717 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
4720 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
4721 /// return a DAG expression to select that will generate the same value by
4722 /// multiplying by a magic number. See:
4723 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4724 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
4725 std::vector<SDNode*> Built;
4726 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
4728 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4734 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
4735 /// return a DAG expression to select that will generate the same value by
4736 /// multiplying by a magic number. See:
4737 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4738 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
4739 std::vector<SDNode*> Built;
4740 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
4742 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4748 /// FindBaseOffset - Return true if base is known not to alias with anything
4749 /// but itself. Provides base object and offset as results.
4750 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4751 // Assume it is a primitive operation.
4752 Base = Ptr; Offset = 0;
4754 // If it's an adding a simple constant then integrate the offset.
4755 if (Base.getOpcode() == ISD::ADD) {
4756 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4757 Base = Base.getOperand(0);
4758 Offset += C->getValue();
4762 // If it's any of the following then it can't alias with anything but itself.
4763 return isa<FrameIndexSDNode>(Base) ||
4764 isa<ConstantPoolSDNode>(Base) ||
4765 isa<GlobalAddressSDNode>(Base);
4768 /// isAlias - Return true if there is any possibility that the two addresses
4770 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4771 const Value *SrcValue1, int SrcValueOffset1,
4772 SDOperand Ptr2, int64_t Size2,
4773 const Value *SrcValue2, int SrcValueOffset2)
4775 // If they are the same then they must be aliases.
4776 if (Ptr1 == Ptr2) return true;
4778 // Gather base node and offset information.
4779 SDOperand Base1, Base2;
4780 int64_t Offset1, Offset2;
4781 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4782 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4784 // If they have a same base address then...
4785 if (Base1 == Base2) {
4786 // Check to see if the addresses overlap.
4787 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4790 // If we know both bases then they can't alias.
4791 if (KnownBase1 && KnownBase2) return false;
4793 if (CombinerGlobalAA) {
4794 // Use alias analysis information.
4795 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
4796 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
4797 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
4798 AliasAnalysis::AliasResult AAResult =
4799 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
4800 if (AAResult == AliasAnalysis::NoAlias)
4804 // Otherwise we have to assume they alias.
4808 /// FindAliasInfo - Extracts the relevant alias information from the memory
4809 /// node. Returns true if the operand was a load.
4810 bool DAGCombiner::FindAliasInfo(SDNode *N,
4811 SDOperand &Ptr, int64_t &Size,
4812 const Value *&SrcValue, int &SrcValueOffset) {
4813 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4814 Ptr = LD->getBasePtr();
4815 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4816 SrcValue = LD->getSrcValue();
4817 SrcValueOffset = LD->getSrcValueOffset();
4819 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4820 Ptr = ST->getBasePtr();
4821 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4822 SrcValue = ST->getSrcValue();
4823 SrcValueOffset = ST->getSrcValueOffset();
4825 assert(0 && "FindAliasInfo expected a memory operand");
4831 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4832 /// looking for aliasing nodes and adding them to the Aliases vector.
4833 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4834 SmallVector<SDOperand, 8> &Aliases) {
4835 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4836 std::set<SDNode *> Visited; // Visited node set.
4838 // Get alias information for node.
4841 const Value *SrcValue;
4843 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
4846 Chains.push_back(OriginalChain);
4848 // Look at each chain and determine if it is an alias. If so, add it to the
4849 // aliases list. If not, then continue up the chain looking for the next
4851 while (!Chains.empty()) {
4852 SDOperand Chain = Chains.back();
4855 // Don't bother if we've been before.
4856 if (Visited.find(Chain.Val) != Visited.end()) continue;
4857 Visited.insert(Chain.Val);
4859 switch (Chain.getOpcode()) {
4860 case ISD::EntryToken:
4861 // Entry token is ideal chain operand, but handled in FindBetterChain.
4866 // Get alias information for Chain.
4869 const Value *OpSrcValue;
4870 int OpSrcValueOffset;
4871 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
4872 OpSrcValue, OpSrcValueOffset);
4874 // If chain is alias then stop here.
4875 if (!(IsLoad && IsOpLoad) &&
4876 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
4877 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
4878 Aliases.push_back(Chain);
4880 // Look further up the chain.
4881 Chains.push_back(Chain.getOperand(0));
4882 // Clean up old chain.
4883 AddToWorkList(Chain.Val);
4888 case ISD::TokenFactor:
4889 // We have to check each of the operands of the token factor, so we queue
4890 // then up. Adding the operands to the queue (stack) in reverse order
4891 // maintains the original order and increases the likelihood that getNode
4892 // will find a matching token factor (CSE.)
4893 for (unsigned n = Chain.getNumOperands(); n;)
4894 Chains.push_back(Chain.getOperand(--n));
4895 // Eliminate the token factor if we can.
4896 AddToWorkList(Chain.Val);
4900 // For all other instructions we will just have to take what we can get.
4901 Aliases.push_back(Chain);
4907 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4908 /// for a better chain (aliasing node.)
4909 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4910 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4912 // Accumulate all the aliases to this node.
4913 GatherAllAliases(N, OldChain, Aliases);
4915 if (Aliases.size() == 0) {
4916 // If no operands then chain to entry token.
4917 return DAG.getEntryNode();
4918 } else if (Aliases.size() == 1) {
4919 // If a single operand then chain to it. We don't need to revisit it.
4923 // Construct a custom tailored token factor.
4924 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4925 &Aliases[0], Aliases.size());
4927 // Make sure the old chain gets cleaned up.
4928 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4933 // SelectionDAG::Combine - This is the entry point for the file.
4935 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
4936 if (!RunningAfterLegalize && ViewDAGCombine1)
4938 if (RunningAfterLegalize && ViewDAGCombine2)
4940 /// run - This is the main entry point to this class.
4942 DAGCombiner(*this, AA).Run(RunningAfterLegalize);