1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/Target/TargetData.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/SmallPtrSet.h"
39 #include "llvm/ADT/Statistic.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/MathExtras.h"
47 STATISTIC(NodesCombined , "Number of dag nodes combined");
48 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
49 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
54 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
55 cl::desc("Pop up a window to show dags before the first "
58 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
59 cl::desc("Pop up a window to show dags before the second "
62 static const bool ViewDAGCombine1 = false;
63 static const bool ViewDAGCombine2 = false;
67 CombinerAA("combiner-alias-analysis", cl::Hidden,
68 cl::desc("Turn on alias analysis during testing"));
71 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
72 cl::desc("Include global information in alias analysis"));
74 //------------------------------ DAGCombiner ---------------------------------//
76 class VISIBILITY_HIDDEN DAGCombiner {
81 // Worklist of all of the nodes that need to be simplified.
82 std::vector<SDNode*> WorkList;
84 // AA - Used for DAG load/store alias analysis.
87 /// AddUsersToWorkList - When an instruction is simplified, add all users of
88 /// the instruction to the work lists because they might get more simplified
91 void AddUsersToWorkList(SDNode *N) {
92 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
97 /// removeFromWorkList - remove all instances of N from the worklist.
99 void removeFromWorkList(SDNode *N) {
100 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
104 /// visit - call the node-specific routine that knows how to fold each
105 /// particular type of node.
106 SDOperand visit(SDNode *N);
109 /// AddToWorkList - Add to the work list making sure it's instance is at the
110 /// the back (next to be processed.)
111 void AddToWorkList(SDNode *N) {
112 removeFromWorkList(N);
113 WorkList.push_back(N);
116 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
118 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
120 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
121 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
122 DOUT << " and " << NumTo-1 << " other values\n";
123 std::vector<SDNode*> NowDead;
124 DAG.ReplaceAllUsesWith(N, To, &NowDead);
127 // Push the new nodes and any users onto the worklist
128 for (unsigned i = 0, e = NumTo; i != e; ++i) {
129 AddToWorkList(To[i].Val);
130 AddUsersToWorkList(To[i].Val);
134 // Nodes can be reintroduced into the worklist. Make sure we do not
135 // process a node that has been replaced.
136 removeFromWorkList(N);
137 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
138 removeFromWorkList(NowDead[i]);
140 // Finally, since the node is now dead, remove it from the graph.
142 return SDOperand(N, 0);
145 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
146 return CombineTo(N, &Res, 1, AddTo);
149 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
151 SDOperand To[] = { Res0, Res1 };
152 return CombineTo(N, To, 2, AddTo);
156 /// SimplifyDemandedBits - Check the specified integer node value to see if
157 /// it can be simplified or if things it uses can be simplified by bit
158 /// propagation. If so, return true.
159 bool SimplifyDemandedBits(SDOperand Op) {
160 TargetLowering::TargetLoweringOpt TLO(DAG);
161 uint64_t KnownZero, KnownOne;
162 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
163 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
167 AddToWorkList(Op.Val);
169 // Replace the old value with the new one.
171 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
172 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
175 std::vector<SDNode*> NowDead;
176 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
178 // Push the new node and any (possibly new) users onto the worklist.
179 AddToWorkList(TLO.New.Val);
180 AddUsersToWorkList(TLO.New.Val);
182 // Nodes can end up on the worklist more than once. Make sure we do
183 // not process a node that has been replaced.
184 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
185 removeFromWorkList(NowDead[i]);
187 // Finally, if the node is now dead, remove it from the graph. The node
188 // may not be dead if the replacement process recursively simplified to
189 // something else needing this node.
190 if (TLO.Old.Val->use_empty()) {
191 removeFromWorkList(TLO.Old.Val);
193 // If the operands of this node are only used by the node, they will now
194 // be dead. Make sure to visit them first to delete dead nodes early.
195 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i)
196 if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
197 AddToWorkList(TLO.Old.Val->getOperand(i).Val);
199 DAG.DeleteNode(TLO.Old.Val);
204 bool CombineToPreIndexedLoadStore(SDNode *N);
205 bool CombineToPostIndexedLoadStore(SDNode *N);
208 /// combine - call the node-specific routine that knows how to fold each
209 /// particular type of node. If that doesn't do anything, try the
210 /// target-specific DAG combines.
211 SDOperand combine(SDNode *N);
213 // Visitation implementation - Implement dag node combining for different
214 // node types. The semantics are as follows:
216 // SDOperand.Val == 0 - No change was made
217 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
218 // otherwise - N should be replaced by the returned Operand.
220 SDOperand visitTokenFactor(SDNode *N);
221 SDOperand visitADD(SDNode *N);
222 SDOperand visitSUB(SDNode *N);
223 SDOperand visitADDC(SDNode *N);
224 SDOperand visitADDE(SDNode *N);
225 SDOperand visitMUL(SDNode *N);
226 SDOperand visitSDIV(SDNode *N);
227 SDOperand visitUDIV(SDNode *N);
228 SDOperand visitSREM(SDNode *N);
229 SDOperand visitUREM(SDNode *N);
230 SDOperand visitMULHU(SDNode *N);
231 SDOperand visitMULHS(SDNode *N);
232 SDOperand visitSMUL_LOHI(SDNode *N);
233 SDOperand visitUMUL_LOHI(SDNode *N);
234 SDOperand visitSDIVREM(SDNode *N);
235 SDOperand visitUDIVREM(SDNode *N);
236 SDOperand visitAND(SDNode *N);
237 SDOperand visitOR(SDNode *N);
238 SDOperand visitXOR(SDNode *N);
239 SDOperand SimplifyVBinOp(SDNode *N);
240 SDOperand visitSHL(SDNode *N);
241 SDOperand visitSRA(SDNode *N);
242 SDOperand visitSRL(SDNode *N);
243 SDOperand visitCTLZ(SDNode *N);
244 SDOperand visitCTTZ(SDNode *N);
245 SDOperand visitCTPOP(SDNode *N);
246 SDOperand visitSELECT(SDNode *N);
247 SDOperand visitSELECT_CC(SDNode *N);
248 SDOperand visitSETCC(SDNode *N);
249 SDOperand visitSIGN_EXTEND(SDNode *N);
250 SDOperand visitZERO_EXTEND(SDNode *N);
251 SDOperand visitANY_EXTEND(SDNode *N);
252 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
253 SDOperand visitTRUNCATE(SDNode *N);
254 SDOperand visitBIT_CONVERT(SDNode *N);
255 SDOperand visitFADD(SDNode *N);
256 SDOperand visitFSUB(SDNode *N);
257 SDOperand visitFMUL(SDNode *N);
258 SDOperand visitFDIV(SDNode *N);
259 SDOperand visitFREM(SDNode *N);
260 SDOperand visitFCOPYSIGN(SDNode *N);
261 SDOperand visitSINT_TO_FP(SDNode *N);
262 SDOperand visitUINT_TO_FP(SDNode *N);
263 SDOperand visitFP_TO_SINT(SDNode *N);
264 SDOperand visitFP_TO_UINT(SDNode *N);
265 SDOperand visitFP_ROUND(SDNode *N);
266 SDOperand visitFP_ROUND_INREG(SDNode *N);
267 SDOperand visitFP_EXTEND(SDNode *N);
268 SDOperand visitFNEG(SDNode *N);
269 SDOperand visitFABS(SDNode *N);
270 SDOperand visitBRCOND(SDNode *N);
271 SDOperand visitBR_CC(SDNode *N);
272 SDOperand visitLOAD(SDNode *N);
273 SDOperand visitSTORE(SDNode *N);
274 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
275 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N);
276 SDOperand visitBUILD_VECTOR(SDNode *N);
277 SDOperand visitCONCAT_VECTORS(SDNode *N);
278 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
280 SDOperand XformToShuffleWithZero(SDNode *N);
281 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
283 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
284 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
285 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
286 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
287 SDOperand N3, ISD::CondCode CC,
288 bool NotExtCompare = false);
289 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
290 ISD::CondCode Cond, bool foldBooleans = true);
291 bool SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp);
292 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
293 SDOperand BuildSDIV(SDNode *N);
294 SDOperand BuildUDIV(SDNode *N);
295 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
296 SDOperand ReduceLoadWidth(SDNode *N);
298 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask);
300 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
301 /// looking for aliasing nodes and adding them to the Aliases vector.
302 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
303 SmallVector<SDOperand, 8> &Aliases);
305 /// isAlias - Return true if there is any possibility that the two addresses
307 bool isAlias(SDOperand Ptr1, int64_t Size1,
308 const Value *SrcValue1, int SrcValueOffset1,
309 SDOperand Ptr2, int64_t Size2,
310 const Value *SrcValue2, int SrcValueOffset2);
312 /// FindAliasInfo - Extracts the relevant alias information from the memory
313 /// node. Returns true if the operand was a load.
314 bool FindAliasInfo(SDNode *N,
315 SDOperand &Ptr, int64_t &Size,
316 const Value *&SrcValue, int &SrcValueOffset);
318 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
319 /// looking for a better chain (aliasing node.)
320 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
323 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
325 TLI(D.getTargetLoweringInfo()),
326 AfterLegalize(false),
329 /// Run - runs the dag combiner on all nodes in the work list
330 void Run(bool RunningAfterLegalize);
334 //===----------------------------------------------------------------------===//
335 // TargetLowering::DAGCombinerInfo implementation
336 //===----------------------------------------------------------------------===//
338 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
339 ((DAGCombiner*)DC)->AddToWorkList(N);
342 SDOperand TargetLowering::DAGCombinerInfo::
343 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
344 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
347 SDOperand TargetLowering::DAGCombinerInfo::
348 CombineTo(SDNode *N, SDOperand Res) {
349 return ((DAGCombiner*)DC)->CombineTo(N, Res);
353 SDOperand TargetLowering::DAGCombinerInfo::
354 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
355 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
359 //===----------------------------------------------------------------------===//
361 //===----------------------------------------------------------------------===//
363 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
364 /// specified expression for the same cost as the expression itself, or 2 if we
365 /// can compute the negated form more cheaply than the expression itself.
366 static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) {
367 // fneg is removable even if it has multiple uses.
368 if (Op.getOpcode() == ISD::FNEG) return 2;
370 // Don't allow anything with multiple uses.
371 if (!Op.hasOneUse()) return 0;
373 // Don't recurse exponentially.
374 if (Depth > 6) return 0;
376 switch (Op.getOpcode()) {
377 default: return false;
378 case ISD::ConstantFP:
381 // FIXME: determine better conditions for this xform.
382 if (!UnsafeFPMath) return 0;
385 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
388 return isNegatibleForFree(Op.getOperand(1), Depth+1);
390 // We can't turn -(A-B) into B-A when we honor signed zeros.
391 if (!UnsafeFPMath) return 0;
398 if (HonorSignDependentRoundingFPMath()) return 0;
400 // -(X*Y) -> (-X * Y) or (X*-Y)
401 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
404 return isNegatibleForFree(Op.getOperand(1), Depth+1);
409 return isNegatibleForFree(Op.getOperand(0), Depth+1);
413 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
414 /// returns the newly negated expression.
415 static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
416 unsigned Depth = 0) {
417 // fneg is removable even if it has multiple uses.
418 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
420 // Don't allow anything with multiple uses.
421 assert(Op.hasOneUse() && "Unknown reuse!");
423 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
424 switch (Op.getOpcode()) {
425 default: assert(0 && "Unknown code");
426 case ISD::ConstantFP: {
427 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
429 return DAG.getConstantFP(V, Op.getValueType());
432 // FIXME: determine better conditions for this xform.
433 assert(UnsafeFPMath);
436 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
437 return DAG.getNode(ISD::FSUB, Op.getValueType(),
438 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
441 return DAG.getNode(ISD::FSUB, Op.getValueType(),
442 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1),
445 // We can't turn -(A-B) into B-A when we honor signed zeros.
446 assert(UnsafeFPMath);
449 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
450 if (N0CFP->getValueAPF().isZero())
451 return Op.getOperand(1);
454 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1),
459 assert(!HonorSignDependentRoundingFPMath());
462 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
463 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
464 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
468 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
470 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1));
475 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
476 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1));
481 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
482 // that selects between the values 1 and 0, making it equivalent to a setcc.
483 // Also, set the incoming LHS, RHS, and CC references to the appropriate
484 // nodes based on the type of node we are checking. This simplifies life a
485 // bit for the callers.
486 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
488 if (N.getOpcode() == ISD::SETCC) {
489 LHS = N.getOperand(0);
490 RHS = N.getOperand(1);
491 CC = N.getOperand(2);
494 if (N.getOpcode() == ISD::SELECT_CC &&
495 N.getOperand(2).getOpcode() == ISD::Constant &&
496 N.getOperand(3).getOpcode() == ISD::Constant &&
497 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
498 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
499 LHS = N.getOperand(0);
500 RHS = N.getOperand(1);
501 CC = N.getOperand(4);
507 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
508 // one use. If this is true, it allows the users to invert the operation for
509 // free when it is profitable to do so.
510 static bool isOneUseSetCC(SDOperand N) {
511 SDOperand N0, N1, N2;
512 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
517 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
518 MVT::ValueType VT = N0.getValueType();
519 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
520 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
521 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
522 if (isa<ConstantSDNode>(N1)) {
523 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
524 AddToWorkList(OpNode.Val);
525 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
526 } else if (N0.hasOneUse()) {
527 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
528 AddToWorkList(OpNode.Val);
529 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
532 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
533 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
534 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
535 if (isa<ConstantSDNode>(N0)) {
536 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
537 AddToWorkList(OpNode.Val);
538 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
539 } else if (N1.hasOneUse()) {
540 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
541 AddToWorkList(OpNode.Val);
542 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
548 //===----------------------------------------------------------------------===//
549 // Main DAG Combiner implementation
550 //===----------------------------------------------------------------------===//
552 void DAGCombiner::Run(bool RunningAfterLegalize) {
553 // set the instance variable, so that the various visit routines may use it.
554 AfterLegalize = RunningAfterLegalize;
556 // Add all the dag nodes to the worklist.
557 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
558 E = DAG.allnodes_end(); I != E; ++I)
559 WorkList.push_back(I);
561 // Create a dummy node (which is not added to allnodes), that adds a reference
562 // to the root node, preventing it from being deleted, and tracking any
563 // changes of the root.
564 HandleSDNode Dummy(DAG.getRoot());
566 // The root of the dag may dangle to deleted nodes until the dag combiner is
567 // done. Set it to null to avoid confusion.
568 DAG.setRoot(SDOperand());
570 // while the worklist isn't empty, inspect the node on the end of it and
571 // try and combine it.
572 while (!WorkList.empty()) {
573 SDNode *N = WorkList.back();
576 // If N has no uses, it is dead. Make sure to revisit all N's operands once
577 // N is deleted from the DAG, since they too may now be dead or may have a
578 // reduced number of uses, allowing other xforms.
579 if (N->use_empty() && N != &Dummy) {
580 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
581 AddToWorkList(N->getOperand(i).Val);
587 SDOperand RV = combine(N);
591 // If we get back the same node we passed in, rather than a new node or
592 // zero, we know that the node must have defined multiple values and
593 // CombineTo was used. Since CombineTo takes care of the worklist
594 // mechanics for us, we have no work to do in this case.
596 assert(N->getOpcode() != ISD::DELETED_NODE &&
597 RV.Val->getOpcode() != ISD::DELETED_NODE &&
598 "Node was deleted but visit returned new node!");
600 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
601 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
603 std::vector<SDNode*> NowDead;
604 if (N->getNumValues() == RV.Val->getNumValues())
605 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
607 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
609 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
612 // Push the new node and any users onto the worklist
613 AddToWorkList(RV.Val);
614 AddUsersToWorkList(RV.Val);
616 // Nodes can be reintroduced into the worklist. Make sure we do not
617 // process a node that has been replaced.
618 removeFromWorkList(N);
619 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
620 removeFromWorkList(NowDead[i]);
622 // Finally, since the node is now dead, remove it from the graph.
628 // If the root changed (e.g. it was a dead load, update the root).
629 DAG.setRoot(Dummy.getValue());
632 SDOperand DAGCombiner::visit(SDNode *N) {
633 switch(N->getOpcode()) {
635 case ISD::TokenFactor: return visitTokenFactor(N);
636 case ISD::ADD: return visitADD(N);
637 case ISD::SUB: return visitSUB(N);
638 case ISD::ADDC: return visitADDC(N);
639 case ISD::ADDE: return visitADDE(N);
640 case ISD::MUL: return visitMUL(N);
641 case ISD::SDIV: return visitSDIV(N);
642 case ISD::UDIV: return visitUDIV(N);
643 case ISD::SREM: return visitSREM(N);
644 case ISD::UREM: return visitUREM(N);
645 case ISD::MULHU: return visitMULHU(N);
646 case ISD::MULHS: return visitMULHS(N);
647 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
648 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
649 case ISD::SDIVREM: return visitSDIVREM(N);
650 case ISD::UDIVREM: return visitUDIVREM(N);
651 case ISD::AND: return visitAND(N);
652 case ISD::OR: return visitOR(N);
653 case ISD::XOR: return visitXOR(N);
654 case ISD::SHL: return visitSHL(N);
655 case ISD::SRA: return visitSRA(N);
656 case ISD::SRL: return visitSRL(N);
657 case ISD::CTLZ: return visitCTLZ(N);
658 case ISD::CTTZ: return visitCTTZ(N);
659 case ISD::CTPOP: return visitCTPOP(N);
660 case ISD::SELECT: return visitSELECT(N);
661 case ISD::SELECT_CC: return visitSELECT_CC(N);
662 case ISD::SETCC: return visitSETCC(N);
663 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
664 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
665 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
666 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
667 case ISD::TRUNCATE: return visitTRUNCATE(N);
668 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
669 case ISD::FADD: return visitFADD(N);
670 case ISD::FSUB: return visitFSUB(N);
671 case ISD::FMUL: return visitFMUL(N);
672 case ISD::FDIV: return visitFDIV(N);
673 case ISD::FREM: return visitFREM(N);
674 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
675 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
676 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
677 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
678 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
679 case ISD::FP_ROUND: return visitFP_ROUND(N);
680 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
681 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
682 case ISD::FNEG: return visitFNEG(N);
683 case ISD::FABS: return visitFABS(N);
684 case ISD::BRCOND: return visitBRCOND(N);
685 case ISD::BR_CC: return visitBR_CC(N);
686 case ISD::LOAD: return visitLOAD(N);
687 case ISD::STORE: return visitSTORE(N);
688 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
689 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
690 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
691 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
692 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
697 SDOperand DAGCombiner::combine(SDNode *N) {
699 SDOperand RV = visit(N);
701 // If nothing happened, try a target-specific DAG combine.
703 assert(N->getOpcode() != ISD::DELETED_NODE &&
704 "Node was deleted but visit returned NULL!");
706 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
707 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
709 // Expose the DAG combiner to the target combiner impls.
710 TargetLowering::DAGCombinerInfo
711 DagCombineInfo(DAG, !AfterLegalize, false, this);
713 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
720 /// getInputChainForNode - Given a node, return its input chain if it has one,
721 /// otherwise return a null sd operand.
722 static SDOperand getInputChainForNode(SDNode *N) {
723 if (unsigned NumOps = N->getNumOperands()) {
724 if (N->getOperand(0).getValueType() == MVT::Other)
725 return N->getOperand(0);
726 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
727 return N->getOperand(NumOps-1);
728 for (unsigned i = 1; i < NumOps-1; ++i)
729 if (N->getOperand(i).getValueType() == MVT::Other)
730 return N->getOperand(i);
732 return SDOperand(0, 0);
735 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
736 // If N has two operands, where one has an input chain equal to the other,
737 // the 'other' chain is redundant.
738 if (N->getNumOperands() == 2) {
739 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
740 return N->getOperand(0);
741 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
742 return N->getOperand(1);
745 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
746 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
747 SmallPtrSet<SDNode*, 16> SeenOps;
748 bool Changed = false; // If we should replace this token factor.
750 // Start out with this token factor.
753 // Iterate through token factors. The TFs grows when new token factors are
755 for (unsigned i = 0; i < TFs.size(); ++i) {
758 // Check each of the operands.
759 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
760 SDOperand Op = TF->getOperand(i);
762 switch (Op.getOpcode()) {
763 case ISD::EntryToken:
764 // Entry tokens don't need to be added to the list. They are
769 case ISD::TokenFactor:
770 if ((CombinerAA || Op.hasOneUse()) &&
771 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
772 // Queue up for processing.
773 TFs.push_back(Op.Val);
774 // Clean up in case the token factor is removed.
775 AddToWorkList(Op.Val);
782 // Only add if it isn't already in the list.
783 if (SeenOps.insert(Op.Val))
794 // If we've change things around then replace token factor.
796 if (Ops.size() == 0) {
797 // The entry token is the only possible outcome.
798 Result = DAG.getEntryNode();
800 // New and improved token factor.
801 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
804 // Don't add users to work list.
805 return CombineTo(N, Result, false);
812 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
813 MVT::ValueType VT = N0.getValueType();
814 SDOperand N00 = N0.getOperand(0);
815 SDOperand N01 = N0.getOperand(1);
816 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
817 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
818 isa<ConstantSDNode>(N00.getOperand(1))) {
819 N0 = DAG.getNode(ISD::ADD, VT,
820 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
821 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
822 return DAG.getNode(ISD::ADD, VT, N0, N1);
828 SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
830 MVT::ValueType VT = N->getValueType(0);
831 unsigned Opc = N->getOpcode();
832 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
833 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
834 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
835 ISD::CondCode CC = ISD::SETCC_INVALID;
837 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
839 SDOperand CCOp = Slct.getOperand(0);
840 if (CCOp.getOpcode() == ISD::SETCC)
841 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
844 bool DoXform = false;
846 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
848 if (LHS.getOpcode() == ISD::Constant &&
849 cast<ConstantSDNode>(LHS)->isNullValue())
851 else if (CC != ISD::SETCC_INVALID &&
852 RHS.getOpcode() == ISD::Constant &&
853 cast<ConstantSDNode>(RHS)->isNullValue()) {
855 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType()
856 : Slct.getOperand(0).getOperand(0).getValueType());
857 CC = ISD::getSetCCInverse(CC, isInt);
863 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS);
865 return DAG.getSelectCC(OtherOp, Result,
866 Slct.getOperand(0), Slct.getOperand(1), CC);
867 SDOperand CCOp = Slct.getOperand(0);
869 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
870 CCOp.getOperand(1), CC);
871 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
876 SDOperand DAGCombiner::visitADD(SDNode *N) {
877 SDOperand N0 = N->getOperand(0);
878 SDOperand N1 = N->getOperand(1);
879 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
880 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
881 MVT::ValueType VT = N0.getValueType();
884 if (MVT::isVector(VT)) {
885 SDOperand FoldedVOp = SimplifyVBinOp(N);
886 if (FoldedVOp.Val) return FoldedVOp;
889 // fold (add x, undef) -> undef
890 if (N0.getOpcode() == ISD::UNDEF)
892 if (N1.getOpcode() == ISD::UNDEF)
894 // fold (add c1, c2) -> c1+c2
896 return DAG.getNode(ISD::ADD, VT, N0, N1);
897 // canonicalize constant to RHS
899 return DAG.getNode(ISD::ADD, VT, N1, N0);
900 // fold (add x, 0) -> x
901 if (N1C && N1C->isNullValue())
903 // fold ((c1-A)+c2) -> (c1+c2)-A
904 if (N1C && N0.getOpcode() == ISD::SUB)
905 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
906 return DAG.getNode(ISD::SUB, VT,
907 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
910 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
913 // fold ((0-A) + B) -> B-A
914 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
915 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
916 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
917 // fold (A + (0-B)) -> A-B
918 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
919 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
920 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
921 // fold (A+(B-A)) -> B
922 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
923 return N1.getOperand(0);
925 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
926 return SDOperand(N, 0);
928 // fold (a+b) -> (a|b) iff a and b share no bits.
929 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
930 uint64_t LHSZero, LHSOne;
931 uint64_t RHSZero, RHSOne;
932 uint64_t Mask = MVT::getIntVTBitMask(VT);
933 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
935 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
937 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
938 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
939 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
940 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
941 return DAG.getNode(ISD::OR, VT, N0, N1);
945 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
946 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
947 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
948 if (Result.Val) return Result;
950 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
951 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
952 if (Result.Val) return Result;
955 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
956 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
957 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG);
958 if (Result.Val) return Result;
960 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
961 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
962 if (Result.Val) return Result;
968 SDOperand DAGCombiner::visitADDC(SDNode *N) {
969 SDOperand N0 = N->getOperand(0);
970 SDOperand N1 = N->getOperand(1);
971 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
972 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
973 MVT::ValueType VT = N0.getValueType();
975 // If the flag result is dead, turn this into an ADD.
976 if (N->hasNUsesOfValue(0, 1))
977 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
978 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
980 // canonicalize constant to RHS.
982 SDOperand Ops[] = { N1, N0 };
983 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
986 // fold (addc x, 0) -> x + no carry out
987 if (N1C && N1C->isNullValue())
988 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
990 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
991 uint64_t LHSZero, LHSOne;
992 uint64_t RHSZero, RHSOne;
993 uint64_t Mask = MVT::getIntVTBitMask(VT);
994 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
996 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
998 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
999 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1000 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1001 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1002 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
1003 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
1009 SDOperand DAGCombiner::visitADDE(SDNode *N) {
1010 SDOperand N0 = N->getOperand(0);
1011 SDOperand N1 = N->getOperand(1);
1012 SDOperand CarryIn = N->getOperand(2);
1013 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1014 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1015 //MVT::ValueType VT = N0.getValueType();
1017 // canonicalize constant to RHS
1019 SDOperand Ops[] = { N1, N0, CarryIn };
1020 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
1023 // fold (adde x, y, false) -> (addc x, y)
1024 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
1025 SDOperand Ops[] = { N1, N0 };
1026 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
1034 SDOperand DAGCombiner::visitSUB(SDNode *N) {
1035 SDOperand N0 = N->getOperand(0);
1036 SDOperand N1 = N->getOperand(1);
1037 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1038 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1039 MVT::ValueType VT = N0.getValueType();
1042 if (MVT::isVector(VT)) {
1043 SDOperand FoldedVOp = SimplifyVBinOp(N);
1044 if (FoldedVOp.Val) return FoldedVOp;
1047 // fold (sub x, x) -> 0
1049 return DAG.getConstant(0, N->getValueType(0));
1050 // fold (sub c1, c2) -> c1-c2
1052 return DAG.getNode(ISD::SUB, VT, N0, N1);
1053 // fold (sub x, c) -> (add x, -c)
1055 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
1056 // fold (A+B)-A -> B
1057 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1058 return N0.getOperand(1);
1059 // fold (A+B)-B -> A
1060 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1061 return N0.getOperand(0);
1062 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1063 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
1064 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
1065 if (Result.Val) return Result;
1067 // If either operand of a sub is undef, the result is undef
1068 if (N0.getOpcode() == ISD::UNDEF)
1070 if (N1.getOpcode() == ISD::UNDEF)
1076 SDOperand DAGCombiner::visitMUL(SDNode *N) {
1077 SDOperand N0 = N->getOperand(0);
1078 SDOperand N1 = N->getOperand(1);
1079 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1080 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1081 MVT::ValueType VT = N0.getValueType();
1084 if (MVT::isVector(VT)) {
1085 SDOperand FoldedVOp = SimplifyVBinOp(N);
1086 if (FoldedVOp.Val) return FoldedVOp;
1089 // fold (mul x, undef) -> 0
1090 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1091 return DAG.getConstant(0, VT);
1092 // fold (mul c1, c2) -> c1*c2
1094 return DAG.getNode(ISD::MUL, VT, N0, N1);
1095 // canonicalize constant to RHS
1097 return DAG.getNode(ISD::MUL, VT, N1, N0);
1098 // fold (mul x, 0) -> 0
1099 if (N1C && N1C->isNullValue())
1101 // fold (mul x, -1) -> 0-x
1102 if (N1C && N1C->isAllOnesValue())
1103 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1104 // fold (mul x, (1 << c)) -> x << c
1105 if (N1C && isPowerOf2_64(N1C->getValue()))
1106 return DAG.getNode(ISD::SHL, VT, N0,
1107 DAG.getConstant(Log2_64(N1C->getValue()),
1108 TLI.getShiftAmountTy()));
1109 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1110 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
1111 // FIXME: If the input is something that is easily negated (e.g. a
1112 // single-use add), we should put the negate there.
1113 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
1114 DAG.getNode(ISD::SHL, VT, N0,
1115 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
1116 TLI.getShiftAmountTy())));
1119 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1120 if (N1C && N0.getOpcode() == ISD::SHL &&
1121 isa<ConstantSDNode>(N0.getOperand(1))) {
1122 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
1123 AddToWorkList(C3.Val);
1124 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
1127 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1130 SDOperand Sh(0,0), Y(0,0);
1131 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1132 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1133 N0.Val->hasOneUse()) {
1135 } else if (N1.getOpcode() == ISD::SHL &&
1136 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
1140 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
1141 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
1144 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1145 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1146 isa<ConstantSDNode>(N0.getOperand(1))) {
1147 return DAG.getNode(ISD::ADD, VT,
1148 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
1149 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
1153 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
1160 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
1161 SDOperand N0 = N->getOperand(0);
1162 SDOperand N1 = N->getOperand(1);
1163 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1164 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1165 MVT::ValueType VT = N->getValueType(0);
1168 if (MVT::isVector(VT)) {
1169 SDOperand FoldedVOp = SimplifyVBinOp(N);
1170 if (FoldedVOp.Val) return FoldedVOp;
1173 // fold (sdiv c1, c2) -> c1/c2
1174 if (N0C && N1C && !N1C->isNullValue())
1175 return DAG.getNode(ISD::SDIV, VT, N0, N1);
1176 // fold (sdiv X, 1) -> X
1177 if (N1C && N1C->getSignExtended() == 1LL)
1179 // fold (sdiv X, -1) -> 0-X
1180 if (N1C && N1C->isAllOnesValue())
1181 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1182 // If we know the sign bits of both operands are zero, strength reduce to a
1183 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1184 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1185 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1186 DAG.MaskedValueIsZero(N0, SignBit))
1187 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
1188 // fold (sdiv X, pow2) -> simple ops after legalize
1189 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
1190 (isPowerOf2_64(N1C->getSignExtended()) ||
1191 isPowerOf2_64(-N1C->getSignExtended()))) {
1192 // If dividing by powers of two is cheap, then don't perform the following
1194 if (TLI.isPow2DivCheap())
1196 int64_t pow2 = N1C->getSignExtended();
1197 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1198 unsigned lg2 = Log2_64(abs2);
1199 // Splat the sign bit into the register
1200 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
1201 DAG.getConstant(MVT::getSizeInBits(VT)-1,
1202 TLI.getShiftAmountTy()));
1203 AddToWorkList(SGN.Val);
1204 // Add (N0 < 0) ? abs2 - 1 : 0;
1205 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
1206 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
1207 TLI.getShiftAmountTy()));
1208 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
1209 AddToWorkList(SRL.Val);
1210 AddToWorkList(ADD.Val); // Divide by pow2
1211 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
1212 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
1213 // If we're dividing by a positive value, we're done. Otherwise, we must
1214 // negate the result.
1217 AddToWorkList(SRA.Val);
1218 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
1220 // if integer divide is expensive and we satisfy the requirements, emit an
1221 // alternate sequence.
1222 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
1223 !TLI.isIntDivCheap()) {
1224 SDOperand Op = BuildSDIV(N);
1225 if (Op.Val) return Op;
1229 if (N0.getOpcode() == ISD::UNDEF)
1230 return DAG.getConstant(0, VT);
1231 // X / undef -> undef
1232 if (N1.getOpcode() == ISD::UNDEF)
1238 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
1239 SDOperand N0 = N->getOperand(0);
1240 SDOperand N1 = N->getOperand(1);
1241 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1242 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1243 MVT::ValueType VT = N->getValueType(0);
1246 if (MVT::isVector(VT)) {
1247 SDOperand FoldedVOp = SimplifyVBinOp(N);
1248 if (FoldedVOp.Val) return FoldedVOp;
1251 // fold (udiv c1, c2) -> c1/c2
1252 if (N0C && N1C && !N1C->isNullValue())
1253 return DAG.getNode(ISD::UDIV, VT, N0, N1);
1254 // fold (udiv x, (1 << c)) -> x >>u c
1255 if (N1C && isPowerOf2_64(N1C->getValue()))
1256 return DAG.getNode(ISD::SRL, VT, N0,
1257 DAG.getConstant(Log2_64(N1C->getValue()),
1258 TLI.getShiftAmountTy()));
1259 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1260 if (N1.getOpcode() == ISD::SHL) {
1261 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1262 if (isPowerOf2_64(SHC->getValue())) {
1263 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
1264 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
1265 DAG.getConstant(Log2_64(SHC->getValue()),
1267 AddToWorkList(Add.Val);
1268 return DAG.getNode(ISD::SRL, VT, N0, Add);
1272 // fold (udiv x, c) -> alternate
1273 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1274 SDOperand Op = BuildUDIV(N);
1275 if (Op.Val) return Op;
1279 if (N0.getOpcode() == ISD::UNDEF)
1280 return DAG.getConstant(0, VT);
1281 // X / undef -> undef
1282 if (N1.getOpcode() == ISD::UNDEF)
1288 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1289 SDOperand N0 = N->getOperand(0);
1290 SDOperand N1 = N->getOperand(1);
1291 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1292 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1293 MVT::ValueType VT = N->getValueType(0);
1295 // fold (srem c1, c2) -> c1%c2
1296 if (N0C && N1C && !N1C->isNullValue())
1297 return DAG.getNode(ISD::SREM, VT, N0, N1);
1298 // If we know the sign bits of both operands are zero, strength reduce to a
1299 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1300 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1301 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1302 DAG.MaskedValueIsZero(N0, SignBit))
1303 return DAG.getNode(ISD::UREM, VT, N0, N1);
1305 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1306 // the remainder operation.
1307 if (N1C && !N1C->isNullValue()) {
1308 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1309 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1310 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1311 AddToWorkList(Div.Val);
1312 AddToWorkList(Mul.Val);
1317 if (N0.getOpcode() == ISD::UNDEF)
1318 return DAG.getConstant(0, VT);
1319 // X % undef -> undef
1320 if (N1.getOpcode() == ISD::UNDEF)
1326 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1327 SDOperand N0 = N->getOperand(0);
1328 SDOperand N1 = N->getOperand(1);
1329 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1330 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1331 MVT::ValueType VT = N->getValueType(0);
1333 // fold (urem c1, c2) -> c1%c2
1334 if (N0C && N1C && !N1C->isNullValue())
1335 return DAG.getNode(ISD::UREM, VT, N0, N1);
1336 // fold (urem x, pow2) -> (and x, pow2-1)
1337 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1338 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1339 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1340 if (N1.getOpcode() == ISD::SHL) {
1341 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1342 if (isPowerOf2_64(SHC->getValue())) {
1343 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1344 AddToWorkList(Add.Val);
1345 return DAG.getNode(ISD::AND, VT, N0, Add);
1350 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1351 // the remainder operation.
1352 if (N1C && !N1C->isNullValue()) {
1353 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1354 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1355 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1356 AddToWorkList(Div.Val);
1357 AddToWorkList(Mul.Val);
1362 if (N0.getOpcode() == ISD::UNDEF)
1363 return DAG.getConstant(0, VT);
1364 // X % undef -> undef
1365 if (N1.getOpcode() == ISD::UNDEF)
1371 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1372 SDOperand N0 = N->getOperand(0);
1373 SDOperand N1 = N->getOperand(1);
1374 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1375 MVT::ValueType VT = N->getValueType(0);
1377 // fold (mulhs x, 0) -> 0
1378 if (N1C && N1C->isNullValue())
1380 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1381 if (N1C && N1C->getValue() == 1)
1382 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1383 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1384 TLI.getShiftAmountTy()));
1385 // fold (mulhs x, undef) -> 0
1386 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1387 return DAG.getConstant(0, VT);
1392 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1393 SDOperand N0 = N->getOperand(0);
1394 SDOperand N1 = N->getOperand(1);
1395 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1396 MVT::ValueType VT = N->getValueType(0);
1398 // fold (mulhu x, 0) -> 0
1399 if (N1C && N1C->isNullValue())
1401 // fold (mulhu x, 1) -> 0
1402 if (N1C && N1C->getValue() == 1)
1403 return DAG.getConstant(0, N0.getValueType());
1404 // fold (mulhu x, undef) -> 0
1405 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1406 return DAG.getConstant(0, VT);
1411 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1412 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1413 /// that are being performed. Return true if a simplification was made.
1415 bool DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N,
1416 unsigned LoOp, unsigned HiOp) {
1417 std::vector<SDNode*> NowDead;
1419 // If the high half is not needed, just compute the low half.
1420 if (!N->hasAnyUseOfValue(1) &&
1422 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1423 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0),
1424 DAG.getNode(LoOp, N->getValueType(0),
1426 N->getNumOperands()),
1431 // If the low half is not needed, just compute the high half.
1432 if (!N->hasAnyUseOfValue(0) &&
1434 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1435 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1),
1436 DAG.getNode(HiOp, N->getValueType(1),
1438 N->getNumOperands()),
1443 // If the two computed results can be siplified separately, separate them.
1444 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0),
1445 N->op_begin(), N->getNumOperands());
1446 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1),
1447 N->op_begin(), N->getNumOperands());
1448 unsigned LoExists = !Lo.use_empty();
1449 unsigned HiExists = !Hi.use_empty();
1450 SDOperand LoOpt = Lo;
1451 SDOperand HiOpt = Hi;
1452 if (!LoExists || !HiExists) {
1453 SDOperand Pair = DAG.getNode(ISD::BUILD_PAIR, MVT::Other, Lo, Hi);
1454 assert(Pair.use_empty() && "Pair with type MVT::Other already exists!");
1455 LoOpt = combine(Lo.Val);
1456 HiOpt = combine(Hi.Val);
1458 LoOpt = Pair.getOperand(0);
1460 HiOpt = Pair.getOperand(1);
1461 DAG.DeleteNode(Pair.Val);
1463 if ((LoExists || LoOpt != Lo) &&
1464 (HiExists || HiOpt != Hi) &&
1465 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()) &&
1466 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) {
1467 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), LoOpt, NowDead);
1468 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), HiOpt, NowDead);
1475 SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1477 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
1483 SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1485 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
1491 SDOperand DAGCombiner::visitSDIVREM(SDNode *N) {
1493 if (SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM))
1499 SDOperand DAGCombiner::visitUDIVREM(SDNode *N) {
1501 if (SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM))
1507 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1508 /// two operands of the same opcode, try to simplify it.
1509 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1510 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1511 MVT::ValueType VT = N0.getValueType();
1512 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1514 // For each of OP in AND/OR/XOR:
1515 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1516 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1517 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1518 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1519 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1520 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1521 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1522 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1523 N0.getOperand(0).getValueType(),
1524 N0.getOperand(0), N1.getOperand(0));
1525 AddToWorkList(ORNode.Val);
1526 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1529 // For each of OP in SHL/SRL/SRA/AND...
1530 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1531 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1532 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1533 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1534 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1535 N0.getOperand(1) == N1.getOperand(1)) {
1536 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1537 N0.getOperand(0).getValueType(),
1538 N0.getOperand(0), N1.getOperand(0));
1539 AddToWorkList(ORNode.Val);
1540 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1546 SDOperand DAGCombiner::visitAND(SDNode *N) {
1547 SDOperand N0 = N->getOperand(0);
1548 SDOperand N1 = N->getOperand(1);
1549 SDOperand LL, LR, RL, RR, CC0, CC1;
1550 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1551 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1552 MVT::ValueType VT = N1.getValueType();
1555 if (MVT::isVector(VT)) {
1556 SDOperand FoldedVOp = SimplifyVBinOp(N);
1557 if (FoldedVOp.Val) return FoldedVOp;
1560 // fold (and x, undef) -> 0
1561 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1562 return DAG.getConstant(0, VT);
1563 // fold (and c1, c2) -> c1&c2
1565 return DAG.getNode(ISD::AND, VT, N0, N1);
1566 // canonicalize constant to RHS
1568 return DAG.getNode(ISD::AND, VT, N1, N0);
1569 // fold (and x, -1) -> x
1570 if (N1C && N1C->isAllOnesValue())
1572 // if (and x, c) is known to be zero, return 0
1573 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1574 return DAG.getConstant(0, VT);
1576 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1579 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1580 if (N1C && N0.getOpcode() == ISD::OR)
1581 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1582 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1584 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1585 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1586 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1587 if (DAG.MaskedValueIsZero(N0.getOperand(0),
1588 ~N1C->getValue() & InMask)) {
1589 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1592 // Replace uses of the AND with uses of the Zero extend node.
1595 // We actually want to replace all uses of the any_extend with the
1596 // zero_extend, to avoid duplicating things. This will later cause this
1597 // AND to be folded.
1598 CombineTo(N0.Val, Zext);
1599 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1602 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1603 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1604 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1605 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1607 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1608 MVT::isInteger(LL.getValueType())) {
1609 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1610 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1611 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1612 AddToWorkList(ORNode.Val);
1613 return DAG.getSetCC(VT, ORNode, LR, Op1);
1615 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1616 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1617 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1618 AddToWorkList(ANDNode.Val);
1619 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1621 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1622 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1623 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1624 AddToWorkList(ORNode.Val);
1625 return DAG.getSetCC(VT, ORNode, LR, Op1);
1628 // canonicalize equivalent to ll == rl
1629 if (LL == RR && LR == RL) {
1630 Op1 = ISD::getSetCCSwappedOperands(Op1);
1633 if (LL == RL && LR == RR) {
1634 bool isInteger = MVT::isInteger(LL.getValueType());
1635 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1636 if (Result != ISD::SETCC_INVALID)
1637 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1641 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1642 if (N0.getOpcode() == N1.getOpcode()) {
1643 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1644 if (Tmp.Val) return Tmp;
1647 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1648 // fold (and (sra)) -> (and (srl)) when possible.
1649 if (!MVT::isVector(VT) &&
1650 SimplifyDemandedBits(SDOperand(N, 0)))
1651 return SDOperand(N, 0);
1652 // fold (zext_inreg (extload x)) -> (zextload x)
1653 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
1654 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1655 MVT::ValueType EVT = LN0->getLoadedVT();
1656 // If we zero all the possible extended bits, then we can turn this into
1657 // a zextload if we are running before legalize or the operation is legal.
1658 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1659 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1660 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1661 LN0->getBasePtr(), LN0->getSrcValue(),
1662 LN0->getSrcValueOffset(), EVT,
1664 LN0->getAlignment());
1666 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1667 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1670 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1671 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
1673 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1674 MVT::ValueType EVT = LN0->getLoadedVT();
1675 // If we zero all the possible extended bits, then we can turn this into
1676 // a zextload if we are running before legalize or the operation is legal.
1677 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1678 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1679 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1680 LN0->getBasePtr(), LN0->getSrcValue(),
1681 LN0->getSrcValueOffset(), EVT,
1683 LN0->getAlignment());
1685 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1686 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1690 // fold (and (load x), 255) -> (zextload x, i8)
1691 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1692 if (N1C && N0.getOpcode() == ISD::LOAD) {
1693 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1694 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1695 LN0->getAddressingMode() == ISD::UNINDEXED &&
1697 MVT::ValueType EVT, LoadedVT;
1698 if (N1C->getValue() == 255)
1700 else if (N1C->getValue() == 65535)
1702 else if (N1C->getValue() == ~0U)
1707 LoadedVT = LN0->getLoadedVT();
1708 if (EVT != MVT::Other && LoadedVT > EVT &&
1709 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1710 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1711 // For big endian targets, we need to add an offset to the pointer to
1712 // load the correct bytes. For little endian systems, we merely need to
1713 // read fewer bytes from the same pointer.
1715 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1716 SDOperand NewPtr = LN0->getBasePtr();
1717 if (!TLI.isLittleEndian())
1718 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1719 DAG.getConstant(PtrOff, PtrType));
1720 AddToWorkList(NewPtr.Val);
1722 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1723 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
1724 LN0->isVolatile(), LN0->getAlignment());
1726 CombineTo(N0.Val, Load, Load.getValue(1));
1727 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1735 SDOperand DAGCombiner::visitOR(SDNode *N) {
1736 SDOperand N0 = N->getOperand(0);
1737 SDOperand N1 = N->getOperand(1);
1738 SDOperand LL, LR, RL, RR, CC0, CC1;
1739 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1740 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1741 MVT::ValueType VT = N1.getValueType();
1742 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1745 if (MVT::isVector(VT)) {
1746 SDOperand FoldedVOp = SimplifyVBinOp(N);
1747 if (FoldedVOp.Val) return FoldedVOp;
1750 // fold (or x, undef) -> -1
1751 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1752 return DAG.getConstant(~0ULL, VT);
1753 // fold (or c1, c2) -> c1|c2
1755 return DAG.getNode(ISD::OR, VT, N0, N1);
1756 // canonicalize constant to RHS
1758 return DAG.getNode(ISD::OR, VT, N1, N0);
1759 // fold (or x, 0) -> x
1760 if (N1C && N1C->isNullValue())
1762 // fold (or x, -1) -> -1
1763 if (N1C && N1C->isAllOnesValue())
1765 // fold (or x, c) -> c iff (x & ~c) == 0
1767 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1770 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1773 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1774 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1775 isa<ConstantSDNode>(N0.getOperand(1))) {
1776 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1777 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1779 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1781 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1782 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1783 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1784 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1786 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1787 MVT::isInteger(LL.getValueType())) {
1788 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1789 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1790 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1791 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1792 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1793 AddToWorkList(ORNode.Val);
1794 return DAG.getSetCC(VT, ORNode, LR, Op1);
1796 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1797 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1798 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1799 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1800 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1801 AddToWorkList(ANDNode.Val);
1802 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1805 // canonicalize equivalent to ll == rl
1806 if (LL == RR && LR == RL) {
1807 Op1 = ISD::getSetCCSwappedOperands(Op1);
1810 if (LL == RL && LR == RR) {
1811 bool isInteger = MVT::isInteger(LL.getValueType());
1812 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1813 if (Result != ISD::SETCC_INVALID)
1814 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1818 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1819 if (N0.getOpcode() == N1.getOpcode()) {
1820 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1821 if (Tmp.Val) return Tmp;
1824 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1825 if (N0.getOpcode() == ISD::AND &&
1826 N1.getOpcode() == ISD::AND &&
1827 N0.getOperand(1).getOpcode() == ISD::Constant &&
1828 N1.getOperand(1).getOpcode() == ISD::Constant &&
1829 // Don't increase # computations.
1830 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1831 // We can only do this xform if we know that bits from X that are set in C2
1832 // but not in C1 are already zero. Likewise for Y.
1833 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1834 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1836 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1837 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1838 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1839 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1844 // See if this is some rotate idiom.
1845 if (SDNode *Rot = MatchRotate(N0, N1))
1846 return SDOperand(Rot, 0);
1852 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1853 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1854 if (Op.getOpcode() == ISD::AND) {
1855 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1856 Mask = Op.getOperand(1);
1857 Op = Op.getOperand(0);
1863 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1871 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1872 // idioms for rotate, and if the target supports rotation instructions, generate
1874 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1875 // Must be a legal type. Expanded an promoted things won't work with rotates.
1876 MVT::ValueType VT = LHS.getValueType();
1877 if (!TLI.isTypeLegal(VT)) return 0;
1879 // The target must have at least one rotate flavor.
1880 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1881 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1882 if (!HasROTL && !HasROTR) return 0;
1884 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1885 SDOperand LHSShift; // The shift.
1886 SDOperand LHSMask; // AND value if any.
1887 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1888 return 0; // Not part of a rotate.
1890 SDOperand RHSShift; // The shift.
1891 SDOperand RHSMask; // AND value if any.
1892 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1893 return 0; // Not part of a rotate.
1895 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1896 return 0; // Not shifting the same value.
1898 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1899 return 0; // Shifts must disagree.
1901 // Canonicalize shl to left side in a shl/srl pair.
1902 if (RHSShift.getOpcode() == ISD::SHL) {
1903 std::swap(LHS, RHS);
1904 std::swap(LHSShift, RHSShift);
1905 std::swap(LHSMask , RHSMask );
1908 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1909 SDOperand LHSShiftArg = LHSShift.getOperand(0);
1910 SDOperand LHSShiftAmt = LHSShift.getOperand(1);
1911 SDOperand RHSShiftAmt = RHSShift.getOperand(1);
1913 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1914 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1915 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
1916 RHSShiftAmt.getOpcode() == ISD::Constant) {
1917 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
1918 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
1919 if ((LShVal + RShVal) != OpSizeInBits)
1924 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
1926 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
1928 // If there is an AND of either shifted operand, apply it to the result.
1929 if (LHSMask.Val || RHSMask.Val) {
1930 uint64_t Mask = MVT::getIntVTBitMask(VT);
1933 uint64_t RHSBits = (1ULL << LShVal)-1;
1934 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1937 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1938 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1941 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1947 // If there is a mask here, and we have a variable shift, we can't be sure
1948 // that we're masking out the right stuff.
1949 if (LHSMask.Val || RHSMask.Val)
1952 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1953 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1954 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
1955 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
1956 if (ConstantSDNode *SUBC =
1957 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
1958 if (SUBC->getValue() == OpSizeInBits)
1960 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1962 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1966 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1967 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1968 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
1969 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
1970 if (ConstantSDNode *SUBC =
1971 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
1972 if (SUBC->getValue() == OpSizeInBits)
1974 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1976 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1980 // Look for sign/zext/any-extended cases:
1981 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1982 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1983 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
1984 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1985 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1986 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
1987 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
1988 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
1989 if (RExtOp0.getOpcode() == ISD::SUB &&
1990 RExtOp0.getOperand(1) == LExtOp0) {
1991 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1993 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1994 // (rotl x, (sub 32, y))
1995 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
1996 if (SUBC->getValue() == OpSizeInBits) {
1998 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2000 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
2003 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2004 RExtOp0 == LExtOp0.getOperand(1)) {
2005 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2007 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2008 // (rotr x, (sub 32, y))
2009 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2010 if (SUBC->getValue() == OpSizeInBits) {
2012 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
2014 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2024 SDOperand DAGCombiner::visitXOR(SDNode *N) {
2025 SDOperand N0 = N->getOperand(0);
2026 SDOperand N1 = N->getOperand(1);
2027 SDOperand LHS, RHS, CC;
2028 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2029 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2030 MVT::ValueType VT = N0.getValueType();
2033 if (MVT::isVector(VT)) {
2034 SDOperand FoldedVOp = SimplifyVBinOp(N);
2035 if (FoldedVOp.Val) return FoldedVOp;
2038 // fold (xor x, undef) -> undef
2039 if (N0.getOpcode() == ISD::UNDEF)
2041 if (N1.getOpcode() == ISD::UNDEF)
2043 // fold (xor c1, c2) -> c1^c2
2045 return DAG.getNode(ISD::XOR, VT, N0, N1);
2046 // canonicalize constant to RHS
2048 return DAG.getNode(ISD::XOR, VT, N1, N0);
2049 // fold (xor x, 0) -> x
2050 if (N1C && N1C->isNullValue())
2053 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
2056 // fold !(x cc y) -> (x !cc y)
2057 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2058 bool isInt = MVT::isInteger(LHS.getValueType());
2059 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2061 if (N0.getOpcode() == ISD::SETCC)
2062 return DAG.getSetCC(VT, LHS, RHS, NotCC);
2063 if (N0.getOpcode() == ISD::SELECT_CC)
2064 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
2065 assert(0 && "Unhandled SetCC Equivalent!");
2068 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2069 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2070 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2071 SDOperand V = N0.getOperand(0);
2072 V = DAG.getNode(ISD::XOR, V.getValueType(), V,
2073 DAG.getConstant(1, V.getValueType()));
2074 AddToWorkList(V.Val);
2075 return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
2078 // fold !(x or y) -> (!x and !y) iff x or y are setcc
2079 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
2080 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2081 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2082 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2083 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2084 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2085 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2086 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2087 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2090 // fold !(x or y) -> (!x and !y) iff x or y are constants
2091 if (N1C && N1C->isAllOnesValue() &&
2092 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2093 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2094 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2095 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2096 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2097 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2098 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2099 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2102 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
2103 if (N1C && N0.getOpcode() == ISD::XOR) {
2104 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2105 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2107 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
2108 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
2110 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
2111 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
2113 // fold (xor x, x) -> 0
2115 if (!MVT::isVector(VT)) {
2116 return DAG.getConstant(0, VT);
2117 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
2118 // Produce a vector of zeros.
2119 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
2120 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
2121 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2125 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2126 if (N0.getOpcode() == N1.getOpcode()) {
2127 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2128 if (Tmp.Val) return Tmp;
2131 // Simplify the expression using non-local knowledge.
2132 if (!MVT::isVector(VT) &&
2133 SimplifyDemandedBits(SDOperand(N, 0)))
2134 return SDOperand(N, 0);
2139 SDOperand DAGCombiner::visitSHL(SDNode *N) {
2140 SDOperand N0 = N->getOperand(0);
2141 SDOperand N1 = N->getOperand(1);
2142 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2143 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2144 MVT::ValueType VT = N0.getValueType();
2145 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2147 // fold (shl c1, c2) -> c1<<c2
2149 return DAG.getNode(ISD::SHL, VT, N0, N1);
2150 // fold (shl 0, x) -> 0
2151 if (N0C && N0C->isNullValue())
2153 // fold (shl x, c >= size(x)) -> undef
2154 if (N1C && N1C->getValue() >= OpSizeInBits)
2155 return DAG.getNode(ISD::UNDEF, VT);
2156 // fold (shl x, 0) -> x
2157 if (N1C && N1C->isNullValue())
2159 // if (shl x, c) is known to be zero, return 0
2160 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
2161 return DAG.getConstant(0, VT);
2162 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2163 return SDOperand(N, 0);
2164 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
2165 if (N1C && N0.getOpcode() == ISD::SHL &&
2166 N0.getOperand(1).getOpcode() == ISD::Constant) {
2167 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2168 uint64_t c2 = N1C->getValue();
2169 if (c1 + c2 > OpSizeInBits)
2170 return DAG.getConstant(0, VT);
2171 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
2172 DAG.getConstant(c1 + c2, N1.getValueType()));
2174 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
2175 // (srl (and x, -1 << c1), c1-c2)
2176 if (N1C && N0.getOpcode() == ISD::SRL &&
2177 N0.getOperand(1).getOpcode() == ISD::Constant) {
2178 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2179 uint64_t c2 = N1C->getValue();
2180 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2181 DAG.getConstant(~0ULL << c1, VT));
2183 return DAG.getNode(ISD::SHL, VT, Mask,
2184 DAG.getConstant(c2-c1, N1.getValueType()));
2186 return DAG.getNode(ISD::SRL, VT, Mask,
2187 DAG.getConstant(c1-c2, N1.getValueType()));
2189 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
2190 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2191 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2192 DAG.getConstant(~0ULL << N1C->getValue(), VT));
2196 SDOperand DAGCombiner::visitSRA(SDNode *N) {
2197 SDOperand N0 = N->getOperand(0);
2198 SDOperand N1 = N->getOperand(1);
2199 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2200 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2201 MVT::ValueType VT = N0.getValueType();
2203 // fold (sra c1, c2) -> c1>>c2
2205 return DAG.getNode(ISD::SRA, VT, N0, N1);
2206 // fold (sra 0, x) -> 0
2207 if (N0C && N0C->isNullValue())
2209 // fold (sra -1, x) -> -1
2210 if (N0C && N0C->isAllOnesValue())
2212 // fold (sra x, c >= size(x)) -> undef
2213 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
2214 return DAG.getNode(ISD::UNDEF, VT);
2215 // fold (sra x, 0) -> x
2216 if (N1C && N1C->isNullValue())
2218 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2220 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2221 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
2224 default: EVT = MVT::Other; break;
2225 case 1: EVT = MVT::i1; break;
2226 case 8: EVT = MVT::i8; break;
2227 case 16: EVT = MVT::i16; break;
2228 case 32: EVT = MVT::i32; break;
2230 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
2231 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
2232 DAG.getValueType(EVT));
2235 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
2236 if (N1C && N0.getOpcode() == ISD::SRA) {
2237 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2238 unsigned Sum = N1C->getValue() + C1->getValue();
2239 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
2240 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
2241 DAG.getConstant(Sum, N1C->getValueType(0)));
2245 // Simplify, based on bits shifted out of the LHS.
2246 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2247 return SDOperand(N, 0);
2250 // If the sign bit is known to be zero, switch this to a SRL.
2251 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
2252 return DAG.getNode(ISD::SRL, VT, N0, N1);
2256 SDOperand DAGCombiner::visitSRL(SDNode *N) {
2257 SDOperand N0 = N->getOperand(0);
2258 SDOperand N1 = N->getOperand(1);
2259 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2260 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2261 MVT::ValueType VT = N0.getValueType();
2262 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2264 // fold (srl c1, c2) -> c1 >>u c2
2266 return DAG.getNode(ISD::SRL, VT, N0, N1);
2267 // fold (srl 0, x) -> 0
2268 if (N0C && N0C->isNullValue())
2270 // fold (srl x, c >= size(x)) -> undef
2271 if (N1C && N1C->getValue() >= OpSizeInBits)
2272 return DAG.getNode(ISD::UNDEF, VT);
2273 // fold (srl x, 0) -> x
2274 if (N1C && N1C->isNullValue())
2276 // if (srl x, c) is known to be zero, return 0
2277 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
2278 return DAG.getConstant(0, VT);
2280 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
2281 if (N1C && N0.getOpcode() == ISD::SRL &&
2282 N0.getOperand(1).getOpcode() == ISD::Constant) {
2283 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2284 uint64_t c2 = N1C->getValue();
2285 if (c1 + c2 > OpSizeInBits)
2286 return DAG.getConstant(0, VT);
2287 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
2288 DAG.getConstant(c1 + c2, N1.getValueType()));
2291 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2292 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2293 // Shifting in all undef bits?
2294 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
2295 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
2296 return DAG.getNode(ISD::UNDEF, VT);
2298 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
2299 AddToWorkList(SmallShift.Val);
2300 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
2303 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2304 // bit, which is unmodified by sra.
2305 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
2306 if (N0.getOpcode() == ISD::SRA)
2307 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
2310 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2311 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2312 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
2313 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
2314 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2316 // If any of the input bits are KnownOne, then the input couldn't be all
2317 // zeros, thus the result of the srl will always be zero.
2318 if (KnownOne) return DAG.getConstant(0, VT);
2320 // If all of the bits input the to ctlz node are known to be zero, then
2321 // the result of the ctlz is "32" and the result of the shift is one.
2322 uint64_t UnknownBits = ~KnownZero & Mask;
2323 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2325 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2326 if ((UnknownBits & (UnknownBits-1)) == 0) {
2327 // Okay, we know that only that the single bit specified by UnknownBits
2328 // could be set on input to the CTLZ node. If this bit is set, the SRL
2329 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2330 // to an SRL,XOR pair, which is likely to simplify more.
2331 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
2332 SDOperand Op = N0.getOperand(0);
2334 Op = DAG.getNode(ISD::SRL, VT, Op,
2335 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
2336 AddToWorkList(Op.Val);
2338 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
2342 // fold operands of srl based on knowledge that the low bits are not
2344 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2345 return SDOperand(N, 0);
2350 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
2351 SDOperand N0 = N->getOperand(0);
2352 MVT::ValueType VT = N->getValueType(0);
2354 // fold (ctlz c1) -> c2
2355 if (isa<ConstantSDNode>(N0))
2356 return DAG.getNode(ISD::CTLZ, VT, N0);
2360 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
2361 SDOperand N0 = N->getOperand(0);
2362 MVT::ValueType VT = N->getValueType(0);
2364 // fold (cttz c1) -> c2
2365 if (isa<ConstantSDNode>(N0))
2366 return DAG.getNode(ISD::CTTZ, VT, N0);
2370 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
2371 SDOperand N0 = N->getOperand(0);
2372 MVT::ValueType VT = N->getValueType(0);
2374 // fold (ctpop c1) -> c2
2375 if (isa<ConstantSDNode>(N0))
2376 return DAG.getNode(ISD::CTPOP, VT, N0);
2380 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
2381 SDOperand N0 = N->getOperand(0);
2382 SDOperand N1 = N->getOperand(1);
2383 SDOperand N2 = N->getOperand(2);
2384 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2385 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2386 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2387 MVT::ValueType VT = N->getValueType(0);
2388 MVT::ValueType VT0 = N0.getValueType();
2390 // fold select C, X, X -> X
2393 // fold select true, X, Y -> X
2394 if (N0C && !N0C->isNullValue())
2396 // fold select false, X, Y -> Y
2397 if (N0C && N0C->isNullValue())
2399 // fold select C, 1, X -> C | X
2400 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
2401 return DAG.getNode(ISD::OR, VT, N0, N2);
2402 // fold select C, 0, 1 -> ~C
2403 if (MVT::isInteger(VT) && MVT::isInteger(VT0) &&
2404 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) {
2405 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
2408 AddToWorkList(XORNode.Val);
2409 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0))
2410 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
2411 return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
2413 // fold select C, 0, X -> ~C & X
2414 if (VT == VT0 && N1C && N1C->isNullValue()) {
2415 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2416 AddToWorkList(XORNode.Val);
2417 return DAG.getNode(ISD::AND, VT, XORNode, N2);
2419 // fold select C, X, 1 -> ~C | X
2420 if (VT == VT0 && N2C && N2C->getValue() == 1) {
2421 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2422 AddToWorkList(XORNode.Val);
2423 return DAG.getNode(ISD::OR, VT, XORNode, N1);
2425 // fold select C, X, 0 -> C & X
2426 // FIXME: this should check for C type == X type, not i1?
2427 if (MVT::i1 == VT && N2C && N2C->isNullValue())
2428 return DAG.getNode(ISD::AND, VT, N0, N1);
2429 // fold X ? X : Y --> X ? 1 : Y --> X | Y
2430 if (MVT::i1 == VT && N0 == N1)
2431 return DAG.getNode(ISD::OR, VT, N0, N2);
2432 // fold X ? Y : X --> X ? Y : 0 --> X & Y
2433 if (MVT::i1 == VT && N0 == N2)
2434 return DAG.getNode(ISD::AND, VT, N0, N1);
2436 // If we can fold this based on the true/false value, do so.
2437 if (SimplifySelectOps(N, N1, N2))
2438 return SDOperand(N, 0); // Don't revisit N.
2440 // fold selects based on a setcc into other things, such as min/max/abs
2441 if (N0.getOpcode() == ISD::SETCC)
2443 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2444 // having to say they don't support SELECT_CC on every type the DAG knows
2445 // about, since there is no way to mark an opcode illegal at all value types
2446 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
2447 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
2448 N1, N2, N0.getOperand(2));
2450 return SimplifySelect(N0, N1, N2);
2454 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
2455 SDOperand N0 = N->getOperand(0);
2456 SDOperand N1 = N->getOperand(1);
2457 SDOperand N2 = N->getOperand(2);
2458 SDOperand N3 = N->getOperand(3);
2459 SDOperand N4 = N->getOperand(4);
2460 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2462 // fold select_cc lhs, rhs, x, x, cc -> x
2466 // Determine if the condition we're dealing with is constant
2467 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2468 if (SCC.Val) AddToWorkList(SCC.Val);
2470 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
2471 if (SCCC->getValue())
2472 return N2; // cond always true -> true val
2474 return N3; // cond always false -> false val
2477 // Fold to a simpler select_cc
2478 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2479 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
2480 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2483 // If we can fold this based on the true/false value, do so.
2484 if (SimplifySelectOps(N, N2, N3))
2485 return SDOperand(N, 0); // Don't revisit N.
2487 // fold select_cc into other things, such as min/max/abs
2488 return SimplifySelectCC(N0, N1, N2, N3, CC);
2491 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
2492 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2493 cast<CondCodeSDNode>(N->getOperand(2))->get());
2496 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2497 SDOperand N0 = N->getOperand(0);
2498 MVT::ValueType VT = N->getValueType(0);
2500 // fold (sext c1) -> c1
2501 if (isa<ConstantSDNode>(N0))
2502 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2504 // fold (sext (sext x)) -> (sext x)
2505 // fold (sext (aext x)) -> (sext x)
2506 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2507 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2509 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2510 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2511 if (N0.getOpcode() == ISD::TRUNCATE) {
2512 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2513 if (NarrowLoad.Val) {
2514 if (NarrowLoad.Val != N0.Val)
2515 CombineTo(N0.Val, NarrowLoad);
2516 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
2520 // See if the value being truncated is already sign extended. If so, just
2521 // eliminate the trunc/sext pair.
2522 if (N0.getOpcode() == ISD::TRUNCATE) {
2523 SDOperand Op = N0.getOperand(0);
2524 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2525 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2526 unsigned DestBits = MVT::getSizeInBits(VT);
2527 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2529 if (OpBits == DestBits) {
2530 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2531 // bits, it is already ready.
2532 if (NumSignBits > DestBits-MidBits)
2534 } else if (OpBits < DestBits) {
2535 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2536 // bits, just sext from i32.
2537 if (NumSignBits > OpBits-MidBits)
2538 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2540 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2541 // bits, just truncate to i32.
2542 if (NumSignBits > OpBits-MidBits)
2543 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2546 // fold (sext (truncate x)) -> (sextinreg x).
2547 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2548 N0.getValueType())) {
2549 if (Op.getValueType() < VT)
2550 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2551 else if (Op.getValueType() > VT)
2552 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2553 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2554 DAG.getValueType(N0.getValueType()));
2558 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2559 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2560 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2561 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2562 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2563 LN0->getBasePtr(), LN0->getSrcValue(),
2564 LN0->getSrcValueOffset(),
2567 LN0->getAlignment());
2568 CombineTo(N, ExtLoad);
2569 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2570 ExtLoad.getValue(1));
2571 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2574 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2575 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2576 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2577 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2578 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2579 MVT::ValueType EVT = LN0->getLoadedVT();
2580 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2581 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2582 LN0->getBasePtr(), LN0->getSrcValue(),
2583 LN0->getSrcValueOffset(), EVT,
2585 LN0->getAlignment());
2586 CombineTo(N, ExtLoad);
2587 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2588 ExtLoad.getValue(1));
2589 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2593 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
2594 if (N0.getOpcode() == ISD::SETCC) {
2596 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2597 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
2598 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2599 if (SCC.Val) return SCC;
2605 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2606 SDOperand N0 = N->getOperand(0);
2607 MVT::ValueType VT = N->getValueType(0);
2609 // fold (zext c1) -> c1
2610 if (isa<ConstantSDNode>(N0))
2611 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2612 // fold (zext (zext x)) -> (zext x)
2613 // fold (zext (aext x)) -> (zext x)
2614 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2615 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2617 // fold (zext (truncate (load x))) -> (zext (smaller load x))
2618 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
2619 if (N0.getOpcode() == ISD::TRUNCATE) {
2620 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2621 if (NarrowLoad.Val) {
2622 if (NarrowLoad.Val != N0.Val)
2623 CombineTo(N0.Val, NarrowLoad);
2624 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
2628 // fold (zext (truncate x)) -> (and x, mask)
2629 if (N0.getOpcode() == ISD::TRUNCATE &&
2630 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2631 SDOperand Op = N0.getOperand(0);
2632 if (Op.getValueType() < VT) {
2633 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2634 } else if (Op.getValueType() > VT) {
2635 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2637 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2640 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2641 if (N0.getOpcode() == ISD::AND &&
2642 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2643 N0.getOperand(1).getOpcode() == ISD::Constant) {
2644 SDOperand X = N0.getOperand(0).getOperand(0);
2645 if (X.getValueType() < VT) {
2646 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2647 } else if (X.getValueType() > VT) {
2648 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2650 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2651 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2654 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2655 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2656 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2657 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2658 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2659 LN0->getBasePtr(), LN0->getSrcValue(),
2660 LN0->getSrcValueOffset(),
2663 LN0->getAlignment());
2664 CombineTo(N, ExtLoad);
2665 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2666 ExtLoad.getValue(1));
2667 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2670 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2671 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2672 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2673 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2674 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2675 MVT::ValueType EVT = LN0->getLoadedVT();
2676 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2677 LN0->getBasePtr(), LN0->getSrcValue(),
2678 LN0->getSrcValueOffset(), EVT,
2680 LN0->getAlignment());
2681 CombineTo(N, ExtLoad);
2682 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2683 ExtLoad.getValue(1));
2684 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2687 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2688 if (N0.getOpcode() == ISD::SETCC) {
2690 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2691 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2692 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2693 if (SCC.Val) return SCC;
2699 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2700 SDOperand N0 = N->getOperand(0);
2701 MVT::ValueType VT = N->getValueType(0);
2703 // fold (aext c1) -> c1
2704 if (isa<ConstantSDNode>(N0))
2705 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2706 // fold (aext (aext x)) -> (aext x)
2707 // fold (aext (zext x)) -> (zext x)
2708 // fold (aext (sext x)) -> (sext x)
2709 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2710 N0.getOpcode() == ISD::ZERO_EXTEND ||
2711 N0.getOpcode() == ISD::SIGN_EXTEND)
2712 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2714 // fold (aext (truncate (load x))) -> (aext (smaller load x))
2715 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
2716 if (N0.getOpcode() == ISD::TRUNCATE) {
2717 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2718 if (NarrowLoad.Val) {
2719 if (NarrowLoad.Val != N0.Val)
2720 CombineTo(N0.Val, NarrowLoad);
2721 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
2725 // fold (aext (truncate x))
2726 if (N0.getOpcode() == ISD::TRUNCATE) {
2727 SDOperand TruncOp = N0.getOperand(0);
2728 if (TruncOp.getValueType() == VT)
2729 return TruncOp; // x iff x size == zext size.
2730 if (TruncOp.getValueType() > VT)
2731 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2732 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2735 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2736 if (N0.getOpcode() == ISD::AND &&
2737 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2738 N0.getOperand(1).getOpcode() == ISD::Constant) {
2739 SDOperand X = N0.getOperand(0).getOperand(0);
2740 if (X.getValueType() < VT) {
2741 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2742 } else if (X.getValueType() > VT) {
2743 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2745 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2746 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2749 // fold (aext (load x)) -> (aext (truncate (extload x)))
2750 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2751 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2752 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2753 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2754 LN0->getBasePtr(), LN0->getSrcValue(),
2755 LN0->getSrcValueOffset(),
2758 LN0->getAlignment());
2759 CombineTo(N, ExtLoad);
2760 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2761 ExtLoad.getValue(1));
2762 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2765 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2766 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2767 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2768 if (N0.getOpcode() == ISD::LOAD &&
2769 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2771 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2772 MVT::ValueType EVT = LN0->getLoadedVT();
2773 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2774 LN0->getChain(), LN0->getBasePtr(),
2776 LN0->getSrcValueOffset(), EVT,
2778 LN0->getAlignment());
2779 CombineTo(N, ExtLoad);
2780 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2781 ExtLoad.getValue(1));
2782 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2785 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2786 if (N0.getOpcode() == ISD::SETCC) {
2788 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2789 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2790 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2798 /// GetDemandedBits - See if the specified operand can be simplified with the
2799 /// knowledge that only the bits specified by Mask are used. If so, return the
2800 /// simpler operand, otherwise return a null SDOperand.
2801 SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) {
2802 switch (V.getOpcode()) {
2806 // If the LHS or RHS don't contribute bits to the or, drop them.
2807 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
2808 return V.getOperand(1);
2809 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
2810 return V.getOperand(0);
2816 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
2817 /// bits and then truncated to a narrower type and where N is a multiple
2818 /// of number of bits of the narrower type, transform it to a narrower load
2819 /// from address + N / num of bits of new type. If the result is to be
2820 /// extended, also fold the extension to form a extending load.
2821 SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
2822 unsigned Opc = N->getOpcode();
2823 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2824 SDOperand N0 = N->getOperand(0);
2825 MVT::ValueType VT = N->getValueType(0);
2826 MVT::ValueType EVT = N->getValueType(0);
2828 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
2830 if (Opc == ISD::SIGN_EXTEND_INREG) {
2831 ExtType = ISD::SEXTLOAD;
2832 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2833 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
2837 unsigned EVTBits = MVT::getSizeInBits(EVT);
2839 bool CombineSRL = false;
2840 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
2841 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2842 ShAmt = N01->getValue();
2843 // Is the shift amount a multiple of size of VT?
2844 if ((ShAmt & (EVTBits-1)) == 0) {
2845 N0 = N0.getOperand(0);
2846 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
2853 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2854 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
2855 // zero extended form: by shrinking the load, we lose track of the fact
2856 // that it is already zero extended.
2857 // FIXME: This should be reevaluated.
2859 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
2860 "Cannot truncate to larger type!");
2861 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2862 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2863 // For big endian targets, we need to adjust the offset to the pointer to
2864 // load the correct bytes.
2865 if (!TLI.isLittleEndian())
2866 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits;
2867 uint64_t PtrOff = ShAmt / 8;
2868 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2869 DAG.getConstant(PtrOff, PtrType));
2870 AddToWorkList(NewPtr.Val);
2871 SDOperand Load = (ExtType == ISD::NON_EXTLOAD)
2872 ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
2873 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2874 LN0->isVolatile(), LN0->getAlignment())
2875 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
2876 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
2877 LN0->isVolatile(), LN0->getAlignment());
2880 std::vector<SDNode*> NowDead;
2881 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead);
2882 CombineTo(N->getOperand(0).Val, Load);
2884 CombineTo(N0.Val, Load, Load.getValue(1));
2886 if (Opc == ISD::SIGN_EXTEND_INREG)
2887 return DAG.getNode(Opc, VT, Load, N->getOperand(1));
2889 return DAG.getNode(Opc, VT, Load);
2891 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2898 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2899 SDOperand N0 = N->getOperand(0);
2900 SDOperand N1 = N->getOperand(1);
2901 MVT::ValueType VT = N->getValueType(0);
2902 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2903 unsigned EVTBits = MVT::getSizeInBits(EVT);
2905 // fold (sext_in_reg c1) -> c1
2906 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2907 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2909 // If the input is already sign extended, just drop the extension.
2910 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2913 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2914 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2915 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2916 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2919 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
2920 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2921 return DAG.getZeroExtendInReg(N0, EVT);
2923 // fold operands of sext_in_reg based on knowledge that the top bits are not
2925 if (SimplifyDemandedBits(SDOperand(N, 0)))
2926 return SDOperand(N, 0);
2928 // fold (sext_in_reg (load x)) -> (smaller sextload x)
2929 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
2930 SDOperand NarrowLoad = ReduceLoadWidth(N);
2934 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2935 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2936 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2937 if (N0.getOpcode() == ISD::SRL) {
2938 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2939 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2940 // We can turn this into an SRA iff the input to the SRL is already sign
2942 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
2943 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2944 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2948 // fold (sext_inreg (extload x)) -> (sextload x)
2949 if (ISD::isEXTLoad(N0.Val) &&
2950 ISD::isUNINDEXEDLoad(N0.Val) &&
2951 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2952 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2953 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2954 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2955 LN0->getBasePtr(), LN0->getSrcValue(),
2956 LN0->getSrcValueOffset(), EVT,
2958 LN0->getAlignment());
2959 CombineTo(N, ExtLoad);
2960 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2961 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2963 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2964 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2966 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2967 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2968 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2969 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2970 LN0->getBasePtr(), LN0->getSrcValue(),
2971 LN0->getSrcValueOffset(), EVT,
2973 LN0->getAlignment());
2974 CombineTo(N, ExtLoad);
2975 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2976 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2981 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2982 SDOperand N0 = N->getOperand(0);
2983 MVT::ValueType VT = N->getValueType(0);
2986 if (N0.getValueType() == N->getValueType(0))
2988 // fold (truncate c1) -> c1
2989 if (isa<ConstantSDNode>(N0))
2990 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2991 // fold (truncate (truncate x)) -> (truncate x)
2992 if (N0.getOpcode() == ISD::TRUNCATE)
2993 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2994 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2995 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2996 N0.getOpcode() == ISD::ANY_EXTEND) {
2997 if (N0.getOperand(0).getValueType() < VT)
2998 // if the source is smaller than the dest, we still need an extend
2999 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
3000 else if (N0.getOperand(0).getValueType() > VT)
3001 // if the source is larger than the dest, than we just need the truncate
3002 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3004 // if the source and dest are the same type, we can drop both the extend
3006 return N0.getOperand(0);
3009 // See if we can simplify the input to this truncate through knowledge that
3010 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3012 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT));
3014 return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
3016 // fold (truncate (load x)) -> (smaller load x)
3017 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3018 return ReduceLoadWidth(N);
3021 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3022 SDOperand N0 = N->getOperand(0);
3023 MVT::ValueType VT = N->getValueType(0);
3025 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3026 // Only do this before legalize, since afterward the target may be depending
3027 // on the bitconvert.
3028 // First check to see if this is all constant.
3029 if (!AfterLegalize &&
3030 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
3031 MVT::isVector(VT)) {
3032 bool isSimple = true;
3033 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3034 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3035 N0.getOperand(i).getOpcode() != ISD::Constant &&
3036 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3041 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0));
3042 assert(!MVT::isVector(DestEltVT) &&
3043 "Element type of vector ValueType must not be vector!");
3045 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
3049 // If the input is a constant, let getNode() fold it.
3050 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3051 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3052 if (Res.Val != N) return Res;
3055 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
3056 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3058 // fold (conv (load x)) -> (load (conv*)x)
3059 // If the resultant load doesn't need a higher alignment than the original!
3060 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() &&
3061 TLI.isOperationLegal(ISD::LOAD, VT)) {
3062 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3063 unsigned Align = TLI.getTargetMachine().getTargetData()->
3064 getABITypeAlignment(MVT::getTypeForValueType(VT));
3065 unsigned OrigAlign = LN0->getAlignment();
3066 if (Align <= OrigAlign) {
3067 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
3068 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3069 LN0->isVolatile(), Align);
3071 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
3080 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3081 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3082 /// destination element value type.
3083 SDOperand DAGCombiner::
3084 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
3085 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
3087 // If this is already the right type, we're done.
3088 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
3090 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
3091 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
3093 // If this is a conversion of N elements of one type to N elements of another
3094 // type, convert each element. This handles FP<->INT cases.
3095 if (SrcBitSize == DstBitSize) {
3096 SmallVector<SDOperand, 8> Ops;
3097 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3098 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
3099 AddToWorkList(Ops.back().Val);
3102 MVT::getVectorType(DstEltVT,
3103 MVT::getVectorNumElements(BV->getValueType(0)));
3104 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3107 // Otherwise, we're growing or shrinking the elements. To avoid having to
3108 // handle annoying details of growing/shrinking FP values, we convert them to
3110 if (MVT::isFloatingPoint(SrcEltVT)) {
3111 // Convert the input float vector to a int vector where the elements are the
3113 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3114 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
3115 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
3119 // Now we know the input is an integer vector. If the output is a FP type,
3120 // convert to integer first, then to FP of the right size.
3121 if (MVT::isFloatingPoint(DstEltVT)) {
3122 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3123 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
3124 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val;
3126 // Next, convert to FP elements of the same size.
3127 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3130 // Okay, we know the src/dst types are both integers of differing types.
3131 // Handling growing first.
3132 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
3133 if (SrcBitSize < DstBitSize) {
3134 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3136 SmallVector<SDOperand, 8> Ops;
3137 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3138 i += NumInputsPerOutput) {
3139 bool isLE = TLI.isLittleEndian();
3140 uint64_t NewBits = 0;
3141 bool EltIsUndef = true;
3142 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3143 // Shift the previously computed bits over.
3144 NewBits <<= SrcBitSize;
3145 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3146 if (Op.getOpcode() == ISD::UNDEF) continue;
3149 NewBits |= cast<ConstantSDNode>(Op)->getValue();
3153 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3155 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3158 MVT::ValueType VT = MVT::getVectorType(DstEltVT,
3160 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3163 // Finally, this must be the case where we are shrinking elements: each input
3164 // turns into multiple outputs.
3165 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3166 SmallVector<SDOperand, 8> Ops;
3167 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3168 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3169 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3170 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3173 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
3175 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3176 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
3177 OpVal >>= DstBitSize;
3178 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3181 // For big endian targets, swap the order of the pieces of each element.
3182 if (!TLI.isLittleEndian())
3183 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3185 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size());
3186 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3191 SDOperand DAGCombiner::visitFADD(SDNode *N) {
3192 SDOperand N0 = N->getOperand(0);
3193 SDOperand N1 = N->getOperand(1);
3194 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3195 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3196 MVT::ValueType VT = N->getValueType(0);
3199 if (MVT::isVector(VT)) {
3200 SDOperand FoldedVOp = SimplifyVBinOp(N);
3201 if (FoldedVOp.Val) return FoldedVOp;
3204 // fold (fadd c1, c2) -> c1+c2
3206 return DAG.getNode(ISD::FADD, VT, N0, N1);
3207 // canonicalize constant to RHS
3208 if (N0CFP && !N1CFP)
3209 return DAG.getNode(ISD::FADD, VT, N1, N0);
3210 // fold (A + (-B)) -> A-B
3211 if (isNegatibleForFree(N1) == 2)
3212 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG));
3213 // fold ((-A) + B) -> B-A
3214 if (isNegatibleForFree(N0) == 2)
3215 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG));
3217 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3218 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3219 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3220 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
3221 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
3226 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
3227 SDOperand N0 = N->getOperand(0);
3228 SDOperand N1 = N->getOperand(1);
3229 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3230 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3231 MVT::ValueType VT = N->getValueType(0);
3234 if (MVT::isVector(VT)) {
3235 SDOperand FoldedVOp = SimplifyVBinOp(N);
3236 if (FoldedVOp.Val) return FoldedVOp;
3239 // fold (fsub c1, c2) -> c1-c2
3241 return DAG.getNode(ISD::FSUB, VT, N0, N1);
3243 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
3244 if (isNegatibleForFree(N1))
3245 return GetNegatedExpression(N1, DAG);
3246 return DAG.getNode(ISD::FNEG, VT, N1);
3248 // fold (A-(-B)) -> A+B
3249 if (isNegatibleForFree(N1))
3250 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG));
3255 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
3256 SDOperand N0 = N->getOperand(0);
3257 SDOperand N1 = N->getOperand(1);
3258 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3259 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3260 MVT::ValueType VT = N->getValueType(0);
3263 if (MVT::isVector(VT)) {
3264 SDOperand FoldedVOp = SimplifyVBinOp(N);
3265 if (FoldedVOp.Val) return FoldedVOp;
3268 // fold (fmul c1, c2) -> c1*c2
3270 return DAG.getNode(ISD::FMUL, VT, N0, N1);
3271 // canonicalize constant to RHS
3272 if (N0CFP && !N1CFP)
3273 return DAG.getNode(ISD::FMUL, VT, N1, N0);
3274 // fold (fmul X, 2.0) -> (fadd X, X)
3275 if (N1CFP && N1CFP->isExactlyValue(+2.0))
3276 return DAG.getNode(ISD::FADD, VT, N0, N0);
3277 // fold (fmul X, -1.0) -> (fneg X)
3278 if (N1CFP && N1CFP->isExactlyValue(-1.0))
3279 return DAG.getNode(ISD::FNEG, VT, N0);
3282 if (char LHSNeg = isNegatibleForFree(N0)) {
3283 if (char RHSNeg = isNegatibleForFree(N1)) {
3284 // Both can be negated for free, check to see if at least one is cheaper
3286 if (LHSNeg == 2 || RHSNeg == 2)
3287 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG),
3288 GetNegatedExpression(N1, DAG));
3292 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
3293 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
3294 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3295 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
3296 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
3301 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
3302 SDOperand N0 = N->getOperand(0);
3303 SDOperand N1 = N->getOperand(1);
3304 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3305 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3306 MVT::ValueType VT = N->getValueType(0);
3309 if (MVT::isVector(VT)) {
3310 SDOperand FoldedVOp = SimplifyVBinOp(N);
3311 if (FoldedVOp.Val) return FoldedVOp;
3314 // fold (fdiv c1, c2) -> c1/c2
3316 return DAG.getNode(ISD::FDIV, VT, N0, N1);
3320 if (char LHSNeg = isNegatibleForFree(N0)) {
3321 if (char RHSNeg = isNegatibleForFree(N1)) {
3322 // Both can be negated for free, check to see if at least one is cheaper
3324 if (LHSNeg == 2 || RHSNeg == 2)
3325 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG),
3326 GetNegatedExpression(N1, DAG));
3333 SDOperand DAGCombiner::visitFREM(SDNode *N) {
3334 SDOperand N0 = N->getOperand(0);
3335 SDOperand N1 = N->getOperand(1);
3336 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3337 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3338 MVT::ValueType VT = N->getValueType(0);
3340 // fold (frem c1, c2) -> fmod(c1,c2)
3342 return DAG.getNode(ISD::FREM, VT, N0, N1);
3347 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
3348 SDOperand N0 = N->getOperand(0);
3349 SDOperand N1 = N->getOperand(1);
3350 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3351 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3352 MVT::ValueType VT = N->getValueType(0);
3354 if (N0CFP && N1CFP) // Constant fold
3355 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
3358 const APFloat& V = N1CFP->getValueAPF();
3359 // copysign(x, c1) -> fabs(x) iff ispos(c1)
3360 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
3361 if (!V.isNegative())
3362 return DAG.getNode(ISD::FABS, VT, N0);
3364 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
3367 // copysign(fabs(x), y) -> copysign(x, y)
3368 // copysign(fneg(x), y) -> copysign(x, y)
3369 // copysign(copysign(x,z), y) -> copysign(x, y)
3370 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
3371 N0.getOpcode() == ISD::FCOPYSIGN)
3372 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
3374 // copysign(x, abs(y)) -> abs(x)
3375 if (N1.getOpcode() == ISD::FABS)
3376 return DAG.getNode(ISD::FABS, VT, N0);
3378 // copysign(x, copysign(y,z)) -> copysign(x, z)
3379 if (N1.getOpcode() == ISD::FCOPYSIGN)
3380 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
3382 // copysign(x, fp_extend(y)) -> copysign(x, y)
3383 // copysign(x, fp_round(y)) -> copysign(x, y)
3384 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
3385 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
3392 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
3393 SDOperand N0 = N->getOperand(0);
3394 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3395 MVT::ValueType VT = N->getValueType(0);
3397 // fold (sint_to_fp c1) -> c1fp
3399 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
3403 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
3404 SDOperand N0 = N->getOperand(0);
3405 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3406 MVT::ValueType VT = N->getValueType(0);
3408 // fold (uint_to_fp c1) -> c1fp
3410 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
3414 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
3415 SDOperand N0 = N->getOperand(0);
3416 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3417 MVT::ValueType VT = N->getValueType(0);
3419 // fold (fp_to_sint c1fp) -> c1
3421 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
3425 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
3426 SDOperand N0 = N->getOperand(0);
3427 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3428 MVT::ValueType VT = N->getValueType(0);
3430 // fold (fp_to_uint c1fp) -> c1
3432 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
3436 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
3437 SDOperand N0 = N->getOperand(0);
3438 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3439 MVT::ValueType VT = N->getValueType(0);
3441 // fold (fp_round c1fp) -> c1fp
3443 return DAG.getNode(ISD::FP_ROUND, VT, N0);
3445 // fold (fp_round (fp_extend x)) -> x
3446 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
3447 return N0.getOperand(0);
3449 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
3450 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
3451 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
3452 AddToWorkList(Tmp.Val);
3453 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
3459 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
3460 SDOperand N0 = N->getOperand(0);
3461 MVT::ValueType VT = N->getValueType(0);
3462 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3463 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3465 // fold (fp_round_inreg c1fp) -> c1fp
3467 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT);
3468 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
3473 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
3474 SDOperand N0 = N->getOperand(0);
3475 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3476 MVT::ValueType VT = N->getValueType(0);
3478 // fold (fp_extend c1fp) -> c1fp
3480 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
3482 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
3483 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3484 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
3485 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3486 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
3487 LN0->getBasePtr(), LN0->getSrcValue(),
3488 LN0->getSrcValueOffset(),
3491 LN0->getAlignment());
3492 CombineTo(N, ExtLoad);
3493 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
3494 ExtLoad.getValue(1));
3495 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3502 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
3503 SDOperand N0 = N->getOperand(0);
3505 if (isNegatibleForFree(N0))
3506 return GetNegatedExpression(N0, DAG);
3511 SDOperand DAGCombiner::visitFABS(SDNode *N) {
3512 SDOperand N0 = N->getOperand(0);
3513 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3514 MVT::ValueType VT = N->getValueType(0);
3516 // fold (fabs c1) -> fabs(c1)
3518 return DAG.getNode(ISD::FABS, VT, N0);
3519 // fold (fabs (fabs x)) -> (fabs x)
3520 if (N0.getOpcode() == ISD::FABS)
3521 return N->getOperand(0);
3522 // fold (fabs (fneg x)) -> (fabs x)
3523 // fold (fabs (fcopysign x, y)) -> (fabs x)
3524 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
3525 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
3530 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
3531 SDOperand Chain = N->getOperand(0);
3532 SDOperand N1 = N->getOperand(1);
3533 SDOperand N2 = N->getOperand(2);
3534 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3536 // never taken branch, fold to chain
3537 if (N1C && N1C->isNullValue())
3539 // unconditional branch
3540 if (N1C && N1C->getValue() == 1)
3541 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
3542 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
3544 if (N1.getOpcode() == ISD::SETCC &&
3545 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
3546 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
3547 N1.getOperand(0), N1.getOperand(1), N2);
3552 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
3554 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
3555 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
3556 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
3558 // Use SimplifySetCC to simplify SETCC's.
3559 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
3560 if (Simp.Val) AddToWorkList(Simp.Val);
3562 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
3564 // fold br_cc true, dest -> br dest (unconditional branch)
3565 if (SCCC && SCCC->getValue())
3566 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
3568 // fold br_cc false, dest -> unconditional fall through
3569 if (SCCC && SCCC->isNullValue())
3570 return N->getOperand(0);
3572 // fold to a simpler setcc
3573 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
3574 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
3575 Simp.getOperand(2), Simp.getOperand(0),
3576 Simp.getOperand(1), N->getOperand(4));
3581 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
3582 /// pre-indexed load / store when the base pointer is a add or subtract
3583 /// and it has other uses besides the load / store. After the
3584 /// transformation, the new indexed load / store has effectively folded
3585 /// the add / subtract in and all of its other uses are redirected to the
3586 /// new load / store.
3587 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
3594 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3595 if (LD->getAddressingMode() != ISD::UNINDEXED)
3597 VT = LD->getLoadedVT();
3598 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
3599 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
3601 Ptr = LD->getBasePtr();
3602 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3603 if (ST->getAddressingMode() != ISD::UNINDEXED)
3605 VT = ST->getStoredVT();
3606 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
3607 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
3609 Ptr = ST->getBasePtr();
3614 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
3615 // out. There is no reason to make this a preinc/predec.
3616 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
3617 Ptr.Val->hasOneUse())
3620 // Ask the target to do addressing mode selection.
3623 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3624 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
3626 // Don't create a indexed load / store with zero offset.
3627 if (isa<ConstantSDNode>(Offset) &&
3628 cast<ConstantSDNode>(Offset)->getValue() == 0)
3631 // Try turning it into a pre-indexed load / store except when:
3632 // 1) The new base ptr is a frame index.
3633 // 2) If N is a store and the new base ptr is either the same as or is a
3634 // predecessor of the value being stored.
3635 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
3636 // that would create a cycle.
3637 // 4) All uses are load / store ops that use it as old base ptr.
3639 // Check #1. Preinc'ing a frame index would require copying the stack pointer
3640 // (plus the implicit offset) to a register to preinc anyway.
3641 if (isa<FrameIndexSDNode>(BasePtr))
3646 SDOperand Val = cast<StoreSDNode>(N)->getValue();
3647 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val))
3651 // Now check for #3 and #4.
3652 bool RealUse = false;
3653 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3654 E = Ptr.Val->use_end(); I != E; ++I) {
3658 if (Use->isPredecessor(N))
3661 if (!((Use->getOpcode() == ISD::LOAD &&
3662 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
3663 (Use->getOpcode() == ISD::STORE) &&
3664 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
3672 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
3674 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3677 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
3678 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3680 std::vector<SDNode*> NowDead;
3682 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3684 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3687 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3691 // Nodes can end up on the worklist more than once. Make sure we do
3692 // not process a node that has been replaced.
3693 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3694 removeFromWorkList(NowDead[i]);
3695 // Finally, since the node is now dead, remove it from the graph.
3698 // Replace the uses of Ptr with uses of the updated base value.
3699 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
3701 removeFromWorkList(Ptr.Val);
3702 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3703 removeFromWorkList(NowDead[i]);
3704 DAG.DeleteNode(Ptr.Val);
3709 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
3710 /// add / sub of the base pointer node into a post-indexed load / store.
3711 /// The transformation folded the add / subtract into the new indexed
3712 /// load / store effectively and all of its uses are redirected to the
3713 /// new load / store.
3714 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
3721 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3722 if (LD->getAddressingMode() != ISD::UNINDEXED)
3724 VT = LD->getLoadedVT();
3725 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
3726 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
3728 Ptr = LD->getBasePtr();
3729 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3730 if (ST->getAddressingMode() != ISD::UNINDEXED)
3732 VT = ST->getStoredVT();
3733 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
3734 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
3736 Ptr = ST->getBasePtr();
3741 if (Ptr.Val->hasOneUse())
3744 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3745 E = Ptr.Val->use_end(); I != E; ++I) {
3748 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
3753 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3754 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
3756 std::swap(BasePtr, Offset);
3759 // Don't create a indexed load / store with zero offset.
3760 if (isa<ConstantSDNode>(Offset) &&
3761 cast<ConstantSDNode>(Offset)->getValue() == 0)
3764 // Try turning it into a post-indexed load / store except when
3765 // 1) All uses are load / store ops that use it as base ptr.
3766 // 2) Op must be independent of N, i.e. Op is neither a predecessor
3767 // nor a successor of N. Otherwise, if Op is folded that would
3771 bool TryNext = false;
3772 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
3773 EE = BasePtr.Val->use_end(); II != EE; ++II) {
3778 // If all the uses are load / store addresses, then don't do the
3780 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
3781 bool RealUse = false;
3782 for (SDNode::use_iterator III = Use->use_begin(),
3783 EEE = Use->use_end(); III != EEE; ++III) {
3784 SDNode *UseUse = *III;
3785 if (!((UseUse->getOpcode() == ISD::LOAD &&
3786 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
3787 (UseUse->getOpcode() == ISD::STORE) &&
3788 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
3802 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
3803 SDOperand Result = isLoad
3804 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
3805 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3808 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
3809 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3811 std::vector<SDNode*> NowDead;
3813 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3815 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3818 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3822 // Nodes can end up on the worklist more than once. Make sure we do
3823 // not process a node that has been replaced.
3824 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3825 removeFromWorkList(NowDead[i]);
3826 // Finally, since the node is now dead, remove it from the graph.
3829 // Replace the uses of Use with uses of the updated base value.
3830 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
3831 Result.getValue(isLoad ? 1 : 0),
3833 removeFromWorkList(Op);
3834 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3835 removeFromWorkList(NowDead[i]);
3846 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
3847 LoadSDNode *LD = cast<LoadSDNode>(N);
3848 SDOperand Chain = LD->getChain();
3849 SDOperand Ptr = LD->getBasePtr();
3851 // If load is not volatile and there are no uses of the loaded value (and
3852 // the updated indexed value in case of indexed loads), change uses of the
3853 // chain value into uses of the chain input (i.e. delete the dead load).
3854 if (!LD->isVolatile()) {
3855 if (N->getValueType(1) == MVT::Other) {
3857 if (N->hasNUsesOfValue(0, 0))
3858 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
3861 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
3862 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
3863 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0));
3864 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1));
3865 SDOperand To[] = { Undef0, Undef1, Chain };
3866 return CombineTo(N, To, 3);
3871 // If this load is directly stored, replace the load value with the stored
3873 // TODO: Handle store large -> read small portion.
3874 // TODO: Handle TRUNCSTORE/LOADEXT
3875 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3876 if (ISD::isNON_TRUNCStore(Chain.Val)) {
3877 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
3878 if (PrevST->getBasePtr() == Ptr &&
3879 PrevST->getValue().getValueType() == N->getValueType(0))
3880 return CombineTo(N, Chain.getOperand(1), Chain);
3885 // Walk up chain skipping non-aliasing memory nodes.
3886 SDOperand BetterChain = FindBetterChain(N, Chain);
3888 // If there is a better chain.
3889 if (Chain != BetterChain) {
3892 // Replace the chain to void dependency.
3893 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3894 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
3895 LD->getSrcValue(), LD->getSrcValueOffset(),
3896 LD->isVolatile(), LD->getAlignment());
3898 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
3899 LD->getValueType(0),
3900 BetterChain, Ptr, LD->getSrcValue(),
3901 LD->getSrcValueOffset(),
3904 LD->getAlignment());
3907 // Create token factor to keep old chain connected.
3908 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
3909 Chain, ReplLoad.getValue(1));
3911 // Replace uses with load result and token factor. Don't add users
3913 return CombineTo(N, ReplLoad.getValue(0), Token, false);
3917 // Try transforming N to an indexed load.
3918 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3919 return SDOperand(N, 0);
3924 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
3925 StoreSDNode *ST = cast<StoreSDNode>(N);
3926 SDOperand Chain = ST->getChain();
3927 SDOperand Value = ST->getValue();
3928 SDOperand Ptr = ST->getBasePtr();
3930 // If this is a store of a bit convert, store the input value if the
3931 // resultant store does not need a higher alignment than the original.
3932 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
3933 ST->getAddressingMode() == ISD::UNINDEXED) {
3934 unsigned Align = ST->getAlignment();
3935 MVT::ValueType SVT = Value.getOperand(0).getValueType();
3936 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
3937 getABITypeAlignment(MVT::getTypeForValueType(SVT));
3938 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
3939 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
3940 ST->getSrcValueOffset(), ST->isVolatile(), Align);
3943 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
3944 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
3945 if (Value.getOpcode() != ISD::TargetConstantFP) {
3947 switch (CFP->getValueType(0)) {
3948 default: assert(0 && "Unknown FP type");
3949 case MVT::f80: // We don't do this for these yet.
3954 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
3955 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
3956 convertToAPInt().getZExtValue(), MVT::i32);
3957 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3958 ST->getSrcValueOffset(), ST->isVolatile(),
3959 ST->getAlignment());
3963 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
3964 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
3965 getZExtValue(), MVT::i64);
3966 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3967 ST->getSrcValueOffset(), ST->isVolatile(),
3968 ST->getAlignment());
3969 } else if (TLI.isTypeLegal(MVT::i32)) {
3970 // Many FP stores are not make apparent until after legalize, e.g. for
3971 // argument passing. Since this is so common, custom legalize the
3972 // 64-bit integer store into two 32-bit stores.
3973 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue();
3974 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
3975 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
3976 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
3978 int SVOffset = ST->getSrcValueOffset();
3979 unsigned Alignment = ST->getAlignment();
3980 bool isVolatile = ST->isVolatile();
3982 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
3983 ST->getSrcValueOffset(),
3984 isVolatile, ST->getAlignment());
3985 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3986 DAG.getConstant(4, Ptr.getValueType()));
3990 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
3991 SVOffset, isVolatile, Alignment);
3992 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
4000 // Walk up chain skipping non-aliasing memory nodes.
4001 SDOperand BetterChain = FindBetterChain(N, Chain);
4003 // If there is a better chain.
4004 if (Chain != BetterChain) {
4005 // Replace the chain to avoid dependency.
4006 SDOperand ReplStore;
4007 if (ST->isTruncatingStore()) {
4008 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
4009 ST->getSrcValue(), ST->getSrcValueOffset(), ST->getStoredVT(),
4010 ST->isVolatile(), ST->getAlignment());
4012 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
4013 ST->getSrcValue(), ST->getSrcValueOffset(),
4014 ST->isVolatile(), ST->getAlignment());
4017 // Create token to keep both nodes around.
4019 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
4021 // Don't add users to work list.
4022 return CombineTo(N, Token, false);
4026 // Try transforming N to an indexed store.
4027 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4028 return SDOperand(N, 0);
4030 // FIXME: is there such a think as a truncating indexed store?
4031 if (ST->isTruncatingStore() && ST->getAddressingMode() == ISD::UNINDEXED &&
4032 MVT::isInteger(Value.getValueType())) {
4033 // See if we can simplify the input to this truncstore with knowledge that
4034 // only the low bits are being used. For example:
4035 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
4037 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT()));
4038 AddToWorkList(Value.Val);
4040 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
4041 ST->getSrcValueOffset(), ST->getStoredVT(),
4042 ST->isVolatile(), ST->getAlignment());
4048 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
4049 SDOperand InVec = N->getOperand(0);
4050 SDOperand InVal = N->getOperand(1);
4051 SDOperand EltNo = N->getOperand(2);
4053 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
4054 // vector with the inserted element.
4055 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
4056 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4057 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
4058 if (Elt < Ops.size())
4060 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
4061 &Ops[0], Ops.size());
4067 SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
4068 SDOperand InVec = N->getOperand(0);
4069 SDOperand EltNo = N->getOperand(1);
4071 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr)
4072 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
4073 if (isa<ConstantSDNode>(EltNo)) {
4074 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4075 bool NewLoad = false;
4077 MVT::ValueType VT = InVec.getValueType();
4078 MVT::ValueType EVT = MVT::getVectorElementType(VT);
4079 MVT::ValueType LVT = EVT;
4080 unsigned NumElts = MVT::getVectorNumElements(VT);
4081 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
4082 MVT::ValueType BCVT = InVec.getOperand(0).getValueType();
4083 if (NumElts != MVT::getVectorNumElements(BCVT))
4085 InVec = InVec.getOperand(0);
4086 EVT = MVT::getVectorElementType(BCVT);
4089 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4090 InVec.getOperand(0).getValueType() == EVT &&
4091 ISD::isNormalLoad(InVec.getOperand(0).Val) &&
4092 InVec.getOperand(0).hasOneUse()) {
4093 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0));
4094 unsigned Align = LN0->getAlignment();
4096 // Check the resultant load doesn't need a higher alignment than the
4098 unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
4099 getABITypeAlignment(MVT::getTypeForValueType(LVT));
4100 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align)
4105 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(),
4106 LN0->getSrcValue(), LN0->getSrcValueOffset(),
4107 LN0->isVolatile(), Align);
4115 SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
4116 unsigned NumInScalars = N->getNumOperands();
4117 MVT::ValueType VT = N->getValueType(0);
4118 unsigned NumElts = MVT::getVectorNumElements(VT);
4119 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4121 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
4122 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
4123 // at most two distinct vectors, turn this into a shuffle node.
4124 SDOperand VecIn1, VecIn2;
4125 for (unsigned i = 0; i != NumInScalars; ++i) {
4126 // Ignore undef inputs.
4127 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4129 // If this input is something other than a EXTRACT_VECTOR_ELT with a
4130 // constant index, bail out.
4131 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4132 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
4133 VecIn1 = VecIn2 = SDOperand(0, 0);
4137 // If the input vector type disagrees with the result of the build_vector,
4138 // we can't make a shuffle.
4139 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
4140 if (ExtractedFromVec.getValueType() != VT) {
4141 VecIn1 = VecIn2 = SDOperand(0, 0);
4145 // Otherwise, remember this. We allow up to two distinct input vectors.
4146 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
4149 if (VecIn1.Val == 0) {
4150 VecIn1 = ExtractedFromVec;
4151 } else if (VecIn2.Val == 0) {
4152 VecIn2 = ExtractedFromVec;
4155 VecIn1 = VecIn2 = SDOperand(0, 0);
4160 // If everything is good, we can make a shuffle operation.
4162 SmallVector<SDOperand, 8> BuildVecIndices;
4163 for (unsigned i = 0; i != NumInScalars; ++i) {
4164 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
4165 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
4169 SDOperand Extract = N->getOperand(i);
4171 // If extracting from the first vector, just use the index directly.
4172 if (Extract.getOperand(0) == VecIn1) {
4173 BuildVecIndices.push_back(Extract.getOperand(1));
4177 // Otherwise, use InIdx + VecSize
4178 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
4179 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars,
4180 TLI.getPointerTy()));
4183 // Add count and size info.
4184 MVT::ValueType BuildVecVT =
4185 MVT::getVectorType(TLI.getPointerTy(), NumElts);
4187 // Return the new VECTOR_SHUFFLE node.
4193 // Use an undef build_vector as input for the second operand.
4194 std::vector<SDOperand> UnOps(NumInScalars,
4195 DAG.getNode(ISD::UNDEF,
4197 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
4198 &UnOps[0], UnOps.size());
4199 AddToWorkList(Ops[1].Val);
4201 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
4202 &BuildVecIndices[0], BuildVecIndices.size());
4203 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3);
4209 SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
4210 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
4211 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
4212 // inputs come from at most two distinct vectors, turn this into a shuffle
4215 // If we only have one input vector, we don't need to do any concatenation.
4216 if (N->getNumOperands() == 1) {
4217 return N->getOperand(0);
4223 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
4224 SDOperand ShufMask = N->getOperand(2);
4225 unsigned NumElts = ShufMask.getNumOperands();
4227 // If the shuffle mask is an identity operation on the LHS, return the LHS.
4228 bool isIdentity = true;
4229 for (unsigned i = 0; i != NumElts; ++i) {
4230 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4231 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
4236 if (isIdentity) return N->getOperand(0);
4238 // If the shuffle mask is an identity operation on the RHS, return the RHS.
4240 for (unsigned i = 0; i != NumElts; ++i) {
4241 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4242 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
4247 if (isIdentity) return N->getOperand(1);
4249 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
4251 bool isUnary = true;
4252 bool isSplat = true;
4254 unsigned BaseIdx = 0;
4255 for (unsigned i = 0; i != NumElts; ++i)
4256 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
4257 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
4258 int V = (Idx < NumElts) ? 0 : 1;
4272 SDOperand N0 = N->getOperand(0);
4273 SDOperand N1 = N->getOperand(1);
4274 // Normalize unary shuffle so the RHS is undef.
4275 if (isUnary && VecNum == 1)
4278 // If it is a splat, check if the argument vector is a build_vector with
4279 // all scalar elements the same.
4283 // If this is a bit convert that changes the element type of the vector but
4284 // not the number of vector elements, look through it. Be careful not to
4285 // look though conversions that change things like v4f32 to v2f64.
4286 if (V->getOpcode() == ISD::BIT_CONVERT) {
4287 SDOperand ConvInput = V->getOperand(0);
4288 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts)
4292 if (V->getOpcode() == ISD::BUILD_VECTOR) {
4293 unsigned NumElems = V->getNumOperands();
4294 if (NumElems > BaseIdx) {
4296 bool AllSame = true;
4297 for (unsigned i = 0; i != NumElems; ++i) {
4298 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
4299 Base = V->getOperand(i);
4303 // Splat of <u, u, u, u>, return <u, u, u, u>
4306 for (unsigned i = 0; i != NumElems; ++i) {
4307 if (V->getOperand(i) != Base) {
4312 // Splat of <x, x, x, x>, return <x, x, x, x>
4319 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
4321 if (isUnary || N0 == N1) {
4322 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
4324 SmallVector<SDOperand, 8> MappedOps;
4325 for (unsigned i = 0; i != NumElts; ++i) {
4326 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
4327 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
4328 MappedOps.push_back(ShufMask.getOperand(i));
4331 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
4332 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
4335 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
4336 &MappedOps[0], MappedOps.size());
4337 AddToWorkList(ShufMask.Val);
4338 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
4340 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
4347 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
4348 /// an AND to a vector_shuffle with the destination vector and a zero vector.
4349 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
4350 /// vector_shuffle V, Zero, <0, 4, 2, 4>
4351 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
4352 SDOperand LHS = N->getOperand(0);
4353 SDOperand RHS = N->getOperand(1);
4354 if (N->getOpcode() == ISD::AND) {
4355 if (RHS.getOpcode() == ISD::BIT_CONVERT)
4356 RHS = RHS.getOperand(0);
4357 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
4358 std::vector<SDOperand> IdxOps;
4359 unsigned NumOps = RHS.getNumOperands();
4360 unsigned NumElts = NumOps;
4361 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType());
4362 for (unsigned i = 0; i != NumElts; ++i) {
4363 SDOperand Elt = RHS.getOperand(i);
4364 if (!isa<ConstantSDNode>(Elt))
4366 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
4367 IdxOps.push_back(DAG.getConstant(i, EVT));
4368 else if (cast<ConstantSDNode>(Elt)->isNullValue())
4369 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
4374 // Let's see if the target supports this vector_shuffle.
4375 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
4378 // Return the new VECTOR_SHUFFLE node.
4379 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts);
4380 std::vector<SDOperand> Ops;
4381 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
4383 AddToWorkList(LHS.Val);
4384 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
4385 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4386 &ZeroOps[0], ZeroOps.size()));
4387 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4388 &IdxOps[0], IdxOps.size()));
4389 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
4390 &Ops[0], Ops.size());
4391 if (VT != LHS.getValueType()) {
4392 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result);
4400 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
4401 SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
4402 // After legalize, the target may be depending on adds and other
4403 // binary ops to provide legal ways to construct constants or other
4404 // things. Simplifying them may result in a loss of legality.
4405 if (AfterLegalize) return SDOperand();
4407 MVT::ValueType VT = N->getValueType(0);
4408 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!");
4410 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4411 SDOperand LHS = N->getOperand(0);
4412 SDOperand RHS = N->getOperand(1);
4413 SDOperand Shuffle = XformToShuffleWithZero(N);
4414 if (Shuffle.Val) return Shuffle;
4416 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
4418 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
4419 RHS.getOpcode() == ISD::BUILD_VECTOR) {
4420 SmallVector<SDOperand, 8> Ops;
4421 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
4422 SDOperand LHSOp = LHS.getOperand(i);
4423 SDOperand RHSOp = RHS.getOperand(i);
4424 // If these two elements can't be folded, bail out.
4425 if ((LHSOp.getOpcode() != ISD::UNDEF &&
4426 LHSOp.getOpcode() != ISD::Constant &&
4427 LHSOp.getOpcode() != ISD::ConstantFP) ||
4428 (RHSOp.getOpcode() != ISD::UNDEF &&
4429 RHSOp.getOpcode() != ISD::Constant &&
4430 RHSOp.getOpcode() != ISD::ConstantFP))
4432 // Can't fold divide by zero.
4433 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
4434 N->getOpcode() == ISD::FDIV) {
4435 if ((RHSOp.getOpcode() == ISD::Constant &&
4436 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
4437 (RHSOp.getOpcode() == ISD::ConstantFP &&
4438 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero()))
4441 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
4442 AddToWorkList(Ops.back().Val);
4443 assert((Ops.back().getOpcode() == ISD::UNDEF ||
4444 Ops.back().getOpcode() == ISD::Constant ||
4445 Ops.back().getOpcode() == ISD::ConstantFP) &&
4446 "Scalar binop didn't fold!");
4449 if (Ops.size() == LHS.getNumOperands()) {
4450 MVT::ValueType VT = LHS.getValueType();
4451 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
4458 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
4459 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
4461 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
4462 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4463 // If we got a simplified select_cc node back from SimplifySelectCC, then
4464 // break it down into a new SETCC node, and a new SELECT node, and then return
4465 // the SELECT node, since we were called with a SELECT node.
4467 // Check to see if we got a select_cc back (to turn into setcc/select).
4468 // Otherwise, just return whatever node we got back, like fabs.
4469 if (SCC.getOpcode() == ISD::SELECT_CC) {
4470 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
4471 SCC.getOperand(0), SCC.getOperand(1),
4473 AddToWorkList(SETCC.Val);
4474 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
4475 SCC.getOperand(3), SETCC);
4482 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
4483 /// are the two values being selected between, see if we can simplify the
4484 /// select. Callers of this should assume that TheSelect is deleted if this
4485 /// returns true. As such, they should return the appropriate thing (e.g. the
4486 /// node) back to the top-level of the DAG combiner loop to avoid it being
4489 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
4492 // If this is a select from two identical things, try to pull the operation
4493 // through the select.
4494 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
4495 // If this is a load and the token chain is identical, replace the select
4496 // of two loads with a load through a select of the address to load from.
4497 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
4498 // constants have been dropped into the constant pool.
4499 if (LHS.getOpcode() == ISD::LOAD &&
4500 // Token chains must be identical.
4501 LHS.getOperand(0) == RHS.getOperand(0)) {
4502 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
4503 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
4505 // If this is an EXTLOAD, the VT's must match.
4506 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
4507 // FIXME: this conflates two src values, discarding one. This is not
4508 // the right thing to do, but nothing uses srcvalues now. When they do,
4509 // turn SrcValue into a list of locations.
4511 if (TheSelect->getOpcode() == ISD::SELECT) {
4512 // Check that the condition doesn't reach either load. If so, folding
4513 // this will induce a cycle into the DAG.
4514 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4515 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
4516 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
4517 TheSelect->getOperand(0), LLD->getBasePtr(),
4521 // Check that the condition doesn't reach either load. If so, folding
4522 // this will induce a cycle into the DAG.
4523 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4524 !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4525 !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
4526 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
4527 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
4528 TheSelect->getOperand(0),
4529 TheSelect->getOperand(1),
4530 LLD->getBasePtr(), RLD->getBasePtr(),
4531 TheSelect->getOperand(4));
4537 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
4538 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
4539 Addr,LLD->getSrcValue(),
4540 LLD->getSrcValueOffset(),
4542 LLD->getAlignment());
4544 Load = DAG.getExtLoad(LLD->getExtensionType(),
4545 TheSelect->getValueType(0),
4546 LLD->getChain(), Addr, LLD->getSrcValue(),
4547 LLD->getSrcValueOffset(),
4550 LLD->getAlignment());
4552 // Users of the select now use the result of the load.
4553 CombineTo(TheSelect, Load);
4555 // Users of the old loads now use the new load's chain. We know the
4556 // old-load value is dead now.
4557 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
4558 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
4568 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
4569 SDOperand N2, SDOperand N3,
4570 ISD::CondCode CC, bool NotExtCompare) {
4572 MVT::ValueType VT = N2.getValueType();
4573 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
4574 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
4575 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
4577 // Determine if the condition we're dealing with is constant
4578 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
4579 if (SCC.Val) AddToWorkList(SCC.Val);
4580 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
4582 // fold select_cc true, x, y -> x
4583 if (SCCC && SCCC->getValue())
4585 // fold select_cc false, x, y -> y
4586 if (SCCC && SCCC->getValue() == 0)
4589 // Check to see if we can simplify the select into an fabs node
4590 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
4591 // Allow either -0.0 or 0.0
4592 if (CFP->getValueAPF().isZero()) {
4593 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
4594 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
4595 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
4596 N2 == N3.getOperand(0))
4597 return DAG.getNode(ISD::FABS, VT, N0);
4599 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
4600 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
4601 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
4602 N2.getOperand(0) == N3)
4603 return DAG.getNode(ISD::FABS, VT, N3);
4607 // Check to see if we can perform the "gzip trick", transforming
4608 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
4609 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
4610 MVT::isInteger(N0.getValueType()) &&
4611 MVT::isInteger(N2.getValueType()) &&
4612 (N1C->isNullValue() || // (a < 0) ? b : 0
4613 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
4614 MVT::ValueType XType = N0.getValueType();
4615 MVT::ValueType AType = N2.getValueType();
4616 if (XType >= AType) {
4617 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
4618 // single-bit constant.
4619 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
4620 unsigned ShCtV = Log2_64(N2C->getValue());
4621 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
4622 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
4623 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
4624 AddToWorkList(Shift.Val);
4625 if (XType > AType) {
4626 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4627 AddToWorkList(Shift.Val);
4629 return DAG.getNode(ISD::AND, AType, Shift, N2);
4631 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4632 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4633 TLI.getShiftAmountTy()));
4634 AddToWorkList(Shift.Val);
4635 if (XType > AType) {
4636 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4637 AddToWorkList(Shift.Val);
4639 return DAG.getNode(ISD::AND, AType, Shift, N2);
4643 // fold select C, 16, 0 -> shl C, 4
4644 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
4645 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
4647 // If the caller doesn't want us to simplify this into a zext of a compare,
4649 if (NotExtCompare && N2C->getValue() == 1)
4652 // Get a SetCC of the condition
4653 // FIXME: Should probably make sure that setcc is legal if we ever have a
4654 // target where it isn't.
4655 SDOperand Temp, SCC;
4656 // cast from setcc result type to select result type
4657 if (AfterLegalize) {
4658 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4659 if (N2.getValueType() < SCC.getValueType())
4660 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
4662 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4664 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
4665 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4667 AddToWorkList(SCC.Val);
4668 AddToWorkList(Temp.Val);
4670 if (N2C->getValue() == 1)
4672 // shl setcc result by log2 n2c
4673 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
4674 DAG.getConstant(Log2_64(N2C->getValue()),
4675 TLI.getShiftAmountTy()));
4678 // Check to see if this is the equivalent of setcc
4679 // FIXME: Turn all of these into setcc if setcc if setcc is legal
4680 // otherwise, go ahead with the folds.
4681 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
4682 MVT::ValueType XType = N0.getValueType();
4683 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
4684 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4685 if (Res.getValueType() != VT)
4686 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
4690 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
4691 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
4692 TLI.isOperationLegal(ISD::CTLZ, XType)) {
4693 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
4694 return DAG.getNode(ISD::SRL, XType, Ctlz,
4695 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
4696 TLI.getShiftAmountTy()));
4698 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
4699 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
4700 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
4702 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
4703 DAG.getConstant(~0ULL, XType));
4704 return DAG.getNode(ISD::SRL, XType,
4705 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
4706 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4707 TLI.getShiftAmountTy()));
4709 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
4710 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
4711 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
4712 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4713 TLI.getShiftAmountTy()));
4714 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
4718 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
4719 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4720 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
4721 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
4722 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) {
4723 MVT::ValueType XType = N0.getValueType();
4724 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4725 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4726 TLI.getShiftAmountTy()));
4727 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4728 AddToWorkList(Shift.Val);
4729 AddToWorkList(Add.Val);
4730 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4732 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
4733 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4734 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
4735 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
4736 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
4737 MVT::ValueType XType = N0.getValueType();
4738 if (SubC->isNullValue() && MVT::isInteger(XType)) {
4739 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4740 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4741 TLI.getShiftAmountTy()));
4742 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4743 AddToWorkList(Shift.Val);
4744 AddToWorkList(Add.Val);
4745 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4753 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
4754 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
4755 SDOperand N1, ISD::CondCode Cond,
4756 bool foldBooleans) {
4757 TargetLowering::DAGCombinerInfo
4758 DagCombineInfo(DAG, !AfterLegalize, false, this);
4759 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
4762 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
4763 /// return a DAG expression to select that will generate the same value by
4764 /// multiplying by a magic number. See:
4765 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4766 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
4767 std::vector<SDNode*> Built;
4768 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
4770 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4776 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
4777 /// return a DAG expression to select that will generate the same value by
4778 /// multiplying by a magic number. See:
4779 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4780 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
4781 std::vector<SDNode*> Built;
4782 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
4784 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4790 /// FindBaseOffset - Return true if base is known not to alias with anything
4791 /// but itself. Provides base object and offset as results.
4792 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4793 // Assume it is a primitive operation.
4794 Base = Ptr; Offset = 0;
4796 // If it's an adding a simple constant then integrate the offset.
4797 if (Base.getOpcode() == ISD::ADD) {
4798 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4799 Base = Base.getOperand(0);
4800 Offset += C->getValue();
4804 // If it's any of the following then it can't alias with anything but itself.
4805 return isa<FrameIndexSDNode>(Base) ||
4806 isa<ConstantPoolSDNode>(Base) ||
4807 isa<GlobalAddressSDNode>(Base);
4810 /// isAlias - Return true if there is any possibility that the two addresses
4812 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4813 const Value *SrcValue1, int SrcValueOffset1,
4814 SDOperand Ptr2, int64_t Size2,
4815 const Value *SrcValue2, int SrcValueOffset2)
4817 // If they are the same then they must be aliases.
4818 if (Ptr1 == Ptr2) return true;
4820 // Gather base node and offset information.
4821 SDOperand Base1, Base2;
4822 int64_t Offset1, Offset2;
4823 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4824 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4826 // If they have a same base address then...
4827 if (Base1 == Base2) {
4828 // Check to see if the addresses overlap.
4829 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4832 // If we know both bases then they can't alias.
4833 if (KnownBase1 && KnownBase2) return false;
4835 if (CombinerGlobalAA) {
4836 // Use alias analysis information.
4837 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
4838 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
4839 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
4840 AliasAnalysis::AliasResult AAResult =
4841 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
4842 if (AAResult == AliasAnalysis::NoAlias)
4846 // Otherwise we have to assume they alias.
4850 /// FindAliasInfo - Extracts the relevant alias information from the memory
4851 /// node. Returns true if the operand was a load.
4852 bool DAGCombiner::FindAliasInfo(SDNode *N,
4853 SDOperand &Ptr, int64_t &Size,
4854 const Value *&SrcValue, int &SrcValueOffset) {
4855 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4856 Ptr = LD->getBasePtr();
4857 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4858 SrcValue = LD->getSrcValue();
4859 SrcValueOffset = LD->getSrcValueOffset();
4861 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4862 Ptr = ST->getBasePtr();
4863 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4864 SrcValue = ST->getSrcValue();
4865 SrcValueOffset = ST->getSrcValueOffset();
4867 assert(0 && "FindAliasInfo expected a memory operand");
4873 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4874 /// looking for aliasing nodes and adding them to the Aliases vector.
4875 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4876 SmallVector<SDOperand, 8> &Aliases) {
4877 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4878 std::set<SDNode *> Visited; // Visited node set.
4880 // Get alias information for node.
4883 const Value *SrcValue;
4885 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
4888 Chains.push_back(OriginalChain);
4890 // Look at each chain and determine if it is an alias. If so, add it to the
4891 // aliases list. If not, then continue up the chain looking for the next
4893 while (!Chains.empty()) {
4894 SDOperand Chain = Chains.back();
4897 // Don't bother if we've been before.
4898 if (Visited.find(Chain.Val) != Visited.end()) continue;
4899 Visited.insert(Chain.Val);
4901 switch (Chain.getOpcode()) {
4902 case ISD::EntryToken:
4903 // Entry token is ideal chain operand, but handled in FindBetterChain.
4908 // Get alias information for Chain.
4911 const Value *OpSrcValue;
4912 int OpSrcValueOffset;
4913 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
4914 OpSrcValue, OpSrcValueOffset);
4916 // If chain is alias then stop here.
4917 if (!(IsLoad && IsOpLoad) &&
4918 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
4919 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
4920 Aliases.push_back(Chain);
4922 // Look further up the chain.
4923 Chains.push_back(Chain.getOperand(0));
4924 // Clean up old chain.
4925 AddToWorkList(Chain.Val);
4930 case ISD::TokenFactor:
4931 // We have to check each of the operands of the token factor, so we queue
4932 // then up. Adding the operands to the queue (stack) in reverse order
4933 // maintains the original order and increases the likelihood that getNode
4934 // will find a matching token factor (CSE.)
4935 for (unsigned n = Chain.getNumOperands(); n;)
4936 Chains.push_back(Chain.getOperand(--n));
4937 // Eliminate the token factor if we can.
4938 AddToWorkList(Chain.Val);
4942 // For all other instructions we will just have to take what we can get.
4943 Aliases.push_back(Chain);
4949 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4950 /// for a better chain (aliasing node.)
4951 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4952 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4954 // Accumulate all the aliases to this node.
4955 GatherAllAliases(N, OldChain, Aliases);
4957 if (Aliases.size() == 0) {
4958 // If no operands then chain to entry token.
4959 return DAG.getEntryNode();
4960 } else if (Aliases.size() == 1) {
4961 // If a single operand then chain to it. We don't need to revisit it.
4965 // Construct a custom tailored token factor.
4966 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4967 &Aliases[0], Aliases.size());
4969 // Make sure the old chain gets cleaned up.
4970 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4975 // SelectionDAG::Combine - This is the entry point for the file.
4977 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
4978 if (!RunningAfterLegalize && ViewDAGCombine1)
4980 if (RunningAfterLegalize && ViewDAGCombine2)
4982 /// run - This is the main entry point to this class.
4984 DAGCombiner(*this, AA).Run(RunningAfterLegalize);