1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "dagcombine"
16 #include "llvm/CodeGen/SelectionDAG.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/ADT/SmallPtrSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
31 STATISTIC(NodesCombined , "Number of dag nodes combined");
32 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
33 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
38 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
39 cl::desc("Pop up a window to show dags before the first "
42 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
43 cl::desc("Pop up a window to show dags before the second "
46 static const bool ViewDAGCombine1 = false;
47 static const bool ViewDAGCombine2 = false;
51 CombinerAA("combiner-alias-analysis", cl::Hidden,
52 cl::desc("Turn on alias analysis during testing"));
55 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
56 cl::desc("Include global information in alias analysis"));
58 //------------------------------ DAGCombiner ---------------------------------//
60 class VISIBILITY_HIDDEN DAGCombiner {
65 // Worklist of all of the nodes that need to be simplified.
66 std::vector<SDNode*> WorkList;
68 // AA - Used for DAG load/store alias analysis.
71 /// AddUsersToWorkList - When an instruction is simplified, add all users of
72 /// the instruction to the work lists because they might get more simplified
75 void AddUsersToWorkList(SDNode *N) {
76 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
81 /// removeFromWorkList - remove all instances of N from the worklist.
83 void removeFromWorkList(SDNode *N) {
84 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
88 /// visit - call the node-specific routine that knows how to fold each
89 /// particular type of node.
90 SDOperand visit(SDNode *N);
93 /// AddToWorkList - Add to the work list making sure it's instance is at the
94 /// the back (next to be processed.)
95 void AddToWorkList(SDNode *N) {
96 removeFromWorkList(N);
97 WorkList.push_back(N);
100 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
102 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
104 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
105 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
106 DOUT << " and " << NumTo-1 << " other values\n";
107 std::vector<SDNode*> NowDead;
108 DAG.ReplaceAllUsesWith(N, To, &NowDead);
111 // Push the new nodes and any users onto the worklist
112 for (unsigned i = 0, e = NumTo; i != e; ++i) {
113 AddToWorkList(To[i].Val);
114 AddUsersToWorkList(To[i].Val);
118 // Nodes can be reintroduced into the worklist. Make sure we do not
119 // process a node that has been replaced.
120 removeFromWorkList(N);
121 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
122 removeFromWorkList(NowDead[i]);
124 // Finally, since the node is now dead, remove it from the graph.
126 return SDOperand(N, 0);
129 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
130 return CombineTo(N, &Res, 1, AddTo);
133 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
135 SDOperand To[] = { Res0, Res1 };
136 return CombineTo(N, To, 2, AddTo);
141 /// SimplifyDemandedBits - Check the specified integer node value to see if
142 /// it can be simplified or if things it uses can be simplified by bit
143 /// propagation. If so, return true.
144 bool SimplifyDemandedBits(SDOperand Op, uint64_t Demanded = ~0ULL) {
145 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize);
146 uint64_t KnownZero, KnownOne;
147 Demanded &= MVT::getIntVTBitMask(Op.getValueType());
148 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
152 AddToWorkList(Op.Val);
154 // Replace the old value with the new one.
156 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
157 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
160 std::vector<SDNode*> NowDead;
161 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &NowDead);
163 // Push the new node and any (possibly new) users onto the worklist.
164 AddToWorkList(TLO.New.Val);
165 AddUsersToWorkList(TLO.New.Val);
167 // Nodes can end up on the worklist more than once. Make sure we do
168 // not process a node that has been replaced.
169 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
170 removeFromWorkList(NowDead[i]);
172 // Finally, if the node is now dead, remove it from the graph. The node
173 // may not be dead if the replacement process recursively simplified to
174 // something else needing this node.
175 if (TLO.Old.Val->use_empty()) {
176 removeFromWorkList(TLO.Old.Val);
178 // If the operands of this node are only used by the node, they will now
179 // be dead. Make sure to visit them first to delete dead nodes early.
180 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i)
181 if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
182 AddToWorkList(TLO.Old.Val->getOperand(i).Val);
184 DAG.DeleteNode(TLO.Old.Val);
189 bool CombineToPreIndexedLoadStore(SDNode *N);
190 bool CombineToPostIndexedLoadStore(SDNode *N);
193 /// combine - call the node-specific routine that knows how to fold each
194 /// particular type of node. If that doesn't do anything, try the
195 /// target-specific DAG combines.
196 SDOperand combine(SDNode *N);
198 // Visitation implementation - Implement dag node combining for different
199 // node types. The semantics are as follows:
201 // SDOperand.Val == 0 - No change was made
202 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
203 // otherwise - N should be replaced by the returned Operand.
205 SDOperand visitTokenFactor(SDNode *N);
206 SDOperand visitADD(SDNode *N);
207 SDOperand visitSUB(SDNode *N);
208 SDOperand visitADDC(SDNode *N);
209 SDOperand visitADDE(SDNode *N);
210 SDOperand visitMUL(SDNode *N);
211 SDOperand visitSDIV(SDNode *N);
212 SDOperand visitUDIV(SDNode *N);
213 SDOperand visitSREM(SDNode *N);
214 SDOperand visitUREM(SDNode *N);
215 SDOperand visitMULHU(SDNode *N);
216 SDOperand visitMULHS(SDNode *N);
217 SDOperand visitSMUL_LOHI(SDNode *N);
218 SDOperand visitUMUL_LOHI(SDNode *N);
219 SDOperand visitSDIVREM(SDNode *N);
220 SDOperand visitUDIVREM(SDNode *N);
221 SDOperand visitAND(SDNode *N);
222 SDOperand visitOR(SDNode *N);
223 SDOperand visitXOR(SDNode *N);
224 SDOperand SimplifyVBinOp(SDNode *N);
225 SDOperand visitSHL(SDNode *N);
226 SDOperand visitSRA(SDNode *N);
227 SDOperand visitSRL(SDNode *N);
228 SDOperand visitCTLZ(SDNode *N);
229 SDOperand visitCTTZ(SDNode *N);
230 SDOperand visitCTPOP(SDNode *N);
231 SDOperand visitSELECT(SDNode *N);
232 SDOperand visitSELECT_CC(SDNode *N);
233 SDOperand visitSETCC(SDNode *N);
234 SDOperand visitSIGN_EXTEND(SDNode *N);
235 SDOperand visitZERO_EXTEND(SDNode *N);
236 SDOperand visitANY_EXTEND(SDNode *N);
237 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
238 SDOperand visitTRUNCATE(SDNode *N);
239 SDOperand visitBIT_CONVERT(SDNode *N);
240 SDOperand visitFADD(SDNode *N);
241 SDOperand visitFSUB(SDNode *N);
242 SDOperand visitFMUL(SDNode *N);
243 SDOperand visitFDIV(SDNode *N);
244 SDOperand visitFREM(SDNode *N);
245 SDOperand visitFCOPYSIGN(SDNode *N);
246 SDOperand visitSINT_TO_FP(SDNode *N);
247 SDOperand visitUINT_TO_FP(SDNode *N);
248 SDOperand visitFP_TO_SINT(SDNode *N);
249 SDOperand visitFP_TO_UINT(SDNode *N);
250 SDOperand visitFP_ROUND(SDNode *N);
251 SDOperand visitFP_ROUND_INREG(SDNode *N);
252 SDOperand visitFP_EXTEND(SDNode *N);
253 SDOperand visitFNEG(SDNode *N);
254 SDOperand visitFABS(SDNode *N);
255 SDOperand visitBRCOND(SDNode *N);
256 SDOperand visitBR_CC(SDNode *N);
257 SDOperand visitLOAD(SDNode *N);
258 SDOperand visitSTORE(SDNode *N);
259 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
260 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N);
261 SDOperand visitBUILD_VECTOR(SDNode *N);
262 SDOperand visitCONCAT_VECTORS(SDNode *N);
263 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
265 SDOperand XformToShuffleWithZero(SDNode *N);
266 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
268 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt);
270 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
271 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
272 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
273 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
274 SDOperand N3, ISD::CondCode CC,
275 bool NotExtCompare = false);
276 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
277 ISD::CondCode Cond, bool foldBooleans = true);
278 bool SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp);
279 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
280 SDOperand BuildSDIV(SDNode *N);
281 SDOperand BuildUDIV(SDNode *N);
282 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
283 SDOperand ReduceLoadWidth(SDNode *N);
285 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask);
287 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
288 /// looking for aliasing nodes and adding them to the Aliases vector.
289 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
290 SmallVector<SDOperand, 8> &Aliases);
292 /// isAlias - Return true if there is any possibility that the two addresses
294 bool isAlias(SDOperand Ptr1, int64_t Size1,
295 const Value *SrcValue1, int SrcValueOffset1,
296 SDOperand Ptr2, int64_t Size2,
297 const Value *SrcValue2, int SrcValueOffset2);
299 /// FindAliasInfo - Extracts the relevant alias information from the memory
300 /// node. Returns true if the operand was a load.
301 bool FindAliasInfo(SDNode *N,
302 SDOperand &Ptr, int64_t &Size,
303 const Value *&SrcValue, int &SrcValueOffset);
305 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
306 /// looking for a better chain (aliasing node.)
307 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
310 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
312 TLI(D.getTargetLoweringInfo()),
313 AfterLegalize(false),
316 /// Run - runs the dag combiner on all nodes in the work list
317 void Run(bool RunningAfterLegalize);
321 //===----------------------------------------------------------------------===//
322 // TargetLowering::DAGCombinerInfo implementation
323 //===----------------------------------------------------------------------===//
325 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
326 ((DAGCombiner*)DC)->AddToWorkList(N);
329 SDOperand TargetLowering::DAGCombinerInfo::
330 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
331 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
334 SDOperand TargetLowering::DAGCombinerInfo::
335 CombineTo(SDNode *N, SDOperand Res) {
336 return ((DAGCombiner*)DC)->CombineTo(N, Res);
340 SDOperand TargetLowering::DAGCombinerInfo::
341 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
342 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
346 //===----------------------------------------------------------------------===//
348 //===----------------------------------------------------------------------===//
350 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
351 /// specified expression for the same cost as the expression itself, or 2 if we
352 /// can compute the negated form more cheaply than the expression itself.
353 static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) {
354 // No compile time optimizations on this type.
355 if (Op.getValueType() == MVT::ppcf128)
358 // fneg is removable even if it has multiple uses.
359 if (Op.getOpcode() == ISD::FNEG) return 2;
361 // Don't allow anything with multiple uses.
362 if (!Op.hasOneUse()) return 0;
364 // Don't recurse exponentially.
365 if (Depth > 6) return 0;
367 switch (Op.getOpcode()) {
368 default: return false;
369 case ISD::ConstantFP:
372 // FIXME: determine better conditions for this xform.
373 if (!UnsafeFPMath) return 0;
376 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
379 return isNegatibleForFree(Op.getOperand(1), Depth+1);
381 // We can't turn -(A-B) into B-A when we honor signed zeros.
382 if (!UnsafeFPMath) return 0;
389 if (HonorSignDependentRoundingFPMath()) return 0;
391 // -(X*Y) -> (-X * Y) or (X*-Y)
392 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
395 return isNegatibleForFree(Op.getOperand(1), Depth+1);
400 return isNegatibleForFree(Op.getOperand(0), Depth+1);
404 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
405 /// returns the newly negated expression.
406 static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
407 unsigned Depth = 0) {
408 // fneg is removable even if it has multiple uses.
409 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
411 // Don't allow anything with multiple uses.
412 assert(Op.hasOneUse() && "Unknown reuse!");
414 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
415 switch (Op.getOpcode()) {
416 default: assert(0 && "Unknown code");
417 case ISD::ConstantFP: {
418 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
420 return DAG.getConstantFP(V, Op.getValueType());
423 // FIXME: determine better conditions for this xform.
424 assert(UnsafeFPMath);
427 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
428 return DAG.getNode(ISD::FSUB, Op.getValueType(),
429 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
432 return DAG.getNode(ISD::FSUB, Op.getValueType(),
433 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1),
436 // We can't turn -(A-B) into B-A when we honor signed zeros.
437 assert(UnsafeFPMath);
440 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
441 if (N0CFP->getValueAPF().isZero())
442 return Op.getOperand(1);
445 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1),
450 assert(!HonorSignDependentRoundingFPMath());
453 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
454 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
455 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
459 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
461 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1));
465 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
466 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1));
468 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(),
469 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
475 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
476 // that selects between the values 1 and 0, making it equivalent to a setcc.
477 // Also, set the incoming LHS, RHS, and CC references to the appropriate
478 // nodes based on the type of node we are checking. This simplifies life a
479 // bit for the callers.
480 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
482 if (N.getOpcode() == ISD::SETCC) {
483 LHS = N.getOperand(0);
484 RHS = N.getOperand(1);
485 CC = N.getOperand(2);
488 if (N.getOpcode() == ISD::SELECT_CC &&
489 N.getOperand(2).getOpcode() == ISD::Constant &&
490 N.getOperand(3).getOpcode() == ISD::Constant &&
491 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
492 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
493 LHS = N.getOperand(0);
494 RHS = N.getOperand(1);
495 CC = N.getOperand(4);
501 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
502 // one use. If this is true, it allows the users to invert the operation for
503 // free when it is profitable to do so.
504 static bool isOneUseSetCC(SDOperand N) {
505 SDOperand N0, N1, N2;
506 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
511 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
512 MVT::ValueType VT = N0.getValueType();
513 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
514 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
515 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
516 if (isa<ConstantSDNode>(N1)) {
517 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
518 AddToWorkList(OpNode.Val);
519 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
520 } else if (N0.hasOneUse()) {
521 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
522 AddToWorkList(OpNode.Val);
523 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
526 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
527 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
528 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
529 if (isa<ConstantSDNode>(N0)) {
530 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
531 AddToWorkList(OpNode.Val);
532 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
533 } else if (N1.hasOneUse()) {
534 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
535 AddToWorkList(OpNode.Val);
536 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
542 //===----------------------------------------------------------------------===//
543 // Main DAG Combiner implementation
544 //===----------------------------------------------------------------------===//
546 void DAGCombiner::Run(bool RunningAfterLegalize) {
547 // set the instance variable, so that the various visit routines may use it.
548 AfterLegalize = RunningAfterLegalize;
550 // Add all the dag nodes to the worklist.
551 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
552 E = DAG.allnodes_end(); I != E; ++I)
553 WorkList.push_back(I);
555 // Create a dummy node (which is not added to allnodes), that adds a reference
556 // to the root node, preventing it from being deleted, and tracking any
557 // changes of the root.
558 HandleSDNode Dummy(DAG.getRoot());
560 // The root of the dag may dangle to deleted nodes until the dag combiner is
561 // done. Set it to null to avoid confusion.
562 DAG.setRoot(SDOperand());
564 // while the worklist isn't empty, inspect the node on the end of it and
565 // try and combine it.
566 while (!WorkList.empty()) {
567 SDNode *N = WorkList.back();
570 // If N has no uses, it is dead. Make sure to revisit all N's operands once
571 // N is deleted from the DAG, since they too may now be dead or may have a
572 // reduced number of uses, allowing other xforms.
573 if (N->use_empty() && N != &Dummy) {
574 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
575 AddToWorkList(N->getOperand(i).Val);
581 SDOperand RV = combine(N);
585 // If we get back the same node we passed in, rather than a new node or
586 // zero, we know that the node must have defined multiple values and
587 // CombineTo was used. Since CombineTo takes care of the worklist
588 // mechanics for us, we have no work to do in this case.
590 assert(N->getOpcode() != ISD::DELETED_NODE &&
591 RV.Val->getOpcode() != ISD::DELETED_NODE &&
592 "Node was deleted but visit returned new node!");
594 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
595 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
597 std::vector<SDNode*> NowDead;
598 if (N->getNumValues() == RV.Val->getNumValues())
599 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
601 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
603 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
606 // Push the new node and any users onto the worklist
607 AddToWorkList(RV.Val);
608 AddUsersToWorkList(RV.Val);
610 // Add any uses of the old node to the worklist if they have a single
611 // use. They may be dead after this node is deleted.
612 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
613 AddToWorkList(N->getOperand(i).Val);
615 // Nodes can be reintroduced into the worklist. Make sure we do not
616 // process a node that has been replaced.
617 removeFromWorkList(N);
618 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
619 removeFromWorkList(NowDead[i]);
621 // Finally, since the node is now dead, remove it from the graph.
627 // If the root changed (e.g. it was a dead load, update the root).
628 DAG.setRoot(Dummy.getValue());
631 SDOperand DAGCombiner::visit(SDNode *N) {
632 switch(N->getOpcode()) {
634 case ISD::TokenFactor: return visitTokenFactor(N);
635 case ISD::ADD: return visitADD(N);
636 case ISD::SUB: return visitSUB(N);
637 case ISD::ADDC: return visitADDC(N);
638 case ISD::ADDE: return visitADDE(N);
639 case ISD::MUL: return visitMUL(N);
640 case ISD::SDIV: return visitSDIV(N);
641 case ISD::UDIV: return visitUDIV(N);
642 case ISD::SREM: return visitSREM(N);
643 case ISD::UREM: return visitUREM(N);
644 case ISD::MULHU: return visitMULHU(N);
645 case ISD::MULHS: return visitMULHS(N);
646 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
647 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
648 case ISD::SDIVREM: return visitSDIVREM(N);
649 case ISD::UDIVREM: return visitUDIVREM(N);
650 case ISD::AND: return visitAND(N);
651 case ISD::OR: return visitOR(N);
652 case ISD::XOR: return visitXOR(N);
653 case ISD::SHL: return visitSHL(N);
654 case ISD::SRA: return visitSRA(N);
655 case ISD::SRL: return visitSRL(N);
656 case ISD::CTLZ: return visitCTLZ(N);
657 case ISD::CTTZ: return visitCTTZ(N);
658 case ISD::CTPOP: return visitCTPOP(N);
659 case ISD::SELECT: return visitSELECT(N);
660 case ISD::SELECT_CC: return visitSELECT_CC(N);
661 case ISD::SETCC: return visitSETCC(N);
662 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
663 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
664 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
665 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
666 case ISD::TRUNCATE: return visitTRUNCATE(N);
667 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
668 case ISD::FADD: return visitFADD(N);
669 case ISD::FSUB: return visitFSUB(N);
670 case ISD::FMUL: return visitFMUL(N);
671 case ISD::FDIV: return visitFDIV(N);
672 case ISD::FREM: return visitFREM(N);
673 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
674 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
675 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
676 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
677 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
678 case ISD::FP_ROUND: return visitFP_ROUND(N);
679 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
680 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
681 case ISD::FNEG: return visitFNEG(N);
682 case ISD::FABS: return visitFABS(N);
683 case ISD::BRCOND: return visitBRCOND(N);
684 case ISD::BR_CC: return visitBR_CC(N);
685 case ISD::LOAD: return visitLOAD(N);
686 case ISD::STORE: return visitSTORE(N);
687 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
688 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
689 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
690 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
691 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
696 SDOperand DAGCombiner::combine(SDNode *N) {
698 SDOperand RV = visit(N);
700 // If nothing happened, try a target-specific DAG combine.
702 assert(N->getOpcode() != ISD::DELETED_NODE &&
703 "Node was deleted but visit returned NULL!");
705 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
706 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
708 // Expose the DAG combiner to the target combiner impls.
709 TargetLowering::DAGCombinerInfo
710 DagCombineInfo(DAG, !AfterLegalize, false, this);
712 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
719 /// getInputChainForNode - Given a node, return its input chain if it has one,
720 /// otherwise return a null sd operand.
721 static SDOperand getInputChainForNode(SDNode *N) {
722 if (unsigned NumOps = N->getNumOperands()) {
723 if (N->getOperand(0).getValueType() == MVT::Other)
724 return N->getOperand(0);
725 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
726 return N->getOperand(NumOps-1);
727 for (unsigned i = 1; i < NumOps-1; ++i)
728 if (N->getOperand(i).getValueType() == MVT::Other)
729 return N->getOperand(i);
731 return SDOperand(0, 0);
734 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
735 // If N has two operands, where one has an input chain equal to the other,
736 // the 'other' chain is redundant.
737 if (N->getNumOperands() == 2) {
738 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
739 return N->getOperand(0);
740 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
741 return N->getOperand(1);
744 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
745 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
746 SmallPtrSet<SDNode*, 16> SeenOps;
747 bool Changed = false; // If we should replace this token factor.
749 // Start out with this token factor.
752 // Iterate through token factors. The TFs grows when new token factors are
754 for (unsigned i = 0; i < TFs.size(); ++i) {
757 // Check each of the operands.
758 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
759 SDOperand Op = TF->getOperand(i);
761 switch (Op.getOpcode()) {
762 case ISD::EntryToken:
763 // Entry tokens don't need to be added to the list. They are
768 case ISD::TokenFactor:
769 if ((CombinerAA || Op.hasOneUse()) &&
770 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
771 // Queue up for processing.
772 TFs.push_back(Op.Val);
773 // Clean up in case the token factor is removed.
774 AddToWorkList(Op.Val);
781 // Only add if it isn't already in the list.
782 if (SeenOps.insert(Op.Val))
793 // If we've change things around then replace token factor.
795 if (Ops.size() == 0) {
796 // The entry token is the only possible outcome.
797 Result = DAG.getEntryNode();
799 // New and improved token factor.
800 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
803 // Don't add users to work list.
804 return CombineTo(N, Result, false);
811 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
812 MVT::ValueType VT = N0.getValueType();
813 SDOperand N00 = N0.getOperand(0);
814 SDOperand N01 = N0.getOperand(1);
815 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
816 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
817 isa<ConstantSDNode>(N00.getOperand(1))) {
818 N0 = DAG.getNode(ISD::ADD, VT,
819 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
820 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
821 return DAG.getNode(ISD::ADD, VT, N0, N1);
827 SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
829 MVT::ValueType VT = N->getValueType(0);
830 unsigned Opc = N->getOpcode();
831 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
832 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
833 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
834 ISD::CondCode CC = ISD::SETCC_INVALID;
836 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
838 SDOperand CCOp = Slct.getOperand(0);
839 if (CCOp.getOpcode() == ISD::SETCC)
840 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
843 bool DoXform = false;
845 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
847 if (LHS.getOpcode() == ISD::Constant &&
848 cast<ConstantSDNode>(LHS)->isNullValue())
850 else if (CC != ISD::SETCC_INVALID &&
851 RHS.getOpcode() == ISD::Constant &&
852 cast<ConstantSDNode>(RHS)->isNullValue()) {
854 SDOperand Op0 = Slct.getOperand(0);
855 bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType()
856 : Op0.getOperand(0).getValueType());
857 CC = ISD::getSetCCInverse(CC, isInt);
863 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS);
865 return DAG.getSelectCC(OtherOp, Result,
866 Slct.getOperand(0), Slct.getOperand(1), CC);
867 SDOperand CCOp = Slct.getOperand(0);
869 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
870 CCOp.getOperand(1), CC);
871 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
876 SDOperand DAGCombiner::visitADD(SDNode *N) {
877 SDOperand N0 = N->getOperand(0);
878 SDOperand N1 = N->getOperand(1);
879 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
880 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
881 MVT::ValueType VT = N0.getValueType();
884 if (MVT::isVector(VT)) {
885 SDOperand FoldedVOp = SimplifyVBinOp(N);
886 if (FoldedVOp.Val) return FoldedVOp;
889 // fold (add x, undef) -> undef
890 if (N0.getOpcode() == ISD::UNDEF)
892 if (N1.getOpcode() == ISD::UNDEF)
894 // fold (add c1, c2) -> c1+c2
896 return DAG.getNode(ISD::ADD, VT, N0, N1);
897 // canonicalize constant to RHS
899 return DAG.getNode(ISD::ADD, VT, N1, N0);
900 // fold (add x, 0) -> x
901 if (N1C && N1C->isNullValue())
903 // fold ((c1-A)+c2) -> (c1+c2)-A
904 if (N1C && N0.getOpcode() == ISD::SUB)
905 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
906 return DAG.getNode(ISD::SUB, VT,
907 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
910 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
913 // fold ((0-A) + B) -> B-A
914 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
915 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
916 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
917 // fold (A + (0-B)) -> A-B
918 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
919 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
920 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
921 // fold (A+(B-A)) -> B
922 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
923 return N1.getOperand(0);
925 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
926 return SDOperand(N, 0);
928 // fold (a+b) -> (a|b) iff a and b share no bits.
929 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
930 uint64_t LHSZero, LHSOne;
931 uint64_t RHSZero, RHSOne;
932 uint64_t Mask = MVT::getIntVTBitMask(VT);
933 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
935 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
937 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
938 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
939 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
940 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
941 return DAG.getNode(ISD::OR, VT, N0, N1);
945 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
946 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
947 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
948 if (Result.Val) return Result;
950 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
951 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
952 if (Result.Val) return Result;
955 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
956 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
957 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG);
958 if (Result.Val) return Result;
960 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
961 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
962 if (Result.Val) return Result;
968 SDOperand DAGCombiner::visitADDC(SDNode *N) {
969 SDOperand N0 = N->getOperand(0);
970 SDOperand N1 = N->getOperand(1);
971 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
972 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
973 MVT::ValueType VT = N0.getValueType();
975 // If the flag result is dead, turn this into an ADD.
976 if (N->hasNUsesOfValue(0, 1))
977 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
978 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
980 // canonicalize constant to RHS.
982 SDOperand Ops[] = { N1, N0 };
983 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
986 // fold (addc x, 0) -> x + no carry out
987 if (N1C && N1C->isNullValue())
988 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
990 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
991 uint64_t LHSZero, LHSOne;
992 uint64_t RHSZero, RHSOne;
993 uint64_t Mask = MVT::getIntVTBitMask(VT);
994 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
996 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
998 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
999 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1000 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1001 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1002 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
1003 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
1009 SDOperand DAGCombiner::visitADDE(SDNode *N) {
1010 SDOperand N0 = N->getOperand(0);
1011 SDOperand N1 = N->getOperand(1);
1012 SDOperand CarryIn = N->getOperand(2);
1013 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1014 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1015 //MVT::ValueType VT = N0.getValueType();
1017 // canonicalize constant to RHS
1019 SDOperand Ops[] = { N1, N0, CarryIn };
1020 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
1023 // fold (adde x, y, false) -> (addc x, y)
1024 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
1025 SDOperand Ops[] = { N1, N0 };
1026 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
1034 SDOperand DAGCombiner::visitSUB(SDNode *N) {
1035 SDOperand N0 = N->getOperand(0);
1036 SDOperand N1 = N->getOperand(1);
1037 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1038 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1039 MVT::ValueType VT = N0.getValueType();
1042 if (MVT::isVector(VT)) {
1043 SDOperand FoldedVOp = SimplifyVBinOp(N);
1044 if (FoldedVOp.Val) return FoldedVOp;
1047 // fold (sub x, x) -> 0
1049 return DAG.getConstant(0, N->getValueType(0));
1050 // fold (sub c1, c2) -> c1-c2
1052 return DAG.getNode(ISD::SUB, VT, N0, N1);
1053 // fold (sub x, c) -> (add x, -c)
1055 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
1056 // fold (A+B)-A -> B
1057 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1058 return N0.getOperand(1);
1059 // fold (A+B)-B -> A
1060 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1061 return N0.getOperand(0);
1062 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1063 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
1064 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
1065 if (Result.Val) return Result;
1067 // If either operand of a sub is undef, the result is undef
1068 if (N0.getOpcode() == ISD::UNDEF)
1070 if (N1.getOpcode() == ISD::UNDEF)
1076 SDOperand DAGCombiner::visitMUL(SDNode *N) {
1077 SDOperand N0 = N->getOperand(0);
1078 SDOperand N1 = N->getOperand(1);
1079 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1080 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1081 MVT::ValueType VT = N0.getValueType();
1084 if (MVT::isVector(VT)) {
1085 SDOperand FoldedVOp = SimplifyVBinOp(N);
1086 if (FoldedVOp.Val) return FoldedVOp;
1089 // fold (mul x, undef) -> 0
1090 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1091 return DAG.getConstant(0, VT);
1092 // fold (mul c1, c2) -> c1*c2
1094 return DAG.getNode(ISD::MUL, VT, N0, N1);
1095 // canonicalize constant to RHS
1097 return DAG.getNode(ISD::MUL, VT, N1, N0);
1098 // fold (mul x, 0) -> 0
1099 if (N1C && N1C->isNullValue())
1101 // fold (mul x, -1) -> 0-x
1102 if (N1C && N1C->isAllOnesValue())
1103 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1104 // fold (mul x, (1 << c)) -> x << c
1105 if (N1C && isPowerOf2_64(N1C->getValue()))
1106 return DAG.getNode(ISD::SHL, VT, N0,
1107 DAG.getConstant(Log2_64(N1C->getValue()),
1108 TLI.getShiftAmountTy()));
1109 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1110 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
1111 // FIXME: If the input is something that is easily negated (e.g. a
1112 // single-use add), we should put the negate there.
1113 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
1114 DAG.getNode(ISD::SHL, VT, N0,
1115 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
1116 TLI.getShiftAmountTy())));
1119 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1120 if (N1C && N0.getOpcode() == ISD::SHL &&
1121 isa<ConstantSDNode>(N0.getOperand(1))) {
1122 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
1123 AddToWorkList(C3.Val);
1124 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
1127 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1130 SDOperand Sh(0,0), Y(0,0);
1131 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1132 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1133 N0.Val->hasOneUse()) {
1135 } else if (N1.getOpcode() == ISD::SHL &&
1136 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
1140 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
1141 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
1144 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1145 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1146 isa<ConstantSDNode>(N0.getOperand(1))) {
1147 return DAG.getNode(ISD::ADD, VT,
1148 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
1149 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
1153 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
1160 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
1161 SDOperand N0 = N->getOperand(0);
1162 SDOperand N1 = N->getOperand(1);
1163 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1164 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1165 MVT::ValueType VT = N->getValueType(0);
1168 if (MVT::isVector(VT)) {
1169 SDOperand FoldedVOp = SimplifyVBinOp(N);
1170 if (FoldedVOp.Val) return FoldedVOp;
1173 // fold (sdiv c1, c2) -> c1/c2
1174 if (N0C && N1C && !N1C->isNullValue())
1175 return DAG.getNode(ISD::SDIV, VT, N0, N1);
1176 // fold (sdiv X, 1) -> X
1177 if (N1C && N1C->getSignExtended() == 1LL)
1179 // fold (sdiv X, -1) -> 0-X
1180 if (N1C && N1C->isAllOnesValue())
1181 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1182 // If we know the sign bits of both operands are zero, strength reduce to a
1183 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1184 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1185 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1186 DAG.MaskedValueIsZero(N0, SignBit))
1187 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
1188 // fold (sdiv X, pow2) -> simple ops after legalize
1189 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
1190 (isPowerOf2_64(N1C->getSignExtended()) ||
1191 isPowerOf2_64(-N1C->getSignExtended()))) {
1192 // If dividing by powers of two is cheap, then don't perform the following
1194 if (TLI.isPow2DivCheap())
1196 int64_t pow2 = N1C->getSignExtended();
1197 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1198 unsigned lg2 = Log2_64(abs2);
1199 // Splat the sign bit into the register
1200 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
1201 DAG.getConstant(MVT::getSizeInBits(VT)-1,
1202 TLI.getShiftAmountTy()));
1203 AddToWorkList(SGN.Val);
1204 // Add (N0 < 0) ? abs2 - 1 : 0;
1205 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
1206 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
1207 TLI.getShiftAmountTy()));
1208 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
1209 AddToWorkList(SRL.Val);
1210 AddToWorkList(ADD.Val); // Divide by pow2
1211 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
1212 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
1213 // If we're dividing by a positive value, we're done. Otherwise, we must
1214 // negate the result.
1217 AddToWorkList(SRA.Val);
1218 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
1220 // if integer divide is expensive and we satisfy the requirements, emit an
1221 // alternate sequence.
1222 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
1223 !TLI.isIntDivCheap()) {
1224 SDOperand Op = BuildSDIV(N);
1225 if (Op.Val) return Op;
1229 if (N0.getOpcode() == ISD::UNDEF)
1230 return DAG.getConstant(0, VT);
1231 // X / undef -> undef
1232 if (N1.getOpcode() == ISD::UNDEF)
1238 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
1239 SDOperand N0 = N->getOperand(0);
1240 SDOperand N1 = N->getOperand(1);
1241 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1242 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1243 MVT::ValueType VT = N->getValueType(0);
1246 if (MVT::isVector(VT)) {
1247 SDOperand FoldedVOp = SimplifyVBinOp(N);
1248 if (FoldedVOp.Val) return FoldedVOp;
1251 // fold (udiv c1, c2) -> c1/c2
1252 if (N0C && N1C && !N1C->isNullValue())
1253 return DAG.getNode(ISD::UDIV, VT, N0, N1);
1254 // fold (udiv x, (1 << c)) -> x >>u c
1255 if (N1C && isPowerOf2_64(N1C->getValue()))
1256 return DAG.getNode(ISD::SRL, VT, N0,
1257 DAG.getConstant(Log2_64(N1C->getValue()),
1258 TLI.getShiftAmountTy()));
1259 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1260 if (N1.getOpcode() == ISD::SHL) {
1261 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1262 if (isPowerOf2_64(SHC->getValue())) {
1263 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
1264 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
1265 DAG.getConstant(Log2_64(SHC->getValue()),
1267 AddToWorkList(Add.Val);
1268 return DAG.getNode(ISD::SRL, VT, N0, Add);
1272 // fold (udiv x, c) -> alternate
1273 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1274 SDOperand Op = BuildUDIV(N);
1275 if (Op.Val) return Op;
1279 if (N0.getOpcode() == ISD::UNDEF)
1280 return DAG.getConstant(0, VT);
1281 // X / undef -> undef
1282 if (N1.getOpcode() == ISD::UNDEF)
1288 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1289 SDOperand N0 = N->getOperand(0);
1290 SDOperand N1 = N->getOperand(1);
1291 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1292 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1293 MVT::ValueType VT = N->getValueType(0);
1295 // fold (srem c1, c2) -> c1%c2
1296 if (N0C && N1C && !N1C->isNullValue())
1297 return DAG.getNode(ISD::SREM, VT, N0, N1);
1298 // If we know the sign bits of both operands are zero, strength reduce to a
1299 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1300 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1301 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1302 DAG.MaskedValueIsZero(N0, SignBit))
1303 return DAG.getNode(ISD::UREM, VT, N0, N1);
1305 // If X/C can be simplified by the division-by-constant logic, lower
1306 // X%C to the equivalent of X-X/C*C.
1307 if (N1C && !N1C->isNullValue()) {
1308 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1309 SDOperand OptimizedDiv = combine(Div.Val);
1310 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
1311 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
1312 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1313 AddToWorkList(Mul.Val);
1319 if (N0.getOpcode() == ISD::UNDEF)
1320 return DAG.getConstant(0, VT);
1321 // X % undef -> undef
1322 if (N1.getOpcode() == ISD::UNDEF)
1328 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1329 SDOperand N0 = N->getOperand(0);
1330 SDOperand N1 = N->getOperand(1);
1331 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1332 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1333 MVT::ValueType VT = N->getValueType(0);
1335 // fold (urem c1, c2) -> c1%c2
1336 if (N0C && N1C && !N1C->isNullValue())
1337 return DAG.getNode(ISD::UREM, VT, N0, N1);
1338 // fold (urem x, pow2) -> (and x, pow2-1)
1339 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1340 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1341 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1342 if (N1.getOpcode() == ISD::SHL) {
1343 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1344 if (isPowerOf2_64(SHC->getValue())) {
1345 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1346 AddToWorkList(Add.Val);
1347 return DAG.getNode(ISD::AND, VT, N0, Add);
1352 // If X/C can be simplified by the division-by-constant logic, lower
1353 // X%C to the equivalent of X-X/C*C.
1354 if (N1C && !N1C->isNullValue()) {
1355 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1356 SDOperand OptimizedDiv = combine(Div.Val);
1357 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
1358 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
1359 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1360 AddToWorkList(Mul.Val);
1366 if (N0.getOpcode() == ISD::UNDEF)
1367 return DAG.getConstant(0, VT);
1368 // X % undef -> undef
1369 if (N1.getOpcode() == ISD::UNDEF)
1375 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1376 SDOperand N0 = N->getOperand(0);
1377 SDOperand N1 = N->getOperand(1);
1378 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1379 MVT::ValueType VT = N->getValueType(0);
1381 // fold (mulhs x, 0) -> 0
1382 if (N1C && N1C->isNullValue())
1384 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1385 if (N1C && N1C->getValue() == 1)
1386 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1387 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1388 TLI.getShiftAmountTy()));
1389 // fold (mulhs x, undef) -> 0
1390 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1391 return DAG.getConstant(0, VT);
1396 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1397 SDOperand N0 = N->getOperand(0);
1398 SDOperand N1 = N->getOperand(1);
1399 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1400 MVT::ValueType VT = N->getValueType(0);
1402 // fold (mulhu x, 0) -> 0
1403 if (N1C && N1C->isNullValue())
1405 // fold (mulhu x, 1) -> 0
1406 if (N1C && N1C->getValue() == 1)
1407 return DAG.getConstant(0, N0.getValueType());
1408 // fold (mulhu x, undef) -> 0
1409 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1410 return DAG.getConstant(0, VT);
1415 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1416 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1417 /// that are being performed. Return true if a simplification was made.
1419 bool DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N,
1420 unsigned LoOp, unsigned HiOp) {
1421 // If the high half is not needed, just compute the low half.
1422 bool HiExists = N->hasAnyUseOfValue(1);
1425 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1426 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0),
1427 DAG.getNode(LoOp, N->getValueType(0),
1429 N->getNumOperands()));
1433 // If the low half is not needed, just compute the high half.
1434 bool LoExists = N->hasAnyUseOfValue(0);
1437 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1438 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1),
1439 DAG.getNode(HiOp, N->getValueType(1),
1441 N->getNumOperands()));
1445 // If both halves are used, return as it is.
1446 if (LoExists && HiExists)
1449 // If the two computed results can be simplified separately, separate them.
1450 bool RetVal = false;
1452 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0),
1453 N->op_begin(), N->getNumOperands());
1454 SDOperand LoOpt = combine(Lo.Val);
1455 if (LoOpt.Val && LoOpt != Lo &&
1456 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) {
1458 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), LoOpt);
1460 DAG.DeleteNode(Lo.Val);
1464 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1),
1465 N->op_begin(), N->getNumOperands());
1466 SDOperand HiOpt = combine(Hi.Val);
1467 if (HiOpt.Val && HiOpt != Hi &&
1468 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) {
1470 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), HiOpt);
1472 DAG.DeleteNode(Hi.Val);
1478 SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1480 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
1486 SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1488 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
1494 SDOperand DAGCombiner::visitSDIVREM(SDNode *N) {
1496 if (SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM))
1502 SDOperand DAGCombiner::visitUDIVREM(SDNode *N) {
1504 if (SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM))
1510 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1511 /// two operands of the same opcode, try to simplify it.
1512 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1513 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1514 MVT::ValueType VT = N0.getValueType();
1515 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1517 // For each of OP in AND/OR/XOR:
1518 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1519 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1520 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1521 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1522 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1523 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1524 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1525 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1526 N0.getOperand(0).getValueType(),
1527 N0.getOperand(0), N1.getOperand(0));
1528 AddToWorkList(ORNode.Val);
1529 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1532 // For each of OP in SHL/SRL/SRA/AND...
1533 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1534 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1535 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1536 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1537 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1538 N0.getOperand(1) == N1.getOperand(1)) {
1539 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1540 N0.getOperand(0).getValueType(),
1541 N0.getOperand(0), N1.getOperand(0));
1542 AddToWorkList(ORNode.Val);
1543 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1549 SDOperand DAGCombiner::visitAND(SDNode *N) {
1550 SDOperand N0 = N->getOperand(0);
1551 SDOperand N1 = N->getOperand(1);
1552 SDOperand LL, LR, RL, RR, CC0, CC1;
1553 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1554 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1555 MVT::ValueType VT = N1.getValueType();
1558 if (MVT::isVector(VT)) {
1559 SDOperand FoldedVOp = SimplifyVBinOp(N);
1560 if (FoldedVOp.Val) return FoldedVOp;
1563 // fold (and x, undef) -> 0
1564 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1565 return DAG.getConstant(0, VT);
1566 // fold (and c1, c2) -> c1&c2
1568 return DAG.getNode(ISD::AND, VT, N0, N1);
1569 // canonicalize constant to RHS
1571 return DAG.getNode(ISD::AND, VT, N1, N0);
1572 // fold (and x, -1) -> x
1573 if (N1C && N1C->isAllOnesValue())
1575 // if (and x, c) is known to be zero, return 0
1576 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1577 return DAG.getConstant(0, VT);
1579 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1582 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1583 if (N1C && N0.getOpcode() == ISD::OR)
1584 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1585 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1587 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1588 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1589 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1590 if (DAG.MaskedValueIsZero(N0.getOperand(0),
1591 ~N1C->getValue() & InMask)) {
1592 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1595 // Replace uses of the AND with uses of the Zero extend node.
1598 // We actually want to replace all uses of the any_extend with the
1599 // zero_extend, to avoid duplicating things. This will later cause this
1600 // AND to be folded.
1601 CombineTo(N0.Val, Zext);
1602 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1605 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1606 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1607 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1608 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1610 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1611 MVT::isInteger(LL.getValueType())) {
1612 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1613 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1614 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1615 AddToWorkList(ORNode.Val);
1616 return DAG.getSetCC(VT, ORNode, LR, Op1);
1618 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1619 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1620 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1621 AddToWorkList(ANDNode.Val);
1622 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1624 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1625 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1626 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1627 AddToWorkList(ORNode.Val);
1628 return DAG.getSetCC(VT, ORNode, LR, Op1);
1631 // canonicalize equivalent to ll == rl
1632 if (LL == RR && LR == RL) {
1633 Op1 = ISD::getSetCCSwappedOperands(Op1);
1636 if (LL == RL && LR == RR) {
1637 bool isInteger = MVT::isInteger(LL.getValueType());
1638 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1639 if (Result != ISD::SETCC_INVALID)
1640 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1644 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1645 if (N0.getOpcode() == N1.getOpcode()) {
1646 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1647 if (Tmp.Val) return Tmp;
1650 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1651 // fold (and (sra)) -> (and (srl)) when possible.
1652 if (!MVT::isVector(VT) &&
1653 SimplifyDemandedBits(SDOperand(N, 0)))
1654 return SDOperand(N, 0);
1655 // fold (zext_inreg (extload x)) -> (zextload x)
1656 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
1657 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1658 MVT::ValueType EVT = LN0->getLoadedVT();
1659 // If we zero all the possible extended bits, then we can turn this into
1660 // a zextload if we are running before legalize or the operation is legal.
1661 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1662 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1663 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1664 LN0->getBasePtr(), LN0->getSrcValue(),
1665 LN0->getSrcValueOffset(), EVT,
1667 LN0->getAlignment());
1669 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1670 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1673 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1674 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
1676 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1677 MVT::ValueType EVT = LN0->getLoadedVT();
1678 // If we zero all the possible extended bits, then we can turn this into
1679 // a zextload if we are running before legalize or the operation is legal.
1680 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1681 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1682 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1683 LN0->getBasePtr(), LN0->getSrcValue(),
1684 LN0->getSrcValueOffset(), EVT,
1686 LN0->getAlignment());
1688 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1689 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1693 // fold (and (load x), 255) -> (zextload x, i8)
1694 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1695 if (N1C && N0.getOpcode() == ISD::LOAD) {
1696 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1697 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1698 LN0->isUnindexed() && N0.hasOneUse()) {
1699 MVT::ValueType EVT, LoadedVT;
1700 if (N1C->getValue() == 255)
1702 else if (N1C->getValue() == 65535)
1704 else if (N1C->getValue() == ~0U)
1709 LoadedVT = LN0->getLoadedVT();
1710 if (EVT != MVT::Other && LoadedVT > EVT &&
1711 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1712 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1713 // For big endian targets, we need to add an offset to the pointer to
1714 // load the correct bytes. For little endian systems, we merely need to
1715 // read fewer bytes from the same pointer.
1716 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8;
1717 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8;
1718 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
1719 unsigned Alignment = LN0->getAlignment();
1720 SDOperand NewPtr = LN0->getBasePtr();
1721 if (!TLI.isLittleEndian()) {
1722 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1723 DAG.getConstant(PtrOff, PtrType));
1724 Alignment = MinAlign(Alignment, PtrOff);
1726 AddToWorkList(NewPtr.Val);
1728 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1729 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
1730 LN0->isVolatile(), Alignment);
1732 CombineTo(N0.Val, Load, Load.getValue(1));
1733 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1741 SDOperand DAGCombiner::visitOR(SDNode *N) {
1742 SDOperand N0 = N->getOperand(0);
1743 SDOperand N1 = N->getOperand(1);
1744 SDOperand LL, LR, RL, RR, CC0, CC1;
1745 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1746 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1747 MVT::ValueType VT = N1.getValueType();
1748 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1751 if (MVT::isVector(VT)) {
1752 SDOperand FoldedVOp = SimplifyVBinOp(N);
1753 if (FoldedVOp.Val) return FoldedVOp;
1756 // fold (or x, undef) -> -1
1757 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1758 return DAG.getConstant(~0ULL, VT);
1759 // fold (or c1, c2) -> c1|c2
1761 return DAG.getNode(ISD::OR, VT, N0, N1);
1762 // canonicalize constant to RHS
1764 return DAG.getNode(ISD::OR, VT, N1, N0);
1765 // fold (or x, 0) -> x
1766 if (N1C && N1C->isNullValue())
1768 // fold (or x, -1) -> -1
1769 if (N1C && N1C->isAllOnesValue())
1771 // fold (or x, c) -> c iff (x & ~c) == 0
1773 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1776 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1779 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1780 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1781 isa<ConstantSDNode>(N0.getOperand(1))) {
1782 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1783 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1785 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1787 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1788 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1789 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1790 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1792 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1793 MVT::isInteger(LL.getValueType())) {
1794 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1795 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1796 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1797 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1798 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1799 AddToWorkList(ORNode.Val);
1800 return DAG.getSetCC(VT, ORNode, LR, Op1);
1802 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1803 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1804 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1805 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1806 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1807 AddToWorkList(ANDNode.Val);
1808 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1811 // canonicalize equivalent to ll == rl
1812 if (LL == RR && LR == RL) {
1813 Op1 = ISD::getSetCCSwappedOperands(Op1);
1816 if (LL == RL && LR == RR) {
1817 bool isInteger = MVT::isInteger(LL.getValueType());
1818 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1819 if (Result != ISD::SETCC_INVALID)
1820 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1824 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1825 if (N0.getOpcode() == N1.getOpcode()) {
1826 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1827 if (Tmp.Val) return Tmp;
1830 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1831 if (N0.getOpcode() == ISD::AND &&
1832 N1.getOpcode() == ISD::AND &&
1833 N0.getOperand(1).getOpcode() == ISD::Constant &&
1834 N1.getOperand(1).getOpcode() == ISD::Constant &&
1835 // Don't increase # computations.
1836 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1837 // We can only do this xform if we know that bits from X that are set in C2
1838 // but not in C1 are already zero. Likewise for Y.
1839 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1840 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1842 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1843 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1844 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1845 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1850 // See if this is some rotate idiom.
1851 if (SDNode *Rot = MatchRotate(N0, N1))
1852 return SDOperand(Rot, 0);
1858 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1859 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1860 if (Op.getOpcode() == ISD::AND) {
1861 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1862 Mask = Op.getOperand(1);
1863 Op = Op.getOperand(0);
1869 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1877 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1878 // idioms for rotate, and if the target supports rotation instructions, generate
1880 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1881 // Must be a legal type. Expanded an promoted things won't work with rotates.
1882 MVT::ValueType VT = LHS.getValueType();
1883 if (!TLI.isTypeLegal(VT)) return 0;
1885 // The target must have at least one rotate flavor.
1886 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1887 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1888 if (!HasROTL && !HasROTR) return 0;
1890 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1891 SDOperand LHSShift; // The shift.
1892 SDOperand LHSMask; // AND value if any.
1893 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1894 return 0; // Not part of a rotate.
1896 SDOperand RHSShift; // The shift.
1897 SDOperand RHSMask; // AND value if any.
1898 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1899 return 0; // Not part of a rotate.
1901 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1902 return 0; // Not shifting the same value.
1904 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1905 return 0; // Shifts must disagree.
1907 // Canonicalize shl to left side in a shl/srl pair.
1908 if (RHSShift.getOpcode() == ISD::SHL) {
1909 std::swap(LHS, RHS);
1910 std::swap(LHSShift, RHSShift);
1911 std::swap(LHSMask , RHSMask );
1914 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1915 SDOperand LHSShiftArg = LHSShift.getOperand(0);
1916 SDOperand LHSShiftAmt = LHSShift.getOperand(1);
1917 SDOperand RHSShiftAmt = RHSShift.getOperand(1);
1919 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1920 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1921 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
1922 RHSShiftAmt.getOpcode() == ISD::Constant) {
1923 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
1924 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
1925 if ((LShVal + RShVal) != OpSizeInBits)
1930 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
1932 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
1934 // If there is an AND of either shifted operand, apply it to the result.
1935 if (LHSMask.Val || RHSMask.Val) {
1936 uint64_t Mask = MVT::getIntVTBitMask(VT);
1939 uint64_t RHSBits = (1ULL << LShVal)-1;
1940 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1943 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1944 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1947 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1953 // If there is a mask here, and we have a variable shift, we can't be sure
1954 // that we're masking out the right stuff.
1955 if (LHSMask.Val || RHSMask.Val)
1958 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1959 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1960 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
1961 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
1962 if (ConstantSDNode *SUBC =
1963 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
1964 if (SUBC->getValue() == OpSizeInBits)
1966 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1968 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1972 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1973 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1974 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
1975 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
1976 if (ConstantSDNode *SUBC =
1977 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
1978 if (SUBC->getValue() == OpSizeInBits)
1980 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1982 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1986 // Look for sign/zext/any-extended cases:
1987 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1988 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1989 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
1990 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1991 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1992 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
1993 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
1994 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
1995 if (RExtOp0.getOpcode() == ISD::SUB &&
1996 RExtOp0.getOperand(1) == LExtOp0) {
1997 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1999 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2000 // (rotl x, (sub 32, y))
2001 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2002 if (SUBC->getValue() == OpSizeInBits) {
2004 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2006 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
2009 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2010 RExtOp0 == LExtOp0.getOperand(1)) {
2011 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2013 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2014 // (rotr x, (sub 32, y))
2015 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2016 if (SUBC->getValue() == OpSizeInBits) {
2018 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
2020 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2030 SDOperand DAGCombiner::visitXOR(SDNode *N) {
2031 SDOperand N0 = N->getOperand(0);
2032 SDOperand N1 = N->getOperand(1);
2033 SDOperand LHS, RHS, CC;
2034 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2035 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2036 MVT::ValueType VT = N0.getValueType();
2039 if (MVT::isVector(VT)) {
2040 SDOperand FoldedVOp = SimplifyVBinOp(N);
2041 if (FoldedVOp.Val) return FoldedVOp;
2044 // fold (xor x, undef) -> undef
2045 if (N0.getOpcode() == ISD::UNDEF)
2047 if (N1.getOpcode() == ISD::UNDEF)
2049 // fold (xor c1, c2) -> c1^c2
2051 return DAG.getNode(ISD::XOR, VT, N0, N1);
2052 // canonicalize constant to RHS
2054 return DAG.getNode(ISD::XOR, VT, N1, N0);
2055 // fold (xor x, 0) -> x
2056 if (N1C && N1C->isNullValue())
2059 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
2062 // fold !(x cc y) -> (x !cc y)
2063 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2064 bool isInt = MVT::isInteger(LHS.getValueType());
2065 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2067 if (N0.getOpcode() == ISD::SETCC)
2068 return DAG.getSetCC(VT, LHS, RHS, NotCC);
2069 if (N0.getOpcode() == ISD::SELECT_CC)
2070 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
2071 assert(0 && "Unhandled SetCC Equivalent!");
2074 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2075 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2076 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2077 SDOperand V = N0.getOperand(0);
2078 V = DAG.getNode(ISD::XOR, V.getValueType(), V,
2079 DAG.getConstant(1, V.getValueType()));
2080 AddToWorkList(V.Val);
2081 return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
2084 // fold !(x or y) -> (!x and !y) iff x or y are setcc
2085 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
2086 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2087 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2088 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2089 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2090 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2091 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2092 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2093 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2096 // fold !(x or y) -> (!x and !y) iff x or y are constants
2097 if (N1C && N1C->isAllOnesValue() &&
2098 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2099 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2100 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2101 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2102 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2103 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2104 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2105 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2108 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
2109 if (N1C && N0.getOpcode() == ISD::XOR) {
2110 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2111 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2113 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
2114 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
2116 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
2117 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
2119 // fold (xor x, x) -> 0
2121 if (!MVT::isVector(VT)) {
2122 return DAG.getConstant(0, VT);
2123 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
2124 // Produce a vector of zeros.
2125 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
2126 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
2127 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2131 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2132 if (N0.getOpcode() == N1.getOpcode()) {
2133 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2134 if (Tmp.Val) return Tmp;
2137 // Simplify the expression using non-local knowledge.
2138 if (!MVT::isVector(VT) &&
2139 SimplifyDemandedBits(SDOperand(N, 0)))
2140 return SDOperand(N, 0);
2145 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2146 /// the shift amount is a constant.
2147 SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2148 SDNode *LHS = N->getOperand(0).Val;
2149 if (!LHS->hasOneUse()) return SDOperand();
2151 // We want to pull some binops through shifts, so that we have (and (shift))
2152 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2153 // thing happens with address calculations, so it's important to canonicalize
2155 bool HighBitSet = false; // Can we transform this if the high bit is set?
2157 switch (LHS->getOpcode()) {
2158 default: return SDOperand();
2161 HighBitSet = false; // We can only transform sra if the high bit is clear.
2164 HighBitSet = true; // We can only transform sra if the high bit is set.
2167 if (N->getOpcode() != ISD::SHL)
2168 return SDOperand(); // only shl(add) not sr[al](add).
2169 HighBitSet = false; // We can only transform sra if the high bit is clear.
2173 // We require the RHS of the binop to be a constant as well.
2174 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2175 if (!BinOpCst) return SDOperand();
2178 // FIXME: disable this for unless the input to the binop is a shift by a
2179 // constant. If it is not a shift, it pessimizes some common cases like:
2181 //void foo(int *X, int i) { X[i & 1235] = 1; }
2182 //int bar(int *X, int i) { return X[i & 255]; }
2183 SDNode *BinOpLHSVal = LHS->getOperand(0).Val;
2184 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2185 BinOpLHSVal->getOpcode() != ISD::SRA &&
2186 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2187 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2190 MVT::ValueType VT = N->getValueType(0);
2192 // If this is a signed shift right, and the high bit is modified
2193 // by the logical operation, do not perform the transformation.
2194 // The highBitSet boolean indicates the value of the high bit of
2195 // the constant which would cause it to be modified for this
2197 if (N->getOpcode() == ISD::SRA) {
2198 uint64_t BinOpRHSSign = BinOpCst->getValue() >> MVT::getSizeInBits(VT)-1;
2199 if ((bool)BinOpRHSSign != HighBitSet)
2203 // Fold the constants, shifting the binop RHS by the shift amount.
2204 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0),
2205 LHS->getOperand(1), N->getOperand(1));
2207 // Create the new shift.
2208 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0),
2211 // Create the new binop.
2212 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS);
2216 SDOperand DAGCombiner::visitSHL(SDNode *N) {
2217 SDOperand N0 = N->getOperand(0);
2218 SDOperand N1 = N->getOperand(1);
2219 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2220 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2221 MVT::ValueType VT = N0.getValueType();
2222 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2224 // fold (shl c1, c2) -> c1<<c2
2226 return DAG.getNode(ISD::SHL, VT, N0, N1);
2227 // fold (shl 0, x) -> 0
2228 if (N0C && N0C->isNullValue())
2230 // fold (shl x, c >= size(x)) -> undef
2231 if (N1C && N1C->getValue() >= OpSizeInBits)
2232 return DAG.getNode(ISD::UNDEF, VT);
2233 // fold (shl x, 0) -> x
2234 if (N1C && N1C->isNullValue())
2236 // if (shl x, c) is known to be zero, return 0
2237 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
2238 return DAG.getConstant(0, VT);
2239 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2240 return SDOperand(N, 0);
2241 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
2242 if (N1C && N0.getOpcode() == ISD::SHL &&
2243 N0.getOperand(1).getOpcode() == ISD::Constant) {
2244 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2245 uint64_t c2 = N1C->getValue();
2246 if (c1 + c2 > OpSizeInBits)
2247 return DAG.getConstant(0, VT);
2248 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
2249 DAG.getConstant(c1 + c2, N1.getValueType()));
2251 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
2252 // (srl (and x, -1 << c1), c1-c2)
2253 if (N1C && N0.getOpcode() == ISD::SRL &&
2254 N0.getOperand(1).getOpcode() == ISD::Constant) {
2255 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2256 uint64_t c2 = N1C->getValue();
2257 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2258 DAG.getConstant(~0ULL << c1, VT));
2260 return DAG.getNode(ISD::SHL, VT, Mask,
2261 DAG.getConstant(c2-c1, N1.getValueType()));
2263 return DAG.getNode(ISD::SRL, VT, Mask,
2264 DAG.getConstant(c1-c2, N1.getValueType()));
2266 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
2267 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2268 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2269 DAG.getConstant(~0ULL << N1C->getValue(), VT));
2271 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2274 SDOperand DAGCombiner::visitSRA(SDNode *N) {
2275 SDOperand N0 = N->getOperand(0);
2276 SDOperand N1 = N->getOperand(1);
2277 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2278 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2279 MVT::ValueType VT = N0.getValueType();
2281 // fold (sra c1, c2) -> c1>>c2
2283 return DAG.getNode(ISD::SRA, VT, N0, N1);
2284 // fold (sra 0, x) -> 0
2285 if (N0C && N0C->isNullValue())
2287 // fold (sra -1, x) -> -1
2288 if (N0C && N0C->isAllOnesValue())
2290 // fold (sra x, c >= size(x)) -> undef
2291 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
2292 return DAG.getNode(ISD::UNDEF, VT);
2293 // fold (sra x, 0) -> x
2294 if (N1C && N1C->isNullValue())
2296 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2298 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2299 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
2302 default: EVT = MVT::Other; break;
2303 case 1: EVT = MVT::i1; break;
2304 case 8: EVT = MVT::i8; break;
2305 case 16: EVT = MVT::i16; break;
2306 case 32: EVT = MVT::i32; break;
2308 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
2309 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
2310 DAG.getValueType(EVT));
2313 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
2314 if (N1C && N0.getOpcode() == ISD::SRA) {
2315 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2316 unsigned Sum = N1C->getValue() + C1->getValue();
2317 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
2318 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
2319 DAG.getConstant(Sum, N1C->getValueType(0)));
2323 // Simplify, based on bits shifted out of the LHS.
2324 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2325 return SDOperand(N, 0);
2328 // If the sign bit is known to be zero, switch this to a SRL.
2329 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
2330 return DAG.getNode(ISD::SRL, VT, N0, N1);
2332 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2335 SDOperand DAGCombiner::visitSRL(SDNode *N) {
2336 SDOperand N0 = N->getOperand(0);
2337 SDOperand N1 = N->getOperand(1);
2338 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2339 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2340 MVT::ValueType VT = N0.getValueType();
2341 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2343 // fold (srl c1, c2) -> c1 >>u c2
2345 return DAG.getNode(ISD::SRL, VT, N0, N1);
2346 // fold (srl 0, x) -> 0
2347 if (N0C && N0C->isNullValue())
2349 // fold (srl x, c >= size(x)) -> undef
2350 if (N1C && N1C->getValue() >= OpSizeInBits)
2351 return DAG.getNode(ISD::UNDEF, VT);
2352 // fold (srl x, 0) -> x
2353 if (N1C && N1C->isNullValue())
2355 // if (srl x, c) is known to be zero, return 0
2356 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
2357 return DAG.getConstant(0, VT);
2359 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
2360 if (N1C && N0.getOpcode() == ISD::SRL &&
2361 N0.getOperand(1).getOpcode() == ISD::Constant) {
2362 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2363 uint64_t c2 = N1C->getValue();
2364 if (c1 + c2 > OpSizeInBits)
2365 return DAG.getConstant(0, VT);
2366 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
2367 DAG.getConstant(c1 + c2, N1.getValueType()));
2370 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2371 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2372 // Shifting in all undef bits?
2373 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
2374 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
2375 return DAG.getNode(ISD::UNDEF, VT);
2377 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
2378 AddToWorkList(SmallShift.Val);
2379 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
2382 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2383 // bit, which is unmodified by sra.
2384 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
2385 if (N0.getOpcode() == ISD::SRA)
2386 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
2389 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2390 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2391 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
2392 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
2393 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2395 // If any of the input bits are KnownOne, then the input couldn't be all
2396 // zeros, thus the result of the srl will always be zero.
2397 if (KnownOne) return DAG.getConstant(0, VT);
2399 // If all of the bits input the to ctlz node are known to be zero, then
2400 // the result of the ctlz is "32" and the result of the shift is one.
2401 uint64_t UnknownBits = ~KnownZero & Mask;
2402 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2404 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2405 if ((UnknownBits & (UnknownBits-1)) == 0) {
2406 // Okay, we know that only that the single bit specified by UnknownBits
2407 // could be set on input to the CTLZ node. If this bit is set, the SRL
2408 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2409 // to an SRL,XOR pair, which is likely to simplify more.
2410 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
2411 SDOperand Op = N0.getOperand(0);
2413 Op = DAG.getNode(ISD::SRL, VT, Op,
2414 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
2415 AddToWorkList(Op.Val);
2417 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
2421 // fold operands of srl based on knowledge that the low bits are not
2423 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2424 return SDOperand(N, 0);
2426 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2429 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
2430 SDOperand N0 = N->getOperand(0);
2431 MVT::ValueType VT = N->getValueType(0);
2433 // fold (ctlz c1) -> c2
2434 if (isa<ConstantSDNode>(N0))
2435 return DAG.getNode(ISD::CTLZ, VT, N0);
2439 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
2440 SDOperand N0 = N->getOperand(0);
2441 MVT::ValueType VT = N->getValueType(0);
2443 // fold (cttz c1) -> c2
2444 if (isa<ConstantSDNode>(N0))
2445 return DAG.getNode(ISD::CTTZ, VT, N0);
2449 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
2450 SDOperand N0 = N->getOperand(0);
2451 MVT::ValueType VT = N->getValueType(0);
2453 // fold (ctpop c1) -> c2
2454 if (isa<ConstantSDNode>(N0))
2455 return DAG.getNode(ISD::CTPOP, VT, N0);
2459 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
2460 SDOperand N0 = N->getOperand(0);
2461 SDOperand N1 = N->getOperand(1);
2462 SDOperand N2 = N->getOperand(2);
2463 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2464 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2465 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2466 MVT::ValueType VT = N->getValueType(0);
2467 MVT::ValueType VT0 = N0.getValueType();
2469 // fold select C, X, X -> X
2472 // fold select true, X, Y -> X
2473 if (N0C && !N0C->isNullValue())
2475 // fold select false, X, Y -> Y
2476 if (N0C && N0C->isNullValue())
2478 // fold select C, 1, X -> C | X
2479 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
2480 return DAG.getNode(ISD::OR, VT, N0, N2);
2481 // fold select C, 0, 1 -> ~C
2482 if (MVT::isInteger(VT) && MVT::isInteger(VT0) &&
2483 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) {
2484 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
2487 AddToWorkList(XORNode.Val);
2488 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0))
2489 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
2490 return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
2492 // fold select C, 0, X -> ~C & X
2493 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2494 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2495 AddToWorkList(XORNode.Val);
2496 return DAG.getNode(ISD::AND, VT, XORNode, N2);
2498 // fold select C, X, 1 -> ~C | X
2499 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getValue() == 1) {
2500 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2501 AddToWorkList(XORNode.Val);
2502 return DAG.getNode(ISD::OR, VT, XORNode, N1);
2504 // fold select C, X, 0 -> C & X
2505 // FIXME: this should check for C type == X type, not i1?
2506 if (MVT::i1 == VT && N2C && N2C->isNullValue())
2507 return DAG.getNode(ISD::AND, VT, N0, N1);
2508 // fold X ? X : Y --> X ? 1 : Y --> X | Y
2509 if (MVT::i1 == VT && N0 == N1)
2510 return DAG.getNode(ISD::OR, VT, N0, N2);
2511 // fold X ? Y : X --> X ? Y : 0 --> X & Y
2512 if (MVT::i1 == VT && N0 == N2)
2513 return DAG.getNode(ISD::AND, VT, N0, N1);
2515 // If we can fold this based on the true/false value, do so.
2516 if (SimplifySelectOps(N, N1, N2))
2517 return SDOperand(N, 0); // Don't revisit N.
2519 // fold selects based on a setcc into other things, such as min/max/abs
2520 if (N0.getOpcode() == ISD::SETCC)
2522 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2523 // having to say they don't support SELECT_CC on every type the DAG knows
2524 // about, since there is no way to mark an opcode illegal at all value types
2525 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
2526 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
2527 N1, N2, N0.getOperand(2));
2529 return SimplifySelect(N0, N1, N2);
2533 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
2534 SDOperand N0 = N->getOperand(0);
2535 SDOperand N1 = N->getOperand(1);
2536 SDOperand N2 = N->getOperand(2);
2537 SDOperand N3 = N->getOperand(3);
2538 SDOperand N4 = N->getOperand(4);
2539 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2541 // fold select_cc lhs, rhs, x, x, cc -> x
2545 // Determine if the condition we're dealing with is constant
2546 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2547 if (SCC.Val) AddToWorkList(SCC.Val);
2549 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
2550 if (SCCC->getValue())
2551 return N2; // cond always true -> true val
2553 return N3; // cond always false -> false val
2556 // Fold to a simpler select_cc
2557 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2558 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
2559 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2562 // If we can fold this based on the true/false value, do so.
2563 if (SimplifySelectOps(N, N2, N3))
2564 return SDOperand(N, 0); // Don't revisit N.
2566 // fold select_cc into other things, such as min/max/abs
2567 return SimplifySelectCC(N0, N1, N2, N3, CC);
2570 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
2571 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2572 cast<CondCodeSDNode>(N->getOperand(2))->get());
2575 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
2576 // "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))"
2577 // transformation. Returns true if extension are possible and the above
2578 // mentioned transformation is profitable.
2579 static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0,
2581 SmallVector<SDNode*, 4> &ExtendNodes,
2582 TargetLowering &TLI) {
2583 bool HasCopyToRegUses = false;
2584 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
2585 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end();
2590 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
2591 if (User->getOpcode() == ISD::SETCC) {
2592 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
2593 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
2594 // Sign bits will be lost after a zext.
2597 for (unsigned i = 0; i != 2; ++i) {
2598 SDOperand UseOp = User->getOperand(i);
2601 if (!isa<ConstantSDNode>(UseOp))
2606 ExtendNodes.push_back(User);
2608 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2609 SDOperand UseOp = User->getOperand(i);
2611 // If truncate from extended type to original load type is free
2612 // on this target, then it's ok to extend a CopyToReg.
2613 if (isTruncFree && User->getOpcode() == ISD::CopyToReg)
2614 HasCopyToRegUses = true;
2622 if (HasCopyToRegUses) {
2623 bool BothLiveOut = false;
2624 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
2627 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2628 SDOperand UseOp = User->getOperand(i);
2629 if (UseOp.Val == N && UseOp.ResNo == 0) {
2636 // Both unextended and extended values are live out. There had better be
2637 // good a reason for the transformation.
2638 return ExtendNodes.size();
2643 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2644 SDOperand N0 = N->getOperand(0);
2645 MVT::ValueType VT = N->getValueType(0);
2647 // fold (sext c1) -> c1
2648 if (isa<ConstantSDNode>(N0))
2649 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2651 // fold (sext (sext x)) -> (sext x)
2652 // fold (sext (aext x)) -> (sext x)
2653 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2654 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2656 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2657 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2658 if (N0.getOpcode() == ISD::TRUNCATE) {
2659 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2660 if (NarrowLoad.Val) {
2661 if (NarrowLoad.Val != N0.Val)
2662 CombineTo(N0.Val, NarrowLoad);
2663 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
2667 // See if the value being truncated is already sign extended. If so, just
2668 // eliminate the trunc/sext pair.
2669 if (N0.getOpcode() == ISD::TRUNCATE) {
2670 SDOperand Op = N0.getOperand(0);
2671 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2672 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2673 unsigned DestBits = MVT::getSizeInBits(VT);
2674 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2676 if (OpBits == DestBits) {
2677 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2678 // bits, it is already ready.
2679 if (NumSignBits > DestBits-MidBits)
2681 } else if (OpBits < DestBits) {
2682 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2683 // bits, just sext from i32.
2684 if (NumSignBits > OpBits-MidBits)
2685 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2687 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2688 // bits, just truncate to i32.
2689 if (NumSignBits > OpBits-MidBits)
2690 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2693 // fold (sext (truncate x)) -> (sextinreg x).
2694 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2695 N0.getValueType())) {
2696 if (Op.getValueType() < VT)
2697 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2698 else if (Op.getValueType() > VT)
2699 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2700 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2701 DAG.getValueType(N0.getValueType()));
2705 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2706 if (ISD::isNON_EXTLoad(N0.Val) &&
2707 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2708 bool DoXform = true;
2709 SmallVector<SDNode*, 4> SetCCs;
2710 if (!N0.hasOneUse())
2711 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
2713 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2714 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2715 LN0->getBasePtr(), LN0->getSrcValue(),
2716 LN0->getSrcValueOffset(),
2719 LN0->getAlignment());
2720 CombineTo(N, ExtLoad);
2721 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
2722 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
2723 // Extend SetCC uses if necessary.
2724 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
2725 SDNode *SetCC = SetCCs[i];
2726 SmallVector<SDOperand, 4> Ops;
2727 for (unsigned j = 0; j != 2; ++j) {
2728 SDOperand SOp = SetCC->getOperand(j);
2730 Ops.push_back(ExtLoad);
2732 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp));
2734 Ops.push_back(SetCC->getOperand(2));
2735 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
2736 &Ops[0], Ops.size()));
2738 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2742 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2743 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2744 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2745 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2746 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2747 MVT::ValueType EVT = LN0->getLoadedVT();
2748 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2749 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2750 LN0->getBasePtr(), LN0->getSrcValue(),
2751 LN0->getSrcValueOffset(), EVT,
2753 LN0->getAlignment());
2754 CombineTo(N, ExtLoad);
2755 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2756 ExtLoad.getValue(1));
2757 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2761 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
2762 if (N0.getOpcode() == ISD::SETCC) {
2764 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2765 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
2766 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2767 if (SCC.Val) return SCC;
2773 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2774 SDOperand N0 = N->getOperand(0);
2775 MVT::ValueType VT = N->getValueType(0);
2777 // fold (zext c1) -> c1
2778 if (isa<ConstantSDNode>(N0))
2779 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2780 // fold (zext (zext x)) -> (zext x)
2781 // fold (zext (aext x)) -> (zext x)
2782 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2783 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2785 // fold (zext (truncate (load x))) -> (zext (smaller load x))
2786 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
2787 if (N0.getOpcode() == ISD::TRUNCATE) {
2788 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2789 if (NarrowLoad.Val) {
2790 if (NarrowLoad.Val != N0.Val)
2791 CombineTo(N0.Val, NarrowLoad);
2792 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
2796 // fold (zext (truncate x)) -> (and x, mask)
2797 if (N0.getOpcode() == ISD::TRUNCATE &&
2798 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2799 SDOperand Op = N0.getOperand(0);
2800 if (Op.getValueType() < VT) {
2801 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2802 } else if (Op.getValueType() > VT) {
2803 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2805 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2808 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2809 if (N0.getOpcode() == ISD::AND &&
2810 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2811 N0.getOperand(1).getOpcode() == ISD::Constant) {
2812 SDOperand X = N0.getOperand(0).getOperand(0);
2813 if (X.getValueType() < VT) {
2814 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2815 } else if (X.getValueType() > VT) {
2816 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2818 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2819 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2822 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2823 if (ISD::isNON_EXTLoad(N0.Val) &&
2824 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2825 bool DoXform = true;
2826 SmallVector<SDNode*, 4> SetCCs;
2827 if (!N0.hasOneUse())
2828 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
2830 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2831 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2832 LN0->getBasePtr(), LN0->getSrcValue(),
2833 LN0->getSrcValueOffset(),
2836 LN0->getAlignment());
2837 CombineTo(N, ExtLoad);
2838 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
2839 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
2840 // Extend SetCC uses if necessary.
2841 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
2842 SDNode *SetCC = SetCCs[i];
2843 SmallVector<SDOperand, 4> Ops;
2844 for (unsigned j = 0; j != 2; ++j) {
2845 SDOperand SOp = SetCC->getOperand(j);
2847 Ops.push_back(ExtLoad);
2849 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp));
2851 Ops.push_back(SetCC->getOperand(2));
2852 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
2853 &Ops[0], Ops.size()));
2855 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2859 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2860 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2861 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2862 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2863 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2864 MVT::ValueType EVT = LN0->getLoadedVT();
2865 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2866 LN0->getBasePtr(), LN0->getSrcValue(),
2867 LN0->getSrcValueOffset(), EVT,
2869 LN0->getAlignment());
2870 CombineTo(N, ExtLoad);
2871 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2872 ExtLoad.getValue(1));
2873 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2876 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2877 if (N0.getOpcode() == ISD::SETCC) {
2879 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2880 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2881 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2882 if (SCC.Val) return SCC;
2888 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2889 SDOperand N0 = N->getOperand(0);
2890 MVT::ValueType VT = N->getValueType(0);
2892 // fold (aext c1) -> c1
2893 if (isa<ConstantSDNode>(N0))
2894 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2895 // fold (aext (aext x)) -> (aext x)
2896 // fold (aext (zext x)) -> (zext x)
2897 // fold (aext (sext x)) -> (sext x)
2898 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2899 N0.getOpcode() == ISD::ZERO_EXTEND ||
2900 N0.getOpcode() == ISD::SIGN_EXTEND)
2901 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2903 // fold (aext (truncate (load x))) -> (aext (smaller load x))
2904 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
2905 if (N0.getOpcode() == ISD::TRUNCATE) {
2906 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2907 if (NarrowLoad.Val) {
2908 if (NarrowLoad.Val != N0.Val)
2909 CombineTo(N0.Val, NarrowLoad);
2910 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
2914 // fold (aext (truncate x))
2915 if (N0.getOpcode() == ISD::TRUNCATE) {
2916 SDOperand TruncOp = N0.getOperand(0);
2917 if (TruncOp.getValueType() == VT)
2918 return TruncOp; // x iff x size == zext size.
2919 if (TruncOp.getValueType() > VT)
2920 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2921 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2924 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2925 if (N0.getOpcode() == ISD::AND &&
2926 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2927 N0.getOperand(1).getOpcode() == ISD::Constant) {
2928 SDOperand X = N0.getOperand(0).getOperand(0);
2929 if (X.getValueType() < VT) {
2930 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2931 } else if (X.getValueType() > VT) {
2932 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2934 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2935 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2938 // fold (aext (load x)) -> (aext (truncate (extload x)))
2939 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2940 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2941 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2942 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2943 LN0->getBasePtr(), LN0->getSrcValue(),
2944 LN0->getSrcValueOffset(),
2947 LN0->getAlignment());
2948 CombineTo(N, ExtLoad);
2949 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2950 ExtLoad.getValue(1));
2951 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2954 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2955 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2956 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2957 if (N0.getOpcode() == ISD::LOAD &&
2958 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2960 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2961 MVT::ValueType EVT = LN0->getLoadedVT();
2962 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2963 LN0->getChain(), LN0->getBasePtr(),
2965 LN0->getSrcValueOffset(), EVT,
2967 LN0->getAlignment());
2968 CombineTo(N, ExtLoad);
2969 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2970 ExtLoad.getValue(1));
2971 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2974 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2975 if (N0.getOpcode() == ISD::SETCC) {
2977 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2978 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2979 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2987 /// GetDemandedBits - See if the specified operand can be simplified with the
2988 /// knowledge that only the bits specified by Mask are used. If so, return the
2989 /// simpler operand, otherwise return a null SDOperand.
2990 SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) {
2991 switch (V.getOpcode()) {
2995 // If the LHS or RHS don't contribute bits to the or, drop them.
2996 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
2997 return V.getOperand(1);
2998 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
2999 return V.getOperand(0);
3002 // Only look at single-use SRLs.
3003 if (!V.Val->hasOneUse())
3005 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3006 // See if we can recursively simplify the LHS.
3007 unsigned Amt = RHSC->getValue();
3008 Mask = (Mask << Amt) & MVT::getIntVTBitMask(V.getValueType());
3009 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), Mask);
3010 if (SimplifyLHS.Val) {
3011 return DAG.getNode(ISD::SRL, V.getValueType(),
3012 SimplifyLHS, V.getOperand(1));
3019 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3020 /// bits and then truncated to a narrower type and where N is a multiple
3021 /// of number of bits of the narrower type, transform it to a narrower load
3022 /// from address + N / num of bits of new type. If the result is to be
3023 /// extended, also fold the extension to form a extending load.
3024 SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
3025 unsigned Opc = N->getOpcode();
3026 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3027 SDOperand N0 = N->getOperand(0);
3028 MVT::ValueType VT = N->getValueType(0);
3029 MVT::ValueType EVT = N->getValueType(0);
3031 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
3033 if (Opc == ISD::SIGN_EXTEND_INREG) {
3034 ExtType = ISD::SEXTLOAD;
3035 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3036 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
3040 unsigned EVTBits = MVT::getSizeInBits(EVT);
3042 bool CombineSRL = false;
3043 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
3044 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3045 ShAmt = N01->getValue();
3046 // Is the shift amount a multiple of size of VT?
3047 if ((ShAmt & (EVTBits-1)) == 0) {
3048 N0 = N0.getOperand(0);
3049 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
3056 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3057 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
3058 // zero extended form: by shrinking the load, we lose track of the fact
3059 // that it is already zero extended.
3060 // FIXME: This should be reevaluated.
3062 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
3063 "Cannot truncate to larger type!");
3064 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3065 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
3066 // For big endian targets, we need to adjust the offset to the pointer to
3067 // load the correct bytes.
3068 if (!TLI.isLittleEndian()) {
3069 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType());
3070 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT);
3071 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3073 uint64_t PtrOff = ShAmt / 8;
3074 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3075 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
3076 DAG.getConstant(PtrOff, PtrType));
3077 AddToWorkList(NewPtr.Val);
3078 SDOperand Load = (ExtType == ISD::NON_EXTLOAD)
3079 ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
3080 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3081 LN0->isVolatile(), NewAlign)
3082 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
3083 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
3084 LN0->isVolatile(), NewAlign);
3087 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
3088 CombineTo(N->getOperand(0).Val, Load);
3090 CombineTo(N0.Val, Load, Load.getValue(1));
3092 if (Opc == ISD::SIGN_EXTEND_INREG)
3093 return DAG.getNode(Opc, VT, Load, N->getOperand(1));
3095 return DAG.getNode(Opc, VT, Load);
3097 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3104 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3105 SDOperand N0 = N->getOperand(0);
3106 SDOperand N1 = N->getOperand(1);
3107 MVT::ValueType VT = N->getValueType(0);
3108 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
3109 unsigned EVTBits = MVT::getSizeInBits(EVT);
3111 // fold (sext_in_reg c1) -> c1
3112 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3113 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
3115 // If the input is already sign extended, just drop the extension.
3116 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
3119 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3120 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3121 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
3122 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
3125 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3126 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
3127 return DAG.getZeroExtendInReg(N0, EVT);
3129 // fold operands of sext_in_reg based on knowledge that the top bits are not
3131 if (SimplifyDemandedBits(SDOperand(N, 0)))
3132 return SDOperand(N, 0);
3134 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3135 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3136 SDOperand NarrowLoad = ReduceLoadWidth(N);
3140 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
3141 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
3142 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3143 if (N0.getOpcode() == ISD::SRL) {
3144 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3145 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
3146 // We can turn this into an SRA iff the input to the SRL is already sign
3148 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3149 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
3150 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
3154 // fold (sext_inreg (extload x)) -> (sextload x)
3155 if (ISD::isEXTLoad(N0.Val) &&
3156 ISD::isUNINDEXEDLoad(N0.Val) &&
3157 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
3158 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
3159 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3160 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
3161 LN0->getBasePtr(), LN0->getSrcValue(),
3162 LN0->getSrcValueOffset(), EVT,
3164 LN0->getAlignment());
3165 CombineTo(N, ExtLoad);
3166 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
3167 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3169 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3170 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
3172 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
3173 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
3174 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3175 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
3176 LN0->getBasePtr(), LN0->getSrcValue(),
3177 LN0->getSrcValueOffset(), EVT,
3179 LN0->getAlignment());
3180 CombineTo(N, ExtLoad);
3181 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
3182 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3187 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
3188 SDOperand N0 = N->getOperand(0);
3189 MVT::ValueType VT = N->getValueType(0);
3192 if (N0.getValueType() == N->getValueType(0))
3194 // fold (truncate c1) -> c1
3195 if (isa<ConstantSDNode>(N0))
3196 return DAG.getNode(ISD::TRUNCATE, VT, N0);
3197 // fold (truncate (truncate x)) -> (truncate x)
3198 if (N0.getOpcode() == ISD::TRUNCATE)
3199 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3200 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3201 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
3202 N0.getOpcode() == ISD::ANY_EXTEND) {
3203 if (N0.getOperand(0).getValueType() < VT)
3204 // if the source is smaller than the dest, we still need an extend
3205 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
3206 else if (N0.getOperand(0).getValueType() > VT)
3207 // if the source is larger than the dest, than we just need the truncate
3208 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3210 // if the source and dest are the same type, we can drop both the extend
3212 return N0.getOperand(0);
3215 // See if we can simplify the input to this truncate through knowledge that
3216 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3218 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT));
3220 return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
3222 // fold (truncate (load x)) -> (smaller load x)
3223 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3224 return ReduceLoadWidth(N);
3227 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3228 SDOperand N0 = N->getOperand(0);
3229 MVT::ValueType VT = N->getValueType(0);
3231 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3232 // Only do this before legalize, since afterward the target may be depending
3233 // on the bitconvert.
3234 // First check to see if this is all constant.
3235 if (!AfterLegalize &&
3236 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
3237 MVT::isVector(VT)) {
3238 bool isSimple = true;
3239 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3240 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3241 N0.getOperand(i).getOpcode() != ISD::Constant &&
3242 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3247 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0));
3248 assert(!MVT::isVector(DestEltVT) &&
3249 "Element type of vector ValueType must not be vector!");
3251 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
3255 // If the input is a constant, let getNode() fold it.
3256 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3257 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3258 if (Res.Val != N) return Res;
3261 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
3262 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3264 // fold (conv (load x)) -> (load (conv*)x)
3265 // If the resultant load doesn't need a higher alignment than the original!
3266 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() &&
3267 TLI.isOperationLegal(ISD::LOAD, VT)) {
3268 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3269 unsigned Align = TLI.getTargetMachine().getTargetData()->
3270 getABITypeAlignment(MVT::getTypeForValueType(VT));
3271 unsigned OrigAlign = LN0->getAlignment();
3272 if (Align <= OrigAlign) {
3273 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
3274 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3275 LN0->isVolatile(), Align);
3277 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
3286 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3287 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3288 /// destination element value type.
3289 SDOperand DAGCombiner::
3290 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
3291 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
3293 // If this is already the right type, we're done.
3294 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
3296 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
3297 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
3299 // If this is a conversion of N elements of one type to N elements of another
3300 // type, convert each element. This handles FP<->INT cases.
3301 if (SrcBitSize == DstBitSize) {
3302 SmallVector<SDOperand, 8> Ops;
3303 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3304 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
3305 AddToWorkList(Ops.back().Val);
3308 MVT::getVectorType(DstEltVT,
3309 MVT::getVectorNumElements(BV->getValueType(0)));
3310 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3313 // Otherwise, we're growing or shrinking the elements. To avoid having to
3314 // handle annoying details of growing/shrinking FP values, we convert them to
3316 if (MVT::isFloatingPoint(SrcEltVT)) {
3317 // Convert the input float vector to a int vector where the elements are the
3319 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3320 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
3321 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
3325 // Now we know the input is an integer vector. If the output is a FP type,
3326 // convert to integer first, then to FP of the right size.
3327 if (MVT::isFloatingPoint(DstEltVT)) {
3328 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3329 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
3330 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val;
3332 // Next, convert to FP elements of the same size.
3333 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3336 // Okay, we know the src/dst types are both integers of differing types.
3337 // Handling growing first.
3338 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
3339 if (SrcBitSize < DstBitSize) {
3340 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3342 SmallVector<SDOperand, 8> Ops;
3343 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3344 i += NumInputsPerOutput) {
3345 bool isLE = TLI.isLittleEndian();
3346 uint64_t NewBits = 0;
3347 bool EltIsUndef = true;
3348 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3349 // Shift the previously computed bits over.
3350 NewBits <<= SrcBitSize;
3351 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3352 if (Op.getOpcode() == ISD::UNDEF) continue;
3355 NewBits |= cast<ConstantSDNode>(Op)->getValue();
3359 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3361 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3364 MVT::ValueType VT = MVT::getVectorType(DstEltVT,
3366 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3369 // Finally, this must be the case where we are shrinking elements: each input
3370 // turns into multiple outputs.
3371 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3372 SmallVector<SDOperand, 8> Ops;
3373 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3374 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3375 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3376 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3379 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
3381 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3382 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
3383 OpVal >>= DstBitSize;
3384 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3387 // For big endian targets, swap the order of the pieces of each element.
3388 if (!TLI.isLittleEndian())
3389 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3391 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size());
3392 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3397 SDOperand DAGCombiner::visitFADD(SDNode *N) {
3398 SDOperand N0 = N->getOperand(0);
3399 SDOperand N1 = N->getOperand(1);
3400 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3401 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3402 MVT::ValueType VT = N->getValueType(0);
3405 if (MVT::isVector(VT)) {
3406 SDOperand FoldedVOp = SimplifyVBinOp(N);
3407 if (FoldedVOp.Val) return FoldedVOp;
3410 // fold (fadd c1, c2) -> c1+c2
3411 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3412 return DAG.getNode(ISD::FADD, VT, N0, N1);
3413 // canonicalize constant to RHS
3414 if (N0CFP && !N1CFP)
3415 return DAG.getNode(ISD::FADD, VT, N1, N0);
3416 // fold (A + (-B)) -> A-B
3417 if (isNegatibleForFree(N1) == 2)
3418 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG));
3419 // fold ((-A) + B) -> B-A
3420 if (isNegatibleForFree(N0) == 2)
3421 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG));
3423 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3424 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3425 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3426 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
3427 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
3432 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
3433 SDOperand N0 = N->getOperand(0);
3434 SDOperand N1 = N->getOperand(1);
3435 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3436 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3437 MVT::ValueType VT = N->getValueType(0);
3440 if (MVT::isVector(VT)) {
3441 SDOperand FoldedVOp = SimplifyVBinOp(N);
3442 if (FoldedVOp.Val) return FoldedVOp;
3445 // fold (fsub c1, c2) -> c1-c2
3446 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3447 return DAG.getNode(ISD::FSUB, VT, N0, N1);
3449 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
3450 if (isNegatibleForFree(N1))
3451 return GetNegatedExpression(N1, DAG);
3452 return DAG.getNode(ISD::FNEG, VT, N1);
3454 // fold (A-(-B)) -> A+B
3455 if (isNegatibleForFree(N1))
3456 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG));
3461 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
3462 SDOperand N0 = N->getOperand(0);
3463 SDOperand N1 = N->getOperand(1);
3464 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3465 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3466 MVT::ValueType VT = N->getValueType(0);
3469 if (MVT::isVector(VT)) {
3470 SDOperand FoldedVOp = SimplifyVBinOp(N);
3471 if (FoldedVOp.Val) return FoldedVOp;
3474 // fold (fmul c1, c2) -> c1*c2
3475 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3476 return DAG.getNode(ISD::FMUL, VT, N0, N1);
3477 // canonicalize constant to RHS
3478 if (N0CFP && !N1CFP)
3479 return DAG.getNode(ISD::FMUL, VT, N1, N0);
3480 // fold (fmul X, 2.0) -> (fadd X, X)
3481 if (N1CFP && N1CFP->isExactlyValue(+2.0))
3482 return DAG.getNode(ISD::FADD, VT, N0, N0);
3483 // fold (fmul X, -1.0) -> (fneg X)
3484 if (N1CFP && N1CFP->isExactlyValue(-1.0))
3485 return DAG.getNode(ISD::FNEG, VT, N0);
3488 if (char LHSNeg = isNegatibleForFree(N0)) {
3489 if (char RHSNeg = isNegatibleForFree(N1)) {
3490 // Both can be negated for free, check to see if at least one is cheaper
3492 if (LHSNeg == 2 || RHSNeg == 2)
3493 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG),
3494 GetNegatedExpression(N1, DAG));
3498 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
3499 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
3500 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3501 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
3502 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
3507 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
3508 SDOperand N0 = N->getOperand(0);
3509 SDOperand N1 = N->getOperand(1);
3510 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3511 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3512 MVT::ValueType VT = N->getValueType(0);
3515 if (MVT::isVector(VT)) {
3516 SDOperand FoldedVOp = SimplifyVBinOp(N);
3517 if (FoldedVOp.Val) return FoldedVOp;
3520 // fold (fdiv c1, c2) -> c1/c2
3521 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3522 return DAG.getNode(ISD::FDIV, VT, N0, N1);
3526 if (char LHSNeg = isNegatibleForFree(N0)) {
3527 if (char RHSNeg = isNegatibleForFree(N1)) {
3528 // Both can be negated for free, check to see if at least one is cheaper
3530 if (LHSNeg == 2 || RHSNeg == 2)
3531 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG),
3532 GetNegatedExpression(N1, DAG));
3539 SDOperand DAGCombiner::visitFREM(SDNode *N) {
3540 SDOperand N0 = N->getOperand(0);
3541 SDOperand N1 = N->getOperand(1);
3542 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3543 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3544 MVT::ValueType VT = N->getValueType(0);
3546 // fold (frem c1, c2) -> fmod(c1,c2)
3547 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3548 return DAG.getNode(ISD::FREM, VT, N0, N1);
3553 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
3554 SDOperand N0 = N->getOperand(0);
3555 SDOperand N1 = N->getOperand(1);
3556 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3557 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3558 MVT::ValueType VT = N->getValueType(0);
3560 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
3561 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
3564 const APFloat& V = N1CFP->getValueAPF();
3565 // copysign(x, c1) -> fabs(x) iff ispos(c1)
3566 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
3567 if (!V.isNegative())
3568 return DAG.getNode(ISD::FABS, VT, N0);
3570 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
3573 // copysign(fabs(x), y) -> copysign(x, y)
3574 // copysign(fneg(x), y) -> copysign(x, y)
3575 // copysign(copysign(x,z), y) -> copysign(x, y)
3576 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
3577 N0.getOpcode() == ISD::FCOPYSIGN)
3578 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
3580 // copysign(x, abs(y)) -> abs(x)
3581 if (N1.getOpcode() == ISD::FABS)
3582 return DAG.getNode(ISD::FABS, VT, N0);
3584 // copysign(x, copysign(y,z)) -> copysign(x, z)
3585 if (N1.getOpcode() == ISD::FCOPYSIGN)
3586 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
3588 // copysign(x, fp_extend(y)) -> copysign(x, y)
3589 // copysign(x, fp_round(y)) -> copysign(x, y)
3590 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
3591 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
3598 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
3599 SDOperand N0 = N->getOperand(0);
3600 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3601 MVT::ValueType VT = N->getValueType(0);
3603 // fold (sint_to_fp c1) -> c1fp
3604 if (N0C && N0.getValueType() != MVT::ppcf128)
3605 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
3609 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
3610 SDOperand N0 = N->getOperand(0);
3611 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3612 MVT::ValueType VT = N->getValueType(0);
3614 // fold (uint_to_fp c1) -> c1fp
3615 if (N0C && N0.getValueType() != MVT::ppcf128)
3616 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
3620 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
3621 SDOperand N0 = N->getOperand(0);
3622 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3623 MVT::ValueType VT = N->getValueType(0);
3625 // fold (fp_to_sint c1fp) -> c1
3627 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
3631 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
3632 SDOperand N0 = N->getOperand(0);
3633 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3634 MVT::ValueType VT = N->getValueType(0);
3636 // fold (fp_to_uint c1fp) -> c1
3637 if (N0CFP && VT != MVT::ppcf128)
3638 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
3642 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
3643 SDOperand N0 = N->getOperand(0);
3644 SDOperand N1 = N->getOperand(1);
3645 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3646 MVT::ValueType VT = N->getValueType(0);
3648 // fold (fp_round c1fp) -> c1fp
3649 if (N0CFP && N0.getValueType() != MVT::ppcf128)
3650 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1);
3652 // fold (fp_round (fp_extend x)) -> x
3653 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
3654 return N0.getOperand(0);
3656 // fold (fp_round (fp_round x)) -> (fp_round x)
3657 if (N0.getOpcode() == ISD::FP_ROUND) {
3658 // This is a value preserving truncation if both round's are.
3659 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
3660 N0.Val->getConstantOperandVal(1) == 1;
3661 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0),
3662 DAG.getIntPtrConstant(IsTrunc));
3665 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
3666 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
3667 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1);
3668 AddToWorkList(Tmp.Val);
3669 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
3675 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
3676 SDOperand N0 = N->getOperand(0);
3677 MVT::ValueType VT = N->getValueType(0);
3678 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3679 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3681 // fold (fp_round_inreg c1fp) -> c1fp
3683 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT);
3684 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
3689 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
3690 SDOperand N0 = N->getOperand(0);
3691 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3692 MVT::ValueType VT = N->getValueType(0);
3694 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
3695 if (N->hasOneUse() && (*N->use_begin())->getOpcode() == ISD::FP_ROUND)
3698 // fold (fp_extend c1fp) -> c1fp
3699 if (N0CFP && VT != MVT::ppcf128)
3700 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
3702 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
3704 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){
3705 SDOperand In = N0.getOperand(0);
3706 if (In.getValueType() == VT) return In;
3707 if (VT < In.getValueType())
3708 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1));
3709 return DAG.getNode(ISD::FP_EXTEND, VT, In);
3712 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
3713 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3714 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
3715 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3716 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
3717 LN0->getBasePtr(), LN0->getSrcValue(),
3718 LN0->getSrcValueOffset(),
3721 LN0->getAlignment());
3722 CombineTo(N, ExtLoad);
3723 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad,
3724 DAG.getIntPtrConstant(1)),
3725 ExtLoad.getValue(1));
3726 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3733 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
3734 SDOperand N0 = N->getOperand(0);
3736 if (isNegatibleForFree(N0))
3737 return GetNegatedExpression(N0, DAG);
3742 SDOperand DAGCombiner::visitFABS(SDNode *N) {
3743 SDOperand N0 = N->getOperand(0);
3744 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3745 MVT::ValueType VT = N->getValueType(0);
3747 // fold (fabs c1) -> fabs(c1)
3748 if (N0CFP && VT != MVT::ppcf128)
3749 return DAG.getNode(ISD::FABS, VT, N0);
3750 // fold (fabs (fabs x)) -> (fabs x)
3751 if (N0.getOpcode() == ISD::FABS)
3752 return N->getOperand(0);
3753 // fold (fabs (fneg x)) -> (fabs x)
3754 // fold (fabs (fcopysign x, y)) -> (fabs x)
3755 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
3756 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
3761 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
3762 SDOperand Chain = N->getOperand(0);
3763 SDOperand N1 = N->getOperand(1);
3764 SDOperand N2 = N->getOperand(2);
3765 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3767 // never taken branch, fold to chain
3768 if (N1C && N1C->isNullValue())
3770 // unconditional branch
3771 if (N1C && N1C->getValue() == 1)
3772 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
3773 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
3775 if (N1.getOpcode() == ISD::SETCC &&
3776 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
3777 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
3778 N1.getOperand(0), N1.getOperand(1), N2);
3783 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
3785 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
3786 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
3787 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
3789 // Use SimplifySetCC to simplify SETCC's.
3790 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
3791 if (Simp.Val) AddToWorkList(Simp.Val);
3793 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
3795 // fold br_cc true, dest -> br dest (unconditional branch)
3796 if (SCCC && SCCC->getValue())
3797 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
3799 // fold br_cc false, dest -> unconditional fall through
3800 if (SCCC && SCCC->isNullValue())
3801 return N->getOperand(0);
3803 // fold to a simpler setcc
3804 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
3805 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
3806 Simp.getOperand(2), Simp.getOperand(0),
3807 Simp.getOperand(1), N->getOperand(4));
3812 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
3813 /// pre-indexed load / store when the base pointer is a add or subtract
3814 /// and it has other uses besides the load / store. After the
3815 /// transformation, the new indexed load / store has effectively folded
3816 /// the add / subtract in and all of its other uses are redirected to the
3817 /// new load / store.
3818 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
3825 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3826 if (LD->isIndexed())
3828 VT = LD->getLoadedVT();
3829 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
3830 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
3832 Ptr = LD->getBasePtr();
3833 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3834 if (ST->isIndexed())
3836 VT = ST->getStoredVT();
3837 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
3838 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
3840 Ptr = ST->getBasePtr();
3845 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
3846 // out. There is no reason to make this a preinc/predec.
3847 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
3848 Ptr.Val->hasOneUse())
3851 // Ask the target to do addressing mode selection.
3854 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3855 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
3857 // Don't create a indexed load / store with zero offset.
3858 if (isa<ConstantSDNode>(Offset) &&
3859 cast<ConstantSDNode>(Offset)->getValue() == 0)
3862 // Try turning it into a pre-indexed load / store except when:
3863 // 1) The new base ptr is a frame index.
3864 // 2) If N is a store and the new base ptr is either the same as or is a
3865 // predecessor of the value being stored.
3866 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
3867 // that would create a cycle.
3868 // 4) All uses are load / store ops that use it as old base ptr.
3870 // Check #1. Preinc'ing a frame index would require copying the stack pointer
3871 // (plus the implicit offset) to a register to preinc anyway.
3872 if (isa<FrameIndexSDNode>(BasePtr))
3877 SDOperand Val = cast<StoreSDNode>(N)->getValue();
3878 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val))
3882 // Now check for #3 and #4.
3883 bool RealUse = false;
3884 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3885 E = Ptr.Val->use_end(); I != E; ++I) {
3889 if (Use->isPredecessor(N))
3892 if (!((Use->getOpcode() == ISD::LOAD &&
3893 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
3894 (Use->getOpcode() == ISD::STORE) &&
3895 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
3903 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
3905 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3908 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
3909 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3911 std::vector<SDNode*> NowDead;
3913 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3915 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3918 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3922 // Nodes can end up on the worklist more than once. Make sure we do
3923 // not process a node that has been replaced.
3924 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3925 removeFromWorkList(NowDead[i]);
3926 // Finally, since the node is now dead, remove it from the graph.
3929 // Replace the uses of Ptr with uses of the updated base value.
3930 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
3932 removeFromWorkList(Ptr.Val);
3933 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3934 removeFromWorkList(NowDead[i]);
3935 DAG.DeleteNode(Ptr.Val);
3940 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
3941 /// add / sub of the base pointer node into a post-indexed load / store.
3942 /// The transformation folded the add / subtract into the new indexed
3943 /// load / store effectively and all of its uses are redirected to the
3944 /// new load / store.
3945 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
3952 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3953 if (LD->isIndexed())
3955 VT = LD->getLoadedVT();
3956 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
3957 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
3959 Ptr = LD->getBasePtr();
3960 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3961 if (ST->isIndexed())
3963 VT = ST->getStoredVT();
3964 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
3965 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
3967 Ptr = ST->getBasePtr();
3972 if (Ptr.Val->hasOneUse())
3975 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3976 E = Ptr.Val->use_end(); I != E; ++I) {
3979 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
3984 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3985 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
3987 std::swap(BasePtr, Offset);
3990 // Don't create a indexed load / store with zero offset.
3991 if (isa<ConstantSDNode>(Offset) &&
3992 cast<ConstantSDNode>(Offset)->getValue() == 0)
3995 // Try turning it into a post-indexed load / store except when
3996 // 1) All uses are load / store ops that use it as base ptr.
3997 // 2) Op must be independent of N, i.e. Op is neither a predecessor
3998 // nor a successor of N. Otherwise, if Op is folded that would
4002 bool TryNext = false;
4003 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
4004 EE = BasePtr.Val->use_end(); II != EE; ++II) {
4009 // If all the uses are load / store addresses, then don't do the
4011 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
4012 bool RealUse = false;
4013 for (SDNode::use_iterator III = Use->use_begin(),
4014 EEE = Use->use_end(); III != EEE; ++III) {
4015 SDNode *UseUse = *III;
4016 if (!((UseUse->getOpcode() == ISD::LOAD &&
4017 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
4018 (UseUse->getOpcode() == ISD::STORE) &&
4019 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
4033 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
4034 SDOperand Result = isLoad
4035 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
4036 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
4039 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
4040 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
4042 std::vector<SDNode*> NowDead;
4044 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
4046 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
4049 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
4053 // Nodes can end up on the worklist more than once. Make sure we do
4054 // not process a node that has been replaced.
4055 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
4056 removeFromWorkList(NowDead[i]);
4057 // Finally, since the node is now dead, remove it from the graph.
4060 // Replace the uses of Use with uses of the updated base value.
4061 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
4062 Result.getValue(isLoad ? 1 : 0),
4064 removeFromWorkList(Op);
4065 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
4066 removeFromWorkList(NowDead[i]);
4077 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
4078 LoadSDNode *LD = cast<LoadSDNode>(N);
4079 SDOperand Chain = LD->getChain();
4080 SDOperand Ptr = LD->getBasePtr();
4082 // If load is not volatile and there are no uses of the loaded value (and
4083 // the updated indexed value in case of indexed loads), change uses of the
4084 // chain value into uses of the chain input (i.e. delete the dead load).
4085 if (!LD->isVolatile()) {
4086 if (N->getValueType(1) == MVT::Other) {
4088 if (N->hasNUsesOfValue(0, 0)) {
4089 // It's not safe to use the two value CombineTo variant here. e.g.
4090 // v1, chain2 = load chain1, loc
4091 // v2, chain3 = load chain2, loc
4093 // Now we replace use of v1 with undef, use of chain2 with chain1.
4094 // ReplaceAllUsesWith() will iterate through uses of the first load and
4096 // v1, chain2 = load chain1, loc
4097 // v2, chain3 = load chain1, loc
4099 // Now the second load is the same as the first load, SelectionDAG cse
4100 // will ensure the use of second load is replaced with the first load.
4101 // v1, chain2 = load chain1, loc
4103 // Then v1 is replaced with undef and bad things happen.
4104 std::vector<SDNode*> NowDead;
4105 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0));
4106 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4107 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG));
4108 DOUT << " and 1 other value\n";
4109 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &NowDead);
4110 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &NowDead);
4111 removeFromWorkList(N);
4112 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
4113 removeFromWorkList(NowDead[i]);
4115 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
4119 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
4120 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
4121 std::vector<SDNode*> NowDead;
4122 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0));
4123 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4124 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG));
4125 DOUT << " and 2 other values\n";
4126 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &NowDead);
4127 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1),
4128 DAG.getNode(ISD::UNDEF, N->getValueType(1)),
4130 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &NowDead);
4131 removeFromWorkList(N);
4132 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
4133 removeFromWorkList(NowDead[i]);
4135 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
4140 // If this load is directly stored, replace the load value with the stored
4142 // TODO: Handle store large -> read small portion.
4143 // TODO: Handle TRUNCSTORE/LOADEXT
4144 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4145 if (ISD::isNON_TRUNCStore(Chain.Val)) {
4146 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
4147 if (PrevST->getBasePtr() == Ptr &&
4148 PrevST->getValue().getValueType() == N->getValueType(0))
4149 return CombineTo(N, Chain.getOperand(1), Chain);
4154 // Walk up chain skipping non-aliasing memory nodes.
4155 SDOperand BetterChain = FindBetterChain(N, Chain);
4157 // If there is a better chain.
4158 if (Chain != BetterChain) {
4161 // Replace the chain to void dependency.
4162 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4163 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
4164 LD->getSrcValue(), LD->getSrcValueOffset(),
4165 LD->isVolatile(), LD->getAlignment());
4167 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
4168 LD->getValueType(0),
4169 BetterChain, Ptr, LD->getSrcValue(),
4170 LD->getSrcValueOffset(),
4173 LD->getAlignment());
4176 // Create token factor to keep old chain connected.
4177 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
4178 Chain, ReplLoad.getValue(1));
4180 // Replace uses with load result and token factor. Don't add users
4182 return CombineTo(N, ReplLoad.getValue(0), Token, false);
4186 // Try transforming N to an indexed load.
4187 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4188 return SDOperand(N, 0);
4194 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
4195 StoreSDNode *ST = cast<StoreSDNode>(N);
4196 SDOperand Chain = ST->getChain();
4197 SDOperand Value = ST->getValue();
4198 SDOperand Ptr = ST->getBasePtr();
4200 // If this is a store of a bit convert, store the input value if the
4201 // resultant store does not need a higher alignment than the original.
4202 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
4203 ST->isUnindexed()) {
4204 unsigned Align = ST->getAlignment();
4205 MVT::ValueType SVT = Value.getOperand(0).getValueType();
4206 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
4207 getABITypeAlignment(MVT::getTypeForValueType(SVT));
4208 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
4209 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
4210 ST->getSrcValueOffset(), ST->isVolatile(), Align);
4213 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
4214 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
4215 if (Value.getOpcode() != ISD::TargetConstantFP) {
4217 switch (CFP->getValueType(0)) {
4218 default: assert(0 && "Unknown FP type");
4219 case MVT::f80: // We don't do this for these yet.
4224 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
4225 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
4226 convertToAPInt().getZExtValue(), MVT::i32);
4227 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4228 ST->getSrcValueOffset(), ST->isVolatile(),
4229 ST->getAlignment());
4233 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
4234 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
4235 getZExtValue(), MVT::i64);
4236 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4237 ST->getSrcValueOffset(), ST->isVolatile(),
4238 ST->getAlignment());
4239 } else if (TLI.isTypeLegal(MVT::i32)) {
4240 // Many FP stores are not made apparent until after legalize, e.g. for
4241 // argument passing. Since this is so common, custom legalize the
4242 // 64-bit integer store into two 32-bit stores.
4243 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue();
4244 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
4245 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
4246 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
4248 int SVOffset = ST->getSrcValueOffset();
4249 unsigned Alignment = ST->getAlignment();
4250 bool isVolatile = ST->isVolatile();
4252 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
4253 ST->getSrcValueOffset(),
4254 isVolatile, ST->getAlignment());
4255 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4256 DAG.getConstant(4, Ptr.getValueType()));
4258 Alignment = MinAlign(Alignment, 4U);
4259 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
4260 SVOffset, isVolatile, Alignment);
4261 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
4269 // Walk up chain skipping non-aliasing memory nodes.
4270 SDOperand BetterChain = FindBetterChain(N, Chain);
4272 // If there is a better chain.
4273 if (Chain != BetterChain) {
4274 // Replace the chain to avoid dependency.
4275 SDOperand ReplStore;
4276 if (ST->isTruncatingStore()) {
4277 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
4278 ST->getSrcValue(),ST->getSrcValueOffset(),
4280 ST->isVolatile(), ST->getAlignment());
4282 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
4283 ST->getSrcValue(), ST->getSrcValueOffset(),
4284 ST->isVolatile(), ST->getAlignment());
4287 // Create token to keep both nodes around.
4289 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
4291 // Don't add users to work list.
4292 return CombineTo(N, Token, false);
4296 // Try transforming N to an indexed store.
4297 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4298 return SDOperand(N, 0);
4300 // FIXME: is there such a thing as a truncating indexed store?
4301 if (ST->isTruncatingStore() && ST->isUnindexed() &&
4302 MVT::isInteger(Value.getValueType())) {
4303 // See if we can simplify the input to this truncstore with knowledge that
4304 // only the low bits are being used. For example:
4305 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
4307 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT()));
4308 AddToWorkList(Value.Val);
4310 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
4311 ST->getSrcValueOffset(), ST->getStoredVT(),
4312 ST->isVolatile(), ST->getAlignment());
4314 // Otherwise, see if we can simplify the operation with
4315 // SimplifyDemandedBits, which only works if the value has a single use.
4316 if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT())))
4317 return SDOperand(N, 0);
4320 // If this is a load followed by a store to the same location, then the store
4322 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
4323 if (Ld->getBasePtr() == Ptr && ST->getStoredVT() == Ld->getLoadedVT() &&
4324 ST->isUnindexed() && !ST->isVolatile() &&
4325 // There can't be any side effects between the load and store, such as
4327 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) {
4328 // The store is dead, remove it.
4333 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
4334 // truncating store. We can do this even if this is already a truncstore.
4335 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
4336 && TLI.isTypeLegal(Value.getOperand(0).getValueType()) &&
4337 Value.Val->hasOneUse() && ST->isUnindexed() &&
4338 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
4339 ST->getStoredVT())) {
4340 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
4341 ST->getSrcValueOffset(), ST->getStoredVT(),
4342 ST->isVolatile(), ST->getAlignment());
4348 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
4349 SDOperand InVec = N->getOperand(0);
4350 SDOperand InVal = N->getOperand(1);
4351 SDOperand EltNo = N->getOperand(2);
4353 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
4354 // vector with the inserted element.
4355 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
4356 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4357 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
4358 if (Elt < Ops.size())
4360 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
4361 &Ops[0], Ops.size());
4367 SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
4368 SDOperand InVec = N->getOperand(0);
4369 SDOperand EltNo = N->getOperand(1);
4371 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr)
4372 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
4373 if (isa<ConstantSDNode>(EltNo)) {
4374 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4375 bool NewLoad = false;
4377 MVT::ValueType VT = InVec.getValueType();
4378 MVT::ValueType EVT = MVT::getVectorElementType(VT);
4379 MVT::ValueType LVT = EVT;
4380 unsigned NumElts = MVT::getVectorNumElements(VT);
4381 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
4382 MVT::ValueType BCVT = InVec.getOperand(0).getValueType();
4383 if (!MVT::isVector(BCVT) ||
4384 NumElts != MVT::getVectorNumElements(BCVT))
4386 InVec = InVec.getOperand(0);
4387 EVT = MVT::getVectorElementType(BCVT);
4390 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4391 InVec.getOperand(0).getValueType() == EVT &&
4392 ISD::isNormalLoad(InVec.getOperand(0).Val) &&
4393 InVec.getOperand(0).hasOneUse()) {
4394 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0));
4395 unsigned Align = LN0->getAlignment();
4397 // Check the resultant load doesn't need a higher alignment than the
4399 unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
4400 getABITypeAlignment(MVT::getTypeForValueType(LVT));
4401 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align)
4406 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(),
4407 LN0->getSrcValue(), LN0->getSrcValueOffset(),
4408 LN0->isVolatile(), Align);
4416 SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
4417 unsigned NumInScalars = N->getNumOperands();
4418 MVT::ValueType VT = N->getValueType(0);
4419 unsigned NumElts = MVT::getVectorNumElements(VT);
4420 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4422 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
4423 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
4424 // at most two distinct vectors, turn this into a shuffle node.
4425 SDOperand VecIn1, VecIn2;
4426 for (unsigned i = 0; i != NumInScalars; ++i) {
4427 // Ignore undef inputs.
4428 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4430 // If this input is something other than a EXTRACT_VECTOR_ELT with a
4431 // constant index, bail out.
4432 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4433 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
4434 VecIn1 = VecIn2 = SDOperand(0, 0);
4438 // If the input vector type disagrees with the result of the build_vector,
4439 // we can't make a shuffle.
4440 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
4441 if (ExtractedFromVec.getValueType() != VT) {
4442 VecIn1 = VecIn2 = SDOperand(0, 0);
4446 // Otherwise, remember this. We allow up to two distinct input vectors.
4447 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
4450 if (VecIn1.Val == 0) {
4451 VecIn1 = ExtractedFromVec;
4452 } else if (VecIn2.Val == 0) {
4453 VecIn2 = ExtractedFromVec;
4456 VecIn1 = VecIn2 = SDOperand(0, 0);
4461 // If everything is good, we can make a shuffle operation.
4463 SmallVector<SDOperand, 8> BuildVecIndices;
4464 for (unsigned i = 0; i != NumInScalars; ++i) {
4465 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
4466 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
4470 SDOperand Extract = N->getOperand(i);
4472 // If extracting from the first vector, just use the index directly.
4473 if (Extract.getOperand(0) == VecIn1) {
4474 BuildVecIndices.push_back(Extract.getOperand(1));
4478 // Otherwise, use InIdx + VecSize
4479 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
4480 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars));
4483 // Add count and size info.
4484 MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts);
4486 // Return the new VECTOR_SHUFFLE node.
4492 // Use an undef build_vector as input for the second operand.
4493 std::vector<SDOperand> UnOps(NumInScalars,
4494 DAG.getNode(ISD::UNDEF,
4496 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
4497 &UnOps[0], UnOps.size());
4498 AddToWorkList(Ops[1].Val);
4500 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
4501 &BuildVecIndices[0], BuildVecIndices.size());
4502 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3);
4508 SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
4509 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
4510 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
4511 // inputs come from at most two distinct vectors, turn this into a shuffle
4514 // If we only have one input vector, we don't need to do any concatenation.
4515 if (N->getNumOperands() == 1) {
4516 return N->getOperand(0);
4522 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
4523 SDOperand ShufMask = N->getOperand(2);
4524 unsigned NumElts = ShufMask.getNumOperands();
4526 // If the shuffle mask is an identity operation on the LHS, return the LHS.
4527 bool isIdentity = true;
4528 for (unsigned i = 0; i != NumElts; ++i) {
4529 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4530 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
4535 if (isIdentity) return N->getOperand(0);
4537 // If the shuffle mask is an identity operation on the RHS, return the RHS.
4539 for (unsigned i = 0; i != NumElts; ++i) {
4540 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4541 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
4546 if (isIdentity) return N->getOperand(1);
4548 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
4550 bool isUnary = true;
4551 bool isSplat = true;
4553 unsigned BaseIdx = 0;
4554 for (unsigned i = 0; i != NumElts; ++i)
4555 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
4556 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
4557 int V = (Idx < NumElts) ? 0 : 1;
4571 SDOperand N0 = N->getOperand(0);
4572 SDOperand N1 = N->getOperand(1);
4573 // Normalize unary shuffle so the RHS is undef.
4574 if (isUnary && VecNum == 1)
4577 // If it is a splat, check if the argument vector is a build_vector with
4578 // all scalar elements the same.
4582 // If this is a bit convert that changes the element type of the vector but
4583 // not the number of vector elements, look through it. Be careful not to
4584 // look though conversions that change things like v4f32 to v2f64.
4585 if (V->getOpcode() == ISD::BIT_CONVERT) {
4586 SDOperand ConvInput = V->getOperand(0);
4587 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts)
4591 if (V->getOpcode() == ISD::BUILD_VECTOR) {
4592 unsigned NumElems = V->getNumOperands();
4593 if (NumElems > BaseIdx) {
4595 bool AllSame = true;
4596 for (unsigned i = 0; i != NumElems; ++i) {
4597 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
4598 Base = V->getOperand(i);
4602 // Splat of <u, u, u, u>, return <u, u, u, u>
4605 for (unsigned i = 0; i != NumElems; ++i) {
4606 if (V->getOperand(i) != Base) {
4611 // Splat of <x, x, x, x>, return <x, x, x, x>
4618 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
4620 if (isUnary || N0 == N1) {
4621 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
4623 SmallVector<SDOperand, 8> MappedOps;
4624 for (unsigned i = 0; i != NumElts; ++i) {
4625 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
4626 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
4627 MappedOps.push_back(ShufMask.getOperand(i));
4630 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
4631 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
4634 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
4635 &MappedOps[0], MappedOps.size());
4636 AddToWorkList(ShufMask.Val);
4637 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
4639 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
4646 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
4647 /// an AND to a vector_shuffle with the destination vector and a zero vector.
4648 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
4649 /// vector_shuffle V, Zero, <0, 4, 2, 4>
4650 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
4651 SDOperand LHS = N->getOperand(0);
4652 SDOperand RHS = N->getOperand(1);
4653 if (N->getOpcode() == ISD::AND) {
4654 if (RHS.getOpcode() == ISD::BIT_CONVERT)
4655 RHS = RHS.getOperand(0);
4656 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
4657 std::vector<SDOperand> IdxOps;
4658 unsigned NumOps = RHS.getNumOperands();
4659 unsigned NumElts = NumOps;
4660 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType());
4661 for (unsigned i = 0; i != NumElts; ++i) {
4662 SDOperand Elt = RHS.getOperand(i);
4663 if (!isa<ConstantSDNode>(Elt))
4665 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
4666 IdxOps.push_back(DAG.getConstant(i, EVT));
4667 else if (cast<ConstantSDNode>(Elt)->isNullValue())
4668 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
4673 // Let's see if the target supports this vector_shuffle.
4674 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
4677 // Return the new VECTOR_SHUFFLE node.
4678 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts);
4679 std::vector<SDOperand> Ops;
4680 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
4682 AddToWorkList(LHS.Val);
4683 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
4684 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4685 &ZeroOps[0], ZeroOps.size()));
4686 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4687 &IdxOps[0], IdxOps.size()));
4688 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
4689 &Ops[0], Ops.size());
4690 if (VT != LHS.getValueType()) {
4691 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result);
4699 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
4700 SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
4701 // After legalize, the target may be depending on adds and other
4702 // binary ops to provide legal ways to construct constants or other
4703 // things. Simplifying them may result in a loss of legality.
4704 if (AfterLegalize) return SDOperand();
4706 MVT::ValueType VT = N->getValueType(0);
4707 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!");
4709 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4710 SDOperand LHS = N->getOperand(0);
4711 SDOperand RHS = N->getOperand(1);
4712 SDOperand Shuffle = XformToShuffleWithZero(N);
4713 if (Shuffle.Val) return Shuffle;
4715 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
4717 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
4718 RHS.getOpcode() == ISD::BUILD_VECTOR) {
4719 SmallVector<SDOperand, 8> Ops;
4720 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
4721 SDOperand LHSOp = LHS.getOperand(i);
4722 SDOperand RHSOp = RHS.getOperand(i);
4723 // If these two elements can't be folded, bail out.
4724 if ((LHSOp.getOpcode() != ISD::UNDEF &&
4725 LHSOp.getOpcode() != ISD::Constant &&
4726 LHSOp.getOpcode() != ISD::ConstantFP) ||
4727 (RHSOp.getOpcode() != ISD::UNDEF &&
4728 RHSOp.getOpcode() != ISD::Constant &&
4729 RHSOp.getOpcode() != ISD::ConstantFP))
4731 // Can't fold divide by zero.
4732 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
4733 N->getOpcode() == ISD::FDIV) {
4734 if ((RHSOp.getOpcode() == ISD::Constant &&
4735 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
4736 (RHSOp.getOpcode() == ISD::ConstantFP &&
4737 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero()))
4740 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
4741 AddToWorkList(Ops.back().Val);
4742 assert((Ops.back().getOpcode() == ISD::UNDEF ||
4743 Ops.back().getOpcode() == ISD::Constant ||
4744 Ops.back().getOpcode() == ISD::ConstantFP) &&
4745 "Scalar binop didn't fold!");
4748 if (Ops.size() == LHS.getNumOperands()) {
4749 MVT::ValueType VT = LHS.getValueType();
4750 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
4757 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
4758 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
4760 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
4761 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4762 // If we got a simplified select_cc node back from SimplifySelectCC, then
4763 // break it down into a new SETCC node, and a new SELECT node, and then return
4764 // the SELECT node, since we were called with a SELECT node.
4766 // Check to see if we got a select_cc back (to turn into setcc/select).
4767 // Otherwise, just return whatever node we got back, like fabs.
4768 if (SCC.getOpcode() == ISD::SELECT_CC) {
4769 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
4770 SCC.getOperand(0), SCC.getOperand(1),
4772 AddToWorkList(SETCC.Val);
4773 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
4774 SCC.getOperand(3), SETCC);
4781 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
4782 /// are the two values being selected between, see if we can simplify the
4783 /// select. Callers of this should assume that TheSelect is deleted if this
4784 /// returns true. As such, they should return the appropriate thing (e.g. the
4785 /// node) back to the top-level of the DAG combiner loop to avoid it being
4788 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
4791 // If this is a select from two identical things, try to pull the operation
4792 // through the select.
4793 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
4794 // If this is a load and the token chain is identical, replace the select
4795 // of two loads with a load through a select of the address to load from.
4796 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
4797 // constants have been dropped into the constant pool.
4798 if (LHS.getOpcode() == ISD::LOAD &&
4799 // Token chains must be identical.
4800 LHS.getOperand(0) == RHS.getOperand(0)) {
4801 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
4802 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
4804 // If this is an EXTLOAD, the VT's must match.
4805 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
4806 // FIXME: this conflates two src values, discarding one. This is not
4807 // the right thing to do, but nothing uses srcvalues now. When they do,
4808 // turn SrcValue into a list of locations.
4810 if (TheSelect->getOpcode() == ISD::SELECT) {
4811 // Check that the condition doesn't reach either load. If so, folding
4812 // this will induce a cycle into the DAG.
4813 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4814 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
4815 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
4816 TheSelect->getOperand(0), LLD->getBasePtr(),
4820 // Check that the condition doesn't reach either load. If so, folding
4821 // this will induce a cycle into the DAG.
4822 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4823 !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4824 !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
4825 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
4826 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
4827 TheSelect->getOperand(0),
4828 TheSelect->getOperand(1),
4829 LLD->getBasePtr(), RLD->getBasePtr(),
4830 TheSelect->getOperand(4));
4836 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
4837 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
4838 Addr,LLD->getSrcValue(),
4839 LLD->getSrcValueOffset(),
4841 LLD->getAlignment());
4843 Load = DAG.getExtLoad(LLD->getExtensionType(),
4844 TheSelect->getValueType(0),
4845 LLD->getChain(), Addr, LLD->getSrcValue(),
4846 LLD->getSrcValueOffset(),
4849 LLD->getAlignment());
4851 // Users of the select now use the result of the load.
4852 CombineTo(TheSelect, Load);
4854 // Users of the old loads now use the new load's chain. We know the
4855 // old-load value is dead now.
4856 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
4857 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
4867 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
4868 SDOperand N2, SDOperand N3,
4869 ISD::CondCode CC, bool NotExtCompare) {
4871 MVT::ValueType VT = N2.getValueType();
4872 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
4873 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
4874 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
4876 // Determine if the condition we're dealing with is constant
4877 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
4878 if (SCC.Val) AddToWorkList(SCC.Val);
4879 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
4881 // fold select_cc true, x, y -> x
4882 if (SCCC && SCCC->getValue())
4884 // fold select_cc false, x, y -> y
4885 if (SCCC && SCCC->getValue() == 0)
4888 // Check to see if we can simplify the select into an fabs node
4889 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
4890 // Allow either -0.0 or 0.0
4891 if (CFP->getValueAPF().isZero()) {
4892 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
4893 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
4894 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
4895 N2 == N3.getOperand(0))
4896 return DAG.getNode(ISD::FABS, VT, N0);
4898 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
4899 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
4900 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
4901 N2.getOperand(0) == N3)
4902 return DAG.getNode(ISD::FABS, VT, N3);
4906 // Check to see if we can perform the "gzip trick", transforming
4907 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
4908 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
4909 MVT::isInteger(N0.getValueType()) &&
4910 MVT::isInteger(N2.getValueType()) &&
4911 (N1C->isNullValue() || // (a < 0) ? b : 0
4912 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
4913 MVT::ValueType XType = N0.getValueType();
4914 MVT::ValueType AType = N2.getValueType();
4915 if (XType >= AType) {
4916 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
4917 // single-bit constant.
4918 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
4919 unsigned ShCtV = Log2_64(N2C->getValue());
4920 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
4921 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
4922 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
4923 AddToWorkList(Shift.Val);
4924 if (XType > AType) {
4925 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4926 AddToWorkList(Shift.Val);
4928 return DAG.getNode(ISD::AND, AType, Shift, N2);
4930 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4931 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4932 TLI.getShiftAmountTy()));
4933 AddToWorkList(Shift.Val);
4934 if (XType > AType) {
4935 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4936 AddToWorkList(Shift.Val);
4938 return DAG.getNode(ISD::AND, AType, Shift, N2);
4942 // fold select C, 16, 0 -> shl C, 4
4943 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
4944 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
4946 // If the caller doesn't want us to simplify this into a zext of a compare,
4948 if (NotExtCompare && N2C->getValue() == 1)
4951 // Get a SetCC of the condition
4952 // FIXME: Should probably make sure that setcc is legal if we ever have a
4953 // target where it isn't.
4954 SDOperand Temp, SCC;
4955 // cast from setcc result type to select result type
4956 if (AfterLegalize) {
4957 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4958 if (N2.getValueType() < SCC.getValueType())
4959 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
4961 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4963 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
4964 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4966 AddToWorkList(SCC.Val);
4967 AddToWorkList(Temp.Val);
4969 if (N2C->getValue() == 1)
4971 // shl setcc result by log2 n2c
4972 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
4973 DAG.getConstant(Log2_64(N2C->getValue()),
4974 TLI.getShiftAmountTy()));
4977 // Check to see if this is the equivalent of setcc
4978 // FIXME: Turn all of these into setcc if setcc if setcc is legal
4979 // otherwise, go ahead with the folds.
4980 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
4981 MVT::ValueType XType = N0.getValueType();
4982 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
4983 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4984 if (Res.getValueType() != VT)
4985 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
4989 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
4990 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
4991 TLI.isOperationLegal(ISD::CTLZ, XType)) {
4992 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
4993 return DAG.getNode(ISD::SRL, XType, Ctlz,
4994 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
4995 TLI.getShiftAmountTy()));
4997 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
4998 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
4999 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
5001 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
5002 DAG.getConstant(~0ULL, XType));
5003 return DAG.getNode(ISD::SRL, XType,
5004 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
5005 DAG.getConstant(MVT::getSizeInBits(XType)-1,
5006 TLI.getShiftAmountTy()));
5008 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
5009 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
5010 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
5011 DAG.getConstant(MVT::getSizeInBits(XType)-1,
5012 TLI.getShiftAmountTy()));
5013 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
5017 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
5018 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5019 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
5020 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
5021 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) {
5022 MVT::ValueType XType = N0.getValueType();
5023 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
5024 DAG.getConstant(MVT::getSizeInBits(XType)-1,
5025 TLI.getShiftAmountTy()));
5026 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
5027 AddToWorkList(Shift.Val);
5028 AddToWorkList(Add.Val);
5029 return DAG.getNode(ISD::XOR, XType, Add, Shift);
5031 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
5032 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5033 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
5034 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
5035 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
5036 MVT::ValueType XType = N0.getValueType();
5037 if (SubC->isNullValue() && MVT::isInteger(XType)) {
5038 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
5039 DAG.getConstant(MVT::getSizeInBits(XType)-1,
5040 TLI.getShiftAmountTy()));
5041 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
5042 AddToWorkList(Shift.Val);
5043 AddToWorkList(Add.Val);
5044 return DAG.getNode(ISD::XOR, XType, Add, Shift);
5052 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
5053 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
5054 SDOperand N1, ISD::CondCode Cond,
5055 bool foldBooleans) {
5056 TargetLowering::DAGCombinerInfo
5057 DagCombineInfo(DAG, !AfterLegalize, false, this);
5058 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
5061 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
5062 /// return a DAG expression to select that will generate the same value by
5063 /// multiplying by a magic number. See:
5064 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5065 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
5066 std::vector<SDNode*> Built;
5067 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
5069 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5075 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
5076 /// return a DAG expression to select that will generate the same value by
5077 /// multiplying by a magic number. See:
5078 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5079 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
5080 std::vector<SDNode*> Built;
5081 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
5083 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5089 /// FindBaseOffset - Return true if base is known not to alias with anything
5090 /// but itself. Provides base object and offset as results.
5091 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
5092 // Assume it is a primitive operation.
5093 Base = Ptr; Offset = 0;
5095 // If it's an adding a simple constant then integrate the offset.
5096 if (Base.getOpcode() == ISD::ADD) {
5097 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
5098 Base = Base.getOperand(0);
5099 Offset += C->getValue();
5103 // If it's any of the following then it can't alias with anything but itself.
5104 return isa<FrameIndexSDNode>(Base) ||
5105 isa<ConstantPoolSDNode>(Base) ||
5106 isa<GlobalAddressSDNode>(Base);
5109 /// isAlias - Return true if there is any possibility that the two addresses
5111 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
5112 const Value *SrcValue1, int SrcValueOffset1,
5113 SDOperand Ptr2, int64_t Size2,
5114 const Value *SrcValue2, int SrcValueOffset2)
5116 // If they are the same then they must be aliases.
5117 if (Ptr1 == Ptr2) return true;
5119 // Gather base node and offset information.
5120 SDOperand Base1, Base2;
5121 int64_t Offset1, Offset2;
5122 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
5123 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
5125 // If they have a same base address then...
5126 if (Base1 == Base2) {
5127 // Check to see if the addresses overlap.
5128 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
5131 // If we know both bases then they can't alias.
5132 if (KnownBase1 && KnownBase2) return false;
5134 if (CombinerGlobalAA) {
5135 // Use alias analysis information.
5136 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
5137 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
5138 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
5139 AliasAnalysis::AliasResult AAResult =
5140 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
5141 if (AAResult == AliasAnalysis::NoAlias)
5145 // Otherwise we have to assume they alias.
5149 /// FindAliasInfo - Extracts the relevant alias information from the memory
5150 /// node. Returns true if the operand was a load.
5151 bool DAGCombiner::FindAliasInfo(SDNode *N,
5152 SDOperand &Ptr, int64_t &Size,
5153 const Value *&SrcValue, int &SrcValueOffset) {
5154 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5155 Ptr = LD->getBasePtr();
5156 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
5157 SrcValue = LD->getSrcValue();
5158 SrcValueOffset = LD->getSrcValueOffset();
5160 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5161 Ptr = ST->getBasePtr();
5162 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
5163 SrcValue = ST->getSrcValue();
5164 SrcValueOffset = ST->getSrcValueOffset();
5166 assert(0 && "FindAliasInfo expected a memory operand");
5172 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
5173 /// looking for aliasing nodes and adding them to the Aliases vector.
5174 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
5175 SmallVector<SDOperand, 8> &Aliases) {
5176 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
5177 std::set<SDNode *> Visited; // Visited node set.
5179 // Get alias information for node.
5182 const Value *SrcValue;
5184 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
5187 Chains.push_back(OriginalChain);
5189 // Look at each chain and determine if it is an alias. If so, add it to the
5190 // aliases list. If not, then continue up the chain looking for the next
5192 while (!Chains.empty()) {
5193 SDOperand Chain = Chains.back();
5196 // Don't bother if we've been before.
5197 if (Visited.find(Chain.Val) != Visited.end()) continue;
5198 Visited.insert(Chain.Val);
5200 switch (Chain.getOpcode()) {
5201 case ISD::EntryToken:
5202 // Entry token is ideal chain operand, but handled in FindBetterChain.
5207 // Get alias information for Chain.
5210 const Value *OpSrcValue;
5211 int OpSrcValueOffset;
5212 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
5213 OpSrcValue, OpSrcValueOffset);
5215 // If chain is alias then stop here.
5216 if (!(IsLoad && IsOpLoad) &&
5217 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
5218 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
5219 Aliases.push_back(Chain);
5221 // Look further up the chain.
5222 Chains.push_back(Chain.getOperand(0));
5223 // Clean up old chain.
5224 AddToWorkList(Chain.Val);
5229 case ISD::TokenFactor:
5230 // We have to check each of the operands of the token factor, so we queue
5231 // then up. Adding the operands to the queue (stack) in reverse order
5232 // maintains the original order and increases the likelihood that getNode
5233 // will find a matching token factor (CSE.)
5234 for (unsigned n = Chain.getNumOperands(); n;)
5235 Chains.push_back(Chain.getOperand(--n));
5236 // Eliminate the token factor if we can.
5237 AddToWorkList(Chain.Val);
5241 // For all other instructions we will just have to take what we can get.
5242 Aliases.push_back(Chain);
5248 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
5249 /// for a better chain (aliasing node.)
5250 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
5251 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
5253 // Accumulate all the aliases to this node.
5254 GatherAllAliases(N, OldChain, Aliases);
5256 if (Aliases.size() == 0) {
5257 // If no operands then chain to entry token.
5258 return DAG.getEntryNode();
5259 } else if (Aliases.size() == 1) {
5260 // If a single operand then chain to it. We don't need to revisit it.
5264 // Construct a custom tailored token factor.
5265 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5266 &Aliases[0], Aliases.size());
5268 // Make sure the old chain gets cleaned up.
5269 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
5274 // SelectionDAG::Combine - This is the entry point for the file.
5276 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
5277 if (!RunningAfterLegalize && ViewDAGCombine1)
5279 if (RunningAfterLegalize && ViewDAGCombine2)
5281 /// run - This is the main entry point to this class.
5283 DAGCombiner(*this, AA).Run(RunningAfterLegalize);