1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/Support/Compiler.h"
40 #include "llvm/Support/CommandLine.h"
44 STATISTIC(NodesCombined , "Number of dag nodes combined");
45 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
46 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
51 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
52 cl::desc("Pop up a window to show dags before the first "
55 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
56 cl::desc("Pop up a window to show dags before the second "
59 static const bool ViewDAGCombine1 = false;
60 static const bool ViewDAGCombine2 = false;
64 CombinerAA("combiner-alias-analysis", cl::Hidden,
65 cl::desc("Turn on alias analysis during testing"));
68 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
69 cl::desc("Include global information in alias analysis"));
71 //------------------------------ DAGCombiner ---------------------------------//
73 class VISIBILITY_HIDDEN DAGCombiner {
78 // Worklist of all of the nodes that need to be simplified.
79 std::vector<SDNode*> WorkList;
81 // AA - Used for DAG load/store alias analysis.
84 /// AddUsersToWorkList - When an instruction is simplified, add all users of
85 /// the instruction to the work lists because they might get more simplified
88 void AddUsersToWorkList(SDNode *N) {
89 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
94 /// removeFromWorkList - remove all instances of N from the worklist.
96 void removeFromWorkList(SDNode *N) {
97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
102 /// AddToWorkList - Add to the work list making sure it's instance is at the
103 /// the back (next to be processed.)
104 void AddToWorkList(SDNode *N) {
105 removeFromWorkList(N);
106 WorkList.push_back(N);
109 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
111 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
113 DOUT << "\nReplacing.1 "; DEBUG(N->dump());
114 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
115 DOUT << " and " << NumTo-1 << " other values\n";
116 std::vector<SDNode*> NowDead;
117 DAG.ReplaceAllUsesWith(N, To, &NowDead);
120 // Push the new nodes and any users onto the worklist
121 for (unsigned i = 0, e = NumTo; i != e; ++i) {
122 AddToWorkList(To[i].Val);
123 AddUsersToWorkList(To[i].Val);
127 // Nodes can be reintroduced into the worklist. Make sure we do not
128 // process a node that has been replaced.
129 removeFromWorkList(N);
130 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
131 removeFromWorkList(NowDead[i]);
133 // Finally, since the node is now dead, remove it from the graph.
135 return SDOperand(N, 0);
138 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
139 return CombineTo(N, &Res, 1, AddTo);
142 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
144 SDOperand To[] = { Res0, Res1 };
145 return CombineTo(N, To, 2, AddTo);
149 /// SimplifyDemandedBits - Check the specified integer node value to see if
150 /// it can be simplified or if things it uses can be simplified by bit
151 /// propagation. If so, return true.
152 bool SimplifyDemandedBits(SDOperand Op) {
153 TargetLowering::TargetLoweringOpt TLO(DAG);
154 uint64_t KnownZero, KnownOne;
155 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
156 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
160 AddToWorkList(Op.Val);
162 // Replace the old value with the new one.
164 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump());
165 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
168 std::vector<SDNode*> NowDead;
169 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
171 // Push the new node and any (possibly new) users onto the worklist.
172 AddToWorkList(TLO.New.Val);
173 AddUsersToWorkList(TLO.New.Val);
175 // Nodes can end up on the worklist more than once. Make sure we do
176 // not process a node that has been replaced.
177 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
178 removeFromWorkList(NowDead[i]);
180 // Finally, if the node is now dead, remove it from the graph. The node
181 // may not be dead if the replacement process recursively simplified to
182 // something else needing this node.
183 if (TLO.Old.Val->use_empty()) {
184 removeFromWorkList(TLO.Old.Val);
185 DAG.DeleteNode(TLO.Old.Val);
190 bool CombineToPreIndexedLoadStore(SDNode *N);
191 bool CombineToPostIndexedLoadStore(SDNode *N);
194 /// visit - call the node-specific routine that knows how to fold each
195 /// particular type of node.
196 SDOperand visit(SDNode *N);
198 // Visitation implementation - Implement dag node combining for different
199 // node types. The semantics are as follows:
201 // SDOperand.Val == 0 - No change was made
202 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
203 // otherwise - N should be replaced by the returned Operand.
205 SDOperand visitTokenFactor(SDNode *N);
206 SDOperand visitADD(SDNode *N);
207 SDOperand visitSUB(SDNode *N);
208 SDOperand visitADDC(SDNode *N);
209 SDOperand visitADDE(SDNode *N);
210 SDOperand visitMUL(SDNode *N);
211 SDOperand visitSDIV(SDNode *N);
212 SDOperand visitUDIV(SDNode *N);
213 SDOperand visitSREM(SDNode *N);
214 SDOperand visitUREM(SDNode *N);
215 SDOperand visitMULHU(SDNode *N);
216 SDOperand visitMULHS(SDNode *N);
217 SDOperand visitAND(SDNode *N);
218 SDOperand visitOR(SDNode *N);
219 SDOperand visitXOR(SDNode *N);
220 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
221 SDOperand visitSHL(SDNode *N);
222 SDOperand visitSRA(SDNode *N);
223 SDOperand visitSRL(SDNode *N);
224 SDOperand visitCTLZ(SDNode *N);
225 SDOperand visitCTTZ(SDNode *N);
226 SDOperand visitCTPOP(SDNode *N);
227 SDOperand visitSELECT(SDNode *N);
228 SDOperand visitSELECT_CC(SDNode *N);
229 SDOperand visitSETCC(SDNode *N);
230 SDOperand visitSIGN_EXTEND(SDNode *N);
231 SDOperand visitZERO_EXTEND(SDNode *N);
232 SDOperand visitANY_EXTEND(SDNode *N);
233 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
234 SDOperand visitTRUNCATE(SDNode *N);
235 SDOperand visitBIT_CONVERT(SDNode *N);
236 SDOperand visitVBIT_CONVERT(SDNode *N);
237 SDOperand visitFADD(SDNode *N);
238 SDOperand visitFSUB(SDNode *N);
239 SDOperand visitFMUL(SDNode *N);
240 SDOperand visitFDIV(SDNode *N);
241 SDOperand visitFREM(SDNode *N);
242 SDOperand visitFCOPYSIGN(SDNode *N);
243 SDOperand visitSINT_TO_FP(SDNode *N);
244 SDOperand visitUINT_TO_FP(SDNode *N);
245 SDOperand visitFP_TO_SINT(SDNode *N);
246 SDOperand visitFP_TO_UINT(SDNode *N);
247 SDOperand visitFP_ROUND(SDNode *N);
248 SDOperand visitFP_ROUND_INREG(SDNode *N);
249 SDOperand visitFP_EXTEND(SDNode *N);
250 SDOperand visitFNEG(SDNode *N);
251 SDOperand visitFABS(SDNode *N);
252 SDOperand visitBRCOND(SDNode *N);
253 SDOperand visitBR_CC(SDNode *N);
254 SDOperand visitLOAD(SDNode *N);
255 SDOperand visitSTORE(SDNode *N);
256 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
257 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
258 SDOperand visitVBUILD_VECTOR(SDNode *N);
259 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
260 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
262 SDOperand XformToShuffleWithZero(SDNode *N);
263 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
265 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
266 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
267 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
268 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
269 SDOperand N3, ISD::CondCode CC);
270 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
271 ISD::CondCode Cond, bool foldBooleans = true);
272 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
273 SDOperand BuildSDIV(SDNode *N);
274 SDOperand BuildUDIV(SDNode *N);
275 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
276 SDOperand ReduceLoadWidth(SDNode *N);
278 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
279 /// looking for aliasing nodes and adding them to the Aliases vector.
280 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
281 SmallVector<SDOperand, 8> &Aliases);
283 /// isAlias - Return true if there is any possibility that the two addresses
285 bool isAlias(SDOperand Ptr1, int64_t Size1,
286 const Value *SrcValue1, int SrcValueOffset1,
287 SDOperand Ptr2, int64_t Size2,
288 const Value *SrcValue2, int SrcValueOffset2);
290 /// FindAliasInfo - Extracts the relevant alias information from the memory
291 /// node. Returns true if the operand was a load.
292 bool FindAliasInfo(SDNode *N,
293 SDOperand &Ptr, int64_t &Size,
294 const Value *&SrcValue, int &SrcValueOffset);
296 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
297 /// looking for a better chain (aliasing node.)
298 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
301 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
303 TLI(D.getTargetLoweringInfo()),
304 AfterLegalize(false),
307 /// Run - runs the dag combiner on all nodes in the work list
308 void Run(bool RunningAfterLegalize);
312 //===----------------------------------------------------------------------===//
313 // TargetLowering::DAGCombinerInfo implementation
314 //===----------------------------------------------------------------------===//
316 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
317 ((DAGCombiner*)DC)->AddToWorkList(N);
320 SDOperand TargetLowering::DAGCombinerInfo::
321 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
322 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
325 SDOperand TargetLowering::DAGCombinerInfo::
326 CombineTo(SDNode *N, SDOperand Res) {
327 return ((DAGCombiner*)DC)->CombineTo(N, Res);
331 SDOperand TargetLowering::DAGCombinerInfo::
332 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
333 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
339 //===----------------------------------------------------------------------===//
342 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
343 // that selects between the values 1 and 0, making it equivalent to a setcc.
344 // Also, set the incoming LHS, RHS, and CC references to the appropriate
345 // nodes based on the type of node we are checking. This simplifies life a
346 // bit for the callers.
347 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
349 if (N.getOpcode() == ISD::SETCC) {
350 LHS = N.getOperand(0);
351 RHS = N.getOperand(1);
352 CC = N.getOperand(2);
355 if (N.getOpcode() == ISD::SELECT_CC &&
356 N.getOperand(2).getOpcode() == ISD::Constant &&
357 N.getOperand(3).getOpcode() == ISD::Constant &&
358 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
359 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
360 LHS = N.getOperand(0);
361 RHS = N.getOperand(1);
362 CC = N.getOperand(4);
368 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
369 // one use. If this is true, it allows the users to invert the operation for
370 // free when it is profitable to do so.
371 static bool isOneUseSetCC(SDOperand N) {
372 SDOperand N0, N1, N2;
373 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
378 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
379 MVT::ValueType VT = N0.getValueType();
380 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
381 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
382 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
383 if (isa<ConstantSDNode>(N1)) {
384 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
385 AddToWorkList(OpNode.Val);
386 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
387 } else if (N0.hasOneUse()) {
388 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
389 AddToWorkList(OpNode.Val);
390 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
393 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
394 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
395 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
396 if (isa<ConstantSDNode>(N0)) {
397 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
398 AddToWorkList(OpNode.Val);
399 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
400 } else if (N1.hasOneUse()) {
401 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
402 AddToWorkList(OpNode.Val);
403 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
409 void DAGCombiner::Run(bool RunningAfterLegalize) {
410 // set the instance variable, so that the various visit routines may use it.
411 AfterLegalize = RunningAfterLegalize;
413 // Add all the dag nodes to the worklist.
414 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
415 E = DAG.allnodes_end(); I != E; ++I)
416 WorkList.push_back(I);
418 // Create a dummy node (which is not added to allnodes), that adds a reference
419 // to the root node, preventing it from being deleted, and tracking any
420 // changes of the root.
421 HandleSDNode Dummy(DAG.getRoot());
423 // The root of the dag may dangle to deleted nodes until the dag combiner is
424 // done. Set it to null to avoid confusion.
425 DAG.setRoot(SDOperand());
427 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
428 TargetLowering::DAGCombinerInfo
429 DagCombineInfo(DAG, !RunningAfterLegalize, false, this);
431 // while the worklist isn't empty, inspect the node on the end of it and
432 // try and combine it.
433 while (!WorkList.empty()) {
434 SDNode *N = WorkList.back();
437 // If N has no uses, it is dead. Make sure to revisit all N's operands once
438 // N is deleted from the DAG, since they too may now be dead or may have a
439 // reduced number of uses, allowing other xforms.
440 if (N->use_empty() && N != &Dummy) {
441 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
442 AddToWorkList(N->getOperand(i).Val);
448 SDOperand RV = visit(N);
450 // If nothing happened, try a target-specific DAG combine.
452 assert(N->getOpcode() != ISD::DELETED_NODE &&
453 "Node was deleted but visit returned NULL!");
454 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
455 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
456 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
461 // If we get back the same node we passed in, rather than a new node or
462 // zero, we know that the node must have defined multiple values and
463 // CombineTo was used. Since CombineTo takes care of the worklist
464 // mechanics for us, we have no work to do in this case.
466 assert(N->getOpcode() != ISD::DELETED_NODE &&
467 RV.Val->getOpcode() != ISD::DELETED_NODE &&
468 "Node was deleted but visit returned new node!");
470 DOUT << "\nReplacing.3 "; DEBUG(N->dump());
471 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
473 std::vector<SDNode*> NowDead;
474 if (N->getNumValues() == RV.Val->getNumValues())
475 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
477 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
479 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
482 // Push the new node and any users onto the worklist
483 AddToWorkList(RV.Val);
484 AddUsersToWorkList(RV.Val);
486 // Nodes can be reintroduced into the worklist. Make sure we do not
487 // process a node that has been replaced.
488 removeFromWorkList(N);
489 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
490 removeFromWorkList(NowDead[i]);
492 // Finally, since the node is now dead, remove it from the graph.
498 // If the root changed (e.g. it was a dead load, update the root).
499 DAG.setRoot(Dummy.getValue());
502 SDOperand DAGCombiner::visit(SDNode *N) {
503 switch(N->getOpcode()) {
505 case ISD::TokenFactor: return visitTokenFactor(N);
506 case ISD::ADD: return visitADD(N);
507 case ISD::SUB: return visitSUB(N);
508 case ISD::ADDC: return visitADDC(N);
509 case ISD::ADDE: return visitADDE(N);
510 case ISD::MUL: return visitMUL(N);
511 case ISD::SDIV: return visitSDIV(N);
512 case ISD::UDIV: return visitUDIV(N);
513 case ISD::SREM: return visitSREM(N);
514 case ISD::UREM: return visitUREM(N);
515 case ISD::MULHU: return visitMULHU(N);
516 case ISD::MULHS: return visitMULHS(N);
517 case ISD::AND: return visitAND(N);
518 case ISD::OR: return visitOR(N);
519 case ISD::XOR: return visitXOR(N);
520 case ISD::SHL: return visitSHL(N);
521 case ISD::SRA: return visitSRA(N);
522 case ISD::SRL: return visitSRL(N);
523 case ISD::CTLZ: return visitCTLZ(N);
524 case ISD::CTTZ: return visitCTTZ(N);
525 case ISD::CTPOP: return visitCTPOP(N);
526 case ISD::SELECT: return visitSELECT(N);
527 case ISD::SELECT_CC: return visitSELECT_CC(N);
528 case ISD::SETCC: return visitSETCC(N);
529 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
530 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
531 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
532 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
533 case ISD::TRUNCATE: return visitTRUNCATE(N);
534 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
535 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
536 case ISD::FADD: return visitFADD(N);
537 case ISD::FSUB: return visitFSUB(N);
538 case ISD::FMUL: return visitFMUL(N);
539 case ISD::FDIV: return visitFDIV(N);
540 case ISD::FREM: return visitFREM(N);
541 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
542 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
543 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
544 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
545 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
546 case ISD::FP_ROUND: return visitFP_ROUND(N);
547 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
548 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
549 case ISD::FNEG: return visitFNEG(N);
550 case ISD::FABS: return visitFABS(N);
551 case ISD::BRCOND: return visitBRCOND(N);
552 case ISD::BR_CC: return visitBR_CC(N);
553 case ISD::LOAD: return visitLOAD(N);
554 case ISD::STORE: return visitSTORE(N);
555 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
556 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
557 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
558 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
559 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
560 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
561 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
562 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
563 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
564 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
565 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
566 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
567 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
572 /// getInputChainForNode - Given a node, return its input chain if it has one,
573 /// otherwise return a null sd operand.
574 static SDOperand getInputChainForNode(SDNode *N) {
575 if (unsigned NumOps = N->getNumOperands()) {
576 if (N->getOperand(0).getValueType() == MVT::Other)
577 return N->getOperand(0);
578 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
579 return N->getOperand(NumOps-1);
580 for (unsigned i = 1; i < NumOps-1; ++i)
581 if (N->getOperand(i).getValueType() == MVT::Other)
582 return N->getOperand(i);
584 return SDOperand(0, 0);
587 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
588 // If N has two operands, where one has an input chain equal to the other,
589 // the 'other' chain is redundant.
590 if (N->getNumOperands() == 2) {
591 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
592 return N->getOperand(0);
593 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
594 return N->getOperand(1);
598 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
599 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
600 bool Changed = false; // If we should replace this token factor.
602 // Start out with this token factor.
605 // Iterate through token factors. The TFs grows when new token factors are
607 for (unsigned i = 0; i < TFs.size(); ++i) {
610 // Check each of the operands.
611 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
612 SDOperand Op = TF->getOperand(i);
614 switch (Op.getOpcode()) {
615 case ISD::EntryToken:
616 // Entry tokens don't need to be added to the list. They are
621 case ISD::TokenFactor:
622 if ((CombinerAA || Op.hasOneUse()) &&
623 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
624 // Queue up for processing.
625 TFs.push_back(Op.Val);
626 // Clean up in case the token factor is removed.
627 AddToWorkList(Op.Val);
634 // Only add if not there prior.
635 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end())
644 // If we've change things around then replace token factor.
646 if (Ops.size() == 0) {
647 // The entry token is the only possible outcome.
648 Result = DAG.getEntryNode();
650 // New and improved token factor.
651 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
654 // Don't add users to work list.
655 return CombineTo(N, Result, false);
662 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
663 MVT::ValueType VT = N0.getValueType();
664 SDOperand N00 = N0.getOperand(0);
665 SDOperand N01 = N0.getOperand(1);
666 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
667 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
668 isa<ConstantSDNode>(N00.getOperand(1))) {
669 N0 = DAG.getNode(ISD::ADD, VT,
670 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
671 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
672 return DAG.getNode(ISD::ADD, VT, N0, N1);
677 SDOperand DAGCombiner::visitADD(SDNode *N) {
678 SDOperand N0 = N->getOperand(0);
679 SDOperand N1 = N->getOperand(1);
680 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
681 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
682 MVT::ValueType VT = N0.getValueType();
684 // fold (add c1, c2) -> c1+c2
686 return DAG.getNode(ISD::ADD, VT, N0, N1);
687 // canonicalize constant to RHS
689 return DAG.getNode(ISD::ADD, VT, N1, N0);
690 // fold (add x, 0) -> x
691 if (N1C && N1C->isNullValue())
693 // fold ((c1-A)+c2) -> (c1+c2)-A
694 if (N1C && N0.getOpcode() == ISD::SUB)
695 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
696 return DAG.getNode(ISD::SUB, VT,
697 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
700 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
703 // fold ((0-A) + B) -> B-A
704 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
705 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
706 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
707 // fold (A + (0-B)) -> A-B
708 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
709 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
710 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
711 // fold (A+(B-A)) -> B
712 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
713 return N1.getOperand(0);
715 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
716 return SDOperand(N, 0);
718 // fold (a+b) -> (a|b) iff a and b share no bits.
719 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
720 uint64_t LHSZero, LHSOne;
721 uint64_t RHSZero, RHSOne;
722 uint64_t Mask = MVT::getIntVTBitMask(VT);
723 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
725 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
727 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
728 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
729 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
730 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
731 return DAG.getNode(ISD::OR, VT, N0, N1);
735 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
736 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
737 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
738 if (Result.Val) return Result;
740 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
741 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
742 if (Result.Val) return Result;
748 SDOperand DAGCombiner::visitADDC(SDNode *N) {
749 SDOperand N0 = N->getOperand(0);
750 SDOperand N1 = N->getOperand(1);
751 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
752 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
753 MVT::ValueType VT = N0.getValueType();
755 // If the flag result is dead, turn this into an ADD.
756 if (N->hasNUsesOfValue(0, 1))
757 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
758 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
760 // canonicalize constant to RHS.
762 SDOperand Ops[] = { N1, N0 };
763 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
766 // fold (addc x, 0) -> x + no carry out
767 if (N1C && N1C->isNullValue())
768 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
770 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
771 uint64_t LHSZero, LHSOne;
772 uint64_t RHSZero, RHSOne;
773 uint64_t Mask = MVT::getIntVTBitMask(VT);
774 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
776 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
778 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
779 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
780 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
781 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
782 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
783 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
789 SDOperand DAGCombiner::visitADDE(SDNode *N) {
790 SDOperand N0 = N->getOperand(0);
791 SDOperand N1 = N->getOperand(1);
792 SDOperand CarryIn = N->getOperand(2);
793 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
794 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
795 //MVT::ValueType VT = N0.getValueType();
797 // canonicalize constant to RHS
799 SDOperand Ops[] = { N1, N0, CarryIn };
800 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
803 // fold (adde x, y, false) -> (addc x, y)
804 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
805 SDOperand Ops[] = { N1, N0 };
806 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
814 SDOperand DAGCombiner::visitSUB(SDNode *N) {
815 SDOperand N0 = N->getOperand(0);
816 SDOperand N1 = N->getOperand(1);
817 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
818 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
819 MVT::ValueType VT = N0.getValueType();
821 // fold (sub x, x) -> 0
823 return DAG.getConstant(0, N->getValueType(0));
824 // fold (sub c1, c2) -> c1-c2
826 return DAG.getNode(ISD::SUB, VT, N0, N1);
827 // fold (sub x, c) -> (add x, -c)
829 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
831 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
832 return N0.getOperand(1);
834 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
835 return N0.getOperand(0);
839 SDOperand DAGCombiner::visitMUL(SDNode *N) {
840 SDOperand N0 = N->getOperand(0);
841 SDOperand N1 = N->getOperand(1);
842 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
843 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
844 MVT::ValueType VT = N0.getValueType();
846 // fold (mul c1, c2) -> c1*c2
848 return DAG.getNode(ISD::MUL, VT, N0, N1);
849 // canonicalize constant to RHS
851 return DAG.getNode(ISD::MUL, VT, N1, N0);
852 // fold (mul x, 0) -> 0
853 if (N1C && N1C->isNullValue())
855 // fold (mul x, -1) -> 0-x
856 if (N1C && N1C->isAllOnesValue())
857 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
858 // fold (mul x, (1 << c)) -> x << c
859 if (N1C && isPowerOf2_64(N1C->getValue()))
860 return DAG.getNode(ISD::SHL, VT, N0,
861 DAG.getConstant(Log2_64(N1C->getValue()),
862 TLI.getShiftAmountTy()));
863 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
864 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
865 // FIXME: If the input is something that is easily negated (e.g. a
866 // single-use add), we should put the negate there.
867 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
868 DAG.getNode(ISD::SHL, VT, N0,
869 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
870 TLI.getShiftAmountTy())));
873 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
874 if (N1C && N0.getOpcode() == ISD::SHL &&
875 isa<ConstantSDNode>(N0.getOperand(1))) {
876 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
877 AddToWorkList(C3.Val);
878 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
881 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
884 SDOperand Sh(0,0), Y(0,0);
885 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
886 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
887 N0.Val->hasOneUse()) {
889 } else if (N1.getOpcode() == ISD::SHL &&
890 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
894 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
895 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
898 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
899 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
900 isa<ConstantSDNode>(N0.getOperand(1))) {
901 return DAG.getNode(ISD::ADD, VT,
902 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
903 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
907 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
913 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
914 SDOperand N0 = N->getOperand(0);
915 SDOperand N1 = N->getOperand(1);
916 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
917 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
918 MVT::ValueType VT = N->getValueType(0);
920 // fold (sdiv c1, c2) -> c1/c2
921 if (N0C && N1C && !N1C->isNullValue())
922 return DAG.getNode(ISD::SDIV, VT, N0, N1);
923 // fold (sdiv X, 1) -> X
924 if (N1C && N1C->getSignExtended() == 1LL)
926 // fold (sdiv X, -1) -> 0-X
927 if (N1C && N1C->isAllOnesValue())
928 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
929 // If we know the sign bits of both operands are zero, strength reduce to a
930 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
931 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
932 if (TLI.MaskedValueIsZero(N1, SignBit) &&
933 TLI.MaskedValueIsZero(N0, SignBit))
934 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
935 // fold (sdiv X, pow2) -> simple ops after legalize
936 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
937 (isPowerOf2_64(N1C->getSignExtended()) ||
938 isPowerOf2_64(-N1C->getSignExtended()))) {
939 // If dividing by powers of two is cheap, then don't perform the following
941 if (TLI.isPow2DivCheap())
943 int64_t pow2 = N1C->getSignExtended();
944 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
945 unsigned lg2 = Log2_64(abs2);
946 // Splat the sign bit into the register
947 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
948 DAG.getConstant(MVT::getSizeInBits(VT)-1,
949 TLI.getShiftAmountTy()));
950 AddToWorkList(SGN.Val);
951 // Add (N0 < 0) ? abs2 - 1 : 0;
952 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
953 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
954 TLI.getShiftAmountTy()));
955 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
956 AddToWorkList(SRL.Val);
957 AddToWorkList(ADD.Val); // Divide by pow2
958 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
959 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
960 // If we're dividing by a positive value, we're done. Otherwise, we must
961 // negate the result.
964 AddToWorkList(SRA.Val);
965 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
967 // if integer divide is expensive and we satisfy the requirements, emit an
968 // alternate sequence.
969 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
970 !TLI.isIntDivCheap()) {
971 SDOperand Op = BuildSDIV(N);
972 if (Op.Val) return Op;
977 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
978 SDOperand N0 = N->getOperand(0);
979 SDOperand N1 = N->getOperand(1);
980 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
981 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
982 MVT::ValueType VT = N->getValueType(0);
984 // fold (udiv c1, c2) -> c1/c2
985 if (N0C && N1C && !N1C->isNullValue())
986 return DAG.getNode(ISD::UDIV, VT, N0, N1);
987 // fold (udiv x, (1 << c)) -> x >>u c
988 if (N1C && isPowerOf2_64(N1C->getValue()))
989 return DAG.getNode(ISD::SRL, VT, N0,
990 DAG.getConstant(Log2_64(N1C->getValue()),
991 TLI.getShiftAmountTy()));
992 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
993 if (N1.getOpcode() == ISD::SHL) {
994 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
995 if (isPowerOf2_64(SHC->getValue())) {
996 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
997 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
998 DAG.getConstant(Log2_64(SHC->getValue()),
1000 AddToWorkList(Add.Val);
1001 return DAG.getNode(ISD::SRL, VT, N0, Add);
1005 // fold (udiv x, c) -> alternate
1006 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1007 SDOperand Op = BuildUDIV(N);
1008 if (Op.Val) return Op;
1013 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1014 SDOperand N0 = N->getOperand(0);
1015 SDOperand N1 = N->getOperand(1);
1016 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1017 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1018 MVT::ValueType VT = N->getValueType(0);
1020 // fold (srem c1, c2) -> c1%c2
1021 if (N0C && N1C && !N1C->isNullValue())
1022 return DAG.getNode(ISD::SREM, VT, N0, N1);
1023 // If we know the sign bits of both operands are zero, strength reduce to a
1024 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1025 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1026 if (TLI.MaskedValueIsZero(N1, SignBit) &&
1027 TLI.MaskedValueIsZero(N0, SignBit))
1028 return DAG.getNode(ISD::UREM, VT, N0, N1);
1030 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1031 // the remainder operation.
1032 if (N1C && !N1C->isNullValue()) {
1033 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1034 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1035 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1036 AddToWorkList(Div.Val);
1037 AddToWorkList(Mul.Val);
1044 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1045 SDOperand N0 = N->getOperand(0);
1046 SDOperand N1 = N->getOperand(1);
1047 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1048 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1049 MVT::ValueType VT = N->getValueType(0);
1051 // fold (urem c1, c2) -> c1%c2
1052 if (N0C && N1C && !N1C->isNullValue())
1053 return DAG.getNode(ISD::UREM, VT, N0, N1);
1054 // fold (urem x, pow2) -> (and x, pow2-1)
1055 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1056 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1057 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1058 if (N1.getOpcode() == ISD::SHL) {
1059 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1060 if (isPowerOf2_64(SHC->getValue())) {
1061 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1062 AddToWorkList(Add.Val);
1063 return DAG.getNode(ISD::AND, VT, N0, Add);
1068 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1069 // the remainder operation.
1070 if (N1C && !N1C->isNullValue()) {
1071 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1072 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1073 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1074 AddToWorkList(Div.Val);
1075 AddToWorkList(Mul.Val);
1082 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1083 SDOperand N0 = N->getOperand(0);
1084 SDOperand N1 = N->getOperand(1);
1085 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1087 // fold (mulhs x, 0) -> 0
1088 if (N1C && N1C->isNullValue())
1090 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1091 if (N1C && N1C->getValue() == 1)
1092 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1093 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1094 TLI.getShiftAmountTy()));
1098 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1099 SDOperand N0 = N->getOperand(0);
1100 SDOperand N1 = N->getOperand(1);
1101 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1103 // fold (mulhu x, 0) -> 0
1104 if (N1C && N1C->isNullValue())
1106 // fold (mulhu x, 1) -> 0
1107 if (N1C && N1C->getValue() == 1)
1108 return DAG.getConstant(0, N0.getValueType());
1112 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1113 /// two operands of the same opcode, try to simplify it.
1114 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1115 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1116 MVT::ValueType VT = N0.getValueType();
1117 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1119 // For each of OP in AND/OR/XOR:
1120 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1121 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1122 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1123 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1124 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1125 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1126 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1127 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1128 N0.getOperand(0).getValueType(),
1129 N0.getOperand(0), N1.getOperand(0));
1130 AddToWorkList(ORNode.Val);
1131 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1134 // For each of OP in SHL/SRL/SRA/AND...
1135 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1136 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1137 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1138 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1139 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1140 N0.getOperand(1) == N1.getOperand(1)) {
1141 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1142 N0.getOperand(0).getValueType(),
1143 N0.getOperand(0), N1.getOperand(0));
1144 AddToWorkList(ORNode.Val);
1145 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1151 SDOperand DAGCombiner::visitAND(SDNode *N) {
1152 SDOperand N0 = N->getOperand(0);
1153 SDOperand N1 = N->getOperand(1);
1154 SDOperand LL, LR, RL, RR, CC0, CC1;
1155 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1156 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1157 MVT::ValueType VT = N1.getValueType();
1159 // fold (and c1, c2) -> c1&c2
1161 return DAG.getNode(ISD::AND, VT, N0, N1);
1162 // canonicalize constant to RHS
1164 return DAG.getNode(ISD::AND, VT, N1, N0);
1165 // fold (and x, -1) -> x
1166 if (N1C && N1C->isAllOnesValue())
1168 // if (and x, c) is known to be zero, return 0
1169 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1170 return DAG.getConstant(0, VT);
1172 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1175 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1176 if (N1C && N0.getOpcode() == ISD::OR)
1177 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1178 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1180 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1181 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1182 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1183 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1184 ~N1C->getValue() & InMask)) {
1185 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1188 // Replace uses of the AND with uses of the Zero extend node.
1191 // We actually want to replace all uses of the any_extend with the
1192 // zero_extend, to avoid duplicating things. This will later cause this
1193 // AND to be folded.
1194 CombineTo(N0.Val, Zext);
1195 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1198 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1199 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1200 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1201 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1203 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1204 MVT::isInteger(LL.getValueType())) {
1205 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1206 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1207 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1208 AddToWorkList(ORNode.Val);
1209 return DAG.getSetCC(VT, ORNode, LR, Op1);
1211 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1212 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1213 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1214 AddToWorkList(ANDNode.Val);
1215 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1217 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1218 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1219 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1220 AddToWorkList(ORNode.Val);
1221 return DAG.getSetCC(VT, ORNode, LR, Op1);
1224 // canonicalize equivalent to ll == rl
1225 if (LL == RR && LR == RL) {
1226 Op1 = ISD::getSetCCSwappedOperands(Op1);
1229 if (LL == RL && LR == RR) {
1230 bool isInteger = MVT::isInteger(LL.getValueType());
1231 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1232 if (Result != ISD::SETCC_INVALID)
1233 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1237 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1238 if (N0.getOpcode() == N1.getOpcode()) {
1239 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1240 if (Tmp.Val) return Tmp;
1243 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1244 // fold (and (sra)) -> (and (srl)) when possible.
1245 if (!MVT::isVector(VT) &&
1246 SimplifyDemandedBits(SDOperand(N, 0)))
1247 return SDOperand(N, 0);
1248 // fold (zext_inreg (extload x)) -> (zextload x)
1249 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
1250 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1251 MVT::ValueType EVT = LN0->getLoadedVT();
1252 // If we zero all the possible extended bits, then we can turn this into
1253 // a zextload if we are running before legalize or the operation is legal.
1254 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1255 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1256 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1257 LN0->getBasePtr(), LN0->getSrcValue(),
1258 LN0->getSrcValueOffset(), EVT);
1260 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1261 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1264 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1265 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
1267 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1268 MVT::ValueType EVT = LN0->getLoadedVT();
1269 // If we zero all the possible extended bits, then we can turn this into
1270 // a zextload if we are running before legalize or the operation is legal.
1271 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1272 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1273 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1274 LN0->getBasePtr(), LN0->getSrcValue(),
1275 LN0->getSrcValueOffset(), EVT);
1277 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1278 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1282 // fold (and (load x), 255) -> (zextload x, i8)
1283 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1284 if (N1C && N0.getOpcode() == ISD::LOAD) {
1285 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1286 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1287 LN0->getAddressingMode() == ISD::UNINDEXED &&
1289 MVT::ValueType EVT, LoadedVT;
1290 if (N1C->getValue() == 255)
1292 else if (N1C->getValue() == 65535)
1294 else if (N1C->getValue() == ~0U)
1299 LoadedVT = LN0->getLoadedVT();
1300 if (EVT != MVT::Other && LoadedVT > EVT &&
1301 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1302 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1303 // For big endian targets, we need to add an offset to the pointer to
1304 // load the correct bytes. For little endian systems, we merely need to
1305 // read fewer bytes from the same pointer.
1307 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1308 SDOperand NewPtr = LN0->getBasePtr();
1309 if (!TLI.isLittleEndian())
1310 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1311 DAG.getConstant(PtrOff, PtrType));
1312 AddToWorkList(NewPtr.Val);
1314 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1315 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
1317 CombineTo(N0.Val, Load, Load.getValue(1));
1318 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1326 SDOperand DAGCombiner::visitOR(SDNode *N) {
1327 SDOperand N0 = N->getOperand(0);
1328 SDOperand N1 = N->getOperand(1);
1329 SDOperand LL, LR, RL, RR, CC0, CC1;
1330 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1331 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1332 MVT::ValueType VT = N1.getValueType();
1333 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1335 // fold (or c1, c2) -> c1|c2
1337 return DAG.getNode(ISD::OR, VT, N0, N1);
1338 // canonicalize constant to RHS
1340 return DAG.getNode(ISD::OR, VT, N1, N0);
1341 // fold (or x, 0) -> x
1342 if (N1C && N1C->isNullValue())
1344 // fold (or x, -1) -> -1
1345 if (N1C && N1C->isAllOnesValue())
1347 // fold (or x, c) -> c iff (x & ~c) == 0
1349 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1352 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1355 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1356 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1357 isa<ConstantSDNode>(N0.getOperand(1))) {
1358 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1359 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1361 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1363 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1364 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1365 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1366 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1368 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1369 MVT::isInteger(LL.getValueType())) {
1370 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1371 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1372 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1373 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1374 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1375 AddToWorkList(ORNode.Val);
1376 return DAG.getSetCC(VT, ORNode, LR, Op1);
1378 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1379 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1380 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1381 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1382 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1383 AddToWorkList(ANDNode.Val);
1384 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1387 // canonicalize equivalent to ll == rl
1388 if (LL == RR && LR == RL) {
1389 Op1 = ISD::getSetCCSwappedOperands(Op1);
1392 if (LL == RL && LR == RR) {
1393 bool isInteger = MVT::isInteger(LL.getValueType());
1394 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1395 if (Result != ISD::SETCC_INVALID)
1396 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1400 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1401 if (N0.getOpcode() == N1.getOpcode()) {
1402 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1403 if (Tmp.Val) return Tmp;
1406 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1407 if (N0.getOpcode() == ISD::AND &&
1408 N1.getOpcode() == ISD::AND &&
1409 N0.getOperand(1).getOpcode() == ISD::Constant &&
1410 N1.getOperand(1).getOpcode() == ISD::Constant &&
1411 // Don't increase # computations.
1412 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1413 // We can only do this xform if we know that bits from X that are set in C2
1414 // but not in C1 are already zero. Likewise for Y.
1415 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1416 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1418 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1419 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1420 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1421 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1426 // See if this is some rotate idiom.
1427 if (SDNode *Rot = MatchRotate(N0, N1))
1428 return SDOperand(Rot, 0);
1434 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1435 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1436 if (Op.getOpcode() == ISD::AND) {
1437 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1438 Mask = Op.getOperand(1);
1439 Op = Op.getOperand(0);
1445 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1453 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1454 // idioms for rotate, and if the target supports rotation instructions, generate
1456 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1457 // Must be a legal type. Expanded an promoted things won't work with rotates.
1458 MVT::ValueType VT = LHS.getValueType();
1459 if (!TLI.isTypeLegal(VT)) return 0;
1461 // The target must have at least one rotate flavor.
1462 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1463 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1464 if (!HasROTL && !HasROTR) return 0;
1466 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1467 SDOperand LHSShift; // The shift.
1468 SDOperand LHSMask; // AND value if any.
1469 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1470 return 0; // Not part of a rotate.
1472 SDOperand RHSShift; // The shift.
1473 SDOperand RHSMask; // AND value if any.
1474 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1475 return 0; // Not part of a rotate.
1477 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1478 return 0; // Not shifting the same value.
1480 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1481 return 0; // Shifts must disagree.
1483 // Canonicalize shl to left side in a shl/srl pair.
1484 if (RHSShift.getOpcode() == ISD::SHL) {
1485 std::swap(LHS, RHS);
1486 std::swap(LHSShift, RHSShift);
1487 std::swap(LHSMask , RHSMask );
1490 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1491 SDOperand LHSShiftArg = LHSShift.getOperand(0);
1492 SDOperand LHSShiftAmt = LHSShift.getOperand(1);
1493 SDOperand RHSShiftAmt = RHSShift.getOperand(1);
1495 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1496 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1497 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
1498 RHSShiftAmt.getOpcode() == ISD::Constant) {
1499 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
1500 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
1501 if ((LShVal + RShVal) != OpSizeInBits)
1506 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
1508 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
1510 // If there is an AND of either shifted operand, apply it to the result.
1511 if (LHSMask.Val || RHSMask.Val) {
1512 uint64_t Mask = MVT::getIntVTBitMask(VT);
1515 uint64_t RHSBits = (1ULL << LShVal)-1;
1516 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1519 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1520 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1523 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1529 // If there is a mask here, and we have a variable shift, we can't be sure
1530 // that we're masking out the right stuff.
1531 if (LHSMask.Val || RHSMask.Val)
1534 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1535 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1536 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
1537 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
1538 if (ConstantSDNode *SUBC =
1539 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
1540 if (SUBC->getValue() == OpSizeInBits)
1542 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1544 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1548 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1549 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1550 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
1551 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
1552 if (ConstantSDNode *SUBC =
1553 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
1554 if (SUBC->getValue() == OpSizeInBits)
1556 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1558 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1562 // Look for sign/zext/any-extended cases:
1563 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1564 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1565 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
1566 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1567 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1568 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
1569 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
1570 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
1571 if (RExtOp0.getOpcode() == ISD::SUB &&
1572 RExtOp0.getOperand(1) == LExtOp0) {
1573 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1575 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1576 // (rotl x, (sub 32, y))
1577 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
1578 if (SUBC->getValue() == OpSizeInBits) {
1580 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1582 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1585 } else if (LExtOp0.getOpcode() == ISD::SUB &&
1586 RExtOp0 == LExtOp0.getOperand(1)) {
1587 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
1589 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
1590 // (rotr x, (sub 32, y))
1591 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
1592 if (SUBC->getValue() == OpSizeInBits) {
1594 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
1596 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1606 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1607 SDOperand N0 = N->getOperand(0);
1608 SDOperand N1 = N->getOperand(1);
1609 SDOperand LHS, RHS, CC;
1610 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1611 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1612 MVT::ValueType VT = N0.getValueType();
1614 // fold (xor c1, c2) -> c1^c2
1616 return DAG.getNode(ISD::XOR, VT, N0, N1);
1617 // canonicalize constant to RHS
1619 return DAG.getNode(ISD::XOR, VT, N1, N0);
1620 // fold (xor x, 0) -> x
1621 if (N1C && N1C->isNullValue())
1624 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1627 // fold !(x cc y) -> (x !cc y)
1628 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1629 bool isInt = MVT::isInteger(LHS.getValueType());
1630 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1632 if (N0.getOpcode() == ISD::SETCC)
1633 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1634 if (N0.getOpcode() == ISD::SELECT_CC)
1635 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1636 assert(0 && "Unhandled SetCC Equivalent!");
1639 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1640 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
1641 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1642 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1643 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1644 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1645 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1646 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1647 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1648 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1651 // fold !(x or y) -> (!x and !y) iff x or y are constants
1652 if (N1C && N1C->isAllOnesValue() &&
1653 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1654 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1655 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1656 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1657 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1658 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1659 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1660 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1663 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1664 if (N1C && N0.getOpcode() == ISD::XOR) {
1665 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1666 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1668 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1669 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1671 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1672 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1674 // fold (xor x, x) -> 0
1676 if (!MVT::isVector(VT)) {
1677 return DAG.getConstant(0, VT);
1678 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1679 // Produce a vector of zeros.
1680 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1681 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1682 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1686 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1687 if (N0.getOpcode() == N1.getOpcode()) {
1688 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1689 if (Tmp.Val) return Tmp;
1692 // Simplify the expression using non-local knowledge.
1693 if (!MVT::isVector(VT) &&
1694 SimplifyDemandedBits(SDOperand(N, 0)))
1695 return SDOperand(N, 0);
1700 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1701 SDOperand N0 = N->getOperand(0);
1702 SDOperand N1 = N->getOperand(1);
1703 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1704 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1705 MVT::ValueType VT = N0.getValueType();
1706 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1708 // fold (shl c1, c2) -> c1<<c2
1710 return DAG.getNode(ISD::SHL, VT, N0, N1);
1711 // fold (shl 0, x) -> 0
1712 if (N0C && N0C->isNullValue())
1714 // fold (shl x, c >= size(x)) -> undef
1715 if (N1C && N1C->getValue() >= OpSizeInBits)
1716 return DAG.getNode(ISD::UNDEF, VT);
1717 // fold (shl x, 0) -> x
1718 if (N1C && N1C->isNullValue())
1720 // if (shl x, c) is known to be zero, return 0
1721 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1722 return DAG.getConstant(0, VT);
1723 if (SimplifyDemandedBits(SDOperand(N, 0)))
1724 return SDOperand(N, 0);
1725 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1726 if (N1C && N0.getOpcode() == ISD::SHL &&
1727 N0.getOperand(1).getOpcode() == ISD::Constant) {
1728 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1729 uint64_t c2 = N1C->getValue();
1730 if (c1 + c2 > OpSizeInBits)
1731 return DAG.getConstant(0, VT);
1732 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1733 DAG.getConstant(c1 + c2, N1.getValueType()));
1735 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1736 // (srl (and x, -1 << c1), c1-c2)
1737 if (N1C && N0.getOpcode() == ISD::SRL &&
1738 N0.getOperand(1).getOpcode() == ISD::Constant) {
1739 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1740 uint64_t c2 = N1C->getValue();
1741 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1742 DAG.getConstant(~0ULL << c1, VT));
1744 return DAG.getNode(ISD::SHL, VT, Mask,
1745 DAG.getConstant(c2-c1, N1.getValueType()));
1747 return DAG.getNode(ISD::SRL, VT, Mask,
1748 DAG.getConstant(c1-c2, N1.getValueType()));
1750 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1751 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1752 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1753 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1757 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1758 SDOperand N0 = N->getOperand(0);
1759 SDOperand N1 = N->getOperand(1);
1760 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1761 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1762 MVT::ValueType VT = N0.getValueType();
1764 // fold (sra c1, c2) -> c1>>c2
1766 return DAG.getNode(ISD::SRA, VT, N0, N1);
1767 // fold (sra 0, x) -> 0
1768 if (N0C && N0C->isNullValue())
1770 // fold (sra -1, x) -> -1
1771 if (N0C && N0C->isAllOnesValue())
1773 // fold (sra x, c >= size(x)) -> undef
1774 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1775 return DAG.getNode(ISD::UNDEF, VT);
1776 // fold (sra x, 0) -> x
1777 if (N1C && N1C->isNullValue())
1779 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1781 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1782 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1785 default: EVT = MVT::Other; break;
1786 case 1: EVT = MVT::i1; break;
1787 case 8: EVT = MVT::i8; break;
1788 case 16: EVT = MVT::i16; break;
1789 case 32: EVT = MVT::i32; break;
1791 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1792 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1793 DAG.getValueType(EVT));
1796 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1797 if (N1C && N0.getOpcode() == ISD::SRA) {
1798 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1799 unsigned Sum = N1C->getValue() + C1->getValue();
1800 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1801 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1802 DAG.getConstant(Sum, N1C->getValueType(0)));
1806 // Simplify, based on bits shifted out of the LHS.
1807 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1808 return SDOperand(N, 0);
1811 // If the sign bit is known to be zero, switch this to a SRL.
1812 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1813 return DAG.getNode(ISD::SRL, VT, N0, N1);
1817 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1818 SDOperand N0 = N->getOperand(0);
1819 SDOperand N1 = N->getOperand(1);
1820 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1821 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1822 MVT::ValueType VT = N0.getValueType();
1823 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1825 // fold (srl c1, c2) -> c1 >>u c2
1827 return DAG.getNode(ISD::SRL, VT, N0, N1);
1828 // fold (srl 0, x) -> 0
1829 if (N0C && N0C->isNullValue())
1831 // fold (srl x, c >= size(x)) -> undef
1832 if (N1C && N1C->getValue() >= OpSizeInBits)
1833 return DAG.getNode(ISD::UNDEF, VT);
1834 // fold (srl x, 0) -> x
1835 if (N1C && N1C->isNullValue())
1837 // if (srl x, c) is known to be zero, return 0
1838 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1839 return DAG.getConstant(0, VT);
1840 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1841 if (N1C && N0.getOpcode() == ISD::SRL &&
1842 N0.getOperand(1).getOpcode() == ISD::Constant) {
1843 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1844 uint64_t c2 = N1C->getValue();
1845 if (c1 + c2 > OpSizeInBits)
1846 return DAG.getConstant(0, VT);
1847 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1848 DAG.getConstant(c1 + c2, N1.getValueType()));
1851 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1852 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1853 // Shifting in all undef bits?
1854 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1855 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1856 return DAG.getNode(ISD::UNDEF, VT);
1858 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1859 AddToWorkList(SmallShift.Val);
1860 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1863 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
1864 // bit, which is unmodified by sra.
1865 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
1866 if (N0.getOpcode() == ISD::SRA)
1867 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
1870 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1871 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1872 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1873 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1874 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1876 // If any of the input bits are KnownOne, then the input couldn't be all
1877 // zeros, thus the result of the srl will always be zero.
1878 if (KnownOne) return DAG.getConstant(0, VT);
1880 // If all of the bits input the to ctlz node are known to be zero, then
1881 // the result of the ctlz is "32" and the result of the shift is one.
1882 uint64_t UnknownBits = ~KnownZero & Mask;
1883 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1885 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1886 if ((UnknownBits & (UnknownBits-1)) == 0) {
1887 // Okay, we know that only that the single bit specified by UnknownBits
1888 // could be set on input to the CTLZ node. If this bit is set, the SRL
1889 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1890 // to an SRL,XOR pair, which is likely to simplify more.
1891 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1892 SDOperand Op = N0.getOperand(0);
1894 Op = DAG.getNode(ISD::SRL, VT, Op,
1895 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1896 AddToWorkList(Op.Val);
1898 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1905 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1906 SDOperand N0 = N->getOperand(0);
1907 MVT::ValueType VT = N->getValueType(0);
1909 // fold (ctlz c1) -> c2
1910 if (isa<ConstantSDNode>(N0))
1911 return DAG.getNode(ISD::CTLZ, VT, N0);
1915 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1916 SDOperand N0 = N->getOperand(0);
1917 MVT::ValueType VT = N->getValueType(0);
1919 // fold (cttz c1) -> c2
1920 if (isa<ConstantSDNode>(N0))
1921 return DAG.getNode(ISD::CTTZ, VT, N0);
1925 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1926 SDOperand N0 = N->getOperand(0);
1927 MVT::ValueType VT = N->getValueType(0);
1929 // fold (ctpop c1) -> c2
1930 if (isa<ConstantSDNode>(N0))
1931 return DAG.getNode(ISD::CTPOP, VT, N0);
1935 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1936 SDOperand N0 = N->getOperand(0);
1937 SDOperand N1 = N->getOperand(1);
1938 SDOperand N2 = N->getOperand(2);
1939 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1940 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1941 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1942 MVT::ValueType VT = N->getValueType(0);
1944 // fold select C, X, X -> X
1947 // fold select true, X, Y -> X
1948 if (N0C && !N0C->isNullValue())
1950 // fold select false, X, Y -> Y
1951 if (N0C && N0C->isNullValue())
1953 // fold select C, 1, X -> C | X
1954 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1955 return DAG.getNode(ISD::OR, VT, N0, N2);
1956 // fold select C, 0, X -> ~C & X
1957 // FIXME: this should check for C type == X type, not i1?
1958 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1959 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1960 AddToWorkList(XORNode.Val);
1961 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1963 // fold select C, X, 1 -> ~C | X
1964 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1965 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1966 AddToWorkList(XORNode.Val);
1967 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1969 // fold select C, X, 0 -> C & X
1970 // FIXME: this should check for C type == X type, not i1?
1971 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1972 return DAG.getNode(ISD::AND, VT, N0, N1);
1973 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1974 if (MVT::i1 == VT && N0 == N1)
1975 return DAG.getNode(ISD::OR, VT, N0, N2);
1976 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1977 if (MVT::i1 == VT && N0 == N2)
1978 return DAG.getNode(ISD::AND, VT, N0, N1);
1980 // If we can fold this based on the true/false value, do so.
1981 if (SimplifySelectOps(N, N1, N2))
1982 return SDOperand(N, 0); // Don't revisit N.
1984 // fold selects based on a setcc into other things, such as min/max/abs
1985 if (N0.getOpcode() == ISD::SETCC)
1987 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1988 // having to say they don't support SELECT_CC on every type the DAG knows
1989 // about, since there is no way to mark an opcode illegal at all value types
1990 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1991 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1992 N1, N2, N0.getOperand(2));
1994 return SimplifySelect(N0, N1, N2);
1998 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1999 SDOperand N0 = N->getOperand(0);
2000 SDOperand N1 = N->getOperand(1);
2001 SDOperand N2 = N->getOperand(2);
2002 SDOperand N3 = N->getOperand(3);
2003 SDOperand N4 = N->getOperand(4);
2004 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2006 // fold select_cc lhs, rhs, x, x, cc -> x
2010 // Determine if the condition we're dealing with is constant
2011 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2012 if (SCC.Val) AddToWorkList(SCC.Val);
2014 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
2015 if (SCCC->getValue())
2016 return N2; // cond always true -> true val
2018 return N3; // cond always false -> false val
2021 // Fold to a simpler select_cc
2022 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2023 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
2024 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2027 // If we can fold this based on the true/false value, do so.
2028 if (SimplifySelectOps(N, N2, N3))
2029 return SDOperand(N, 0); // Don't revisit N.
2031 // fold select_cc into other things, such as min/max/abs
2032 return SimplifySelectCC(N0, N1, N2, N3, CC);
2035 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
2036 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2037 cast<CondCodeSDNode>(N->getOperand(2))->get());
2040 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2041 SDOperand N0 = N->getOperand(0);
2042 MVT::ValueType VT = N->getValueType(0);
2044 // fold (sext c1) -> c1
2045 if (isa<ConstantSDNode>(N0))
2046 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2048 // fold (sext (sext x)) -> (sext x)
2049 // fold (sext (aext x)) -> (sext x)
2050 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2051 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2053 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2054 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2055 if (N0.getOpcode() == ISD::TRUNCATE) {
2056 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2057 if (NarrowLoad.Val) {
2058 if (NarrowLoad.Val != N0.Val)
2059 CombineTo(N0.Val, NarrowLoad);
2060 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
2064 // See if the value being truncated is already sign extended. If so, just
2065 // eliminate the trunc/sext pair.
2066 if (N0.getOpcode() == ISD::TRUNCATE) {
2067 SDOperand Op = N0.getOperand(0);
2068 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2069 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2070 unsigned DestBits = MVT::getSizeInBits(VT);
2071 unsigned NumSignBits = TLI.ComputeNumSignBits(Op);
2073 if (OpBits == DestBits) {
2074 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2075 // bits, it is already ready.
2076 if (NumSignBits > DestBits-MidBits)
2078 } else if (OpBits < DestBits) {
2079 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2080 // bits, just sext from i32.
2081 if (NumSignBits > OpBits-MidBits)
2082 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2084 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2085 // bits, just truncate to i32.
2086 if (NumSignBits > OpBits-MidBits)
2087 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2090 // fold (sext (truncate x)) -> (sextinreg x).
2091 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2092 N0.getValueType())) {
2093 if (Op.getValueType() < VT)
2094 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2095 else if (Op.getValueType() > VT)
2096 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2097 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2098 DAG.getValueType(N0.getValueType()));
2102 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2103 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2104 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2105 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2106 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2107 LN0->getBasePtr(), LN0->getSrcValue(),
2108 LN0->getSrcValueOffset(),
2110 CombineTo(N, ExtLoad);
2111 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2112 ExtLoad.getValue(1));
2113 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2116 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2117 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2118 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2119 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2120 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2121 MVT::ValueType EVT = LN0->getLoadedVT();
2122 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2123 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2124 LN0->getBasePtr(), LN0->getSrcValue(),
2125 LN0->getSrcValueOffset(), EVT);
2126 CombineTo(N, ExtLoad);
2127 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2128 ExtLoad.getValue(1));
2129 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2133 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
2134 if (N0.getOpcode() == ISD::SETCC) {
2136 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2137 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
2138 cast<CondCodeSDNode>(N0.getOperand(2))->get());
2139 if (SCC.Val) return SCC;
2145 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2146 SDOperand N0 = N->getOperand(0);
2147 MVT::ValueType VT = N->getValueType(0);
2149 // fold (zext c1) -> c1
2150 if (isa<ConstantSDNode>(N0))
2151 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2152 // fold (zext (zext x)) -> (zext x)
2153 // fold (zext (aext x)) -> (zext x)
2154 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2155 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2157 // fold (zext (truncate (load x))) -> (zext (smaller load x))
2158 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
2159 if (N0.getOpcode() == ISD::TRUNCATE) {
2160 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2161 if (NarrowLoad.Val) {
2162 if (NarrowLoad.Val != N0.Val)
2163 CombineTo(N0.Val, NarrowLoad);
2164 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
2168 // fold (zext (truncate x)) -> (and x, mask)
2169 if (N0.getOpcode() == ISD::TRUNCATE &&
2170 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2171 SDOperand Op = N0.getOperand(0);
2172 if (Op.getValueType() < VT) {
2173 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2174 } else if (Op.getValueType() > VT) {
2175 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2177 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2180 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2181 if (N0.getOpcode() == ISD::AND &&
2182 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2183 N0.getOperand(1).getOpcode() == ISD::Constant) {
2184 SDOperand X = N0.getOperand(0).getOperand(0);
2185 if (X.getValueType() < VT) {
2186 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2187 } else if (X.getValueType() > VT) {
2188 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2190 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2191 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2194 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2195 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2196 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2197 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2198 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2199 LN0->getBasePtr(), LN0->getSrcValue(),
2200 LN0->getSrcValueOffset(),
2202 CombineTo(N, ExtLoad);
2203 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2204 ExtLoad.getValue(1));
2205 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2208 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2209 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2210 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2211 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2212 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2213 MVT::ValueType EVT = LN0->getLoadedVT();
2214 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2215 LN0->getBasePtr(), LN0->getSrcValue(),
2216 LN0->getSrcValueOffset(), EVT);
2217 CombineTo(N, ExtLoad);
2218 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2219 ExtLoad.getValue(1));
2220 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2223 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2224 if (N0.getOpcode() == ISD::SETCC) {
2226 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2227 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2228 cast<CondCodeSDNode>(N0.getOperand(2))->get());
2229 if (SCC.Val) return SCC;
2235 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2236 SDOperand N0 = N->getOperand(0);
2237 MVT::ValueType VT = N->getValueType(0);
2239 // fold (aext c1) -> c1
2240 if (isa<ConstantSDNode>(N0))
2241 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2242 // fold (aext (aext x)) -> (aext x)
2243 // fold (aext (zext x)) -> (zext x)
2244 // fold (aext (sext x)) -> (sext x)
2245 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2246 N0.getOpcode() == ISD::ZERO_EXTEND ||
2247 N0.getOpcode() == ISD::SIGN_EXTEND)
2248 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2250 // fold (aext (truncate (load x))) -> (aext (smaller load x))
2251 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
2252 if (N0.getOpcode() == ISD::TRUNCATE) {
2253 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2254 if (NarrowLoad.Val) {
2255 if (NarrowLoad.Val != N0.Val)
2256 CombineTo(N0.Val, NarrowLoad);
2257 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
2261 // fold (aext (truncate x))
2262 if (N0.getOpcode() == ISD::TRUNCATE) {
2263 SDOperand TruncOp = N0.getOperand(0);
2264 if (TruncOp.getValueType() == VT)
2265 return TruncOp; // x iff x size == zext size.
2266 if (TruncOp.getValueType() > VT)
2267 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2268 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2271 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2272 if (N0.getOpcode() == ISD::AND &&
2273 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2274 N0.getOperand(1).getOpcode() == ISD::Constant) {
2275 SDOperand X = N0.getOperand(0).getOperand(0);
2276 if (X.getValueType() < VT) {
2277 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2278 } else if (X.getValueType() > VT) {
2279 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2281 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2282 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2285 // fold (aext (load x)) -> (aext (truncate (extload x)))
2286 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2287 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2288 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2289 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2290 LN0->getBasePtr(), LN0->getSrcValue(),
2291 LN0->getSrcValueOffset(),
2293 CombineTo(N, ExtLoad);
2294 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2295 ExtLoad.getValue(1));
2296 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2299 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2300 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2301 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2302 if (N0.getOpcode() == ISD::LOAD &&
2303 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2305 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2306 MVT::ValueType EVT = LN0->getLoadedVT();
2307 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2308 LN0->getChain(), LN0->getBasePtr(),
2310 LN0->getSrcValueOffset(), EVT);
2311 CombineTo(N, ExtLoad);
2312 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2313 ExtLoad.getValue(1));
2314 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2317 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2318 if (N0.getOpcode() == ISD::SETCC) {
2320 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2321 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2322 cast<CondCodeSDNode>(N0.getOperand(2))->get());
2323 if (SCC.Val) return SCC;
2329 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
2330 /// bits and then truncated to a narrower type and where N is a multiple
2331 /// of number of bits of the narrower type, transform it to a narrower load
2332 /// from address + N / num of bits of new type. If the result is to be
2333 /// extended, also fold the extension to form a extending load.
2334 SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
2335 unsigned Opc = N->getOpcode();
2336 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2337 SDOperand N0 = N->getOperand(0);
2338 MVT::ValueType VT = N->getValueType(0);
2339 MVT::ValueType EVT = N->getValueType(0);
2341 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
2343 if (Opc == ISD::SIGN_EXTEND_INREG) {
2344 ExtType = ISD::SEXTLOAD;
2345 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2346 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
2350 unsigned EVTBits = MVT::getSizeInBits(EVT);
2352 bool CombineSRL = false;
2353 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
2354 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2355 ShAmt = N01->getValue();
2356 // Is the shift amount a multiple of size of VT?
2357 if ((ShAmt & (EVTBits-1)) == 0) {
2358 N0 = N0.getOperand(0);
2359 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
2366 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2367 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
2368 // zero extended form: by shrinking the load, we lose track of the fact
2369 // that it is already zero extended.
2370 // FIXME: This should be reevaluated.
2372 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
2373 "Cannot truncate to larger type!");
2374 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2375 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2376 // For big endian targets, we need to adjust the offset to the pointer to
2377 // load the correct bytes.
2378 if (!TLI.isLittleEndian())
2379 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits;
2380 uint64_t PtrOff = ShAmt / 8;
2381 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2382 DAG.getConstant(PtrOff, PtrType));
2383 AddToWorkList(NewPtr.Val);
2384 SDOperand Load = (ExtType == ISD::NON_EXTLOAD)
2385 ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
2386 LN0->getSrcValue(), LN0->getSrcValueOffset())
2387 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
2388 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
2391 std::vector<SDNode*> NowDead;
2392 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead);
2393 CombineTo(N->getOperand(0).Val, Load);
2395 CombineTo(N0.Val, Load, Load.getValue(1));
2397 if (Opc == ISD::SIGN_EXTEND_INREG)
2398 return DAG.getNode(Opc, VT, Load, N->getOperand(1));
2400 return DAG.getNode(Opc, VT, Load);
2402 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2409 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2410 SDOperand N0 = N->getOperand(0);
2411 SDOperand N1 = N->getOperand(1);
2412 MVT::ValueType VT = N->getValueType(0);
2413 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2414 unsigned EVTBits = MVT::getSizeInBits(EVT);
2416 // fold (sext_in_reg c1) -> c1
2417 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2418 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2420 // If the input is already sign extended, just drop the extension.
2421 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2424 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2425 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2426 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2427 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2430 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
2431 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2432 return DAG.getZeroExtendInReg(N0, EVT);
2434 // fold (sext_in_reg (load x)) -> (smaller sextload x)
2435 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
2436 SDOperand NarrowLoad = ReduceLoadWidth(N);
2440 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2441 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2442 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2443 if (N0.getOpcode() == ISD::SRL) {
2444 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2445 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2446 // We can turn this into an SRA iff the input to the SRL is already sign
2448 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
2449 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2450 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2454 // fold (sext_inreg (extload x)) -> (sextload x)
2455 if (ISD::isEXTLoad(N0.Val) &&
2456 ISD::isUNINDEXEDLoad(N0.Val) &&
2457 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2458 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2459 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2460 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2461 LN0->getBasePtr(), LN0->getSrcValue(),
2462 LN0->getSrcValueOffset(), EVT);
2463 CombineTo(N, ExtLoad);
2464 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2465 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2467 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2468 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2470 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2471 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2472 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2473 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2474 LN0->getBasePtr(), LN0->getSrcValue(),
2475 LN0->getSrcValueOffset(), EVT);
2476 CombineTo(N, ExtLoad);
2477 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2478 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2483 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2484 SDOperand N0 = N->getOperand(0);
2485 MVT::ValueType VT = N->getValueType(0);
2488 if (N0.getValueType() == N->getValueType(0))
2490 // fold (truncate c1) -> c1
2491 if (isa<ConstantSDNode>(N0))
2492 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2493 // fold (truncate (truncate x)) -> (truncate x)
2494 if (N0.getOpcode() == ISD::TRUNCATE)
2495 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2496 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2497 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2498 N0.getOpcode() == ISD::ANY_EXTEND) {
2499 if (N0.getOperand(0).getValueType() < VT)
2500 // if the source is smaller than the dest, we still need an extend
2501 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2502 else if (N0.getOperand(0).getValueType() > VT)
2503 // if the source is larger than the dest, than we just need the truncate
2504 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2506 // if the source and dest are the same type, we can drop both the extend
2508 return N0.getOperand(0);
2511 // fold (truncate (load x)) -> (smaller load x)
2512 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
2513 return ReduceLoadWidth(N);
2516 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2517 SDOperand N0 = N->getOperand(0);
2518 MVT::ValueType VT = N->getValueType(0);
2520 // If the input is a constant, let getNode() fold it.
2521 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2522 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2523 if (Res.Val != N) return Res;
2526 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2527 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2529 // fold (conv (load x)) -> (load (conv*)x)
2530 // FIXME: These xforms need to know that the resultant load doesn't need a
2531 // higher alignment than the original!
2532 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2533 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2534 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2535 LN0->getSrcValue(), LN0->getSrcValueOffset());
2537 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2545 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2546 SDOperand N0 = N->getOperand(0);
2547 MVT::ValueType VT = N->getValueType(0);
2549 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2550 // First check to see if this is all constant.
2551 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2552 VT == MVT::Vector) {
2553 bool isSimple = true;
2554 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2555 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2556 N0.getOperand(i).getOpcode() != ISD::Constant &&
2557 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2562 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2563 if (isSimple && !MVT::isVector(DestEltVT)) {
2564 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2571 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2572 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2573 /// destination element value type.
2574 SDOperand DAGCombiner::
2575 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2576 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2578 // If this is already the right type, we're done.
2579 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2581 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2582 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2584 // If this is a conversion of N elements of one type to N elements of another
2585 // type, convert each element. This handles FP<->INT cases.
2586 if (SrcBitSize == DstBitSize) {
2587 SmallVector<SDOperand, 8> Ops;
2588 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2589 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2590 AddToWorkList(Ops.back().Val);
2592 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2593 Ops.push_back(DAG.getValueType(DstEltVT));
2594 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2597 // Otherwise, we're growing or shrinking the elements. To avoid having to
2598 // handle annoying details of growing/shrinking FP values, we convert them to
2600 if (MVT::isFloatingPoint(SrcEltVT)) {
2601 // Convert the input float vector to a int vector where the elements are the
2603 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2604 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2605 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2609 // Now we know the input is an integer vector. If the output is a FP type,
2610 // convert to integer first, then to FP of the right size.
2611 if (MVT::isFloatingPoint(DstEltVT)) {
2612 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2613 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2614 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2616 // Next, convert to FP elements of the same size.
2617 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2620 // Okay, we know the src/dst types are both integers of differing types.
2621 // Handling growing first.
2622 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2623 if (SrcBitSize < DstBitSize) {
2624 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2626 SmallVector<SDOperand, 8> Ops;
2627 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2628 i += NumInputsPerOutput) {
2629 bool isLE = TLI.isLittleEndian();
2630 uint64_t NewBits = 0;
2631 bool EltIsUndef = true;
2632 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2633 // Shift the previously computed bits over.
2634 NewBits <<= SrcBitSize;
2635 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2636 if (Op.getOpcode() == ISD::UNDEF) continue;
2639 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2643 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2645 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2648 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2649 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2650 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2653 // Finally, this must be the case where we are shrinking elements: each input
2654 // turns into multiple outputs.
2655 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2656 SmallVector<SDOperand, 8> Ops;
2657 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2658 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2659 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2660 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2663 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2665 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2666 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2667 OpVal >>= DstBitSize;
2668 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2671 // For big endian targets, swap the order of the pieces of each element.
2672 if (!TLI.isLittleEndian())
2673 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2675 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2676 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2677 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2682 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2683 SDOperand N0 = N->getOperand(0);
2684 SDOperand N1 = N->getOperand(1);
2685 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2686 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2687 MVT::ValueType VT = N->getValueType(0);
2689 // fold (fadd c1, c2) -> c1+c2
2691 return DAG.getNode(ISD::FADD, VT, N0, N1);
2692 // canonicalize constant to RHS
2693 if (N0CFP && !N1CFP)
2694 return DAG.getNode(ISD::FADD, VT, N1, N0);
2695 // fold (A + (-B)) -> A-B
2696 if (N1.getOpcode() == ISD::FNEG)
2697 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2698 // fold ((-A) + B) -> B-A
2699 if (N0.getOpcode() == ISD::FNEG)
2700 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2702 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
2703 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
2704 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
2705 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
2706 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
2711 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2712 SDOperand N0 = N->getOperand(0);
2713 SDOperand N1 = N->getOperand(1);
2714 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2715 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2716 MVT::ValueType VT = N->getValueType(0);
2718 // fold (fsub c1, c2) -> c1-c2
2720 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2721 // fold (A-(-B)) -> A+B
2722 if (N1.getOpcode() == ISD::FNEG)
2723 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2727 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2728 SDOperand N0 = N->getOperand(0);
2729 SDOperand N1 = N->getOperand(1);
2730 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2731 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2732 MVT::ValueType VT = N->getValueType(0);
2734 // fold (fmul c1, c2) -> c1*c2
2736 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2737 // canonicalize constant to RHS
2738 if (N0CFP && !N1CFP)
2739 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2740 // fold (fmul X, 2.0) -> (fadd X, X)
2741 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2742 return DAG.getNode(ISD::FADD, VT, N0, N0);
2744 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
2745 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
2746 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
2747 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
2748 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
2753 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2754 SDOperand N0 = N->getOperand(0);
2755 SDOperand N1 = N->getOperand(1);
2756 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2757 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2758 MVT::ValueType VT = N->getValueType(0);
2760 // fold (fdiv c1, c2) -> c1/c2
2762 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2766 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2767 SDOperand N0 = N->getOperand(0);
2768 SDOperand N1 = N->getOperand(1);
2769 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2770 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2771 MVT::ValueType VT = N->getValueType(0);
2773 // fold (frem c1, c2) -> fmod(c1,c2)
2775 return DAG.getNode(ISD::FREM, VT, N0, N1);
2779 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2780 SDOperand N0 = N->getOperand(0);
2781 SDOperand N1 = N->getOperand(1);
2782 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2783 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2784 MVT::ValueType VT = N->getValueType(0);
2786 if (N0CFP && N1CFP) // Constant fold
2787 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2790 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2791 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2796 u.d = N1CFP->getValue();
2798 return DAG.getNode(ISD::FABS, VT, N0);
2800 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2803 // copysign(fabs(x), y) -> copysign(x, y)
2804 // copysign(fneg(x), y) -> copysign(x, y)
2805 // copysign(copysign(x,z), y) -> copysign(x, y)
2806 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2807 N0.getOpcode() == ISD::FCOPYSIGN)
2808 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2810 // copysign(x, abs(y)) -> abs(x)
2811 if (N1.getOpcode() == ISD::FABS)
2812 return DAG.getNode(ISD::FABS, VT, N0);
2814 // copysign(x, copysign(y,z)) -> copysign(x, z)
2815 if (N1.getOpcode() == ISD::FCOPYSIGN)
2816 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2818 // copysign(x, fp_extend(y)) -> copysign(x, y)
2819 // copysign(x, fp_round(y)) -> copysign(x, y)
2820 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2821 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2828 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2829 SDOperand N0 = N->getOperand(0);
2830 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2831 MVT::ValueType VT = N->getValueType(0);
2833 // fold (sint_to_fp c1) -> c1fp
2835 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2839 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2840 SDOperand N0 = N->getOperand(0);
2841 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2842 MVT::ValueType VT = N->getValueType(0);
2844 // fold (uint_to_fp c1) -> c1fp
2846 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2850 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2851 SDOperand N0 = N->getOperand(0);
2852 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2853 MVT::ValueType VT = N->getValueType(0);
2855 // fold (fp_to_sint c1fp) -> c1
2857 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2861 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2862 SDOperand N0 = N->getOperand(0);
2863 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2864 MVT::ValueType VT = N->getValueType(0);
2866 // fold (fp_to_uint c1fp) -> c1
2868 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2872 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2873 SDOperand N0 = N->getOperand(0);
2874 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2875 MVT::ValueType VT = N->getValueType(0);
2877 // fold (fp_round c1fp) -> c1fp
2879 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2881 // fold (fp_round (fp_extend x)) -> x
2882 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2883 return N0.getOperand(0);
2885 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2886 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2887 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2888 AddToWorkList(Tmp.Val);
2889 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2895 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2896 SDOperand N0 = N->getOperand(0);
2897 MVT::ValueType VT = N->getValueType(0);
2898 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2899 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2901 // fold (fp_round_inreg c1fp) -> c1fp
2903 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2904 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2909 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2910 SDOperand N0 = N->getOperand(0);
2911 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2912 MVT::ValueType VT = N->getValueType(0);
2914 // fold (fp_extend c1fp) -> c1fp
2916 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2918 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2919 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2920 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2921 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2922 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2923 LN0->getBasePtr(), LN0->getSrcValue(),
2924 LN0->getSrcValueOffset(),
2926 CombineTo(N, ExtLoad);
2927 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2928 ExtLoad.getValue(1));
2929 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2936 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2937 SDOperand N0 = N->getOperand(0);
2938 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2939 MVT::ValueType VT = N->getValueType(0);
2941 // fold (fneg c1) -> -c1
2943 return DAG.getNode(ISD::FNEG, VT, N0);
2944 // fold (fneg (sub x, y)) -> (sub y, x)
2945 if (N0.getOpcode() == ISD::SUB)
2946 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2947 // fold (fneg (fneg x)) -> x
2948 if (N0.getOpcode() == ISD::FNEG)
2949 return N0.getOperand(0);
2953 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2954 SDOperand N0 = N->getOperand(0);
2955 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2956 MVT::ValueType VT = N->getValueType(0);
2958 // fold (fabs c1) -> fabs(c1)
2960 return DAG.getNode(ISD::FABS, VT, N0);
2961 // fold (fabs (fabs x)) -> (fabs x)
2962 if (N0.getOpcode() == ISD::FABS)
2963 return N->getOperand(0);
2964 // fold (fabs (fneg x)) -> (fabs x)
2965 // fold (fabs (fcopysign x, y)) -> (fabs x)
2966 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2967 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2972 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2973 SDOperand Chain = N->getOperand(0);
2974 SDOperand N1 = N->getOperand(1);
2975 SDOperand N2 = N->getOperand(2);
2976 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2978 // never taken branch, fold to chain
2979 if (N1C && N1C->isNullValue())
2981 // unconditional branch
2982 if (N1C && N1C->getValue() == 1)
2983 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2984 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2986 if (N1.getOpcode() == ISD::SETCC &&
2987 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2988 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2989 N1.getOperand(0), N1.getOperand(1), N2);
2994 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2996 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2997 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2998 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
3000 // Use SimplifySetCC to simplify SETCC's.
3001 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
3002 if (Simp.Val) AddToWorkList(Simp.Val);
3004 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
3006 // fold br_cc true, dest -> br dest (unconditional branch)
3007 if (SCCC && SCCC->getValue())
3008 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
3010 // fold br_cc false, dest -> unconditional fall through
3011 if (SCCC && SCCC->isNullValue())
3012 return N->getOperand(0);
3014 // fold to a simpler setcc
3015 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
3016 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
3017 Simp.getOperand(2), Simp.getOperand(0),
3018 Simp.getOperand(1), N->getOperand(4));
3023 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
3024 /// pre-indexed load / store when the base pointer is a add or subtract
3025 /// and it has other uses besides the load / store. After the
3026 /// transformation, the new indexed load / store has effectively folded
3027 /// the add / subtract in and all of its other uses are redirected to the
3028 /// new load / store.
3029 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
3036 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3037 if (LD->getAddressingMode() != ISD::UNINDEXED)
3039 VT = LD->getLoadedVT();
3040 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
3041 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
3043 Ptr = LD->getBasePtr();
3044 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3045 if (ST->getAddressingMode() != ISD::UNINDEXED)
3047 VT = ST->getStoredVT();
3048 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
3049 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
3051 Ptr = ST->getBasePtr();
3056 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
3057 // out. There is no reason to make this a preinc/predec.
3058 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
3059 Ptr.Val->hasOneUse())
3062 // Ask the target to do addressing mode selection.
3065 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3066 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
3069 // Try turning it into a pre-indexed load / store except when:
3070 // 1) The base is a frame index.
3071 // 2) If N is a store and the ptr is either the same as or is a
3072 // predecessor of the value being stored.
3073 // 3) Another use of base ptr is a predecessor of N. If ptr is folded
3074 // that would create a cycle.
3075 // 4) All uses are load / store ops that use it as base ptr.
3077 // Check #1. Preinc'ing a frame index would require copying the stack pointer
3078 // (plus the implicit offset) to a register to preinc anyway.
3079 if (isa<FrameIndexSDNode>(BasePtr))
3084 SDOperand Val = cast<StoreSDNode>(N)->getValue();
3085 if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val))
3089 // Now check for #2 and #3.
3090 bool RealUse = false;
3091 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3092 E = Ptr.Val->use_end(); I != E; ++I) {
3096 if (Use->isPredecessor(N))
3099 if (!((Use->getOpcode() == ISD::LOAD &&
3100 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
3101 (Use->getOpcode() == ISD::STORE) &&
3102 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
3110 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
3112 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3115 DOUT << "\nReplacing.4 "; DEBUG(N->dump());
3116 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3118 std::vector<SDNode*> NowDead;
3120 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3122 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3125 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3129 // Nodes can end up on the worklist more than once. Make sure we do
3130 // not process a node that has been replaced.
3131 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3132 removeFromWorkList(NowDead[i]);
3133 // Finally, since the node is now dead, remove it from the graph.
3136 // Replace the uses of Ptr with uses of the updated base value.
3137 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
3139 removeFromWorkList(Ptr.Val);
3140 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3141 removeFromWorkList(NowDead[i]);
3142 DAG.DeleteNode(Ptr.Val);
3147 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
3148 /// add / sub of the base pointer node into a post-indexed load / store.
3149 /// The transformation folded the add / subtract into the new indexed
3150 /// load / store effectively and all of its uses are redirected to the
3151 /// new load / store.
3152 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
3159 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3160 if (LD->getAddressingMode() != ISD::UNINDEXED)
3162 VT = LD->getLoadedVT();
3163 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
3164 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
3166 Ptr = LD->getBasePtr();
3167 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3168 if (ST->getAddressingMode() != ISD::UNINDEXED)
3170 VT = ST->getStoredVT();
3171 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
3172 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
3174 Ptr = ST->getBasePtr();
3179 if (Ptr.Val->hasOneUse())
3182 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3183 E = Ptr.Val->use_end(); I != E; ++I) {
3186 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
3191 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3192 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
3194 std::swap(BasePtr, Offset);
3198 // Try turning it into a post-indexed load / store except when
3199 // 1) All uses are load / store ops that use it as base ptr.
3200 // 2) Op must be independent of N, i.e. Op is neither a predecessor
3201 // nor a successor of N. Otherwise, if Op is folded that would
3205 bool TryNext = false;
3206 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
3207 EE = BasePtr.Val->use_end(); II != EE; ++II) {
3212 // If all the uses are load / store addresses, then don't do the
3214 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
3215 bool RealUse = false;
3216 for (SDNode::use_iterator III = Use->use_begin(),
3217 EEE = Use->use_end(); III != EEE; ++III) {
3218 SDNode *UseUse = *III;
3219 if (!((UseUse->getOpcode() == ISD::LOAD &&
3220 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
3221 (UseUse->getOpcode() == ISD::STORE) &&
3222 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
3236 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
3237 SDOperand Result = isLoad
3238 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
3239 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3242 DOUT << "\nReplacing.5 "; DEBUG(N->dump());
3243 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3245 std::vector<SDNode*> NowDead;
3247 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3249 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3252 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3256 // Nodes can end up on the worklist more than once. Make sure we do
3257 // not process a node that has been replaced.
3258 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3259 removeFromWorkList(NowDead[i]);
3260 // Finally, since the node is now dead, remove it from the graph.
3263 // Replace the uses of Use with uses of the updated base value.
3264 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
3265 Result.getValue(isLoad ? 1 : 0),
3267 removeFromWorkList(Op);
3268 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3269 removeFromWorkList(NowDead[i]);
3280 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
3281 LoadSDNode *LD = cast<LoadSDNode>(N);
3282 SDOperand Chain = LD->getChain();
3283 SDOperand Ptr = LD->getBasePtr();
3285 // If there are no uses of the loaded value, change uses of the chain value
3286 // into uses of the chain input (i.e. delete the dead load).
3287 if (N->hasNUsesOfValue(0, 0))
3288 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
3290 // If this load is directly stored, replace the load value with the stored
3292 // TODO: Handle store large -> read small portion.
3293 // TODO: Handle TRUNCSTORE/LOADEXT
3294 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3295 if (ISD::isNON_TRUNCStore(Chain.Val)) {
3296 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
3297 if (PrevST->getBasePtr() == Ptr &&
3298 PrevST->getValue().getValueType() == N->getValueType(0))
3299 return CombineTo(N, Chain.getOperand(1), Chain);
3304 // Walk up chain skipping non-aliasing memory nodes.
3305 SDOperand BetterChain = FindBetterChain(N, Chain);
3307 // If there is a better chain.
3308 if (Chain != BetterChain) {
3311 // Replace the chain to void dependency.
3312 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3313 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
3314 LD->getSrcValue(), LD->getSrcValueOffset());
3316 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
3317 LD->getValueType(0),
3318 BetterChain, Ptr, LD->getSrcValue(),
3319 LD->getSrcValueOffset(),
3323 // Create token factor to keep old chain connected.
3324 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
3325 Chain, ReplLoad.getValue(1));
3327 // Replace uses with load result and token factor. Don't add users
3329 return CombineTo(N, ReplLoad.getValue(0), Token, false);
3333 // Try transforming N to an indexed load.
3334 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3335 return SDOperand(N, 0);
3340 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
3341 StoreSDNode *ST = cast<StoreSDNode>(N);
3342 SDOperand Chain = ST->getChain();
3343 SDOperand Value = ST->getValue();
3344 SDOperand Ptr = ST->getBasePtr();
3346 // If this is a store of a bit convert, store the input value.
3347 // FIXME: This needs to know that the resultant store does not need a
3348 // higher alignment than the original.
3349 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
3350 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
3351 ST->getSrcValueOffset());
3354 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
3355 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
3356 if (Value.getOpcode() != ISD::TargetConstantFP) {
3358 switch (CFP->getValueType(0)) {
3359 default: assert(0 && "Unknown FP type");
3361 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
3362 Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
3363 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3364 ST->getSrcValueOffset());
3368 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
3369 Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
3370 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3371 ST->getSrcValueOffset());
3372 } else if (TLI.isTypeLegal(MVT::i32)) {
3373 // Many FP stores are not make apparent until after legalize, e.g. for
3374 // argument passing. Since this is so common, custom legalize the
3375 // 64-bit integer store into two 32-bit stores.
3376 uint64_t Val = DoubleToBits(CFP->getValue());
3377 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
3378 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
3379 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
3381 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
3382 ST->getSrcValueOffset());
3383 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3384 DAG.getConstant(4, Ptr.getValueType()));
3385 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
3386 ST->getSrcValueOffset()+4);
3387 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
3395 // Walk up chain skipping non-aliasing memory nodes.
3396 SDOperand BetterChain = FindBetterChain(N, Chain);
3398 // If there is a better chain.
3399 if (Chain != BetterChain) {
3400 // Replace the chain to avoid dependency.
3401 SDOperand ReplStore;
3402 if (ST->isTruncatingStore()) {
3403 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
3404 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT());
3406 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
3407 ST->getSrcValue(), ST->getSrcValueOffset());
3410 // Create token to keep both nodes around.
3412 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
3414 // Don't add users to work list.
3415 return CombineTo(N, Token, false);
3419 // Try transforming N to an indexed store.
3420 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3421 return SDOperand(N, 0);
3426 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
3427 SDOperand InVec = N->getOperand(0);
3428 SDOperand InVal = N->getOperand(1);
3429 SDOperand EltNo = N->getOperand(2);
3431 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
3432 // vector with the inserted element.
3433 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
3434 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3435 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
3436 if (Elt < Ops.size())
3438 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
3439 &Ops[0], Ops.size());
3445 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
3446 SDOperand InVec = N->getOperand(0);
3447 SDOperand InVal = N->getOperand(1);
3448 SDOperand EltNo = N->getOperand(2);
3449 SDOperand NumElts = N->getOperand(3);
3450 SDOperand EltType = N->getOperand(4);
3452 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
3453 // vector with the inserted element.
3454 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
3455 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3456 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
3457 if (Elt < Ops.size()-2)
3459 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
3460 &Ops[0], Ops.size());
3466 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
3467 unsigned NumInScalars = N->getNumOperands()-2;
3468 SDOperand NumElts = N->getOperand(NumInScalars);
3469 SDOperand EltType = N->getOperand(NumInScalars+1);
3471 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
3472 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
3473 // two distinct vectors, turn this into a shuffle node.
3474 SDOperand VecIn1, VecIn2;
3475 for (unsigned i = 0; i != NumInScalars; ++i) {
3476 // Ignore undef inputs.
3477 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3479 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
3480 // constant index, bail out.
3481 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
3482 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
3483 VecIn1 = VecIn2 = SDOperand(0, 0);
3487 // If the input vector type disagrees with the result of the vbuild_vector,
3488 // we can't make a shuffle.
3489 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
3490 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
3491 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
3492 VecIn1 = VecIn2 = SDOperand(0, 0);
3496 // Otherwise, remember this. We allow up to two distinct input vectors.
3497 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
3500 if (VecIn1.Val == 0) {
3501 VecIn1 = ExtractedFromVec;
3502 } else if (VecIn2.Val == 0) {
3503 VecIn2 = ExtractedFromVec;
3506 VecIn1 = VecIn2 = SDOperand(0, 0);
3511 // If everything is good, we can make a shuffle operation.
3513 SmallVector<SDOperand, 8> BuildVecIndices;
3514 for (unsigned i = 0; i != NumInScalars; ++i) {
3515 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
3516 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
3520 SDOperand Extract = N->getOperand(i);
3522 // If extracting from the first vector, just use the index directly.
3523 if (Extract.getOperand(0) == VecIn1) {
3524 BuildVecIndices.push_back(Extract.getOperand(1));
3528 // Otherwise, use InIdx + VecSize
3529 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
3530 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars,
3531 TLI.getPointerTy()));
3534 // Add count and size info.
3535 BuildVecIndices.push_back(NumElts);
3536 BuildVecIndices.push_back(DAG.getValueType(TLI.getPointerTy()));
3538 // Return the new VVECTOR_SHUFFLE node.
3544 // Use an undef vbuild_vector as input for the second operand.
3545 std::vector<SDOperand> UnOps(NumInScalars,
3546 DAG.getNode(ISD::UNDEF,
3547 cast<VTSDNode>(EltType)->getVT()));
3548 UnOps.push_back(NumElts);
3549 UnOps.push_back(EltType);
3550 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3551 &UnOps[0], UnOps.size());
3552 AddToWorkList(Ops[1].Val);
3554 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3555 &BuildVecIndices[0], BuildVecIndices.size());
3558 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
3564 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
3565 SDOperand ShufMask = N->getOperand(2);
3566 unsigned NumElts = ShufMask.getNumOperands();
3568 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3569 bool isIdentity = true;
3570 for (unsigned i = 0; i != NumElts; ++i) {
3571 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3572 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3577 if (isIdentity) return N->getOperand(0);
3579 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3581 for (unsigned i = 0; i != NumElts; ++i) {
3582 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3583 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3588 if (isIdentity) return N->getOperand(1);
3590 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3592 bool isUnary = true;
3593 bool isSplat = true;
3595 unsigned BaseIdx = 0;
3596 for (unsigned i = 0; i != NumElts; ++i)
3597 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3598 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3599 int V = (Idx < NumElts) ? 0 : 1;
3613 SDOperand N0 = N->getOperand(0);
3614 SDOperand N1 = N->getOperand(1);
3615 // Normalize unary shuffle so the RHS is undef.
3616 if (isUnary && VecNum == 1)
3619 // If it is a splat, check if the argument vector is a build_vector with
3620 // all scalar elements the same.
3623 if (V->getOpcode() == ISD::BIT_CONVERT)
3624 V = V->getOperand(0).Val;
3625 if (V->getOpcode() == ISD::BUILD_VECTOR) {
3626 unsigned NumElems = V->getNumOperands()-2;
3627 if (NumElems > BaseIdx) {
3629 bool AllSame = true;
3630 for (unsigned i = 0; i != NumElems; ++i) {
3631 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3632 Base = V->getOperand(i);
3636 // Splat of <u, u, u, u>, return <u, u, u, u>
3639 for (unsigned i = 0; i != NumElems; ++i) {
3640 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3641 V->getOperand(i) != Base) {
3646 // Splat of <x, x, x, x>, return <x, x, x, x>
3653 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3655 if (isUnary || N0 == N1) {
3656 if (N0.getOpcode() == ISD::UNDEF)
3657 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
3658 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3660 SmallVector<SDOperand, 8> MappedOps;
3661 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
3662 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3663 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3664 MappedOps.push_back(ShufMask.getOperand(i));
3667 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3668 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3671 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
3672 &MappedOps[0], MappedOps.size());
3673 AddToWorkList(ShufMask.Val);
3674 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
3676 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
3683 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
3684 SDOperand ShufMask = N->getOperand(2);
3685 unsigned NumElts = ShufMask.getNumOperands()-2;
3687 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3688 bool isIdentity = true;
3689 for (unsigned i = 0; i != NumElts; ++i) {
3690 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3691 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3696 if (isIdentity) return N->getOperand(0);
3698 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3700 for (unsigned i = 0; i != NumElts; ++i) {
3701 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3702 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3707 if (isIdentity) return N->getOperand(1);
3709 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3711 bool isUnary = true;
3712 bool isSplat = true;
3714 unsigned BaseIdx = 0;
3715 for (unsigned i = 0; i != NumElts; ++i)
3716 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3717 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3718 int V = (Idx < NumElts) ? 0 : 1;
3732 SDOperand N0 = N->getOperand(0);
3733 SDOperand N1 = N->getOperand(1);
3734 // Normalize unary shuffle so the RHS is undef.
3735 if (isUnary && VecNum == 1)
3738 // If it is a splat, check if the argument vector is a build_vector with
3739 // all scalar elements the same.
3743 // If this is a vbit convert that changes the element type of the vector but
3744 // not the number of vector elements, look through it. Be careful not to
3745 // look though conversions that change things like v4f32 to v2f64.
3746 if (V->getOpcode() == ISD::VBIT_CONVERT) {
3747 SDOperand ConvInput = V->getOperand(0);
3748 if (ConvInput.getValueType() == MVT::Vector &&
3750 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2))
3754 if (V->getOpcode() == ISD::VBUILD_VECTOR) {
3755 unsigned NumElems = V->getNumOperands()-2;
3756 if (NumElems > BaseIdx) {
3758 bool AllSame = true;
3759 for (unsigned i = 0; i != NumElems; ++i) {
3760 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3761 Base = V->getOperand(i);
3765 // Splat of <u, u, u, u>, return <u, u, u, u>
3768 for (unsigned i = 0; i != NumElems; ++i) {
3769 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3770 V->getOperand(i) != Base) {
3775 // Splat of <x, x, x, x>, return <x, x, x, x>
3782 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3784 if (isUnary || N0 == N1) {
3785 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3787 SmallVector<SDOperand, 8> MappedOps;
3788 for (unsigned i = 0; i != NumElts; ++i) {
3789 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3790 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3791 MappedOps.push_back(ShufMask.getOperand(i));
3794 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3795 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3798 // Add the type/#elts values.
3799 MappedOps.push_back(ShufMask.getOperand(NumElts));
3800 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
3802 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
3803 &MappedOps[0], MappedOps.size());
3804 AddToWorkList(ShufMask.Val);
3806 // Build the undef vector.
3807 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
3808 for (unsigned i = 0; i != NumElts; ++i)
3809 MappedOps[i] = UDVal;
3810 MappedOps[NumElts ] = *(N0.Val->op_end()-2);
3811 MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
3812 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3813 &MappedOps[0], MappedOps.size());
3815 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3816 N0, UDVal, ShufMask,
3817 MappedOps[NumElts], MappedOps[NumElts+1]);
3823 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
3824 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
3825 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
3826 /// vector_shuffle V, Zero, <0, 4, 2, 4>
3827 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
3828 SDOperand LHS = N->getOperand(0);
3829 SDOperand RHS = N->getOperand(1);
3830 if (N->getOpcode() == ISD::VAND) {
3831 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
3832 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
3833 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
3834 RHS = RHS.getOperand(0);
3835 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3836 std::vector<SDOperand> IdxOps;
3837 unsigned NumOps = RHS.getNumOperands();
3838 unsigned NumElts = NumOps-2;
3839 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
3840 for (unsigned i = 0; i != NumElts; ++i) {
3841 SDOperand Elt = RHS.getOperand(i);
3842 if (!isa<ConstantSDNode>(Elt))
3844 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
3845 IdxOps.push_back(DAG.getConstant(i, EVT));
3846 else if (cast<ConstantSDNode>(Elt)->isNullValue())
3847 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
3852 // Let's see if the target supports this vector_shuffle.
3853 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
3856 // Return the new VVECTOR_SHUFFLE node.
3857 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
3858 SDOperand EVTNode = DAG.getValueType(EVT);
3859 std::vector<SDOperand> Ops;
3860 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode,
3863 AddToWorkList(LHS.Val);
3864 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
3865 ZeroOps.push_back(NumEltsNode);
3866 ZeroOps.push_back(EVTNode);
3867 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3868 &ZeroOps[0], ZeroOps.size()));
3869 IdxOps.push_back(NumEltsNode);
3870 IdxOps.push_back(EVTNode);
3871 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3872 &IdxOps[0], IdxOps.size()));
3873 Ops.push_back(NumEltsNode);
3874 Ops.push_back(EVTNode);
3875 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3876 &Ops[0], Ops.size());
3877 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
3878 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
3879 DstVecSize, DstVecEVT);
3887 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
3888 /// the scalar operation of the vop if it is operating on an integer vector
3889 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
3890 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
3891 ISD::NodeType FPOp) {
3892 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
3893 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
3894 SDOperand LHS = N->getOperand(0);
3895 SDOperand RHS = N->getOperand(1);
3896 SDOperand Shuffle = XformToShuffleWithZero(N);
3897 if (Shuffle.Val) return Shuffle;
3899 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
3901 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
3902 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3903 SmallVector<SDOperand, 8> Ops;
3904 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
3905 SDOperand LHSOp = LHS.getOperand(i);
3906 SDOperand RHSOp = RHS.getOperand(i);
3907 // If these two elements can't be folded, bail out.
3908 if ((LHSOp.getOpcode() != ISD::UNDEF &&
3909 LHSOp.getOpcode() != ISD::Constant &&
3910 LHSOp.getOpcode() != ISD::ConstantFP) ||
3911 (RHSOp.getOpcode() != ISD::UNDEF &&
3912 RHSOp.getOpcode() != ISD::Constant &&
3913 RHSOp.getOpcode() != ISD::ConstantFP))
3915 // Can't fold divide by zero.
3916 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
3917 if ((RHSOp.getOpcode() == ISD::Constant &&
3918 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
3919 (RHSOp.getOpcode() == ISD::ConstantFP &&
3920 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
3923 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
3924 AddToWorkList(Ops.back().Val);
3925 assert((Ops.back().getOpcode() == ISD::UNDEF ||
3926 Ops.back().getOpcode() == ISD::Constant ||
3927 Ops.back().getOpcode() == ISD::ConstantFP) &&
3928 "Scalar binop didn't fold!");
3931 if (Ops.size() == LHS.getNumOperands()-2) {
3932 Ops.push_back(*(LHS.Val->op_end()-2));
3933 Ops.push_back(*(LHS.Val->op_end()-1));
3934 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
3941 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
3942 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
3944 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
3945 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3946 // If we got a simplified select_cc node back from SimplifySelectCC, then
3947 // break it down into a new SETCC node, and a new SELECT node, and then return
3948 // the SELECT node, since we were called with a SELECT node.
3950 // Check to see if we got a select_cc back (to turn into setcc/select).
3951 // Otherwise, just return whatever node we got back, like fabs.
3952 if (SCC.getOpcode() == ISD::SELECT_CC) {
3953 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
3954 SCC.getOperand(0), SCC.getOperand(1),
3956 AddToWorkList(SETCC.Val);
3957 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
3958 SCC.getOperand(3), SETCC);
3965 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
3966 /// are the two values being selected between, see if we can simplify the
3967 /// select. Callers of this should assume that TheSelect is deleted if this
3968 /// returns true. As such, they should return the appropriate thing (e.g. the
3969 /// node) back to the top-level of the DAG combiner loop to avoid it being
3972 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
3975 // If this is a select from two identical things, try to pull the operation
3976 // through the select.
3977 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
3978 // If this is a load and the token chain is identical, replace the select
3979 // of two loads with a load through a select of the address to load from.
3980 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3981 // constants have been dropped into the constant pool.
3982 if (LHS.getOpcode() == ISD::LOAD &&
3983 // Token chains must be identical.
3984 LHS.getOperand(0) == RHS.getOperand(0)) {
3985 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
3986 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
3988 // If this is an EXTLOAD, the VT's must match.
3989 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
3990 // FIXME: this conflates two src values, discarding one. This is not
3991 // the right thing to do, but nothing uses srcvalues now. When they do,
3992 // turn SrcValue into a list of locations.
3994 if (TheSelect->getOpcode() == ISD::SELECT) {
3995 // Check that the condition doesn't reach either load. If so, folding
3996 // this will induce a cycle into the DAG.
3997 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
3998 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
3999 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
4000 TheSelect->getOperand(0), LLD->getBasePtr(),
4004 // Check that the condition doesn't reach either load. If so, folding
4005 // this will induce a cycle into the DAG.
4006 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4007 !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4008 !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
4009 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
4010 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
4011 TheSelect->getOperand(0),
4012 TheSelect->getOperand(1),
4013 LLD->getBasePtr(), RLD->getBasePtr(),
4014 TheSelect->getOperand(4));
4020 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
4021 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
4022 Addr,LLD->getSrcValue(),
4023 LLD->getSrcValueOffset());
4025 Load = DAG.getExtLoad(LLD->getExtensionType(),
4026 TheSelect->getValueType(0),
4027 LLD->getChain(), Addr, LLD->getSrcValue(),
4028 LLD->getSrcValueOffset(),
4029 LLD->getLoadedVT());
4031 // Users of the select now use the result of the load.
4032 CombineTo(TheSelect, Load);
4034 // Users of the old loads now use the new load's chain. We know the
4035 // old-load value is dead now.
4036 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
4037 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
4047 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
4048 SDOperand N2, SDOperand N3,
4051 MVT::ValueType VT = N2.getValueType();
4052 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
4053 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
4054 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
4056 // Determine if the condition we're dealing with is constant
4057 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
4058 if (SCC.Val) AddToWorkList(SCC.Val);
4059 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
4061 // fold select_cc true, x, y -> x
4062 if (SCCC && SCCC->getValue())
4064 // fold select_cc false, x, y -> y
4065 if (SCCC && SCCC->getValue() == 0)
4068 // Check to see if we can simplify the select into an fabs node
4069 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
4070 // Allow either -0.0 or 0.0
4071 if (CFP->getValue() == 0.0) {
4072 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
4073 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
4074 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
4075 N2 == N3.getOperand(0))
4076 return DAG.getNode(ISD::FABS, VT, N0);
4078 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
4079 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
4080 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
4081 N2.getOperand(0) == N3)
4082 return DAG.getNode(ISD::FABS, VT, N3);
4086 // Check to see if we can perform the "gzip trick", transforming
4087 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
4088 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
4089 MVT::isInteger(N0.getValueType()) &&
4090 MVT::isInteger(N2.getValueType()) &&
4091 (N1C->isNullValue() || // (a < 0) ? b : 0
4092 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
4093 MVT::ValueType XType = N0.getValueType();
4094 MVT::ValueType AType = N2.getValueType();
4095 if (XType >= AType) {
4096 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
4097 // single-bit constant.
4098 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
4099 unsigned ShCtV = Log2_64(N2C->getValue());
4100 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
4101 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
4102 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
4103 AddToWorkList(Shift.Val);
4104 if (XType > AType) {
4105 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4106 AddToWorkList(Shift.Val);
4108 return DAG.getNode(ISD::AND, AType, Shift, N2);
4110 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4111 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4112 TLI.getShiftAmountTy()));
4113 AddToWorkList(Shift.Val);
4114 if (XType > AType) {
4115 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4116 AddToWorkList(Shift.Val);
4118 return DAG.getNode(ISD::AND, AType, Shift, N2);
4122 // fold select C, 16, 0 -> shl C, 4
4123 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
4124 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
4125 // Get a SetCC of the condition
4126 // FIXME: Should probably make sure that setcc is legal if we ever have a
4127 // target where it isn't.
4128 SDOperand Temp, SCC;
4129 // cast from setcc result type to select result type
4130 if (AfterLegalize) {
4131 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4132 if (N2.getValueType() < SCC.getValueType())
4133 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
4135 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4137 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
4138 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4140 AddToWorkList(SCC.Val);
4141 AddToWorkList(Temp.Val);
4142 // shl setcc result by log2 n2c
4143 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
4144 DAG.getConstant(Log2_64(N2C->getValue()),
4145 TLI.getShiftAmountTy()));
4148 // Check to see if this is the equivalent of setcc
4149 // FIXME: Turn all of these into setcc if setcc if setcc is legal
4150 // otherwise, go ahead with the folds.
4151 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
4152 MVT::ValueType XType = N0.getValueType();
4153 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
4154 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4155 if (Res.getValueType() != VT)
4156 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
4160 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
4161 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
4162 TLI.isOperationLegal(ISD::CTLZ, XType)) {
4163 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
4164 return DAG.getNode(ISD::SRL, XType, Ctlz,
4165 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
4166 TLI.getShiftAmountTy()));
4168 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
4169 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
4170 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
4172 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
4173 DAG.getConstant(~0ULL, XType));
4174 return DAG.getNode(ISD::SRL, XType,
4175 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
4176 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4177 TLI.getShiftAmountTy()));
4179 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
4180 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
4181 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
4182 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4183 TLI.getShiftAmountTy()));
4184 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
4188 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
4189 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4190 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
4191 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
4192 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) {
4193 MVT::ValueType XType = N0.getValueType();
4194 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4195 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4196 TLI.getShiftAmountTy()));
4197 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4198 AddToWorkList(Shift.Val);
4199 AddToWorkList(Add.Val);
4200 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4202 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
4203 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4204 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
4205 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
4206 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
4207 MVT::ValueType XType = N0.getValueType();
4208 if (SubC->isNullValue() && MVT::isInteger(XType)) {
4209 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4210 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4211 TLI.getShiftAmountTy()));
4212 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4213 AddToWorkList(Shift.Val);
4214 AddToWorkList(Add.Val);
4215 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4223 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
4224 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
4225 SDOperand N1, ISD::CondCode Cond,
4226 bool foldBooleans) {
4227 TargetLowering::DAGCombinerInfo
4228 DagCombineInfo(DAG, !AfterLegalize, false, this);
4229 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
4232 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
4233 /// return a DAG expression to select that will generate the same value by
4234 /// multiplying by a magic number. See:
4235 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4236 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
4237 std::vector<SDNode*> Built;
4238 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
4240 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4246 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
4247 /// return a DAG expression to select that will generate the same value by
4248 /// multiplying by a magic number. See:
4249 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4250 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
4251 std::vector<SDNode*> Built;
4252 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
4254 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4260 /// FindBaseOffset - Return true if base is known not to alias with anything
4261 /// but itself. Provides base object and offset as results.
4262 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4263 // Assume it is a primitive operation.
4264 Base = Ptr; Offset = 0;
4266 // If it's an adding a simple constant then integrate the offset.
4267 if (Base.getOpcode() == ISD::ADD) {
4268 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4269 Base = Base.getOperand(0);
4270 Offset += C->getValue();
4274 // If it's any of the following then it can't alias with anything but itself.
4275 return isa<FrameIndexSDNode>(Base) ||
4276 isa<ConstantPoolSDNode>(Base) ||
4277 isa<GlobalAddressSDNode>(Base);
4280 /// isAlias - Return true if there is any possibility that the two addresses
4282 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4283 const Value *SrcValue1, int SrcValueOffset1,
4284 SDOperand Ptr2, int64_t Size2,
4285 const Value *SrcValue2, int SrcValueOffset2)
4287 // If they are the same then they must be aliases.
4288 if (Ptr1 == Ptr2) return true;
4290 // Gather base node and offset information.
4291 SDOperand Base1, Base2;
4292 int64_t Offset1, Offset2;
4293 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4294 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4296 // If they have a same base address then...
4297 if (Base1 == Base2) {
4298 // Check to see if the addresses overlap.
4299 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4302 // If we know both bases then they can't alias.
4303 if (KnownBase1 && KnownBase2) return false;
4305 if (CombinerGlobalAA) {
4306 // Use alias analysis information.
4307 int Overlap1 = Size1 + SrcValueOffset1 + Offset1;
4308 int Overlap2 = Size2 + SrcValueOffset2 + Offset2;
4309 AliasAnalysis::AliasResult AAResult =
4310 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
4311 if (AAResult == AliasAnalysis::NoAlias)
4315 // Otherwise we have to assume they alias.
4319 /// FindAliasInfo - Extracts the relevant alias information from the memory
4320 /// node. Returns true if the operand was a load.
4321 bool DAGCombiner::FindAliasInfo(SDNode *N,
4322 SDOperand &Ptr, int64_t &Size,
4323 const Value *&SrcValue, int &SrcValueOffset) {
4324 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4325 Ptr = LD->getBasePtr();
4326 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4327 SrcValue = LD->getSrcValue();
4328 SrcValueOffset = LD->getSrcValueOffset();
4330 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4331 Ptr = ST->getBasePtr();
4332 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4333 SrcValue = ST->getSrcValue();
4334 SrcValueOffset = ST->getSrcValueOffset();
4336 assert(0 && "FindAliasInfo expected a memory operand");
4342 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4343 /// looking for aliasing nodes and adding them to the Aliases vector.
4344 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4345 SmallVector<SDOperand, 8> &Aliases) {
4346 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4347 std::set<SDNode *> Visited; // Visited node set.
4349 // Get alias information for node.
4352 const Value *SrcValue;
4354 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
4357 Chains.push_back(OriginalChain);
4359 // Look at each chain and determine if it is an alias. If so, add it to the
4360 // aliases list. If not, then continue up the chain looking for the next
4362 while (!Chains.empty()) {
4363 SDOperand Chain = Chains.back();
4366 // Don't bother if we've been before.
4367 if (Visited.find(Chain.Val) != Visited.end()) continue;
4368 Visited.insert(Chain.Val);
4370 switch (Chain.getOpcode()) {
4371 case ISD::EntryToken:
4372 // Entry token is ideal chain operand, but handled in FindBetterChain.
4377 // Get alias information for Chain.
4380 const Value *OpSrcValue;
4381 int OpSrcValueOffset;
4382 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
4383 OpSrcValue, OpSrcValueOffset);
4385 // If chain is alias then stop here.
4386 if (!(IsLoad && IsOpLoad) &&
4387 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
4388 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
4389 Aliases.push_back(Chain);
4391 // Look further up the chain.
4392 Chains.push_back(Chain.getOperand(0));
4393 // Clean up old chain.
4394 AddToWorkList(Chain.Val);
4399 case ISD::TokenFactor:
4400 // We have to check each of the operands of the token factor, so we queue
4401 // then up. Adding the operands to the queue (stack) in reverse order
4402 // maintains the original order and increases the likelihood that getNode
4403 // will find a matching token factor (CSE.)
4404 for (unsigned n = Chain.getNumOperands(); n;)
4405 Chains.push_back(Chain.getOperand(--n));
4406 // Eliminate the token factor if we can.
4407 AddToWorkList(Chain.Val);
4411 // For all other instructions we will just have to take what we can get.
4412 Aliases.push_back(Chain);
4418 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4419 /// for a better chain (aliasing node.)
4420 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4421 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4423 // Accumulate all the aliases to this node.
4424 GatherAllAliases(N, OldChain, Aliases);
4426 if (Aliases.size() == 0) {
4427 // If no operands then chain to entry token.
4428 return DAG.getEntryNode();
4429 } else if (Aliases.size() == 1) {
4430 // If a single operand then chain to it. We don't need to revisit it.
4434 // Construct a custom tailored token factor.
4435 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4436 &Aliases[0], Aliases.size());
4438 // Make sure the old chain gets cleaned up.
4439 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4444 // SelectionDAG::Combine - This is the entry point for the file.
4446 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
4447 if (!RunningAfterLegalize && ViewDAGCombine1)
4449 if (RunningAfterLegalize && ViewDAGCombine2)
4451 /// run - This is the main entry point to this class.
4453 DAGCombiner(*this, AA).Run(RunningAfterLegalize);