1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/SmallBitVector.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/SetVector.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Analysis/AliasAnalysis.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetLowering.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
43 #define DEBUG_TYPE "dagcombine"
45 STATISTIC(NodesCombined , "Number of dag nodes combined");
46 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
47 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
48 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
49 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
50 STATISTIC(SlicedLoads, "Number of load sliced");
54 CombinerAA("combiner-alias-analysis", cl::Hidden,
55 cl::desc("Enable DAG combiner alias-analysis heuristics"));
58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
59 cl::desc("Enable DAG combiner's use of IR alias analysis"));
62 UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
63 cl::desc("Enable DAG combiner's use of TBAA"));
66 static cl::opt<std::string>
67 CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
68 cl::desc("Only use DAG-combiner alias analysis in this"
72 /// Hidden option to stress test load slicing, i.e., when this option
73 /// is enabled, load slicing bypasses most of its profitability guards.
75 StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
76 cl::desc("Bypass the profitability model of load "
81 MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
82 cl::desc("DAG combiner may split indexing from loads"));
84 //------------------------------ DAGCombiner ---------------------------------//
88 const TargetLowering &TLI;
90 CodeGenOpt::Level OptLevel;
95 /// \brief Worklist of all of the nodes that need to be simplified.
97 /// This must behave as a stack -- new nodes to process are pushed onto the
98 /// back and when processing we pop off of the back.
100 /// The worklist will not contain duplicates but may contain null entries
101 /// due to nodes being deleted from the underlying DAG.
102 SmallVector<SDNode *, 64> Worklist;
104 /// \brief Mapping from an SDNode to its position on the worklist.
106 /// This is used to find and remove nodes from the worklist (by nulling
107 /// them) when they are deleted from the underlying DAG. It relies on
108 /// stable indices of nodes within the worklist.
109 DenseMap<SDNode *, unsigned> WorklistMap;
111 /// \brief Set of nodes which have been combined (at least once).
113 /// This is used to allow us to reliably add any operands of a DAG node
114 /// which have not yet been combined to the worklist.
115 SmallPtrSet<SDNode *, 64> CombinedNodes;
117 // AA - Used for DAG load/store alias analysis.
120 /// When an instruction is simplified, add all users of the instruction to
121 /// the work lists because they might get more simplified now.
122 void AddUsersToWorklist(SDNode *N) {
123 for (SDNode *Node : N->uses())
127 /// Call the node-specific routine that folds each particular type of node.
128 SDValue visit(SDNode *N);
131 /// Add to the worklist making sure its instance is at the back (next to be
133 void AddToWorklist(SDNode *N) {
134 // Skip handle nodes as they can't usefully be combined and confuse the
135 // zero-use deletion strategy.
136 if (N->getOpcode() == ISD::HANDLENODE)
139 if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)
140 Worklist.push_back(N);
143 /// Remove all instances of N from the worklist.
144 void removeFromWorklist(SDNode *N) {
145 CombinedNodes.erase(N);
147 auto It = WorklistMap.find(N);
148 if (It == WorklistMap.end())
149 return; // Not in the worklist.
151 // Null out the entry rather than erasing it to avoid a linear operation.
152 Worklist[It->second] = nullptr;
153 WorklistMap.erase(It);
156 void deleteAndRecombine(SDNode *N);
157 bool recursivelyDeleteUnusedNodes(SDNode *N);
159 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
162 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
163 return CombineTo(N, &Res, 1, AddTo);
166 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
168 SDValue To[] = { Res0, Res1 };
169 return CombineTo(N, To, 2, AddTo);
172 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
176 /// Check the specified integer node value to see if it can be simplified or
177 /// if things it uses can be simplified by bit propagation.
178 /// If so, return true.
179 bool SimplifyDemandedBits(SDValue Op) {
180 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
181 APInt Demanded = APInt::getAllOnesValue(BitWidth);
182 return SimplifyDemandedBits(Op, Demanded);
185 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
187 bool CombineToPreIndexedLoadStore(SDNode *N);
188 bool CombineToPostIndexedLoadStore(SDNode *N);
189 SDValue SplitIndexingFromLoad(LoadSDNode *LD);
190 bool SliceUpLoad(SDNode *N);
192 /// \brief Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
195 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
196 /// \param InVecVT type of the input vector to EVE with bitcasts resolved.
197 /// \param EltNo index of the vector element to load.
198 /// \param OriginalLoad load that EVE came from to be replaced.
199 /// \returns EVE on success SDValue() on failure.
200 SDValue ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
201 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad);
202 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
203 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
204 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
205 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
206 SDValue PromoteIntBinOp(SDValue Op);
207 SDValue PromoteIntShiftOp(SDValue Op);
208 SDValue PromoteExtend(SDValue Op);
209 bool PromoteLoad(SDValue Op);
211 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
212 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
213 ISD::NodeType ExtType);
215 /// Call the node-specific routine that knows how to fold each
216 /// particular type of node. If that doesn't do anything, try the
217 /// target-specific DAG combines.
218 SDValue combine(SDNode *N);
220 // Visitation implementation - Implement dag node combining for different
221 // node types. The semantics are as follows:
223 // SDValue.getNode() == 0 - No change was made
224 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
225 // otherwise - N should be replaced by the returned Operand.
227 SDValue visitTokenFactor(SDNode *N);
228 SDValue visitMERGE_VALUES(SDNode *N);
229 SDValue visitADD(SDNode *N);
230 SDValue visitSUB(SDNode *N);
231 SDValue visitADDC(SDNode *N);
232 SDValue visitSUBC(SDNode *N);
233 SDValue visitADDE(SDNode *N);
234 SDValue visitSUBE(SDNode *N);
235 SDValue visitMUL(SDNode *N);
236 SDValue visitSDIV(SDNode *N);
237 SDValue visitUDIV(SDNode *N);
238 SDValue visitSREM(SDNode *N);
239 SDValue visitUREM(SDNode *N);
240 SDValue visitMULHU(SDNode *N);
241 SDValue visitMULHS(SDNode *N);
242 SDValue visitSMUL_LOHI(SDNode *N);
243 SDValue visitUMUL_LOHI(SDNode *N);
244 SDValue visitSMULO(SDNode *N);
245 SDValue visitUMULO(SDNode *N);
246 SDValue visitSDIVREM(SDNode *N);
247 SDValue visitUDIVREM(SDNode *N);
248 SDValue visitAND(SDNode *N);
249 SDValue visitOR(SDNode *N);
250 SDValue visitXOR(SDNode *N);
251 SDValue SimplifyVBinOp(SDNode *N);
252 SDValue SimplifyVUnaryOp(SDNode *N);
253 SDValue visitSHL(SDNode *N);
254 SDValue visitSRA(SDNode *N);
255 SDValue visitSRL(SDNode *N);
256 SDValue visitRotate(SDNode *N);
257 SDValue visitCTLZ(SDNode *N);
258 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
259 SDValue visitCTTZ(SDNode *N);
260 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
261 SDValue visitCTPOP(SDNode *N);
262 SDValue visitSELECT(SDNode *N);
263 SDValue visitVSELECT(SDNode *N);
264 SDValue visitSELECT_CC(SDNode *N);
265 SDValue visitSETCC(SDNode *N);
266 SDValue visitSIGN_EXTEND(SDNode *N);
267 SDValue visitZERO_EXTEND(SDNode *N);
268 SDValue visitANY_EXTEND(SDNode *N);
269 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
270 SDValue visitTRUNCATE(SDNode *N);
271 SDValue visitBITCAST(SDNode *N);
272 SDValue visitBUILD_PAIR(SDNode *N);
273 SDValue visitFADD(SDNode *N);
274 SDValue visitFSUB(SDNode *N);
275 SDValue visitFMUL(SDNode *N);
276 SDValue visitFMA(SDNode *N);
277 SDValue visitFDIV(SDNode *N);
278 SDValue visitFREM(SDNode *N);
279 SDValue visitFSQRT(SDNode *N);
280 SDValue visitFCOPYSIGN(SDNode *N);
281 SDValue visitSINT_TO_FP(SDNode *N);
282 SDValue visitUINT_TO_FP(SDNode *N);
283 SDValue visitFP_TO_SINT(SDNode *N);
284 SDValue visitFP_TO_UINT(SDNode *N);
285 SDValue visitFP_ROUND(SDNode *N);
286 SDValue visitFP_ROUND_INREG(SDNode *N);
287 SDValue visitFP_EXTEND(SDNode *N);
288 SDValue visitFNEG(SDNode *N);
289 SDValue visitFABS(SDNode *N);
290 SDValue visitFCEIL(SDNode *N);
291 SDValue visitFTRUNC(SDNode *N);
292 SDValue visitFFLOOR(SDNode *N);
293 SDValue visitFMINNUM(SDNode *N);
294 SDValue visitFMAXNUM(SDNode *N);
295 SDValue visitBRCOND(SDNode *N);
296 SDValue visitBR_CC(SDNode *N);
297 SDValue visitLOAD(SDNode *N);
298 SDValue visitSTORE(SDNode *N);
299 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
300 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
301 SDValue visitBUILD_VECTOR(SDNode *N);
302 SDValue visitCONCAT_VECTORS(SDNode *N);
303 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
304 SDValue visitVECTOR_SHUFFLE(SDNode *N);
305 SDValue visitINSERT_SUBVECTOR(SDNode *N);
306 SDValue visitMLOAD(SDNode *N);
307 SDValue visitMSTORE(SDNode *N);
309 SDValue XformToShuffleWithZero(SDNode *N);
310 SDValue ReassociateOps(unsigned Opc, SDLoc DL, SDValue LHS, SDValue RHS);
312 SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
314 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
315 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
316 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
317 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
318 SDValue N3, ISD::CondCode CC,
319 bool NotExtCompare = false);
320 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
321 SDLoc DL, bool foldBooleans = true);
323 bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
325 bool isOneUseSetCC(SDValue N) const;
327 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
329 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
330 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
331 SDValue BuildSDIV(SDNode *N);
332 SDValue BuildSDIVPow2(SDNode *N);
333 SDValue BuildUDIV(SDNode *N);
334 SDValue BuildReciprocalEstimate(SDValue Op);
335 SDValue BuildRsqrtEstimate(SDValue Op);
336 SDValue BuildRsqrtNROneConst(SDValue Op, SDValue Est, unsigned Iterations);
337 SDValue BuildRsqrtNRTwoConst(SDValue Op, SDValue Est, unsigned Iterations);
338 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
339 bool DemandHighBits = true);
340 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
341 SDNode *MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
342 SDValue InnerPos, SDValue InnerNeg,
343 unsigned PosOpcode, unsigned NegOpcode,
345 SDNode *MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL);
346 SDValue ReduceLoadWidth(SDNode *N);
347 SDValue ReduceLoadOpStoreWidth(SDNode *N);
348 SDValue TransformFPLoadStorePair(SDNode *N);
349 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
350 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N);
352 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
354 /// Walk up chain skipping non-aliasing memory nodes,
355 /// looking for aliasing nodes and adding them to the Aliases vector.
356 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
357 SmallVectorImpl<SDValue> &Aliases);
359 /// Return true if there is any possibility that the two addresses overlap.
360 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const;
362 /// Walk up chain skipping non-aliasing memory nodes, looking for a better
363 /// chain (aliasing node.)
364 SDValue FindBetterChain(SDNode *N, SDValue Chain);
366 /// Merge consecutive store operations into a wide store.
367 /// This optimization uses wide integers or vectors when possible.
368 /// \return True if some memory operations were changed.
369 bool MergeConsecutiveStores(StoreSDNode *N);
371 /// \brief Try to transform a truncation where C is a constant:
372 /// (trunc (and X, C)) -> (and (trunc X), (trunc C))
374 /// \p N needs to be a truncation and its first operand an AND. Other
375 /// requirements are checked by the function (e.g. that trunc is
376 /// single-use) and if missed an empty SDValue is returned.
377 SDValue distributeTruncateThroughAnd(SDNode *N);
380 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
381 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
382 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {
383 AttributeSet FnAttrs =
384 DAG.getMachineFunction().getFunction()->getAttributes();
386 FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
387 Attribute::OptimizeForSize) ||
388 FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
391 /// Runs the dag combiner on all nodes in the work list
392 void Run(CombineLevel AtLevel);
394 SelectionDAG &getDAG() const { return DAG; }
396 /// Returns a type large enough to hold any valid shift amount - before type
397 /// legalization these can be huge.
398 EVT getShiftAmountTy(EVT LHSTy) {
399 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
400 if (LHSTy.isVector())
402 return LegalTypes ? TLI.getScalarShiftAmountTy(LHSTy)
403 : TLI.getPointerTy();
406 /// This method returns true if we are running before type legalization or
407 /// if the specified VT is legal.
408 bool isTypeLegal(const EVT &VT) {
409 if (!LegalTypes) return true;
410 return TLI.isTypeLegal(VT);
413 /// Convenience wrapper around TargetLowering::getSetCCResultType
414 EVT getSetCCResultType(EVT VT) const {
415 return TLI.getSetCCResultType(*DAG.getContext(), VT);
422 /// This class is a DAGUpdateListener that removes any deleted
423 /// nodes from the worklist.
424 class WorklistRemover : public SelectionDAG::DAGUpdateListener {
427 explicit WorklistRemover(DAGCombiner &dc)
428 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
430 void NodeDeleted(SDNode *N, SDNode *E) override {
431 DC.removeFromWorklist(N);
436 //===----------------------------------------------------------------------===//
437 // TargetLowering::DAGCombinerInfo implementation
438 //===----------------------------------------------------------------------===//
440 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
441 ((DAGCombiner*)DC)->AddToWorklist(N);
444 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
445 ((DAGCombiner*)DC)->removeFromWorklist(N);
448 SDValue TargetLowering::DAGCombinerInfo::
449 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
450 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
453 SDValue TargetLowering::DAGCombinerInfo::
454 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
455 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
459 SDValue TargetLowering::DAGCombinerInfo::
460 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
461 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
464 void TargetLowering::DAGCombinerInfo::
465 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
466 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
469 //===----------------------------------------------------------------------===//
471 //===----------------------------------------------------------------------===//
473 void DAGCombiner::deleteAndRecombine(SDNode *N) {
474 removeFromWorklist(N);
476 // If the operands of this node are only used by the node, they will now be
477 // dead. Make sure to re-visit them and recursively delete dead nodes.
478 for (const SDValue &Op : N->ops())
479 // For an operand generating multiple values, one of the values may
480 // become dead allowing further simplification (e.g. split index
481 // arithmetic from an indexed load).
482 if (Op->hasOneUse() || Op->getNumValues() > 1)
483 AddToWorklist(Op.getNode());
488 /// Return 1 if we can compute the negated form of the specified expression for
489 /// the same cost as the expression itself, or 2 if we can compute the negated
490 /// form more cheaply than the expression itself.
491 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
492 const TargetLowering &TLI,
493 const TargetOptions *Options,
494 unsigned Depth = 0) {
495 // fneg is removable even if it has multiple uses.
496 if (Op.getOpcode() == ISD::FNEG) return 2;
498 // Don't allow anything with multiple uses.
499 if (!Op.hasOneUse()) return 0;
501 // Don't recurse exponentially.
502 if (Depth > 6) return 0;
504 switch (Op.getOpcode()) {
505 default: return false;
506 case ISD::ConstantFP:
507 // Don't invert constant FP values after legalize. The negated constant
508 // isn't necessarily legal.
509 return LegalOperations ? 0 : 1;
511 // FIXME: determine better conditions for this xform.
512 if (!Options->UnsafeFPMath) return 0;
514 // After operation legalization, it might not be legal to create new FSUBs.
515 if (LegalOperations &&
516 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
519 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
520 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
523 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
524 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
527 // We can't turn -(A-B) into B-A when we honor signed zeros.
528 if (!Options->UnsafeFPMath) return 0;
530 // fold (fneg (fsub A, B)) -> (fsub B, A)
535 if (Options->HonorSignDependentRoundingFPMath()) return 0;
537 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
538 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
542 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
548 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
553 /// If isNegatibleForFree returns true, return the newly negated expression.
554 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
555 bool LegalOperations, unsigned Depth = 0) {
556 const TargetOptions &Options = DAG.getTarget().Options;
557 // fneg is removable even if it has multiple uses.
558 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
560 // Don't allow anything with multiple uses.
561 assert(Op.hasOneUse() && "Unknown reuse!");
563 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
564 switch (Op.getOpcode()) {
565 default: llvm_unreachable("Unknown code");
566 case ISD::ConstantFP: {
567 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
569 return DAG.getConstantFP(V, Op.getValueType());
572 // FIXME: determine better conditions for this xform.
573 assert(Options.UnsafeFPMath);
575 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
576 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
577 DAG.getTargetLoweringInfo(), &Options, Depth+1))
578 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
579 GetNegatedExpression(Op.getOperand(0), DAG,
580 LegalOperations, Depth+1),
582 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
583 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
584 GetNegatedExpression(Op.getOperand(1), DAG,
585 LegalOperations, Depth+1),
588 // We can't turn -(A-B) into B-A when we honor signed zeros.
589 assert(Options.UnsafeFPMath);
591 // fold (fneg (fsub 0, B)) -> B
592 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
593 if (N0CFP->getValueAPF().isZero())
594 return Op.getOperand(1);
596 // fold (fneg (fsub A, B)) -> (fsub B, A)
597 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
598 Op.getOperand(1), Op.getOperand(0));
602 assert(!Options.HonorSignDependentRoundingFPMath());
604 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
605 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
606 DAG.getTargetLoweringInfo(), &Options, Depth+1))
607 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
608 GetNegatedExpression(Op.getOperand(0), DAG,
609 LegalOperations, Depth+1),
612 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
613 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
615 GetNegatedExpression(Op.getOperand(1), DAG,
616 LegalOperations, Depth+1));
620 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
621 GetNegatedExpression(Op.getOperand(0), DAG,
622 LegalOperations, Depth+1));
624 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
625 GetNegatedExpression(Op.getOperand(0), DAG,
626 LegalOperations, Depth+1),
631 // Return true if this node is a setcc, or is a select_cc
632 // that selects between the target values used for true and false, making it
633 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
634 // the appropriate nodes based on the type of node we are checking. This
635 // simplifies life a bit for the callers.
636 bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
638 if (N.getOpcode() == ISD::SETCC) {
639 LHS = N.getOperand(0);
640 RHS = N.getOperand(1);
641 CC = N.getOperand(2);
645 if (N.getOpcode() != ISD::SELECT_CC ||
646 !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
647 !TLI.isConstFalseVal(N.getOperand(3).getNode()))
650 if (TLI.getBooleanContents(N.getValueType()) ==
651 TargetLowering::UndefinedBooleanContent)
654 LHS = N.getOperand(0);
655 RHS = N.getOperand(1);
656 CC = N.getOperand(4);
660 /// Return true if this is a SetCC-equivalent operation with only one use.
661 /// If this is true, it allows the users to invert the operation for free when
662 /// it is profitable to do so.
663 bool DAGCombiner::isOneUseSetCC(SDValue N) const {
665 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
670 /// Returns true if N is a BUILD_VECTOR node whose
671 /// elements are all the same constant or undefined.
672 static bool isConstantSplatVector(SDNode *N, APInt& SplatValue) {
673 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(N);
678 unsigned SplatBitSize;
680 EVT EltVT = N->getValueType(0).getVectorElementType();
681 return (C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
683 EltVT.getSizeInBits() >= SplatBitSize);
686 // \brief Returns the SDNode if it is a constant BuildVector or constant.
687 static SDNode *isConstantBuildVectorOrConstantInt(SDValue N) {
688 if (isa<ConstantSDNode>(N))
690 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
691 if (BV && BV->isConstant())
696 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
698 static ConstantSDNode *isConstOrConstSplat(SDValue N) {
699 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N))
702 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
703 BitVector UndefElements;
704 ConstantSDNode *CN = BV->getConstantSplatNode(&UndefElements);
706 // BuildVectors can truncate their operands. Ignore that case here.
707 // FIXME: We blindly ignore splats which include undef which is overly
709 if (CN && UndefElements.none() &&
710 CN->getValueType(0) == N.getValueType().getScalarType())
717 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
719 static ConstantFPSDNode *isConstOrConstSplatFP(SDValue N) {
720 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
723 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
724 BitVector UndefElements;
725 ConstantFPSDNode *CN = BV->getConstantFPSplatNode(&UndefElements);
727 if (CN && UndefElements.none())
734 SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDLoc DL,
735 SDValue N0, SDValue N1) {
736 EVT VT = N0.getValueType();
737 if (N0.getOpcode() == Opc) {
738 if (SDNode *L = isConstantBuildVectorOrConstantInt(N0.getOperand(1))) {
739 if (SDNode *R = isConstantBuildVectorOrConstantInt(N1)) {
740 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
741 SDValue OpNode = DAG.FoldConstantArithmetic(Opc, VT, L, R);
742 if (!OpNode.getNode())
744 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
746 if (N0.hasOneUse()) {
747 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one
749 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
750 if (!OpNode.getNode())
752 AddToWorklist(OpNode.getNode());
753 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
758 if (N1.getOpcode() == Opc) {
759 if (SDNode *R = isConstantBuildVectorOrConstantInt(N1.getOperand(1))) {
760 if (SDNode *L = isConstantBuildVectorOrConstantInt(N0)) {
761 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
762 SDValue OpNode = DAG.FoldConstantArithmetic(Opc, VT, R, L);
763 if (!OpNode.getNode())
765 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
767 if (N1.hasOneUse()) {
768 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one
770 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N1.getOperand(0), N0);
771 if (!OpNode.getNode())
773 AddToWorklist(OpNode.getNode());
774 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
782 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
784 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
786 DEBUG(dbgs() << "\nReplacing.1 ";
788 dbgs() << "\nWith: ";
789 To[0].getNode()->dump(&DAG);
790 dbgs() << " and " << NumTo-1 << " other values\n");
791 for (unsigned i = 0, e = NumTo; i != e; ++i)
792 assert((!To[i].getNode() ||
793 N->getValueType(i) == To[i].getValueType()) &&
794 "Cannot combine value to value of different type!");
796 WorklistRemover DeadNodes(*this);
797 DAG.ReplaceAllUsesWith(N, To);
799 // Push the new nodes and any users onto the worklist
800 for (unsigned i = 0, e = NumTo; i != e; ++i) {
801 if (To[i].getNode()) {
802 AddToWorklist(To[i].getNode());
803 AddUsersToWorklist(To[i].getNode());
808 // Finally, if the node is now dead, remove it from the graph. The node
809 // may not be dead if the replacement process recursively simplified to
810 // something else needing this node.
812 deleteAndRecombine(N);
813 return SDValue(N, 0);
817 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
818 // Replace all uses. If any nodes become isomorphic to other nodes and
819 // are deleted, make sure to remove them from our worklist.
820 WorklistRemover DeadNodes(*this);
821 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
823 // Push the new node and any (possibly new) users onto the worklist.
824 AddToWorklist(TLO.New.getNode());
825 AddUsersToWorklist(TLO.New.getNode());
827 // Finally, if the node is now dead, remove it from the graph. The node
828 // may not be dead if the replacement process recursively simplified to
829 // something else needing this node.
830 if (TLO.Old.getNode()->use_empty())
831 deleteAndRecombine(TLO.Old.getNode());
834 /// Check the specified integer node value to see if it can be simplified or if
835 /// things it uses can be simplified by bit propagation. If so, return true.
836 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
837 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
838 APInt KnownZero, KnownOne;
839 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
843 AddToWorklist(Op.getNode());
845 // Replace the old value with the new one.
847 DEBUG(dbgs() << "\nReplacing.2 ";
848 TLO.Old.getNode()->dump(&DAG);
849 dbgs() << "\nWith: ";
850 TLO.New.getNode()->dump(&DAG);
853 CommitTargetLoweringOpt(TLO);
857 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
859 EVT VT = Load->getValueType(0);
860 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
862 DEBUG(dbgs() << "\nReplacing.9 ";
864 dbgs() << "\nWith: ";
865 Trunc.getNode()->dump(&DAG);
867 WorklistRemover DeadNodes(*this);
868 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
869 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
870 deleteAndRecombine(Load);
871 AddToWorklist(Trunc.getNode());
874 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
877 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
878 EVT MemVT = LD->getMemoryVT();
879 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
880 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
882 : LD->getExtensionType();
884 return DAG.getExtLoad(ExtType, dl, PVT,
885 LD->getChain(), LD->getBasePtr(),
886 MemVT, LD->getMemOperand());
889 unsigned Opc = Op.getOpcode();
892 case ISD::AssertSext:
893 return DAG.getNode(ISD::AssertSext, dl, PVT,
894 SExtPromoteOperand(Op.getOperand(0), PVT),
896 case ISD::AssertZext:
897 return DAG.getNode(ISD::AssertZext, dl, PVT,
898 ZExtPromoteOperand(Op.getOperand(0), PVT),
900 case ISD::Constant: {
902 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
903 return DAG.getNode(ExtOpc, dl, PVT, Op);
907 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
909 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
912 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
913 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
915 EVT OldVT = Op.getValueType();
917 bool Replace = false;
918 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
919 if (!NewOp.getNode())
921 AddToWorklist(NewOp.getNode());
924 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
925 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
926 DAG.getValueType(OldVT));
929 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
930 EVT OldVT = Op.getValueType();
932 bool Replace = false;
933 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
934 if (!NewOp.getNode())
936 AddToWorklist(NewOp.getNode());
939 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
940 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
943 /// Promote the specified integer binary operation if the target indicates it is
944 /// beneficial. e.g. On x86, it's usually better to promote i16 operations to
945 /// i32 since i16 instructions are longer.
946 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
947 if (!LegalOperations)
950 EVT VT = Op.getValueType();
951 if (VT.isVector() || !VT.isInteger())
954 // If operation type is 'undesirable', e.g. i16 on x86, consider
956 unsigned Opc = Op.getOpcode();
957 if (TLI.isTypeDesirableForOp(Opc, VT))
961 // Consult target whether it is a good idea to promote this operation and
962 // what's the right type to promote it to.
963 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
964 assert(PVT != VT && "Don't know what type to promote to!");
966 bool Replace0 = false;
967 SDValue N0 = Op.getOperand(0);
968 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
972 bool Replace1 = false;
973 SDValue N1 = Op.getOperand(1);
978 NN1 = PromoteOperand(N1, PVT, Replace1);
983 AddToWorklist(NN0.getNode());
985 AddToWorklist(NN1.getNode());
988 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
990 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
992 DEBUG(dbgs() << "\nPromoting ";
993 Op.getNode()->dump(&DAG));
995 return DAG.getNode(ISD::TRUNCATE, dl, VT,
996 DAG.getNode(Opc, dl, PVT, NN0, NN1));
1001 /// Promote the specified integer shift operation if the target indicates it is
1002 /// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1003 /// i32 since i16 instructions are longer.
1004 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
1005 if (!LegalOperations)
1008 EVT VT = Op.getValueType();
1009 if (VT.isVector() || !VT.isInteger())
1012 // If operation type is 'undesirable', e.g. i16 on x86, consider
1014 unsigned Opc = Op.getOpcode();
1015 if (TLI.isTypeDesirableForOp(Opc, VT))
1019 // Consult target whether it is a good idea to promote this operation and
1020 // what's the right type to promote it to.
1021 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1022 assert(PVT != VT && "Don't know what type to promote to!");
1024 bool Replace = false;
1025 SDValue N0 = Op.getOperand(0);
1026 if (Opc == ISD::SRA)
1027 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
1028 else if (Opc == ISD::SRL)
1029 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
1031 N0 = PromoteOperand(N0, PVT, Replace);
1035 AddToWorklist(N0.getNode());
1037 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
1039 DEBUG(dbgs() << "\nPromoting ";
1040 Op.getNode()->dump(&DAG));
1042 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1043 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
1048 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
1049 if (!LegalOperations)
1052 EVT VT = Op.getValueType();
1053 if (VT.isVector() || !VT.isInteger())
1056 // If operation type is 'undesirable', e.g. i16 on x86, consider
1058 unsigned Opc = Op.getOpcode();
1059 if (TLI.isTypeDesirableForOp(Opc, VT))
1063 // Consult target whether it is a good idea to promote this operation and
1064 // what's the right type to promote it to.
1065 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1066 assert(PVT != VT && "Don't know what type to promote to!");
1067 // fold (aext (aext x)) -> (aext x)
1068 // fold (aext (zext x)) -> (zext x)
1069 // fold (aext (sext x)) -> (sext x)
1070 DEBUG(dbgs() << "\nPromoting ";
1071 Op.getNode()->dump(&DAG));
1072 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1077 bool DAGCombiner::PromoteLoad(SDValue Op) {
1078 if (!LegalOperations)
1081 EVT VT = Op.getValueType();
1082 if (VT.isVector() || !VT.isInteger())
1085 // If operation type is 'undesirable', e.g. i16 on x86, consider
1087 unsigned Opc = Op.getOpcode();
1088 if (TLI.isTypeDesirableForOp(Opc, VT))
1092 // Consult target whether it is a good idea to promote this operation and
1093 // what's the right type to promote it to.
1094 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1095 assert(PVT != VT && "Don't know what type to promote to!");
1098 SDNode *N = Op.getNode();
1099 LoadSDNode *LD = cast<LoadSDNode>(N);
1100 EVT MemVT = LD->getMemoryVT();
1101 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
1102 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
1104 : LD->getExtensionType();
1105 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
1106 LD->getChain(), LD->getBasePtr(),
1107 MemVT, LD->getMemOperand());
1108 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
1110 DEBUG(dbgs() << "\nPromoting ";
1113 Result.getNode()->dump(&DAG);
1115 WorklistRemover DeadNodes(*this);
1116 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
1117 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1118 deleteAndRecombine(N);
1119 AddToWorklist(Result.getNode());
1125 /// \brief Recursively delete a node which has no uses and any operands for
1126 /// which it is the only use.
1128 /// Note that this both deletes the nodes and removes them from the worklist.
1129 /// It also adds any nodes who have had a user deleted to the worklist as they
1130 /// may now have only one use and subject to other combines.
1131 bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
1132 if (!N->use_empty())
1135 SmallSetVector<SDNode *, 16> Nodes;
1138 N = Nodes.pop_back_val();
1142 if (N->use_empty()) {
1143 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1144 Nodes.insert(N->getOperand(i).getNode());
1146 removeFromWorklist(N);
1151 } while (!Nodes.empty());
1155 //===----------------------------------------------------------------------===//
1156 // Main DAG Combiner implementation
1157 //===----------------------------------------------------------------------===//
1159 void DAGCombiner::Run(CombineLevel AtLevel) {
1160 // set the instance variables, so that the various visit routines may use it.
1162 LegalOperations = Level >= AfterLegalizeVectorOps;
1163 LegalTypes = Level >= AfterLegalizeTypes;
1165 // Early exit if this basic block is in an optnone function.
1166 AttributeSet FnAttrs =
1167 DAG.getMachineFunction().getFunction()->getAttributes();
1168 if (FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
1169 Attribute::OptimizeNone))
1172 // Add all the dag nodes to the worklist.
1173 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
1174 E = DAG.allnodes_end(); I != E; ++I)
1177 // Create a dummy node (which is not added to allnodes), that adds a reference
1178 // to the root node, preventing it from being deleted, and tracking any
1179 // changes of the root.
1180 HandleSDNode Dummy(DAG.getRoot());
1182 // while the worklist isn't empty, find a node and
1183 // try and combine it.
1184 while (!WorklistMap.empty()) {
1186 // The Worklist holds the SDNodes in order, but it may contain null entries.
1188 N = Worklist.pop_back_val();
1191 bool GoodWorklistEntry = WorklistMap.erase(N);
1192 (void)GoodWorklistEntry;
1193 assert(GoodWorklistEntry &&
1194 "Found a worklist entry without a corresponding map entry!");
1196 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1197 // N is deleted from the DAG, since they too may now be dead or may have a
1198 // reduced number of uses, allowing other xforms.
1199 if (recursivelyDeleteUnusedNodes(N))
1202 WorklistRemover DeadNodes(*this);
1204 // If this combine is running after legalizing the DAG, re-legalize any
1205 // nodes pulled off the worklist.
1206 if (Level == AfterLegalizeDAG) {
1207 SmallSetVector<SDNode *, 16> UpdatedNodes;
1208 bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);
1210 for (SDNode *LN : UpdatedNodes) {
1212 AddUsersToWorklist(LN);
1218 DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG));
1220 // Add any operands of the new node which have not yet been combined to the
1221 // worklist as well. Because the worklist uniques things already, this
1222 // won't repeatedly process the same operand.
1223 CombinedNodes.insert(N);
1224 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1225 if (!CombinedNodes.count(N->getOperand(i).getNode()))
1226 AddToWorklist(N->getOperand(i).getNode());
1228 SDValue RV = combine(N);
1235 // If we get back the same node we passed in, rather than a new node or
1236 // zero, we know that the node must have defined multiple values and
1237 // CombineTo was used. Since CombineTo takes care of the worklist
1238 // mechanics for us, we have no work to do in this case.
1239 if (RV.getNode() == N)
1242 assert(N->getOpcode() != ISD::DELETED_NODE &&
1243 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1244 "Node was deleted but visit returned new node!");
1246 DEBUG(dbgs() << " ... into: ";
1247 RV.getNode()->dump(&DAG));
1249 // Transfer debug value.
1250 DAG.TransferDbgValues(SDValue(N, 0), RV);
1251 if (N->getNumValues() == RV.getNode()->getNumValues())
1252 DAG.ReplaceAllUsesWith(N, RV.getNode());
1254 assert(N->getValueType(0) == RV.getValueType() &&
1255 N->getNumValues() == 1 && "Type mismatch");
1257 DAG.ReplaceAllUsesWith(N, &OpV);
1260 // Push the new node and any users onto the worklist
1261 AddToWorklist(RV.getNode());
1262 AddUsersToWorklist(RV.getNode());
1264 // Finally, if the node is now dead, remove it from the graph. The node
1265 // may not be dead if the replacement process recursively simplified to
1266 // something else needing this node. This will also take care of adding any
1267 // operands which have lost a user to the worklist.
1268 recursivelyDeleteUnusedNodes(N);
1271 // If the root changed (e.g. it was a dead load, update the root).
1272 DAG.setRoot(Dummy.getValue());
1273 DAG.RemoveDeadNodes();
1276 SDValue DAGCombiner::visit(SDNode *N) {
1277 switch (N->getOpcode()) {
1279 case ISD::TokenFactor: return visitTokenFactor(N);
1280 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1281 case ISD::ADD: return visitADD(N);
1282 case ISD::SUB: return visitSUB(N);
1283 case ISD::ADDC: return visitADDC(N);
1284 case ISD::SUBC: return visitSUBC(N);
1285 case ISD::ADDE: return visitADDE(N);
1286 case ISD::SUBE: return visitSUBE(N);
1287 case ISD::MUL: return visitMUL(N);
1288 case ISD::SDIV: return visitSDIV(N);
1289 case ISD::UDIV: return visitUDIV(N);
1290 case ISD::SREM: return visitSREM(N);
1291 case ISD::UREM: return visitUREM(N);
1292 case ISD::MULHU: return visitMULHU(N);
1293 case ISD::MULHS: return visitMULHS(N);
1294 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1295 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1296 case ISD::SMULO: return visitSMULO(N);
1297 case ISD::UMULO: return visitUMULO(N);
1298 case ISD::SDIVREM: return visitSDIVREM(N);
1299 case ISD::UDIVREM: return visitUDIVREM(N);
1300 case ISD::AND: return visitAND(N);
1301 case ISD::OR: return visitOR(N);
1302 case ISD::XOR: return visitXOR(N);
1303 case ISD::SHL: return visitSHL(N);
1304 case ISD::SRA: return visitSRA(N);
1305 case ISD::SRL: return visitSRL(N);
1307 case ISD::ROTL: return visitRotate(N);
1308 case ISD::CTLZ: return visitCTLZ(N);
1309 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1310 case ISD::CTTZ: return visitCTTZ(N);
1311 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1312 case ISD::CTPOP: return visitCTPOP(N);
1313 case ISD::SELECT: return visitSELECT(N);
1314 case ISD::VSELECT: return visitVSELECT(N);
1315 case ISD::SELECT_CC: return visitSELECT_CC(N);
1316 case ISD::SETCC: return visitSETCC(N);
1317 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1318 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1319 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1320 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1321 case ISD::TRUNCATE: return visitTRUNCATE(N);
1322 case ISD::BITCAST: return visitBITCAST(N);
1323 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1324 case ISD::FADD: return visitFADD(N);
1325 case ISD::FSUB: return visitFSUB(N);
1326 case ISD::FMUL: return visitFMUL(N);
1327 case ISD::FMA: return visitFMA(N);
1328 case ISD::FDIV: return visitFDIV(N);
1329 case ISD::FREM: return visitFREM(N);
1330 case ISD::FSQRT: return visitFSQRT(N);
1331 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1332 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1333 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1334 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1335 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1336 case ISD::FP_ROUND: return visitFP_ROUND(N);
1337 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1338 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1339 case ISD::FNEG: return visitFNEG(N);
1340 case ISD::FABS: return visitFABS(N);
1341 case ISD::FFLOOR: return visitFFLOOR(N);
1342 case ISD::FMINNUM: return visitFMINNUM(N);
1343 case ISD::FMAXNUM: return visitFMAXNUM(N);
1344 case ISD::FCEIL: return visitFCEIL(N);
1345 case ISD::FTRUNC: return visitFTRUNC(N);
1346 case ISD::BRCOND: return visitBRCOND(N);
1347 case ISD::BR_CC: return visitBR_CC(N);
1348 case ISD::LOAD: return visitLOAD(N);
1349 case ISD::STORE: return visitSTORE(N);
1350 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1351 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1352 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1353 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1354 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1355 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1356 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
1357 case ISD::MLOAD: return visitMLOAD(N);
1358 case ISD::MSTORE: return visitMSTORE(N);
1363 SDValue DAGCombiner::combine(SDNode *N) {
1364 SDValue RV = visit(N);
1366 // If nothing happened, try a target-specific DAG combine.
1367 if (!RV.getNode()) {
1368 assert(N->getOpcode() != ISD::DELETED_NODE &&
1369 "Node was deleted but visit returned NULL!");
1371 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1372 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1374 // Expose the DAG combiner to the target combiner impls.
1375 TargetLowering::DAGCombinerInfo
1376 DagCombineInfo(DAG, Level, false, this);
1378 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1382 // If nothing happened still, try promoting the operation.
1383 if (!RV.getNode()) {
1384 switch (N->getOpcode()) {
1392 RV = PromoteIntBinOp(SDValue(N, 0));
1397 RV = PromoteIntShiftOp(SDValue(N, 0));
1399 case ISD::SIGN_EXTEND:
1400 case ISD::ZERO_EXTEND:
1401 case ISD::ANY_EXTEND:
1402 RV = PromoteExtend(SDValue(N, 0));
1405 if (PromoteLoad(SDValue(N, 0)))
1411 // If N is a commutative binary node, try commuting it to enable more
1413 if (!RV.getNode() && SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1414 N->getNumValues() == 1) {
1415 SDValue N0 = N->getOperand(0);
1416 SDValue N1 = N->getOperand(1);
1418 // Constant operands are canonicalized to RHS.
1419 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1420 SDValue Ops[] = {N1, N0};
1422 if (const BinaryWithFlagsSDNode *BinNode =
1423 dyn_cast<BinaryWithFlagsSDNode>(N)) {
1424 CSENode = DAG.getNodeIfExists(
1425 N->getOpcode(), N->getVTList(), Ops, BinNode->hasNoUnsignedWrap(),
1426 BinNode->hasNoSignedWrap(), BinNode->isExact());
1428 CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops);
1431 return SDValue(CSENode, 0);
1438 /// Given a node, return its input chain if it has one, otherwise return a null
1440 static SDValue getInputChainForNode(SDNode *N) {
1441 if (unsigned NumOps = N->getNumOperands()) {
1442 if (N->getOperand(0).getValueType() == MVT::Other)
1443 return N->getOperand(0);
1444 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1445 return N->getOperand(NumOps-1);
1446 for (unsigned i = 1; i < NumOps-1; ++i)
1447 if (N->getOperand(i).getValueType() == MVT::Other)
1448 return N->getOperand(i);
1453 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1454 // If N has two operands, where one has an input chain equal to the other,
1455 // the 'other' chain is redundant.
1456 if (N->getNumOperands() == 2) {
1457 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1458 return N->getOperand(0);
1459 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1460 return N->getOperand(1);
1463 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1464 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1465 SmallPtrSet<SDNode*, 16> SeenOps;
1466 bool Changed = false; // If we should replace this token factor.
1468 // Start out with this token factor.
1471 // Iterate through token factors. The TFs grows when new token factors are
1473 for (unsigned i = 0; i < TFs.size(); ++i) {
1474 SDNode *TF = TFs[i];
1476 // Check each of the operands.
1477 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1478 SDValue Op = TF->getOperand(i);
1480 switch (Op.getOpcode()) {
1481 case ISD::EntryToken:
1482 // Entry tokens don't need to be added to the list. They are
1487 case ISD::TokenFactor:
1488 if (Op.hasOneUse() &&
1489 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1490 // Queue up for processing.
1491 TFs.push_back(Op.getNode());
1492 // Clean up in case the token factor is removed.
1493 AddToWorklist(Op.getNode());
1500 // Only add if it isn't already in the list.
1501 if (SeenOps.insert(Op.getNode()).second)
1512 // If we've change things around then replace token factor.
1515 // The entry token is the only possible outcome.
1516 Result = DAG.getEntryNode();
1518 // New and improved token factor.
1519 Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Ops);
1522 // Don't add users to work list.
1523 return CombineTo(N, Result, false);
1529 /// MERGE_VALUES can always be eliminated.
1530 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1531 WorklistRemover DeadNodes(*this);
1532 // Replacing results may cause a different MERGE_VALUES to suddenly
1533 // be CSE'd with N, and carry its uses with it. Iterate until no
1534 // uses remain, to ensure that the node can be safely deleted.
1535 // First add the users of this node to the work list so that they
1536 // can be tried again once they have new operands.
1537 AddUsersToWorklist(N);
1539 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1540 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1541 } while (!N->use_empty());
1542 deleteAndRecombine(N);
1543 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1546 SDValue DAGCombiner::visitADD(SDNode *N) {
1547 SDValue N0 = N->getOperand(0);
1548 SDValue N1 = N->getOperand(1);
1549 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1550 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1551 EVT VT = N0.getValueType();
1554 if (VT.isVector()) {
1555 SDValue FoldedVOp = SimplifyVBinOp(N);
1556 if (FoldedVOp.getNode()) return FoldedVOp;
1558 // fold (add x, 0) -> x, vector edition
1559 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1561 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1565 // fold (add x, undef) -> undef
1566 if (N0.getOpcode() == ISD::UNDEF)
1568 if (N1.getOpcode() == ISD::UNDEF)
1570 // fold (add c1, c2) -> c1+c2
1572 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1573 // canonicalize constant to RHS
1575 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
1576 // fold (add x, 0) -> x
1577 if (N1C && N1C->isNullValue())
1579 // fold (add Sym, c) -> Sym+c
1580 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1581 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1582 GA->getOpcode() == ISD::GlobalAddress)
1583 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1585 (uint64_t)N1C->getSExtValue());
1586 // fold ((c1-A)+c2) -> (c1+c2)-A
1587 if (N1C && N0.getOpcode() == ISD::SUB)
1588 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1589 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1590 DAG.getConstant(N1C->getAPIntValue()+
1591 N0C->getAPIntValue(), VT),
1594 SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1);
1597 // fold ((0-A) + B) -> B-A
1598 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1599 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1600 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1));
1601 // fold (A + (0-B)) -> A-B
1602 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1603 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1604 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1));
1605 // fold (A+(B-A)) -> B
1606 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1607 return N1.getOperand(0);
1608 // fold ((B-A)+A) -> B
1609 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1610 return N0.getOperand(0);
1611 // fold (A+(B-(A+C))) to (B-C)
1612 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1613 N0 == N1.getOperand(1).getOperand(0))
1614 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1615 N1.getOperand(1).getOperand(1));
1616 // fold (A+(B-(C+A))) to (B-C)
1617 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1618 N0 == N1.getOperand(1).getOperand(1))
1619 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1620 N1.getOperand(1).getOperand(0));
1621 // fold (A+((B-A)+or-C)) to (B+or-C)
1622 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1623 N1.getOperand(0).getOpcode() == ISD::SUB &&
1624 N0 == N1.getOperand(0).getOperand(1))
1625 return DAG.getNode(N1.getOpcode(), SDLoc(N), VT,
1626 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1628 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1629 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1630 SDValue N00 = N0.getOperand(0);
1631 SDValue N01 = N0.getOperand(1);
1632 SDValue N10 = N1.getOperand(0);
1633 SDValue N11 = N1.getOperand(1);
1635 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1636 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1637 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
1638 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
1641 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1642 return SDValue(N, 0);
1644 // fold (a+b) -> (a|b) iff a and b share no bits.
1645 if (VT.isInteger() && !VT.isVector()) {
1646 APInt LHSZero, LHSOne;
1647 APInt RHSZero, RHSOne;
1648 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1650 if (LHSZero.getBoolValue()) {
1651 DAG.computeKnownBits(N1, RHSZero, RHSOne);
1653 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1654 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1655 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero){
1656 if (!LegalOperations || TLI.isOperationLegal(ISD::OR, VT))
1657 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
1662 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1663 if (N1.getOpcode() == ISD::SHL &&
1664 N1.getOperand(0).getOpcode() == ISD::SUB)
1665 if (ConstantSDNode *C =
1666 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1667 if (C->getAPIntValue() == 0)
1668 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0,
1669 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1670 N1.getOperand(0).getOperand(1),
1672 if (N0.getOpcode() == ISD::SHL &&
1673 N0.getOperand(0).getOpcode() == ISD::SUB)
1674 if (ConstantSDNode *C =
1675 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1676 if (C->getAPIntValue() == 0)
1677 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1,
1678 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1679 N0.getOperand(0).getOperand(1),
1682 if (N1.getOpcode() == ISD::AND) {
1683 SDValue AndOp0 = N1.getOperand(0);
1684 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1685 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1686 unsigned DestBits = VT.getScalarType().getSizeInBits();
1688 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1689 // and similar xforms where the inner op is either ~0 or 0.
1690 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1692 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1696 // add (sext i1), X -> sub X, (zext i1)
1697 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1698 N0.getOperand(0).getValueType() == MVT::i1 &&
1699 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1701 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1702 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1705 // add X, (sextinreg Y i1) -> sub X, (and Y 1)
1706 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
1707 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
1708 if (TN->getVT() == MVT::i1) {
1710 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
1711 DAG.getConstant(1, VT));
1712 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
1719 SDValue DAGCombiner::visitADDC(SDNode *N) {
1720 SDValue N0 = N->getOperand(0);
1721 SDValue N1 = N->getOperand(1);
1722 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1723 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1724 EVT VT = N0.getValueType();
1726 // If the flag result is dead, turn this into an ADD.
1727 if (!N->hasAnyUseOfValue(1))
1728 return CombineTo(N, DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1),
1729 DAG.getNode(ISD::CARRY_FALSE,
1730 SDLoc(N), MVT::Glue));
1732 // canonicalize constant to RHS.
1734 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
1736 // fold (addc x, 0) -> x + no carry out
1737 if (N1C && N1C->isNullValue())
1738 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1739 SDLoc(N), MVT::Glue));
1741 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1742 APInt LHSZero, LHSOne;
1743 APInt RHSZero, RHSOne;
1744 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1746 if (LHSZero.getBoolValue()) {
1747 DAG.computeKnownBits(N1, RHSZero, RHSOne);
1749 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1750 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1751 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1752 return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1),
1753 DAG.getNode(ISD::CARRY_FALSE,
1754 SDLoc(N), MVT::Glue));
1760 SDValue DAGCombiner::visitADDE(SDNode *N) {
1761 SDValue N0 = N->getOperand(0);
1762 SDValue N1 = N->getOperand(1);
1763 SDValue CarryIn = N->getOperand(2);
1764 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1765 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1767 // canonicalize constant to RHS
1769 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
1772 // fold (adde x, y, false) -> (addc x, y)
1773 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1774 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
1779 // Since it may not be valid to emit a fold to zero for vector initializers
1780 // check if we can before folding.
1781 static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT,
1783 bool LegalOperations, bool LegalTypes) {
1785 return DAG.getConstant(0, VT);
1786 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
1787 return DAG.getConstant(0, VT);
1791 SDValue DAGCombiner::visitSUB(SDNode *N) {
1792 SDValue N0 = N->getOperand(0);
1793 SDValue N1 = N->getOperand(1);
1794 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1795 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1796 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? nullptr :
1797 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1798 EVT VT = N0.getValueType();
1801 if (VT.isVector()) {
1802 SDValue FoldedVOp = SimplifyVBinOp(N);
1803 if (FoldedVOp.getNode()) return FoldedVOp;
1805 // fold (sub x, 0) -> x, vector edition
1806 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1810 // fold (sub x, x) -> 0
1811 // FIXME: Refactor this and xor and other similar operations together.
1813 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
1814 // fold (sub c1, c2) -> c1-c2
1816 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1817 // fold (sub x, c) -> (add x, -c)
1819 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0,
1820 DAG.getConstant(-N1C->getAPIntValue(), VT));
1821 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1822 if (N0C && N0C->isAllOnesValue())
1823 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
1824 // fold A-(A-B) -> B
1825 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1826 return N1.getOperand(1);
1827 // fold (A+B)-A -> B
1828 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1829 return N0.getOperand(1);
1830 // fold (A+B)-B -> A
1831 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1832 return N0.getOperand(0);
1833 // fold C2-(A+C1) -> (C2-C1)-A
1834 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1835 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
1837 return DAG.getNode(ISD::SUB, SDLoc(N), VT, NewC,
1840 // fold ((A+(B+or-C))-B) -> A+or-C
1841 if (N0.getOpcode() == ISD::ADD &&
1842 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1843 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1844 N0.getOperand(1).getOperand(0) == N1)
1845 return DAG.getNode(N0.getOperand(1).getOpcode(), SDLoc(N), VT,
1846 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1847 // fold ((A+(C+B))-B) -> A+C
1848 if (N0.getOpcode() == ISD::ADD &&
1849 N0.getOperand(1).getOpcode() == ISD::ADD &&
1850 N0.getOperand(1).getOperand(1) == N1)
1851 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
1852 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1853 // fold ((A-(B-C))-C) -> A-B
1854 if (N0.getOpcode() == ISD::SUB &&
1855 N0.getOperand(1).getOpcode() == ISD::SUB &&
1856 N0.getOperand(1).getOperand(1) == N1)
1857 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1858 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1860 // If either operand of a sub is undef, the result is undef
1861 if (N0.getOpcode() == ISD::UNDEF)
1863 if (N1.getOpcode() == ISD::UNDEF)
1866 // If the relocation model supports it, consider symbol offsets.
1867 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1868 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1869 // fold (sub Sym, c) -> Sym-c
1870 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1871 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1873 (uint64_t)N1C->getSExtValue());
1874 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1875 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1876 if (GA->getGlobal() == GB->getGlobal())
1877 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1881 // sub X, (sextinreg Y i1) -> add X, (and Y 1)
1882 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
1883 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
1884 if (TN->getVT() == MVT::i1) {
1886 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
1887 DAG.getConstant(1, VT));
1888 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
1895 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1896 SDValue N0 = N->getOperand(0);
1897 SDValue N1 = N->getOperand(1);
1898 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1899 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1900 EVT VT = N0.getValueType();
1902 // If the flag result is dead, turn this into an SUB.
1903 if (!N->hasAnyUseOfValue(1))
1904 return CombineTo(N, DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1),
1905 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1908 // fold (subc x, x) -> 0 + no borrow
1910 return CombineTo(N, DAG.getConstant(0, VT),
1911 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1914 // fold (subc x, 0) -> x + no borrow
1915 if (N1C && N1C->isNullValue())
1916 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1919 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1920 if (N0C && N0C->isAllOnesValue())
1921 return CombineTo(N, DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0),
1922 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1928 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1929 SDValue N0 = N->getOperand(0);
1930 SDValue N1 = N->getOperand(1);
1931 SDValue CarryIn = N->getOperand(2);
1933 // fold (sube x, y, false) -> (subc x, y)
1934 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1935 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
1940 SDValue DAGCombiner::visitMUL(SDNode *N) {
1941 SDValue N0 = N->getOperand(0);
1942 SDValue N1 = N->getOperand(1);
1943 EVT VT = N0.getValueType();
1945 // fold (mul x, undef) -> 0
1946 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1947 return DAG.getConstant(0, VT);
1949 bool N0IsConst = false;
1950 bool N1IsConst = false;
1951 APInt ConstValue0, ConstValue1;
1953 if (VT.isVector()) {
1954 SDValue FoldedVOp = SimplifyVBinOp(N);
1955 if (FoldedVOp.getNode()) return FoldedVOp;
1957 N0IsConst = isConstantSplatVector(N0.getNode(), ConstValue0);
1958 N1IsConst = isConstantSplatVector(N1.getNode(), ConstValue1);
1960 N0IsConst = dyn_cast<ConstantSDNode>(N0) != nullptr;
1961 ConstValue0 = N0IsConst ? (dyn_cast<ConstantSDNode>(N0))->getAPIntValue()
1963 N1IsConst = dyn_cast<ConstantSDNode>(N1) != nullptr;
1964 ConstValue1 = N1IsConst ? (dyn_cast<ConstantSDNode>(N1))->getAPIntValue()
1968 // fold (mul c1, c2) -> c1*c2
1969 if (N0IsConst && N1IsConst)
1970 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0.getNode(), N1.getNode());
1972 // canonicalize constant to RHS
1973 if (N0IsConst && !N1IsConst)
1974 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
1975 // fold (mul x, 0) -> 0
1976 if (N1IsConst && ConstValue1 == 0)
1978 // We require a splat of the entire scalar bit width for non-contiguous
1981 ConstValue1.getBitWidth() == VT.getScalarType().getSizeInBits();
1982 // fold (mul x, 1) -> x
1983 if (N1IsConst && ConstValue1 == 1 && IsFullSplat)
1985 // fold (mul x, -1) -> 0-x
1986 if (N1IsConst && ConstValue1.isAllOnesValue())
1987 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1988 DAG.getConstant(0, VT), N0);
1989 // fold (mul x, (1 << c)) -> x << c
1990 if (N1IsConst && ConstValue1.isPowerOf2() && IsFullSplat)
1991 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1992 DAG.getConstant(ConstValue1.logBase2(),
1993 getShiftAmountTy(N0.getValueType())));
1994 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1995 if (N1IsConst && (-ConstValue1).isPowerOf2() && IsFullSplat) {
1996 unsigned Log2Val = (-ConstValue1).logBase2();
1997 // FIXME: If the input is something that is easily negated (e.g. a
1998 // single-use add), we should put the negate there.
1999 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
2000 DAG.getConstant(0, VT),
2001 DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
2002 DAG.getConstant(Log2Val,
2003 getShiftAmountTy(N0.getValueType()))));
2007 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
2008 if (N1IsConst && N0.getOpcode() == ISD::SHL &&
2009 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2010 isa<ConstantSDNode>(N0.getOperand(1)))) {
2011 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT,
2012 N1, N0.getOperand(1));
2013 AddToWorklist(C3.getNode());
2014 return DAG.getNode(ISD::MUL, SDLoc(N), VT,
2015 N0.getOperand(0), C3);
2018 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
2021 SDValue Sh(nullptr,0), Y(nullptr,0);
2022 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
2023 if (N0.getOpcode() == ISD::SHL &&
2024 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2025 isa<ConstantSDNode>(N0.getOperand(1))) &&
2026 N0.getNode()->hasOneUse()) {
2028 } else if (N1.getOpcode() == ISD::SHL &&
2029 isa<ConstantSDNode>(N1.getOperand(1)) &&
2030 N1.getNode()->hasOneUse()) {
2035 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2036 Sh.getOperand(0), Y);
2037 return DAG.getNode(ISD::SHL, SDLoc(N), VT,
2038 Mul, Sh.getOperand(1));
2042 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
2043 if (N1IsConst && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
2044 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2045 isa<ConstantSDNode>(N0.getOperand(1))))
2046 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
2047 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
2048 N0.getOperand(0), N1),
2049 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
2050 N0.getOperand(1), N1));
2053 SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1);
2060 SDValue DAGCombiner::visitSDIV(SDNode *N) {
2061 SDValue N0 = N->getOperand(0);
2062 SDValue N1 = N->getOperand(1);
2063 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2064 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2065 EVT VT = N->getValueType(0);
2068 if (VT.isVector()) {
2069 SDValue FoldedVOp = SimplifyVBinOp(N);
2070 if (FoldedVOp.getNode()) return FoldedVOp;
2073 // fold (sdiv c1, c2) -> c1/c2
2074 if (N0C && N1C && !N1C->isNullValue())
2075 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
2076 // fold (sdiv X, 1) -> X
2077 if (N1C && N1C->getAPIntValue() == 1LL)
2079 // fold (sdiv X, -1) -> 0-X
2080 if (N1C && N1C->isAllOnesValue())
2081 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
2082 DAG.getConstant(0, VT), N0);
2083 // If we know the sign bits of both operands are zero, strength reduce to a
2084 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
2085 if (!VT.isVector()) {
2086 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2087 return DAG.getNode(ISD::UDIV, SDLoc(N), N1.getValueType(),
2091 // fold (sdiv X, pow2) -> simple ops after legalize
2092 if (N1C && !N1C->isNullValue() && (N1C->getAPIntValue().isPowerOf2() ||
2093 (-N1C->getAPIntValue()).isPowerOf2())) {
2094 // If dividing by powers of two is cheap, then don't perform the following
2096 if (TLI.isPow2SDivCheap())
2099 // Target-specific implementation of sdiv x, pow2.
2100 SDValue Res = BuildSDIVPow2(N);
2104 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
2106 // Splat the sign bit into the register
2108 DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
2109 DAG.getConstant(VT.getScalarSizeInBits() - 1,
2110 getShiftAmountTy(N0.getValueType())));
2111 AddToWorklist(SGN.getNode());
2113 // Add (N0 < 0) ? abs2 - 1 : 0;
2115 DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN,
2116 DAG.getConstant(VT.getScalarSizeInBits() - lg2,
2117 getShiftAmountTy(SGN.getValueType())));
2118 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL);
2119 AddToWorklist(SRL.getNode());
2120 AddToWorklist(ADD.getNode()); // Divide by pow2
2121 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), VT, ADD,
2122 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
2124 // If we're dividing by a positive value, we're done. Otherwise, we must
2125 // negate the result.
2126 if (N1C->getAPIntValue().isNonNegative())
2129 AddToWorklist(SRA.getNode());
2130 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), SRA);
2133 // if integer divide is expensive and we satisfy the requirements, emit an
2134 // alternate sequence.
2135 if (N1C && !TLI.isIntDivCheap()) {
2136 SDValue Op = BuildSDIV(N);
2137 if (Op.getNode()) return Op;
2141 if (N0.getOpcode() == ISD::UNDEF)
2142 return DAG.getConstant(0, VT);
2143 // X / undef -> undef
2144 if (N1.getOpcode() == ISD::UNDEF)
2150 SDValue DAGCombiner::visitUDIV(SDNode *N) {
2151 SDValue N0 = N->getOperand(0);
2152 SDValue N1 = N->getOperand(1);
2153 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2154 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2155 EVT VT = N->getValueType(0);
2158 if (VT.isVector()) {
2159 SDValue FoldedVOp = SimplifyVBinOp(N);
2160 if (FoldedVOp.getNode()) return FoldedVOp;
2163 // fold (udiv c1, c2) -> c1/c2
2164 if (N0C && N1C && !N1C->isNullValue())
2165 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
2166 // fold (udiv x, (1 << c)) -> x >>u c
2167 if (N1C && N1C->getAPIntValue().isPowerOf2())
2168 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
2169 DAG.getConstant(N1C->getAPIntValue().logBase2(),
2170 getShiftAmountTy(N0.getValueType())));
2171 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
2172 if (N1.getOpcode() == ISD::SHL) {
2173 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2174 if (SHC->getAPIntValue().isPowerOf2()) {
2175 EVT ADDVT = N1.getOperand(1).getValueType();
2176 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N), ADDVT,
2178 DAG.getConstant(SHC->getAPIntValue()
2181 AddToWorklist(Add.getNode());
2182 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add);
2186 // fold (udiv x, c) -> alternate
2187 if (N1C && !TLI.isIntDivCheap()) {
2188 SDValue Op = BuildUDIV(N);
2189 if (Op.getNode()) return Op;
2193 if (N0.getOpcode() == ISD::UNDEF)
2194 return DAG.getConstant(0, VT);
2195 // X / undef -> undef
2196 if (N1.getOpcode() == ISD::UNDEF)
2202 SDValue DAGCombiner::visitSREM(SDNode *N) {
2203 SDValue N0 = N->getOperand(0);
2204 SDValue N1 = N->getOperand(1);
2205 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2206 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2207 EVT VT = N->getValueType(0);
2209 // fold (srem c1, c2) -> c1%c2
2210 if (N0C && N1C && !N1C->isNullValue())
2211 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
2212 // If we know the sign bits of both operands are zero, strength reduce to a
2213 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
2214 if (!VT.isVector()) {
2215 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2216 return DAG.getNode(ISD::UREM, SDLoc(N), VT, N0, N1);
2219 // If X/C can be simplified by the division-by-constant logic, lower
2220 // X%C to the equivalent of X-X/C*C.
2221 if (N1C && !N1C->isNullValue()) {
2222 SDValue Div = DAG.getNode(ISD::SDIV, SDLoc(N), VT, N0, N1);
2223 AddToWorklist(Div.getNode());
2224 SDValue OptimizedDiv = combine(Div.getNode());
2225 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2226 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2228 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2229 AddToWorklist(Mul.getNode());
2235 if (N0.getOpcode() == ISD::UNDEF)
2236 return DAG.getConstant(0, VT);
2237 // X % undef -> undef
2238 if (N1.getOpcode() == ISD::UNDEF)
2244 SDValue DAGCombiner::visitUREM(SDNode *N) {
2245 SDValue N0 = N->getOperand(0);
2246 SDValue N1 = N->getOperand(1);
2247 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2248 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2249 EVT VT = N->getValueType(0);
2251 // fold (urem c1, c2) -> c1%c2
2252 if (N0C && N1C && !N1C->isNullValue())
2253 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2254 // fold (urem x, pow2) -> (and x, pow2-1)
2255 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2256 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0,
2257 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2258 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2259 if (N1.getOpcode() == ISD::SHL) {
2260 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2261 if (SHC->getAPIntValue().isPowerOf2()) {
2263 DAG.getNode(ISD::ADD, SDLoc(N), VT, N1,
2264 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2266 AddToWorklist(Add.getNode());
2267 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, Add);
2272 // If X/C can be simplified by the division-by-constant logic, lower
2273 // X%C to the equivalent of X-X/C*C.
2274 if (N1C && !N1C->isNullValue()) {
2275 SDValue Div = DAG.getNode(ISD::UDIV, SDLoc(N), VT, N0, N1);
2276 AddToWorklist(Div.getNode());
2277 SDValue OptimizedDiv = combine(Div.getNode());
2278 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2279 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2281 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2282 AddToWorklist(Mul.getNode());
2288 if (N0.getOpcode() == ISD::UNDEF)
2289 return DAG.getConstant(0, VT);
2290 // X % undef -> undef
2291 if (N1.getOpcode() == ISD::UNDEF)
2297 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2298 SDValue N0 = N->getOperand(0);
2299 SDValue N1 = N->getOperand(1);
2300 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2301 EVT VT = N->getValueType(0);
2304 // fold (mulhs x, 0) -> 0
2305 if (N1C && N1C->isNullValue())
2307 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2308 if (N1C && N1C->getAPIntValue() == 1)
2309 return DAG.getNode(ISD::SRA, SDLoc(N), N0.getValueType(), N0,
2310 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2311 getShiftAmountTy(N0.getValueType())));
2312 // fold (mulhs x, undef) -> 0
2313 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2314 return DAG.getConstant(0, VT);
2316 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2318 if (VT.isSimple() && !VT.isVector()) {
2319 MVT Simple = VT.getSimpleVT();
2320 unsigned SimpleSize = Simple.getSizeInBits();
2321 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2322 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2323 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2324 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2325 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2326 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2327 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2328 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2335 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2336 SDValue N0 = N->getOperand(0);
2337 SDValue N1 = N->getOperand(1);
2338 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2339 EVT VT = N->getValueType(0);
2342 // fold (mulhu x, 0) -> 0
2343 if (N1C && N1C->isNullValue())
2345 // fold (mulhu x, 1) -> 0
2346 if (N1C && N1C->getAPIntValue() == 1)
2347 return DAG.getConstant(0, N0.getValueType());
2348 // fold (mulhu x, undef) -> 0
2349 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2350 return DAG.getConstant(0, VT);
2352 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2354 if (VT.isSimple() && !VT.isVector()) {
2355 MVT Simple = VT.getSimpleVT();
2356 unsigned SimpleSize = Simple.getSizeInBits();
2357 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2358 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2359 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2360 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2361 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2362 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2363 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2364 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2371 /// Perform optimizations common to nodes that compute two values. LoOp and HiOp
2372 /// give the opcodes for the two computations that are being performed. Return
2373 /// true if a simplification was made.
2374 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2376 // If the high half is not needed, just compute the low half.
2377 bool HiExists = N->hasAnyUseOfValue(1);
2379 (!LegalOperations ||
2380 TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) {
2381 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
2382 return CombineTo(N, Res, Res);
2385 // If the low half is not needed, just compute the high half.
2386 bool LoExists = N->hasAnyUseOfValue(0);
2388 (!LegalOperations ||
2389 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2390 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
2391 return CombineTo(N, Res, Res);
2394 // If both halves are used, return as it is.
2395 if (LoExists && HiExists)
2398 // If the two computed results can be simplified separately, separate them.
2400 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
2401 AddToWorklist(Lo.getNode());
2402 SDValue LoOpt = combine(Lo.getNode());
2403 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2404 (!LegalOperations ||
2405 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2406 return CombineTo(N, LoOpt, LoOpt);
2410 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
2411 AddToWorklist(Hi.getNode());
2412 SDValue HiOpt = combine(Hi.getNode());
2413 if (HiOpt.getNode() && HiOpt != Hi &&
2414 (!LegalOperations ||
2415 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2416 return CombineTo(N, HiOpt, HiOpt);
2422 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2423 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2424 if (Res.getNode()) return Res;
2426 EVT VT = N->getValueType(0);
2429 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2431 if (VT.isSimple() && !VT.isVector()) {
2432 MVT Simple = VT.getSimpleVT();
2433 unsigned SimpleSize = Simple.getSizeInBits();
2434 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2435 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2436 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2437 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2438 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2439 // Compute the high part as N1.
2440 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2441 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2442 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2443 // Compute the low part as N0.
2444 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2445 return CombineTo(N, Lo, Hi);
2452 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2453 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2454 if (Res.getNode()) return Res;
2456 EVT VT = N->getValueType(0);
2459 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2461 if (VT.isSimple() && !VT.isVector()) {
2462 MVT Simple = VT.getSimpleVT();
2463 unsigned SimpleSize = Simple.getSizeInBits();
2464 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2465 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2466 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2467 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2468 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2469 // Compute the high part as N1.
2470 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2471 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2472 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2473 // Compute the low part as N0.
2474 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2475 return CombineTo(N, Lo, Hi);
2482 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2483 // (smulo x, 2) -> (saddo x, x)
2484 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2485 if (C2->getAPIntValue() == 2)
2486 return DAG.getNode(ISD::SADDO, SDLoc(N), N->getVTList(),
2487 N->getOperand(0), N->getOperand(0));
2492 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2493 // (umulo x, 2) -> (uaddo x, x)
2494 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2495 if (C2->getAPIntValue() == 2)
2496 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(),
2497 N->getOperand(0), N->getOperand(0));
2502 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2503 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2504 if (Res.getNode()) return Res;
2509 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2510 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2511 if (Res.getNode()) return Res;
2516 /// If this is a binary operator with two operands of the same opcode, try to
2518 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2519 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2520 EVT VT = N0.getValueType();
2521 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2523 // Bail early if none of these transforms apply.
2524 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2526 // For each of OP in AND/OR/XOR:
2527 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2528 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2529 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2530 // fold (OP (bswap x), (bswap y)) -> (bswap (OP x, y))
2531 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2533 // do not sink logical op inside of a vector extend, since it may combine
2535 EVT Op0VT = N0.getOperand(0).getValueType();
2536 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2537 N0.getOpcode() == ISD::SIGN_EXTEND ||
2538 N0.getOpcode() == ISD::BSWAP ||
2539 // Avoid infinite looping with PromoteIntBinOp.
2540 (N0.getOpcode() == ISD::ANY_EXTEND &&
2541 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2542 (N0.getOpcode() == ISD::TRUNCATE &&
2543 (!TLI.isZExtFree(VT, Op0VT) ||
2544 !TLI.isTruncateFree(Op0VT, VT)) &&
2545 TLI.isTypeLegal(Op0VT))) &&
2547 Op0VT == N1.getOperand(0).getValueType() &&
2548 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2549 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2550 N0.getOperand(0).getValueType(),
2551 N0.getOperand(0), N1.getOperand(0));
2552 AddToWorklist(ORNode.getNode());
2553 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode);
2556 // For each of OP in SHL/SRL/SRA/AND...
2557 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2558 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2559 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2560 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2561 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2562 N0.getOperand(1) == N1.getOperand(1)) {
2563 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2564 N0.getOperand(0).getValueType(),
2565 N0.getOperand(0), N1.getOperand(0));
2566 AddToWorklist(ORNode.getNode());
2567 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
2568 ORNode, N0.getOperand(1));
2571 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2572 // Only perform this optimization after type legalization and before
2573 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2574 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2575 // we don't want to undo this promotion.
2576 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2578 if ((N0.getOpcode() == ISD::BITCAST ||
2579 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2580 Level == AfterLegalizeTypes) {
2581 SDValue In0 = N0.getOperand(0);
2582 SDValue In1 = N1.getOperand(0);
2583 EVT In0Ty = In0.getValueType();
2584 EVT In1Ty = In1.getValueType();
2586 // If both incoming values are integers, and the original types are the
2588 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2589 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2590 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2591 AddToWorklist(Op.getNode());
2596 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2597 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2598 // If both shuffles use the same mask, and both shuffle within a single
2599 // vector, then it is worthwhile to move the swizzle after the operation.
2600 // The type-legalizer generates this pattern when loading illegal
2601 // vector types from memory. In many cases this allows additional shuffle
2603 // There are other cases where moving the shuffle after the xor/and/or
2604 // is profitable even if shuffles don't perform a swizzle.
2605 // If both shuffles use the same mask, and both shuffles have the same first
2606 // or second operand, then it might still be profitable to move the shuffle
2607 // after the xor/and/or operation.
2608 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
2609 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2610 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2612 assert(N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() &&
2613 "Inputs to shuffles are not the same type");
2615 // Check that both shuffles use the same mask. The masks are known to be of
2616 // the same length because the result vector type is the same.
2617 // Check also that shuffles have only one use to avoid introducing extra
2619 if (SVN0->hasOneUse() && SVN1->hasOneUse() &&
2620 SVN0->getMask().equals(SVN1->getMask())) {
2621 SDValue ShOp = N0->getOperand(1);
2623 // Don't try to fold this node if it requires introducing a
2624 // build vector of all zeros that might be illegal at this stage.
2625 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2627 ShOp = DAG.getConstant(0, VT);
2632 // (AND (shuf (A, C), shuf (B, C)) -> shuf (AND (A, B), C)
2633 // (OR (shuf (A, C), shuf (B, C)) -> shuf (OR (A, B), C)
2634 // (XOR (shuf (A, C), shuf (B, C)) -> shuf (XOR (A, B), V_0)
2635 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
2636 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2637 N0->getOperand(0), N1->getOperand(0));
2638 AddToWorklist(NewNode.getNode());
2639 return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp,
2640 &SVN0->getMask()[0]);
2643 // Don't try to fold this node if it requires introducing a
2644 // build vector of all zeros that might be illegal at this stage.
2645 ShOp = N0->getOperand(0);
2646 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2648 ShOp = DAG.getConstant(0, VT);
2653 // (AND (shuf (C, A), shuf (C, B)) -> shuf (C, AND (A, B))
2654 // (OR (shuf (C, A), shuf (C, B)) -> shuf (C, OR (A, B))
2655 // (XOR (shuf (C, A), shuf (C, B)) -> shuf (V_0, XOR (A, B))
2656 if (N0->getOperand(0) == N1->getOperand(0) && ShOp.getNode()) {
2657 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2658 N0->getOperand(1), N1->getOperand(1));
2659 AddToWorklist(NewNode.getNode());
2660 return DAG.getVectorShuffle(VT, SDLoc(N), ShOp, NewNode,
2661 &SVN0->getMask()[0]);
2669 SDValue DAGCombiner::visitAND(SDNode *N) {
2670 SDValue N0 = N->getOperand(0);
2671 SDValue N1 = N->getOperand(1);
2672 SDValue LL, LR, RL, RR, CC0, CC1;
2673 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2674 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2675 EVT VT = N1.getValueType();
2676 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2679 if (VT.isVector()) {
2680 SDValue FoldedVOp = SimplifyVBinOp(N);
2681 if (FoldedVOp.getNode()) return FoldedVOp;
2683 // fold (and x, 0) -> 0, vector edition
2684 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2685 // do not return N0, because undef node may exist in N0
2686 return DAG.getConstant(
2687 APInt::getNullValue(
2688 N0.getValueType().getScalarType().getSizeInBits()),
2690 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2691 // do not return N1, because undef node may exist in N1
2692 return DAG.getConstant(
2693 APInt::getNullValue(
2694 N1.getValueType().getScalarType().getSizeInBits()),
2697 // fold (and x, -1) -> x, vector edition
2698 if (ISD::isBuildVectorAllOnes(N0.getNode()))
2700 if (ISD::isBuildVectorAllOnes(N1.getNode()))
2704 // fold (and x, undef) -> 0
2705 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2706 return DAG.getConstant(0, VT);
2707 // fold (and c1, c2) -> c1&c2
2709 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2710 // canonicalize constant to RHS
2712 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
2713 // fold (and x, -1) -> x
2714 if (N1C && N1C->isAllOnesValue())
2716 // if (and x, c) is known to be zero, return 0
2717 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2718 APInt::getAllOnesValue(BitWidth)))
2719 return DAG.getConstant(0, VT);
2721 SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1);
2724 // fold (and (or x, C), D) -> D if (C & D) == D
2725 if (N1C && N0.getOpcode() == ISD::OR)
2726 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2727 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2729 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2730 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2731 SDValue N0Op0 = N0.getOperand(0);
2732 APInt Mask = ~N1C->getAPIntValue();
2733 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2734 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2735 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
2736 N0.getValueType(), N0Op0);
2738 // Replace uses of the AND with uses of the Zero extend node.
2741 // We actually want to replace all uses of the any_extend with the
2742 // zero_extend, to avoid duplicating things. This will later cause this
2743 // AND to be folded.
2744 CombineTo(N0.getNode(), Zext);
2745 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2748 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2749 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2750 // already be zero by virtue of the width of the base type of the load.
2752 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2754 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2755 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2756 N0.getOpcode() == ISD::LOAD) {
2757 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2758 N0 : N0.getOperand(0) );
2760 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2761 // This can be a pure constant or a vector splat, in which case we treat the
2762 // vector as a scalar and use the splat value.
2763 APInt Constant = APInt::getNullValue(1);
2764 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2765 Constant = C->getAPIntValue();
2766 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2767 APInt SplatValue, SplatUndef;
2768 unsigned SplatBitSize;
2770 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2771 SplatBitSize, HasAnyUndefs);
2773 // Undef bits can contribute to a possible optimisation if set, so
2775 SplatValue |= SplatUndef;
2777 // The splat value may be something like "0x00FFFFFF", which means 0 for
2778 // the first vector value and FF for the rest, repeating. We need a mask
2779 // that will apply equally to all members of the vector, so AND all the
2780 // lanes of the constant together.
2781 EVT VT = Vector->getValueType(0);
2782 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2784 // If the splat value has been compressed to a bitlength lower
2785 // than the size of the vector lane, we need to re-expand it to
2787 if (BitWidth > SplatBitSize)
2788 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
2789 SplatBitSize < BitWidth;
2790 SplatBitSize = SplatBitSize * 2)
2791 SplatValue |= SplatValue.shl(SplatBitSize);
2793 Constant = APInt::getAllOnesValue(BitWidth);
2794 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
2795 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2799 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2800 // actually legal and isn't going to get expanded, else this is a false
2802 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2803 Load->getMemoryVT());
2805 // Resize the constant to the same size as the original memory access before
2806 // extension. If it is still the AllOnesValue then this AND is completely
2809 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2812 switch (Load->getExtensionType()) {
2813 default: B = false; break;
2814 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2816 case ISD::NON_EXTLOAD: B = true; break;
2819 if (B && Constant.isAllOnesValue()) {
2820 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2821 // preserve semantics once we get rid of the AND.
2822 SDValue NewLoad(Load, 0);
2823 if (Load->getExtensionType() == ISD::EXTLOAD) {
2824 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2825 Load->getValueType(0), SDLoc(Load),
2826 Load->getChain(), Load->getBasePtr(),
2827 Load->getOffset(), Load->getMemoryVT(),
2828 Load->getMemOperand());
2829 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2830 if (Load->getNumValues() == 3) {
2831 // PRE/POST_INC loads have 3 values.
2832 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
2833 NewLoad.getValue(2) };
2834 CombineTo(Load, To, 3, true);
2836 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2840 // Fold the AND away, taking care not to fold to the old load node if we
2842 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2844 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2847 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2848 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2849 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2850 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2852 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2853 LL.getValueType().isInteger()) {
2854 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2855 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2856 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2857 LR.getValueType(), LL, RL);
2858 AddToWorklist(ORNode.getNode());
2859 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
2861 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2862 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2863 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0),
2864 LR.getValueType(), LL, RL);
2865 AddToWorklist(ANDNode.getNode());
2866 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
2868 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2869 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2870 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2871 LR.getValueType(), LL, RL);
2872 AddToWorklist(ORNode.getNode());
2873 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
2876 // Simplify (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
2877 if (LL == RL && isa<ConstantSDNode>(LR) && isa<ConstantSDNode>(RR) &&
2878 Op0 == Op1 && LL.getValueType().isInteger() &&
2879 Op0 == ISD::SETNE && ((cast<ConstantSDNode>(LR)->isNullValue() &&
2880 cast<ConstantSDNode>(RR)->isAllOnesValue()) ||
2881 (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2882 cast<ConstantSDNode>(RR)->isNullValue()))) {
2883 SDValue ADDNode = DAG.getNode(ISD::ADD, SDLoc(N0), LL.getValueType(),
2884 LL, DAG.getConstant(1, LL.getValueType()));
2885 AddToWorklist(ADDNode.getNode());
2886 return DAG.getSetCC(SDLoc(N), VT, ADDNode,
2887 DAG.getConstant(2, LL.getValueType()), ISD::SETUGE);
2889 // canonicalize equivalent to ll == rl
2890 if (LL == RR && LR == RL) {
2891 Op1 = ISD::getSetCCSwappedOperands(Op1);
2894 if (LL == RL && LR == RR) {
2895 bool isInteger = LL.getValueType().isInteger();
2896 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2897 if (Result != ISD::SETCC_INVALID &&
2898 (!LegalOperations ||
2899 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
2900 TLI.isOperationLegal(ISD::SETCC,
2901 getSetCCResultType(N0.getSimpleValueType())))))
2902 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
2907 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2908 if (N0.getOpcode() == N1.getOpcode()) {
2909 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2910 if (Tmp.getNode()) return Tmp;
2913 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2914 // fold (and (sra)) -> (and (srl)) when possible.
2915 if (!VT.isVector() &&
2916 SimplifyDemandedBits(SDValue(N, 0)))
2917 return SDValue(N, 0);
2919 // fold (zext_inreg (extload x)) -> (zextload x)
2920 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2921 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2922 EVT MemVT = LN0->getMemoryVT();
2923 // If we zero all the possible extended bits, then we can turn this into
2924 // a zextload if we are running before legalize or the operation is legal.
2925 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2926 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2927 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2928 ((!LegalOperations && !LN0->isVolatile()) ||
2929 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2930 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2931 LN0->getChain(), LN0->getBasePtr(),
2932 MemVT, LN0->getMemOperand());
2934 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2935 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2938 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2939 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2941 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2942 EVT MemVT = LN0->getMemoryVT();
2943 // If we zero all the possible extended bits, then we can turn this into
2944 // a zextload if we are running before legalize or the operation is legal.
2945 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2946 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2947 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2948 ((!LegalOperations && !LN0->isVolatile()) ||
2949 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2950 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2951 LN0->getChain(), LN0->getBasePtr(),
2952 MemVT, LN0->getMemOperand());
2954 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2955 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2959 // fold (and (load x), 255) -> (zextload x, i8)
2960 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2961 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2962 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2963 (N0.getOpcode() == ISD::ANY_EXTEND &&
2964 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2965 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2966 LoadSDNode *LN0 = HasAnyExt
2967 ? cast<LoadSDNode>(N0.getOperand(0))
2968 : cast<LoadSDNode>(N0);
2969 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2970 LN0->isUnindexed() && N0.hasOneUse() && SDValue(LN0, 0).hasOneUse()) {
2971 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2972 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2973 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2974 EVT LoadedVT = LN0->getMemoryVT();
2976 if (ExtVT == LoadedVT &&
2977 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2978 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2981 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
2982 LN0->getChain(), LN0->getBasePtr(), ExtVT,
2983 LN0->getMemOperand());
2985 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2986 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2989 // Do not change the width of a volatile load.
2990 // Do not generate loads of non-round integer types since these can
2991 // be expensive (and would be wrong if the type is not byte sized).
2992 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2993 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2994 EVT PtrType = LN0->getOperand(1).getValueType();
2996 unsigned Alignment = LN0->getAlignment();
2997 SDValue NewPtr = LN0->getBasePtr();
2999 // For big endian targets, we need to add an offset to the pointer
3000 // to load the correct bytes. For little endian systems, we merely
3001 // need to read fewer bytes from the same pointer.
3002 if (TLI.isBigEndian()) {
3003 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
3004 unsigned EVTStoreBytes = ExtVT.getStoreSize();
3005 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
3006 NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0), PtrType,
3007 NewPtr, DAG.getConstant(PtrOff, PtrType));
3008 Alignment = MinAlign(Alignment, PtrOff);
3011 AddToWorklist(NewPtr.getNode());
3013 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
3015 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
3016 LN0->getChain(), NewPtr,
3017 LN0->getPointerInfo(),
3018 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
3019 LN0->isInvariant(), Alignment, LN0->getAAInfo());
3021 CombineTo(LN0, Load, Load.getValue(1));
3022 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3028 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
3029 VT.getSizeInBits() <= 64) {
3030 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3031 APInt ADDC = ADDI->getAPIntValue();
3032 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
3033 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
3034 // immediate for an add, but it is legal if its top c2 bits are set,
3035 // transform the ADD so the immediate doesn't need to be materialized
3037 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
3038 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3039 SRLI->getZExtValue());
3040 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
3042 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
3044 DAG.getNode(ISD::ADD, SDLoc(N0), VT,
3045 N0.getOperand(0), DAG.getConstant(ADDC, VT));
3046 CombineTo(N0.getNode(), NewAdd);
3047 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3055 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
3056 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
3057 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
3058 N0.getOperand(1), false);
3059 if (BSwap.getNode())
3066 /// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
3067 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
3068 bool DemandHighBits) {
3069 if (!LegalOperations)
3072 EVT VT = N->getValueType(0);
3073 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
3075 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3078 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
3079 bool LookPassAnd0 = false;
3080 bool LookPassAnd1 = false;
3081 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
3083 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
3085 if (N0.getOpcode() == ISD::AND) {
3086 if (!N0.getNode()->hasOneUse())
3088 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3089 if (!N01C || N01C->getZExtValue() != 0xFF00)
3091 N0 = N0.getOperand(0);
3092 LookPassAnd0 = true;
3095 if (N1.getOpcode() == ISD::AND) {
3096 if (!N1.getNode()->hasOneUse())
3098 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
3099 if (!N11C || N11C->getZExtValue() != 0xFF)
3101 N1 = N1.getOperand(0);
3102 LookPassAnd1 = true;
3105 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
3107 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
3109 if (!N0.getNode()->hasOneUse() ||
3110 !N1.getNode()->hasOneUse())
3113 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3114 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
3117 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
3120 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
3121 SDValue N00 = N0->getOperand(0);
3122 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
3123 if (!N00.getNode()->hasOneUse())
3125 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
3126 if (!N001C || N001C->getZExtValue() != 0xFF)
3128 N00 = N00.getOperand(0);
3129 LookPassAnd0 = true;
3132 SDValue N10 = N1->getOperand(0);
3133 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
3134 if (!N10.getNode()->hasOneUse())
3136 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
3137 if (!N101C || N101C->getZExtValue() != 0xFF00)
3139 N10 = N10.getOperand(0);
3140 LookPassAnd1 = true;
3146 // Make sure everything beyond the low halfword gets set to zero since the SRL
3147 // 16 will clear the top bits.
3148 unsigned OpSizeInBits = VT.getSizeInBits();
3149 if (DemandHighBits && OpSizeInBits > 16) {
3150 // If the left-shift isn't masked out then the only way this is a bswap is
3151 // if all bits beyond the low 8 are 0. In that case the entire pattern
3152 // reduces to a left shift anyway: leave it for other parts of the combiner.
3156 // However, if the right shift isn't masked out then it might be because
3157 // it's not needed. See if we can spot that too.
3158 if (!LookPassAnd1 &&
3159 !DAG.MaskedValueIsZero(
3160 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
3164 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
3165 if (OpSizeInBits > 16)
3166 Res = DAG.getNode(ISD::SRL, SDLoc(N), VT, Res,
3167 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
3171 /// Return true if the specified node is an element that makes up a 32-bit
3172 /// packed halfword byteswap.
3173 /// ((x & 0x000000ff) << 8) |
3174 /// ((x & 0x0000ff00) >> 8) |
3175 /// ((x & 0x00ff0000) << 8) |
3176 /// ((x & 0xff000000) >> 8)
3177 static bool isBSwapHWordElement(SDValue N, MutableArrayRef<SDNode *> Parts) {
3178 if (!N.getNode()->hasOneUse())
3181 unsigned Opc = N.getOpcode();
3182 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
3185 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3190 switch (N1C->getZExtValue()) {
3193 case 0xFF: Num = 0; break;
3194 case 0xFF00: Num = 1; break;
3195 case 0xFF0000: Num = 2; break;
3196 case 0xFF000000: Num = 3; break;
3199 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
3200 SDValue N0 = N.getOperand(0);
3201 if (Opc == ISD::AND) {
3202 if (Num == 0 || Num == 2) {
3204 // (x >> 8) & 0xff0000
3205 if (N0.getOpcode() != ISD::SRL)
3207 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3208 if (!C || C->getZExtValue() != 8)
3211 // (x << 8) & 0xff00
3212 // (x << 8) & 0xff000000
3213 if (N0.getOpcode() != ISD::SHL)
3215 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3216 if (!C || C->getZExtValue() != 8)
3219 } else if (Opc == ISD::SHL) {
3221 // (x & 0xff0000) << 8
3222 if (Num != 0 && Num != 2)
3224 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3225 if (!C || C->getZExtValue() != 8)
3227 } else { // Opc == ISD::SRL
3228 // (x & 0xff00) >> 8
3229 // (x & 0xff000000) >> 8
3230 if (Num != 1 && Num != 3)
3232 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3233 if (!C || C->getZExtValue() != 8)
3240 Parts[Num] = N0.getOperand(0).getNode();
3244 /// Match a 32-bit packed halfword bswap. That is
3245 /// ((x & 0x000000ff) << 8) |
3246 /// ((x & 0x0000ff00) >> 8) |
3247 /// ((x & 0x00ff0000) << 8) |
3248 /// ((x & 0xff000000) >> 8)
3249 /// => (rotl (bswap x), 16)
3250 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
3251 if (!LegalOperations)
3254 EVT VT = N->getValueType(0);
3257 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3261 // (or (or (and), (and)), (or (and), (and)))
3262 // (or (or (or (and), (and)), (and)), (and))
3263 if (N0.getOpcode() != ISD::OR)
3265 SDValue N00 = N0.getOperand(0);
3266 SDValue N01 = N0.getOperand(1);
3267 SDNode *Parts[4] = {};
3269 if (N1.getOpcode() == ISD::OR &&
3270 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) {
3271 // (or (or (and), (and)), (or (and), (and)))
3272 SDValue N000 = N00.getOperand(0);
3273 if (!isBSwapHWordElement(N000, Parts))
3276 SDValue N001 = N00.getOperand(1);
3277 if (!isBSwapHWordElement(N001, Parts))
3279 SDValue N010 = N01.getOperand(0);
3280 if (!isBSwapHWordElement(N010, Parts))
3282 SDValue N011 = N01.getOperand(1);
3283 if (!isBSwapHWordElement(N011, Parts))
3286 // (or (or (or (and), (and)), (and)), (and))
3287 if (!isBSwapHWordElement(N1, Parts))
3289 if (!isBSwapHWordElement(N01, Parts))
3291 if (N00.getOpcode() != ISD::OR)
3293 SDValue N000 = N00.getOperand(0);
3294 if (!isBSwapHWordElement(N000, Parts))
3296 SDValue N001 = N00.getOperand(1);
3297 if (!isBSwapHWordElement(N001, Parts))
3301 // Make sure the parts are all coming from the same node.
3302 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
3305 SDValue BSwap = DAG.getNode(ISD::BSWAP, SDLoc(N), VT,
3306 SDValue(Parts[0],0));
3308 // Result of the bswap should be rotated by 16. If it's not legal, then
3309 // do (x << 16) | (x >> 16).
3310 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
3311 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3312 return DAG.getNode(ISD::ROTL, SDLoc(N), VT, BSwap, ShAmt);
3313 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3314 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, BSwap, ShAmt);
3315 return DAG.getNode(ISD::OR, SDLoc(N), VT,
3316 DAG.getNode(ISD::SHL, SDLoc(N), VT, BSwap, ShAmt),
3317 DAG.getNode(ISD::SRL, SDLoc(N), VT, BSwap, ShAmt));
3320 SDValue DAGCombiner::visitOR(SDNode *N) {
3321 SDValue N0 = N->getOperand(0);
3322 SDValue N1 = N->getOperand(1);
3323 SDValue LL, LR, RL, RR, CC0, CC1;
3324 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3325 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3326 EVT VT = N1.getValueType();
3329 if (VT.isVector()) {
3330 SDValue FoldedVOp = SimplifyVBinOp(N);
3331 if (FoldedVOp.getNode()) return FoldedVOp;
3333 // fold (or x, 0) -> x, vector edition
3334 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3336 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3339 // fold (or x, -1) -> -1, vector edition
3340 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3341 // do not return N0, because undef node may exist in N0
3342 return DAG.getConstant(
3343 APInt::getAllOnesValue(
3344 N0.getValueType().getScalarType().getSizeInBits()),
3346 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3347 // do not return N1, because undef node may exist in N1
3348 return DAG.getConstant(
3349 APInt::getAllOnesValue(
3350 N1.getValueType().getScalarType().getSizeInBits()),
3353 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
3354 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
3355 // Do this only if the resulting shuffle is legal.
3356 if (isa<ShuffleVectorSDNode>(N0) &&
3357 isa<ShuffleVectorSDNode>(N1) &&
3358 // Avoid folding a node with illegal type.
3359 TLI.isTypeLegal(VT) &&
3360 N0->getOperand(1) == N1->getOperand(1) &&
3361 ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode())) {
3362 bool CanFold = true;
3363 unsigned NumElts = VT.getVectorNumElements();
3364 const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
3365 const ShuffleVectorSDNode *SV1 = cast<ShuffleVectorSDNode>(N1);
3366 // We construct two shuffle masks:
3367 // - Mask1 is a shuffle mask for a shuffle with N0 as the first operand
3368 // and N1 as the second operand.
3369 // - Mask2 is a shuffle mask for a shuffle with N1 as the first operand
3370 // and N0 as the second operand.
3371 // We do this because OR is commutable and therefore there might be
3372 // two ways to fold this node into a shuffle.
3373 SmallVector<int,4> Mask1;
3374 SmallVector<int,4> Mask2;
3376 for (unsigned i = 0; i != NumElts && CanFold; ++i) {
3377 int M0 = SV0->getMaskElt(i);
3378 int M1 = SV1->getMaskElt(i);
3380 // Both shuffle indexes are undef. Propagate Undef.
3381 if (M0 < 0 && M1 < 0) {
3382 Mask1.push_back(M0);
3383 Mask2.push_back(M0);
3387 if (M0 < 0 || M1 < 0 ||
3388 (M0 < (int)NumElts && M1 < (int)NumElts) ||
3389 (M0 >= (int)NumElts && M1 >= (int)NumElts)) {
3394 Mask1.push_back(M0 < (int)NumElts ? M0 : M1 + NumElts);
3395 Mask2.push_back(M1 < (int)NumElts ? M1 : M0 + NumElts);
3399 // Fold this sequence only if the resulting shuffle is 'legal'.
3400 if (TLI.isShuffleMaskLegal(Mask1, VT))
3401 return DAG.getVectorShuffle(VT, SDLoc(N), N0->getOperand(0),
3402 N1->getOperand(0), &Mask1[0]);
3403 if (TLI.isShuffleMaskLegal(Mask2, VT))
3404 return DAG.getVectorShuffle(VT, SDLoc(N), N1->getOperand(0),
3405 N0->getOperand(0), &Mask2[0]);
3410 // fold (or x, undef) -> -1
3411 if (!LegalOperations &&
3412 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3413 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3414 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
3416 // fold (or c1, c2) -> c1|c2
3418 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
3419 // canonicalize constant to RHS
3421 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
3422 // fold (or x, 0) -> x
3423 if (N1C && N1C->isNullValue())
3425 // fold (or x, -1) -> -1
3426 if (N1C && N1C->isAllOnesValue())
3428 // fold (or x, c) -> c iff (x & ~c) == 0
3429 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3432 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3433 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3434 if (BSwap.getNode())
3436 BSwap = MatchBSwapHWordLow(N, N0, N1);
3437 if (BSwap.getNode())
3441 SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1);
3444 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3445 // iff (c1 & c2) == 0.
3446 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3447 isa<ConstantSDNode>(N0.getOperand(1))) {
3448 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3449 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) {
3450 SDValue COR = DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1);
3453 return DAG.getNode(ISD::AND, SDLoc(N), VT,
3454 DAG.getNode(ISD::OR, SDLoc(N0), VT,
3455 N0.getOperand(0), N1), COR);
3458 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3459 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3460 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3461 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3463 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3464 LL.getValueType().isInteger()) {
3465 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3466 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3467 if (cast<ConstantSDNode>(LR)->isNullValue() &&
3468 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3469 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(LR),
3470 LR.getValueType(), LL, RL);
3471 AddToWorklist(ORNode.getNode());
3472 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
3474 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3475 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3476 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
3477 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3478 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(LR),
3479 LR.getValueType(), LL, RL);
3480 AddToWorklist(ANDNode.getNode());
3481 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
3484 // canonicalize equivalent to ll == rl
3485 if (LL == RR && LR == RL) {
3486 Op1 = ISD::getSetCCSwappedOperands(Op1);
3489 if (LL == RL && LR == RR) {
3490 bool isInteger = LL.getValueType().isInteger();
3491 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3492 if (Result != ISD::SETCC_INVALID &&
3493 (!LegalOperations ||
3494 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
3495 TLI.isOperationLegal(ISD::SETCC,
3496 getSetCCResultType(N0.getValueType())))))
3497 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
3502 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3503 if (N0.getOpcode() == N1.getOpcode()) {
3504 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3505 if (Tmp.getNode()) return Tmp;
3508 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3509 if (N0.getOpcode() == ISD::AND &&
3510 N1.getOpcode() == ISD::AND &&
3511 N0.getOperand(1).getOpcode() == ISD::Constant &&
3512 N1.getOperand(1).getOpcode() == ISD::Constant &&
3513 // Don't increase # computations.
3514 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3515 // We can only do this xform if we know that bits from X that are set in C2
3516 // but not in C1 are already zero. Likewise for Y.
3517 const APInt &LHSMask =
3518 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3519 const APInt &RHSMask =
3520 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3522 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3523 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3524 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3525 N0.getOperand(0), N1.getOperand(0));
3526 return DAG.getNode(ISD::AND, SDLoc(N), VT, X,
3527 DAG.getConstant(LHSMask | RHSMask, VT));
3531 // See if this is some rotate idiom.
3532 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
3533 return SDValue(Rot, 0);
3535 // Simplify the operands using demanded-bits information.
3536 if (!VT.isVector() &&
3537 SimplifyDemandedBits(SDValue(N, 0)))
3538 return SDValue(N, 0);
3543 /// Match "(X shl/srl V1) & V2" where V2 may not be present.
3544 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3545 if (Op.getOpcode() == ISD::AND) {
3546 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3547 Mask = Op.getOperand(1);
3548 Op = Op.getOperand(0);
3554 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3562 // Return true if we can prove that, whenever Neg and Pos are both in the
3563 // range [0, OpSize), Neg == (Pos == 0 ? 0 : OpSize - Pos). This means that
3564 // for two opposing shifts shift1 and shift2 and a value X with OpBits bits:
3566 // (or (shift1 X, Neg), (shift2 X, Pos))
3568 // reduces to a rotate in direction shift2 by Pos or (equivalently) a rotate
3569 // in direction shift1 by Neg. The range [0, OpSize) means that we only need
3570 // to consider shift amounts with defined behavior.
3571 static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned OpSize) {
3572 // If OpSize is a power of 2 then:
3574 // (a) (Pos == 0 ? 0 : OpSize - Pos) == (OpSize - Pos) & (OpSize - 1)
3575 // (b) Neg == Neg & (OpSize - 1) whenever Neg is in [0, OpSize).
3577 // So if OpSize is a power of 2 and Neg is (and Neg', OpSize-1), we check
3578 // for the stronger condition:
3580 // Neg & (OpSize - 1) == (OpSize - Pos) & (OpSize - 1) [A]
3582 // for all Neg and Pos. Since Neg & (OpSize - 1) == Neg' & (OpSize - 1)
3583 // we can just replace Neg with Neg' for the rest of the function.
3585 // In other cases we check for the even stronger condition:
3587 // Neg == OpSize - Pos [B]
3589 // for all Neg and Pos. Note that the (or ...) then invokes undefined
3590 // behavior if Pos == 0 (and consequently Neg == OpSize).
3592 // We could actually use [A] whenever OpSize is a power of 2, but the
3593 // only extra cases that it would match are those uninteresting ones
3594 // where Neg and Pos are never in range at the same time. E.g. for
3595 // OpSize == 32, using [A] would allow a Neg of the form (sub 64, Pos)
3596 // as well as (sub 32, Pos), but:
3598 // (or (shift1 X, (sub 64, Pos)), (shift2 X, Pos))
3600 // always invokes undefined behavior for 32-bit X.
3602 // Below, Mask == OpSize - 1 when using [A] and is all-ones otherwise.
3603 unsigned MaskLoBits = 0;
3604 if (Neg.getOpcode() == ISD::AND &&
3605 isPowerOf2_64(OpSize) &&
3606 Neg.getOperand(1).getOpcode() == ISD::Constant &&
3607 cast<ConstantSDNode>(Neg.getOperand(1))->getAPIntValue() == OpSize - 1) {
3608 Neg = Neg.getOperand(0);
3609 MaskLoBits = Log2_64(OpSize);
3612 // Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1.
3613 if (Neg.getOpcode() != ISD::SUB)
3615 ConstantSDNode *NegC = dyn_cast<ConstantSDNode>(Neg.getOperand(0));
3618 SDValue NegOp1 = Neg.getOperand(1);
3620 // On the RHS of [A], if Pos is Pos' & (OpSize - 1), just replace Pos with
3621 // Pos'. The truncation is redundant for the purpose of the equality.
3623 Pos.getOpcode() == ISD::AND &&
3624 Pos.getOperand(1).getOpcode() == ISD::Constant &&
3625 cast<ConstantSDNode>(Pos.getOperand(1))->getAPIntValue() == OpSize - 1)
3626 Pos = Pos.getOperand(0);
3628 // The condition we need is now:
3630 // (NegC - NegOp1) & Mask == (OpSize - Pos) & Mask
3632 // If NegOp1 == Pos then we need:
3634 // OpSize & Mask == NegC & Mask
3636 // (because "x & Mask" is a truncation and distributes through subtraction).
3639 Width = NegC->getAPIntValue();
3640 // Check for cases where Pos has the form (add NegOp1, PosC) for some PosC.
3641 // Then the condition we want to prove becomes:
3643 // (NegC - NegOp1) & Mask == (OpSize - (NegOp1 + PosC)) & Mask
3645 // which, again because "x & Mask" is a truncation, becomes:
3647 // NegC & Mask == (OpSize - PosC) & Mask
3648 // OpSize & Mask == (NegC + PosC) & Mask
3649 else if (Pos.getOpcode() == ISD::ADD &&
3650 Pos.getOperand(0) == NegOp1 &&
3651 Pos.getOperand(1).getOpcode() == ISD::Constant)
3652 Width = (cast<ConstantSDNode>(Pos.getOperand(1))->getAPIntValue() +
3653 NegC->getAPIntValue());
3657 // Now we just need to check that OpSize & Mask == Width & Mask.
3659 // Opsize & Mask is 0 since Mask is Opsize - 1.
3660 return Width.getLoBits(MaskLoBits) == 0;
3661 return Width == OpSize;
3664 // A subroutine of MatchRotate used once we have found an OR of two opposite
3665 // shifts of Shifted. If Neg == <operand size> - Pos then the OR reduces
3666 // to both (PosOpcode Shifted, Pos) and (NegOpcode Shifted, Neg), with the
3667 // former being preferred if supported. InnerPos and InnerNeg are Pos and
3668 // Neg with outer conversions stripped away.
3669 SDNode *DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
3670 SDValue Neg, SDValue InnerPos,
3671 SDValue InnerNeg, unsigned PosOpcode,
3672 unsigned NegOpcode, SDLoc DL) {
3673 // fold (or (shl x, (*ext y)),
3674 // (srl x, (*ext (sub 32, y)))) ->
3675 // (rotl x, y) or (rotr x, (sub 32, y))
3677 // fold (or (shl x, (*ext (sub 32, y))),
3678 // (srl x, (*ext y))) ->
3679 // (rotr x, y) or (rotl x, (sub 32, y))
3680 EVT VT = Shifted.getValueType();
3681 if (matchRotateSub(InnerPos, InnerNeg, VT.getSizeInBits())) {
3682 bool HasPos = TLI.isOperationLegalOrCustom(PosOpcode, VT);
3683 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted,
3684 HasPos ? Pos : Neg).getNode();
3690 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3691 // idioms for rotate, and if the target supports rotation instructions, generate
3693 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) {
3694 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3695 EVT VT = LHS.getValueType();
3696 if (!TLI.isTypeLegal(VT)) return nullptr;
3698 // The target must have at least one rotate flavor.
3699 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3700 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3701 if (!HasROTL && !HasROTR) return nullptr;
3703 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3704 SDValue LHSShift; // The shift.
3705 SDValue LHSMask; // AND value if any.
3706 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3707 return nullptr; // Not part of a rotate.
3709 SDValue RHSShift; // The shift.
3710 SDValue RHSMask; // AND value if any.
3711 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3712 return nullptr; // Not part of a rotate.
3714 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3715 return nullptr; // Not shifting the same value.
3717 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3718 return nullptr; // Shifts must disagree.
3720 // Canonicalize shl to left side in a shl/srl pair.
3721 if (RHSShift.getOpcode() == ISD::SHL) {
3722 std::swap(LHS, RHS);
3723 std::swap(LHSShift, RHSShift);
3724 std::swap(LHSMask , RHSMask );
3727 unsigned OpSizeInBits = VT.getSizeInBits();
3728 SDValue LHSShiftArg = LHSShift.getOperand(0);
3729 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3730 SDValue RHSShiftArg = RHSShift.getOperand(0);
3731 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3733 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3734 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3735 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3736 RHSShiftAmt.getOpcode() == ISD::Constant) {
3737 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3738 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3739 if ((LShVal + RShVal) != OpSizeInBits)
3742 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3743 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
3745 // If there is an AND of either shifted operand, apply it to the result.
3746 if (LHSMask.getNode() || RHSMask.getNode()) {
3747 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3749 if (LHSMask.getNode()) {
3750 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3751 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3753 if (RHSMask.getNode()) {
3754 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3755 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3758 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3761 return Rot.getNode();
3764 // If there is a mask here, and we have a variable shift, we can't be sure
3765 // that we're masking out the right stuff.
3766 if (LHSMask.getNode() || RHSMask.getNode())
3769 // If the shift amount is sign/zext/any-extended just peel it off.
3770 SDValue LExtOp0 = LHSShiftAmt;
3771 SDValue RExtOp0 = RHSShiftAmt;
3772 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3773 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3774 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3775 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3776 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3777 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3778 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3779 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3780 LExtOp0 = LHSShiftAmt.getOperand(0);
3781 RExtOp0 = RHSShiftAmt.getOperand(0);
3784 SDNode *TryL = MatchRotatePosNeg(LHSShiftArg, LHSShiftAmt, RHSShiftAmt,
3785 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
3789 SDNode *TryR = MatchRotatePosNeg(RHSShiftArg, RHSShiftAmt, LHSShiftAmt,
3790 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
3797 SDValue DAGCombiner::visitXOR(SDNode *N) {
3798 SDValue N0 = N->getOperand(0);
3799 SDValue N1 = N->getOperand(1);
3800 SDValue LHS, RHS, CC;
3801 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3802 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3803 EVT VT = N0.getValueType();
3806 if (VT.isVector()) {
3807 SDValue FoldedVOp = SimplifyVBinOp(N);
3808 if (FoldedVOp.getNode()) return FoldedVOp;
3810 // fold (xor x, 0) -> x, vector edition
3811 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3813 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3817 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3818 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3819 return DAG.getConstant(0, VT);
3820 // fold (xor x, undef) -> undef
3821 if (N0.getOpcode() == ISD::UNDEF)
3823 if (N1.getOpcode() == ISD::UNDEF)
3825 // fold (xor c1, c2) -> c1^c2
3827 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3828 // canonicalize constant to RHS
3830 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
3831 // fold (xor x, 0) -> x
3832 if (N1C && N1C->isNullValue())
3835 SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1);
3839 // fold !(x cc y) -> (x !cc y)
3840 if (TLI.isConstTrueVal(N1.getNode()) && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3841 bool isInt = LHS.getValueType().isInteger();
3842 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3845 if (!LegalOperations ||
3846 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) {
3847 switch (N0.getOpcode()) {
3849 llvm_unreachable("Unhandled SetCC Equivalent!");
3851 return DAG.getSetCC(SDLoc(N), VT, LHS, RHS, NotCC);
3852 case ISD::SELECT_CC:
3853 return DAG.getSelectCC(SDLoc(N), LHS, RHS, N0.getOperand(2),
3854 N0.getOperand(3), NotCC);
3859 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3860 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3861 N0.getNode()->hasOneUse() &&
3862 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3863 SDValue V = N0.getOperand(0);
3864 V = DAG.getNode(ISD::XOR, SDLoc(N0), V.getValueType(), V,
3865 DAG.getConstant(1, V.getValueType()));
3866 AddToWorklist(V.getNode());
3867 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, V);
3870 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3871 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3872 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3873 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3874 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3875 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3876 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
3877 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
3878 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
3879 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
3882 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3883 if (N1C && N1C->isAllOnesValue() &&
3884 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3885 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3886 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3887 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3888 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
3889 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
3890 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
3891 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
3894 // fold (xor (and x, y), y) -> (and (not x), y)
3895 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3896 N0->getOperand(1) == N1) {
3897 SDValue X = N0->getOperand(0);
3898 SDValue NotX = DAG.getNOT(SDLoc(X), X, VT);
3899 AddToWorklist(NotX.getNode());
3900 return DAG.getNode(ISD::AND, SDLoc(N), VT, NotX, N1);
3902 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3903 if (N1C && N0.getOpcode() == ISD::XOR) {
3904 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3905 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3907 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(1),
3908 DAG.getConstant(N1C->getAPIntValue() ^
3909 N00C->getAPIntValue(), VT));
3911 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(0),
3912 DAG.getConstant(N1C->getAPIntValue() ^
3913 N01C->getAPIntValue(), VT));
3915 // fold (xor x, x) -> 0
3917 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
3919 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3920 if (N0.getOpcode() == N1.getOpcode()) {
3921 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3922 if (Tmp.getNode()) return Tmp;
3925 // Simplify the expression using non-local knowledge.
3926 if (!VT.isVector() &&
3927 SimplifyDemandedBits(SDValue(N, 0)))
3928 return SDValue(N, 0);
3933 /// Handle transforms common to the three shifts, when the shift amount is a
3935 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, ConstantSDNode *Amt) {
3936 // We can't and shouldn't fold opaque constants.
3937 if (Amt->isOpaque())
3940 SDNode *LHS = N->getOperand(0).getNode();
3941 if (!LHS->hasOneUse()) return SDValue();
3943 // We want to pull some binops through shifts, so that we have (and (shift))
3944 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3945 // thing happens with address calculations, so it's important to canonicalize
3947 bool HighBitSet = false; // Can we transform this if the high bit is set?
3949 switch (LHS->getOpcode()) {
3950 default: return SDValue();
3953 HighBitSet = false; // We can only transform sra if the high bit is clear.
3956 HighBitSet = true; // We can only transform sra if the high bit is set.
3959 if (N->getOpcode() != ISD::SHL)
3960 return SDValue(); // only shl(add) not sr[al](add).
3961 HighBitSet = false; // We can only transform sra if the high bit is clear.
3965 // We require the RHS of the binop to be a constant and not opaque as well.
3966 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3967 if (!BinOpCst || BinOpCst->isOpaque()) return SDValue();
3969 // FIXME: disable this unless the input to the binop is a shift by a constant.
3970 // If it is not a shift, it pessimizes some common cases like:
3972 // void foo(int *X, int i) { X[i & 1235] = 1; }
3973 // int bar(int *X, int i) { return X[i & 255]; }
3974 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3975 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3976 BinOpLHSVal->getOpcode() != ISD::SRA &&
3977 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3978 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3981 EVT VT = N->getValueType(0);
3983 // If this is a signed shift right, and the high bit is modified by the
3984 // logical operation, do not perform the transformation. The highBitSet
3985 // boolean indicates the value of the high bit of the constant which would
3986 // cause it to be modified for this operation.
3987 if (N->getOpcode() == ISD::SRA) {
3988 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3989 if (BinOpRHSSignSet != HighBitSet)
3993 if (!TLI.isDesirableToCommuteWithShift(LHS))
3996 // Fold the constants, shifting the binop RHS by the shift amount.
3997 SDValue NewRHS = DAG.getNode(N->getOpcode(), SDLoc(LHS->getOperand(1)),
3999 LHS->getOperand(1), N->getOperand(1));
4000 assert(isa<ConstantSDNode>(NewRHS) && "Folding was not successful!");
4002 // Create the new shift.
4003 SDValue NewShift = DAG.getNode(N->getOpcode(),
4004 SDLoc(LHS->getOperand(0)),
4005 VT, LHS->getOperand(0), N->getOperand(1));
4007 // Create the new binop.
4008 return DAG.getNode(LHS->getOpcode(), SDLoc(N), VT, NewShift, NewRHS);
4011 SDValue DAGCombiner::distributeTruncateThroughAnd(SDNode *N) {
4012 assert(N->getOpcode() == ISD::TRUNCATE);
4013 assert(N->getOperand(0).getOpcode() == ISD::AND);
4015 // (truncate:TruncVT (and N00, N01C)) -> (and (truncate:TruncVT N00), TruncC)
4016 if (N->hasOneUse() && N->getOperand(0).hasOneUse()) {
4017 SDValue N01 = N->getOperand(0).getOperand(1);
4019 if (ConstantSDNode *N01C = isConstOrConstSplat(N01)) {
4020 EVT TruncVT = N->getValueType(0);
4021 SDValue N00 = N->getOperand(0).getOperand(0);
4022 APInt TruncC = N01C->getAPIntValue();
4023 TruncC = TruncC.trunc(TruncVT.getScalarSizeInBits());
4025 return DAG.getNode(ISD::AND, SDLoc(N), TruncVT,
4026 DAG.getNode(ISD::TRUNCATE, SDLoc(N), TruncVT, N00),
4027 DAG.getConstant(TruncC, TruncVT));
4034 SDValue DAGCombiner::visitRotate(SDNode *N) {
4035 // fold (rot* x, (trunc (and y, c))) -> (rot* x, (and (trunc y), (trunc c))).
4036 if (N->getOperand(1).getOpcode() == ISD::TRUNCATE &&
4037 N->getOperand(1).getOperand(0).getOpcode() == ISD::AND) {
4038 SDValue NewOp1 = distributeTruncateThroughAnd(N->getOperand(1).getNode());
4039 if (NewOp1.getNode())
4040 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
4041 N->getOperand(0), NewOp1);
4046 SDValue DAGCombiner::visitSHL(SDNode *N) {
4047 SDValue N0 = N->getOperand(0);
4048 SDValue N1 = N->getOperand(1);
4049 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4050 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4051 EVT VT = N0.getValueType();
4052 unsigned OpSizeInBits = VT.getScalarSizeInBits();
4055 if (VT.isVector()) {
4056 SDValue FoldedVOp = SimplifyVBinOp(N);
4057 if (FoldedVOp.getNode()) return FoldedVOp;
4059 BuildVectorSDNode *N1CV = dyn_cast<BuildVectorSDNode>(N1);
4060 // If setcc produces all-one true value then:
4061 // (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV)
4062 if (N1CV && N1CV->isConstant()) {
4063 if (N0.getOpcode() == ISD::AND) {
4064 SDValue N00 = N0->getOperand(0);
4065 SDValue N01 = N0->getOperand(1);
4066 BuildVectorSDNode *N01CV = dyn_cast<BuildVectorSDNode>(N01);
4068 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
4069 TLI.getBooleanContents(N00.getOperand(0).getValueType()) ==
4070 TargetLowering::ZeroOrNegativeOneBooleanContent) {
4071 SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, VT, N01CV, N1CV);
4073 return DAG.getNode(ISD::AND, SDLoc(N), VT, N00, C);
4076 N1C = isConstOrConstSplat(N1);
4081 // fold (shl c1, c2) -> c1<<c2
4083 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
4084 // fold (shl 0, x) -> 0
4085 if (N0C && N0C->isNullValue())
4087 // fold (shl x, c >= size(x)) -> undef
4088 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4089 return DAG.getUNDEF(VT);
4090 // fold (shl x, 0) -> x
4091 if (N1C && N1C->isNullValue())
4093 // fold (shl undef, x) -> 0
4094 if (N0.getOpcode() == ISD::UNDEF)
4095 return DAG.getConstant(0, VT);
4096 // if (shl x, c) is known to be zero, return 0
4097 if (DAG.MaskedValueIsZero(SDValue(N, 0),
4098 APInt::getAllOnesValue(OpSizeInBits)))
4099 return DAG.getConstant(0, VT);
4100 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
4101 if (N1.getOpcode() == ISD::TRUNCATE &&
4102 N1.getOperand(0).getOpcode() == ISD::AND) {
4103 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4104 if (NewOp1.getNode())
4105 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, NewOp1);
4108 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4109 return SDValue(N, 0);
4111 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
4112 if (N1C && N0.getOpcode() == ISD::SHL) {
4113 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4114 uint64_t c1 = N0C1->getZExtValue();
4115 uint64_t c2 = N1C->getZExtValue();
4116 if (c1 + c2 >= OpSizeInBits)
4117 return DAG.getConstant(0, VT);
4118 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
4119 DAG.getConstant(c1 + c2, N1.getValueType()));
4123 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
4124 // For this to be valid, the second form must not preserve any of the bits
4125 // that are shifted out by the inner shift in the first form. This means
4126 // the outer shift size must be >= the number of bits added by the ext.
4127 // As a corollary, we don't care what kind of ext it is.
4128 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
4129 N0.getOpcode() == ISD::ANY_EXTEND ||
4130 N0.getOpcode() == ISD::SIGN_EXTEND) &&
4131 N0.getOperand(0).getOpcode() == ISD::SHL) {
4132 SDValue N0Op0 = N0.getOperand(0);
4133 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
4134 uint64_t c1 = N0Op0C1->getZExtValue();
4135 uint64_t c2 = N1C->getZExtValue();
4136 EVT InnerShiftVT = N0Op0.getValueType();
4137 uint64_t InnerShiftSize = InnerShiftVT.getScalarSizeInBits();
4138 if (c2 >= OpSizeInBits - InnerShiftSize) {
4139 if (c1 + c2 >= OpSizeInBits)
4140 return DAG.getConstant(0, VT);
4141 return DAG.getNode(ISD::SHL, SDLoc(N0), VT,
4142 DAG.getNode(N0.getOpcode(), SDLoc(N0), VT,
4143 N0Op0->getOperand(0)),
4144 DAG.getConstant(c1 + c2, N1.getValueType()));
4149 // fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
4150 // Only fold this if the inner zext has no other uses to avoid increasing
4151 // the total number of instructions.
4152 if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
4153 N0.getOperand(0).getOpcode() == ISD::SRL) {
4154 SDValue N0Op0 = N0.getOperand(0);
4155 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
4156 uint64_t c1 = N0Op0C1->getZExtValue();
4157 if (c1 < VT.getScalarSizeInBits()) {
4158 uint64_t c2 = N1C->getZExtValue();
4160 SDValue NewOp0 = N0.getOperand(0);
4161 EVT CountVT = NewOp0.getOperand(1).getValueType();
4162 SDValue NewSHL = DAG.getNode(ISD::SHL, SDLoc(N), NewOp0.getValueType(),
4163 NewOp0, DAG.getConstant(c2, CountVT));
4164 AddToWorklist(NewSHL.getNode());
4165 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
4171 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
4172 // (and (srl x, (sub c1, c2), MASK)
4173 // Only fold this if the inner shift has no other uses -- if it does, folding
4174 // this will increase the total number of instructions.
4175 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4176 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4177 uint64_t c1 = N0C1->getZExtValue();
4178 if (c1 < OpSizeInBits) {
4179 uint64_t c2 = N1C->getZExtValue();
4180 APInt Mask = APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - c1);
4183 Mask = Mask.shl(c2 - c1);
4184 Shift = DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
4185 DAG.getConstant(c2 - c1, N1.getValueType()));
4187 Mask = Mask.lshr(c1 - c2);
4188 Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4189 DAG.getConstant(c1 - c2, N1.getValueType()));
4191 return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift,
4192 DAG.getConstant(Mask, VT));
4196 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
4197 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
4198 unsigned BitSize = VT.getScalarSizeInBits();
4199 SDValue HiBitsMask =
4200 DAG.getConstant(APInt::getHighBitsSet(BitSize,
4201 BitSize - N1C->getZExtValue()), VT);
4202 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
4206 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)
4207 // Variant of version done on multiply, except mul by a power of 2 is turned
4210 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
4211 (isa<ConstantSDNode>(N0.getOperand(1)) ||
4212 isConstantSplatVector(N0.getOperand(1).getNode(), Val))) {
4213 SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1);
4214 SDValue Shl1 = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);
4215 return DAG.getNode(ISD::ADD, SDLoc(N), VT, Shl0, Shl1);
4219 SDValue NewSHL = visitShiftByConstant(N, N1C);
4220 if (NewSHL.getNode())
4227 SDValue DAGCombiner::visitSRA(SDNode *N) {
4228 SDValue N0 = N->getOperand(0);
4229 SDValue N1 = N->getOperand(1);
4230 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4231 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4232 EVT VT = N0.getValueType();
4233 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
4236 if (VT.isVector()) {
4237 SDValue FoldedVOp = SimplifyVBinOp(N);
4238 if (FoldedVOp.getNode()) return FoldedVOp;
4240 N1C = isConstOrConstSplat(N1);
4243 // fold (sra c1, c2) -> (sra c1, c2)
4245 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
4246 // fold (sra 0, x) -> 0
4247 if (N0C && N0C->isNullValue())
4249 // fold (sra -1, x) -> -1
4250 if (N0C && N0C->isAllOnesValue())
4252 // fold (sra x, (setge c, size(x))) -> undef
4253 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4254 return DAG.getUNDEF(VT);
4255 // fold (sra x, 0) -> x
4256 if (N1C && N1C->isNullValue())
4258 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
4260 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
4261 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
4262 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
4264 ExtVT = EVT::getVectorVT(*DAG.getContext(),
4265 ExtVT, VT.getVectorNumElements());
4266 if ((!LegalOperations ||
4267 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
4268 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
4269 N0.getOperand(0), DAG.getValueType(ExtVT));
4272 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
4273 if (N1C && N0.getOpcode() == ISD::SRA) {
4274 if (ConstantSDNode *C1 = isConstOrConstSplat(N0.getOperand(1))) {
4275 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
4276 if (Sum >= OpSizeInBits)
4277 Sum = OpSizeInBits - 1;
4278 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0),
4279 DAG.getConstant(Sum, N1.getValueType()));
4283 // fold (sra (shl X, m), (sub result_size, n))
4284 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
4285 // result_size - n != m.
4286 // If truncate is free for the target sext(shl) is likely to result in better
4288 if (N0.getOpcode() == ISD::SHL && N1C) {
4289 // Get the two constanst of the shifts, CN0 = m, CN = n.
4290 const ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1));
4292 LLVMContext &Ctx = *DAG.getContext();
4293 // Determine what the truncate's result bitsize and type would be.
4294 EVT TruncVT = EVT::getIntegerVT(Ctx, OpSizeInBits - N1C->getZExtValue());
4297 TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorNumElements());
4299 // Determine the residual right-shift amount.
4300 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
4302 // If the shift is not a no-op (in which case this should be just a sign
4303 // extend already), the truncated to type is legal, sign_extend is legal
4304 // on that type, and the truncate to that type is both legal and free,
4305 // perform the transform.
4306 if ((ShiftAmt > 0) &&
4307 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
4308 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
4309 TLI.isTruncateFree(VT, TruncVT)) {
4311 SDValue Amt = DAG.getConstant(ShiftAmt,
4312 getShiftAmountTy(N0.getOperand(0).getValueType()));
4313 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT,
4314 N0.getOperand(0), Amt);
4315 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), TruncVT,
4317 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N),
4318 N->getValueType(0), Trunc);
4323 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
4324 if (N1.getOpcode() == ISD::TRUNCATE &&
4325 N1.getOperand(0).getOpcode() == ISD::AND) {
4326 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4327 if (NewOp1.getNode())
4328 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1);
4331 // fold (sra (trunc (srl x, c1)), c2) -> (trunc (sra x, c1 + c2))
4332 // if c1 is equal to the number of bits the trunc removes
4333 if (N0.getOpcode() == ISD::TRUNCATE &&
4334 (N0.getOperand(0).getOpcode() == ISD::SRL ||
4335 N0.getOperand(0).getOpcode() == ISD::SRA) &&
4336 N0.getOperand(0).hasOneUse() &&
4337 N0.getOperand(0).getOperand(1).hasOneUse() &&
4339 SDValue N0Op0 = N0.getOperand(0);
4340 if (ConstantSDNode *LargeShift = isConstOrConstSplat(N0Op0.getOperand(1))) {
4341 unsigned LargeShiftVal = LargeShift->getZExtValue();
4342 EVT LargeVT = N0Op0.getValueType();
4344 if (LargeVT.getScalarSizeInBits() - OpSizeInBits == LargeShiftVal) {
4346 DAG.getConstant(LargeShiftVal + N1C->getZExtValue(),
4347 getShiftAmountTy(N0Op0.getOperand(0).getValueType()));
4348 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), LargeVT,
4349 N0Op0.getOperand(0), Amt);
4350 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, SRA);
4355 // Simplify, based on bits shifted out of the LHS.
4356 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4357 return SDValue(N, 0);
4360 // If the sign bit is known to be zero, switch this to a SRL.
4361 if (DAG.SignBitIsZero(N0))
4362 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
4365 SDValue NewSRA = visitShiftByConstant(N, N1C);
4366 if (NewSRA.getNode())
4373 SDValue DAGCombiner::visitSRL(SDNode *N) {
4374 SDValue N0 = N->getOperand(0);
4375 SDValue N1 = N->getOperand(1);
4376 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4377 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4378 EVT VT = N0.getValueType();
4379 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
4382 if (VT.isVector()) {
4383 SDValue FoldedVOp = SimplifyVBinOp(N);
4384 if (FoldedVOp.getNode()) return FoldedVOp;
4386 N1C = isConstOrConstSplat(N1);
4389 // fold (srl c1, c2) -> c1 >>u c2
4391 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
4392 // fold (srl 0, x) -> 0
4393 if (N0C && N0C->isNullValue())
4395 // fold (srl x, c >= size(x)) -> undef
4396 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4397 return DAG.getUNDEF(VT);
4398 // fold (srl x, 0) -> x
4399 if (N1C && N1C->isNullValue())
4401 // if (srl x, c) is known to be zero, return 0
4402 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
4403 APInt::getAllOnesValue(OpSizeInBits)))
4404 return DAG.getConstant(0, VT);
4406 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
4407 if (N1C && N0.getOpcode() == ISD::SRL) {
4408 if (ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1))) {
4409 uint64_t c1 = N01C->getZExtValue();
4410 uint64_t c2 = N1C->getZExtValue();
4411 if (c1 + c2 >= OpSizeInBits)
4412 return DAG.getConstant(0, VT);
4413 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4414 DAG.getConstant(c1 + c2, N1.getValueType()));
4418 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
4419 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
4420 N0.getOperand(0).getOpcode() == ISD::SRL &&
4421 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
4423 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
4424 uint64_t c2 = N1C->getZExtValue();
4425 EVT InnerShiftVT = N0.getOperand(0).getValueType();
4426 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
4427 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
4428 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
4429 if (c1 + OpSizeInBits == InnerShiftSize) {
4430 if (c1 + c2 >= InnerShiftSize)
4431 return DAG.getConstant(0, VT);
4432 return DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT,
4433 DAG.getNode(ISD::SRL, SDLoc(N0), InnerShiftVT,
4434 N0.getOperand(0)->getOperand(0),
4435 DAG.getConstant(c1 + c2, ShiftCountVT)));
4439 // fold (srl (shl x, c), c) -> (and x, cst2)
4440 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1) {
4441 unsigned BitSize = N0.getScalarValueSizeInBits();
4442 if (BitSize <= 64) {
4443 uint64_t ShAmt = N1C->getZExtValue() + 64 - BitSize;
4444 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
4445 DAG.getConstant(~0ULL >> ShAmt, VT));
4449 // fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask)
4450 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
4451 // Shifting in all undef bits?
4452 EVT SmallVT = N0.getOperand(0).getValueType();
4453 unsigned BitSize = SmallVT.getScalarSizeInBits();
4454 if (N1C->getZExtValue() >= BitSize)
4455 return DAG.getUNDEF(VT);
4457 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
4458 uint64_t ShiftAmt = N1C->getZExtValue();
4459 SDValue SmallShift = DAG.getNode(ISD::SRL, SDLoc(N0), SmallVT,
4461 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
4462 AddToWorklist(SmallShift.getNode());
4463 APInt Mask = APInt::getAllOnesValue(OpSizeInBits).lshr(ShiftAmt);
4464 return DAG.getNode(ISD::AND, SDLoc(N), VT,
4465 DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, SmallShift),
4466 DAG.getConstant(Mask, VT));
4470 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
4471 // bit, which is unmodified by sra.
4472 if (N1C && N1C->getZExtValue() + 1 == OpSizeInBits) {
4473 if (N0.getOpcode() == ISD::SRA)
4474 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
4477 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
4478 if (N1C && N0.getOpcode() == ISD::CTLZ &&
4479 N1C->getAPIntValue() == Log2_32(OpSizeInBits)) {
4480 APInt KnownZero, KnownOne;
4481 DAG.computeKnownBits(N0.getOperand(0), KnownZero, KnownOne);
4483 // If any of the input bits are KnownOne, then the input couldn't be all
4484 // zeros, thus the result of the srl will always be zero.
4485 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
4487 // If all of the bits input the to ctlz node are known to be zero, then
4488 // the result of the ctlz is "32" and the result of the shift is one.
4489 APInt UnknownBits = ~KnownZero;
4490 if (UnknownBits == 0) return DAG.getConstant(1, VT);
4492 // Otherwise, check to see if there is exactly one bit input to the ctlz.
4493 if ((UnknownBits & (UnknownBits - 1)) == 0) {
4494 // Okay, we know that only that the single bit specified by UnknownBits
4495 // could be set on input to the CTLZ node. If this bit is set, the SRL
4496 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
4497 // to an SRL/XOR pair, which is likely to simplify more.
4498 unsigned ShAmt = UnknownBits.countTrailingZeros();
4499 SDValue Op = N0.getOperand(0);
4502 Op = DAG.getNode(ISD::SRL, SDLoc(N0), VT, Op,
4503 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
4504 AddToWorklist(Op.getNode());
4507 return DAG.getNode(ISD::XOR, SDLoc(N), VT,
4508 Op, DAG.getConstant(1, VT));
4512 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
4513 if (N1.getOpcode() == ISD::TRUNCATE &&
4514 N1.getOperand(0).getOpcode() == ISD::AND) {
4515 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4516 if (NewOp1.getNode())
4517 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1);
4520 // fold operands of srl based on knowledge that the low bits are not
4522 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4523 return SDValue(N, 0);
4526 SDValue NewSRL = visitShiftByConstant(N, N1C);
4527 if (NewSRL.getNode())
4531 // Attempt to convert a srl of a load into a narrower zero-extending load.
4532 SDValue NarrowLoad = ReduceLoadWidth(N);
4533 if (NarrowLoad.getNode())
4536 // Here is a common situation. We want to optimize:
4539 // %b = and i32 %a, 2
4540 // %c = srl i32 %b, 1
4541 // brcond i32 %c ...
4547 // %c = setcc eq %b, 0
4550 // However when after the source operand of SRL is optimized into AND, the SRL
4551 // itself may not be optimized further. Look for it and add the BRCOND into
4553 if (N->hasOneUse()) {
4554 SDNode *Use = *N->use_begin();
4555 if (Use->getOpcode() == ISD::BRCOND)
4557 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
4558 // Also look pass the truncate.
4559 Use = *Use->use_begin();
4560 if (Use->getOpcode() == ISD::BRCOND)
4568 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
4569 SDValue N0 = N->getOperand(0);
4570 EVT VT = N->getValueType(0);
4572 // fold (ctlz c1) -> c2
4573 if (isa<ConstantSDNode>(N0))
4574 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
4578 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
4579 SDValue N0 = N->getOperand(0);
4580 EVT VT = N->getValueType(0);
4582 // fold (ctlz_zero_undef c1) -> c2
4583 if (isa<ConstantSDNode>(N0))
4584 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4588 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
4589 SDValue N0 = N->getOperand(0);
4590 EVT VT = N->getValueType(0);
4592 // fold (cttz c1) -> c2
4593 if (isa<ConstantSDNode>(N0))
4594 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0);
4598 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
4599 SDValue N0 = N->getOperand(0);
4600 EVT VT = N->getValueType(0);
4602 // fold (cttz_zero_undef c1) -> c2
4603 if (isa<ConstantSDNode>(N0))
4604 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4608 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4609 SDValue N0 = N->getOperand(0);
4610 EVT VT = N->getValueType(0);
4612 // fold (ctpop c1) -> c2
4613 if (isa<ConstantSDNode>(N0))
4614 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0);
4618 SDValue DAGCombiner::visitSELECT(SDNode *N) {
4619 SDValue N0 = N->getOperand(0);
4620 SDValue N1 = N->getOperand(1);
4621 SDValue N2 = N->getOperand(2);
4622 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4623 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4624 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
4625 EVT VT = N->getValueType(0);
4626 EVT VT0 = N0.getValueType();
4628 // fold (select C, X, X) -> X
4631 // fold (select true, X, Y) -> X
4632 if (N0C && !N0C->isNullValue())
4634 // fold (select false, X, Y) -> Y
4635 if (N0C && N0C->isNullValue())
4637 // fold (select C, 1, X) -> (or C, X)
4638 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
4639 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4640 // fold (select C, 0, 1) -> (xor C, 1)
4641 // We can't do this reliably if integer based booleans have different contents
4642 // to floating point based booleans. This is because we can't tell whether we
4643 // have an integer-based boolean or a floating-point-based boolean unless we
4644 // can find the SETCC that produced it and inspect its operands. This is
4645 // fairly easy if C is the SETCC node, but it can potentially be
4646 // undiscoverable (or not reasonably discoverable). For example, it could be
4647 // in another basic block or it could require searching a complicated
4649 if (VT.isInteger() &&
4650 (VT0 == MVT::i1 || (VT0.isInteger() &&
4651 TLI.getBooleanContents(false, false) ==
4652 TLI.getBooleanContents(false, true) &&
4653 TLI.getBooleanContents(false, false) ==
4654 TargetLowering::ZeroOrOneBooleanContent)) &&
4655 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
4658 return DAG.getNode(ISD::XOR, SDLoc(N), VT0,
4659 N0, DAG.getConstant(1, VT0));
4660 XORNode = DAG.getNode(ISD::XOR, SDLoc(N0), VT0,
4661 N0, DAG.getConstant(1, VT0));
4662 AddToWorklist(XORNode.getNode());
4664 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, XORNode);
4665 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, XORNode);
4667 // fold (select C, 0, X) -> (and (not C), X)
4668 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
4669 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4670 AddToWorklist(NOTNode.getNode());
4671 return DAG.getNode(ISD::AND, SDLoc(N), VT, NOTNode, N2);
4673 // fold (select C, X, 1) -> (or (not C), X)
4674 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
4675 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4676 AddToWorklist(NOTNode.getNode());
4677 return DAG.getNode(ISD::OR, SDLoc(N), VT, NOTNode, N1);
4679 // fold (select C, X, 0) -> (and C, X)
4680 if (VT == MVT::i1 && N2C && N2C->isNullValue())
4681 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4682 // fold (select X, X, Y) -> (or X, Y)
4683 // fold (select X, 1, Y) -> (or X, Y)
4684 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4685 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4686 // fold (select X, Y, X) -> (and X, Y)
4687 // fold (select X, Y, 0) -> (and X, Y)
4688 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4689 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4691 // If we can fold this based on the true/false value, do so.
4692 if (SimplifySelectOps(N, N1, N2))
4693 return SDValue(N, 0); // Don't revisit N.
4695 // fold selects based on a setcc into other things, such as min/max/abs
4696 if (N0.getOpcode() == ISD::SETCC) {
4697 if ((!LegalOperations &&
4698 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) ||
4699 TLI.isOperationLegal(ISD::SELECT_CC, VT))
4700 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT,
4701 N0.getOperand(0), N0.getOperand(1),
4702 N1, N2, N0.getOperand(2));
4703 return SimplifySelect(SDLoc(N), N0, N1, N2);
4710 std::pair<SDValue, SDValue> SplitVSETCC(const SDNode *N, SelectionDAG &DAG) {
4713 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
4715 // Split the inputs.
4716 SDValue Lo, Hi, LL, LH, RL, RH;
4717 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
4718 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
4720 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
4721 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
4723 return std::make_pair(Lo, Hi);
4726 // This function assumes all the vselect's arguments are CONCAT_VECTOR
4727 // nodes and that the condition is a BV of ConstantSDNodes (or undefs).
4728 static SDValue ConvertSelectToConcatVector(SDNode *N, SelectionDAG &DAG) {
4730 SDValue Cond = N->getOperand(0);
4731 SDValue LHS = N->getOperand(1);
4732 SDValue RHS = N->getOperand(2);
4733 EVT VT = N->getValueType(0);
4734 int NumElems = VT.getVectorNumElements();
4735 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS &&
4736 RHS.getOpcode() == ISD::CONCAT_VECTORS &&
4737 Cond.getOpcode() == ISD::BUILD_VECTOR);
4739 // CONCAT_VECTOR can take an arbitrary number of arguments. We only care about
4740 // binary ones here.
4741 if (LHS->getNumOperands() != 2 || RHS->getNumOperands() != 2)
4744 // We're sure we have an even number of elements due to the
4745 // concat_vectors we have as arguments to vselect.
4746 // Skip BV elements until we find one that's not an UNDEF
4747 // After we find an UNDEF element, keep looping until we get to half the
4748 // length of the BV and see if all the non-undef nodes are the same.
4749 ConstantSDNode *BottomHalf = nullptr;
4750 for (int i = 0; i < NumElems / 2; ++i) {
4751 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
4754 if (BottomHalf == nullptr)
4755 BottomHalf = cast<ConstantSDNode>(Cond.getOperand(i));
4756 else if (Cond->getOperand(i).getNode() != BottomHalf)
4760 // Do the same for the second half of the BuildVector
4761 ConstantSDNode *TopHalf = nullptr;
4762 for (int i = NumElems / 2; i < NumElems; ++i) {
4763 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
4766 if (TopHalf == nullptr)
4767 TopHalf = cast<ConstantSDNode>(Cond.getOperand(i));
4768 else if (Cond->getOperand(i).getNode() != TopHalf)
4772 assert(TopHalf && BottomHalf &&
4773 "One half of the selector was all UNDEFs and the other was all the "
4774 "same value. This should have been addressed before this function.");
4776 ISD::CONCAT_VECTORS, dl, VT,
4777 BottomHalf->isNullValue() ? RHS->getOperand(0) : LHS->getOperand(0),
4778 TopHalf->isNullValue() ? RHS->getOperand(1) : LHS->getOperand(1));
4781 SDValue DAGCombiner::visitMSTORE(SDNode *N) {
4783 if (Level >= AfterLegalizeTypes)
4786 MaskedStoreSDNode *MST = dyn_cast<MaskedStoreSDNode>(N);
4787 SDValue Mask = MST->getMask();
4788 SDValue Data = MST->getData();
4791 // If the MSTORE data type requires splitting and the mask is provided by a
4792 // SETCC, then split both nodes and its operands before legalization. This
4793 // prevents the type legalizer from unrolling SETCC into scalar comparisons
4794 // and enables future optimizations (e.g. min/max pattern matching on X86).
4795 if (Mask.getOpcode() == ISD::SETCC) {
4797 // Check if any splitting is required.
4798 if (TLI.getTypeAction(*DAG.getContext(), Data.getValueType()) !=
4799 TargetLowering::TypeSplitVector)
4802 SDValue MaskLo, MaskHi, Lo, Hi;
4803 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
4806 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MST->getValueType(0));
4808 SDValue Chain = MST->getChain();
4809 SDValue Ptr = MST->getBasePtr();
4811 EVT MemoryVT = MST->getMemoryVT();
4812 unsigned Alignment = MST->getOriginalAlignment();
4814 // if Alignment is equal to the vector size,
4815 // take the half of it for the second part
4816 unsigned SecondHalfAlignment =
4817 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
4818 Alignment/2 : Alignment;
4820 EVT LoMemVT, HiMemVT;
4821 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
4823 SDValue DataLo, DataHi;
4824 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
4826 MachineMemOperand *MMO = DAG.getMachineFunction().
4827 getMachineMemOperand(MST->getPointerInfo(),
4828 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
4829 Alignment, MST->getAAInfo(), MST->getRanges());
4831 Lo = DAG.getMaskedStore(Chain, DL, DataLo, Ptr, MaskLo, MMO);
4833 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
4834 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4835 DAG.getConstant(IncrementSize, Ptr.getValueType()));
4837 MMO = DAG.getMachineFunction().
4838 getMachineMemOperand(MST->getPointerInfo(),
4839 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
4840 SecondHalfAlignment, MST->getAAInfo(),
4843 Hi = DAG.getMaskedStore(Chain, DL, DataHi, Ptr, MaskHi, MMO);
4845 AddToWorklist(Lo.getNode());
4846 AddToWorklist(Hi.getNode());
4848 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
4853 SDValue DAGCombiner::visitMLOAD(SDNode *N) {
4855 if (Level >= AfterLegalizeTypes)
4858 MaskedLoadSDNode *MLD = dyn_cast<MaskedLoadSDNode>(N);
4859 SDValue Mask = MLD->getMask();
4862 // If the MLOAD result requires splitting and the mask is provided by a
4863 // SETCC, then split both nodes and its operands before legalization. This
4864 // prevents the type legalizer from unrolling SETCC into scalar comparisons
4865 // and enables future optimizations (e.g. min/max pattern matching on X86).
4867 if (Mask.getOpcode() == ISD::SETCC) {
4868 EVT VT = N->getValueType(0);
4870 // Check if any splitting is required.
4871 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
4872 TargetLowering::TypeSplitVector)
4875 SDValue MaskLo, MaskHi, Lo, Hi;
4876 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
4878 SDValue Src0 = MLD->getSrc0();
4879 SDValue Src0Lo, Src0Hi;
4880 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, DL);
4883 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
4885 SDValue Chain = MLD->getChain();
4886 SDValue Ptr = MLD->getBasePtr();
4887 EVT MemoryVT = MLD->getMemoryVT();
4888 unsigned Alignment = MLD->getOriginalAlignment();
4890 // if Alignment is equal to the vector size,
4891 // take the half of it for the second part
4892 unsigned SecondHalfAlignment =
4893 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
4894 Alignment/2 : Alignment;
4896 EVT LoMemVT, HiMemVT;
4897 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
4899 MachineMemOperand *MMO = DAG.getMachineFunction().
4900 getMachineMemOperand(MLD->getPointerInfo(),
4901 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
4902 Alignment, MLD->getAAInfo(), MLD->getRanges());
4904 Lo = DAG.getMaskedLoad(LoVT, DL, Chain, Ptr, MaskLo, Src0Lo, MMO);
4906 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
4907 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4908 DAG.getConstant(IncrementSize, Ptr.getValueType()));
4910 MMO = DAG.getMachineFunction().
4911 getMachineMemOperand(MLD->getPointerInfo(),
4912 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
4913 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
4915 Hi = DAG.getMaskedLoad(HiVT, DL, Chain, Ptr, MaskHi, Src0Hi, MMO);
4917 AddToWorklist(Lo.getNode());
4918 AddToWorklist(Hi.getNode());
4920 // Build a factor node to remember that this load is independent of the
4922 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo.getValue(1),
4925 // Legalized the chain result - switch anything that used the old chain to
4927 DAG.ReplaceAllUsesOfValueWith(SDValue(MLD, 1), Chain);
4929 SDValue LoadRes = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
4931 SDValue RetOps[] = { LoadRes, Chain };
4932 return DAG.getMergeValues(RetOps, DL);
4937 SDValue DAGCombiner::visitVSELECT(SDNode *N) {
4938 SDValue N0 = N->getOperand(0);
4939 SDValue N1 = N->getOperand(1);
4940 SDValue N2 = N->getOperand(2);
4943 // Canonicalize integer abs.
4944 // vselect (setg[te] X, 0), X, -X ->
4945 // vselect (setgt X, -1), X, -X ->
4946 // vselect (setl[te] X, 0), -X, X ->
4947 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4948 if (N0.getOpcode() == ISD::SETCC) {
4949 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
4950 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
4952 bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
4954 if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
4955 (ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) &&
4956 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
4957 isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode());
4958 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) &&
4959 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
4960 isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
4963 EVT VT = LHS.getValueType();
4964 SDValue Shift = DAG.getNode(
4965 ISD::SRA, DL, VT, LHS,
4966 DAG.getConstant(VT.getScalarType().getSizeInBits() - 1, VT));
4967 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift);
4968 AddToWorklist(Shift.getNode());
4969 AddToWorklist(Add.getNode());
4970 return DAG.getNode(ISD::XOR, DL, VT, Add, Shift);
4974 // If the VSELECT result requires splitting and the mask is provided by a
4975 // SETCC, then split both nodes and its operands before legalization. This
4976 // prevents the type legalizer from unrolling SETCC into scalar comparisons
4977 // and enables future optimizations (e.g. min/max pattern matching on X86).
4978 if (N0.getOpcode() == ISD::SETCC) {
4979 EVT VT = N->getValueType(0);
4981 // Check if any splitting is required.
4982 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
4983 TargetLowering::TypeSplitVector)
4986 SDValue Lo, Hi, CCLo, CCHi, LL, LH, RL, RH;
4987 std::tie(CCLo, CCHi) = SplitVSETCC(N0.getNode(), DAG);
4988 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 1);
4989 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 2);
4991 Lo = DAG.getNode(N->getOpcode(), DL, LL.getValueType(), CCLo, LL, RL);
4992 Hi = DAG.getNode(N->getOpcode(), DL, LH.getValueType(), CCHi, LH, RH);
4994 // Add the new VSELECT nodes to the work list in case they need to be split
4996 AddToWorklist(Lo.getNode());
4997 AddToWorklist(Hi.getNode());
4999 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
5002 // Fold (vselect (build_vector all_ones), N1, N2) -> N1
5003 if (ISD::isBuildVectorAllOnes(N0.getNode()))
5005 // Fold (vselect (build_vector all_zeros), N1, N2) -> N2
5006 if (ISD::isBuildVectorAllZeros(N0.getNode()))
5009 // The ConvertSelectToConcatVector function is assuming both the above
5010 // checks for (vselect (build_vector all{ones,zeros) ...) have been made
5012 if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
5013 N2.getOpcode() == ISD::CONCAT_VECTORS &&
5014 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
5015 SDValue CV = ConvertSelectToConcatVector(N, DAG);
5023 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
5024 SDValue N0 = N->getOperand(0);
5025 SDValue N1 = N->getOperand(1);
5026 SDValue N2 = N->getOperand(2);
5027 SDValue N3 = N->getOperand(3);
5028 SDValue N4 = N->getOperand(4);
5029 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
5031 // fold select_cc lhs, rhs, x, x, cc -> x
5035 // Determine if the condition we're dealing with is constant
5036 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
5037 N0, N1, CC, SDLoc(N), false);
5038 if (SCC.getNode()) {
5039 AddToWorklist(SCC.getNode());
5041 if (ConstantSDNode *SCCC = dyn_cast<ConstantSDNode>(SCC.getNode())) {
5042 if (!SCCC->isNullValue())
5043 return N2; // cond always true -> true val
5045 return N3; // cond always false -> false val
5048 // Fold to a simpler select_cc
5049 if (SCC.getOpcode() == ISD::SETCC)
5050 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(),
5051 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
5055 // If we can fold this based on the true/false value, do so.
5056 if (SimplifySelectOps(N, N2, N3))
5057 return SDValue(N, 0); // Don't revisit N.
5059 // fold select_cc into other things, such as min/max/abs
5060 return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC);
5063 SDValue DAGCombiner::visitSETCC(SDNode *N) {
5064 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
5065 cast<CondCodeSDNode>(N->getOperand(2))->get(),
5069 // tryToFoldExtendOfConstant - Try to fold a sext/zext/aext
5070 // dag node into a ConstantSDNode or a build_vector of constants.
5071 // This function is called by the DAGCombiner when visiting sext/zext/aext
5072 // dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
5073 // Vector extends are not folded if operations are legal; this is to
5074 // avoid introducing illegal build_vector dag nodes.
5075 static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
5076 SelectionDAG &DAG, bool LegalTypes,
5077 bool LegalOperations) {
5078 unsigned Opcode = N->getOpcode();
5079 SDValue N0 = N->getOperand(0);
5080 EVT VT = N->getValueType(0);
5082 assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND ||
5083 Opcode == ISD::ANY_EXTEND) && "Expected EXTEND dag node in input!");
5085 // fold (sext c1) -> c1
5086 // fold (zext c1) -> c1
5087 // fold (aext c1) -> c1
5088 if (isa<ConstantSDNode>(N0))
5089 return DAG.getNode(Opcode, SDLoc(N), VT, N0).getNode();
5091 // fold (sext (build_vector AllConstants) -> (build_vector AllConstants)
5092 // fold (zext (build_vector AllConstants) -> (build_vector AllConstants)
5093 // fold (aext (build_vector AllConstants) -> (build_vector AllConstants)
5094 EVT SVT = VT.getScalarType();
5095 if (!(VT.isVector() &&
5096 (!LegalTypes || (!LegalOperations && TLI.isTypeLegal(SVT))) &&
5097 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())))
5100 // We can fold this node into a build_vector.
5101 unsigned VTBits = SVT.getSizeInBits();
5102 unsigned EVTBits = N0->getValueType(0).getScalarType().getSizeInBits();
5103 unsigned ShAmt = VTBits - EVTBits;
5104 SmallVector<SDValue, 8> Elts;
5105 unsigned NumElts = N0->getNumOperands();
5108 for (unsigned i=0; i != NumElts; ++i) {
5109 SDValue Op = N0->getOperand(i);
5110 if (Op->getOpcode() == ISD::UNDEF) {
5111 Elts.push_back(DAG.getUNDEF(SVT));
5115 ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
5116 const APInt &C = APInt(VTBits, CurrentND->getAPIntValue().getZExtValue());
5117 if (Opcode == ISD::SIGN_EXTEND)
5118 Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt).getZExtValue(),
5121 Elts.push_back(DAG.getConstant(C.shl(ShAmt).lshr(ShAmt).getZExtValue(),
5125 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Elts).getNode();
5128 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
5129 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
5130 // transformation. Returns true if extension are possible and the above
5131 // mentioned transformation is profitable.
5132 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
5134 SmallVectorImpl<SDNode *> &ExtendNodes,
5135 const TargetLowering &TLI) {
5136 bool HasCopyToRegUses = false;
5137 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
5138 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
5139 UE = N0.getNode()->use_end();
5144 if (UI.getUse().getResNo() != N0.getResNo())
5146 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
5147 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
5148 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
5149 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
5150 // Sign bits will be lost after a zext.
5153 for (unsigned i = 0; i != 2; ++i) {
5154 SDValue UseOp = User->getOperand(i);
5157 if (!isa<ConstantSDNode>(UseOp))
5162 ExtendNodes.push_back(User);
5165 // If truncates aren't free and there are users we can't
5166 // extend, it isn't worthwhile.
5169 // Remember if this value is live-out.
5170 if (User->getOpcode() == ISD::CopyToReg)
5171 HasCopyToRegUses = true;
5174 if (HasCopyToRegUses) {
5175 bool BothLiveOut = false;
5176 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
5178 SDUse &Use = UI.getUse();
5179 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
5185 // Both unextended and extended values are live out. There had better be
5186 // a good reason for the transformation.
5187 return ExtendNodes.size();
5192 void DAGCombiner::ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
5193 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
5194 ISD::NodeType ExtType) {
5195 // Extend SetCC uses if necessary.
5196 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
5197 SDNode *SetCC = SetCCs[i];
5198 SmallVector<SDValue, 4> Ops;
5200 for (unsigned j = 0; j != 2; ++j) {
5201 SDValue SOp = SetCC->getOperand(j);
5203 Ops.push_back(ExtLoad);
5205 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
5208 Ops.push_back(SetCC->getOperand(2));
5209 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops));
5213 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
5214 SDValue N0 = N->getOperand(0);
5215 EVT VT = N->getValueType(0);
5217 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5219 return SDValue(Res, 0);
5221 // fold (sext (sext x)) -> (sext x)
5222 // fold (sext (aext x)) -> (sext x)
5223 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5224 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT,
5227 if (N0.getOpcode() == ISD::TRUNCATE) {
5228 // fold (sext (truncate (load x))) -> (sext (smaller load x))
5229 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
5230 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5231 if (NarrowLoad.getNode()) {
5232 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5233 if (NarrowLoad.getNode() != N0.getNode()) {
5234 CombineTo(N0.getNode(), NarrowLoad);
5235 // CombineTo deleted the truncate, if needed, but not what's under it.
5238 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5241 // See if the value being truncated is already sign extended. If so, just
5242 // eliminate the trunc/sext pair.
5243 SDValue Op = N0.getOperand(0);
5244 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
5245 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
5246 unsigned DestBits = VT.getScalarType().getSizeInBits();
5247 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
5249 if (OpBits == DestBits) {
5250 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
5251 // bits, it is already ready.
5252 if (NumSignBits > DestBits-MidBits)
5254 } else if (OpBits < DestBits) {
5255 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
5256 // bits, just sext from i32.
5257 if (NumSignBits > OpBits-MidBits)
5258 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, Op);
5260 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
5261 // bits, just truncate to i32.
5262 if (NumSignBits > OpBits-MidBits)
5263 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5266 // fold (sext (truncate x)) -> (sextinreg x).
5267 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
5268 N0.getValueType())) {
5269 if (OpBits < DestBits)
5270 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op);
5271 else if (OpBits > DestBits)
5272 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op);
5273 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, Op,
5274 DAG.getValueType(N0.getValueType()));
5278 // fold (sext (load x)) -> (sext (truncate (sextload x)))
5279 // None of the supported targets knows how to perform load and sign extend
5280 // on vectors in one instruction. We only perform this transformation on
5282 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5283 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5284 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5285 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
5286 bool DoXform = true;
5287 SmallVector<SDNode*, 4> SetCCs;
5288 if (!N0.hasOneUse())
5289 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
5291 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5292 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5294 LN0->getBasePtr(), N0.getValueType(),
5295 LN0->getMemOperand());
5296 CombineTo(N, ExtLoad);
5297 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5298 N0.getValueType(), ExtLoad);
5299 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5300 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5302 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5306 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
5307 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
5308 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
5309 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
5310 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5311 EVT MemVT = LN0->getMemoryVT();
5312 if ((!LegalOperations && !LN0->isVolatile()) ||
5313 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
5314 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5316 LN0->getBasePtr(), MemVT,
5317 LN0->getMemOperand());
5318 CombineTo(N, ExtLoad);
5319 CombineTo(N0.getNode(),
5320 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5321 N0.getValueType(), ExtLoad),
5322 ExtLoad.getValue(1));
5323 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5327 // fold (sext (and/or/xor (load x), cst)) ->
5328 // (and/or/xor (sextload x), (sext cst))
5329 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
5330 N0.getOpcode() == ISD::XOR) &&
5331 isa<LoadSDNode>(N0.getOperand(0)) &&
5332 N0.getOperand(1).getOpcode() == ISD::Constant &&
5333 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
5334 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
5335 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
5336 if (LN0->getExtensionType() != ISD::ZEXTLOAD && LN0->isUnindexed()) {
5337 bool DoXform = true;
5338 SmallVector<SDNode*, 4> SetCCs;
5339 if (!N0.hasOneUse())
5340 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
5343 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN0), VT,
5344 LN0->getChain(), LN0->getBasePtr(),
5346 LN0->getMemOperand());
5347 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5348 Mask = Mask.sext(VT.getSizeInBits());
5349 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
5350 ExtLoad, DAG.getConstant(Mask, VT));
5351 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
5352 SDLoc(N0.getOperand(0)),
5353 N0.getOperand(0).getValueType(), ExtLoad);
5355 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
5356 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5358 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5363 if (N0.getOpcode() == ISD::SETCC) {
5364 EVT N0VT = N0.getOperand(0).getValueType();
5365 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
5366 // Only do this before legalize for now.
5367 if (VT.isVector() && !LegalOperations &&
5368 TLI.getBooleanContents(N0VT) ==
5369 TargetLowering::ZeroOrNegativeOneBooleanContent) {
5370 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
5371 // of the same size as the compared operands. Only optimize sext(setcc())
5372 // if this is the case.
5373 EVT SVT = getSetCCResultType(N0VT);
5375 // We know that the # elements of the results is the same as the
5376 // # elements of the compare (and the # elements of the compare result
5377 // for that matter). Check to see that they are the same size. If so,
5378 // we know that the element size of the sext'd result matches the
5379 // element size of the compare operands.
5380 if (VT.getSizeInBits() == SVT.getSizeInBits())
5381 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5383 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5385 // If the desired elements are smaller or larger than the source
5386 // elements we can use a matching integer vector type and then
5387 // truncate/sign extend
5388 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
5389 if (SVT == MatchingVectorType) {
5390 SDValue VsetCC = DAG.getSetCC(SDLoc(N), MatchingVectorType,
5391 N0.getOperand(0), N0.getOperand(1),
5392 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5393 return DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT);
5397 // sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)
5398 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
5400 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
5402 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5403 NegOne, DAG.getConstant(0, VT),
5404 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5405 if (SCC.getNode()) return SCC;
5407 if (!VT.isVector()) {
5408 EVT SetCCVT = getSetCCResultType(N0.getOperand(0).getValueType());
5409 if (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, SetCCVT)) {
5411 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
5412 SDValue SetCC = DAG.getSetCC(DL, SetCCVT,
5413 N0.getOperand(0), N0.getOperand(1), CC);
5414 return DAG.getSelect(DL, VT, SetCC,
5415 NegOne, DAG.getConstant(0, VT));
5420 // fold (sext x) -> (zext x) if the sign bit is known zero.
5421 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
5422 DAG.SignBitIsZero(N0))
5423 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0);
5428 // isTruncateOf - If N is a truncate of some other value, return true, record
5429 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
5430 // This function computes KnownZero to avoid a duplicated call to
5431 // computeKnownBits in the caller.
5432 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
5435 if (N->getOpcode() == ISD::TRUNCATE) {
5436 Op = N->getOperand(0);
5437 DAG.computeKnownBits(Op, KnownZero, KnownOne);
5441 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
5442 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
5445 SDValue Op0 = N->getOperand(0);
5446 SDValue Op1 = N->getOperand(1);
5447 assert(Op0.getValueType() == Op1.getValueType());
5449 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0);
5450 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
5451 if (COp0 && COp0->isNullValue())
5453 else if (COp1 && COp1->isNullValue())
5458 DAG.computeKnownBits(Op, KnownZero, KnownOne);
5460 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
5466 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
5467 SDValue N0 = N->getOperand(0);
5468 EVT VT = N->getValueType(0);
5470 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5472 return SDValue(Res, 0);
5474 // fold (zext (zext x)) -> (zext x)
5475 // fold (zext (aext x)) -> (zext x)
5476 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5477 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT,
5480 // fold (zext (truncate x)) -> (zext x) or
5481 // (zext (truncate x)) -> (truncate x)
5482 // This is valid when the truncated bits of x are already zero.
5483 // FIXME: We should extend this to work for vectors too.
5486 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
5487 APInt TruncatedBits =
5488 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
5489 APInt(Op.getValueSizeInBits(), 0) :
5490 APInt::getBitsSet(Op.getValueSizeInBits(),
5491 N0.getValueSizeInBits(),
5492 std::min(Op.getValueSizeInBits(),
5493 VT.getSizeInBits()));
5494 if (TruncatedBits == (KnownZero & TruncatedBits)) {
5495 if (VT.bitsGT(Op.getValueType()))
5496 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, Op);
5497 if (VT.bitsLT(Op.getValueType()))
5498 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5504 // fold (zext (truncate (load x))) -> (zext (smaller load x))
5505 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
5506 if (N0.getOpcode() == ISD::TRUNCATE) {
5507 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5508 if (NarrowLoad.getNode()) {
5509 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5510 if (NarrowLoad.getNode() != N0.getNode()) {
5511 CombineTo(N0.getNode(), NarrowLoad);
5512 // CombineTo deleted the truncate, if needed, but not what's under it.
5515 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5519 // fold (zext (truncate x)) -> (and x, mask)
5520 if (N0.getOpcode() == ISD::TRUNCATE &&
5521 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
5523 // fold (zext (truncate (load x))) -> (zext (smaller load x))
5524 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
5525 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5526 if (NarrowLoad.getNode()) {
5527 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5528 if (NarrowLoad.getNode() != N0.getNode()) {
5529 CombineTo(N0.getNode(), NarrowLoad);
5530 // CombineTo deleted the truncate, if needed, but not what's under it.
5533 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5536 SDValue Op = N0.getOperand(0);
5537 if (Op.getValueType().bitsLT(VT)) {
5538 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Op);
5539 AddToWorklist(Op.getNode());
5540 } else if (Op.getValueType().bitsGT(VT)) {
5541 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5542 AddToWorklist(Op.getNode());
5544 return DAG.getZeroExtendInReg(Op, SDLoc(N),
5545 N0.getValueType().getScalarType());
5548 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
5549 // if either of the casts is not free.
5550 if (N0.getOpcode() == ISD::AND &&
5551 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
5552 N0.getOperand(1).getOpcode() == ISD::Constant &&
5553 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
5554 N0.getValueType()) ||
5555 !TLI.isZExtFree(N0.getValueType(), VT))) {
5556 SDValue X = N0.getOperand(0).getOperand(0);
5557 if (X.getValueType().bitsLT(VT)) {
5558 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(X), VT, X);
5559 } else if (X.getValueType().bitsGT(VT)) {
5560 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
5562 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5563 Mask = Mask.zext(VT.getSizeInBits());
5564 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5565 X, DAG.getConstant(Mask, VT));
5568 // fold (zext (load x)) -> (zext (truncate (zextload x)))
5569 // None of the supported targets knows how to perform load and vector_zext
5570 // on vectors in one instruction. We only perform this transformation on
5572 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5573 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5574 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5575 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
5576 bool DoXform = true;
5577 SmallVector<SDNode*, 4> SetCCs;
5578 if (!N0.hasOneUse())
5579 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
5581 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5582 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
5584 LN0->getBasePtr(), N0.getValueType(),
5585 LN0->getMemOperand());
5586 CombineTo(N, ExtLoad);
5587 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5588 N0.getValueType(), ExtLoad);
5589 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5591 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5593 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5597 // fold (zext (and/or/xor (load x), cst)) ->
5598 // (and/or/xor (zextload x), (zext cst))
5599 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
5600 N0.getOpcode() == ISD::XOR) &&
5601 isa<LoadSDNode>(N0.getOperand(0)) &&
5602 N0.getOperand(1).getOpcode() == ISD::Constant &&
5603 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
5604 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
5605 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
5606 if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed()) {
5607 bool DoXform = true;
5608 SmallVector<SDNode*, 4> SetCCs;
5609 if (!N0.hasOneUse())
5610 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
5613 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), VT,
5614 LN0->getChain(), LN0->getBasePtr(),
5616 LN0->getMemOperand());
5617 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5618 Mask = Mask.zext(VT.getSizeInBits());
5619 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
5620 ExtLoad, DAG.getConstant(Mask, VT));
5621 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
5622 SDLoc(N0.getOperand(0)),
5623 N0.getOperand(0).getValueType(), ExtLoad);
5625 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
5626 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5628 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5633 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
5634 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
5635 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
5636 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
5637 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5638 EVT MemVT = LN0->getMemoryVT();
5639 if ((!LegalOperations && !LN0->isVolatile()) ||
5640 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
5641 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
5643 LN0->getBasePtr(), MemVT,
5644 LN0->getMemOperand());
5645 CombineTo(N, ExtLoad);
5646 CombineTo(N0.getNode(),
5647 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(),
5649 ExtLoad.getValue(1));
5650 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5654 if (N0.getOpcode() == ISD::SETCC) {
5655 if (!LegalOperations && VT.isVector() &&
5656 N0.getValueType().getVectorElementType() == MVT::i1) {
5657 EVT N0VT = N0.getOperand(0).getValueType();
5658 if (getSetCCResultType(N0VT) == N0.getValueType())
5661 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
5662 // Only do this before legalize for now.
5663 EVT EltVT = VT.getVectorElementType();
5664 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
5665 DAG.getConstant(1, EltVT));
5666 if (VT.getSizeInBits() == N0VT.getSizeInBits())
5667 // We know that the # elements of the results is the same as the
5668 // # elements of the compare (and the # elements of the compare result
5669 // for that matter). Check to see that they are the same size. If so,
5670 // we know that the element size of the sext'd result matches the
5671 // element size of the compare operands.
5672 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5673 DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5675 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
5676 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT,
5679 // If the desired elements are smaller or larger than the source
5680 // elements we can use a matching integer vector type and then
5681 // truncate/sign extend
5682 EVT MatchingElementType =
5683 EVT::getIntegerVT(*DAG.getContext(),
5684 N0VT.getScalarType().getSizeInBits());
5685 EVT MatchingVectorType =
5686 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
5687 N0VT.getVectorNumElements());
5689 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
5691 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5692 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5693 DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT),
5694 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, OneOps));
5697 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
5699 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5700 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
5701 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5702 if (SCC.getNode()) return SCC;
5705 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
5706 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
5707 isa<ConstantSDNode>(N0.getOperand(1)) &&
5708 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
5710 SDValue ShAmt = N0.getOperand(1);
5711 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
5712 if (N0.getOpcode() == ISD::SHL) {
5713 SDValue InnerZExt = N0.getOperand(0);
5714 // If the original shl may be shifting out bits, do not perform this
5716 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
5717 InnerZExt.getOperand(0).getValueType().getSizeInBits();
5718 if (ShAmtVal > KnownZeroBits)
5724 // Ensure that the shift amount is wide enough for the shifted value.
5725 if (VT.getSizeInBits() >= 256)
5726 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
5728 return DAG.getNode(N0.getOpcode(), DL, VT,
5729 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
5736 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
5737 SDValue N0 = N->getOperand(0);
5738 EVT VT = N->getValueType(0);
5740 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5742 return SDValue(Res, 0);
5744 // fold (aext (aext x)) -> (aext x)
5745 // fold (aext (zext x)) -> (zext x)
5746 // fold (aext (sext x)) -> (sext x)
5747 if (N0.getOpcode() == ISD::ANY_EXTEND ||
5748 N0.getOpcode() == ISD::ZERO_EXTEND ||
5749 N0.getOpcode() == ISD::SIGN_EXTEND)
5750 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0));
5752 // fold (aext (truncate (load x))) -> (aext (smaller load x))
5753 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
5754 if (N0.getOpcode() == ISD::TRUNCATE) {
5755 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5756 if (NarrowLoad.getNode()) {
5757 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5758 if (NarrowLoad.getNode() != N0.getNode()) {
5759 CombineTo(N0.getNode(), NarrowLoad);
5760 // CombineTo deleted the truncate, if needed, but not what's under it.
5763 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5767 // fold (aext (truncate x))
5768 if (N0.getOpcode() == ISD::TRUNCATE) {
5769 SDValue TruncOp = N0.getOperand(0);
5770 if (TruncOp.getValueType() == VT)
5771 return TruncOp; // x iff x size == zext size.
5772 if (TruncOp.getValueType().bitsGT(VT))
5773 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, TruncOp);
5774 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, TruncOp);
5777 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
5778 // if the trunc is not free.
5779 if (N0.getOpcode() == ISD::AND &&
5780 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
5781 N0.getOperand(1).getOpcode() == ISD::Constant &&
5782 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
5783 N0.getValueType())) {
5784 SDValue X = N0.getOperand(0).getOperand(0);
5785 if (X.getValueType().bitsLT(VT)) {
5786 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, X);
5787 } else if (X.getValueType().bitsGT(VT)) {
5788 X = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, X);
5790 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5791 Mask = Mask.zext(VT.getSizeInBits());
5792 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5793 X, DAG.getConstant(Mask, VT));
5796 // fold (aext (load x)) -> (aext (truncate (extload x)))
5797 // None of the supported targets knows how to perform load and any_ext
5798 // on vectors in one instruction. We only perform this transformation on
5800 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5801 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5802 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType())) {
5803 bool DoXform = true;
5804 SmallVector<SDNode*, 4> SetCCs;
5805 if (!N0.hasOneUse())
5806 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
5808 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5809 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
5811 LN0->getBasePtr(), N0.getValueType(),
5812 LN0->getMemOperand());
5813 CombineTo(N, ExtLoad);
5814 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5815 N0.getValueType(), ExtLoad);
5816 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5817 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5819 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5823 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
5824 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
5825 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
5826 if (N0.getOpcode() == ISD::LOAD &&
5827 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5829 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5830 ISD::LoadExtType ExtType = LN0->getExtensionType();
5831 EVT MemVT = LN0->getMemoryVT();
5832 if (!LegalOperations || TLI.isLoadExtLegal(ExtType, MemVT)) {
5833 SDValue ExtLoad = DAG.getExtLoad(ExtType, SDLoc(N),
5834 VT, LN0->getChain(), LN0->getBasePtr(),
5835 MemVT, LN0->getMemOperand());
5836 CombineTo(N, ExtLoad);
5837 CombineTo(N0.getNode(),
5838 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5839 N0.getValueType(), ExtLoad),
5840 ExtLoad.getValue(1));
5841 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5845 if (N0.getOpcode() == ISD::SETCC) {
5847 // aext(setcc) -> vsetcc
5848 // aext(setcc) -> truncate(vsetcc)
5849 // aext(setcc) -> aext(vsetcc)
5850 // Only do this before legalize for now.
5851 if (VT.isVector() && !LegalOperations) {
5852 EVT N0VT = N0.getOperand(0).getValueType();
5853 // We know that the # elements of the results is the same as the
5854 // # elements of the compare (and the # elements of the compare result
5855 // for that matter). Check to see that they are the same size. If so,
5856 // we know that the element size of the sext'd result matches the
5857 // element size of the compare operands.
5858 if (VT.getSizeInBits() == N0VT.getSizeInBits())
5859 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5861 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5862 // If the desired elements are smaller or larger than the source
5863 // elements we can use a matching integer vector type and then
5864 // truncate/any extend
5866 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
5868 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
5870 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5871 return DAG.getAnyExtOrTrunc(VsetCC, SDLoc(N), VT);
5875 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
5877 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5878 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
5879 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5887 /// See if the specified operand can be simplified with the knowledge that only
5888 /// the bits specified by Mask are used. If so, return the simpler operand,
5889 /// otherwise return a null SDValue.
5890 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
5891 switch (V.getOpcode()) {
5893 case ISD::Constant: {
5894 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
5895 assert(CV && "Const value should be ConstSDNode.");
5896 const APInt &CVal = CV->getAPIntValue();
5897 APInt NewVal = CVal & Mask;
5899 return DAG.getConstant(NewVal, V.getValueType());
5904 // If the LHS or RHS don't contribute bits to the or, drop them.
5905 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
5906 return V.getOperand(1);
5907 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
5908 return V.getOperand(0);
5911 // Only look at single-use SRLs.
5912 if (!V.getNode()->hasOneUse())
5914 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
5915 // See if we can recursively simplify the LHS.
5916 unsigned Amt = RHSC->getZExtValue();
5918 // Watch out for shift count overflow though.
5919 if (Amt >= Mask.getBitWidth()) break;
5920 APInt NewMask = Mask << Amt;
5921 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
5922 if (SimplifyLHS.getNode())
5923 return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(),
5924 SimplifyLHS, V.getOperand(1));
5930 /// If the result of a wider load is shifted to right of N bits and then
5931 /// truncated to a narrower type and where N is a multiple of number of bits of
5932 /// the narrower type, transform it to a narrower load from address + N / num of
5933 /// bits of new type. If the result is to be extended, also fold the extension
5934 /// to form a extending load.
5935 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
5936 unsigned Opc = N->getOpcode();
5938 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
5939 SDValue N0 = N->getOperand(0);
5940 EVT VT = N->getValueType(0);
5943 // This transformation isn't valid for vector loads.
5947 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
5949 if (Opc == ISD::SIGN_EXTEND_INREG) {
5950 ExtType = ISD::SEXTLOAD;
5951 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5952 } else if (Opc == ISD::SRL) {
5953 // Another special-case: SRL is basically zero-extending a narrower value.
5954 ExtType = ISD::ZEXTLOAD;
5956 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5957 if (!N01) return SDValue();
5958 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
5959 VT.getSizeInBits() - N01->getZExtValue());
5961 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
5964 unsigned EVTBits = ExtVT.getSizeInBits();
5966 // Do not generate loads of non-round integer types since these can
5967 // be expensive (and would be wrong if the type is not byte sized).
5968 if (!ExtVT.isRound())
5972 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5973 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5974 ShAmt = N01->getZExtValue();
5975 // Is the shift amount a multiple of size of VT?
5976 if ((ShAmt & (EVTBits-1)) == 0) {
5977 N0 = N0.getOperand(0);
5978 // Is the load width a multiple of size of VT?
5979 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
5983 // At this point, we must have a load or else we can't do the transform.
5984 if (!isa<LoadSDNode>(N0)) return SDValue();
5986 // Because a SRL must be assumed to *need* to zero-extend the high bits
5987 // (as opposed to anyext the high bits), we can't combine the zextload
5988 // lowering of SRL and an sextload.
5989 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD)
5992 // If the shift amount is larger than the input type then we're not
5993 // accessing any of the loaded bytes. If the load was a zextload/extload
5994 // then the result of the shift+trunc is zero/undef (handled elsewhere).
5995 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
6000 // If the load is shifted left (and the result isn't shifted back right),
6001 // we can fold the truncate through the shift.
6002 unsigned ShLeftAmt = 0;
6003 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
6004 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
6005 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
6006 ShLeftAmt = N01->getZExtValue();
6007 N0 = N0.getOperand(0);
6011 // If we haven't found a load, we can't narrow it. Don't transform one with
6012 // multiple uses, this would require adding a new load.
6013 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse())
6016 // Don't change the width of a volatile load.
6017 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6018 if (LN0->isVolatile())
6021 // Verify that we are actually reducing a load width here.
6022 if (LN0->getMemoryVT().getSizeInBits() < EVTBits)
6025 // For the transform to be legal, the load must produce only two values
6026 // (the value loaded and the chain). Don't transform a pre-increment
6027 // load, for example, which produces an extra value. Otherwise the
6028 // transformation is not equivalent, and the downstream logic to replace
6029 // uses gets things wrong.
6030 if (LN0->getNumValues() > 2)
6033 // If the load that we're shrinking is an extload and we're not just
6034 // discarding the extension we can't simply shrink the load. Bail.
6035 // TODO: It would be possible to merge the extensions in some cases.
6036 if (LN0->getExtensionType() != ISD::NON_EXTLOAD &&
6037 LN0->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits() + ShAmt)
6040 if (!TLI.shouldReduceLoadWidth(LN0, ExtType, ExtVT))
6043 EVT PtrType = N0.getOperand(1).getValueType();
6045 if (PtrType == MVT::Untyped || PtrType.isExtended())
6046 // It's not possible to generate a constant of extended or untyped type.
6049 // For big endian targets, we need to adjust the offset to the pointer to
6050 // load the correct bytes.
6051 if (TLI.isBigEndian()) {
6052 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
6053 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
6054 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
6057 uint64_t PtrOff = ShAmt / 8;
6058 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
6059 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0),
6060 PtrType, LN0->getBasePtr(),
6061 DAG.getConstant(PtrOff, PtrType));
6062 AddToWorklist(NewPtr.getNode());
6065 if (ExtType == ISD::NON_EXTLOAD)
6066 Load = DAG.getLoad(VT, SDLoc(N0), LN0->getChain(), NewPtr,
6067 LN0->getPointerInfo().getWithOffset(PtrOff),
6068 LN0->isVolatile(), LN0->isNonTemporal(),
6069 LN0->isInvariant(), NewAlign, LN0->getAAInfo());
6071 Load = DAG.getExtLoad(ExtType, SDLoc(N0), VT, LN0->getChain(),NewPtr,
6072 LN0->getPointerInfo().getWithOffset(PtrOff),
6073 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
6074 LN0->isInvariant(), NewAlign, LN0->getAAInfo());
6076 // Replace the old load's chain with the new load's chain.
6077 WorklistRemover DeadNodes(*this);
6078 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
6080 // Shift the result left, if we've swallowed a left shift.
6081 SDValue Result = Load;
6082 if (ShLeftAmt != 0) {
6083 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
6084 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
6086 // If the shift amount is as large as the result size (but, presumably,
6087 // no larger than the source) then the useful bits of the result are
6088 // zero; we can't simply return the shortened shift, because the result
6089 // of that operation is undefined.
6090 if (ShLeftAmt >= VT.getSizeInBits())
6091 Result = DAG.getConstant(0, VT);
6093 Result = DAG.getNode(ISD::SHL, SDLoc(N0), VT,
6094 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
6097 // Return the new loaded value.
6101 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
6102 SDValue N0 = N->getOperand(0);
6103 SDValue N1 = N->getOperand(1);
6104 EVT VT = N->getValueType(0);
6105 EVT EVT = cast<VTSDNode>(N1)->getVT();
6106 unsigned VTBits = VT.getScalarType().getSizeInBits();
6107 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
6109 // fold (sext_in_reg c1) -> c1
6110 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
6111 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1);
6113 // If the input is already sign extended, just drop the extension.
6114 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
6117 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
6118 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
6119 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT()))
6120 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
6121 N0.getOperand(0), N1);
6123 // fold (sext_in_reg (sext x)) -> (sext x)
6124 // fold (sext_in_reg (aext x)) -> (sext x)
6125 // if x is small enough.
6126 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
6127 SDValue N00 = N0.getOperand(0);
6128 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
6129 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
6130 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1);
6133 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
6134 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
6135 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT);
6137 // fold operands of sext_in_reg based on knowledge that the top bits are not
6139 if (SimplifyDemandedBits(SDValue(N, 0)))
6140 return SDValue(N, 0);
6142 // fold (sext_in_reg (load x)) -> (smaller sextload x)
6143 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
6144 SDValue NarrowLoad = ReduceLoadWidth(N);
6145 if (NarrowLoad.getNode())
6148 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
6149 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
6150 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
6151 if (N0.getOpcode() == ISD::SRL) {
6152 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
6153 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
6154 // We can turn this into an SRA iff the input to the SRL is already sign
6156 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
6157 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
6158 return DAG.getNode(ISD::SRA, SDLoc(N), VT,
6159 N0.getOperand(0), N0.getOperand(1));
6163 // fold (sext_inreg (extload x)) -> (sextload x)
6164 if (ISD::isEXTLoad(N0.getNode()) &&
6165 ISD::isUNINDEXEDLoad(N0.getNode()) &&
6166 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
6167 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6168 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
6169 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6170 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
6172 LN0->getBasePtr(), EVT,
6173 LN0->getMemOperand());
6174 CombineTo(N, ExtLoad);
6175 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
6176 AddToWorklist(ExtLoad.getNode());
6177 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6179 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
6180 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
6182 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
6183 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6184 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
6185 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6186 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
6188 LN0->getBasePtr(), EVT,
6189 LN0->getMemOperand());
6190 CombineTo(N, ExtLoad);
6191 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
6192 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6195 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
6196 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
6197 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
6198 N0.getOperand(1), false);
6199 if (BSwap.getNode())
6200 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
6204 // Fold a sext_inreg of a build_vector of ConstantSDNodes or undefs
6205 // into a build_vector.
6206 if (ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
6207 SmallVector<SDValue, 8> Elts;
6208 unsigned NumElts = N0->getNumOperands();
6209 unsigned ShAmt = VTBits - EVTBits;
6211 for (unsigned i = 0; i != NumElts; ++i) {
6212 SDValue Op = N0->getOperand(i);
6213 if (Op->getOpcode() == ISD::UNDEF) {
6218 ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
6219 const APInt &C = APInt(VTBits, CurrentND->getAPIntValue().getZExtValue());
6220 Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt).getZExtValue(),
6221 Op.getValueType()));
6224 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Elts);
6230 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
6231 SDValue N0 = N->getOperand(0);
6232 EVT VT = N->getValueType(0);
6233 bool isLE = TLI.isLittleEndian();
6236 if (N0.getValueType() == N->getValueType(0))
6238 // fold (truncate c1) -> c1
6239 if (isa<ConstantSDNode>(N0))
6240 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0);
6241 // fold (truncate (truncate x)) -> (truncate x)
6242 if (N0.getOpcode() == ISD::TRUNCATE)
6243 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
6244 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
6245 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
6246 N0.getOpcode() == ISD::SIGN_EXTEND ||
6247 N0.getOpcode() == ISD::ANY_EXTEND) {
6248 if (N0.getOperand(0).getValueType().bitsLT(VT))
6249 // if the source is smaller than the dest, we still need an extend
6250 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
6252 if (N0.getOperand(0).getValueType().bitsGT(VT))
6253 // if the source is larger than the dest, than we just need the truncate
6254 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
6255 // if the source and dest are the same type, we can drop both the extend
6256 // and the truncate.
6257 return N0.getOperand(0);
6260 // Fold extract-and-trunc into a narrow extract. For example:
6261 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
6262 // i32 y = TRUNCATE(i64 x)
6264 // v16i8 b = BITCAST (v2i64 val)
6265 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
6267 // Note: We only run this optimization after type legalization (which often
6268 // creates this pattern) and before operation legalization after which
6269 // we need to be more careful about the vector instructions that we generate.
6270 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6271 LegalTypes && !LegalOperations && N0->hasOneUse() && VT != MVT::i1) {
6273 EVT VecTy = N0.getOperand(0).getValueType();
6274 EVT ExTy = N0.getValueType();
6275 EVT TrTy = N->getValueType(0);
6277 unsigned NumElem = VecTy.getVectorNumElements();
6278 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
6280 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
6281 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
6283 SDValue EltNo = N0->getOperand(1);
6284 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
6285 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6286 EVT IndexTy = TLI.getVectorIdxTy();
6287 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
6289 SDValue V = DAG.getNode(ISD::BITCAST, SDLoc(N),
6290 NVT, N0.getOperand(0));
6292 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
6294 DAG.getConstant(Index, IndexTy));
6298 // trunc (select c, a, b) -> select c, (trunc a), (trunc b)
6299 if (N0.getOpcode() == ISD::SELECT) {
6300 EVT SrcVT = N0.getValueType();
6301 if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) &&
6302 TLI.isTruncateFree(SrcVT, VT)) {
6304 SDValue Cond = N0.getOperand(0);
6305 SDValue TruncOp0 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
6306 SDValue TruncOp1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(2));
6307 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, Cond, TruncOp0, TruncOp1);
6311 // Fold a series of buildvector, bitcast, and truncate if possible.
6313 // (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to
6314 // (2xi32 (buildvector x, y)).
6315 if (Level == AfterLegalizeVectorOps && VT.isVector() &&
6316 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
6317 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
6318 N0.getOperand(0).hasOneUse()) {
6320 SDValue BuildVect = N0.getOperand(0);
6321 EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType();
6322 EVT TruncVecEltTy = VT.getVectorElementType();
6324 // Check that the element types match.
6325 if (BuildVectEltTy == TruncVecEltTy) {
6326 // Now we only need to compute the offset of the truncated elements.
6327 unsigned BuildVecNumElts = BuildVect.getNumOperands();
6328 unsigned TruncVecNumElts = VT.getVectorNumElements();
6329 unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts;
6331 assert((BuildVecNumElts % TruncVecNumElts) == 0 &&
6332 "Invalid number of elements");
6334 SmallVector<SDValue, 8> Opnds;
6335 for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset)
6336 Opnds.push_back(BuildVect.getOperand(i));
6338 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
6342 // See if we can simplify the input to this truncate through knowledge that
6343 // only the low bits are being used.
6344 // For example "trunc (or (shl x, 8), y)" // -> trunc y
6345 // Currently we only perform this optimization on scalars because vectors
6346 // may have different active low bits.
6347 if (!VT.isVector()) {
6349 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
6350 VT.getSizeInBits()));
6351 if (Shorter.getNode())
6352 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Shorter);
6354 // fold (truncate (load x)) -> (smaller load x)
6355 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
6356 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
6357 SDValue Reduced = ReduceLoadWidth(N);
6358 if (Reduced.getNode())
6360 // Handle the case where the load remains an extending load even
6361 // after truncation.
6362 if (N0.hasOneUse() && ISD::isUNINDEXEDLoad(N0.getNode())) {
6363 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6364 if (!LN0->isVolatile() &&
6365 LN0->getMemoryVT().getStoreSizeInBits() < VT.getSizeInBits()) {
6366 SDValue NewLoad = DAG.getExtLoad(LN0->getExtensionType(), SDLoc(LN0),
6367 VT, LN0->getChain(), LN0->getBasePtr(),
6369 LN0->getMemOperand());
6370 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLoad.getValue(1));
6375 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)),
6376 // where ... are all 'undef'.
6377 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
6378 SmallVector<EVT, 8> VTs;
6381 unsigned NumDefs = 0;
6383 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
6384 SDValue X = N0.getOperand(i);
6385 if (X.getOpcode() != ISD::UNDEF) {
6390 // Stop if more than one members are non-undef.
6393 VTs.push_back(EVT::getVectorVT(*DAG.getContext(),
6394 VT.getVectorElementType(),
6395 X.getValueType().getVectorNumElements()));
6399 return DAG.getUNDEF(VT);
6402 assert(V.getNode() && "The single defined operand is empty!");
6403 SmallVector<SDValue, 8> Opnds;
6404 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
6406 Opnds.push_back(DAG.getUNDEF(VTs[i]));
6409 SDValue NV = DAG.getNode(ISD::TRUNCATE, SDLoc(V), VTs[i], V);
6410 AddToWorklist(NV.getNode());
6411 Opnds.push_back(NV);
6413 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds);
6417 // Simplify the operands using demanded-bits information.
6418 if (!VT.isVector() &&
6419 SimplifyDemandedBits(SDValue(N, 0)))
6420 return SDValue(N, 0);
6425 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
6426 SDValue Elt = N->getOperand(i);
6427 if (Elt.getOpcode() != ISD::MERGE_VALUES)
6428 return Elt.getNode();
6429 return Elt.getOperand(Elt.getResNo()).getNode();
6432 /// build_pair (load, load) -> load
6433 /// if load locations are consecutive.
6434 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
6435 assert(N->getOpcode() == ISD::BUILD_PAIR);
6437 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
6438 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
6439 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
6440 LD1->getAddressSpace() != LD2->getAddressSpace())
6442 EVT LD1VT = LD1->getValueType(0);
6444 if (ISD::isNON_EXTLoad(LD2) &&
6446 // If both are volatile this would reduce the number of volatile loads.
6447 // If one is volatile it might be ok, but play conservative and bail out.
6448 !LD1->isVolatile() &&
6449 !LD2->isVolatile() &&
6450 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
6451 unsigned Align = LD1->getAlignment();
6452 unsigned NewAlign = TLI.getDataLayout()->
6453 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
6455 if (NewAlign <= Align &&
6456 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
6457 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(),
6458 LD1->getBasePtr(), LD1->getPointerInfo(),
6459 false, false, false, Align);
6465 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
6466 SDValue N0 = N->getOperand(0);
6467 EVT VT = N->getValueType(0);
6469 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
6470 // Only do this before legalize, since afterward the target may be depending
6471 // on the bitconvert.
6472 // First check to see if this is all constant.
6474 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
6476 bool isSimple = cast<BuildVectorSDNode>(N0)->isConstant();
6478 EVT DestEltVT = N->getValueType(0).getVectorElementType();
6479 assert(!DestEltVT.isVector() &&
6480 "Element type of vector ValueType must not be vector!");
6482 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
6485 // If the input is a constant, let getNode fold it.
6486 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
6487 SDValue Res = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, N0);
6488 if (Res.getNode() != N) {
6489 if (!LegalOperations ||
6490 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
6493 // Folding it resulted in an illegal node, and it's too late to
6494 // do that. Clean up the old node and forego the transformation.
6495 // Ideally this won't happen very often, because instcombine
6496 // and the earlier dagcombine runs (where illegal nodes are
6497 // permitted) should have folded most of them already.
6498 deleteAndRecombine(Res.getNode());
6502 // (conv (conv x, t1), t2) -> (conv x, t2)
6503 if (N0.getOpcode() == ISD::BITCAST)
6504 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT,
6507 // fold (conv (load x)) -> (load (conv*)x)
6508 // If the resultant load doesn't need a higher alignment than the original!
6509 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6510 // Do not change the width of a volatile load.
6511 !cast<LoadSDNode>(N0)->isVolatile() &&
6512 // Do not remove the cast if the types differ in endian layout.
6513 TLI.hasBigEndianPartOrdering(N0.getValueType()) ==
6514 TLI.hasBigEndianPartOrdering(VT) &&
6515 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)) &&
6516 TLI.isLoadBitCastBeneficial(N0.getValueType(), VT)) {
6517 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6518 unsigned Align = TLI.getDataLayout()->
6519 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
6520 unsigned OrigAlign = LN0->getAlignment();
6522 if (Align <= OrigAlign) {
6523 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(),
6524 LN0->getBasePtr(), LN0->getPointerInfo(),
6525 LN0->isVolatile(), LN0->isNonTemporal(),
6526 LN0->isInvariant(), OrigAlign,
6528 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
6533 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
6534 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
6535 // This often reduces constant pool loads.
6536 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
6537 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
6538 N0.getNode()->hasOneUse() && VT.isInteger() &&
6539 !VT.isVector() && !N0.getValueType().isVector()) {
6540 SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT,
6542 AddToWorklist(NewConv.getNode());
6544 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
6545 if (N0.getOpcode() == ISD::FNEG)
6546 return DAG.getNode(ISD::XOR, SDLoc(N), VT,
6547 NewConv, DAG.getConstant(SignBit, VT));
6548 assert(N0.getOpcode() == ISD::FABS);
6549 return DAG.getNode(ISD::AND, SDLoc(N), VT,
6550 NewConv, DAG.getConstant(~SignBit, VT));
6553 // fold (bitconvert (fcopysign cst, x)) ->
6554 // (or (and (bitconvert x), sign), (and cst, (not sign)))
6555 // Note that we don't handle (copysign x, cst) because this can always be
6556 // folded to an fneg or fabs.
6557 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
6558 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
6559 VT.isInteger() && !VT.isVector()) {
6560 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
6561 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
6562 if (isTypeLegal(IntXVT)) {
6563 SDValue X = DAG.getNode(ISD::BITCAST, SDLoc(N0),
6564 IntXVT, N0.getOperand(1));
6565 AddToWorklist(X.getNode());
6567 // If X has a different width than the result/lhs, sext it or truncate it.
6568 unsigned VTWidth = VT.getSizeInBits();
6569 if (OrigXWidth < VTWidth) {
6570 X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X);
6571 AddToWorklist(X.getNode());
6572 } else if (OrigXWidth > VTWidth) {
6573 // To get the sign bit in the right place, we have to shift it right
6574 // before truncating.
6575 X = DAG.getNode(ISD::SRL, SDLoc(X),
6576 X.getValueType(), X,
6577 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
6578 AddToWorklist(X.getNode());
6579 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
6580 AddToWorklist(X.getNode());
6583 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
6584 X = DAG.getNode(ISD::AND, SDLoc(X), VT,
6585 X, DAG.getConstant(SignBit, VT));
6586 AddToWorklist(X.getNode());
6588 SDValue Cst = DAG.getNode(ISD::BITCAST, SDLoc(N0),
6589 VT, N0.getOperand(0));
6590 Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT,
6591 Cst, DAG.getConstant(~SignBit, VT));
6592 AddToWorklist(Cst.getNode());
6594 return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst);
6598 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
6599 if (N0.getOpcode() == ISD::BUILD_PAIR) {
6600 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
6601 if (CombineLD.getNode())
6608 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
6609 EVT VT = N->getValueType(0);
6610 return CombineConsecutiveLoads(N, VT);
6613 /// We know that BV is a build_vector node with Constant, ConstantFP or Undef
6614 /// operands. DstEltVT indicates the destination element value type.
6615 SDValue DAGCombiner::
6616 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
6617 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
6619 // If this is already the right type, we're done.
6620 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
6622 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
6623 unsigned DstBitSize = DstEltVT.getSizeInBits();
6625 // If this is a conversion of N elements of one type to N elements of another
6626 // type, convert each element. This handles FP<->INT cases.
6627 if (SrcBitSize == DstBitSize) {
6628 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
6629 BV->getValueType(0).getVectorNumElements());
6631 // Due to the FP element handling below calling this routine recursively,
6632 // we can end up with a scalar-to-vector node here.
6633 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
6634 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
6635 DAG.getNode(ISD::BITCAST, SDLoc(BV),
6636 DstEltVT, BV->getOperand(0)));
6638 SmallVector<SDValue, 8> Ops;
6639 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
6640 SDValue Op = BV->getOperand(i);
6641 // If the vector element type is not legal, the BUILD_VECTOR operands
6642 // are promoted and implicitly truncated. Make that explicit here.
6643 if (Op.getValueType() != SrcEltVT)
6644 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(BV), SrcEltVT, Op);
6645 Ops.push_back(DAG.getNode(ISD::BITCAST, SDLoc(BV),
6647 AddToWorklist(Ops.back().getNode());
6649 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6652 // Otherwise, we're growing or shrinking the elements. To avoid having to
6653 // handle annoying details of growing/shrinking FP values, we convert them to
6655 if (SrcEltVT.isFloatingPoint()) {
6656 // Convert the input float vector to a int vector where the elements are the
6658 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
6659 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
6663 // Now we know the input is an integer vector. If the output is a FP type,
6664 // convert to integer first, then to FP of the right size.
6665 if (DstEltVT.isFloatingPoint()) {
6666 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
6667 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
6669 // Next, convert to FP elements of the same size.
6670 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
6673 // Okay, we know the src/dst types are both integers of differing types.
6674 // Handling growing first.
6675 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
6676 if (SrcBitSize < DstBitSize) {
6677 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
6679 SmallVector<SDValue, 8> Ops;
6680 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
6681 i += NumInputsPerOutput) {
6682 bool isLE = TLI.isLittleEndian();
6683 APInt NewBits = APInt(DstBitSize, 0);
6684 bool EltIsUndef = true;
6685 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
6686 // Shift the previously computed bits over.
6687 NewBits <<= SrcBitSize;
6688 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
6689 if (Op.getOpcode() == ISD::UNDEF) continue;
6692 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
6693 zextOrTrunc(SrcBitSize).zext(DstBitSize);
6697 Ops.push_back(DAG.getUNDEF(DstEltVT));
6699 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
6702 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
6703 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6706 // Finally, this must be the case where we are shrinking elements: each input
6707 // turns into multiple outputs.
6708 bool isS2V = ISD::isScalarToVector(BV);
6709 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
6710 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
6711 NumOutputsPerInput*BV->getNumOperands());
6712 SmallVector<SDValue, 8> Ops;
6714 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
6715 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
6716 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
6717 Ops.push_back(DAG.getUNDEF(DstEltVT));
6721 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
6722 getAPIntValue().zextOrTrunc(SrcBitSize);
6724 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
6725 APInt ThisVal = OpVal.trunc(DstBitSize);
6726 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
6727 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
6728 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
6729 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
6731 OpVal = OpVal.lshr(DstBitSize);
6734 // For big endian targets, swap the order of the pieces of each element.
6735 if (TLI.isBigEndian())
6736 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
6739 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6742 SDValue DAGCombiner::visitFADD(SDNode *N) {
6743 SDValue N0 = N->getOperand(0);
6744 SDValue N1 = N->getOperand(1);
6745 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6746 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6747 EVT VT = N->getValueType(0);
6748 const TargetOptions &Options = DAG.getTarget().Options;
6751 if (VT.isVector()) {
6752 SDValue FoldedVOp = SimplifyVBinOp(N);
6753 if (FoldedVOp.getNode()) return FoldedVOp;
6756 // fold (fadd c1, c2) -> c1 + c2
6758 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N1);
6760 // canonicalize constant to RHS
6761 if (N0CFP && !N1CFP)
6762 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N0);
6764 // fold (fadd A, (fneg B)) -> (fsub A, B)
6765 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
6766 isNegatibleForFree(N1, LegalOperations, TLI, &Options) == 2)
6767 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0,
6768 GetNegatedExpression(N1, DAG, LegalOperations));
6770 // fold (fadd (fneg A), B) -> (fsub B, A)
6771 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
6772 isNegatibleForFree(N0, LegalOperations, TLI, &Options) == 2)
6773 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N1,
6774 GetNegatedExpression(N0, DAG, LegalOperations));
6776 // If 'unsafe math' is enabled, fold lots of things.
6777 if (Options.UnsafeFPMath) {
6778 // No FP constant should be created after legalization as Instruction
6779 // Selection pass has a hard time dealing with FP constants.
6780 bool AllowNewConst = (Level < AfterLegalizeDAG);
6782 // fold (fadd A, 0) -> A
6783 if (N1CFP && N1CFP->getValueAPF().isZero())
6786 // fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
6787 if (N1CFP && N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
6788 isa<ConstantFPSDNode>(N0.getOperand(1)))
6789 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0.getOperand(0),
6790 DAG.getNode(ISD::FADD, SDLoc(N), VT,
6791 N0.getOperand(1), N1));
6793 // If allowed, fold (fadd (fneg x), x) -> 0.0
6794 if (AllowNewConst && N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
6795 return DAG.getConstantFP(0.0, VT);
6797 // If allowed, fold (fadd x, (fneg x)) -> 0.0
6798 if (AllowNewConst && N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
6799 return DAG.getConstantFP(0.0, VT);
6801 // We can fold chains of FADD's of the same value into multiplications.
6802 // This transform is not safe in general because we are reducing the number
6803 // of rounding steps.
6804 if (TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && !N0CFP && !N1CFP) {
6805 if (N0.getOpcode() == ISD::FMUL) {
6806 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
6807 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
6809 // (fadd (fmul x, c), x) -> (fmul x, c+1)
6810 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
6811 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6813 DAG.getConstantFP(1.0, VT));
6814 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, NewCFP);
6817 // (fadd (fmul x, c), (fadd x, x)) -> (fmul x, c+2)
6818 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
6819 N1.getOperand(0) == N1.getOperand(1) &&
6820 N0.getOperand(0) == N1.getOperand(0)) {
6821 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6823 DAG.getConstantFP(2.0, VT));
6824 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6825 N0.getOperand(0), NewCFP);
6829 if (N1.getOpcode() == ISD::FMUL) {
6830 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
6831 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1));
6833 // (fadd x, (fmul x, c)) -> (fmul x, c+1)
6834 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
6835 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6837 DAG.getConstantFP(1.0, VT));
6838 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, NewCFP);
6841 // (fadd (fadd x, x), (fmul x, c)) -> (fmul x, c+2)
6842 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
6843 N0.getOperand(0) == N0.getOperand(1) &&
6844 N1.getOperand(0) == N0.getOperand(0)) {
6845 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6847 DAG.getConstantFP(2.0, VT));
6848 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1.getOperand(0), NewCFP);
6852 if (N0.getOpcode() == ISD::FADD && AllowNewConst) {
6853 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
6854 // (fadd (fadd x, x), x) -> (fmul x, 3.0)
6855 if (!CFP && N0.getOperand(0) == N0.getOperand(1) &&
6856 (N0.getOperand(0) == N1))
6857 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6858 N1, DAG.getConstantFP(3.0, VT));
6861 if (N1.getOpcode() == ISD::FADD && AllowNewConst) {
6862 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
6863 // (fadd x, (fadd x, x)) -> (fmul x, 3.0)
6864 if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) &&
6865 N1.getOperand(0) == N0)
6866 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6867 N0, DAG.getConstantFP(3.0, VT));
6870 // (fadd (fadd x, x), (fadd x, x)) -> (fmul x, 4.0)
6871 if (AllowNewConst &&
6872 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
6873 N0.getOperand(0) == N0.getOperand(1) &&
6874 N1.getOperand(0) == N1.getOperand(1) &&
6875 N0.getOperand(0) == N1.getOperand(0))
6876 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6877 N0.getOperand(0), DAG.getConstantFP(4.0, VT));
6879 } // enable-unsafe-fp-math
6881 // FADD -> FMA combines:
6882 if ((Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath) &&
6883 TLI.isFMAFasterThanFMulAndFAdd(VT) &&
6884 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) {
6886 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
6887 if (N0.getOpcode() == ISD::FMUL &&
6888 (N0->hasOneUse() || TLI.enableAggressiveFMAFusion(VT)))
6889 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6890 N0.getOperand(0), N0.getOperand(1), N1);
6892 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
6893 // Note: Commutes FADD operands.
6894 if (N1.getOpcode() == ISD::FMUL &&
6895 (N1->hasOneUse() || TLI.enableAggressiveFMAFusion(VT)))
6896 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6897 N1.getOperand(0), N1.getOperand(1), N0);
6899 // Remove FP_EXTEND when there is an opportunity to combine. This is
6900 // legal here since extra precision is allowed.
6902 // fold (fadd (fpext (fmul x, y)), z) -> (fma x, y, z)
6903 if (N0.getOpcode() == ISD::FP_EXTEND) {
6904 SDValue N00 = N0.getOperand(0);
6905 if (N00.getOpcode() == ISD::FMUL)
6906 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6907 N00.getOperand(0), N00.getOperand(1), N1);
6910 // fold (fadd x, (fpext (fmul y, z)), z) -> (fma y, z, x)
6911 // Note: Commutes FADD operands.
6912 if (N1.getOpcode() == ISD::FP_EXTEND) {
6913 SDValue N10 = N1.getOperand(0);
6914 if (N10.getOpcode() == ISD::FMUL)
6915 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6916 N10.getOperand(0), N10.getOperand(1), N0);
6920 // More folding opportunities when target permits.
6921 if (TLI.enableAggressiveFMAFusion(VT)) {
6923 // fold (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, z))
6924 if (N0.getOpcode() == ISD::FMA &&
6925 N0.getOperand(2).getOpcode() == ISD::FMUL)
6926 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6927 N0.getOperand(0), N0.getOperand(1),
6928 DAG.getNode(ISD::FMA, SDLoc(N), VT,
6929 N0.getOperand(2).getOperand(0),
6930 N0.getOperand(2).getOperand(1),
6933 // fold (fadd x, (fma y, z, (fmul u, v)) -> (fma y, z (fma u, v, x))
6934 if (N1->getOpcode() == ISD::FMA &&
6935 N1.getOperand(2).getOpcode() == ISD::FMUL)
6936 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6937 N1.getOperand(0), N1.getOperand(1),
6938 DAG.getNode(ISD::FMA, SDLoc(N), VT,
6939 N1.getOperand(2).getOperand(0),
6940 N1.getOperand(2).getOperand(1),
6947 SDValue DAGCombiner::visitFSUB(SDNode *N) {
6948 SDValue N0 = N->getOperand(0);
6949 SDValue N1 = N->getOperand(1);
6950 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
6951 ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
6952 EVT VT = N->getValueType(0);
6954 const TargetOptions &Options = DAG.getTarget().Options;
6957 if (VT.isVector()) {
6958 SDValue FoldedVOp = SimplifyVBinOp(N);
6959 if (FoldedVOp.getNode()) return FoldedVOp;
6962 // fold (fsub c1, c2) -> c1-c2
6964 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0, N1);
6966 // fold (fsub A, (fneg B)) -> (fadd A, B)
6967 if (isNegatibleForFree(N1, LegalOperations, TLI, &Options))
6968 return DAG.getNode(ISD::FADD, dl, VT, N0,
6969 GetNegatedExpression(N1, DAG, LegalOperations));
6971 // If 'unsafe math' is enabled, fold lots of things.
6972 if (Options.UnsafeFPMath) {
6974 if (N1CFP && N1CFP->getValueAPF().isZero())
6977 // (fsub 0, B) -> -B
6978 if (N0CFP && N0CFP->getValueAPF().isZero()) {
6979 if (isNegatibleForFree(N1, LegalOperations, TLI, &Options))
6980 return GetNegatedExpression(N1, DAG, LegalOperations);
6981 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6982 return DAG.getNode(ISD::FNEG, dl, VT, N1);
6985 // (fsub x, x) -> 0.0
6987 return DAG.getConstantFP(0.0f, VT);
6989 // (fsub x, (fadd x, y)) -> (fneg y)
6990 // (fsub x, (fadd y, x)) -> (fneg y)
6991 if (N1.getOpcode() == ISD::FADD) {
6992 SDValue N10 = N1->getOperand(0);
6993 SDValue N11 = N1->getOperand(1);
6995 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, &Options))
6996 return GetNegatedExpression(N11, DAG, LegalOperations);
6998 if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, &Options))
6999 return GetNegatedExpression(N10, DAG, LegalOperations);
7003 // FSUB -> FMA combines:
7004 if ((Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath) &&
7005 TLI.isFMAFasterThanFMulAndFAdd(VT) &&
7006 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) {
7008 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
7009 if (N0.getOpcode() == ISD::FMUL &&
7010 (N0->hasOneUse() || TLI.enableAggressiveFMAFusion(VT)))
7011 return DAG.getNode(ISD::FMA, dl, VT,
7012 N0.getOperand(0), N0.getOperand(1),
7013 DAG.getNode(ISD::FNEG, dl, VT, N1));
7015 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
7016 // Note: Commutes FSUB operands.
7017 if (N1.getOpcode() == ISD::FMUL &&
7018 (N1->hasOneUse() || TLI.enableAggressiveFMAFusion(VT)))
7019 return DAG.getNode(ISD::FMA, dl, VT,
7020 DAG.getNode(ISD::FNEG, dl, VT,
7022 N1.getOperand(1), N0);
7024 // fold (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
7025 if (N0.getOpcode() == ISD::FNEG &&
7026 N0.getOperand(0).getOpcode() == ISD::FMUL &&
7027 ((N0->hasOneUse() && N0.getOperand(0).hasOneUse()) ||
7028 TLI.enableAggressiveFMAFusion(VT))) {
7029 SDValue N00 = N0.getOperand(0).getOperand(0);
7030 SDValue N01 = N0.getOperand(0).getOperand(1);
7031 return DAG.getNode(ISD::FMA, dl, VT,
7032 DAG.getNode(ISD::FNEG, dl, VT, N00), N01,
7033 DAG.getNode(ISD::FNEG, dl, VT, N1));
7036 // Remove FP_EXTEND when there is an opportunity to combine. This is
7037 // legal here since extra precision is allowed.
7039 // fold (fsub (fpext (fmul x, y)), z) -> (fma x, y, (fneg z))
7040 if (N0.getOpcode() == ISD::FP_EXTEND) {
7041 SDValue N00 = N0.getOperand(0);
7042 if (N00.getOpcode() == ISD::FMUL)
7043 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
7046 DAG.getNode(ISD::FNEG, SDLoc(N), VT, N1));
7049 // fold (fsub x, (fpext (fmul y, z))) -> (fma (fneg y), z, x)
7050 // Note: Commutes FSUB operands.
7051 if (N1.getOpcode() == ISD::FP_EXTEND) {
7052 SDValue N10 = N1.getOperand(0);
7053 if (N10.getOpcode() == ISD::FMUL)
7054 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
7055 DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7061 // fold (fsub (fpext (fneg (fmul, x, y))), z)
7062 // -> (fma (fneg x), y, (fneg z))
7063 if (N0.getOpcode() == ISD::FP_EXTEND) {
7064 SDValue N00 = N0.getOperand(0);
7065 if (N00.getOpcode() == ISD::FNEG) {
7066 SDValue N000 = N00.getOperand(0);
7067 if (N000.getOpcode() == ISD::FMUL) {
7068 return DAG.getNode(ISD::FMA, dl, VT,
7069 DAG.getNode(ISD::FNEG, dl, VT,
7070 N000.getOperand(0)),
7072 DAG.getNode(ISD::FNEG, dl, VT, N1));
7077 // fold (fsub (fneg (fpext (fmul, x, y))), z)
7078 // -> (fma (fneg x), y, (fneg z))
7079 if (N0.getOpcode() == ISD::FNEG) {
7080 SDValue N00 = N0.getOperand(0);
7081 if (N00.getOpcode() == ISD::FP_EXTEND) {
7082 SDValue N000 = N00.getOperand(0);
7083 if (N000.getOpcode() == ISD::FMUL) {
7084 return DAG.getNode(ISD::FMA, dl, VT,
7085 DAG.getNode(ISD::FNEG, dl, VT,
7086 N000.getOperand(0)),
7088 DAG.getNode(ISD::FNEG, dl, VT, N1));
7093 // More folding opportunities when target permits.
7094 if (TLI.enableAggressiveFMAFusion(VT)) {
7096 // fold (fsub (fma x, y, (fmul u, v)), z)
7097 // -> (fma x, y (fma u, v, (fneg z)))
7098 if (N0.getOpcode() == ISD::FMA &&
7099 N0.getOperand(2).getOpcode() == ISD::FMUL)
7100 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
7101 N0.getOperand(0), N0.getOperand(1),
7102 DAG.getNode(ISD::FMA, SDLoc(N), VT,
7103 N0.getOperand(2).getOperand(0),
7104 N0.getOperand(2).getOperand(1),
7105 DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7108 // fold (fsub x, (fma y, z, (fmul u, v)))
7109 // -> (fma (fneg y), z, (fma (fneg u), v, x))
7110 if (N1.getOpcode() == ISD::FMA &&
7111 N1.getOperand(2).getOpcode() == ISD::FMUL) {
7112 SDValue N20 = N1.getOperand(2).getOperand(0);
7113 SDValue N21 = N1.getOperand(2).getOperand(1);
7114 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
7115 DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7118 DAG.getNode(ISD::FMA, SDLoc(N), VT,
7119 DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7129 SDValue DAGCombiner::visitFMUL(SDNode *N) {
7130 SDValue N0 = N->getOperand(0);
7131 SDValue N1 = N->getOperand(1);
7132 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
7133 ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
7134 EVT VT = N->getValueType(0);
7135 const TargetOptions &Options = DAG.getTarget().Options;
7138 if (VT.isVector()) {
7139 // This just handles C1 * C2 for vectors. Other vector folds are below.
7140 SDValue FoldedVOp = SimplifyVBinOp(N);
7141 if (FoldedVOp.getNode())
7143 // Canonicalize vector constant to RHS.
7144 if (N0.getOpcode() == ISD::BUILD_VECTOR &&
7145 N1.getOpcode() != ISD::BUILD_VECTOR)
7146 if (auto *BV0 = dyn_cast<BuildVectorSDNode>(N0))
7147 if (BV0->isConstant())
7148 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
7151 // fold (fmul c1, c2) -> c1*c2
7153 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, N1);
7155 // canonicalize constant to RHS
7156 if (N0CFP && !N1CFP)
7157 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, N0);
7159 // fold (fmul A, 1.0) -> A
7160 if (N1CFP && N1CFP->isExactlyValue(1.0))
7163 if (Options.UnsafeFPMath) {
7164 // fold (fmul A, 0) -> 0
7165 if (N1CFP && N1CFP->getValueAPF().isZero())
7168 // fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
7169 if (N0.getOpcode() == ISD::FMUL) {
7170 // Fold scalars or any vector constants (not just splats).
7171 // This fold is done in general by InstCombine, but extra fmul insts
7172 // may have been generated during lowering.
7173 SDValue N01 = N0.getOperand(1);
7174 auto *BV1 = dyn_cast<BuildVectorSDNode>(N1);
7175 auto *BV01 = dyn_cast<BuildVectorSDNode>(N01);
7176 if ((N1CFP && isConstOrConstSplatFP(N01)) ||
7177 (BV1 && BV01 && BV1->isConstant() && BV01->isConstant())) {
7179 SDValue MulConsts = DAG.getNode(ISD::FMUL, SL, VT, N01, N1);
7180 return DAG.getNode(ISD::FMUL, SL, VT, N0.getOperand(0), MulConsts);
7184 // fold (fmul (fadd x, x), c) -> (fmul x, (fmul 2.0, c))
7185 // Undo the fmul 2.0, x -> fadd x, x transformation, since if it occurs
7186 // during an early run of DAGCombiner can prevent folding with fmuls
7187 // inserted during lowering.
7188 if (N0.getOpcode() == ISD::FADD && N0.getOperand(0) == N0.getOperand(1)) {
7190 const SDValue Two = DAG.getConstantFP(2.0, VT);
7191 SDValue MulConsts = DAG.getNode(ISD::FMUL, SL, VT, Two, N1);
7192 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0), MulConsts);
7196 // fold (fmul X, 2.0) -> (fadd X, X)
7197 if (N1CFP && N1CFP->isExactlyValue(+2.0))
7198 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N0);
7200 // fold (fmul X, -1.0) -> (fneg X)
7201 if (N1CFP && N1CFP->isExactlyValue(-1.0))
7202 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
7203 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
7205 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
7206 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, &Options)) {
7207 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, &Options)) {
7208 // Both can be negated for free, check to see if at least one is cheaper
7210 if (LHSNeg == 2 || RHSNeg == 2)
7211 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
7212 GetNegatedExpression(N0, DAG, LegalOperations),
7213 GetNegatedExpression(N1, DAG, LegalOperations));
7220 SDValue DAGCombiner::visitFMA(SDNode *N) {
7221 SDValue N0 = N->getOperand(0);
7222 SDValue N1 = N->getOperand(1);
7223 SDValue N2 = N->getOperand(2);
7224 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7225 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7226 EVT VT = N->getValueType(0);
7228 const TargetOptions &Options = DAG.getTarget().Options;
7230 // Constant fold FMA.
7231 if (isa<ConstantFPSDNode>(N0) &&
7232 isa<ConstantFPSDNode>(N1) &&
7233 isa<ConstantFPSDNode>(N2)) {
7234 return DAG.getNode(ISD::FMA, dl, VT, N0, N1, N2);
7237 if (Options.UnsafeFPMath) {
7238 if (N0CFP && N0CFP->isZero())
7240 if (N1CFP && N1CFP->isZero())
7243 if (N0CFP && N0CFP->isExactlyValue(1.0))
7244 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N2);
7245 if (N1CFP && N1CFP->isExactlyValue(1.0))
7246 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2);
7248 // Canonicalize (fma c, x, y) -> (fma x, c, y)
7249 if (N0CFP && !N1CFP)
7250 return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2);
7252 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
7253 if (Options.UnsafeFPMath && N1CFP &&
7254 N2.getOpcode() == ISD::FMUL &&
7255 N0 == N2.getOperand(0) &&
7256 N2.getOperand(1).getOpcode() == ISD::ConstantFP) {
7257 return DAG.getNode(ISD::FMUL, dl, VT, N0,
7258 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1)));
7262 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
7263 if (Options.UnsafeFPMath &&
7264 N0.getOpcode() == ISD::FMUL && N1CFP &&
7265 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
7266 return DAG.getNode(ISD::FMA, dl, VT,
7268 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
7272 // (fma x, 1, y) -> (fadd x, y)
7273 // (fma x, -1, y) -> (fadd (fneg x), y)
7275 if (N1CFP->isExactlyValue(1.0))
7276 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
7278 if (N1CFP->isExactlyValue(-1.0) &&
7279 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
7280 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
7281 AddToWorklist(RHSNeg.getNode());
7282 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
7286 // (fma x, c, x) -> (fmul x, (c+1))
7287 if (Options.UnsafeFPMath && N1CFP && N0 == N2)
7288 return DAG.getNode(ISD::FMUL, dl, VT, N0,
7289 DAG.getNode(ISD::FADD, dl, VT,
7290 N1, DAG.getConstantFP(1.0, VT)));
7292 // (fma x, c, (fneg x)) -> (fmul x, (c-1))
7293 if (Options.UnsafeFPMath && N1CFP &&
7294 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0)
7295 return DAG.getNode(ISD::FMUL, dl, VT, N0,
7296 DAG.getNode(ISD::FADD, dl, VT,
7297 N1, DAG.getConstantFP(-1.0, VT)));
7303 SDValue DAGCombiner::visitFDIV(SDNode *N) {
7304 SDValue N0 = N->getOperand(0);
7305 SDValue N1 = N->getOperand(1);
7306 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7307 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7308 EVT VT = N->getValueType(0);
7310 const TargetOptions &Options = DAG.getTarget().Options;
7313 if (VT.isVector()) {
7314 SDValue FoldedVOp = SimplifyVBinOp(N);
7315 if (FoldedVOp.getNode()) return FoldedVOp;
7318 // fold (fdiv c1, c2) -> c1/c2
7320 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1);
7322 if (Options.UnsafeFPMath) {
7323 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
7325 // Compute the reciprocal 1.0 / c2.
7326 APFloat N1APF = N1CFP->getValueAPF();
7327 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
7328 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
7329 // Only do the transform if the reciprocal is a legal fp immediate that
7330 // isn't too nasty (eg NaN, denormal, ...).
7331 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
7332 (!LegalOperations ||
7333 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
7334 // backend)... we should handle this gracefully after Legalize.
7335 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
7336 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
7337 TLI.isFPImmLegal(Recip, VT)))
7338 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0,
7339 DAG.getConstantFP(Recip, VT));
7342 // If this FDIV is part of a reciprocal square root, it may be folded
7343 // into a target-specific square root estimate instruction.
7344 if (N1.getOpcode() == ISD::FSQRT) {
7345 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0))) {
7346 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7348 } else if (N1.getOpcode() == ISD::FP_EXTEND &&
7349 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
7350 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0).getOperand(0))) {
7351 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N1), VT, RV);
7352 AddToWorklist(RV.getNode());
7353 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7355 } else if (N1.getOpcode() == ISD::FP_ROUND &&
7356 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
7357 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0).getOperand(0))) {
7358 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1));
7359 AddToWorklist(RV.getNode());
7360 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7362 } else if (N1.getOpcode() == ISD::FMUL) {
7363 // Look through an FMUL. Even though this won't remove the FDIV directly,
7364 // it's still worthwhile to get rid of the FSQRT if possible.
7367 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) {
7368 SqrtOp = N1.getOperand(0);
7369 OtherOp = N1.getOperand(1);
7370 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) {
7371 SqrtOp = N1.getOperand(1);
7372 OtherOp = N1.getOperand(0);
7374 if (SqrtOp.getNode()) {
7375 // We found a FSQRT, so try to make this fold:
7376 // x / (y * sqrt(z)) -> x * (rsqrt(z) / y)
7377 if (SDValue RV = BuildRsqrtEstimate(SqrtOp.getOperand(0))) {
7378 RV = DAG.getNode(ISD::FDIV, SDLoc(N1), VT, RV, OtherOp);
7379 AddToWorklist(RV.getNode());
7380 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7385 // Fold into a reciprocal estimate and multiply instead of a real divide.
7386 if (SDValue RV = BuildReciprocalEstimate(N1)) {
7387 AddToWorklist(RV.getNode());
7388 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7392 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
7393 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, &Options)) {
7394 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, &Options)) {
7395 // Both can be negated for free, check to see if at least one is cheaper
7397 if (LHSNeg == 2 || RHSNeg == 2)
7398 return DAG.getNode(ISD::FDIV, SDLoc(N), VT,
7399 GetNegatedExpression(N0, DAG, LegalOperations),
7400 GetNegatedExpression(N1, DAG, LegalOperations));
7404 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
7406 // E.g., (a / D; b / D;) -> (recip = 1.0 / D; a * recip; b * recip)
7407 // Notice that this is not always beneficial. One reason is different target
7408 // may have different costs for FDIV and FMUL, so sometimes the cost of two
7409 // FDIVs may be lower than the cost of one FDIV and two FMULs. Another reason
7410 // is the critical path is increased from "one FDIV" to "one FDIV + one FMUL".
7411 if (Options.UnsafeFPMath) {
7412 // Skip if current node is a reciprocal.
7413 if (N0CFP && N0CFP->isExactlyValue(1.0))
7416 SmallVector<SDNode *, 4> Users;
7417 // Find all FDIV users of the same divisor.
7418 for (SDNode::use_iterator UI = N1.getNode()->use_begin(),
7419 UE = N1.getNode()->use_end();
7421 SDNode *User = UI.getUse().getUser();
7422 if (User->getOpcode() == ISD::FDIV && User->getOperand(1) == N1)
7423 Users.push_back(User);
7426 if (TLI.combineRepeatedFPDivisors(Users.size())) {
7427 SDValue FPOne = DAG.getConstantFP(1.0, VT); // floating point 1.0
7428 SDValue Reciprocal = DAG.getNode(ISD::FDIV, SDLoc(N), VT, FPOne, N1);
7430 // Dividend / Divisor -> Dividend * Reciprocal
7431 for (auto I = Users.begin(), E = Users.end(); I != E; ++I) {
7432 if ((*I)->getOperand(0) != FPOne) {
7433 SDValue NewNode = DAG.getNode(ISD::FMUL, SDLoc(*I), VT,
7434 (*I)->getOperand(0), Reciprocal);
7435 DAG.ReplaceAllUsesWith(*I, NewNode.getNode());
7445 SDValue DAGCombiner::visitFREM(SDNode *N) {
7446 SDValue N0 = N->getOperand(0);
7447 SDValue N1 = N->getOperand(1);
7448 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7449 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7450 EVT VT = N->getValueType(0);
7452 // fold (frem c1, c2) -> fmod(c1,c2)
7454 return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1);
7459 SDValue DAGCombiner::visitFSQRT(SDNode *N) {
7460 if (DAG.getTarget().Options.UnsafeFPMath) {
7461 // Compute this as X * (1/sqrt(X)) = X * (X ** -0.5)
7462 if (SDValue RV = BuildRsqrtEstimate(N->getOperand(0))) {
7463 EVT VT = RV.getValueType();
7464 RV = DAG.getNode(ISD::FMUL, SDLoc(N), VT, N->getOperand(0), RV);
7465 AddToWorklist(RV.getNode());
7467 // Unfortunately, RV is now NaN if the input was exactly 0.
7468 // Select out this case and force the answer to 0.
7469 SDValue Zero = DAG.getConstantFP(0.0, VT);
7471 DAG.getSetCC(SDLoc(N), TLI.getSetCCResultType(*DAG.getContext(), VT),
7472 N->getOperand(0), Zero, ISD::SETEQ);
7473 AddToWorklist(ZeroCmp.getNode());
7474 AddToWorklist(RV.getNode());
7476 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT,
7477 SDLoc(N), VT, ZeroCmp, Zero, RV);
7484 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
7485 SDValue N0 = N->getOperand(0);
7486 SDValue N1 = N->getOperand(1);
7487 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7488 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7489 EVT VT = N->getValueType(0);
7491 if (N0CFP && N1CFP) // Constant fold
7492 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1);
7495 const APFloat& V = N1CFP->getValueAPF();
7496 // copysign(x, c1) -> fabs(x) iff ispos(c1)
7497 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
7498 if (!V.isNegative()) {
7499 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
7500 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7502 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
7503 return DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7504 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0));
7508 // copysign(fabs(x), y) -> copysign(x, y)
7509 // copysign(fneg(x), y) -> copysign(x, y)
7510 // copysign(copysign(x,z), y) -> copysign(x, y)
7511 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
7512 N0.getOpcode() == ISD::FCOPYSIGN)
7513 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7514 N0.getOperand(0), N1);
7516 // copysign(x, abs(y)) -> abs(x)
7517 if (N1.getOpcode() == ISD::FABS)
7518 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7520 // copysign(x, copysign(y,z)) -> copysign(x, z)
7521 if (N1.getOpcode() == ISD::FCOPYSIGN)
7522 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7523 N0, N1.getOperand(1));
7525 // copysign(x, fp_extend(y)) -> copysign(x, y)
7526 // copysign(x, fp_round(y)) -> copysign(x, y)
7527 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
7528 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7529 N0, N1.getOperand(0));
7534 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
7535 SDValue N0 = N->getOperand(0);
7536 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
7537 EVT VT = N->getValueType(0);
7538 EVT OpVT = N0.getValueType();
7540 // fold (sint_to_fp c1) -> c1fp
7542 // ...but only if the target supports immediate floating-point values
7543 (!LegalOperations ||
7544 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
7545 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
7547 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
7548 // but UINT_TO_FP is legal on this target, try to convert.
7549 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
7550 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
7551 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
7552 if (DAG.SignBitIsZero(N0))
7553 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
7556 // The next optimizations are desirable only if SELECT_CC can be lowered.
7557 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
7558 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
7559 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
7561 (!LegalOperations ||
7562 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7564 { N0.getOperand(0), N0.getOperand(1),
7565 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT),
7567 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7570 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
7571 // (select_cc x, y, 1.0, 0.0,, cc)
7572 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
7573 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
7574 (!LegalOperations ||
7575 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7577 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
7578 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT),
7579 N0.getOperand(0).getOperand(2) };
7580 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7587 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
7588 SDValue N0 = N->getOperand(0);
7589 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
7590 EVT VT = N->getValueType(0);
7591 EVT OpVT = N0.getValueType();
7593 // fold (uint_to_fp c1) -> c1fp
7595 // ...but only if the target supports immediate floating-point values
7596 (!LegalOperations ||
7597 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
7598 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
7600 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
7601 // but SINT_TO_FP is legal on this target, try to convert.
7602 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
7603 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
7604 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
7605 if (DAG.SignBitIsZero(N0))
7606 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
7609 // The next optimizations are desirable only if SELECT_CC can be lowered.
7610 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
7611 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
7613 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
7614 (!LegalOperations ||
7615 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7617 { N0.getOperand(0), N0.getOperand(1),
7618 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT),
7620 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7627 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
7628 SDValue N0 = N->getOperand(0);
7629 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7630 EVT VT = N->getValueType(0);
7632 // fold (fp_to_sint c1fp) -> c1
7634 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0);
7639 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
7640 SDValue N0 = N->getOperand(0);
7641 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7642 EVT VT = N->getValueType(0);
7644 // fold (fp_to_uint c1fp) -> c1
7646 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0);
7651 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
7652 SDValue N0 = N->getOperand(0);
7653 SDValue N1 = N->getOperand(1);
7654 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7655 EVT VT = N->getValueType(0);
7657 // fold (fp_round c1fp) -> c1fp
7659 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1);
7661 // fold (fp_round (fp_extend x)) -> x
7662 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
7663 return N0.getOperand(0);
7665 // fold (fp_round (fp_round x)) -> (fp_round x)
7666 if (N0.getOpcode() == ISD::FP_ROUND) {
7667 // This is a value preserving truncation if both round's are.
7668 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
7669 N0.getNode()->getConstantOperandVal(1) == 1;
7670 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0.getOperand(0),
7671 DAG.getIntPtrConstant(IsTrunc));
7674 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
7675 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
7676 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,
7677 N0.getOperand(0), N1);
7678 AddToWorklist(Tmp.getNode());
7679 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7680 Tmp, N0.getOperand(1));
7686 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
7687 SDValue N0 = N->getOperand(0);
7688 EVT VT = N->getValueType(0);
7689 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
7690 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7692 // fold (fp_round_inreg c1fp) -> c1fp
7693 if (N0CFP && isTypeLegal(EVT)) {
7694 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
7695 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Round);
7701 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
7702 SDValue N0 = N->getOperand(0);
7703 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7704 EVT VT = N->getValueType(0);
7706 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
7707 if (N->hasOneUse() &&
7708 N->use_begin()->getOpcode() == ISD::FP_ROUND)
7711 // fold (fp_extend c1fp) -> c1fp
7713 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);
7715 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
7717 if (N0.getOpcode() == ISD::FP_ROUND
7718 && N0.getNode()->getConstantOperandVal(1) == 1) {
7719 SDValue In = N0.getOperand(0);
7720 if (In.getValueType() == VT) return In;
7721 if (VT.bitsLT(In.getValueType()))
7722 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT,
7723 In, N0.getOperand(1));
7724 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, In);
7727 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
7728 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7729 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType())) {
7730 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7731 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
7733 LN0->getBasePtr(), N0.getValueType(),
7734 LN0->getMemOperand());
7735 CombineTo(N, ExtLoad);
7736 CombineTo(N0.getNode(),
7737 DAG.getNode(ISD::FP_ROUND, SDLoc(N0),
7738 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
7739 ExtLoad.getValue(1));
7740 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7746 SDValue DAGCombiner::visitFCEIL(SDNode *N) {
7747 SDValue N0 = N->getOperand(0);
7748 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7749 EVT VT = N->getValueType(0);
7751 // fold (fceil c1) -> fceil(c1)
7753 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0);
7758 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
7759 SDValue N0 = N->getOperand(0);
7760 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7761 EVT VT = N->getValueType(0);
7763 // fold (ftrunc c1) -> ftrunc(c1)
7765 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0);
7770 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
7771 SDValue N0 = N->getOperand(0);
7772 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7773 EVT VT = N->getValueType(0);
7775 // fold (ffloor c1) -> ffloor(c1)
7777 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0);
7782 // FIXME: FNEG and FABS have a lot in common; refactor.
7783 SDValue DAGCombiner::visitFNEG(SDNode *N) {
7784 SDValue N0 = N->getOperand(0);
7785 EVT VT = N->getValueType(0);
7787 if (VT.isVector()) {
7788 SDValue FoldedVOp = SimplifyVUnaryOp(N);
7789 if (FoldedVOp.getNode()) return FoldedVOp;
7792 // Constant fold FNEG.
7793 if (isa<ConstantFPSDNode>(N0))
7794 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N->getOperand(0));
7796 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
7797 &DAG.getTarget().Options))
7798 return GetNegatedExpression(N0, DAG, LegalOperations);
7800 // Transform fneg(bitconvert(x)) -> bitconvert(x ^ sign) to avoid loading
7801 // constant pool values.
7802 if (!TLI.isFNegFree(VT) &&
7803 N0.getOpcode() == ISD::BITCAST &&
7804 N0.getNode()->hasOneUse()) {
7805 SDValue Int = N0.getOperand(0);
7806 EVT IntVT = Int.getValueType();
7807 if (IntVT.isInteger() && !IntVT.isVector()) {
7809 if (N0.getValueType().isVector()) {
7810 // For a vector, get a mask such as 0x80... per scalar element
7812 SignMask = APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
7813 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
7815 // For a scalar, just generate 0x80...
7816 SignMask = APInt::getSignBit(IntVT.getSizeInBits());
7818 Int = DAG.getNode(ISD::XOR, SDLoc(N0), IntVT, Int,
7819 DAG.getConstant(SignMask, IntVT));
7820 AddToWorklist(Int.getNode());
7821 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Int);
7825 // (fneg (fmul c, x)) -> (fmul -c, x)
7826 if (N0.getOpcode() == ISD::FMUL) {
7827 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
7829 APFloat CVal = CFP1->getValueAPF();
7831 if (Level >= AfterLegalizeDAG &&
7832 (TLI.isFPImmLegal(CVal, N->getValueType(0)) ||
7833 TLI.isOperationLegal(ISD::ConstantFP, N->getValueType(0))))
7835 ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
7836 DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0.getOperand(1)));
7843 SDValue DAGCombiner::visitFMINNUM(SDNode *N) {
7844 SDValue N0 = N->getOperand(0);
7845 SDValue N1 = N->getOperand(1);
7846 const ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7847 const ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7849 if (N0CFP && N1CFP) {
7850 const APFloat &C0 = N0CFP->getValueAPF();
7851 const APFloat &C1 = N1CFP->getValueAPF();
7852 return DAG.getConstantFP(minnum(C0, C1), N->getValueType(0));
7856 EVT VT = N->getValueType(0);
7857 // Canonicalize to constant on RHS.
7858 return DAG.getNode(ISD::FMINNUM, SDLoc(N), VT, N1, N0);
7864 SDValue DAGCombiner::visitFMAXNUM(SDNode *N) {
7865 SDValue N0 = N->getOperand(0);
7866 SDValue N1 = N->getOperand(1);
7867 const ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7868 const ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7870 if (N0CFP && N1CFP) {
7871 const APFloat &C0 = N0CFP->getValueAPF();
7872 const APFloat &C1 = N1CFP->getValueAPF();
7873 return DAG.getConstantFP(maxnum(C0, C1), N->getValueType(0));
7877 EVT VT = N->getValueType(0);
7878 // Canonicalize to constant on RHS.
7879 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), VT, N1, N0);
7885 SDValue DAGCombiner::visitFABS(SDNode *N) {
7886 SDValue N0 = N->getOperand(0);
7887 EVT VT = N->getValueType(0);
7889 if (VT.isVector()) {
7890 SDValue FoldedVOp = SimplifyVUnaryOp(N);
7891 if (FoldedVOp.getNode()) return FoldedVOp;
7894 // fold (fabs c1) -> fabs(c1)
7895 if (isa<ConstantFPSDNode>(N0))
7896 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7898 // fold (fabs (fabs x)) -> (fabs x)
7899 if (N0.getOpcode() == ISD::FABS)
7900 return N->getOperand(0);
7902 // fold (fabs (fneg x)) -> (fabs x)
7903 // fold (fabs (fcopysign x, y)) -> (fabs x)
7904 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
7905 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0));
7907 // Transform fabs(bitconvert(x)) -> bitconvert(x & ~sign) to avoid loading
7908 // constant pool values.
7909 if (!TLI.isFAbsFree(VT) &&
7910 N0.getOpcode() == ISD::BITCAST &&
7911 N0.getNode()->hasOneUse()) {
7912 SDValue Int = N0.getOperand(0);
7913 EVT IntVT = Int.getValueType();
7914 if (IntVT.isInteger() && !IntVT.isVector()) {
7916 if (N0.getValueType().isVector()) {
7917 // For a vector, get a mask such as 0x7f... per scalar element
7919 SignMask = ~APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
7920 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
7922 // For a scalar, just generate 0x7f...
7923 SignMask = ~APInt::getSignBit(IntVT.getSizeInBits());
7925 Int = DAG.getNode(ISD::AND, SDLoc(N0), IntVT, Int,
7926 DAG.getConstant(SignMask, IntVT));
7927 AddToWorklist(Int.getNode());
7928 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Int);
7935 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
7936 SDValue Chain = N->getOperand(0);
7937 SDValue N1 = N->getOperand(1);
7938 SDValue N2 = N->getOperand(2);
7940 // If N is a constant we could fold this into a fallthrough or unconditional
7941 // branch. However that doesn't happen very often in normal code, because
7942 // Instcombine/SimplifyCFG should have handled the available opportunities.
7943 // If we did this folding here, it would be necessary to update the
7944 // MachineBasicBlock CFG, which is awkward.
7946 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
7948 if (N1.getOpcode() == ISD::SETCC &&
7949 TLI.isOperationLegalOrCustom(ISD::BR_CC,
7950 N1.getOperand(0).getValueType())) {
7951 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
7952 Chain, N1.getOperand(2),
7953 N1.getOperand(0), N1.getOperand(1), N2);
7956 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
7957 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
7958 (N1.getOperand(0).hasOneUse() &&
7959 N1.getOperand(0).getOpcode() == ISD::SRL))) {
7960 SDNode *Trunc = nullptr;
7961 if (N1.getOpcode() == ISD::TRUNCATE) {
7962 // Look pass the truncate.
7963 Trunc = N1.getNode();
7964 N1 = N1.getOperand(0);
7967 // Match this pattern so that we can generate simpler code:
7970 // %b = and i32 %a, 2
7971 // %c = srl i32 %b, 1
7972 // brcond i32 %c ...
7977 // %b = and i32 %a, 2
7978 // %c = setcc eq %b, 0
7981 // This applies only when the AND constant value has one bit set and the
7982 // SRL constant is equal to the log2 of the AND constant. The back-end is
7983 // smart enough to convert the result into a TEST/JMP sequence.
7984 SDValue Op0 = N1.getOperand(0);
7985 SDValue Op1 = N1.getOperand(1);
7987 if (Op0.getOpcode() == ISD::AND &&
7988 Op1.getOpcode() == ISD::Constant) {
7989 SDValue AndOp1 = Op0.getOperand(1);
7991 if (AndOp1.getOpcode() == ISD::Constant) {
7992 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
7994 if (AndConst.isPowerOf2() &&
7995 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
7997 DAG.getSetCC(SDLoc(N),
7998 getSetCCResultType(Op0.getValueType()),
7999 Op0, DAG.getConstant(0, Op0.getValueType()),
8002 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, SDLoc(N),
8003 MVT::Other, Chain, SetCC, N2);
8004 // Don't add the new BRCond into the worklist or else SimplifySelectCC
8005 // will convert it back to (X & C1) >> C2.
8006 CombineTo(N, NewBRCond, false);
8007 // Truncate is dead.
8009 deleteAndRecombine(Trunc);
8010 // Replace the uses of SRL with SETCC
8011 WorklistRemover DeadNodes(*this);
8012 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
8013 deleteAndRecombine(N1.getNode());
8014 return SDValue(N, 0); // Return N so it doesn't get rechecked!
8020 // Restore N1 if the above transformation doesn't match.
8021 N1 = N->getOperand(1);
8024 // Transform br(xor(x, y)) -> br(x != y)
8025 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
8026 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
8027 SDNode *TheXor = N1.getNode();
8028 SDValue Op0 = TheXor->getOperand(0);
8029 SDValue Op1 = TheXor->getOperand(1);
8030 if (Op0.getOpcode() == Op1.getOpcode()) {
8031 // Avoid missing important xor optimizations.
8032 SDValue Tmp = visitXOR(TheXor);
8033 if (Tmp.getNode()) {
8034 if (Tmp.getNode() != TheXor) {
8035 DEBUG(dbgs() << "\nReplacing.8 ";
8037 dbgs() << "\nWith: ";
8038 Tmp.getNode()->dump(&DAG);
8040 WorklistRemover DeadNodes(*this);
8041 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
8042 deleteAndRecombine(TheXor);
8043 return DAG.getNode(ISD::BRCOND, SDLoc(N),
8044 MVT::Other, Chain, Tmp, N2);
8047 // visitXOR has changed XOR's operands or replaced the XOR completely,
8049 return SDValue(N, 0);
8053 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
8055 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
8056 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
8057 Op0.getOpcode() == ISD::XOR) {
8058 TheXor = Op0.getNode();
8062 EVT SetCCVT = N1.getValueType();
8064 SetCCVT = getSetCCResultType(SetCCVT);
8065 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor),
8068 Equal ? ISD::SETEQ : ISD::SETNE);
8069 // Replace the uses of XOR with SETCC
8070 WorklistRemover DeadNodes(*this);
8071 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
8072 deleteAndRecombine(N1.getNode());
8073 return DAG.getNode(ISD::BRCOND, SDLoc(N),
8074 MVT::Other, Chain, SetCC, N2);
8081 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
8083 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
8084 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
8085 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
8087 // If N is a constant we could fold this into a fallthrough or unconditional
8088 // branch. However that doesn't happen very often in normal code, because
8089 // Instcombine/SimplifyCFG should have handled the available opportunities.
8090 // If we did this folding here, it would be necessary to update the
8091 // MachineBasicBlock CFG, which is awkward.
8093 // Use SimplifySetCC to simplify SETCC's.
8094 SDValue Simp = SimplifySetCC(getSetCCResultType(CondLHS.getValueType()),
8095 CondLHS, CondRHS, CC->get(), SDLoc(N),
8097 if (Simp.getNode()) AddToWorklist(Simp.getNode());
8099 // fold to a simpler setcc
8100 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
8101 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
8102 N->getOperand(0), Simp.getOperand(2),
8103 Simp.getOperand(0), Simp.getOperand(1),
8109 /// Return true if 'Use' is a load or a store that uses N as its base pointer
8110 /// and that N may be folded in the load / store addressing mode.
8111 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
8113 const TargetLowering &TLI) {
8115 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
8116 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
8118 VT = Use->getValueType(0);
8119 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
8120 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
8122 VT = ST->getValue().getValueType();
8126 TargetLowering::AddrMode AM;
8127 if (N->getOpcode() == ISD::ADD) {
8128 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
8131 AM.BaseOffs = Offset->getSExtValue();
8135 } else if (N->getOpcode() == ISD::SUB) {
8136 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
8139 AM.BaseOffs = -Offset->getSExtValue();
8146 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
8149 /// Try turning a load/store into a pre-indexed load/store when the base
8150 /// pointer is an add or subtract and it has other uses besides the load/store.
8151 /// After the transformation, the new indexed load/store has effectively folded
8152 /// the add/subtract in and all of its other uses are redirected to the
8154 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
8155 if (Level < AfterLegalizeDAG)
8161 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8162 if (LD->isIndexed())
8164 VT = LD->getMemoryVT();
8165 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
8166 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
8168 Ptr = LD->getBasePtr();
8169 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8170 if (ST->isIndexed())
8172 VT = ST->getMemoryVT();
8173 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
8174 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
8176 Ptr = ST->getBasePtr();
8182 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
8183 // out. There is no reason to make this a preinc/predec.
8184 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
8185 Ptr.getNode()->hasOneUse())
8188 // Ask the target to do addressing mode selection.
8191 ISD::MemIndexedMode AM = ISD::UNINDEXED;
8192 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
8195 // Backends without true r+i pre-indexed forms may need to pass a
8196 // constant base with a variable offset so that constant coercion
8197 // will work with the patterns in canonical form.
8198 bool Swapped = false;
8199 if (isa<ConstantSDNode>(BasePtr)) {
8200 std::swap(BasePtr, Offset);
8204 // Don't create a indexed load / store with zero offset.
8205 if (isa<ConstantSDNode>(Offset) &&
8206 cast<ConstantSDNode>(Offset)->isNullValue())
8209 // Try turning it into a pre-indexed load / store except when:
8210 // 1) The new base ptr is a frame index.
8211 // 2) If N is a store and the new base ptr is either the same as or is a
8212 // predecessor of the value being stored.
8213 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
8214 // that would create a cycle.
8215 // 4) All uses are load / store ops that use it as old base ptr.
8217 // Check #1. Preinc'ing a frame index would require copying the stack pointer
8218 // (plus the implicit offset) to a register to preinc anyway.
8219 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
8224 SDValue Val = cast<StoreSDNode>(N)->getValue();
8225 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
8229 // If the offset is a constant, there may be other adds of constants that
8230 // can be folded with this one. We should do this to avoid having to keep
8231 // a copy of the original base pointer.
8232 SmallVector<SDNode *, 16> OtherUses;
8233 if (isa<ConstantSDNode>(Offset))
8234 for (SDNode *Use : BasePtr.getNode()->uses()) {
8235 if (Use == Ptr.getNode())
8238 if (Use->isPredecessorOf(N))
8241 if (Use->getOpcode() != ISD::ADD && Use->getOpcode() != ISD::SUB) {
8246 SDValue Op0 = Use->getOperand(0), Op1 = Use->getOperand(1);
8247 if (Op1.getNode() == BasePtr.getNode())
8248 std::swap(Op0, Op1);
8249 assert(Op0.getNode() == BasePtr.getNode() &&
8250 "Use of ADD/SUB but not an operand");
8252 if (!isa<ConstantSDNode>(Op1)) {
8257 // FIXME: In some cases, we can be smarter about this.
8258 if (Op1.getValueType() != Offset.getValueType()) {
8263 OtherUses.push_back(Use);
8267 std::swap(BasePtr, Offset);
8269 // Now check for #3 and #4.
8270 bool RealUse = false;
8272 // Caches for hasPredecessorHelper
8273 SmallPtrSet<const SDNode *, 32> Visited;
8274 SmallVector<const SDNode *, 16> Worklist;
8276 for (SDNode *Use : Ptr.getNode()->uses()) {
8279 if (N->hasPredecessorHelper(Use, Visited, Worklist))
8282 // If Ptr may be folded in addressing mode of other use, then it's
8283 // not profitable to do this transformation.
8284 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
8293 Result = DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
8294 BasePtr, Offset, AM);
8296 Result = DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
8297 BasePtr, Offset, AM);
8300 DEBUG(dbgs() << "\nReplacing.4 ";
8302 dbgs() << "\nWith: ";
8303 Result.getNode()->dump(&DAG);
8305 WorklistRemover DeadNodes(*this);
8307 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
8308 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
8310 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
8313 // Finally, since the node is now dead, remove it from the graph.
8314 deleteAndRecombine(N);
8317 std::swap(BasePtr, Offset);
8319 // Replace other uses of BasePtr that can be updated to use Ptr
8320 for (unsigned i = 0, e = OtherUses.size(); i != e; ++i) {
8321 unsigned OffsetIdx = 1;
8322 if (OtherUses[i]->getOperand(OffsetIdx).getNode() == BasePtr.getNode())
8324 assert(OtherUses[i]->getOperand(!OffsetIdx).getNode() ==
8325 BasePtr.getNode() && "Expected BasePtr operand");
8327 // We need to replace ptr0 in the following expression:
8328 // x0 * offset0 + y0 * ptr0 = t0
8330 // x1 * offset1 + y1 * ptr0 = t1 (the indexed load/store)
8332 // where x0, x1, y0 and y1 in {-1, 1} are given by the types of the
8333 // indexed load/store and the expresion that needs to be re-written.
8335 // Therefore, we have:
8336 // t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1
8338 ConstantSDNode *CN =
8339 cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx));
8341 APInt Offset0 = CN->getAPIntValue();
8342 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue();
8344 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
8345 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
8346 X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1;
8347 Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1;
8349 unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD;
8351 APInt CNV = Offset0;
8352 if (X0 < 0) CNV = -CNV;
8353 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1;
8354 else CNV = CNV - Offset1;
8356 // We can now generate the new expression.
8357 SDValue NewOp1 = DAG.getConstant(CNV, CN->getValueType(0));
8358 SDValue NewOp2 = Result.getValue(isLoad ? 1 : 0);
8360 SDValue NewUse = DAG.getNode(Opcode,
8361 SDLoc(OtherUses[i]),
8362 OtherUses[i]->getValueType(0), NewOp1, NewOp2);
8363 DAG.ReplaceAllUsesOfValueWith(SDValue(OtherUses[i], 0), NewUse);
8364 deleteAndRecombine(OtherUses[i]);
8367 // Replace the uses of Ptr with uses of the updated base value.
8368 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
8369 deleteAndRecombine(Ptr.getNode());
8374 /// Try to combine a load/store with a add/sub of the base pointer node into a
8375 /// post-indexed load/store. The transformation folded the add/subtract into the
8376 /// new indexed load/store effectively and all of its uses are redirected to the
8378 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
8379 if (Level < AfterLegalizeDAG)
8385 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8386 if (LD->isIndexed())
8388 VT = LD->getMemoryVT();
8389 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
8390 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
8392 Ptr = LD->getBasePtr();
8393 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8394 if (ST->isIndexed())
8396 VT = ST->getMemoryVT();
8397 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
8398 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
8400 Ptr = ST->getBasePtr();
8406 if (Ptr.getNode()->hasOneUse())
8409 for (SDNode *Op : Ptr.getNode()->uses()) {
8411 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
8416 ISD::MemIndexedMode AM = ISD::UNINDEXED;
8417 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
8418 // Don't create a indexed load / store with zero offset.
8419 if (isa<ConstantSDNode>(Offset) &&
8420 cast<ConstantSDNode>(Offset)->isNullValue())
8423 // Try turning it into a post-indexed load / store except when
8424 // 1) All uses are load / store ops that use it as base ptr (and
8425 // it may be folded as addressing mmode).
8426 // 2) Op must be independent of N, i.e. Op is neither a predecessor
8427 // nor a successor of N. Otherwise, if Op is folded that would
8430 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
8434 bool TryNext = false;
8435 for (SDNode *Use : BasePtr.getNode()->uses()) {
8436 if (Use == Ptr.getNode())
8439 // If all the uses are load / store addresses, then don't do the
8441 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
8442 bool RealUse = false;
8443 for (SDNode *UseUse : Use->uses()) {
8444 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
8459 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
8460 SDValue Result = isLoad
8461 ? DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
8462 BasePtr, Offset, AM)
8463 : DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
8464 BasePtr, Offset, AM);
8467 DEBUG(dbgs() << "\nReplacing.5 ";
8469 dbgs() << "\nWith: ";
8470 Result.getNode()->dump(&DAG);
8472 WorklistRemover DeadNodes(*this);
8474 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
8475 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
8477 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
8480 // Finally, since the node is now dead, remove it from the graph.
8481 deleteAndRecombine(N);
8483 // Replace the uses of Use with uses of the updated base value.
8484 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
8485 Result.getValue(isLoad ? 1 : 0));
8486 deleteAndRecombine(Op);
8495 /// \brief Return the base-pointer arithmetic from an indexed \p LD.
8496 SDValue DAGCombiner::SplitIndexingFromLoad(LoadSDNode *LD) {
8497 ISD::MemIndexedMode AM = LD->getAddressingMode();
8498 assert(AM != ISD::UNINDEXED);
8499 SDValue BP = LD->getOperand(1);
8500 SDValue Inc = LD->getOperand(2);
8502 // Some backends use TargetConstants for load offsets, but don't expect
8503 // TargetConstants in general ADD nodes. We can convert these constants into
8504 // regular Constants (if the constant is not opaque).
8505 assert((Inc.getOpcode() != ISD::TargetConstant ||
8506 !cast<ConstantSDNode>(Inc)->isOpaque()) &&
8507 "Cannot split out indexing using opaque target constants");
8508 if (Inc.getOpcode() == ISD::TargetConstant) {
8509 ConstantSDNode *ConstInc = cast<ConstantSDNode>(Inc);
8510 Inc = DAG.getConstant(*ConstInc->getConstantIntValue(),
8511 ConstInc->getValueType(0));
8515 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB);
8516 return DAG.getNode(Opc, SDLoc(LD), BP.getSimpleValueType(), BP, Inc);
8519 SDValue DAGCombiner::visitLOAD(SDNode *N) {
8520 LoadSDNode *LD = cast<LoadSDNode>(N);
8521 SDValue Chain = LD->getChain();
8522 SDValue Ptr = LD->getBasePtr();
8524 // If load is not volatile and there are no uses of the loaded value (and
8525 // the updated indexed value in case of indexed loads), change uses of the
8526 // chain value into uses of the chain input (i.e. delete the dead load).
8527 if (!LD->isVolatile()) {
8528 if (N->getValueType(1) == MVT::Other) {
8530 if (!N->hasAnyUseOfValue(0)) {
8531 // It's not safe to use the two value CombineTo variant here. e.g.
8532 // v1, chain2 = load chain1, loc
8533 // v2, chain3 = load chain2, loc
8535 // Now we replace use of chain2 with chain1. This makes the second load
8536 // isomorphic to the one we are deleting, and thus makes this load live.
8537 DEBUG(dbgs() << "\nReplacing.6 ";
8539 dbgs() << "\nWith chain: ";
8540 Chain.getNode()->dump(&DAG);
8542 WorklistRemover DeadNodes(*this);
8543 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
8546 deleteAndRecombine(N);
8548 return SDValue(N, 0); // Return N so it doesn't get rechecked!
8552 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
8554 // If this load has an opaque TargetConstant offset, then we cannot split
8555 // the indexing into an add/sub directly (that TargetConstant may not be
8556 // valid for a different type of node, and we cannot convert an opaque
8557 // target constant into a regular constant).
8558 bool HasOTCInc = LD->getOperand(2).getOpcode() == ISD::TargetConstant &&
8559 cast<ConstantSDNode>(LD->getOperand(2))->isOpaque();
8561 if (!N->hasAnyUseOfValue(0) &&
8562 ((MaySplitLoadIndex && !HasOTCInc) || !N->hasAnyUseOfValue(1))) {
8563 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
8565 if (N->hasAnyUseOfValue(1) && MaySplitLoadIndex && !HasOTCInc) {
8566 Index = SplitIndexingFromLoad(LD);
8567 // Try to fold the base pointer arithmetic into subsequent loads and
8569 AddUsersToWorklist(N);
8571 Index = DAG.getUNDEF(N->getValueType(1));
8572 DEBUG(dbgs() << "\nReplacing.7 ";
8574 dbgs() << "\nWith: ";
8575 Undef.getNode()->dump(&DAG);
8576 dbgs() << " and 2 other values\n");
8577 WorklistRemover DeadNodes(*this);
8578 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
8579 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Index);
8580 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
8581 deleteAndRecombine(N);
8582 return SDValue(N, 0); // Return N so it doesn't get rechecked!
8587 // If this load is directly stored, replace the load value with the stored
8589 // TODO: Handle store large -> read small portion.
8590 // TODO: Handle TRUNCSTORE/LOADEXT
8591 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
8592 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
8593 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
8594 if (PrevST->getBasePtr() == Ptr &&
8595 PrevST->getValue().getValueType() == N->getValueType(0))
8596 return CombineTo(N, Chain.getOperand(1), Chain);
8600 // Try to infer better alignment information than the load already has.
8601 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
8602 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
8603 if (Align > LD->getMemOperand()->getBaseAlignment()) {
8605 DAG.getExtLoad(LD->getExtensionType(), SDLoc(N),
8606 LD->getValueType(0),
8607 Chain, Ptr, LD->getPointerInfo(),
8609 LD->isVolatile(), LD->isNonTemporal(),
8610 LD->isInvariant(), Align, LD->getAAInfo());
8611 return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
8616 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
8617 : DAG.getSubtarget().useAA();
8619 if (CombinerAAOnlyFunc.getNumOccurrences() &&
8620 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
8623 if (UseAA && LD->isUnindexed()) {
8624 // Walk up chain skipping non-aliasing memory nodes.
8625 SDValue BetterChain = FindBetterChain(N, Chain);
8627 // If there is a better chain.
8628 if (Chain != BetterChain) {
8631 // Replace the chain to void dependency.
8632 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
8633 ReplLoad = DAG.getLoad(N->getValueType(0), SDLoc(LD),
8634 BetterChain, Ptr, LD->getMemOperand());
8636 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD),
8637 LD->getValueType(0),
8638 BetterChain, Ptr, LD->getMemoryVT(),
8639 LD->getMemOperand());
8642 // Create token factor to keep old chain connected.
8643 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
8644 MVT::Other, Chain, ReplLoad.getValue(1));
8646 // Make sure the new and old chains are cleaned up.
8647 AddToWorklist(Token.getNode());
8649 // Replace uses with load result and token factor. Don't add users
8651 return CombineTo(N, ReplLoad.getValue(0), Token, false);
8655 // Try transforming N to an indexed load.
8656 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
8657 return SDValue(N, 0);
8659 // Try to slice up N to more direct loads if the slices are mapped to
8660 // different register banks or pairing can take place.
8662 return SDValue(N, 0);
8668 /// \brief Helper structure used to slice a load in smaller loads.
8669 /// Basically a slice is obtained from the following sequence:
8670 /// Origin = load Ty1, Base
8671 /// Shift = srl Ty1 Origin, CstTy Amount
8672 /// Inst = trunc Shift to Ty2
8674 /// Then, it will be rewriten into:
8675 /// Slice = load SliceTy, Base + SliceOffset
8676 /// [Inst = zext Slice to Ty2], only if SliceTy <> Ty2
8678 /// SliceTy is deduced from the number of bits that are actually used to
8680 struct LoadedSlice {
8681 /// \brief Helper structure used to compute the cost of a slice.
8683 /// Are we optimizing for code size.
8688 unsigned CrossRegisterBanksCopies;
8692 Cost(bool ForCodeSize = false)
8693 : ForCodeSize(ForCodeSize), Loads(0), Truncates(0),
8694 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {}
8696 /// \brief Get the cost of one isolated slice.
8697 Cost(const LoadedSlice &LS, bool ForCodeSize = false)
8698 : ForCodeSize(ForCodeSize), Loads(1), Truncates(0),
8699 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {
8700 EVT TruncType = LS.Inst->getValueType(0);
8701 EVT LoadedType = LS.getLoadedType();
8702 if (TruncType != LoadedType &&
8703 !LS.DAG->getTargetLoweringInfo().isZExtFree(LoadedType, TruncType))
8707 /// \brief Account for slicing gain in the current cost.
8708 /// Slicing provide a few gains like removing a shift or a
8709 /// truncate. This method allows to grow the cost of the original
8710 /// load with the gain from this slice.
8711 void addSliceGain(const LoadedSlice &LS) {
8712 // Each slice saves a truncate.
8713 const TargetLowering &TLI = LS.DAG->getTargetLoweringInfo();
8714 if (!TLI.isTruncateFree(LS.Inst->getValueType(0),
8715 LS.Inst->getOperand(0).getValueType()))
8717 // If there is a shift amount, this slice gets rid of it.
8720 // If this slice can merge a cross register bank copy, account for it.
8721 if (LS.canMergeExpensiveCrossRegisterBankCopy())
8722 ++CrossRegisterBanksCopies;
8725 Cost &operator+=(const Cost &RHS) {
8727 Truncates += RHS.Truncates;
8728 CrossRegisterBanksCopies += RHS.CrossRegisterBanksCopies;
8734 bool operator==(const Cost &RHS) const {
8735 return Loads == RHS.Loads && Truncates == RHS.Truncates &&
8736 CrossRegisterBanksCopies == RHS.CrossRegisterBanksCopies &&
8737 ZExts == RHS.ZExts && Shift == RHS.Shift;
8740 bool operator!=(const Cost &RHS) const { return !(*this == RHS); }
8742 bool operator<(const Cost &RHS) const {
8743 // Assume cross register banks copies are as expensive as loads.
8744 // FIXME: Do we want some more target hooks?
8745 unsigned ExpensiveOpsLHS = Loads + CrossRegisterBanksCopies;
8746 unsigned ExpensiveOpsRHS = RHS.Loads + RHS.CrossRegisterBanksCopies;
8747 // Unless we are optimizing for code size, consider the
8748 // expensive operation first.
8749 if (!ForCodeSize && ExpensiveOpsLHS != ExpensiveOpsRHS)
8750 return ExpensiveOpsLHS < ExpensiveOpsRHS;
8751 return (Truncates + ZExts + Shift + ExpensiveOpsLHS) <
8752 (RHS.Truncates + RHS.ZExts + RHS.Shift + ExpensiveOpsRHS);
8755 bool operator>(const Cost &RHS) const { return RHS < *this; }
8757 bool operator<=(const Cost &RHS) const { return !(RHS < *this); }
8759 bool operator>=(const Cost &RHS) const { return !(*this < RHS); }
8761 // The last instruction that represent the slice. This should be a
8762 // truncate instruction.
8764 // The original load instruction.
8766 // The right shift amount in bits from the original load.
8768 // The DAG from which Origin came from.
8769 // This is used to get some contextual information about legal types, etc.
8772 LoadedSlice(SDNode *Inst = nullptr, LoadSDNode *Origin = nullptr,
8773 unsigned Shift = 0, SelectionDAG *DAG = nullptr)
8774 : Inst(Inst), Origin(Origin), Shift(Shift), DAG(DAG) {}
8776 LoadedSlice(const LoadedSlice &LS)
8777 : Inst(LS.Inst), Origin(LS.Origin), Shift(LS.Shift), DAG(LS.DAG) {}
8779 /// \brief Get the bits used in a chunk of bits \p BitWidth large.
8780 /// \return Result is \p BitWidth and has used bits set to 1 and
8781 /// not used bits set to 0.
8782 APInt getUsedBits() const {
8783 // Reproduce the trunc(lshr) sequence:
8784 // - Start from the truncated value.
8785 // - Zero extend to the desired bit width.
8787 assert(Origin && "No original load to compare against.");
8788 unsigned BitWidth = Origin->getValueSizeInBits(0);
8789 assert(Inst && "This slice is not bound to an instruction");
8790 assert(Inst->getValueSizeInBits(0) <= BitWidth &&
8791 "Extracted slice is bigger than the whole type!");
8792 APInt UsedBits(Inst->getValueSizeInBits(0), 0);
8793 UsedBits.setAllBits();
8794 UsedBits = UsedBits.zext(BitWidth);
8799 /// \brief Get the size of the slice to be loaded in bytes.
8800 unsigned getLoadedSize() const {
8801 unsigned SliceSize = getUsedBits().countPopulation();
8802 assert(!(SliceSize & 0x7) && "Size is not a multiple of a byte.");
8803 return SliceSize / 8;
8806 /// \brief Get the type that will be loaded for this slice.
8807 /// Note: This may not be the final type for the slice.
8808 EVT getLoadedType() const {
8809 assert(DAG && "Missing context");
8810 LLVMContext &Ctxt = *DAG->getContext();
8811 return EVT::getIntegerVT(Ctxt, getLoadedSize() * 8);
8814 /// \brief Get the alignment of the load used for this slice.
8815 unsigned getAlignment() const {
8816 unsigned Alignment = Origin->getAlignment();
8817 unsigned Offset = getOffsetFromBase();
8819 Alignment = MinAlign(Alignment, Alignment + Offset);
8823 /// \brief Check if this slice can be rewritten with legal operations.
8824 bool isLegal() const {
8825 // An invalid slice is not legal.
8826 if (!Origin || !Inst || !DAG)
8829 // Offsets are for indexed load only, we do not handle that.
8830 if (Origin->getOffset().getOpcode() != ISD::UNDEF)
8833 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
8835 // Check that the type is legal.
8836 EVT SliceType = getLoadedType();
8837 if (!TLI.isTypeLegal(SliceType))
8840 // Check that the load is legal for this type.
8841 if (!TLI.isOperationLegal(ISD::LOAD, SliceType))
8844 // Check that the offset can be computed.
8845 // 1. Check its type.
8846 EVT PtrType = Origin->getBasePtr().getValueType();
8847 if (PtrType == MVT::Untyped || PtrType.isExtended())
8850 // 2. Check that it fits in the immediate.
8851 if (!TLI.isLegalAddImmediate(getOffsetFromBase()))
8854 // 3. Check that the computation is legal.
8855 if (!TLI.isOperationLegal(ISD::ADD, PtrType))
8858 // Check that the zext is legal if it needs one.
8859 EVT TruncateType = Inst->getValueType(0);
8860 if (TruncateType != SliceType &&
8861 !TLI.isOperationLegal(ISD::ZERO_EXTEND, TruncateType))
8867 /// \brief Get the offset in bytes of this slice in the original chunk of
8869 /// \pre DAG != nullptr.
8870 uint64_t getOffsetFromBase() const {
8871 assert(DAG && "Missing context.");
8873 DAG->getTargetLoweringInfo().getDataLayout()->isBigEndian();
8874 assert(!(Shift & 0x7) && "Shifts not aligned on Bytes are not supported.");
8875 uint64_t Offset = Shift / 8;
8876 unsigned TySizeInBytes = Origin->getValueSizeInBits(0) / 8;
8877 assert(!(Origin->getValueSizeInBits(0) & 0x7) &&
8878 "The size of the original loaded type is not a multiple of a"
8880 // If Offset is bigger than TySizeInBytes, it means we are loading all
8881 // zeros. This should have been optimized before in the process.
8882 assert(TySizeInBytes > Offset &&
8883 "Invalid shift amount for given loaded size");
8885 Offset = TySizeInBytes - Offset - getLoadedSize();
8889 /// \brief Generate the sequence of instructions to load the slice
8890 /// represented by this object and redirect the uses of this slice to
8891 /// this new sequence of instructions.
8892 /// \pre this->Inst && this->Origin are valid Instructions and this
8893 /// object passed the legal check: LoadedSlice::isLegal returned true.
8894 /// \return The last instruction of the sequence used to load the slice.
8895 SDValue loadSlice() const {
8896 assert(Inst && Origin && "Unable to replace a non-existing slice.");
8897 const SDValue &OldBaseAddr = Origin->getBasePtr();
8898 SDValue BaseAddr = OldBaseAddr;
8899 // Get the offset in that chunk of bytes w.r.t. the endianess.
8900 int64_t Offset = static_cast<int64_t>(getOffsetFromBase());
8901 assert(Offset >= 0 && "Offset too big to fit in int64_t!");
8903 // BaseAddr = BaseAddr + Offset.
8904 EVT ArithType = BaseAddr.getValueType();
8905 BaseAddr = DAG->getNode(ISD::ADD, SDLoc(Origin), ArithType, BaseAddr,
8906 DAG->getConstant(Offset, ArithType));
8909 // Create the type of the loaded slice according to its size.
8910 EVT SliceType = getLoadedType();
8912 // Create the load for the slice.
8913 SDValue LastInst = DAG->getLoad(
8914 SliceType, SDLoc(Origin), Origin->getChain(), BaseAddr,
8915 Origin->getPointerInfo().getWithOffset(Offset), Origin->isVolatile(),
8916 Origin->isNonTemporal(), Origin->isInvariant(), getAlignment());
8917 // If the final type is not the same as the loaded type, this means that
8918 // we have to pad with zero. Create a zero extend for that.
8919 EVT FinalType = Inst->getValueType(0);
8920 if (SliceType != FinalType)
8922 DAG->getNode(ISD::ZERO_EXTEND, SDLoc(LastInst), FinalType, LastInst);
8926 /// \brief Check if this slice can be merged with an expensive cross register
8927 /// bank copy. E.g.,
8929 /// f = bitcast i32 i to float
8930 bool canMergeExpensiveCrossRegisterBankCopy() const {
8931 if (!Inst || !Inst->hasOneUse())
8933 SDNode *Use = *Inst->use_begin();
8934 if (Use->getOpcode() != ISD::BITCAST)
8936 assert(DAG && "Missing context");
8937 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
8938 EVT ResVT = Use->getValueType(0);
8939 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT());
8940 const TargetRegisterClass *ArgRC =
8941 TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT());
8942 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT))
8945 // At this point, we know that we perform a cross-register-bank copy.
8946 // Check if it is expensive.
8947 const TargetRegisterInfo *TRI = DAG->getSubtarget().getRegisterInfo();
8948 // Assume bitcasts are cheap, unless both register classes do not
8949 // explicitly share a common sub class.
8950 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC))
8953 // Check if it will be merged with the load.
8954 // 1. Check the alignment constraint.
8955 unsigned RequiredAlignment = TLI.getDataLayout()->getABITypeAlignment(
8956 ResVT.getTypeForEVT(*DAG->getContext()));
8958 if (RequiredAlignment > getAlignment())
8961 // 2. Check that the load is a legal operation for that type.
8962 if (!TLI.isOperationLegal(ISD::LOAD, ResVT))
8965 // 3. Check that we do not have a zext in the way.
8966 if (Inst->getValueType(0) != getLoadedType())
8974 /// \brief Check that all bits set in \p UsedBits form a dense region, i.e.,
8975 /// \p UsedBits looks like 0..0 1..1 0..0.
8976 static bool areUsedBitsDense(const APInt &UsedBits) {
8977 // If all the bits are one, this is dense!
8978 if (UsedBits.isAllOnesValue())
8981 // Get rid of the unused bits on the right.
8982 APInt NarrowedUsedBits = UsedBits.lshr(UsedBits.countTrailingZeros());
8983 // Get rid of the unused bits on the left.
8984 if (NarrowedUsedBits.countLeadingZeros())
8985 NarrowedUsedBits = NarrowedUsedBits.trunc(NarrowedUsedBits.getActiveBits());
8986 // Check that the chunk of bits is completely used.
8987 return NarrowedUsedBits.isAllOnesValue();
8990 /// \brief Check whether or not \p First and \p Second are next to each other
8991 /// in memory. This means that there is no hole between the bits loaded
8992 /// by \p First and the bits loaded by \p Second.
8993 static bool areSlicesNextToEachOther(const LoadedSlice &First,
8994 const LoadedSlice &Second) {
8995 assert(First.Origin == Second.Origin && First.Origin &&
8996 "Unable to match different memory origins.");
8997 APInt UsedBits = First.getUsedBits();
8998 assert((UsedBits & Second.getUsedBits()) == 0 &&
8999 "Slices are not supposed to overlap.");
9000 UsedBits |= Second.getUsedBits();
9001 return areUsedBitsDense(UsedBits);
9004 /// \brief Adjust the \p GlobalLSCost according to the target
9005 /// paring capabilities and the layout of the slices.
9006 /// \pre \p GlobalLSCost should account for at least as many loads as
9007 /// there is in the slices in \p LoadedSlices.
9008 static void adjustCostForPairing(SmallVectorImpl<LoadedSlice> &LoadedSlices,
9009 LoadedSlice::Cost &GlobalLSCost) {
9010 unsigned NumberOfSlices = LoadedSlices.size();
9011 // If there is less than 2 elements, no pairing is possible.
9012 if (NumberOfSlices < 2)
9015 // Sort the slices so that elements that are likely to be next to each
9016 // other in memory are next to each other in the list.
9017 std::sort(LoadedSlices.begin(), LoadedSlices.end(),
9018 [](const LoadedSlice &LHS, const LoadedSlice &RHS) {
9019 assert(LHS.Origin == RHS.Origin && "Different bases not implemented.");
9020 return LHS.getOffsetFromBase() < RHS.getOffsetFromBase();
9022 const TargetLowering &TLI = LoadedSlices[0].DAG->getTargetLoweringInfo();
9023 // First (resp. Second) is the first (resp. Second) potentially candidate
9024 // to be placed in a paired load.
9025 const LoadedSlice *First = nullptr;
9026 const LoadedSlice *Second = nullptr;
9027 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice,
9028 // Set the beginning of the pair.
9031 Second = &LoadedSlices[CurrSlice];
9033 // If First is NULL, it means we start a new pair.
9034 // Get to the next slice.
9038 EVT LoadedType = First->getLoadedType();
9040 // If the types of the slices are different, we cannot pair them.
9041 if (LoadedType != Second->getLoadedType())
9044 // Check if the target supplies paired loads for this type.
9045 unsigned RequiredAlignment = 0;
9046 if (!TLI.hasPairedLoad(LoadedType, RequiredAlignment)) {
9047 // move to the next pair, this type is hopeless.
9051 // Check if we meet the alignment requirement.
9052 if (RequiredAlignment > First->getAlignment())
9055 // Check that both loads are next to each other in memory.
9056 if (!areSlicesNextToEachOther(*First, *Second))
9059 assert(GlobalLSCost.Loads > 0 && "We save more loads than we created!");
9060 --GlobalLSCost.Loads;
9061 // Move to the next pair.
9066 /// \brief Check the profitability of all involved LoadedSlice.
9067 /// Currently, it is considered profitable if there is exactly two
9068 /// involved slices (1) which are (2) next to each other in memory, and
9069 /// whose cost (\see LoadedSlice::Cost) is smaller than the original load (3).
9071 /// Note: The order of the elements in \p LoadedSlices may be modified, but not
9072 /// the elements themselves.
9074 /// FIXME: When the cost model will be mature enough, we can relax
9075 /// constraints (1) and (2).
9076 static bool isSlicingProfitable(SmallVectorImpl<LoadedSlice> &LoadedSlices,
9077 const APInt &UsedBits, bool ForCodeSize) {
9078 unsigned NumberOfSlices = LoadedSlices.size();
9079 if (StressLoadSlicing)
9080 return NumberOfSlices > 1;
9083 if (NumberOfSlices != 2)
9087 if (!areUsedBitsDense(UsedBits))
9091 LoadedSlice::Cost OrigCost(ForCodeSize), GlobalSlicingCost(ForCodeSize);
9092 // The original code has one big load.
9094 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice) {
9095 const LoadedSlice &LS = LoadedSlices[CurrSlice];
9096 // Accumulate the cost of all the slices.
9097 LoadedSlice::Cost SliceCost(LS, ForCodeSize);
9098 GlobalSlicingCost += SliceCost;
9100 // Account as cost in the original configuration the gain obtained
9101 // with the current slices.
9102 OrigCost.addSliceGain(LS);
9105 // If the target supports paired load, adjust the cost accordingly.
9106 adjustCostForPairing(LoadedSlices, GlobalSlicingCost);
9107 return OrigCost > GlobalSlicingCost;
9110 /// \brief If the given load, \p LI, is used only by trunc or trunc(lshr)
9111 /// operations, split it in the various pieces being extracted.
9113 /// This sort of thing is introduced by SROA.
9114 /// This slicing takes care not to insert overlapping loads.
9115 /// \pre LI is a simple load (i.e., not an atomic or volatile load).
9116 bool DAGCombiner::SliceUpLoad(SDNode *N) {
9117 if (Level < AfterLegalizeDAG)
9120 LoadSDNode *LD = cast<LoadSDNode>(N);
9121 if (LD->isVolatile() || !ISD::isNormalLoad(LD) ||
9122 !LD->getValueType(0).isInteger())
9125 // Keep track of already used bits to detect overlapping values.
9126 // In that case, we will just abort the transformation.
9127 APInt UsedBits(LD->getValueSizeInBits(0), 0);
9129 SmallVector<LoadedSlice, 4> LoadedSlices;
9131 // Check if this load is used as several smaller chunks of bits.
9132 // Basically, look for uses in trunc or trunc(lshr) and record a new chain
9133 // of computation for each trunc.
9134 for (SDNode::use_iterator UI = LD->use_begin(), UIEnd = LD->use_end();
9135 UI != UIEnd; ++UI) {
9136 // Skip the uses of the chain.
9137 if (UI.getUse().getResNo() != 0)
9143 // Check if this is a trunc(lshr).
9144 if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
9145 isa<ConstantSDNode>(User->getOperand(1))) {
9146 Shift = cast<ConstantSDNode>(User->getOperand(1))->getZExtValue();
9147 User = *User->use_begin();
9150 // At this point, User is a Truncate, iff we encountered, trunc or
9152 if (User->getOpcode() != ISD::TRUNCATE)
9155 // The width of the type must be a power of 2 and greater than 8-bits.
9156 // Otherwise the load cannot be represented in LLVM IR.
9157 // Moreover, if we shifted with a non-8-bits multiple, the slice
9158 // will be across several bytes. We do not support that.
9159 unsigned Width = User->getValueSizeInBits(0);
9160 if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7))
9163 // Build the slice for this chain of computations.
9164 LoadedSlice LS(User, LD, Shift, &DAG);
9165 APInt CurrentUsedBits = LS.getUsedBits();
9167 // Check if this slice overlaps with another.
9168 if ((CurrentUsedBits & UsedBits) != 0)
9170 // Update the bits used globally.
9171 UsedBits |= CurrentUsedBits;
9173 // Check if the new slice would be legal.
9177 // Record the slice.
9178 LoadedSlices.push_back(LS);
9181 // Abort slicing if it does not seem to be profitable.
9182 if (!isSlicingProfitable(LoadedSlices, UsedBits, ForCodeSize))
9187 // Rewrite each chain to use an independent load.
9188 // By construction, each chain can be represented by a unique load.
9190 // Prepare the argument for the new token factor for all the slices.
9191 SmallVector<SDValue, 8> ArgChains;
9192 for (SmallVectorImpl<LoadedSlice>::const_iterator
9193 LSIt = LoadedSlices.begin(),
9194 LSItEnd = LoadedSlices.end();
9195 LSIt != LSItEnd; ++LSIt) {
9196 SDValue SliceInst = LSIt->loadSlice();
9197 CombineTo(LSIt->Inst, SliceInst, true);
9198 if (SliceInst.getNode()->getOpcode() != ISD::LOAD)
9199 SliceInst = SliceInst.getOperand(0);
9200 assert(SliceInst->getOpcode() == ISD::LOAD &&
9201 "It takes more than a zext to get to the loaded slice!!");
9202 ArgChains.push_back(SliceInst.getValue(1));
9205 SDValue Chain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other,
9207 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
9211 /// Check to see if V is (and load (ptr), imm), where the load is having
9212 /// specific bytes cleared out. If so, return the byte size being masked out
9213 /// and the shift amount.
9214 static std::pair<unsigned, unsigned>
9215 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
9216 std::pair<unsigned, unsigned> Result(0, 0);
9218 // Check for the structure we're looking for.
9219 if (V->getOpcode() != ISD::AND ||
9220 !isa<ConstantSDNode>(V->getOperand(1)) ||
9221 !ISD::isNormalLoad(V->getOperand(0).getNode()))
9224 // Check the chain and pointer.
9225 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
9226 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
9228 // The store should be chained directly to the load or be an operand of a
9230 if (LD == Chain.getNode())
9232 else if (Chain->getOpcode() != ISD::TokenFactor)
9233 return Result; // Fail.
9236 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
9237 if (Chain->getOperand(i).getNode() == LD) {
9241 if (!isOk) return Result;
9244 // This only handles simple types.
9245 if (V.getValueType() != MVT::i16 &&
9246 V.getValueType() != MVT::i32 &&
9247 V.getValueType() != MVT::i64)
9250 // Check the constant mask. Invert it so that the bits being masked out are
9251 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
9252 // follow the sign bit for uniformity.
9253 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
9254 unsigned NotMaskLZ = countLeadingZeros(NotMask);
9255 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
9256 unsigned NotMaskTZ = countTrailingZeros(NotMask);
9257 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
9258 if (NotMaskLZ == 64) return Result; // All zero mask.
9260 // See if we have a continuous run of bits. If so, we have 0*1+0*
9261 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
9264 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
9265 if (V.getValueType() != MVT::i64 && NotMaskLZ)
9266 NotMaskLZ -= 64-V.getValueSizeInBits();
9268 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
9269 switch (MaskedBytes) {
9273 default: return Result; // All one mask, or 5-byte mask.
9276 // Verify that the first bit starts at a multiple of mask so that the access
9277 // is aligned the same as the access width.
9278 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
9280 Result.first = MaskedBytes;
9281 Result.second = NotMaskTZ/8;
9286 /// Check to see if IVal is something that provides a value as specified by
9287 /// MaskInfo. If so, replace the specified store with a narrower store of
9290 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
9291 SDValue IVal, StoreSDNode *St,
9293 unsigned NumBytes = MaskInfo.first;
9294 unsigned ByteShift = MaskInfo.second;
9295 SelectionDAG &DAG = DC->getDAG();
9297 // Check to see if IVal is all zeros in the part being masked in by the 'or'
9298 // that uses this. If not, this is not a replacement.
9299 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
9300 ByteShift*8, (ByteShift+NumBytes)*8);
9301 if (!DAG.MaskedValueIsZero(IVal, Mask)) return nullptr;
9303 // Check that it is legal on the target to do this. It is legal if the new
9304 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
9306 MVT VT = MVT::getIntegerVT(NumBytes*8);
9307 if (!DC->isTypeLegal(VT))
9310 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
9311 // shifted by ByteShift and truncated down to NumBytes.
9313 IVal = DAG.getNode(ISD::SRL, SDLoc(IVal), IVal.getValueType(), IVal,
9314 DAG.getConstant(ByteShift*8,
9315 DC->getShiftAmountTy(IVal.getValueType())));
9317 // Figure out the offset for the store and the alignment of the access.
9319 unsigned NewAlign = St->getAlignment();
9321 if (DAG.getTargetLoweringInfo().isLittleEndian())
9322 StOffset = ByteShift;
9324 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
9326 SDValue Ptr = St->getBasePtr();
9328 Ptr = DAG.getNode(ISD::ADD, SDLoc(IVal), Ptr.getValueType(),
9329 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
9330 NewAlign = MinAlign(NewAlign, StOffset);
9333 // Truncate down to the new size.
9334 IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal);
9337 return DAG.getStore(St->getChain(), SDLoc(St), IVal, Ptr,
9338 St->getPointerInfo().getWithOffset(StOffset),
9339 false, false, NewAlign).getNode();
9343 /// Look for sequence of load / op / store where op is one of 'or', 'xor', and
9344 /// 'and' of immediates. If 'op' is only touching some of the loaded bits, try
9345 /// narrowing the load and store if it would end up being a win for performance
9347 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
9348 StoreSDNode *ST = cast<StoreSDNode>(N);
9349 if (ST->isVolatile())
9352 SDValue Chain = ST->getChain();
9353 SDValue Value = ST->getValue();
9354 SDValue Ptr = ST->getBasePtr();
9355 EVT VT = Value.getValueType();
9357 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
9360 unsigned Opc = Value.getOpcode();
9362 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
9363 // is a byte mask indicating a consecutive number of bytes, check to see if
9364 // Y is known to provide just those bytes. If so, we try to replace the
9365 // load + replace + store sequence with a single (narrower) store, which makes
9367 if (Opc == ISD::OR) {
9368 std::pair<unsigned, unsigned> MaskedLoad;
9369 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
9370 if (MaskedLoad.first)
9371 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
9372 Value.getOperand(1), ST,this))
9373 return SDValue(NewST, 0);
9375 // Or is commutative, so try swapping X and Y.
9376 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
9377 if (MaskedLoad.first)
9378 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
9379 Value.getOperand(0), ST,this))
9380 return SDValue(NewST, 0);
9383 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
9384 Value.getOperand(1).getOpcode() != ISD::Constant)
9387 SDValue N0 = Value.getOperand(0);
9388 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
9389 Chain == SDValue(N0.getNode(), 1)) {
9390 LoadSDNode *LD = cast<LoadSDNode>(N0);
9391 if (LD->getBasePtr() != Ptr ||
9392 LD->getPointerInfo().getAddrSpace() !=
9393 ST->getPointerInfo().getAddrSpace())
9396 // Find the type to narrow it the load / op / store to.
9397 SDValue N1 = Value.getOperand(1);
9398 unsigned BitWidth = N1.getValueSizeInBits();
9399 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
9400 if (Opc == ISD::AND)
9401 Imm ^= APInt::getAllOnesValue(BitWidth);
9402 if (Imm == 0 || Imm.isAllOnesValue())
9404 unsigned ShAmt = Imm.countTrailingZeros();
9405 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
9406 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
9407 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
9408 while (NewBW < BitWidth &&
9409 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
9410 TLI.isNarrowingProfitable(VT, NewVT))) {
9411 NewBW = NextPowerOf2(NewBW);
9412 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
9414 if (NewBW >= BitWidth)
9417 // If the lsb changed does not start at the type bitwidth boundary,
9418 // start at the previous one.
9420 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
9421 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt,
9422 std::min(BitWidth, ShAmt + NewBW));
9423 if ((Imm & Mask) == Imm) {
9424 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
9425 if (Opc == ISD::AND)
9426 NewImm ^= APInt::getAllOnesValue(NewBW);
9427 uint64_t PtrOff = ShAmt / 8;
9428 // For big endian targets, we need to adjust the offset to the pointer to
9429 // load the correct bytes.
9430 if (TLI.isBigEndian())
9431 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
9433 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
9434 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
9435 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy))
9438 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LD),
9439 Ptr.getValueType(), Ptr,
9440 DAG.getConstant(PtrOff, Ptr.getValueType()));
9441 SDValue NewLD = DAG.getLoad(NewVT, SDLoc(N0),
9442 LD->getChain(), NewPtr,
9443 LD->getPointerInfo().getWithOffset(PtrOff),
9444 LD->isVolatile(), LD->isNonTemporal(),
9445 LD->isInvariant(), NewAlign,
9447 SDValue NewVal = DAG.getNode(Opc, SDLoc(Value), NewVT, NewLD,
9448 DAG.getConstant(NewImm, NewVT));
9449 SDValue NewST = DAG.getStore(Chain, SDLoc(N),
9451 ST->getPointerInfo().getWithOffset(PtrOff),
9452 false, false, NewAlign);
9454 AddToWorklist(NewPtr.getNode());
9455 AddToWorklist(NewLD.getNode());
9456 AddToWorklist(NewVal.getNode());
9457 WorklistRemover DeadNodes(*this);
9458 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
9467 /// For a given floating point load / store pair, if the load value isn't used
9468 /// by any other operations, then consider transforming the pair to integer
9469 /// load / store operations if the target deems the transformation profitable.
9470 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
9471 StoreSDNode *ST = cast<StoreSDNode>(N);
9472 SDValue Chain = ST->getChain();
9473 SDValue Value = ST->getValue();
9474 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
9475 Value.hasOneUse() &&
9476 Chain == SDValue(Value.getNode(), 1)) {
9477 LoadSDNode *LD = cast<LoadSDNode>(Value);
9478 EVT VT = LD->getMemoryVT();
9479 if (!VT.isFloatingPoint() ||
9480 VT != ST->getMemoryVT() ||
9481 LD->isNonTemporal() ||
9482 ST->isNonTemporal() ||
9483 LD->getPointerInfo().getAddrSpace() != 0 ||
9484 ST->getPointerInfo().getAddrSpace() != 0)
9487 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
9488 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
9489 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
9490 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
9491 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
9494 unsigned LDAlign = LD->getAlignment();
9495 unsigned STAlign = ST->getAlignment();
9496 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
9497 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy);
9498 if (LDAlign < ABIAlign || STAlign < ABIAlign)
9501 SDValue NewLD = DAG.getLoad(IntVT, SDLoc(Value),
9502 LD->getChain(), LD->getBasePtr(),
9503 LD->getPointerInfo(),
9504 false, false, false, LDAlign);
9506 SDValue NewST = DAG.getStore(NewLD.getValue(1), SDLoc(N),
9507 NewLD, ST->getBasePtr(),
9508 ST->getPointerInfo(),
9509 false, false, STAlign);
9511 AddToWorklist(NewLD.getNode());
9512 AddToWorklist(NewST.getNode());
9513 WorklistRemover DeadNodes(*this);
9514 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
9522 /// Helper struct to parse and store a memory address as base + index + offset.
9523 /// We ignore sign extensions when it is safe to do so.
9524 /// The following two expressions are not equivalent. To differentiate we need
9525 /// to store whether there was a sign extension involved in the index
9527 /// (load (i64 add (i64 copyfromreg %c)
9528 /// (i64 signextend (add (i8 load %index)
9532 /// (load (i64 add (i64 copyfromreg %c)
9533 /// (i64 signextend (i32 add (i32 signextend (i8 load %index))
9535 struct BaseIndexOffset {
9539 bool IsIndexSignExt;
9541 BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {}
9543 BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
9544 bool IsIndexSignExt) :
9545 Base(Base), Index(Index), Offset(Offset), IsIndexSignExt(IsIndexSignExt) {}
9547 bool equalBaseIndex(const BaseIndexOffset &Other) {
9548 return Other.Base == Base && Other.Index == Index &&
9549 Other.IsIndexSignExt == IsIndexSignExt;
9552 /// Parses tree in Ptr for base, index, offset addresses.
9553 static BaseIndexOffset match(SDValue Ptr) {
9554 bool IsIndexSignExt = false;
9556 // We only can pattern match BASE + INDEX + OFFSET. If Ptr is not an ADD
9557 // instruction, then it could be just the BASE or everything else we don't
9558 // know how to handle. Just use Ptr as BASE and give up.
9559 if (Ptr->getOpcode() != ISD::ADD)
9560 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
9562 // We know that we have at least an ADD instruction. Try to pattern match
9563 // the simple case of BASE + OFFSET.
9564 if (isa<ConstantSDNode>(Ptr->getOperand(1))) {
9565 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
9566 return BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset,
9570 // Inside a loop the current BASE pointer is calculated using an ADD and a
9571 // MUL instruction. In this case Ptr is the actual BASE pointer.
9572 // (i64 add (i64 %array_ptr)
9573 // (i64 mul (i64 %induction_var)
9574 // (i64 %element_size)))
9575 if (Ptr->getOperand(1)->getOpcode() == ISD::MUL)
9576 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
9578 // Look at Base + Index + Offset cases.
9579 SDValue Base = Ptr->getOperand(0);
9580 SDValue IndexOffset = Ptr->getOperand(1);
9582 // Skip signextends.
9583 if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) {
9584 IndexOffset = IndexOffset->getOperand(0);
9585 IsIndexSignExt = true;
9588 // Either the case of Base + Index (no offset) or something else.
9589 if (IndexOffset->getOpcode() != ISD::ADD)
9590 return BaseIndexOffset(Base, IndexOffset, 0, IsIndexSignExt);
9592 // Now we have the case of Base + Index + offset.
9593 SDValue Index = IndexOffset->getOperand(0);
9594 SDValue Offset = IndexOffset->getOperand(1);
9596 if (!isa<ConstantSDNode>(Offset))
9597 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
9599 // Ignore signextends.
9600 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
9601 Index = Index->getOperand(0);
9602 IsIndexSignExt = true;
9603 } else IsIndexSignExt = false;
9605 int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue();
9606 return BaseIndexOffset(Base, Index, Off, IsIndexSignExt);
9610 /// Holds a pointer to an LSBaseSDNode as well as information on where it
9611 /// is located in a sequence of memory operations connected by a chain.
9613 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq):
9614 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { }
9615 // Ptr to the mem node.
9616 LSBaseSDNode *MemNode;
9617 // Offset from the base ptr.
9618 int64_t OffsetFromBase;
9619 // What is the sequence number of this mem node.
9620 // Lowest mem operand in the DAG starts at zero.
9621 unsigned SequenceNum;
9624 bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
9625 EVT MemVT = St->getMemoryVT();
9626 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8;
9627 bool NoVectors = DAG.getMachineFunction().getFunction()->getAttributes().
9628 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
9630 // Don't merge vectors into wider inputs.
9631 if (MemVT.isVector() || !MemVT.isSimple())
9634 // Perform an early exit check. Do not bother looking at stored values that
9635 // are not constants or loads.
9636 SDValue StoredVal = St->getValue();
9637 bool IsLoadSrc = isa<LoadSDNode>(StoredVal);
9638 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) &&
9642 // Only look at ends of store sequences.
9643 SDValue Chain = SDValue(St, 0);
9644 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
9647 // This holds the base pointer, index, and the offset in bytes from the base
9649 BaseIndexOffset BasePtr = BaseIndexOffset::match(St->getBasePtr());
9651 // We must have a base and an offset.
9652 if (!BasePtr.Base.getNode())
9655 // Do not handle stores to undef base pointers.
9656 if (BasePtr.Base.getOpcode() == ISD::UNDEF)
9659 // Save the LoadSDNodes that we find in the chain.
9660 // We need to make sure that these nodes do not interfere with
9661 // any of the store nodes.
9662 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
9664 // Save the StoreSDNodes that we find in the chain.
9665 SmallVector<MemOpLink, 8> StoreNodes;
9667 // Walk up the chain and look for nodes with offsets from the same
9668 // base pointer. Stop when reaching an instruction with a different kind
9669 // or instruction which has a different base pointer.
9671 StoreSDNode *Index = St;
9673 // If the chain has more than one use, then we can't reorder the mem ops.
9674 if (Index != St && !SDValue(Index, 0)->hasOneUse())
9677 // Find the base pointer and offset for this memory node.
9678 BaseIndexOffset Ptr = BaseIndexOffset::match(Index->getBasePtr());
9680 // Check that the base pointer is the same as the original one.
9681 if (!Ptr.equalBaseIndex(BasePtr))
9684 // Check that the alignment is the same.
9685 if (Index->getAlignment() != St->getAlignment())
9688 // The memory operands must not be volatile.
9689 if (Index->isVolatile() || Index->isIndexed())
9693 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index))
9694 if (St->isTruncatingStore())
9697 // The stored memory type must be the same.
9698 if (Index->getMemoryVT() != MemVT)
9701 // We do not allow unaligned stores because we want to prevent overriding
9703 if (Index->getAlignment()*8 != MemVT.getSizeInBits())
9706 // We found a potential memory operand to merge.
9707 StoreNodes.push_back(MemOpLink(Index, Ptr.Offset, Seq++));
9709 // Find the next memory operand in the chain. If the next operand in the
9710 // chain is a store then move up and continue the scan with the next
9711 // memory operand. If the next operand is a load save it and use alias
9712 // information to check if it interferes with anything.
9713 SDNode *NextInChain = Index->getChain().getNode();
9715 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) {
9716 // We found a store node. Use it for the next iteration.
9719 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) {
9720 if (Ldn->isVolatile()) {
9725 // Save the load node for later. Continue the scan.
9726 AliasLoadNodes.push_back(Ldn);
9727 NextInChain = Ldn->getChain().getNode();
9736 // Check if there is anything to merge.
9737 if (StoreNodes.size() < 2)
9740 // Sort the memory operands according to their distance from the base pointer.
9741 std::sort(StoreNodes.begin(), StoreNodes.end(),
9742 [](MemOpLink LHS, MemOpLink RHS) {
9743 return LHS.OffsetFromBase < RHS.OffsetFromBase ||
9744 (LHS.OffsetFromBase == RHS.OffsetFromBase &&
9745 LHS.SequenceNum > RHS.SequenceNum);
9748 // Scan the memory operations on the chain and find the first non-consecutive
9749 // store memory address.
9750 unsigned LastConsecutiveStore = 0;
9751 int64_t StartAddress = StoreNodes[0].OffsetFromBase;
9752 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) {
9754 // Check that the addresses are consecutive starting from the second
9755 // element in the list of stores.
9757 int64_t CurrAddress = StoreNodes[i].OffsetFromBase;
9758 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
9763 // Check if this store interferes with any of the loads that we found.
9764 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld)
9765 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) {
9769 // We found a load that alias with this store. Stop the sequence.
9773 // Mark this node as useful.
9774 LastConsecutiveStore = i;
9777 // The node with the lowest store address.
9778 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
9780 // Store the constants into memory as one consecutive store.
9782 unsigned LastLegalType = 0;
9783 unsigned LastLegalVectorType = 0;
9784 bool NonZero = false;
9785 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
9786 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9787 SDValue StoredVal = St->getValue();
9789 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) {
9790 NonZero |= !C->isNullValue();
9791 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
9792 NonZero |= !C->getConstantFPValue()->isNullValue();
9798 // Find a legal type for the constant store.
9799 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
9800 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9801 if (TLI.isTypeLegal(StoreTy))
9802 LastLegalType = i+1;
9803 // Or check whether a truncstore is legal.
9804 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
9805 TargetLowering::TypePromoteInteger) {
9806 EVT LegalizedStoredValueTy =
9807 TLI.getTypeToTransformTo(*DAG.getContext(), StoredVal.getValueType());
9808 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy))
9809 LastLegalType = i+1;
9812 // Find a legal type for the vector store.
9813 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
9814 if (TLI.isTypeLegal(Ty))
9815 LastLegalVectorType = i + 1;
9818 // We only use vectors if the constant is known to be zero and the
9819 // function is not marked with the noimplicitfloat attribute.
9820 if (NonZero || NoVectors)
9821 LastLegalVectorType = 0;
9823 // Check if we found a legal integer type to store.
9824 if (LastLegalType == 0 && LastLegalVectorType == 0)
9827 bool UseVector = (LastLegalVectorType > LastLegalType) && !NoVectors;
9828 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType;
9830 // Make sure we have something to merge.
9834 unsigned EarliestNodeUsed = 0;
9835 for (unsigned i=0; i < NumElem; ++i) {
9836 // Find a chain for the new wide-store operand. Notice that some
9837 // of the store nodes that we found may not be selected for inclusion
9838 // in the wide store. The chain we use needs to be the chain of the
9839 // earliest store node which is *used* and replaced by the wide store.
9840 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
9841 EarliestNodeUsed = i;
9844 // The earliest Node in the DAG.
9845 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
9846 SDLoc DL(StoreNodes[0].MemNode);
9850 // Find a legal type for the vector store.
9851 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
9852 assert(TLI.isTypeLegal(Ty) && "Illegal vector store");
9853 StoredVal = DAG.getConstant(0, Ty);
9855 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
9856 APInt StoreInt(StoreBW, 0);
9858 // Construct a single integer constant which is made of the smaller
9860 bool IsLE = TLI.isLittleEndian();
9861 for (unsigned i = 0; i < NumElem ; ++i) {
9862 unsigned Idx = IsLE ?(NumElem - 1 - i) : i;
9863 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode);
9864 SDValue Val = St->getValue();
9865 StoreInt<<=ElementSizeBytes*8;
9866 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) {
9867 StoreInt|=C->getAPIntValue().zext(StoreBW);
9868 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
9869 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW);
9871 llvm_unreachable("Invalid constant element type");
9875 // Create the new Load and Store operations.
9876 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9877 StoredVal = DAG.getConstant(StoreInt, StoreTy);
9880 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal,
9881 FirstInChain->getBasePtr(),
9882 FirstInChain->getPointerInfo(),
9884 FirstInChain->getAlignment());
9886 // Replace the first store with the new store
9887 CombineTo(EarliestOp, NewStore);
9888 // Erase all other stores.
9889 for (unsigned i = 0; i < NumElem ; ++i) {
9890 if (StoreNodes[i].MemNode == EarliestOp)
9892 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9893 // ReplaceAllUsesWith will replace all uses that existed when it was
9894 // called, but graph optimizations may cause new ones to appear. For
9895 // example, the case in pr14333 looks like
9897 // St's chain -> St -> another store -> X
9899 // And the only difference from St to the other store is the chain.
9900 // When we change it's chain to be St's chain they become identical,
9901 // get CSEed and the net result is that X is now a use of St.
9902 // Since we know that St is redundant, just iterate.
9903 while (!St->use_empty())
9904 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain());
9905 deleteAndRecombine(St);
9911 // Below we handle the case of multiple consecutive stores that
9912 // come from multiple consecutive loads. We merge them into a single
9913 // wide load and a single wide store.
9915 // Look for load nodes which are used by the stored values.
9916 SmallVector<MemOpLink, 8> LoadNodes;
9918 // Find acceptable loads. Loads need to have the same chain (token factor),
9919 // must not be zext, volatile, indexed, and they must be consecutive.
9920 BaseIndexOffset LdBasePtr;
9921 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
9922 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9923 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
9926 // Loads must only have one use.
9927 if (!Ld->hasNUsesOfValue(1, 0))
9930 // Check that the alignment is the same as the stores.
9931 if (Ld->getAlignment() != St->getAlignment())
9934 // The memory operands must not be volatile.
9935 if (Ld->isVolatile() || Ld->isIndexed())
9938 // We do not accept ext loads.
9939 if (Ld->getExtensionType() != ISD::NON_EXTLOAD)
9942 // The stored memory type must be the same.
9943 if (Ld->getMemoryVT() != MemVT)
9946 BaseIndexOffset LdPtr = BaseIndexOffset::match(Ld->getBasePtr());
9947 // If this is not the first ptr that we check.
9948 if (LdBasePtr.Base.getNode()) {
9949 // The base ptr must be the same.
9950 if (!LdPtr.equalBaseIndex(LdBasePtr))
9953 // Check that all other base pointers are the same as this one.
9957 // We found a potential memory operand to merge.
9958 LoadNodes.push_back(MemOpLink(Ld, LdPtr.Offset, 0));
9961 if (LoadNodes.size() < 2)
9964 // If we have load/store pair instructions and we only have two values,
9966 unsigned RequiredAlignment;
9967 if (LoadNodes.size() == 2 && TLI.hasPairedLoad(MemVT, RequiredAlignment) &&
9968 St->getAlignment() >= RequiredAlignment)
9971 // Scan the memory operations on the chain and find the first non-consecutive
9972 // load memory address. These variables hold the index in the store node
9974 unsigned LastConsecutiveLoad = 0;
9975 // This variable refers to the size and not index in the array.
9976 unsigned LastLegalVectorType = 0;
9977 unsigned LastLegalIntegerType = 0;
9978 StartAddress = LoadNodes[0].OffsetFromBase;
9979 SDValue FirstChain = LoadNodes[0].MemNode->getChain();
9980 for (unsigned i = 1; i < LoadNodes.size(); ++i) {
9981 // All loads much share the same chain.
9982 if (LoadNodes[i].MemNode->getChain() != FirstChain)
9985 int64_t CurrAddress = LoadNodes[i].OffsetFromBase;
9986 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
9988 LastConsecutiveLoad = i;
9990 // Find a legal type for the vector store.
9991 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
9992 if (TLI.isTypeLegal(StoreTy))
9993 LastLegalVectorType = i + 1;
9995 // Find a legal type for the integer store.
9996 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
9997 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9998 if (TLI.isTypeLegal(StoreTy))
9999 LastLegalIntegerType = i + 1;
10000 // Or check whether a truncstore and extload is legal.
10001 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
10002 TargetLowering::TypePromoteInteger) {
10003 EVT LegalizedStoredValueTy =
10004 TLI.getTypeToTransformTo(*DAG.getContext(), StoreTy);
10005 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
10006 TLI.isLoadExtLegal(ISD::ZEXTLOAD, StoreTy) &&
10007 TLI.isLoadExtLegal(ISD::SEXTLOAD, StoreTy) &&
10008 TLI.isLoadExtLegal(ISD::EXTLOAD, StoreTy))
10009 LastLegalIntegerType = i+1;
10013 // Only use vector types if the vector type is larger than the integer type.
10014 // If they are the same, use integers.
10015 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType && !NoVectors;
10016 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType);
10018 // We add +1 here because the LastXXX variables refer to location while
10019 // the NumElem refers to array/index size.
10020 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1;
10021 NumElem = std::min(LastLegalType, NumElem);
10026 // The earliest Node in the DAG.
10027 unsigned EarliestNodeUsed = 0;
10028 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
10029 for (unsigned i=1; i<NumElem; ++i) {
10030 // Find a chain for the new wide-store operand. Notice that some
10031 // of the store nodes that we found may not be selected for inclusion
10032 // in the wide store. The chain we use needs to be the chain of the
10033 // earliest store node which is *used* and replaced by the wide store.
10034 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
10035 EarliestNodeUsed = i;
10038 // Find if it is better to use vectors or integers to load and store
10042 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
10044 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
10045 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
10048 SDLoc LoadDL(LoadNodes[0].MemNode);
10049 SDLoc StoreDL(StoreNodes[0].MemNode);
10051 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode);
10052 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL,
10053 FirstLoad->getChain(),
10054 FirstLoad->getBasePtr(),
10055 FirstLoad->getPointerInfo(),
10056 false, false, false,
10057 FirstLoad->getAlignment());
10059 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad,
10060 FirstInChain->getBasePtr(),
10061 FirstInChain->getPointerInfo(), false, false,
10062 FirstInChain->getAlignment());
10064 // Replace one of the loads with the new load.
10065 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode);
10066 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1),
10067 SDValue(NewLoad.getNode(), 1));
10069 // Remove the rest of the load chains.
10070 for (unsigned i = 1; i < NumElem ; ++i) {
10071 // Replace all chain users of the old load nodes with the chain of the new
10073 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode);
10074 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain());
10077 // Replace the first store with the new store.
10078 CombineTo(EarliestOp, NewStore);
10079 // Erase all other stores.
10080 for (unsigned i = 0; i < NumElem ; ++i) {
10081 // Remove all Store nodes.
10082 if (StoreNodes[i].MemNode == EarliestOp)
10084 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
10085 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
10086 deleteAndRecombine(St);
10092 SDValue DAGCombiner::visitSTORE(SDNode *N) {
10093 StoreSDNode *ST = cast<StoreSDNode>(N);
10094 SDValue Chain = ST->getChain();
10095 SDValue Value = ST->getValue();
10096 SDValue Ptr = ST->getBasePtr();
10098 // If this is a store of a bit convert, store the input value if the
10099 // resultant store does not need a higher alignment than the original.
10100 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
10101 ST->isUnindexed()) {
10102 unsigned OrigAlign = ST->getAlignment();
10103 EVT SVT = Value.getOperand(0).getValueType();
10104 unsigned Align = TLI.getDataLayout()->
10105 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
10106 if (Align <= OrigAlign &&
10107 ((!LegalOperations && !ST->isVolatile()) ||
10108 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
10109 return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0),
10110 Ptr, ST->getPointerInfo(), ST->isVolatile(),
10111 ST->isNonTemporal(), OrigAlign,
10115 // Turn 'store undef, Ptr' -> nothing.
10116 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
10119 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
10120 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
10121 // NOTE: If the original store is volatile, this transform must not increase
10122 // the number of stores. For example, on x86-32 an f64 can be stored in one
10123 // processor operation but an i64 (which is not legal) requires two. So the
10124 // transform should not be done in this case.
10125 if (Value.getOpcode() != ISD::TargetConstantFP) {
10127 switch (CFP->getSimpleValueType(0).SimpleTy) {
10128 default: llvm_unreachable("Unknown FP type");
10129 case MVT::f16: // We don't do this for these yet.
10135 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
10136 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
10137 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
10138 bitcastToAPInt().getZExtValue(), MVT::i32);
10139 return DAG.getStore(Chain, SDLoc(N), Tmp,
10140 Ptr, ST->getMemOperand());
10144 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
10145 !ST->isVolatile()) ||
10146 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
10147 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
10148 getZExtValue(), MVT::i64);
10149 return DAG.getStore(Chain, SDLoc(N), Tmp,
10150 Ptr, ST->getMemOperand());
10153 if (!ST->isVolatile() &&
10154 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
10155 // Many FP stores are not made apparent until after legalize, e.g. for
10156 // argument passing. Since this is so common, custom legalize the
10157 // 64-bit integer store into two 32-bit stores.
10158 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
10159 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
10160 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
10161 if (TLI.isBigEndian()) std::swap(Lo, Hi);
10163 unsigned Alignment = ST->getAlignment();
10164 bool isVolatile = ST->isVolatile();
10165 bool isNonTemporal = ST->isNonTemporal();
10166 AAMDNodes AAInfo = ST->getAAInfo();
10168 SDValue St0 = DAG.getStore(Chain, SDLoc(ST), Lo,
10169 Ptr, ST->getPointerInfo(),
10170 isVolatile, isNonTemporal,
10171 ST->getAlignment(), AAInfo);
10172 Ptr = DAG.getNode(ISD::ADD, SDLoc(N), Ptr.getValueType(), Ptr,
10173 DAG.getConstant(4, Ptr.getValueType()));
10174 Alignment = MinAlign(Alignment, 4U);
10175 SDValue St1 = DAG.getStore(Chain, SDLoc(ST), Hi,
10176 Ptr, ST->getPointerInfo().getWithOffset(4),
10177 isVolatile, isNonTemporal,
10178 Alignment, AAInfo);
10179 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other,
10188 // Try to infer better alignment information than the store already has.
10189 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
10190 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
10191 if (Align > ST->getAlignment())
10192 return DAG.getTruncStore(Chain, SDLoc(N), Value,
10193 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
10194 ST->isVolatile(), ST->isNonTemporal(), Align,
10199 // Try transforming a pair floating point load / store ops to integer
10200 // load / store ops.
10201 SDValue NewST = TransformFPLoadStorePair(N);
10202 if (NewST.getNode())
10205 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
10206 : DAG.getSubtarget().useAA();
10208 if (CombinerAAOnlyFunc.getNumOccurrences() &&
10209 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
10212 if (UseAA && ST->isUnindexed()) {
10213 // Walk up chain skipping non-aliasing memory nodes.
10214 SDValue BetterChain = FindBetterChain(N, Chain);
10216 // If there is a better chain.
10217 if (Chain != BetterChain) {
10220 // Replace the chain to avoid dependency.
10221 if (ST->isTruncatingStore()) {
10222 ReplStore = DAG.getTruncStore(BetterChain, SDLoc(N), Value, Ptr,
10223 ST->getMemoryVT(), ST->getMemOperand());
10225 ReplStore = DAG.getStore(BetterChain, SDLoc(N), Value, Ptr,
10226 ST->getMemOperand());
10229 // Create token to keep both nodes around.
10230 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
10231 MVT::Other, Chain, ReplStore);
10233 // Make sure the new and old chains are cleaned up.
10234 AddToWorklist(Token.getNode());
10236 // Don't add users to work list.
10237 return CombineTo(N, Token, false);
10241 // Try transforming N to an indexed store.
10242 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
10243 return SDValue(N, 0);
10245 // FIXME: is there such a thing as a truncating indexed store?
10246 if (ST->isTruncatingStore() && ST->isUnindexed() &&
10247 Value.getValueType().isInteger()) {
10248 // See if we can simplify the input to this truncstore with knowledge that
10249 // only the low bits are being used. For example:
10250 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
10252 GetDemandedBits(Value,
10253 APInt::getLowBitsSet(
10254 Value.getValueType().getScalarType().getSizeInBits(),
10255 ST->getMemoryVT().getScalarType().getSizeInBits()));
10256 AddToWorklist(Value.getNode());
10257 if (Shorter.getNode())
10258 return DAG.getTruncStore(Chain, SDLoc(N), Shorter,
10259 Ptr, ST->getMemoryVT(), ST->getMemOperand());
10261 // Otherwise, see if we can simplify the operation with
10262 // SimplifyDemandedBits, which only works if the value has a single use.
10263 if (SimplifyDemandedBits(Value,
10264 APInt::getLowBitsSet(
10265 Value.getValueType().getScalarType().getSizeInBits(),
10266 ST->getMemoryVT().getScalarType().getSizeInBits())))
10267 return SDValue(N, 0);
10270 // If this is a load followed by a store to the same location, then the store
10272 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
10273 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
10274 ST->isUnindexed() && !ST->isVolatile() &&
10275 // There can't be any side effects between the load and store, such as
10276 // a call or store.
10277 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
10278 // The store is dead, remove it.
10283 // If this is a store followed by a store with the same value to the same
10284 // location, then the store is dead/noop.
10285 if (StoreSDNode *ST1 = dyn_cast<StoreSDNode>(Chain)) {
10286 if (ST1->getBasePtr() == Ptr && ST->getMemoryVT() == ST1->getMemoryVT() &&
10287 ST1->getValue() == Value && ST->isUnindexed() && !ST->isVolatile() &&
10288 ST1->isUnindexed() && !ST1->isVolatile()) {
10289 // The store is dead, remove it.
10294 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
10295 // truncating store. We can do this even if this is already a truncstore.
10296 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
10297 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
10298 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
10299 ST->getMemoryVT())) {
10300 return DAG.getTruncStore(Chain, SDLoc(N), Value.getOperand(0),
10301 Ptr, ST->getMemoryVT(), ST->getMemOperand());
10304 // Only perform this optimization before the types are legal, because we
10305 // don't want to perform this optimization on every DAGCombine invocation.
10307 bool EverChanged = false;
10310 // There can be multiple store sequences on the same chain.
10311 // Keep trying to merge store sequences until we are unable to do so
10312 // or until we merge the last store on the chain.
10313 bool Changed = MergeConsecutiveStores(ST);
10314 EverChanged |= Changed;
10315 if (!Changed) break;
10316 } while (ST->getOpcode() != ISD::DELETED_NODE);
10319 return SDValue(N, 0);
10322 return ReduceLoadOpStoreWidth(N);
10325 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
10326 SDValue InVec = N->getOperand(0);
10327 SDValue InVal = N->getOperand(1);
10328 SDValue EltNo = N->getOperand(2);
10331 // If the inserted element is an UNDEF, just use the input vector.
10332 if (InVal.getOpcode() == ISD::UNDEF)
10335 EVT VT = InVec.getValueType();
10337 // If we can't generate a legal BUILD_VECTOR, exit
10338 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
10341 // Check that we know which element is being inserted
10342 if (!isa<ConstantSDNode>(EltNo))
10344 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
10346 // Canonicalize insert_vector_elt dag nodes.
10348 // (insert_vector_elt (insert_vector_elt A, Idx0), Idx1)
10349 // -> (insert_vector_elt (insert_vector_elt A, Idx1), Idx0)
10351 // Do this only if the child insert_vector node has one use; also
10352 // do this only if indices are both constants and Idx1 < Idx0.
10353 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse()
10354 && isa<ConstantSDNode>(InVec.getOperand(2))) {
10355 unsigned OtherElt =
10356 cast<ConstantSDNode>(InVec.getOperand(2))->getZExtValue();
10357 if (Elt < OtherElt) {
10359 SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VT,
10360 InVec.getOperand(0), InVal, EltNo);
10361 AddToWorklist(NewOp.getNode());
10362 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()),
10363 VT, NewOp, InVec.getOperand(1), InVec.getOperand(2));
10367 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
10368 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
10369 // vector elements.
10370 SmallVector<SDValue, 8> Ops;
10371 // Do not combine these two vectors if the output vector will not replace
10372 // the input vector.
10373 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) {
10374 Ops.append(InVec.getNode()->op_begin(),
10375 InVec.getNode()->op_end());
10376 } else if (InVec.getOpcode() == ISD::UNDEF) {
10377 unsigned NElts = VT.getVectorNumElements();
10378 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
10383 // Insert the element
10384 if (Elt < Ops.size()) {
10385 // All the operands of BUILD_VECTOR must have the same type;
10386 // we enforce that here.
10387 EVT OpVT = Ops[0].getValueType();
10388 if (InVal.getValueType() != OpVT)
10389 InVal = OpVT.bitsGT(InVal.getValueType()) ?
10390 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
10391 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
10395 // Return the new vector
10396 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
10399 SDValue DAGCombiner::ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
10400 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad) {
10401 EVT ResultVT = EVE->getValueType(0);
10402 EVT VecEltVT = InVecVT.getVectorElementType();
10403 unsigned Align = OriginalLoad->getAlignment();
10404 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
10405 VecEltVT.getTypeForEVT(*DAG.getContext()));
10407 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VecEltVT))
10412 SDValue NewPtr = OriginalLoad->getBasePtr();
10414 EVT PtrType = NewPtr.getValueType();
10415 MachinePointerInfo MPI;
10416 if (auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo)) {
10417 int Elt = ConstEltNo->getZExtValue();
10418 unsigned PtrOff = VecEltVT.getSizeInBits() * Elt / 8;
10419 if (TLI.isBigEndian())
10420 PtrOff = InVecVT.getSizeInBits() / 8 - PtrOff;
10421 Offset = DAG.getConstant(PtrOff, PtrType);
10422 MPI = OriginalLoad->getPointerInfo().getWithOffset(PtrOff);
10424 Offset = DAG.getNode(
10425 ISD::MUL, SDLoc(EVE), EltNo.getValueType(), EltNo,
10426 DAG.getConstant(VecEltVT.getStoreSize(), EltNo.getValueType()));
10427 if (TLI.isBigEndian())
10428 Offset = DAG.getNode(
10429 ISD::SUB, SDLoc(EVE), EltNo.getValueType(),
10430 DAG.getConstant(InVecVT.getStoreSize(), EltNo.getValueType()), Offset);
10431 MPI = OriginalLoad->getPointerInfo();
10433 NewPtr = DAG.getNode(ISD::ADD, SDLoc(EVE), PtrType, NewPtr, Offset);
10435 // The replacement we need to do here is a little tricky: we need to
10436 // replace an extractelement of a load with a load.
10437 // Use ReplaceAllUsesOfValuesWith to do the replacement.
10438 // Note that this replacement assumes that the extractvalue is the only
10439 // use of the load; that's okay because we don't want to perform this
10440 // transformation in other cases anyway.
10443 if (ResultVT.bitsGT(VecEltVT)) {
10444 // If the result type of vextract is wider than the load, then issue an
10445 // extending load instead.
10446 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, VecEltVT)
10449 Load = DAG.getExtLoad(
10450 ExtType, SDLoc(EVE), ResultVT, OriginalLoad->getChain(), NewPtr, MPI,
10451 VecEltVT, OriginalLoad->isVolatile(), OriginalLoad->isNonTemporal(),
10452 OriginalLoad->isInvariant(), Align, OriginalLoad->getAAInfo());
10453 Chain = Load.getValue(1);
10455 Load = DAG.getLoad(
10456 VecEltVT, SDLoc(EVE), OriginalLoad->getChain(), NewPtr, MPI,
10457 OriginalLoad->isVolatile(), OriginalLoad->isNonTemporal(),
10458 OriginalLoad->isInvariant(), Align, OriginalLoad->getAAInfo());
10459 Chain = Load.getValue(1);
10460 if (ResultVT.bitsLT(VecEltVT))
10461 Load = DAG.getNode(ISD::TRUNCATE, SDLoc(EVE), ResultVT, Load);
10463 Load = DAG.getNode(ISD::BITCAST, SDLoc(EVE), ResultVT, Load);
10465 WorklistRemover DeadNodes(*this);
10466 SDValue From[] = { SDValue(EVE, 0), SDValue(OriginalLoad, 1) };
10467 SDValue To[] = { Load, Chain };
10468 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
10469 // Since we're explicitly calling ReplaceAllUses, add the new node to the
10470 // worklist explicitly as well.
10471 AddToWorklist(Load.getNode());
10472 AddUsersToWorklist(Load.getNode()); // Add users too
10473 // Make sure to revisit this node to clean it up; it will usually be dead.
10474 AddToWorklist(EVE);
10476 return SDValue(EVE, 0);
10479 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
10480 // (vextract (scalar_to_vector val, 0) -> val
10481 SDValue InVec = N->getOperand(0);
10482 EVT VT = InVec.getValueType();
10483 EVT NVT = N->getValueType(0);
10485 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
10486 // Check if the result type doesn't match the inserted element type. A
10487 // SCALAR_TO_VECTOR may truncate the inserted element and the
10488 // EXTRACT_VECTOR_ELT may widen the extracted vector.
10489 SDValue InOp = InVec.getOperand(0);
10490 if (InOp.getValueType() != NVT) {
10491 assert(InOp.getValueType().isInteger() && NVT.isInteger());
10492 return DAG.getSExtOrTrunc(InOp, SDLoc(InVec), NVT);
10497 SDValue EltNo = N->getOperand(1);
10498 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
10500 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
10501 // We only perform this optimization before the op legalization phase because
10502 // we may introduce new vector instructions which are not backed by TD
10503 // patterns. For example on AVX, extracting elements from a wide vector
10504 // without using extract_subvector. However, if we can find an underlying
10505 // scalar value, then we can always use that.
10506 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
10508 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
10509 int NumElem = VT.getVectorNumElements();
10510 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
10511 // Find the new index to extract from.
10512 int OrigElt = SVOp->getMaskElt(Elt);
10514 // Extracting an undef index is undef.
10516 return DAG.getUNDEF(NVT);
10518 // Select the right vector half to extract from.
10520 if (OrigElt < NumElem) {
10521 SVInVec = InVec->getOperand(0);
10523 SVInVec = InVec->getOperand(1);
10524 OrigElt -= NumElem;
10527 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) {
10528 SDValue InOp = SVInVec.getOperand(OrigElt);
10529 if (InOp.getValueType() != NVT) {
10530 assert(InOp.getValueType().isInteger() && NVT.isInteger());
10531 InOp = DAG.getSExtOrTrunc(InOp, SDLoc(SVInVec), NVT);
10537 // FIXME: We should handle recursing on other vector shuffles and
10538 // scalar_to_vector here as well.
10540 if (!LegalOperations) {
10541 EVT IndexTy = TLI.getVectorIdxTy();
10542 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), NVT,
10543 SVInVec, DAG.getConstant(OrigElt, IndexTy));
10547 bool BCNumEltsChanged = false;
10548 EVT ExtVT = VT.getVectorElementType();
10551 // If the result of load has to be truncated, then it's not necessarily
10553 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
10556 if (InVec.getOpcode() == ISD::BITCAST) {
10557 // Don't duplicate a load with other uses.
10558 if (!InVec.hasOneUse())
10561 EVT BCVT = InVec.getOperand(0).getValueType();
10562 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
10564 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
10565 BCNumEltsChanged = true;
10566 InVec = InVec.getOperand(0);
10567 ExtVT = BCVT.getVectorElementType();
10570 // (vextract (vN[if]M load $addr), i) -> ([if]M load $addr + i * size)
10571 if (!LegalOperations && !ConstEltNo && InVec.hasOneUse() &&
10572 ISD::isNormalLoad(InVec.getNode()) &&
10573 !N->getOperand(1)->hasPredecessor(InVec.getNode())) {
10574 SDValue Index = N->getOperand(1);
10575 if (LoadSDNode *OrigLoad = dyn_cast<LoadSDNode>(InVec))
10576 return ReplaceExtractVectorEltOfLoadWithNarrowedLoad(N, VT, Index,
10580 // Perform only after legalization to ensure build_vector / vector_shuffle
10581 // optimizations have already been done.
10582 if (!LegalOperations) return SDValue();
10584 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
10585 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
10586 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
10589 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
10591 LoadSDNode *LN0 = nullptr;
10592 const ShuffleVectorSDNode *SVN = nullptr;
10593 if (ISD::isNormalLoad(InVec.getNode())) {
10594 LN0 = cast<LoadSDNode>(InVec);
10595 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10596 InVec.getOperand(0).getValueType() == ExtVT &&
10597 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
10598 // Don't duplicate a load with other uses.
10599 if (!InVec.hasOneUse())
10602 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
10603 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
10604 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
10606 // (load $addr+1*size)
10608 // Don't duplicate a load with other uses.
10609 if (!InVec.hasOneUse())
10612 // If the bit convert changed the number of elements, it is unsafe
10613 // to examine the mask.
10614 if (BCNumEltsChanged)
10617 // Select the input vector, guarding against out of range extract vector.
10618 unsigned NumElems = VT.getVectorNumElements();
10619 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
10620 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
10622 if (InVec.getOpcode() == ISD::BITCAST) {
10623 // Don't duplicate a load with other uses.
10624 if (!InVec.hasOneUse())
10627 InVec = InVec.getOperand(0);
10629 if (ISD::isNormalLoad(InVec.getNode())) {
10630 LN0 = cast<LoadSDNode>(InVec);
10631 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
10632 EltNo = DAG.getConstant(Elt, EltNo.getValueType());
10636 // Make sure we found a non-volatile load and the extractelement is
10638 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
10641 // If Idx was -1 above, Elt is going to be -1, so just return undef.
10643 return DAG.getUNDEF(LVT);
10645 return ReplaceExtractVectorEltOfLoadWithNarrowedLoad(N, VT, EltNo, LN0);
10651 // Simplify (build_vec (ext )) to (bitcast (build_vec ))
10652 SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) {
10653 // We perform this optimization post type-legalization because
10654 // the type-legalizer often scalarizes integer-promoted vectors.
10655 // Performing this optimization before may create bit-casts which
10656 // will be type-legalized to complex code sequences.
10657 // We perform this optimization only before the operation legalizer because we
10658 // may introduce illegal operations.
10659 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes)
10662 unsigned NumInScalars = N->getNumOperands();
10664 EVT VT = N->getValueType(0);
10666 // Check to see if this is a BUILD_VECTOR of a bunch of values
10667 // which come from any_extend or zero_extend nodes. If so, we can create
10668 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
10669 // optimizations. We do not handle sign-extend because we can't fill the sign
10671 EVT SourceType = MVT::Other;
10672 bool AllAnyExt = true;
10674 for (unsigned i = 0; i != NumInScalars; ++i) {
10675 SDValue In = N->getOperand(i);
10676 // Ignore undef inputs.
10677 if (In.getOpcode() == ISD::UNDEF) continue;
10679 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
10680 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
10682 // Abort if the element is not an extension.
10683 if (!ZeroExt && !AnyExt) {
10684 SourceType = MVT::Other;
10688 // The input is a ZeroExt or AnyExt. Check the original type.
10689 EVT InTy = In.getOperand(0).getValueType();
10691 // Check that all of the widened source types are the same.
10692 if (SourceType == MVT::Other)
10695 else if (InTy != SourceType) {
10696 // Multiple income types. Abort.
10697 SourceType = MVT::Other;
10701 // Check if all of the extends are ANY_EXTENDs.
10702 AllAnyExt &= AnyExt;
10705 // In order to have valid types, all of the inputs must be extended from the
10706 // same source type and all of the inputs must be any or zero extend.
10707 // Scalar sizes must be a power of two.
10708 EVT OutScalarTy = VT.getScalarType();
10709 bool ValidTypes = SourceType != MVT::Other &&
10710 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
10711 isPowerOf2_32(SourceType.getSizeInBits());
10713 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
10714 // turn into a single shuffle instruction.
10718 bool isLE = TLI.isLittleEndian();
10719 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
10720 assert(ElemRatio > 1 && "Invalid element size ratio");
10721 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
10722 DAG.getConstant(0, SourceType);
10724 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements();
10725 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
10727 // Populate the new build_vector
10728 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
10729 SDValue Cast = N->getOperand(i);
10730 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
10731 Cast.getOpcode() == ISD::ZERO_EXTEND ||
10732 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
10734 if (Cast.getOpcode() == ISD::UNDEF)
10735 In = DAG.getUNDEF(SourceType);
10737 In = Cast->getOperand(0);
10738 unsigned Index = isLE ? (i * ElemRatio) :
10739 (i * ElemRatio + (ElemRatio - 1));
10741 assert(Index < Ops.size() && "Invalid index");
10745 // The type of the new BUILD_VECTOR node.
10746 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
10747 assert(VecVT.getSizeInBits() == VT.getSizeInBits() &&
10748 "Invalid vector size");
10749 // Check if the new vector type is legal.
10750 if (!isTypeLegal(VecVT)) return SDValue();
10752 // Make the new BUILD_VECTOR.
10753 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
10755 // The new BUILD_VECTOR node has the potential to be further optimized.
10756 AddToWorklist(BV.getNode());
10757 // Bitcast to the desired type.
10758 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
10761 SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
10762 EVT VT = N->getValueType(0);
10764 unsigned NumInScalars = N->getNumOperands();
10767 EVT SrcVT = MVT::Other;
10768 unsigned Opcode = ISD::DELETED_NODE;
10769 unsigned NumDefs = 0;
10771 for (unsigned i = 0; i != NumInScalars; ++i) {
10772 SDValue In = N->getOperand(i);
10773 unsigned Opc = In.getOpcode();
10775 if (Opc == ISD::UNDEF)
10778 // If all scalar values are floats and converted from integers.
10779 if (Opcode == ISD::DELETED_NODE &&
10780 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
10787 EVT InVT = In.getOperand(0).getValueType();
10789 // If all scalar values are typed differently, bail out. It's chosen to
10790 // simplify BUILD_VECTOR of integer types.
10791 if (SrcVT == MVT::Other)
10798 // If the vector has just one element defined, it's not worth to fold it into
10799 // a vectorized one.
10803 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP)
10804 && "Should only handle conversion from integer to float.");
10805 assert(SrcVT != MVT::Other && "Cannot determine source type!");
10807 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
10809 if (!TLI.isOperationLegalOrCustom(Opcode, NVT))
10812 SmallVector<SDValue, 8> Opnds;
10813 for (unsigned i = 0; i != NumInScalars; ++i) {
10814 SDValue In = N->getOperand(i);
10816 if (In.getOpcode() == ISD::UNDEF)
10817 Opnds.push_back(DAG.getUNDEF(SrcVT));
10819 Opnds.push_back(In.getOperand(0));
10821 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Opnds);
10822 AddToWorklist(BV.getNode());
10824 return DAG.getNode(Opcode, dl, VT, BV);
10827 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
10828 unsigned NumInScalars = N->getNumOperands();
10830 EVT VT = N->getValueType(0);
10832 // A vector built entirely of undefs is undef.
10833 if (ISD::allOperandsUndef(N))
10834 return DAG.getUNDEF(VT);
10836 SDValue V = reduceBuildVecExtToExtBuildVec(N);
10840 V = reduceBuildVecConvertToConvertBuildVec(N);
10844 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
10845 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
10846 // at most two distinct vectors, turn this into a shuffle node.
10848 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
10849 if (!isTypeLegal(VT))
10852 // May only combine to shuffle after legalize if shuffle is legal.
10853 if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VT))
10856 SDValue VecIn1, VecIn2;
10857 bool UsesZeroVector = false;
10858 for (unsigned i = 0; i != NumInScalars; ++i) {
10859 SDValue Op = N->getOperand(i);
10860 // Ignore undef inputs.
10861 if (Op.getOpcode() == ISD::UNDEF) continue;
10863 // See if we can combine this build_vector into a blend with a zero vector.
10864 if (!VecIn2.getNode() && ((Op.getOpcode() == ISD::Constant &&
10865 cast<ConstantSDNode>(Op.getNode())->isNullValue()) ||
10866 (Op.getOpcode() == ISD::ConstantFP &&
10867 cast<ConstantFPSDNode>(Op.getNode())->getValueAPF().isZero()))) {
10868 UsesZeroVector = true;
10872 // If this input is something other than a EXTRACT_VECTOR_ELT with a
10873 // constant index, bail out.
10874 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
10875 !isa<ConstantSDNode>(Op.getOperand(1))) {
10876 VecIn1 = VecIn2 = SDValue(nullptr, 0);
10880 // We allow up to two distinct input vectors.
10881 SDValue ExtractedFromVec = Op.getOperand(0);
10882 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
10885 if (!VecIn1.getNode()) {
10886 VecIn1 = ExtractedFromVec;
10887 } else if (!VecIn2.getNode() && !UsesZeroVector) {
10888 VecIn2 = ExtractedFromVec;
10890 // Too many inputs.
10891 VecIn1 = VecIn2 = SDValue(nullptr, 0);
10896 // If everything is good, we can make a shuffle operation.
10897 if (VecIn1.getNode()) {
10898 unsigned InNumElements = VecIn1.getValueType().getVectorNumElements();
10899 SmallVector<int, 8> Mask;
10900 for (unsigned i = 0; i != NumInScalars; ++i) {
10901 unsigned Opcode = N->getOperand(i).getOpcode();
10902 if (Opcode == ISD::UNDEF) {
10903 Mask.push_back(-1);
10907 // Operands can also be zero.
10908 if (Opcode != ISD::EXTRACT_VECTOR_ELT) {
10909 assert(UsesZeroVector &&
10910 (Opcode == ISD::Constant || Opcode == ISD::ConstantFP) &&
10911 "Unexpected node found!");
10912 Mask.push_back(NumInScalars+i);
10916 // If extracting from the first vector, just use the index directly.
10917 SDValue Extract = N->getOperand(i);
10918 SDValue ExtVal = Extract.getOperand(1);
10919 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
10920 if (Extract.getOperand(0) == VecIn1) {
10921 Mask.push_back(ExtIndex);
10925 // Otherwise, use InIdx + InputVecSize
10926 Mask.push_back(InNumElements + ExtIndex);
10929 // Avoid introducing illegal shuffles with zero.
10930 if (UsesZeroVector && !TLI.isVectorClearMaskLegal(Mask, VT))
10933 // We can't generate a shuffle node with mismatched input and output types.
10934 // Attempt to transform a single input vector to the correct type.
10935 if ((VT != VecIn1.getValueType())) {
10936 // If the input vector type has a different base type to the output
10937 // vector type, bail out.
10938 EVT VTElemType = VT.getVectorElementType();
10939 if ((VecIn1.getValueType().getVectorElementType() != VTElemType) ||
10940 (VecIn2.getNode() &&
10941 (VecIn2.getValueType().getVectorElementType() != VTElemType)))
10944 // If the input vector is too small, widen it.
10945 // We only support widening of vectors which are half the size of the
10946 // output registers. For example XMM->YMM widening on X86 with AVX.
10947 EVT VecInT = VecIn1.getValueType();
10948 if (VecInT.getSizeInBits() * 2 == VT.getSizeInBits()) {
10949 // If we only have one small input, widen it by adding undef values.
10950 if (!VecIn2.getNode())
10951 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, VecIn1,
10952 DAG.getUNDEF(VecIn1.getValueType()));
10953 else if (VecIn1.getValueType() == VecIn2.getValueType()) {
10954 // If we have two small inputs of the same type, try to concat them.
10955 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, VecIn1, VecIn2);
10956 VecIn2 = SDValue(nullptr, 0);
10959 } else if (VecInT.getSizeInBits() == VT.getSizeInBits() * 2) {
10960 // If the input vector is too large, try to split it.
10961 // We don't support having two input vectors that are too large.
10962 if (VecIn2.getNode())
10965 if (!TLI.isExtractSubvectorCheap(VT, VT.getVectorNumElements()))
10968 // Try to replace VecIn1 with two extract_subvectors
10969 // No need to update the masks, they should still be correct.
10970 VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1,
10971 DAG.getConstant(VT.getVectorNumElements(), TLI.getVectorIdxTy()));
10972 VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1,
10973 DAG.getConstant(0, TLI.getVectorIdxTy()));
10974 UsesZeroVector = false;
10979 if (UsesZeroVector)
10980 VecIn2 = VT.isInteger() ? DAG.getConstant(0, VT) :
10981 DAG.getConstantFP(0.0, VT);
10983 // If VecIn2 is unused then change it to undef.
10984 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
10986 // Check that we were able to transform all incoming values to the same
10988 if (VecIn2.getValueType() != VecIn1.getValueType() ||
10989 VecIn1.getValueType() != VT)
10992 // Return the new VECTOR_SHUFFLE node.
10996 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]);
11002 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
11003 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
11004 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
11005 // inputs come from at most two distinct vectors, turn this into a shuffle
11008 // If we only have one input vector, we don't need to do any concatenation.
11009 if (N->getNumOperands() == 1)
11010 return N->getOperand(0);
11012 // Check if all of the operands are undefs.
11013 EVT VT = N->getValueType(0);
11014 if (ISD::allOperandsUndef(N))
11015 return DAG.getUNDEF(VT);
11017 // Optimize concat_vectors where one of the vectors is undef.
11018 if (N->getNumOperands() == 2 &&
11019 N->getOperand(1)->getOpcode() == ISD::UNDEF) {
11020 SDValue In = N->getOperand(0);
11021 assert(In.getValueType().isVector() && "Must concat vectors");
11023 // Transform: concat_vectors(scalar, undef) -> scalar_to_vector(sclr).
11024 if (In->getOpcode() == ISD::BITCAST &&
11025 !In->getOperand(0)->getValueType(0).isVector()) {
11026 SDValue Scalar = In->getOperand(0);
11027 EVT SclTy = Scalar->getValueType(0);
11029 if (!SclTy.isFloatingPoint() && !SclTy.isInteger())
11032 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SclTy,
11033 VT.getSizeInBits() / SclTy.getSizeInBits());
11034 if (!TLI.isTypeLegal(NVT) || !TLI.isTypeLegal(Scalar.getValueType()))
11037 SDLoc dl = SDLoc(N);
11038 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NVT, Scalar);
11039 return DAG.getNode(ISD::BITCAST, dl, VT, Res);
11043 // fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
11044 // -> (BUILD_VECTOR A, B, ..., C, D, ...)
11045 if (N->getNumOperands() == 2 &&
11046 N->getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
11047 N->getOperand(1).getOpcode() == ISD::BUILD_VECTOR) {
11048 EVT VT = N->getValueType(0);
11049 SDValue N0 = N->getOperand(0);
11050 SDValue N1 = N->getOperand(1);
11051 SmallVector<SDValue, 8> Opnds;
11052 unsigned BuildVecNumElts = N0.getNumOperands();
11054 EVT SclTy0 = N0.getOperand(0)->getValueType(0);
11055 EVT SclTy1 = N1.getOperand(0)->getValueType(0);
11056 if (SclTy0.isFloatingPoint()) {
11057 for (unsigned i = 0; i != BuildVecNumElts; ++i)
11058 Opnds.push_back(N0.getOperand(i));
11059 for (unsigned i = 0; i != BuildVecNumElts; ++i)
11060 Opnds.push_back(N1.getOperand(i));
11062 // If BUILD_VECTOR are from built from integer, they may have different
11063 // operand types. Get the smaller type and truncate all operands to it.
11064 EVT MinTy = SclTy0.bitsLE(SclTy1) ? SclTy0 : SclTy1;
11065 for (unsigned i = 0; i != BuildVecNumElts; ++i)
11066 Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
11067 N0.getOperand(i)));
11068 for (unsigned i = 0; i != BuildVecNumElts; ++i)
11069 Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
11070 N1.getOperand(i)));
11073 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
11076 // Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR
11077 // nodes often generate nop CONCAT_VECTOR nodes.
11078 // Scan the CONCAT_VECTOR operands and look for a CONCAT operations that
11079 // place the incoming vectors at the exact same location.
11080 SDValue SingleSource = SDValue();
11081 unsigned PartNumElem = N->getOperand(0).getValueType().getVectorNumElements();
11083 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
11084 SDValue Op = N->getOperand(i);
11086 if (Op.getOpcode() == ISD::UNDEF)
11089 // Check if this is the identity extract:
11090 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
11093 // Find the single incoming vector for the extract_subvector.
11094 if (SingleSource.getNode()) {
11095 if (Op.getOperand(0) != SingleSource)
11098 SingleSource = Op.getOperand(0);
11100 // Check the source type is the same as the type of the result.
11101 // If not, this concat may extend the vector, so we can not
11102 // optimize it away.
11103 if (SingleSource.getValueType() != N->getValueType(0))
11107 unsigned IdentityIndex = i * PartNumElem;
11108 ConstantSDNode *CS = dyn_cast<ConstantSDNode>(Op.getOperand(1));
11109 // The extract index must be constant.
11113 // Check that we are reading from the identity index.
11114 if (CS->getZExtValue() != IdentityIndex)
11118 if (SingleSource.getNode())
11119 return SingleSource;
11124 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
11125 EVT NVT = N->getValueType(0);
11126 SDValue V = N->getOperand(0);
11128 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
11130 // (extract_subvec (concat V1, V2, ...), i)
11133 // Only operand 0 is checked as 'concat' assumes all inputs of the same
11135 if (V->getOperand(0).getValueType() != NVT)
11137 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
11138 unsigned NumElems = NVT.getVectorNumElements();
11139 assert((Idx % NumElems) == 0 &&
11140 "IDX in concat is not a multiple of the result vector length.");
11141 return V->getOperand(Idx / NumElems);
11145 if (V->getOpcode() == ISD::BITCAST)
11146 V = V.getOperand(0);
11148 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
11150 // Handle only simple case where vector being inserted and vector
11151 // being extracted are of same type, and are half size of larger vectors.
11152 EVT BigVT = V->getOperand(0).getValueType();
11153 EVT SmallVT = V->getOperand(1).getValueType();
11154 if (!NVT.bitsEq(SmallVT) || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
11157 // Only handle cases where both indexes are constants with the same type.
11158 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
11159 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
11161 if (InsIdx && ExtIdx &&
11162 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
11163 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
11165 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
11167 // indices are equal or bit offsets are equal => V1
11168 // otherwise => (extract_subvec V1, ExtIdx)
11169 if (InsIdx->getZExtValue() * SmallVT.getScalarType().getSizeInBits() ==
11170 ExtIdx->getZExtValue() * NVT.getScalarType().getSizeInBits())
11171 return DAG.getNode(ISD::BITCAST, dl, NVT, V->getOperand(1));
11172 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT,
11173 DAG.getNode(ISD::BITCAST, dl,
11174 N->getOperand(0).getValueType(),
11175 V->getOperand(0)), N->getOperand(1));
11182 static SDValue simplifyShuffleOperandRecursively(SmallBitVector &UsedElements,
11183 SDValue V, SelectionDAG &DAG) {
11185 EVT VT = V.getValueType();
11187 switch (V.getOpcode()) {
11191 case ISD::CONCAT_VECTORS: {
11192 EVT OpVT = V->getOperand(0).getValueType();
11193 int OpSize = OpVT.getVectorNumElements();
11194 SmallBitVector OpUsedElements(OpSize, false);
11195 bool FoundSimplification = false;
11196 SmallVector<SDValue, 4> NewOps;
11197 NewOps.reserve(V->getNumOperands());
11198 for (int i = 0, NumOps = V->getNumOperands(); i < NumOps; ++i) {
11199 SDValue Op = V->getOperand(i);
11200 bool OpUsed = false;
11201 for (int j = 0; j < OpSize; ++j)
11202 if (UsedElements[i * OpSize + j]) {
11203 OpUsedElements[j] = true;
11207 OpUsed ? simplifyShuffleOperandRecursively(OpUsedElements, Op, DAG)
11208 : DAG.getUNDEF(OpVT));
11209 FoundSimplification |= Op == NewOps.back();
11210 OpUsedElements.reset();
11212 if (FoundSimplification)
11213 V = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, NewOps);
11217 case ISD::INSERT_SUBVECTOR: {
11218 SDValue BaseV = V->getOperand(0);
11219 SDValue SubV = V->getOperand(1);
11220 auto *IdxN = dyn_cast<ConstantSDNode>(V->getOperand(2));
11224 int SubSize = SubV.getValueType().getVectorNumElements();
11225 int Idx = IdxN->getZExtValue();
11226 bool SubVectorUsed = false;
11227 SmallBitVector SubUsedElements(SubSize, false);
11228 for (int i = 0; i < SubSize; ++i)
11229 if (UsedElements[i + Idx]) {
11230 SubVectorUsed = true;
11231 SubUsedElements[i] = true;
11232 UsedElements[i + Idx] = false;
11235 // Now recurse on both the base and sub vectors.
11236 SDValue SimplifiedSubV =
11238 ? simplifyShuffleOperandRecursively(SubUsedElements, SubV, DAG)
11239 : DAG.getUNDEF(SubV.getValueType());
11240 SDValue SimplifiedBaseV = simplifyShuffleOperandRecursively(UsedElements, BaseV, DAG);
11241 if (SimplifiedSubV != SubV || SimplifiedBaseV != BaseV)
11242 V = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
11243 SimplifiedBaseV, SimplifiedSubV, V->getOperand(2));
11249 static SDValue simplifyShuffleOperands(ShuffleVectorSDNode *SVN, SDValue N0,
11250 SDValue N1, SelectionDAG &DAG) {
11251 EVT VT = SVN->getValueType(0);
11252 int NumElts = VT.getVectorNumElements();
11253 SmallBitVector N0UsedElements(NumElts, false), N1UsedElements(NumElts, false);
11254 for (int M : SVN->getMask())
11255 if (M >= 0 && M < NumElts)
11256 N0UsedElements[M] = true;
11257 else if (M >= NumElts)
11258 N1UsedElements[M - NumElts] = true;
11260 SDValue S0 = simplifyShuffleOperandRecursively(N0UsedElements, N0, DAG);
11261 SDValue S1 = simplifyShuffleOperandRecursively(N1UsedElements, N1, DAG);
11262 if (S0 == N0 && S1 == N1)
11265 return DAG.getVectorShuffle(VT, SDLoc(SVN), S0, S1, SVN->getMask());
11268 // Tries to turn a shuffle of two CONCAT_VECTORS into a single concat.
11269 static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) {
11270 EVT VT = N->getValueType(0);
11271 unsigned NumElts = VT.getVectorNumElements();
11273 SDValue N0 = N->getOperand(0);
11274 SDValue N1 = N->getOperand(1);
11275 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
11277 SmallVector<SDValue, 4> Ops;
11278 EVT ConcatVT = N0.getOperand(0).getValueType();
11279 unsigned NumElemsPerConcat = ConcatVT.getVectorNumElements();
11280 unsigned NumConcats = NumElts / NumElemsPerConcat;
11282 // Look at every vector that's inserted. We're looking for exact
11283 // subvector-sized copies from a concatenated vector
11284 for (unsigned I = 0; I != NumConcats; ++I) {
11285 // Make sure we're dealing with a copy.
11286 unsigned Begin = I * NumElemsPerConcat;
11287 bool AllUndef = true, NoUndef = true;
11288 for (unsigned J = Begin; J != Begin + NumElemsPerConcat; ++J) {
11289 if (SVN->getMaskElt(J) >= 0)
11296 if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0)
11299 for (unsigned J = 1; J != NumElemsPerConcat; ++J)
11300 if (SVN->getMaskElt(Begin + J - 1) + 1 != SVN->getMaskElt(Begin + J))
11303 unsigned FirstElt = SVN->getMaskElt(Begin) / NumElemsPerConcat;
11304 if (FirstElt < N0.getNumOperands())
11305 Ops.push_back(N0.getOperand(FirstElt));
11307 Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands()));
11309 } else if (AllUndef) {
11310 Ops.push_back(DAG.getUNDEF(N0.getOperand(0).getValueType()));
11311 } else { // Mixed with general masks and undefs, can't do optimization.
11316 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
11319 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
11320 EVT VT = N->getValueType(0);
11321 unsigned NumElts = VT.getVectorNumElements();
11323 SDValue N0 = N->getOperand(0);
11324 SDValue N1 = N->getOperand(1);
11326 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
11328 // Canonicalize shuffle undef, undef -> undef
11329 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
11330 return DAG.getUNDEF(VT);
11332 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
11334 // Canonicalize shuffle v, v -> v, undef
11336 SmallVector<int, 8> NewMask;
11337 for (unsigned i = 0; i != NumElts; ++i) {
11338 int Idx = SVN->getMaskElt(i);
11339 if (Idx >= (int)NumElts) Idx -= NumElts;
11340 NewMask.push_back(Idx);
11342 return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT),
11346 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
11347 if (N0.getOpcode() == ISD::UNDEF) {
11348 SmallVector<int, 8> NewMask;
11349 for (unsigned i = 0; i != NumElts; ++i) {
11350 int Idx = SVN->getMaskElt(i);
11352 if (Idx >= (int)NumElts)
11355 Idx = -1; // remove reference to lhs
11357 NewMask.push_back(Idx);
11359 return DAG.getVectorShuffle(VT, SDLoc(N), N1, DAG.getUNDEF(VT),
11363 // Remove references to rhs if it is undef
11364 if (N1.getOpcode() == ISD::UNDEF) {
11365 bool Changed = false;
11366 SmallVector<int, 8> NewMask;
11367 for (unsigned i = 0; i != NumElts; ++i) {
11368 int Idx = SVN->getMaskElt(i);
11369 if (Idx >= (int)NumElts) {
11373 NewMask.push_back(Idx);
11376 return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, &NewMask[0]);
11379 // If it is a splat, check if the argument vector is another splat or a
11380 // build_vector with all scalar elements the same.
11381 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
11382 SDNode *V = N0.getNode();
11384 // If this is a bit convert that changes the element type of the vector but
11385 // not the number of vector elements, look through it. Be careful not to
11386 // look though conversions that change things like v4f32 to v2f64.
11387 if (V->getOpcode() == ISD::BITCAST) {
11388 SDValue ConvInput = V->getOperand(0);
11389 if (ConvInput.getValueType().isVector() &&
11390 ConvInput.getValueType().getVectorNumElements() == NumElts)
11391 V = ConvInput.getNode();
11394 if (V->getOpcode() == ISD::BUILD_VECTOR) {
11395 assert(V->getNumOperands() == NumElts &&
11396 "BUILD_VECTOR has wrong number of operands");
11398 bool AllSame = true;
11399 for (unsigned i = 0; i != NumElts; ++i) {
11400 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
11401 Base = V->getOperand(i);
11405 // Splat of <u, u, u, u>, return <u, u, u, u>
11406 if (!Base.getNode())
11408 for (unsigned i = 0; i != NumElts; ++i) {
11409 if (V->getOperand(i) != Base) {
11414 // Splat of <x, x, x, x>, return <x, x, x, x>
11420 // There are various patterns used to build up a vector from smaller vectors,
11421 // subvectors, or elements. Scan chains of these and replace unused insertions
11422 // or components with undef.
11423 if (SDValue S = simplifyShuffleOperands(SVN, N0, N1, DAG))
11426 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
11427 Level < AfterLegalizeVectorOps &&
11428 (N1.getOpcode() == ISD::UNDEF ||
11429 (N1.getOpcode() == ISD::CONCAT_VECTORS &&
11430 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) {
11431 SDValue V = partitionShuffleOfConcats(N, DAG);
11437 // Canonicalize shuffles according to rules:
11438 // shuffle(A, shuffle(A, B)) -> shuffle(shuffle(A,B), A)
11439 // shuffle(B, shuffle(A, B)) -> shuffle(shuffle(A,B), B)
11440 // shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
11441 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
11442 N0.getOpcode() != ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
11443 TLI.isTypeLegal(VT)) {
11444 // The incoming shuffle must be of the same type as the result of the
11445 // current shuffle.
11446 assert(N1->getOperand(0).getValueType() == VT &&
11447 "Shuffle types don't match");
11449 SDValue SV0 = N1->getOperand(0);
11450 SDValue SV1 = N1->getOperand(1);
11451 bool HasSameOp0 = N0 == SV0;
11452 bool IsSV1Undef = SV1.getOpcode() == ISD::UNDEF;
11453 if (HasSameOp0 || IsSV1Undef || N0 == SV1)
11454 // Commute the operands of this shuffle so that next rule
11456 return DAG.getCommutedVectorShuffle(*SVN);
11459 // Try to fold according to rules:
11460 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, B, M2)
11461 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, C, M2)
11462 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, C, M2)
11463 // Don't try to fold shuffles with illegal type.
11464 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
11465 TLI.isTypeLegal(VT)) {
11466 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
11468 // The incoming shuffle must be of the same type as the result of the
11469 // current shuffle.
11470 assert(OtherSV->getOperand(0).getValueType() == VT &&
11471 "Shuffle types don't match");
11474 SmallVector<int, 4> Mask;
11475 // Compute the combined shuffle mask for a shuffle with SV0 as the first
11476 // operand, and SV1 as the second operand.
11477 for (unsigned i = 0; i != NumElts; ++i) {
11478 int Idx = SVN->getMaskElt(i);
11480 // Propagate Undef.
11481 Mask.push_back(Idx);
11485 SDValue CurrentVec;
11486 if (Idx < (int)NumElts) {
11487 // This shuffle index refers to the inner shuffle N0. Lookup the inner
11488 // shuffle mask to identify which vector is actually referenced.
11489 Idx = OtherSV->getMaskElt(Idx);
11491 // Propagate Undef.
11492 Mask.push_back(Idx);
11496 CurrentVec = (Idx < (int) NumElts) ? OtherSV->getOperand(0)
11497 : OtherSV->getOperand(1);
11499 // This shuffle index references an element within N1.
11503 // Simple case where 'CurrentVec' is UNDEF.
11504 if (CurrentVec.getOpcode() == ISD::UNDEF) {
11505 Mask.push_back(-1);
11509 // Canonicalize the shuffle index. We don't know yet if CurrentVec
11510 // will be the first or second operand of the combined shuffle.
11511 Idx = Idx % NumElts;
11512 if (!SV0.getNode() || SV0 == CurrentVec) {
11513 // Ok. CurrentVec is the left hand side.
11514 // Update the mask accordingly.
11516 Mask.push_back(Idx);
11520 // Bail out if we cannot convert the shuffle pair into a single shuffle.
11521 if (SV1.getNode() && SV1 != CurrentVec)
11524 // Ok. CurrentVec is the right hand side.
11525 // Update the mask accordingly.
11527 Mask.push_back(Idx + NumElts);
11530 // Check if all indices in Mask are Undef. In case, propagate Undef.
11531 bool isUndefMask = true;
11532 for (unsigned i = 0; i != NumElts && isUndefMask; ++i)
11533 isUndefMask &= Mask[i] < 0;
11536 return DAG.getUNDEF(VT);
11538 if (!SV0.getNode())
11539 SV0 = DAG.getUNDEF(VT);
11540 if (!SV1.getNode())
11541 SV1 = DAG.getUNDEF(VT);
11543 // Avoid introducing shuffles with illegal mask.
11544 if (!TLI.isShuffleMaskLegal(Mask, VT)) {
11545 // Compute the commuted shuffle mask and test again.
11546 for (unsigned i = 0; i != NumElts; ++i) {
11550 else if (idx < (int)NumElts)
11551 Mask[i] = idx + NumElts;
11553 Mask[i] = idx - NumElts;
11556 if (!TLI.isShuffleMaskLegal(Mask, VT))
11559 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, A, M2)
11560 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(C, A, M2)
11561 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(C, B, M2)
11562 std::swap(SV0, SV1);
11565 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, B, M2)
11566 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, C, M2)
11567 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, C, M2)
11568 return DAG.getVectorShuffle(VT, SDLoc(N), SV0, SV1, &Mask[0]);
11574 SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) {
11575 SDValue N0 = N->getOperand(0);
11576 SDValue N2 = N->getOperand(2);
11578 // If the input vector is a concatenation, and the insert replaces
11579 // one of the halves, we can optimize into a single concat_vectors.
11580 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
11581 N0->getNumOperands() == 2 && N2.getOpcode() == ISD::Constant) {
11582 APInt InsIdx = cast<ConstantSDNode>(N2)->getAPIntValue();
11583 EVT VT = N->getValueType(0);
11585 // Lower half: fold (insert_subvector (concat_vectors X, Y), Z) ->
11586 // (concat_vectors Z, Y)
11588 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
11589 N->getOperand(1), N0.getOperand(1));
11591 // Upper half: fold (insert_subvector (concat_vectors X, Y), Z) ->
11592 // (concat_vectors X, Z)
11593 if (InsIdx == VT.getVectorNumElements()/2)
11594 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
11595 N0.getOperand(0), N->getOperand(1));
11601 /// Returns a vector_shuffle if it able to transform an AND to a vector_shuffle
11602 /// with the destination vector and a zero vector.
11603 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
11604 /// vector_shuffle V, Zero, <0, 4, 2, 4>
11605 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
11606 EVT VT = N->getValueType(0);
11608 SDValue LHS = N->getOperand(0);
11609 SDValue RHS = N->getOperand(1);
11610 if (N->getOpcode() == ISD::AND) {
11611 if (RHS.getOpcode() == ISD::BITCAST)
11612 RHS = RHS.getOperand(0);
11613 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
11614 SmallVector<int, 8> Indices;
11615 unsigned NumElts = RHS.getNumOperands();
11616 for (unsigned i = 0; i != NumElts; ++i) {
11617 SDValue Elt = RHS.getOperand(i);
11618 if (!isa<ConstantSDNode>(Elt))
11621 if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
11622 Indices.push_back(i);
11623 else if (cast<ConstantSDNode>(Elt)->isNullValue())
11624 Indices.push_back(NumElts+i);
11629 // Let's see if the target supports this vector_shuffle.
11630 EVT RVT = RHS.getValueType();
11631 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
11634 // Return the new VECTOR_SHUFFLE node.
11635 EVT EltVT = RVT.getVectorElementType();
11636 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
11637 DAG.getConstant(0, EltVT));
11638 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), RVT, ZeroOps);
11639 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
11640 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
11641 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
11648 /// Visit a binary vector operation, like ADD.
11649 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
11650 assert(N->getValueType(0).isVector() &&
11651 "SimplifyVBinOp only works on vectors!");
11653 SDValue LHS = N->getOperand(0);
11654 SDValue RHS = N->getOperand(1);
11655 SDValue Shuffle = XformToShuffleWithZero(N);
11656 if (Shuffle.getNode()) return Shuffle;
11658 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
11660 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
11661 RHS.getOpcode() == ISD::BUILD_VECTOR) {
11662 // Check if both vectors are constants. If not bail out.
11663 if (!(cast<BuildVectorSDNode>(LHS)->isConstant() &&
11664 cast<BuildVectorSDNode>(RHS)->isConstant()))
11667 SmallVector<SDValue, 8> Ops;
11668 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
11669 SDValue LHSOp = LHS.getOperand(i);
11670 SDValue RHSOp = RHS.getOperand(i);
11672 // Can't fold divide by zero.
11673 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
11674 N->getOpcode() == ISD::FDIV) {
11675 if ((RHSOp.getOpcode() == ISD::Constant &&
11676 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
11677 (RHSOp.getOpcode() == ISD::ConstantFP &&
11678 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
11682 EVT VT = LHSOp.getValueType();
11683 EVT RVT = RHSOp.getValueType();
11685 // Integer BUILD_VECTOR operands may have types larger than the element
11686 // size (e.g., when the element type is not legal). Prior to type
11687 // legalization, the types may not match between the two BUILD_VECTORS.
11688 // Truncate one of the operands to make them match.
11689 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
11690 RHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, RHSOp);
11692 LHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), RVT, LHSOp);
11696 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(LHS), VT,
11698 if (FoldOp.getOpcode() != ISD::UNDEF &&
11699 FoldOp.getOpcode() != ISD::Constant &&
11700 FoldOp.getOpcode() != ISD::ConstantFP)
11702 Ops.push_back(FoldOp);
11703 AddToWorklist(FoldOp.getNode());
11706 if (Ops.size() == LHS.getNumOperands())
11707 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), LHS.getValueType(), Ops);
11710 // Type legalization might introduce new shuffles in the DAG.
11711 // Fold (VBinOp (shuffle (A, Undef, Mask)), (shuffle (B, Undef, Mask)))
11712 // -> (shuffle (VBinOp (A, B)), Undef, Mask).
11713 if (LegalTypes && isa<ShuffleVectorSDNode>(LHS) &&
11714 isa<ShuffleVectorSDNode>(RHS) && LHS.hasOneUse() && RHS.hasOneUse() &&
11715 LHS.getOperand(1).getOpcode() == ISD::UNDEF &&
11716 RHS.getOperand(1).getOpcode() == ISD::UNDEF) {
11717 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(LHS);
11718 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(RHS);
11720 if (SVN0->getMask().equals(SVN1->getMask())) {
11721 EVT VT = N->getValueType(0);
11722 SDValue UndefVector = LHS.getOperand(1);
11723 SDValue NewBinOp = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
11724 LHS.getOperand(0), RHS.getOperand(0));
11725 AddUsersToWorklist(N);
11726 return DAG.getVectorShuffle(VT, SDLoc(N), NewBinOp, UndefVector,
11727 &SVN0->getMask()[0]);
11734 /// Visit a binary vector operation, like FABS/FNEG.
11735 SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) {
11736 assert(N->getValueType(0).isVector() &&
11737 "SimplifyVUnaryOp only works on vectors!");
11739 SDValue N0 = N->getOperand(0);
11741 if (N0.getOpcode() != ISD::BUILD_VECTOR)
11744 // Operand is a BUILD_VECTOR node, see if we can constant fold it.
11745 SmallVector<SDValue, 8> Ops;
11746 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
11747 SDValue Op = N0.getOperand(i);
11748 if (Op.getOpcode() != ISD::UNDEF &&
11749 Op.getOpcode() != ISD::ConstantFP)
11751 EVT EltVT = Op.getValueType();
11752 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(N0), EltVT, Op);
11753 if (FoldOp.getOpcode() != ISD::UNDEF &&
11754 FoldOp.getOpcode() != ISD::ConstantFP)
11756 Ops.push_back(FoldOp);
11757 AddToWorklist(FoldOp.getNode());
11760 if (Ops.size() != N0.getNumOperands())
11763 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N0.getValueType(), Ops);
11766 SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0,
11767 SDValue N1, SDValue N2){
11768 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
11770 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
11771 cast<CondCodeSDNode>(N0.getOperand(2))->get());
11773 // If we got a simplified select_cc node back from SimplifySelectCC, then
11774 // break it down into a new SETCC node, and a new SELECT node, and then return
11775 // the SELECT node, since we were called with a SELECT node.
11776 if (SCC.getNode()) {
11777 // Check to see if we got a select_cc back (to turn into setcc/select).
11778 // Otherwise, just return whatever node we got back, like fabs.
11779 if (SCC.getOpcode() == ISD::SELECT_CC) {
11780 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
11782 SCC.getOperand(0), SCC.getOperand(1),
11783 SCC.getOperand(4));
11784 AddToWorklist(SETCC.getNode());
11785 return DAG.getSelect(SDLoc(SCC), SCC.getValueType(), SETCC,
11786 SCC.getOperand(2), SCC.getOperand(3));
11794 /// Given a SELECT or a SELECT_CC node, where LHS and RHS are the two values
11795 /// being selected between, see if we can simplify the select. Callers of this
11796 /// should assume that TheSelect is deleted if this returns true. As such, they
11797 /// should return the appropriate thing (e.g. the node) back to the top-level of
11798 /// the DAG combiner loop to avoid it being looked at.
11799 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
11802 // Cannot simplify select with vector condition
11803 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
11805 // If this is a select from two identical things, try to pull the operation
11806 // through the select.
11807 if (LHS.getOpcode() != RHS.getOpcode() ||
11808 !LHS.hasOneUse() || !RHS.hasOneUse())
11811 // If this is a load and the token chain is identical, replace the select
11812 // of two loads with a load through a select of the address to load from.
11813 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
11814 // constants have been dropped into the constant pool.
11815 if (LHS.getOpcode() == ISD::LOAD) {
11816 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
11817 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
11819 // Token chains must be identical.
11820 if (LHS.getOperand(0) != RHS.getOperand(0) ||
11821 // Do not let this transformation reduce the number of volatile loads.
11822 LLD->isVolatile() || RLD->isVolatile() ||
11823 // If this is an EXTLOAD, the VT's must match.
11824 LLD->getMemoryVT() != RLD->getMemoryVT() ||
11825 // If this is an EXTLOAD, the kind of extension must match.
11826 (LLD->getExtensionType() != RLD->getExtensionType() &&
11827 // The only exception is if one of the extensions is anyext.
11828 LLD->getExtensionType() != ISD::EXTLOAD &&
11829 RLD->getExtensionType() != ISD::EXTLOAD) ||
11830 // FIXME: this discards src value information. This is
11831 // over-conservative. It would be beneficial to be able to remember
11832 // both potential memory locations. Since we are discarding
11833 // src value info, don't do the transformation if the memory
11834 // locations are not in the default address space.
11835 LLD->getPointerInfo().getAddrSpace() != 0 ||
11836 RLD->getPointerInfo().getAddrSpace() != 0 ||
11837 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(),
11838 LLD->getBasePtr().getValueType()))
11841 // Check that the select condition doesn't reach either load. If so,
11842 // folding this will induce a cycle into the DAG. If not, this is safe to
11843 // xform, so create a select of the addresses.
11845 if (TheSelect->getOpcode() == ISD::SELECT) {
11846 SDNode *CondNode = TheSelect->getOperand(0).getNode();
11847 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
11848 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
11850 // The loads must not depend on one another.
11851 if (LLD->isPredecessorOf(RLD) ||
11852 RLD->isPredecessorOf(LLD))
11854 Addr = DAG.getSelect(SDLoc(TheSelect),
11855 LLD->getBasePtr().getValueType(),
11856 TheSelect->getOperand(0), LLD->getBasePtr(),
11857 RLD->getBasePtr());
11858 } else { // Otherwise SELECT_CC
11859 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
11860 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
11862 if ((LLD->hasAnyUseOfValue(1) &&
11863 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
11864 (RLD->hasAnyUseOfValue(1) &&
11865 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
11868 Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect),
11869 LLD->getBasePtr().getValueType(),
11870 TheSelect->getOperand(0),
11871 TheSelect->getOperand(1),
11872 LLD->getBasePtr(), RLD->getBasePtr(),
11873 TheSelect->getOperand(4));
11877 // It is safe to replace the two loads if they have different alignments,
11878 // but the new load must be the minimum (most restrictive) alignment of the
11880 bool isInvariant = LLD->isInvariant() & RLD->isInvariant();
11881 unsigned Alignment = std::min(LLD->getAlignment(), RLD->getAlignment());
11882 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
11883 Load = DAG.getLoad(TheSelect->getValueType(0),
11885 // FIXME: Discards pointer and AA info.
11886 LLD->getChain(), Addr, MachinePointerInfo(),
11887 LLD->isVolatile(), LLD->isNonTemporal(),
11888 isInvariant, Alignment);
11890 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
11891 RLD->getExtensionType() : LLD->getExtensionType(),
11893 TheSelect->getValueType(0),
11894 // FIXME: Discards pointer and AA info.
11895 LLD->getChain(), Addr, MachinePointerInfo(),
11896 LLD->getMemoryVT(), LLD->isVolatile(),
11897 LLD->isNonTemporal(), isInvariant, Alignment);
11900 // Users of the select now use the result of the load.
11901 CombineTo(TheSelect, Load);
11903 // Users of the old loads now use the new load's chain. We know the
11904 // old-load value is dead now.
11905 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
11906 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
11913 /// Simplify an expression of the form (N0 cond N1) ? N2 : N3
11914 /// where 'cond' is the comparison specified by CC.
11915 SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
11916 SDValue N2, SDValue N3,
11917 ISD::CondCode CC, bool NotExtCompare) {
11918 // (x ? y : y) -> y.
11919 if (N2 == N3) return N2;
11921 EVT VT = N2.getValueType();
11922 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
11923 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
11924 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
11926 // Determine if the condition we're dealing with is constant
11927 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
11928 N0, N1, CC, DL, false);
11929 if (SCC.getNode()) AddToWorklist(SCC.getNode());
11930 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
11932 // fold select_cc true, x, y -> x
11933 if (SCCC && !SCCC->isNullValue())
11935 // fold select_cc false, x, y -> y
11936 if (SCCC && SCCC->isNullValue())
11939 // Check to see if we can simplify the select into an fabs node
11940 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
11941 // Allow either -0.0 or 0.0
11942 if (CFP->getValueAPF().isZero()) {
11943 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
11944 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
11945 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
11946 N2 == N3.getOperand(0))
11947 return DAG.getNode(ISD::FABS, DL, VT, N0);
11949 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
11950 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
11951 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
11952 N2.getOperand(0) == N3)
11953 return DAG.getNode(ISD::FABS, DL, VT, N3);
11957 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
11958 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
11959 // in it. This is a win when the constant is not otherwise available because
11960 // it replaces two constant pool loads with one. We only do this if the FP
11961 // type is known to be legal, because if it isn't, then we are before legalize
11962 // types an we want the other legalization to happen first (e.g. to avoid
11963 // messing with soft float) and if the ConstantFP is not legal, because if
11964 // it is legal, we may not need to store the FP constant in a constant pool.
11965 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
11966 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
11967 if (TLI.isTypeLegal(N2.getValueType()) &&
11968 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
11969 TargetLowering::Legal &&
11970 !TLI.isFPImmLegal(TV->getValueAPF(), TV->getValueType(0)) &&
11971 !TLI.isFPImmLegal(FV->getValueAPF(), FV->getValueType(0))) &&
11972 // If both constants have multiple uses, then we won't need to do an
11973 // extra load, they are likely around in registers for other users.
11974 (TV->hasOneUse() || FV->hasOneUse())) {
11975 Constant *Elts[] = {
11976 const_cast<ConstantFP*>(FV->getConstantFPValue()),
11977 const_cast<ConstantFP*>(TV->getConstantFPValue())
11979 Type *FPTy = Elts[0]->getType();
11980 const DataLayout &TD = *TLI.getDataLayout();
11982 // Create a ConstantArray of the two constants.
11983 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
11984 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
11985 TD.getPrefTypeAlignment(FPTy));
11986 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11988 // Get the offsets to the 0 and 1 element of the array so that we can
11989 // select between them.
11990 SDValue Zero = DAG.getIntPtrConstant(0);
11991 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
11992 SDValue One = DAG.getIntPtrConstant(EltSize);
11994 SDValue Cond = DAG.getSetCC(DL,
11995 getSetCCResultType(N0.getValueType()),
11997 AddToWorklist(Cond.getNode());
11998 SDValue CstOffset = DAG.getSelect(DL, Zero.getValueType(),
12000 AddToWorklist(CstOffset.getNode());
12001 CPIdx = DAG.getNode(ISD::ADD, DL, CPIdx.getValueType(), CPIdx,
12003 AddToWorklist(CPIdx.getNode());
12004 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
12005 MachinePointerInfo::getConstantPool(), false,
12006 false, false, Alignment);
12011 // Check to see if we can perform the "gzip trick", transforming
12012 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
12013 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
12014 (N1C->isNullValue() || // (a < 0) ? b : 0
12015 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
12016 EVT XType = N0.getValueType();
12017 EVT AType = N2.getValueType();
12018 if (XType.bitsGE(AType)) {
12019 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
12020 // single-bit constant.
12021 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
12022 unsigned ShCtV = N2C->getAPIntValue().logBase2();
12023 ShCtV = XType.getSizeInBits()-ShCtV-1;
12024 SDValue ShCt = DAG.getConstant(ShCtV,
12025 getShiftAmountTy(N0.getValueType()));
12026 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0),
12028 AddToWorklist(Shift.getNode());
12030 if (XType.bitsGT(AType)) {
12031 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
12032 AddToWorklist(Shift.getNode());
12035 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
12038 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0),
12040 DAG.getConstant(XType.getSizeInBits()-1,
12041 getShiftAmountTy(N0.getValueType())));
12042 AddToWorklist(Shift.getNode());
12044 if (XType.bitsGT(AType)) {
12045 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
12046 AddToWorklist(Shift.getNode());
12049 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
12053 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
12054 // where y is has a single bit set.
12055 // A plaintext description would be, we can turn the SELECT_CC into an AND
12056 // when the condition can be materialized as an all-ones register. Any
12057 // single bit-test can be materialized as an all-ones register with
12058 // shift-left and shift-right-arith.
12059 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
12060 N0->getValueType(0) == VT &&
12061 N1C && N1C->isNullValue() &&
12062 N2C && N2C->isNullValue()) {
12063 SDValue AndLHS = N0->getOperand(0);
12064 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
12065 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
12066 // Shift the tested bit over the sign bit.
12067 APInt AndMask = ConstAndRHS->getAPIntValue();
12069 DAG.getConstant(AndMask.countLeadingZeros(),
12070 getShiftAmountTy(AndLHS.getValueType()));
12071 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
12073 // Now arithmetic right shift it all the way over, so the result is either
12074 // all-ones, or zero.
12076 DAG.getConstant(AndMask.getBitWidth()-1,
12077 getShiftAmountTy(Shl.getValueType()));
12078 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
12080 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
12084 // fold select C, 16, 0 -> shl C, 4
12085 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
12086 TLI.getBooleanContents(N0.getValueType()) ==
12087 TargetLowering::ZeroOrOneBooleanContent) {
12089 // If the caller doesn't want us to simplify this into a zext of a compare,
12091 if (NotExtCompare && N2C->getAPIntValue() == 1)
12094 // Get a SetCC of the condition
12095 // NOTE: Don't create a SETCC if it's not legal on this target.
12096 if (!LegalOperations ||
12097 TLI.isOperationLegal(ISD::SETCC,
12098 LegalTypes ? getSetCCResultType(N0.getValueType()) : MVT::i1)) {
12100 // cast from setcc result type to select result type
12102 SCC = DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()),
12104 if (N2.getValueType().bitsLT(SCC.getValueType()))
12105 Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2),
12106 N2.getValueType());
12108 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
12109 N2.getValueType(), SCC);
12111 SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
12112 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
12113 N2.getValueType(), SCC);
12116 AddToWorklist(SCC.getNode());
12117 AddToWorklist(Temp.getNode());
12119 if (N2C->getAPIntValue() == 1)
12122 // shl setcc result by log2 n2c
12123 return DAG.getNode(
12124 ISD::SHL, DL, N2.getValueType(), Temp,
12125 DAG.getConstant(N2C->getAPIntValue().logBase2(),
12126 getShiftAmountTy(Temp.getValueType())));
12130 // Check to see if this is the equivalent of setcc
12131 // FIXME: Turn all of these into setcc if setcc if setcc is legal
12132 // otherwise, go ahead with the folds.
12133 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
12134 EVT XType = N0.getValueType();
12135 if (!LegalOperations ||
12136 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(XType))) {
12137 SDValue Res = DAG.getSetCC(DL, getSetCCResultType(XType), N0, N1, CC);
12138 if (Res.getValueType() != VT)
12139 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
12143 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
12144 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
12145 (!LegalOperations ||
12146 TLI.isOperationLegal(ISD::CTLZ, XType))) {
12147 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0);
12148 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
12149 DAG.getConstant(Log2_32(XType.getSizeInBits()),
12150 getShiftAmountTy(Ctlz.getValueType())));
12152 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
12153 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
12154 SDValue NegN0 = DAG.getNode(ISD::SUB, SDLoc(N0),
12155 XType, DAG.getConstant(0, XType), N0);
12156 SDValue NotN0 = DAG.getNOT(SDLoc(N0), N0, XType);
12157 return DAG.getNode(ISD::SRL, DL, XType,
12158 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
12159 DAG.getConstant(XType.getSizeInBits()-1,
12160 getShiftAmountTy(XType)));
12162 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
12163 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
12164 SDValue Sign = DAG.getNode(ISD::SRL, SDLoc(N0), XType, N0,
12165 DAG.getConstant(XType.getSizeInBits()-1,
12166 getShiftAmountTy(N0.getValueType())));
12167 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
12171 // Check to see if this is an integer abs.
12172 // select_cc setg[te] X, 0, X, -X ->
12173 // select_cc setgt X, -1, X, -X ->
12174 // select_cc setl[te] X, 0, -X, X ->
12175 // select_cc setlt X, 1, -X, X ->
12176 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
12178 ConstantSDNode *SubC = nullptr;
12179 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
12180 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
12181 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
12182 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
12183 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
12184 (N1C->isOne() && CC == ISD::SETLT)) &&
12185 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
12186 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
12188 EVT XType = N0.getValueType();
12189 if (SubC && SubC->isNullValue() && XType.isInteger()) {
12190 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), XType,
12192 DAG.getConstant(XType.getSizeInBits()-1,
12193 getShiftAmountTy(N0.getValueType())));
12194 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0),
12196 AddToWorklist(Shift.getNode());
12197 AddToWorklist(Add.getNode());
12198 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
12205 /// This is a stub for TargetLowering::SimplifySetCC.
12206 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
12207 SDValue N1, ISD::CondCode Cond,
12208 SDLoc DL, bool foldBooleans) {
12209 TargetLowering::DAGCombinerInfo
12210 DagCombineInfo(DAG, Level, false, this);
12211 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
12214 /// Given an ISD::SDIV node expressing a divide by constant, return
12215 /// a DAG expression to select that will generate the same value by multiplying
12216 /// by a magic number.
12217 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
12218 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
12219 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
12223 // Avoid division by zero.
12224 if (!C->getAPIntValue())
12227 std::vector<SDNode*> Built;
12229 TLI.BuildSDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
12231 for (SDNode *N : Built)
12236 /// Given an ISD::SDIV node expressing a divide by constant power of 2, return a
12237 /// DAG expression that will generate the same value by right shifting.
12238 SDValue DAGCombiner::BuildSDIVPow2(SDNode *N) {
12239 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
12243 // Avoid division by zero.
12244 if (!C->getAPIntValue())
12247 std::vector<SDNode *> Built;
12248 SDValue S = TLI.BuildSDIVPow2(N, C->getAPIntValue(), DAG, &Built);
12250 for (SDNode *N : Built)
12255 /// Given an ISD::UDIV node expressing a divide by constant, return a DAG
12256 /// expression that will generate the same value by multiplying by a magic
12258 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
12259 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
12260 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
12264 // Avoid division by zero.
12265 if (!C->getAPIntValue())
12268 std::vector<SDNode*> Built;
12270 TLI.BuildUDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
12272 for (SDNode *N : Built)
12277 SDValue DAGCombiner::BuildReciprocalEstimate(SDValue Op) {
12278 if (Level >= AfterLegalizeDAG)
12281 // Expose the DAG combiner to the target combiner implementations.
12282 TargetLowering::DAGCombinerInfo DCI(DAG, Level, false, this);
12284 unsigned Iterations = 0;
12285 if (SDValue Est = TLI.getRecipEstimate(Op, DCI, Iterations)) {
12287 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
12288 // For the reciprocal, we need to find the zero of the function:
12289 // F(X) = A X - 1 [which has a zero at X = 1/A]
12291 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
12292 // does not require additional intermediate precision]
12293 EVT VT = Op.getValueType();
12295 SDValue FPOne = DAG.getConstantFP(1.0, VT);
12297 AddToWorklist(Est.getNode());
12299 // Newton iterations: Est = Est + Est (1 - Arg * Est)
12300 for (unsigned i = 0; i < Iterations; ++i) {
12301 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Op, Est);
12302 AddToWorklist(NewEst.getNode());
12304 NewEst = DAG.getNode(ISD::FSUB, DL, VT, FPOne, NewEst);
12305 AddToWorklist(NewEst.getNode());
12307 NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst);
12308 AddToWorklist(NewEst.getNode());
12310 Est = DAG.getNode(ISD::FADD, DL, VT, Est, NewEst);
12311 AddToWorklist(Est.getNode());
12320 /// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
12321 /// For the reciprocal sqrt, we need to find the zero of the function:
12322 /// F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
12324 /// X_{i+1} = X_i (1.5 - A X_i^2 / 2)
12325 /// As a result, we precompute A/2 prior to the iteration loop.
12326 SDValue DAGCombiner::BuildRsqrtNROneConst(SDValue Arg, SDValue Est,
12327 unsigned Iterations) {
12328 EVT VT = Arg.getValueType();
12330 SDValue ThreeHalves = DAG.getConstantFP(1.5, VT);
12332 // We now need 0.5 * Arg which we can write as (1.5 * Arg - Arg) so that
12333 // this entire sequence requires only one FP constant.
12334 SDValue HalfArg = DAG.getNode(ISD::FMUL, DL, VT, ThreeHalves, Arg);
12335 AddToWorklist(HalfArg.getNode());
12337 HalfArg = DAG.getNode(ISD::FSUB, DL, VT, HalfArg, Arg);
12338 AddToWorklist(HalfArg.getNode());
12340 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
12341 for (unsigned i = 0; i < Iterations; ++i) {
12342 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, Est);
12343 AddToWorklist(NewEst.getNode());
12345 NewEst = DAG.getNode(ISD::FMUL, DL, VT, HalfArg, NewEst);
12346 AddToWorklist(NewEst.getNode());
12348 NewEst = DAG.getNode(ISD::FSUB, DL, VT, ThreeHalves, NewEst);
12349 AddToWorklist(NewEst.getNode());
12351 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst);
12352 AddToWorklist(Est.getNode());
12357 /// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
12358 /// For the reciprocal sqrt, we need to find the zero of the function:
12359 /// F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
12361 /// X_{i+1} = (-0.5 * X_i) * (A * X_i * X_i + (-3.0))
12362 SDValue DAGCombiner::BuildRsqrtNRTwoConst(SDValue Arg, SDValue Est,
12363 unsigned Iterations) {
12364 EVT VT = Arg.getValueType();
12366 SDValue MinusThree = DAG.getConstantFP(-3.0, VT);
12367 SDValue MinusHalf = DAG.getConstantFP(-0.5, VT);
12369 // Newton iterations: Est = -0.5 * Est * (-3.0 + Arg * Est * Est)
12370 for (unsigned i = 0; i < Iterations; ++i) {
12371 SDValue HalfEst = DAG.getNode(ISD::FMUL, DL, VT, Est, MinusHalf);
12372 AddToWorklist(HalfEst.getNode());
12374 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Est);
12375 AddToWorklist(Est.getNode());
12377 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Arg);
12378 AddToWorklist(Est.getNode());
12380 Est = DAG.getNode(ISD::FADD, DL, VT, Est, MinusThree);
12381 AddToWorklist(Est.getNode());
12383 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, HalfEst);
12384 AddToWorklist(Est.getNode());
12389 SDValue DAGCombiner::BuildRsqrtEstimate(SDValue Op) {
12390 if (Level >= AfterLegalizeDAG)
12393 // Expose the DAG combiner to the target combiner implementations.
12394 TargetLowering::DAGCombinerInfo DCI(DAG, Level, false, this);
12395 unsigned Iterations = 0;
12396 bool UseOneConstNR = false;
12397 if (SDValue Est = TLI.getRsqrtEstimate(Op, DCI, Iterations, UseOneConstNR)) {
12398 AddToWorklist(Est.getNode());
12400 Est = UseOneConstNR ?
12401 BuildRsqrtNROneConst(Op, Est, Iterations) :
12402 BuildRsqrtNRTwoConst(Op, Est, Iterations);
12410 /// Return true if base is a frame index, which is known not to alias with
12411 /// anything but itself. Provides base object and offset as results.
12412 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
12413 const GlobalValue *&GV, const void *&CV) {
12414 // Assume it is a primitive operation.
12415 Base = Ptr; Offset = 0; GV = nullptr; CV = nullptr;
12417 // If it's an adding a simple constant then integrate the offset.
12418 if (Base.getOpcode() == ISD::ADD) {
12419 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
12420 Base = Base.getOperand(0);
12421 Offset += C->getZExtValue();
12425 // Return the underlying GlobalValue, and update the Offset. Return false
12426 // for GlobalAddressSDNode since the same GlobalAddress may be represented
12427 // by multiple nodes with different offsets.
12428 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
12429 GV = G->getGlobal();
12430 Offset += G->getOffset();
12434 // Return the underlying Constant value, and update the Offset. Return false
12435 // for ConstantSDNodes since the same constant pool entry may be represented
12436 // by multiple nodes with different offsets.
12437 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
12438 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
12439 : (const void *)C->getConstVal();
12440 Offset += C->getOffset();
12443 // If it's any of the following then it can't alias with anything but itself.
12444 return isa<FrameIndexSDNode>(Base);
12447 /// Return true if there is any possibility that the two addresses overlap.
12448 bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const {
12449 // If they are the same then they must be aliases.
12450 if (Op0->getBasePtr() == Op1->getBasePtr()) return true;
12452 // If they are both volatile then they cannot be reordered.
12453 if (Op0->isVolatile() && Op1->isVolatile()) return true;
12455 // Gather base node and offset information.
12456 SDValue Base1, Base2;
12457 int64_t Offset1, Offset2;
12458 const GlobalValue *GV1, *GV2;
12459 const void *CV1, *CV2;
12460 bool isFrameIndex1 = FindBaseOffset(Op0->getBasePtr(),
12461 Base1, Offset1, GV1, CV1);
12462 bool isFrameIndex2 = FindBaseOffset(Op1->getBasePtr(),
12463 Base2, Offset2, GV2, CV2);
12465 // If they have a same base address then check to see if they overlap.
12466 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
12467 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
12468 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
12470 // It is possible for different frame indices to alias each other, mostly
12471 // when tail call optimization reuses return address slots for arguments.
12472 // To catch this case, look up the actual index of frame indices to compute
12473 // the real alias relationship.
12474 if (isFrameIndex1 && isFrameIndex2) {
12475 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12476 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
12477 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
12478 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
12479 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
12482 // Otherwise, if we know what the bases are, and they aren't identical, then
12483 // we know they cannot alias.
12484 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
12487 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
12488 // compared to the size and offset of the access, we may be able to prove they
12489 // do not alias. This check is conservative for now to catch cases created by
12490 // splitting vector types.
12491 if ((Op0->getOriginalAlignment() == Op1->getOriginalAlignment()) &&
12492 (Op0->getSrcValueOffset() != Op1->getSrcValueOffset()) &&
12493 (Op0->getMemoryVT().getSizeInBits() >> 3 ==
12494 Op1->getMemoryVT().getSizeInBits() >> 3) &&
12495 (Op0->getOriginalAlignment() > Op0->getMemoryVT().getSizeInBits()) >> 3) {
12496 int64_t OffAlign1 = Op0->getSrcValueOffset() % Op0->getOriginalAlignment();
12497 int64_t OffAlign2 = Op1->getSrcValueOffset() % Op1->getOriginalAlignment();
12499 // There is no overlap between these relatively aligned accesses of similar
12500 // size, return no alias.
12501 if ((OffAlign1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign2 ||
12502 (OffAlign2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign1)
12506 bool UseAA = CombinerGlobalAA.getNumOccurrences() > 0
12508 : DAG.getSubtarget().useAA();
12510 if (CombinerAAOnlyFunc.getNumOccurrences() &&
12511 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
12515 Op0->getMemOperand()->getValue() && Op1->getMemOperand()->getValue()) {
12516 // Use alias analysis information.
12517 int64_t MinOffset = std::min(Op0->getSrcValueOffset(),
12518 Op1->getSrcValueOffset());
12519 int64_t Overlap1 = (Op0->getMemoryVT().getSizeInBits() >> 3) +
12520 Op0->getSrcValueOffset() - MinOffset;
12521 int64_t Overlap2 = (Op1->getMemoryVT().getSizeInBits() >> 3) +
12522 Op1->getSrcValueOffset() - MinOffset;
12523 AliasAnalysis::AliasResult AAResult =
12524 AA.alias(AliasAnalysis::Location(Op0->getMemOperand()->getValue(),
12526 UseTBAA ? Op0->getAAInfo() : AAMDNodes()),
12527 AliasAnalysis::Location(Op1->getMemOperand()->getValue(),
12529 UseTBAA ? Op1->getAAInfo() : AAMDNodes()));
12530 if (AAResult == AliasAnalysis::NoAlias)
12534 // Otherwise we have to assume they alias.
12538 /// Walk up chain skipping non-aliasing memory nodes,
12539 /// looking for aliasing nodes and adding them to the Aliases vector.
12540 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
12541 SmallVectorImpl<SDValue> &Aliases) {
12542 SmallVector<SDValue, 8> Chains; // List of chains to visit.
12543 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
12545 // Get alias information for node.
12546 bool IsLoad = isa<LoadSDNode>(N) && !cast<LSBaseSDNode>(N)->isVolatile();
12549 Chains.push_back(OriginalChain);
12550 unsigned Depth = 0;
12552 // Look at each chain and determine if it is an alias. If so, add it to the
12553 // aliases list. If not, then continue up the chain looking for the next
12555 while (!Chains.empty()) {
12556 SDValue Chain = Chains.back();
12559 // For TokenFactor nodes, look at each operand and only continue up the
12560 // chain until we find two aliases. If we've seen two aliases, assume we'll
12561 // find more and revert to original chain since the xform is unlikely to be
12564 // FIXME: The depth check could be made to return the last non-aliasing
12565 // chain we found before we hit a tokenfactor rather than the original
12567 if (Depth > 6 || Aliases.size() == 2) {
12569 Aliases.push_back(OriginalChain);
12573 // Don't bother if we've been before.
12574 if (!Visited.insert(Chain.getNode()).second)
12577 switch (Chain.getOpcode()) {
12578 case ISD::EntryToken:
12579 // Entry token is ideal chain operand, but handled in FindBetterChain.
12584 // Get alias information for Chain.
12585 bool IsOpLoad = isa<LoadSDNode>(Chain.getNode()) &&
12586 !cast<LSBaseSDNode>(Chain.getNode())->isVolatile();
12588 // If chain is alias then stop here.
12589 if (!(IsLoad && IsOpLoad) &&
12590 isAlias(cast<LSBaseSDNode>(N), cast<LSBaseSDNode>(Chain.getNode()))) {
12591 Aliases.push_back(Chain);
12593 // Look further up the chain.
12594 Chains.push_back(Chain.getOperand(0));
12600 case ISD::TokenFactor:
12601 // We have to check each of the operands of the token factor for "small"
12602 // token factors, so we queue them up. Adding the operands to the queue
12603 // (stack) in reverse order maintains the original order and increases the
12604 // likelihood that getNode will find a matching token factor (CSE.)
12605 if (Chain.getNumOperands() > 16) {
12606 Aliases.push_back(Chain);
12609 for (unsigned n = Chain.getNumOperands(); n;)
12610 Chains.push_back(Chain.getOperand(--n));
12615 // For all other instructions we will just have to take what we can get.
12616 Aliases.push_back(Chain);
12621 // We need to be careful here to also search for aliases through the
12622 // value operand of a store, etc. Consider the following situation:
12624 // L1 = load Token1, %52
12625 // S1 = store Token1, L1, %51
12626 // L2 = load Token1, %52+8
12627 // S2 = store Token1, L2, %51+8
12628 // Token2 = Token(S1, S2)
12629 // L3 = load Token2, %53
12630 // S3 = store Token2, L3, %52
12631 // L4 = load Token2, %53+8
12632 // S4 = store Token2, L4, %52+8
12633 // If we search for aliases of S3 (which loads address %52), and we look
12634 // only through the chain, then we'll miss the trivial dependence on L1
12635 // (which also loads from %52). We then might change all loads and
12636 // stores to use Token1 as their chain operand, which could result in
12637 // copying %53 into %52 before copying %52 into %51 (which should
12640 // The problem is, however, that searching for such data dependencies
12641 // can become expensive, and the cost is not directly related to the
12642 // chain depth. Instead, we'll rule out such configurations here by
12643 // insisting that we've visited all chain users (except for users
12644 // of the original chain, which is not necessary). When doing this,
12645 // we need to look through nodes we don't care about (otherwise, things
12646 // like register copies will interfere with trivial cases).
12648 SmallVector<const SDNode *, 16> Worklist;
12649 for (const SDNode *N : Visited)
12650 if (N != OriginalChain.getNode())
12651 Worklist.push_back(N);
12653 while (!Worklist.empty()) {
12654 const SDNode *M = Worklist.pop_back_val();
12656 // We have already visited M, and want to make sure we've visited any uses
12657 // of M that we care about. For uses that we've not visisted, and don't
12658 // care about, queue them to the worklist.
12660 for (SDNode::use_iterator UI = M->use_begin(),
12661 UIE = M->use_end(); UI != UIE; ++UI)
12662 if (UI.getUse().getValueType() == MVT::Other &&
12663 Visited.insert(*UI).second) {
12664 if (isa<MemIntrinsicSDNode>(*UI) || isa<MemSDNode>(*UI)) {
12665 // We've not visited this use, and we care about it (it could have an
12666 // ordering dependency with the original node).
12668 Aliases.push_back(OriginalChain);
12672 // We've not visited this use, but we don't care about it. Mark it as
12673 // visited and enqueue it to the worklist.
12674 Worklist.push_back(*UI);
12679 /// Walk up chain skipping non-aliasing memory nodes, looking for a better chain
12680 /// (aliasing node.)
12681 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
12682 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
12684 // Accumulate all the aliases to this node.
12685 GatherAllAliases(N, OldChain, Aliases);
12687 // If no operands then chain to entry token.
12688 if (Aliases.size() == 0)
12689 return DAG.getEntryNode();
12691 // If a single operand then chain to it. We don't need to revisit it.
12692 if (Aliases.size() == 1)
12695 // Construct a custom tailored token factor.
12696 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Aliases);
12699 /// This is the entry point for the file.
12700 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
12701 CodeGenOpt::Level OptLevel) {
12702 /// This is the main entry point to this class.
12703 DAGCombiner(*this, AA, OptLevel).Run(Level);