1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Target/TargetLowering.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/CommandLine.h"
46 static Statistic<> NodesCombined ("dagcombiner",
47 "Number of dag nodes combined");
50 CombinerAA("combiner-alias-analysis", cl::Hidden,
51 cl::desc("Turn on alias analysis turning testing"));
53 //------------------------------ DAGCombiner ---------------------------------//
55 class VISIBILITY_HIDDEN DAGCombiner {
60 // Worklist of all of the nodes that need to be simplified.
61 std::vector<SDNode*> WorkList;
63 /// AddUsersToWorkList - When an instruction is simplified, add all users of
64 /// the instruction to the work lists because they might get more simplified
67 void AddUsersToWorkList(SDNode *N) {
68 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
73 /// removeFromWorkList - remove all instances of N from the worklist.
75 void removeFromWorkList(SDNode *N) {
76 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
81 /// AddToWorkList - Add to the work list making sure it's instance is at the
82 /// the back (next to be processed.)
83 void AddToWorkList(SDNode *N) {
84 removeFromWorkList(N);
85 WorkList.push_back(N);
88 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
90 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
92 DEBUG(std::cerr << "\nReplacing.1 "; N->dump();
93 std::cerr << "\nWith: "; To[0].Val->dump(&DAG);
94 std::cerr << " and " << NumTo-1 << " other values\n");
95 std::vector<SDNode*> NowDead;
96 DAG.ReplaceAllUsesWith(N, To, &NowDead);
99 // Push the new nodes and any users onto the worklist
100 for (unsigned i = 0, e = NumTo; i != e; ++i) {
101 AddToWorkList(To[i].Val);
102 AddUsersToWorkList(To[i].Val);
106 // Nodes can be reintroduced into the worklist. Make sure we do not
107 // process a node that has been replaced.
108 removeFromWorkList(N);
109 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
110 removeFromWorkList(NowDead[i]);
112 // Finally, since the node is now dead, remove it from the graph.
114 return SDOperand(N, 0);
117 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
118 return CombineTo(N, &Res, 1, AddTo);
121 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
123 SDOperand To[] = { Res0, Res1 };
124 return CombineTo(N, To, 2, AddTo);
128 /// SimplifyDemandedBits - Check the specified integer node value to see if
129 /// it can be simplified or if things it uses can be simplified by bit
130 /// propagation. If so, return true.
131 bool SimplifyDemandedBits(SDOperand Op) {
132 TargetLowering::TargetLoweringOpt TLO(DAG);
133 uint64_t KnownZero, KnownOne;
134 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
135 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
139 AddToWorkList(Op.Val);
141 // Replace the old value with the new one.
143 DEBUG(std::cerr << "\nReplacing.2 "; TLO.Old.Val->dump();
144 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG);
147 std::vector<SDNode*> NowDead;
148 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
150 // Push the new node and any (possibly new) users onto the worklist.
151 AddToWorkList(TLO.New.Val);
152 AddUsersToWorkList(TLO.New.Val);
154 // Nodes can end up on the worklist more than once. Make sure we do
155 // not process a node that has been replaced.
156 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
157 removeFromWorkList(NowDead[i]);
159 // Finally, if the node is now dead, remove it from the graph. The node
160 // may not be dead if the replacement process recursively simplified to
161 // something else needing this node.
162 if (TLO.Old.Val->use_empty()) {
163 removeFromWorkList(TLO.Old.Val);
164 DAG.DeleteNode(TLO.Old.Val);
169 /// visit - call the node-specific routine that knows how to fold each
170 /// particular type of node.
171 SDOperand visit(SDNode *N);
173 // Visitation implementation - Implement dag node combining for different
174 // node types. The semantics are as follows:
176 // SDOperand.Val == 0 - No change was made
177 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
178 // otherwise - N should be replaced by the returned Operand.
180 SDOperand visitTokenFactor(SDNode *N);
181 SDOperand visitADD(SDNode *N);
182 SDOperand visitSUB(SDNode *N);
183 SDOperand visitMUL(SDNode *N);
184 SDOperand visitSDIV(SDNode *N);
185 SDOperand visitUDIV(SDNode *N);
186 SDOperand visitSREM(SDNode *N);
187 SDOperand visitUREM(SDNode *N);
188 SDOperand visitMULHU(SDNode *N);
189 SDOperand visitMULHS(SDNode *N);
190 SDOperand visitAND(SDNode *N);
191 SDOperand visitOR(SDNode *N);
192 SDOperand visitXOR(SDNode *N);
193 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
194 SDOperand visitSHL(SDNode *N);
195 SDOperand visitSRA(SDNode *N);
196 SDOperand visitSRL(SDNode *N);
197 SDOperand visitCTLZ(SDNode *N);
198 SDOperand visitCTTZ(SDNode *N);
199 SDOperand visitCTPOP(SDNode *N);
200 SDOperand visitSELECT(SDNode *N);
201 SDOperand visitSELECT_CC(SDNode *N);
202 SDOperand visitSETCC(SDNode *N);
203 SDOperand visitSIGN_EXTEND(SDNode *N);
204 SDOperand visitZERO_EXTEND(SDNode *N);
205 SDOperand visitANY_EXTEND(SDNode *N);
206 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
207 SDOperand visitTRUNCATE(SDNode *N);
208 SDOperand visitBIT_CONVERT(SDNode *N);
209 SDOperand visitVBIT_CONVERT(SDNode *N);
210 SDOperand visitFADD(SDNode *N);
211 SDOperand visitFSUB(SDNode *N);
212 SDOperand visitFMUL(SDNode *N);
213 SDOperand visitFDIV(SDNode *N);
214 SDOperand visitFREM(SDNode *N);
215 SDOperand visitFCOPYSIGN(SDNode *N);
216 SDOperand visitSINT_TO_FP(SDNode *N);
217 SDOperand visitUINT_TO_FP(SDNode *N);
218 SDOperand visitFP_TO_SINT(SDNode *N);
219 SDOperand visitFP_TO_UINT(SDNode *N);
220 SDOperand visitFP_ROUND(SDNode *N);
221 SDOperand visitFP_ROUND_INREG(SDNode *N);
222 SDOperand visitFP_EXTEND(SDNode *N);
223 SDOperand visitFNEG(SDNode *N);
224 SDOperand visitFABS(SDNode *N);
225 SDOperand visitBRCOND(SDNode *N);
226 SDOperand visitBR_CC(SDNode *N);
227 SDOperand visitLOAD(SDNode *N);
228 SDOperand visitSTORE(SDNode *N);
229 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
230 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
231 SDOperand visitVBUILD_VECTOR(SDNode *N);
232 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
233 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
235 SDOperand XformToShuffleWithZero(SDNode *N);
236 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
238 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
239 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
240 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
241 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
242 SDOperand N3, ISD::CondCode CC);
243 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
244 ISD::CondCode Cond, bool foldBooleans = true);
245 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
246 SDOperand BuildSDIV(SDNode *N);
247 SDOperand BuildUDIV(SDNode *N);
248 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
250 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
251 /// looking for aliasing nodes and adding them to the Aliases vector.
252 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
253 SmallVector<SDOperand, 8> &Aliases);
255 /// FindAliasInfo - Extracts the relevant alias information from the memory
256 /// node. Returns true if the operand was a load.
257 bool FindAliasInfo(SDNode *N,
258 SDOperand &Ptr, int64_t &Size, const Value *&SrcValue);
260 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
261 /// looking for a better chain (aliasing node.)
262 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
265 DAGCombiner(SelectionDAG &D)
266 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
268 /// Run - runs the dag combiner on all nodes in the work list
269 void Run(bool RunningAfterLegalize);
273 //===----------------------------------------------------------------------===//
274 // TargetLowering::DAGCombinerInfo implementation
275 //===----------------------------------------------------------------------===//
277 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
278 ((DAGCombiner*)DC)->AddToWorkList(N);
281 SDOperand TargetLowering::DAGCombinerInfo::
282 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
283 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
286 SDOperand TargetLowering::DAGCombinerInfo::
287 CombineTo(SDNode *N, SDOperand Res) {
288 return ((DAGCombiner*)DC)->CombineTo(N, Res);
292 SDOperand TargetLowering::DAGCombinerInfo::
293 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
294 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
300 //===----------------------------------------------------------------------===//
303 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
304 // that selects between the values 1 and 0, making it equivalent to a setcc.
305 // Also, set the incoming LHS, RHS, and CC references to the appropriate
306 // nodes based on the type of node we are checking. This simplifies life a
307 // bit for the callers.
308 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
310 if (N.getOpcode() == ISD::SETCC) {
311 LHS = N.getOperand(0);
312 RHS = N.getOperand(1);
313 CC = N.getOperand(2);
316 if (N.getOpcode() == ISD::SELECT_CC &&
317 N.getOperand(2).getOpcode() == ISD::Constant &&
318 N.getOperand(3).getOpcode() == ISD::Constant &&
319 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
320 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
321 LHS = N.getOperand(0);
322 RHS = N.getOperand(1);
323 CC = N.getOperand(4);
329 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
330 // one use. If this is true, it allows the users to invert the operation for
331 // free when it is profitable to do so.
332 static bool isOneUseSetCC(SDOperand N) {
333 SDOperand N0, N1, N2;
334 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
339 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
340 MVT::ValueType VT = N0.getValueType();
341 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
342 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
343 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
344 if (isa<ConstantSDNode>(N1)) {
345 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
346 AddToWorkList(OpNode.Val);
347 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
348 } else if (N0.hasOneUse()) {
349 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
350 AddToWorkList(OpNode.Val);
351 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
354 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
355 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
356 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
357 if (isa<ConstantSDNode>(N0)) {
358 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
359 AddToWorkList(OpNode.Val);
360 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
361 } else if (N1.hasOneUse()) {
362 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
363 AddToWorkList(OpNode.Val);
364 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
370 void DAGCombiner::Run(bool RunningAfterLegalize) {
371 // set the instance variable, so that the various visit routines may use it.
372 AfterLegalize = RunningAfterLegalize;
374 // Add all the dag nodes to the worklist.
375 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
376 E = DAG.allnodes_end(); I != E; ++I)
377 WorkList.push_back(I);
379 // Create a dummy node (which is not added to allnodes), that adds a reference
380 // to the root node, preventing it from being deleted, and tracking any
381 // changes of the root.
382 HandleSDNode Dummy(DAG.getRoot());
385 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
386 TargetLowering::DAGCombinerInfo
387 DagCombineInfo(DAG, !RunningAfterLegalize, this);
389 // while the worklist isn't empty, inspect the node on the end of it and
390 // try and combine it.
391 while (!WorkList.empty()) {
392 SDNode *N = WorkList.back();
395 // If N has no uses, it is dead. Make sure to revisit all N's operands once
396 // N is deleted from the DAG, since they too may now be dead or may have a
397 // reduced number of uses, allowing other xforms.
398 if (N->use_empty() && N != &Dummy) {
399 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
400 AddToWorkList(N->getOperand(i).Val);
406 SDOperand RV = visit(N);
408 // If nothing happened, try a target-specific DAG combine.
410 assert(N->getOpcode() != ISD::DELETED_NODE &&
411 "Node was deleted but visit returned NULL!");
412 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
413 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
414 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
419 // If we get back the same node we passed in, rather than a new node or
420 // zero, we know that the node must have defined multiple values and
421 // CombineTo was used. Since CombineTo takes care of the worklist
422 // mechanics for us, we have no work to do in this case.
424 assert(N->getOpcode() != ISD::DELETED_NODE &&
425 RV.Val->getOpcode() != ISD::DELETED_NODE &&
426 "Node was deleted but visit returned new node!");
428 DEBUG(std::cerr << "\nReplacing.3 "; N->dump();
429 std::cerr << "\nWith: "; RV.Val->dump(&DAG);
431 std::vector<SDNode*> NowDead;
432 if (N->getNumValues() == RV.Val->getNumValues())
433 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
435 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
437 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
440 // Push the new node and any users onto the worklist
441 AddToWorkList(RV.Val);
442 AddUsersToWorkList(RV.Val);
444 // Nodes can be reintroduced into the worklist. Make sure we do not
445 // process a node that has been replaced.
446 removeFromWorkList(N);
447 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
448 removeFromWorkList(NowDead[i]);
450 // Finally, since the node is now dead, remove it from the graph.
456 // If the root changed (e.g. it was a dead load, update the root).
457 DAG.setRoot(Dummy.getValue());
460 SDOperand DAGCombiner::visit(SDNode *N) {
461 switch(N->getOpcode()) {
463 case ISD::TokenFactor: return visitTokenFactor(N);
464 case ISD::ADD: return visitADD(N);
465 case ISD::SUB: return visitSUB(N);
466 case ISD::MUL: return visitMUL(N);
467 case ISD::SDIV: return visitSDIV(N);
468 case ISD::UDIV: return visitUDIV(N);
469 case ISD::SREM: return visitSREM(N);
470 case ISD::UREM: return visitUREM(N);
471 case ISD::MULHU: return visitMULHU(N);
472 case ISD::MULHS: return visitMULHS(N);
473 case ISD::AND: return visitAND(N);
474 case ISD::OR: return visitOR(N);
475 case ISD::XOR: return visitXOR(N);
476 case ISD::SHL: return visitSHL(N);
477 case ISD::SRA: return visitSRA(N);
478 case ISD::SRL: return visitSRL(N);
479 case ISD::CTLZ: return visitCTLZ(N);
480 case ISD::CTTZ: return visitCTTZ(N);
481 case ISD::CTPOP: return visitCTPOP(N);
482 case ISD::SELECT: return visitSELECT(N);
483 case ISD::SELECT_CC: return visitSELECT_CC(N);
484 case ISD::SETCC: return visitSETCC(N);
485 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
486 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
487 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
488 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
489 case ISD::TRUNCATE: return visitTRUNCATE(N);
490 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
491 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
492 case ISD::FADD: return visitFADD(N);
493 case ISD::FSUB: return visitFSUB(N);
494 case ISD::FMUL: return visitFMUL(N);
495 case ISD::FDIV: return visitFDIV(N);
496 case ISD::FREM: return visitFREM(N);
497 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
498 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
499 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
500 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
501 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
502 case ISD::FP_ROUND: return visitFP_ROUND(N);
503 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
504 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
505 case ISD::FNEG: return visitFNEG(N);
506 case ISD::FABS: return visitFABS(N);
507 case ISD::BRCOND: return visitBRCOND(N);
508 case ISD::BR_CC: return visitBR_CC(N);
509 case ISD::LOAD: return visitLOAD(N);
510 case ISD::STORE: return visitSTORE(N);
511 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
512 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
513 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
514 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
515 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
516 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
517 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
518 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
519 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
520 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
521 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
522 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
523 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
528 /// getInputChainForNode - Given a node, return its input chain if it has one,
529 /// otherwise return a null sd operand.
530 static SDOperand getInputChainForNode(SDNode *N) {
531 if (unsigned NumOps = N->getNumOperands()) {
532 if (N->getOperand(0).getValueType() == MVT::Other)
533 return N->getOperand(0);
534 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
535 return N->getOperand(NumOps-1);
536 for (unsigned i = 1; i < NumOps-1; ++i)
537 if (N->getOperand(i).getValueType() == MVT::Other)
538 return N->getOperand(i);
540 return SDOperand(0, 0);
543 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
544 // If N has two operands, where one has an input chain equal to the other,
545 // the 'other' chain is redundant.
546 if (N->getNumOperands() == 2) {
547 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
548 return N->getOperand(0);
549 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
550 return N->getOperand(1);
554 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
555 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
556 bool Changed = false; // If we should replace this token factor.
558 // Start out with this token factor.
561 // Iterate through token factors. The TFs grows when new token factors are
563 for (unsigned i = 0; i < TFs.size(); ++i) {
566 // Check each of the operands.
567 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
568 SDOperand Op = TF->getOperand(i);
570 switch (Op.getOpcode()) {
571 case ISD::EntryToken:
572 // Entry tokens don't need to be added to the list. They are
577 case ISD::TokenFactor:
578 if ((CombinerAA || Op.hasOneUse()) &&
579 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
580 // Queue up for processing.
581 TFs.push_back(Op.Val);
582 // Clean up in case the token factor is removed.
583 AddToWorkList(Op.Val);
590 // Only add if not there prior.
591 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end())
600 // If we've change things around then replace token factor.
602 if (Ops.size() == 0) {
603 // The entry token is the only possible outcome.
604 Result = DAG.getEntryNode();
606 // New and improved token factor.
607 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
610 // Don't add users to work list.
611 return CombineTo(N, Result, false);
617 SDOperand DAGCombiner::visitADD(SDNode *N) {
618 SDOperand N0 = N->getOperand(0);
619 SDOperand N1 = N->getOperand(1);
620 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
621 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
622 MVT::ValueType VT = N0.getValueType();
624 // fold (add c1, c2) -> c1+c2
626 return DAG.getNode(ISD::ADD, VT, N0, N1);
627 // canonicalize constant to RHS
629 return DAG.getNode(ISD::ADD, VT, N1, N0);
630 // fold (add x, 0) -> x
631 if (N1C && N1C->isNullValue())
633 // fold ((c1-A)+c2) -> (c1+c2)-A
634 if (N1C && N0.getOpcode() == ISD::SUB)
635 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
636 return DAG.getNode(ISD::SUB, VT,
637 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
640 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
643 // fold ((0-A) + B) -> B-A
644 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
645 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
646 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
647 // fold (A + (0-B)) -> A-B
648 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
649 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
650 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
651 // fold (A+(B-A)) -> B
652 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
653 return N1.getOperand(0);
655 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
656 return SDOperand(N, 0);
658 // fold (a+b) -> (a|b) iff a and b share no bits.
659 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
660 uint64_t LHSZero, LHSOne;
661 uint64_t RHSZero, RHSOne;
662 uint64_t Mask = MVT::getIntVTBitMask(VT);
663 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
665 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
667 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
668 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
669 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
670 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
671 return DAG.getNode(ISD::OR, VT, N0, N1);
678 SDOperand DAGCombiner::visitSUB(SDNode *N) {
679 SDOperand N0 = N->getOperand(0);
680 SDOperand N1 = N->getOperand(1);
681 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
682 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
683 MVT::ValueType VT = N0.getValueType();
685 // fold (sub x, x) -> 0
687 return DAG.getConstant(0, N->getValueType(0));
688 // fold (sub c1, c2) -> c1-c2
690 return DAG.getNode(ISD::SUB, VT, N0, N1);
691 // fold (sub x, c) -> (add x, -c)
693 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
695 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
696 return N0.getOperand(1);
698 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
699 return N0.getOperand(0);
703 SDOperand DAGCombiner::visitMUL(SDNode *N) {
704 SDOperand N0 = N->getOperand(0);
705 SDOperand N1 = N->getOperand(1);
706 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
707 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
708 MVT::ValueType VT = N0.getValueType();
710 // fold (mul c1, c2) -> c1*c2
712 return DAG.getNode(ISD::MUL, VT, N0, N1);
713 // canonicalize constant to RHS
715 return DAG.getNode(ISD::MUL, VT, N1, N0);
716 // fold (mul x, 0) -> 0
717 if (N1C && N1C->isNullValue())
719 // fold (mul x, -1) -> 0-x
720 if (N1C && N1C->isAllOnesValue())
721 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
722 // fold (mul x, (1 << c)) -> x << c
723 if (N1C && isPowerOf2_64(N1C->getValue()))
724 return DAG.getNode(ISD::SHL, VT, N0,
725 DAG.getConstant(Log2_64(N1C->getValue()),
726 TLI.getShiftAmountTy()));
727 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
728 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
729 // FIXME: If the input is something that is easily negated (e.g. a
730 // single-use add), we should put the negate there.
731 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
732 DAG.getNode(ISD::SHL, VT, N0,
733 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
734 TLI.getShiftAmountTy())));
737 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
738 if (N1C && N0.getOpcode() == ISD::SHL &&
739 isa<ConstantSDNode>(N0.getOperand(1))) {
740 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
741 AddToWorkList(C3.Val);
742 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
745 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
748 SDOperand Sh(0,0), Y(0,0);
749 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
750 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
751 N0.Val->hasOneUse()) {
753 } else if (N1.getOpcode() == ISD::SHL &&
754 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
758 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
759 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
762 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
763 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
764 isa<ConstantSDNode>(N0.getOperand(1))) {
765 return DAG.getNode(ISD::ADD, VT,
766 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
767 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
771 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
777 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
778 SDOperand N0 = N->getOperand(0);
779 SDOperand N1 = N->getOperand(1);
780 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
781 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
782 MVT::ValueType VT = N->getValueType(0);
784 // fold (sdiv c1, c2) -> c1/c2
785 if (N0C && N1C && !N1C->isNullValue())
786 return DAG.getNode(ISD::SDIV, VT, N0, N1);
787 // fold (sdiv X, 1) -> X
788 if (N1C && N1C->getSignExtended() == 1LL)
790 // fold (sdiv X, -1) -> 0-X
791 if (N1C && N1C->isAllOnesValue())
792 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
793 // If we know the sign bits of both operands are zero, strength reduce to a
794 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
795 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
796 if (TLI.MaskedValueIsZero(N1, SignBit) &&
797 TLI.MaskedValueIsZero(N0, SignBit))
798 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
799 // fold (sdiv X, pow2) -> simple ops after legalize
800 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
801 (isPowerOf2_64(N1C->getSignExtended()) ||
802 isPowerOf2_64(-N1C->getSignExtended()))) {
803 // If dividing by powers of two is cheap, then don't perform the following
805 if (TLI.isPow2DivCheap())
807 int64_t pow2 = N1C->getSignExtended();
808 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
809 unsigned lg2 = Log2_64(abs2);
810 // Splat the sign bit into the register
811 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
812 DAG.getConstant(MVT::getSizeInBits(VT)-1,
813 TLI.getShiftAmountTy()));
814 AddToWorkList(SGN.Val);
815 // Add (N0 < 0) ? abs2 - 1 : 0;
816 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
817 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
818 TLI.getShiftAmountTy()));
819 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
820 AddToWorkList(SRL.Val);
821 AddToWorkList(ADD.Val); // Divide by pow2
822 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
823 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
824 // If we're dividing by a positive value, we're done. Otherwise, we must
825 // negate the result.
828 AddToWorkList(SRA.Val);
829 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
831 // if integer divide is expensive and we satisfy the requirements, emit an
832 // alternate sequence.
833 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
834 !TLI.isIntDivCheap()) {
835 SDOperand Op = BuildSDIV(N);
836 if (Op.Val) return Op;
841 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
842 SDOperand N0 = N->getOperand(0);
843 SDOperand N1 = N->getOperand(1);
844 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
845 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
846 MVT::ValueType VT = N->getValueType(0);
848 // fold (udiv c1, c2) -> c1/c2
849 if (N0C && N1C && !N1C->isNullValue())
850 return DAG.getNode(ISD::UDIV, VT, N0, N1);
851 // fold (udiv x, (1 << c)) -> x >>u c
852 if (N1C && isPowerOf2_64(N1C->getValue()))
853 return DAG.getNode(ISD::SRL, VT, N0,
854 DAG.getConstant(Log2_64(N1C->getValue()),
855 TLI.getShiftAmountTy()));
856 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
857 if (N1.getOpcode() == ISD::SHL) {
858 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
859 if (isPowerOf2_64(SHC->getValue())) {
860 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
861 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
862 DAG.getConstant(Log2_64(SHC->getValue()),
864 AddToWorkList(Add.Val);
865 return DAG.getNode(ISD::SRL, VT, N0, Add);
869 // fold (udiv x, c) -> alternate
870 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
871 SDOperand Op = BuildUDIV(N);
872 if (Op.Val) return Op;
877 SDOperand DAGCombiner::visitSREM(SDNode *N) {
878 SDOperand N0 = N->getOperand(0);
879 SDOperand N1 = N->getOperand(1);
880 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
881 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
882 MVT::ValueType VT = N->getValueType(0);
884 // fold (srem c1, c2) -> c1%c2
885 if (N0C && N1C && !N1C->isNullValue())
886 return DAG.getNode(ISD::SREM, VT, N0, N1);
887 // If we know the sign bits of both operands are zero, strength reduce to a
888 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
889 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
890 if (TLI.MaskedValueIsZero(N1, SignBit) &&
891 TLI.MaskedValueIsZero(N0, SignBit))
892 return DAG.getNode(ISD::UREM, VT, N0, N1);
894 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
895 // the remainder operation.
896 if (N1C && !N1C->isNullValue()) {
897 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
898 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
899 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
900 AddToWorkList(Div.Val);
901 AddToWorkList(Mul.Val);
908 SDOperand DAGCombiner::visitUREM(SDNode *N) {
909 SDOperand N0 = N->getOperand(0);
910 SDOperand N1 = N->getOperand(1);
911 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
912 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
913 MVT::ValueType VT = N->getValueType(0);
915 // fold (urem c1, c2) -> c1%c2
916 if (N0C && N1C && !N1C->isNullValue())
917 return DAG.getNode(ISD::UREM, VT, N0, N1);
918 // fold (urem x, pow2) -> (and x, pow2-1)
919 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
920 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
921 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
922 if (N1.getOpcode() == ISD::SHL) {
923 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
924 if (isPowerOf2_64(SHC->getValue())) {
925 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
926 AddToWorkList(Add.Val);
927 return DAG.getNode(ISD::AND, VT, N0, Add);
932 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
933 // the remainder operation.
934 if (N1C && !N1C->isNullValue()) {
935 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
936 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
937 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
938 AddToWorkList(Div.Val);
939 AddToWorkList(Mul.Val);
946 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
947 SDOperand N0 = N->getOperand(0);
948 SDOperand N1 = N->getOperand(1);
949 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
951 // fold (mulhs x, 0) -> 0
952 if (N1C && N1C->isNullValue())
954 // fold (mulhs x, 1) -> (sra x, size(x)-1)
955 if (N1C && N1C->getValue() == 1)
956 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
957 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
958 TLI.getShiftAmountTy()));
962 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
963 SDOperand N0 = N->getOperand(0);
964 SDOperand N1 = N->getOperand(1);
965 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
967 // fold (mulhu x, 0) -> 0
968 if (N1C && N1C->isNullValue())
970 // fold (mulhu x, 1) -> 0
971 if (N1C && N1C->getValue() == 1)
972 return DAG.getConstant(0, N0.getValueType());
976 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
977 /// two operands of the same opcode, try to simplify it.
978 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
979 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
980 MVT::ValueType VT = N0.getValueType();
981 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
983 // For each of OP in AND/OR/XOR:
984 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
985 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
986 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
987 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
988 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
989 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
990 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
991 SDOperand ORNode = DAG.getNode(N->getOpcode(),
992 N0.getOperand(0).getValueType(),
993 N0.getOperand(0), N1.getOperand(0));
994 AddToWorkList(ORNode.Val);
995 return DAG.getNode(N0.getOpcode(), VT, ORNode);
998 // For each of OP in SHL/SRL/SRA/AND...
999 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1000 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1001 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1002 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1003 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1004 N0.getOperand(1) == N1.getOperand(1)) {
1005 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1006 N0.getOperand(0).getValueType(),
1007 N0.getOperand(0), N1.getOperand(0));
1008 AddToWorkList(ORNode.Val);
1009 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1015 SDOperand DAGCombiner::visitAND(SDNode *N) {
1016 SDOperand N0 = N->getOperand(0);
1017 SDOperand N1 = N->getOperand(1);
1018 SDOperand LL, LR, RL, RR, CC0, CC1;
1019 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1020 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1021 MVT::ValueType VT = N1.getValueType();
1022 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1024 // fold (and c1, c2) -> c1&c2
1026 return DAG.getNode(ISD::AND, VT, N0, N1);
1027 // canonicalize constant to RHS
1029 return DAG.getNode(ISD::AND, VT, N1, N0);
1030 // fold (and x, -1) -> x
1031 if (N1C && N1C->isAllOnesValue())
1033 // if (and x, c) is known to be zero, return 0
1034 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1035 return DAG.getConstant(0, VT);
1037 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1040 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1041 if (N1C && N0.getOpcode() == ISD::OR)
1042 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1043 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1045 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1046 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1047 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1048 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1049 ~N1C->getValue() & InMask)) {
1050 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1053 // Replace uses of the AND with uses of the Zero extend node.
1056 // We actually want to replace all uses of the any_extend with the
1057 // zero_extend, to avoid duplicating things. This will later cause this
1058 // AND to be folded.
1059 CombineTo(N0.Val, Zext);
1060 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1063 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1064 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1065 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1066 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1068 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1069 MVT::isInteger(LL.getValueType())) {
1070 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1071 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1072 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1073 AddToWorkList(ORNode.Val);
1074 return DAG.getSetCC(VT, ORNode, LR, Op1);
1076 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1077 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1078 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1079 AddToWorkList(ANDNode.Val);
1080 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1082 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1083 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1084 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1085 AddToWorkList(ORNode.Val);
1086 return DAG.getSetCC(VT, ORNode, LR, Op1);
1089 // canonicalize equivalent to ll == rl
1090 if (LL == RR && LR == RL) {
1091 Op1 = ISD::getSetCCSwappedOperands(Op1);
1094 if (LL == RL && LR == RR) {
1095 bool isInteger = MVT::isInteger(LL.getValueType());
1096 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1097 if (Result != ISD::SETCC_INVALID)
1098 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1102 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1103 if (N0.getOpcode() == N1.getOpcode()) {
1104 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1105 if (Tmp.Val) return Tmp;
1108 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1109 // fold (and (sra)) -> (and (srl)) when possible.
1110 if (!MVT::isVector(VT) &&
1111 SimplifyDemandedBits(SDOperand(N, 0)))
1112 return SDOperand(N, 0);
1113 // fold (zext_inreg (extload x)) -> (zextload x)
1114 if (ISD::isEXTLoad(N0.Val)) {
1115 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1116 MVT::ValueType EVT = LN0->getLoadedVT();
1117 // If we zero all the possible extended bits, then we can turn this into
1118 // a zextload if we are running before legalize or the operation is legal.
1119 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1120 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1121 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1122 LN0->getBasePtr(), LN0->getSrcValue(),
1123 LN0->getSrcValueOffset(), EVT);
1125 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1126 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1129 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1130 if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
1131 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1132 MVT::ValueType EVT = LN0->getLoadedVT();
1133 // If we zero all the possible extended bits, then we can turn this into
1134 // a zextload if we are running before legalize or the operation is legal.
1135 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1136 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1137 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1138 LN0->getBasePtr(), LN0->getSrcValue(),
1139 LN0->getSrcValueOffset(), EVT);
1141 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1142 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1146 // fold (and (load x), 255) -> (zextload x, i8)
1147 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1148 if (N1C && N0.getOpcode() == ISD::LOAD) {
1149 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1150 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1152 MVT::ValueType EVT, LoadedVT;
1153 if (N1C->getValue() == 255)
1155 else if (N1C->getValue() == 65535)
1157 else if (N1C->getValue() == ~0U)
1162 LoadedVT = LN0->getLoadedVT();
1163 if (EVT != MVT::Other && LoadedVT > EVT &&
1164 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1165 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1166 // For big endian targets, we need to add an offset to the pointer to
1167 // load the correct bytes. For little endian systems, we merely need to
1168 // read fewer bytes from the same pointer.
1170 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1171 SDOperand NewPtr = LN0->getBasePtr();
1172 if (!TLI.isLittleEndian())
1173 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1174 DAG.getConstant(PtrOff, PtrType));
1175 AddToWorkList(NewPtr.Val);
1177 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1178 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
1180 CombineTo(N0.Val, Load, Load.getValue(1));
1181 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1189 SDOperand DAGCombiner::visitOR(SDNode *N) {
1190 SDOperand N0 = N->getOperand(0);
1191 SDOperand N1 = N->getOperand(1);
1192 SDOperand LL, LR, RL, RR, CC0, CC1;
1193 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1194 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1195 MVT::ValueType VT = N1.getValueType();
1196 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1198 // fold (or c1, c2) -> c1|c2
1200 return DAG.getNode(ISD::OR, VT, N0, N1);
1201 // canonicalize constant to RHS
1203 return DAG.getNode(ISD::OR, VT, N1, N0);
1204 // fold (or x, 0) -> x
1205 if (N1C && N1C->isNullValue())
1207 // fold (or x, -1) -> -1
1208 if (N1C && N1C->isAllOnesValue())
1210 // fold (or x, c) -> c iff (x & ~c) == 0
1212 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1215 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1218 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1219 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1220 isa<ConstantSDNode>(N0.getOperand(1))) {
1221 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1222 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1224 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1226 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1227 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1228 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1229 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1231 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1232 MVT::isInteger(LL.getValueType())) {
1233 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1234 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1235 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1236 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1237 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1238 AddToWorkList(ORNode.Val);
1239 return DAG.getSetCC(VT, ORNode, LR, Op1);
1241 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1242 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1243 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1244 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1245 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1246 AddToWorkList(ANDNode.Val);
1247 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1250 // canonicalize equivalent to ll == rl
1251 if (LL == RR && LR == RL) {
1252 Op1 = ISD::getSetCCSwappedOperands(Op1);
1255 if (LL == RL && LR == RR) {
1256 bool isInteger = MVT::isInteger(LL.getValueType());
1257 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1258 if (Result != ISD::SETCC_INVALID)
1259 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1263 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1264 if (N0.getOpcode() == N1.getOpcode()) {
1265 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1266 if (Tmp.Val) return Tmp;
1269 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1270 if (N0.getOpcode() == ISD::AND &&
1271 N1.getOpcode() == ISD::AND &&
1272 N0.getOperand(1).getOpcode() == ISD::Constant &&
1273 N1.getOperand(1).getOpcode() == ISD::Constant &&
1274 // Don't increase # computations.
1275 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1276 // We can only do this xform if we know that bits from X that are set in C2
1277 // but not in C1 are already zero. Likewise for Y.
1278 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1279 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1281 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1282 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1283 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1284 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1289 // See if this is some rotate idiom.
1290 if (SDNode *Rot = MatchRotate(N0, N1))
1291 return SDOperand(Rot, 0);
1297 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1298 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1299 if (Op.getOpcode() == ISD::AND) {
1300 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1301 Mask = Op.getOperand(1);
1302 Op = Op.getOperand(0);
1308 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1316 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1317 // idioms for rotate, and if the target supports rotation instructions, generate
1319 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1320 // Must be a legal type. Expanded an promoted things won't work with rotates.
1321 MVT::ValueType VT = LHS.getValueType();
1322 if (!TLI.isTypeLegal(VT)) return 0;
1324 // The target must have at least one rotate flavor.
1325 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1326 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1327 if (!HasROTL && !HasROTR) return 0;
1329 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1330 SDOperand LHSShift; // The shift.
1331 SDOperand LHSMask; // AND value if any.
1332 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1333 return 0; // Not part of a rotate.
1335 SDOperand RHSShift; // The shift.
1336 SDOperand RHSMask; // AND value if any.
1337 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1338 return 0; // Not part of a rotate.
1340 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1341 return 0; // Not shifting the same value.
1343 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1344 return 0; // Shifts must disagree.
1346 // Canonicalize shl to left side in a shl/srl pair.
1347 if (RHSShift.getOpcode() == ISD::SHL) {
1348 std::swap(LHS, RHS);
1349 std::swap(LHSShift, RHSShift);
1350 std::swap(LHSMask , RHSMask );
1353 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1355 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1356 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1357 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
1358 RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
1359 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue();
1360 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue();
1361 if ((LShVal + RShVal) != OpSizeInBits)
1366 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1367 LHSShift.getOperand(1));
1369 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1370 RHSShift.getOperand(1));
1372 // If there is an AND of either shifted operand, apply it to the result.
1373 if (LHSMask.Val || RHSMask.Val) {
1374 uint64_t Mask = MVT::getIntVTBitMask(VT);
1377 uint64_t RHSBits = (1ULL << LShVal)-1;
1378 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1381 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1382 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1385 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1391 // If there is a mask here, and we have a variable shift, we can't be sure
1392 // that we're masking out the right stuff.
1393 if (LHSMask.Val || RHSMask.Val)
1396 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1397 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1398 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1399 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
1400 if (ConstantSDNode *SUBC =
1401 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) {
1402 if (SUBC->getValue() == OpSizeInBits)
1404 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1405 LHSShift.getOperand(1)).Val;
1407 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1408 LHSShift.getOperand(1)).Val;
1412 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1413 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1414 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1415 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
1416 if (ConstantSDNode *SUBC =
1417 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) {
1418 if (SUBC->getValue() == OpSizeInBits)
1420 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1421 LHSShift.getOperand(1)).Val;
1423 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1424 RHSShift.getOperand(1)).Val;
1432 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1433 SDOperand N0 = N->getOperand(0);
1434 SDOperand N1 = N->getOperand(1);
1435 SDOperand LHS, RHS, CC;
1436 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1437 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1438 MVT::ValueType VT = N0.getValueType();
1440 // fold (xor c1, c2) -> c1^c2
1442 return DAG.getNode(ISD::XOR, VT, N0, N1);
1443 // canonicalize constant to RHS
1445 return DAG.getNode(ISD::XOR, VT, N1, N0);
1446 // fold (xor x, 0) -> x
1447 if (N1C && N1C->isNullValue())
1450 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1453 // fold !(x cc y) -> (x !cc y)
1454 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1455 bool isInt = MVT::isInteger(LHS.getValueType());
1456 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1458 if (N0.getOpcode() == ISD::SETCC)
1459 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1460 if (N0.getOpcode() == ISD::SELECT_CC)
1461 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1462 assert(0 && "Unhandled SetCC Equivalent!");
1465 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1466 if (N1C && N1C->getValue() == 1 &&
1467 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1468 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1469 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1470 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1471 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1472 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1473 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1474 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1477 // fold !(x or y) -> (!x and !y) iff x or y are constants
1478 if (N1C && N1C->isAllOnesValue() &&
1479 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1480 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1481 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1482 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1483 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1484 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1485 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1486 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1489 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1490 if (N1C && N0.getOpcode() == ISD::XOR) {
1491 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1492 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1494 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1495 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1497 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1498 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1500 // fold (xor x, x) -> 0
1502 if (!MVT::isVector(VT)) {
1503 return DAG.getConstant(0, VT);
1504 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1505 // Produce a vector of zeros.
1506 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1507 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1508 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1512 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1513 if (N0.getOpcode() == N1.getOpcode()) {
1514 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1515 if (Tmp.Val) return Tmp;
1518 // Simplify the expression using non-local knowledge.
1519 if (!MVT::isVector(VT) &&
1520 SimplifyDemandedBits(SDOperand(N, 0)))
1521 return SDOperand(N, 0);
1526 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1527 SDOperand N0 = N->getOperand(0);
1528 SDOperand N1 = N->getOperand(1);
1529 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1530 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1531 MVT::ValueType VT = N0.getValueType();
1532 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1534 // fold (shl c1, c2) -> c1<<c2
1536 return DAG.getNode(ISD::SHL, VT, N0, N1);
1537 // fold (shl 0, x) -> 0
1538 if (N0C && N0C->isNullValue())
1540 // fold (shl x, c >= size(x)) -> undef
1541 if (N1C && N1C->getValue() >= OpSizeInBits)
1542 return DAG.getNode(ISD::UNDEF, VT);
1543 // fold (shl x, 0) -> x
1544 if (N1C && N1C->isNullValue())
1546 // if (shl x, c) is known to be zero, return 0
1547 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1548 return DAG.getConstant(0, VT);
1549 if (SimplifyDemandedBits(SDOperand(N, 0)))
1550 return SDOperand(N, 0);
1551 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1552 if (N1C && N0.getOpcode() == ISD::SHL &&
1553 N0.getOperand(1).getOpcode() == ISD::Constant) {
1554 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1555 uint64_t c2 = N1C->getValue();
1556 if (c1 + c2 > OpSizeInBits)
1557 return DAG.getConstant(0, VT);
1558 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1559 DAG.getConstant(c1 + c2, N1.getValueType()));
1561 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1562 // (srl (and x, -1 << c1), c1-c2)
1563 if (N1C && N0.getOpcode() == ISD::SRL &&
1564 N0.getOperand(1).getOpcode() == ISD::Constant) {
1565 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1566 uint64_t c2 = N1C->getValue();
1567 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1568 DAG.getConstant(~0ULL << c1, VT));
1570 return DAG.getNode(ISD::SHL, VT, Mask,
1571 DAG.getConstant(c2-c1, N1.getValueType()));
1573 return DAG.getNode(ISD::SRL, VT, Mask,
1574 DAG.getConstant(c1-c2, N1.getValueType()));
1576 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1577 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1578 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1579 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1580 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
1581 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1582 isa<ConstantSDNode>(N0.getOperand(1))) {
1583 return DAG.getNode(ISD::ADD, VT,
1584 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
1585 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
1590 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1591 SDOperand N0 = N->getOperand(0);
1592 SDOperand N1 = N->getOperand(1);
1593 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1594 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1595 MVT::ValueType VT = N0.getValueType();
1597 // fold (sra c1, c2) -> c1>>c2
1599 return DAG.getNode(ISD::SRA, VT, N0, N1);
1600 // fold (sra 0, x) -> 0
1601 if (N0C && N0C->isNullValue())
1603 // fold (sra -1, x) -> -1
1604 if (N0C && N0C->isAllOnesValue())
1606 // fold (sra x, c >= size(x)) -> undef
1607 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1608 return DAG.getNode(ISD::UNDEF, VT);
1609 // fold (sra x, 0) -> x
1610 if (N1C && N1C->isNullValue())
1612 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1614 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1615 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1618 default: EVT = MVT::Other; break;
1619 case 1: EVT = MVT::i1; break;
1620 case 8: EVT = MVT::i8; break;
1621 case 16: EVT = MVT::i16; break;
1622 case 32: EVT = MVT::i32; break;
1624 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1625 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1626 DAG.getValueType(EVT));
1629 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1630 if (N1C && N0.getOpcode() == ISD::SRA) {
1631 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1632 unsigned Sum = N1C->getValue() + C1->getValue();
1633 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1634 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1635 DAG.getConstant(Sum, N1C->getValueType(0)));
1639 // Simplify, based on bits shifted out of the LHS.
1640 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1641 return SDOperand(N, 0);
1644 // If the sign bit is known to be zero, switch this to a SRL.
1645 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1646 return DAG.getNode(ISD::SRL, VT, N0, N1);
1650 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1651 SDOperand N0 = N->getOperand(0);
1652 SDOperand N1 = N->getOperand(1);
1653 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1654 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1655 MVT::ValueType VT = N0.getValueType();
1656 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1658 // fold (srl c1, c2) -> c1 >>u c2
1660 return DAG.getNode(ISD::SRL, VT, N0, N1);
1661 // fold (srl 0, x) -> 0
1662 if (N0C && N0C->isNullValue())
1664 // fold (srl x, c >= size(x)) -> undef
1665 if (N1C && N1C->getValue() >= OpSizeInBits)
1666 return DAG.getNode(ISD::UNDEF, VT);
1667 // fold (srl x, 0) -> x
1668 if (N1C && N1C->isNullValue())
1670 // if (srl x, c) is known to be zero, return 0
1671 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1672 return DAG.getConstant(0, VT);
1673 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1674 if (N1C && N0.getOpcode() == ISD::SRL &&
1675 N0.getOperand(1).getOpcode() == ISD::Constant) {
1676 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1677 uint64_t c2 = N1C->getValue();
1678 if (c1 + c2 > OpSizeInBits)
1679 return DAG.getConstant(0, VT);
1680 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1681 DAG.getConstant(c1 + c2, N1.getValueType()));
1684 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1685 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1686 // Shifting in all undef bits?
1687 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1688 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1689 return DAG.getNode(ISD::UNDEF, VT);
1691 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1692 AddToWorkList(SmallShift.Val);
1693 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1696 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
1697 // bit, which is unmodified by sra.
1698 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
1699 if (N0.getOpcode() == ISD::SRA)
1700 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
1703 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1704 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1705 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1706 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1707 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1709 // If any of the input bits are KnownOne, then the input couldn't be all
1710 // zeros, thus the result of the srl will always be zero.
1711 if (KnownOne) return DAG.getConstant(0, VT);
1713 // If all of the bits input the to ctlz node are known to be zero, then
1714 // the result of the ctlz is "32" and the result of the shift is one.
1715 uint64_t UnknownBits = ~KnownZero & Mask;
1716 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1718 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1719 if ((UnknownBits & (UnknownBits-1)) == 0) {
1720 // Okay, we know that only that the single bit specified by UnknownBits
1721 // could be set on input to the CTLZ node. If this bit is set, the SRL
1722 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1723 // to an SRL,XOR pair, which is likely to simplify more.
1724 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1725 SDOperand Op = N0.getOperand(0);
1727 Op = DAG.getNode(ISD::SRL, VT, Op,
1728 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1729 AddToWorkList(Op.Val);
1731 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1738 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1739 SDOperand N0 = N->getOperand(0);
1740 MVT::ValueType VT = N->getValueType(0);
1742 // fold (ctlz c1) -> c2
1743 if (isa<ConstantSDNode>(N0))
1744 return DAG.getNode(ISD::CTLZ, VT, N0);
1748 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1749 SDOperand N0 = N->getOperand(0);
1750 MVT::ValueType VT = N->getValueType(0);
1752 // fold (cttz c1) -> c2
1753 if (isa<ConstantSDNode>(N0))
1754 return DAG.getNode(ISD::CTTZ, VT, N0);
1758 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1759 SDOperand N0 = N->getOperand(0);
1760 MVT::ValueType VT = N->getValueType(0);
1762 // fold (ctpop c1) -> c2
1763 if (isa<ConstantSDNode>(N0))
1764 return DAG.getNode(ISD::CTPOP, VT, N0);
1768 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1769 SDOperand N0 = N->getOperand(0);
1770 SDOperand N1 = N->getOperand(1);
1771 SDOperand N2 = N->getOperand(2);
1772 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1773 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1774 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1775 MVT::ValueType VT = N->getValueType(0);
1777 // fold select C, X, X -> X
1780 // fold select true, X, Y -> X
1781 if (N0C && !N0C->isNullValue())
1783 // fold select false, X, Y -> Y
1784 if (N0C && N0C->isNullValue())
1786 // fold select C, 1, X -> C | X
1787 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1788 return DAG.getNode(ISD::OR, VT, N0, N2);
1789 // fold select C, 0, X -> ~C & X
1790 // FIXME: this should check for C type == X type, not i1?
1791 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1792 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1793 AddToWorkList(XORNode.Val);
1794 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1796 // fold select C, X, 1 -> ~C | X
1797 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1798 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1799 AddToWorkList(XORNode.Val);
1800 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1802 // fold select C, X, 0 -> C & X
1803 // FIXME: this should check for C type == X type, not i1?
1804 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1805 return DAG.getNode(ISD::AND, VT, N0, N1);
1806 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1807 if (MVT::i1 == VT && N0 == N1)
1808 return DAG.getNode(ISD::OR, VT, N0, N2);
1809 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1810 if (MVT::i1 == VT && N0 == N2)
1811 return DAG.getNode(ISD::AND, VT, N0, N1);
1813 // If we can fold this based on the true/false value, do so.
1814 if (SimplifySelectOps(N, N1, N2))
1815 return SDOperand(N, 0); // Don't revisit N.
1817 // fold selects based on a setcc into other things, such as min/max/abs
1818 if (N0.getOpcode() == ISD::SETCC)
1820 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1821 // having to say they don't support SELECT_CC on every type the DAG knows
1822 // about, since there is no way to mark an opcode illegal at all value types
1823 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1824 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1825 N1, N2, N0.getOperand(2));
1827 return SimplifySelect(N0, N1, N2);
1831 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1832 SDOperand N0 = N->getOperand(0);
1833 SDOperand N1 = N->getOperand(1);
1834 SDOperand N2 = N->getOperand(2);
1835 SDOperand N3 = N->getOperand(3);
1836 SDOperand N4 = N->getOperand(4);
1837 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1838 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1839 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1840 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1842 // fold select_cc lhs, rhs, x, x, cc -> x
1846 // Determine if the condition we're dealing with is constant
1847 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1849 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
1850 if (SCCC->getValue())
1851 return N2; // cond always true -> true val
1853 return N3; // cond always false -> false val
1856 // Fold to a simpler select_cc
1857 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1858 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
1859 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
1862 // If we can fold this based on the true/false value, do so.
1863 if (SimplifySelectOps(N, N2, N3))
1864 return SDOperand(N, 0); // Don't revisit N.
1866 // fold select_cc into other things, such as min/max/abs
1867 return SimplifySelectCC(N0, N1, N2, N3, CC);
1870 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1871 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1872 cast<CondCodeSDNode>(N->getOperand(2))->get());
1875 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1876 SDOperand N0 = N->getOperand(0);
1877 MVT::ValueType VT = N->getValueType(0);
1879 // fold (sext c1) -> c1
1880 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1881 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1883 // fold (sext (sext x)) -> (sext x)
1884 // fold (sext (aext x)) -> (sext x)
1885 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1886 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1888 // fold (sext (truncate x)) -> (sextinreg x).
1889 if (N0.getOpcode() == ISD::TRUNCATE &&
1890 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
1891 N0.getValueType()))) {
1892 SDOperand Op = N0.getOperand(0);
1893 if (Op.getValueType() < VT) {
1894 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1895 } else if (Op.getValueType() > VT) {
1896 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1898 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
1899 DAG.getValueType(N0.getValueType()));
1902 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1903 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1904 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
1905 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1906 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1907 LN0->getBasePtr(), LN0->getSrcValue(),
1908 LN0->getSrcValueOffset(),
1910 CombineTo(N, ExtLoad);
1911 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1912 ExtLoad.getValue(1));
1913 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1916 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1917 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1918 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
1919 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1920 MVT::ValueType EVT = LN0->getLoadedVT();
1921 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1922 LN0->getBasePtr(), LN0->getSrcValue(),
1923 LN0->getSrcValueOffset(), EVT);
1924 CombineTo(N, ExtLoad);
1925 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1926 ExtLoad.getValue(1));
1927 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1933 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1934 SDOperand N0 = N->getOperand(0);
1935 MVT::ValueType VT = N->getValueType(0);
1937 // fold (zext c1) -> c1
1938 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1939 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1940 // fold (zext (zext x)) -> (zext x)
1941 // fold (zext (aext x)) -> (zext x)
1942 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1943 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1945 // fold (zext (truncate x)) -> (and x, mask)
1946 if (N0.getOpcode() == ISD::TRUNCATE &&
1947 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
1948 SDOperand Op = N0.getOperand(0);
1949 if (Op.getValueType() < VT) {
1950 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1951 } else if (Op.getValueType() > VT) {
1952 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1954 return DAG.getZeroExtendInReg(Op, N0.getValueType());
1957 // fold (zext (and (trunc x), cst)) -> (and x, cst).
1958 if (N0.getOpcode() == ISD::AND &&
1959 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1960 N0.getOperand(1).getOpcode() == ISD::Constant) {
1961 SDOperand X = N0.getOperand(0).getOperand(0);
1962 if (X.getValueType() < VT) {
1963 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
1964 } else if (X.getValueType() > VT) {
1965 X = DAG.getNode(ISD::TRUNCATE, VT, X);
1967 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1968 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
1971 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1972 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1973 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
1974 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1975 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1976 LN0->getBasePtr(), LN0->getSrcValue(),
1977 LN0->getSrcValueOffset(),
1979 CombineTo(N, ExtLoad);
1980 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1981 ExtLoad.getValue(1));
1982 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1985 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1986 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1987 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
1988 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1989 MVT::ValueType EVT = LN0->getLoadedVT();
1990 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1991 LN0->getBasePtr(), LN0->getSrcValue(),
1992 LN0->getSrcValueOffset(), EVT);
1993 CombineTo(N, ExtLoad);
1994 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1995 ExtLoad.getValue(1));
1996 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2001 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2002 SDOperand N0 = N->getOperand(0);
2003 MVT::ValueType VT = N->getValueType(0);
2005 // fold (aext c1) -> c1
2006 if (isa<ConstantSDNode>(N0))
2007 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2008 // fold (aext (aext x)) -> (aext x)
2009 // fold (aext (zext x)) -> (zext x)
2010 // fold (aext (sext x)) -> (sext x)
2011 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2012 N0.getOpcode() == ISD::ZERO_EXTEND ||
2013 N0.getOpcode() == ISD::SIGN_EXTEND)
2014 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2016 // fold (aext (truncate x))
2017 if (N0.getOpcode() == ISD::TRUNCATE) {
2018 SDOperand TruncOp = N0.getOperand(0);
2019 if (TruncOp.getValueType() == VT)
2020 return TruncOp; // x iff x size == zext size.
2021 if (TruncOp.getValueType() > VT)
2022 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2023 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2026 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2027 if (N0.getOpcode() == ISD::AND &&
2028 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2029 N0.getOperand(1).getOpcode() == ISD::Constant) {
2030 SDOperand X = N0.getOperand(0).getOperand(0);
2031 if (X.getValueType() < VT) {
2032 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2033 } else if (X.getValueType() > VT) {
2034 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2036 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2037 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2040 // fold (aext (load x)) -> (aext (truncate (extload x)))
2041 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2042 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2043 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2044 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2045 LN0->getBasePtr(), LN0->getSrcValue(),
2046 LN0->getSrcValueOffset(),
2048 CombineTo(N, ExtLoad);
2049 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2050 ExtLoad.getValue(1));
2051 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2054 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2055 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2056 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2057 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) &&
2059 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2060 MVT::ValueType EVT = LN0->getLoadedVT();
2061 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2062 LN0->getChain(), LN0->getBasePtr(),
2064 LN0->getSrcValueOffset(), EVT);
2065 CombineTo(N, ExtLoad);
2066 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2067 ExtLoad.getValue(1));
2068 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2074 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2075 SDOperand N0 = N->getOperand(0);
2076 SDOperand N1 = N->getOperand(1);
2077 MVT::ValueType VT = N->getValueType(0);
2078 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2079 unsigned EVTBits = MVT::getSizeInBits(EVT);
2081 // fold (sext_in_reg c1) -> c1
2082 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2083 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2085 // If the input is already sign extended, just drop the extension.
2086 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2089 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2090 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2091 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2092 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2095 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
2096 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2097 return DAG.getZeroExtendInReg(N0, EVT);
2099 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2100 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2101 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2102 if (N0.getOpcode() == ISD::SRL) {
2103 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2104 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2105 // We can turn this into an SRA iff the input to the SRL is already sign
2107 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
2108 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2109 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2113 // fold (sext_inreg (extload x)) -> (sextload x)
2114 if (ISD::isEXTLoad(N0.Val) &&
2115 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2116 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2117 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2118 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2119 LN0->getBasePtr(), LN0->getSrcValue(),
2120 LN0->getSrcValueOffset(), EVT);
2121 CombineTo(N, ExtLoad);
2122 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2123 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2125 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2126 if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
2127 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2128 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2129 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2130 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2131 LN0->getBasePtr(), LN0->getSrcValue(),
2132 LN0->getSrcValueOffset(), EVT);
2133 CombineTo(N, ExtLoad);
2134 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2135 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2140 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2141 SDOperand N0 = N->getOperand(0);
2142 MVT::ValueType VT = N->getValueType(0);
2145 if (N0.getValueType() == N->getValueType(0))
2147 // fold (truncate c1) -> c1
2148 if (isa<ConstantSDNode>(N0))
2149 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2150 // fold (truncate (truncate x)) -> (truncate x)
2151 if (N0.getOpcode() == ISD::TRUNCATE)
2152 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2153 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2154 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2155 N0.getOpcode() == ISD::ANY_EXTEND) {
2156 if (N0.getValueType() < VT)
2157 // if the source is smaller than the dest, we still need an extend
2158 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2159 else if (N0.getValueType() > VT)
2160 // if the source is larger than the dest, than we just need the truncate
2161 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2163 // if the source and dest are the same type, we can drop both the extend
2165 return N0.getOperand(0);
2167 // fold (truncate (load x)) -> (smaller load x)
2168 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2169 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
2170 "Cannot truncate to larger type!");
2171 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2172 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2173 // For big endian targets, we need to add an offset to the pointer to load
2174 // the correct bytes. For little endian systems, we merely need to read
2175 // fewer bytes from the same pointer.
2177 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
2178 SDOperand NewPtr = TLI.isLittleEndian() ? LN0->getBasePtr() :
2179 DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2180 DAG.getConstant(PtrOff, PtrType));
2181 AddToWorkList(NewPtr.Val);
2182 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr,
2183 LN0->getSrcValue(), LN0->getSrcValueOffset());
2185 CombineTo(N0.Val, Load, Load.getValue(1));
2186 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2191 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2192 SDOperand N0 = N->getOperand(0);
2193 MVT::ValueType VT = N->getValueType(0);
2195 // If the input is a constant, let getNode() fold it.
2196 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2197 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2198 if (Res.Val != N) return Res;
2201 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2202 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2204 // fold (conv (load x)) -> (load (conv*)x)
2205 // FIXME: These xforms need to know that the resultant load doesn't need a
2206 // higher alignment than the original!
2207 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2208 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2209 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2210 LN0->getSrcValue(), LN0->getSrcValueOffset());
2212 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2220 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2221 SDOperand N0 = N->getOperand(0);
2222 MVT::ValueType VT = N->getValueType(0);
2224 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2225 // First check to see if this is all constant.
2226 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2227 VT == MVT::Vector) {
2228 bool isSimple = true;
2229 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2230 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2231 N0.getOperand(i).getOpcode() != ISD::Constant &&
2232 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2237 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2238 if (isSimple && !MVT::isVector(DestEltVT)) {
2239 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2246 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2247 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2248 /// destination element value type.
2249 SDOperand DAGCombiner::
2250 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2251 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2253 // If this is already the right type, we're done.
2254 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2256 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2257 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2259 // If this is a conversion of N elements of one type to N elements of another
2260 // type, convert each element. This handles FP<->INT cases.
2261 if (SrcBitSize == DstBitSize) {
2262 SmallVector<SDOperand, 8> Ops;
2263 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2264 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2265 AddToWorkList(Ops.back().Val);
2267 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2268 Ops.push_back(DAG.getValueType(DstEltVT));
2269 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2272 // Otherwise, we're growing or shrinking the elements. To avoid having to
2273 // handle annoying details of growing/shrinking FP values, we convert them to
2275 if (MVT::isFloatingPoint(SrcEltVT)) {
2276 // Convert the input float vector to a int vector where the elements are the
2278 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2279 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2280 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2284 // Now we know the input is an integer vector. If the output is a FP type,
2285 // convert to integer first, then to FP of the right size.
2286 if (MVT::isFloatingPoint(DstEltVT)) {
2287 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2288 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2289 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2291 // Next, convert to FP elements of the same size.
2292 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2295 // Okay, we know the src/dst types are both integers of differing types.
2296 // Handling growing first.
2297 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2298 if (SrcBitSize < DstBitSize) {
2299 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2301 SmallVector<SDOperand, 8> Ops;
2302 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2303 i += NumInputsPerOutput) {
2304 bool isLE = TLI.isLittleEndian();
2305 uint64_t NewBits = 0;
2306 bool EltIsUndef = true;
2307 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2308 // Shift the previously computed bits over.
2309 NewBits <<= SrcBitSize;
2310 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2311 if (Op.getOpcode() == ISD::UNDEF) continue;
2314 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2318 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2320 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2323 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2324 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2325 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2328 // Finally, this must be the case where we are shrinking elements: each input
2329 // turns into multiple outputs.
2330 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2331 SmallVector<SDOperand, 8> Ops;
2332 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2333 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2334 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2335 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2338 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2340 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2341 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2342 OpVal >>= DstBitSize;
2343 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2346 // For big endian targets, swap the order of the pieces of each element.
2347 if (!TLI.isLittleEndian())
2348 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2350 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2351 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2352 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2357 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2358 SDOperand N0 = N->getOperand(0);
2359 SDOperand N1 = N->getOperand(1);
2360 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2361 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2362 MVT::ValueType VT = N->getValueType(0);
2364 // fold (fadd c1, c2) -> c1+c2
2366 return DAG.getNode(ISD::FADD, VT, N0, N1);
2367 // canonicalize constant to RHS
2368 if (N0CFP && !N1CFP)
2369 return DAG.getNode(ISD::FADD, VT, N1, N0);
2370 // fold (A + (-B)) -> A-B
2371 if (N1.getOpcode() == ISD::FNEG)
2372 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2373 // fold ((-A) + B) -> B-A
2374 if (N0.getOpcode() == ISD::FNEG)
2375 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2379 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2380 SDOperand N0 = N->getOperand(0);
2381 SDOperand N1 = N->getOperand(1);
2382 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2383 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2384 MVT::ValueType VT = N->getValueType(0);
2386 // fold (fsub c1, c2) -> c1-c2
2388 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2389 // fold (A-(-B)) -> A+B
2390 if (N1.getOpcode() == ISD::FNEG)
2391 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2395 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2396 SDOperand N0 = N->getOperand(0);
2397 SDOperand N1 = N->getOperand(1);
2398 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2399 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2400 MVT::ValueType VT = N->getValueType(0);
2402 // fold (fmul c1, c2) -> c1*c2
2404 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2405 // canonicalize constant to RHS
2406 if (N0CFP && !N1CFP)
2407 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2408 // fold (fmul X, 2.0) -> (fadd X, X)
2409 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2410 return DAG.getNode(ISD::FADD, VT, N0, N0);
2414 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2415 SDOperand N0 = N->getOperand(0);
2416 SDOperand N1 = N->getOperand(1);
2417 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2418 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2419 MVT::ValueType VT = N->getValueType(0);
2421 // fold (fdiv c1, c2) -> c1/c2
2423 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2427 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2428 SDOperand N0 = N->getOperand(0);
2429 SDOperand N1 = N->getOperand(1);
2430 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2431 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2432 MVT::ValueType VT = N->getValueType(0);
2434 // fold (frem c1, c2) -> fmod(c1,c2)
2436 return DAG.getNode(ISD::FREM, VT, N0, N1);
2440 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2441 SDOperand N0 = N->getOperand(0);
2442 SDOperand N1 = N->getOperand(1);
2443 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2444 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2445 MVT::ValueType VT = N->getValueType(0);
2447 if (N0CFP && N1CFP) // Constant fold
2448 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2451 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2452 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2457 u.d = N1CFP->getValue();
2459 return DAG.getNode(ISD::FABS, VT, N0);
2461 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2464 // copysign(fabs(x), y) -> copysign(x, y)
2465 // copysign(fneg(x), y) -> copysign(x, y)
2466 // copysign(copysign(x,z), y) -> copysign(x, y)
2467 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2468 N0.getOpcode() == ISD::FCOPYSIGN)
2469 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2471 // copysign(x, abs(y)) -> abs(x)
2472 if (N1.getOpcode() == ISD::FABS)
2473 return DAG.getNode(ISD::FABS, VT, N0);
2475 // copysign(x, copysign(y,z)) -> copysign(x, z)
2476 if (N1.getOpcode() == ISD::FCOPYSIGN)
2477 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2479 // copysign(x, fp_extend(y)) -> copysign(x, y)
2480 // copysign(x, fp_round(y)) -> copysign(x, y)
2481 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2482 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2489 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2490 SDOperand N0 = N->getOperand(0);
2491 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2492 MVT::ValueType VT = N->getValueType(0);
2494 // fold (sint_to_fp c1) -> c1fp
2496 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2500 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2501 SDOperand N0 = N->getOperand(0);
2502 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2503 MVT::ValueType VT = N->getValueType(0);
2505 // fold (uint_to_fp c1) -> c1fp
2507 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2511 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2512 SDOperand N0 = N->getOperand(0);
2513 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2514 MVT::ValueType VT = N->getValueType(0);
2516 // fold (fp_to_sint c1fp) -> c1
2518 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2522 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2523 SDOperand N0 = N->getOperand(0);
2524 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2525 MVT::ValueType VT = N->getValueType(0);
2527 // fold (fp_to_uint c1fp) -> c1
2529 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2533 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2534 SDOperand N0 = N->getOperand(0);
2535 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2536 MVT::ValueType VT = N->getValueType(0);
2538 // fold (fp_round c1fp) -> c1fp
2540 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2542 // fold (fp_round (fp_extend x)) -> x
2543 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2544 return N0.getOperand(0);
2546 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2547 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2548 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2549 AddToWorkList(Tmp.Val);
2550 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2556 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2557 SDOperand N0 = N->getOperand(0);
2558 MVT::ValueType VT = N->getValueType(0);
2559 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2560 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2562 // fold (fp_round_inreg c1fp) -> c1fp
2564 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2565 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2570 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2571 SDOperand N0 = N->getOperand(0);
2572 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2573 MVT::ValueType VT = N->getValueType(0);
2575 // fold (fp_extend c1fp) -> c1fp
2577 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2579 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2580 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2581 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2582 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2583 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2584 LN0->getBasePtr(), LN0->getSrcValue(),
2585 LN0->getSrcValueOffset(),
2587 CombineTo(N, ExtLoad);
2588 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2589 ExtLoad.getValue(1));
2590 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2597 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2598 SDOperand N0 = N->getOperand(0);
2599 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2600 MVT::ValueType VT = N->getValueType(0);
2602 // fold (fneg c1) -> -c1
2604 return DAG.getNode(ISD::FNEG, VT, N0);
2605 // fold (fneg (sub x, y)) -> (sub y, x)
2606 if (N0.getOpcode() == ISD::SUB)
2607 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2608 // fold (fneg (fneg x)) -> x
2609 if (N0.getOpcode() == ISD::FNEG)
2610 return N0.getOperand(0);
2614 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2615 SDOperand N0 = N->getOperand(0);
2616 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2617 MVT::ValueType VT = N->getValueType(0);
2619 // fold (fabs c1) -> fabs(c1)
2621 return DAG.getNode(ISD::FABS, VT, N0);
2622 // fold (fabs (fabs x)) -> (fabs x)
2623 if (N0.getOpcode() == ISD::FABS)
2624 return N->getOperand(0);
2625 // fold (fabs (fneg x)) -> (fabs x)
2626 // fold (fabs (fcopysign x, y)) -> (fabs x)
2627 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2628 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2633 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2634 SDOperand Chain = N->getOperand(0);
2635 SDOperand N1 = N->getOperand(1);
2636 SDOperand N2 = N->getOperand(2);
2637 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2639 // never taken branch, fold to chain
2640 if (N1C && N1C->isNullValue())
2642 // unconditional branch
2643 if (N1C && N1C->getValue() == 1)
2644 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2645 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2647 if (N1.getOpcode() == ISD::SETCC &&
2648 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2649 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2650 N1.getOperand(0), N1.getOperand(1), N2);
2655 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2657 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2658 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2659 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2661 // Use SimplifySetCC to simplify SETCC's.
2662 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2663 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2665 // fold br_cc true, dest -> br dest (unconditional branch)
2666 if (SCCC && SCCC->getValue())
2667 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2669 // fold br_cc false, dest -> unconditional fall through
2670 if (SCCC && SCCC->isNullValue())
2671 return N->getOperand(0);
2672 // fold to a simpler setcc
2673 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2674 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2675 Simp.getOperand(2), Simp.getOperand(0),
2676 Simp.getOperand(1), N->getOperand(4));
2680 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2681 LoadSDNode *LD = cast<LoadSDNode>(N);
2682 SDOperand Chain = LD->getChain();
2683 SDOperand Ptr = LD->getBasePtr();
2685 // If there are no uses of the loaded value, change uses of the chain value
2686 // into uses of the chain input (i.e. delete the dead load).
2687 if (N->hasNUsesOfValue(0, 0))
2688 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2690 // If this load is directly stored, replace the load value with the stored
2692 // TODO: Handle store large -> read small portion.
2693 // TODO: Handle TRUNCSTORE/LOADEXT
2694 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
2695 if (ISD::isNON_TRUNCStore(Chain.Val)) {
2696 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
2697 if (PrevST->getBasePtr() == Ptr &&
2698 PrevST->getValue().getValueType() == N->getValueType(0))
2699 return CombineTo(N, Chain.getOperand(1), Chain);
2704 // Walk up chain skipping non-aliasing memory nodes.
2705 SDOperand BetterChain = FindBetterChain(N, Chain);
2707 // If there is a better chain.
2708 if (Chain != BetterChain) {
2711 // Replace the chain to void dependency.
2712 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
2713 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
2714 LD->getSrcValue(), LD->getSrcValueOffset());
2716 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
2717 LD->getValueType(0),
2718 BetterChain, Ptr, LD->getSrcValue(),
2719 LD->getSrcValueOffset(),
2723 // Create token factor to keep old chain connected.
2724 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
2725 Chain, ReplLoad.getValue(1));
2727 // Replace uses with load result and token factor. Don't add users
2729 return CombineTo(N, ReplLoad.getValue(0), Token, false);
2736 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2737 StoreSDNode *ST = cast<StoreSDNode>(N);
2738 SDOperand Chain = ST->getChain();
2739 SDOperand Value = ST->getValue();
2740 SDOperand Ptr = ST->getBasePtr();
2742 // FIXME - Switch over after StoreSDNode comes online.
2743 if (ST->isTruncatingStore()) {
2745 // Walk up chain skipping non-aliasing memory nodes.
2746 SDOperand BetterChain = FindBetterChain(N, Chain);
2748 // If there is a better chain.
2749 if (Chain != BetterChain) {
2750 // Replace the chain to avoid dependency.
2751 SDOperand ReplTStore =
2752 DAG.getTruncStore(BetterChain, Value, Ptr, ST->getSrcValue(),
2753 ST->getSrcValueOffset(), ST->getStoredVT());
2755 // Create token to keep both nodes around.
2757 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplTStore);
2759 // Don't add users to work list.
2760 return CombineTo(N, Token, false);
2767 // If this is a store that kills a previous store, remove the previous store.
2768 if (ISD::isNON_TRUNCStore(Chain.Val)) {
2769 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
2770 if (PrevST->getBasePtr() == Ptr &&
2771 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2772 // Make sure that these stores are the same value type:
2773 // FIXME: we really care that the second store is >= size of the first.
2774 Value.getValueType() == PrevST->getValue().getValueType()) {
2775 // Create a new store of Value that replaces both stores.
2776 if (PrevST->getValue() == Value) // Same value multiply stored.
2778 SDOperand NewStore = DAG.getStore(PrevST->getChain(), Value, Ptr,
2779 ST->getSrcValue(), ST->getSrcValueOffset());
2780 CombineTo(N, NewStore); // Nuke this store.
2781 CombineTo(Chain.Val, NewStore); // Nuke the previous store.
2782 return SDOperand(N, 0);
2786 // If this is a store of a bit convert, store the input value.
2787 // FIXME: This needs to know that the resultant store does not need a
2788 // higher alignment than the original.
2789 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
2790 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
2791 ST->getSrcValueOffset());
2795 // If the store ptr is a frame index and the frame index has a use of one
2796 // and this is a return block, then the store is redundant.
2797 if (Ptr.hasOneUse() && isa<FrameIndexSDNode>(Ptr) &&
2798 DAG.getRoot().getOpcode() == ISD::RET) {
2802 // Walk up chain skipping non-aliasing memory nodes.
2803 SDOperand BetterChain = FindBetterChain(N, Chain);
2805 // If there is a better chain.
2806 if (Chain != BetterChain) {
2807 // Replace the chain to avoid dependency.
2808 SDOperand ReplStore = DAG.getStore(BetterChain, Value, Ptr,
2809 ST->getSrcValue(), ST->getSrcValueOffset());
2810 // Create token to keep both nodes around.
2812 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
2814 // Don't add users to work list.
2815 return CombineTo(N, Token, false);
2822 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
2823 SDOperand InVec = N->getOperand(0);
2824 SDOperand InVal = N->getOperand(1);
2825 SDOperand EltNo = N->getOperand(2);
2827 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
2828 // vector with the inserted element.
2829 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2830 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2831 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2832 if (Elt < Ops.size())
2834 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
2835 &Ops[0], Ops.size());
2841 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
2842 SDOperand InVec = N->getOperand(0);
2843 SDOperand InVal = N->getOperand(1);
2844 SDOperand EltNo = N->getOperand(2);
2845 SDOperand NumElts = N->getOperand(3);
2846 SDOperand EltType = N->getOperand(4);
2848 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
2849 // vector with the inserted element.
2850 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2851 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2852 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2853 if (Elt < Ops.size()-2)
2855 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
2856 &Ops[0], Ops.size());
2862 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
2863 unsigned NumInScalars = N->getNumOperands()-2;
2864 SDOperand NumElts = N->getOperand(NumInScalars);
2865 SDOperand EltType = N->getOperand(NumInScalars+1);
2867 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
2868 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
2869 // two distinct vectors, turn this into a shuffle node.
2870 SDOperand VecIn1, VecIn2;
2871 for (unsigned i = 0; i != NumInScalars; ++i) {
2872 // Ignore undef inputs.
2873 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
2875 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
2876 // constant index, bail out.
2877 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
2878 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
2879 VecIn1 = VecIn2 = SDOperand(0, 0);
2883 // If the input vector type disagrees with the result of the vbuild_vector,
2884 // we can't make a shuffle.
2885 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
2886 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
2887 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
2888 VecIn1 = VecIn2 = SDOperand(0, 0);
2892 // Otherwise, remember this. We allow up to two distinct input vectors.
2893 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
2896 if (VecIn1.Val == 0) {
2897 VecIn1 = ExtractedFromVec;
2898 } else if (VecIn2.Val == 0) {
2899 VecIn2 = ExtractedFromVec;
2902 VecIn1 = VecIn2 = SDOperand(0, 0);
2907 // If everything is good, we can make a shuffle operation.
2909 SmallVector<SDOperand, 8> BuildVecIndices;
2910 for (unsigned i = 0; i != NumInScalars; ++i) {
2911 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
2912 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
2916 SDOperand Extract = N->getOperand(i);
2918 // If extracting from the first vector, just use the index directly.
2919 if (Extract.getOperand(0) == VecIn1) {
2920 BuildVecIndices.push_back(Extract.getOperand(1));
2924 // Otherwise, use InIdx + VecSize
2925 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
2926 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
2929 // Add count and size info.
2930 BuildVecIndices.push_back(NumElts);
2931 BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
2933 // Return the new VVECTOR_SHUFFLE node.
2939 // Use an undef vbuild_vector as input for the second operand.
2940 std::vector<SDOperand> UnOps(NumInScalars,
2941 DAG.getNode(ISD::UNDEF,
2942 cast<VTSDNode>(EltType)->getVT()));
2943 UnOps.push_back(NumElts);
2944 UnOps.push_back(EltType);
2945 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2946 &UnOps[0], UnOps.size());
2947 AddToWorkList(Ops[1].Val);
2949 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2950 &BuildVecIndices[0], BuildVecIndices.size());
2953 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
2959 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
2960 SDOperand ShufMask = N->getOperand(2);
2961 unsigned NumElts = ShufMask.getNumOperands();
2963 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2964 bool isIdentity = true;
2965 for (unsigned i = 0; i != NumElts; ++i) {
2966 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2967 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
2972 if (isIdentity) return N->getOperand(0);
2974 // If the shuffle mask is an identity operation on the RHS, return the RHS.
2976 for (unsigned i = 0; i != NumElts; ++i) {
2977 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2978 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
2983 if (isIdentity) return N->getOperand(1);
2985 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
2987 bool isUnary = true;
2988 bool isSplat = true;
2990 unsigned BaseIdx = 0;
2991 for (unsigned i = 0; i != NumElts; ++i)
2992 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
2993 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
2994 int V = (Idx < NumElts) ? 0 : 1;
3008 SDOperand N0 = N->getOperand(0);
3009 SDOperand N1 = N->getOperand(1);
3010 // Normalize unary shuffle so the RHS is undef.
3011 if (isUnary && VecNum == 1)
3014 // If it is a splat, check if the argument vector is a build_vector with
3015 // all scalar elements the same.
3018 if (V->getOpcode() == ISD::BIT_CONVERT)
3019 V = V->getOperand(0).Val;
3020 if (V->getOpcode() == ISD::BUILD_VECTOR) {
3021 unsigned NumElems = V->getNumOperands()-2;
3022 if (NumElems > BaseIdx) {
3024 bool AllSame = true;
3025 for (unsigned i = 0; i != NumElems; ++i) {
3026 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3027 Base = V->getOperand(i);
3031 // Splat of <u, u, u, u>, return <u, u, u, u>
3034 for (unsigned i = 0; i != NumElems; ++i) {
3035 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3036 V->getOperand(i) != Base) {
3041 // Splat of <x, x, x, x>, return <x, x, x, x>
3048 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3050 if (isUnary || N0 == N1) {
3051 if (N0.getOpcode() == ISD::UNDEF)
3052 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
3053 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3055 SmallVector<SDOperand, 8> MappedOps;
3056 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
3057 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3058 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3059 MappedOps.push_back(ShufMask.getOperand(i));
3062 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3063 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3066 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
3067 &MappedOps[0], MappedOps.size());
3068 AddToWorkList(ShufMask.Val);
3069 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
3071 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
3078 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
3079 SDOperand ShufMask = N->getOperand(2);
3080 unsigned NumElts = ShufMask.getNumOperands()-2;
3082 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3083 bool isIdentity = true;
3084 for (unsigned i = 0; i != NumElts; ++i) {
3085 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3086 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3091 if (isIdentity) return N->getOperand(0);
3093 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3095 for (unsigned i = 0; i != NumElts; ++i) {
3096 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3097 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3102 if (isIdentity) return N->getOperand(1);
3104 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3106 bool isUnary = true;
3107 bool isSplat = true;
3109 unsigned BaseIdx = 0;
3110 for (unsigned i = 0; i != NumElts; ++i)
3111 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3112 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3113 int V = (Idx < NumElts) ? 0 : 1;
3127 SDOperand N0 = N->getOperand(0);
3128 SDOperand N1 = N->getOperand(1);
3129 // Normalize unary shuffle so the RHS is undef.
3130 if (isUnary && VecNum == 1)
3133 // If it is a splat, check if the argument vector is a build_vector with
3134 // all scalar elements the same.
3137 if (V->getOpcode() == ISD::VBIT_CONVERT)
3138 V = V->getOperand(0).Val;
3139 if (V->getOpcode() == ISD::VBUILD_VECTOR) {
3140 unsigned NumElems = V->getNumOperands()-2;
3141 if (NumElems > BaseIdx) {
3143 bool AllSame = true;
3144 for (unsigned i = 0; i != NumElems; ++i) {
3145 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3146 Base = V->getOperand(i);
3150 // Splat of <u, u, u, u>, return <u, u, u, u>
3153 for (unsigned i = 0; i != NumElems; ++i) {
3154 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3155 V->getOperand(i) != Base) {
3160 // Splat of <x, x, x, x>, return <x, x, x, x>
3167 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3169 if (isUnary || N0 == N1) {
3170 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3172 SmallVector<SDOperand, 8> MappedOps;
3173 for (unsigned i = 0; i != NumElts; ++i) {
3174 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3175 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3176 MappedOps.push_back(ShufMask.getOperand(i));
3179 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3180 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3183 // Add the type/#elts values.
3184 MappedOps.push_back(ShufMask.getOperand(NumElts));
3185 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
3187 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
3188 &MappedOps[0], MappedOps.size());
3189 AddToWorkList(ShufMask.Val);
3191 // Build the undef vector.
3192 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
3193 for (unsigned i = 0; i != NumElts; ++i)
3194 MappedOps[i] = UDVal;
3195 MappedOps[NumElts ] = *(N0.Val->op_end()-2);
3196 MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
3197 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3198 &MappedOps[0], MappedOps.size());
3200 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3201 N0, UDVal, ShufMask,
3202 MappedOps[NumElts], MappedOps[NumElts+1]);
3208 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
3209 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
3210 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
3211 /// vector_shuffle V, Zero, <0, 4, 2, 4>
3212 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
3213 SDOperand LHS = N->getOperand(0);
3214 SDOperand RHS = N->getOperand(1);
3215 if (N->getOpcode() == ISD::VAND) {
3216 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
3217 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
3218 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
3219 RHS = RHS.getOperand(0);
3220 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3221 std::vector<SDOperand> IdxOps;
3222 unsigned NumOps = RHS.getNumOperands();
3223 unsigned NumElts = NumOps-2;
3224 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
3225 for (unsigned i = 0; i != NumElts; ++i) {
3226 SDOperand Elt = RHS.getOperand(i);
3227 if (!isa<ConstantSDNode>(Elt))
3229 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
3230 IdxOps.push_back(DAG.getConstant(i, EVT));
3231 else if (cast<ConstantSDNode>(Elt)->isNullValue())
3232 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
3237 // Let's see if the target supports this vector_shuffle.
3238 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
3241 // Return the new VVECTOR_SHUFFLE node.
3242 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
3243 SDOperand EVTNode = DAG.getValueType(EVT);
3244 std::vector<SDOperand> Ops;
3245 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode,
3248 AddToWorkList(LHS.Val);
3249 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
3250 ZeroOps.push_back(NumEltsNode);
3251 ZeroOps.push_back(EVTNode);
3252 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3253 &ZeroOps[0], ZeroOps.size()));
3254 IdxOps.push_back(NumEltsNode);
3255 IdxOps.push_back(EVTNode);
3256 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3257 &IdxOps[0], IdxOps.size()));
3258 Ops.push_back(NumEltsNode);
3259 Ops.push_back(EVTNode);
3260 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3261 &Ops[0], Ops.size());
3262 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
3263 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
3264 DstVecSize, DstVecEVT);
3272 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
3273 /// the scalar operation of the vop if it is operating on an integer vector
3274 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
3275 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
3276 ISD::NodeType FPOp) {
3277 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
3278 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
3279 SDOperand LHS = N->getOperand(0);
3280 SDOperand RHS = N->getOperand(1);
3281 SDOperand Shuffle = XformToShuffleWithZero(N);
3282 if (Shuffle.Val) return Shuffle;
3284 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
3286 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
3287 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3288 SmallVector<SDOperand, 8> Ops;
3289 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
3290 SDOperand LHSOp = LHS.getOperand(i);
3291 SDOperand RHSOp = RHS.getOperand(i);
3292 // If these two elements can't be folded, bail out.
3293 if ((LHSOp.getOpcode() != ISD::UNDEF &&
3294 LHSOp.getOpcode() != ISD::Constant &&
3295 LHSOp.getOpcode() != ISD::ConstantFP) ||
3296 (RHSOp.getOpcode() != ISD::UNDEF &&
3297 RHSOp.getOpcode() != ISD::Constant &&
3298 RHSOp.getOpcode() != ISD::ConstantFP))
3300 // Can't fold divide by zero.
3301 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
3302 if ((RHSOp.getOpcode() == ISD::Constant &&
3303 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
3304 (RHSOp.getOpcode() == ISD::ConstantFP &&
3305 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
3308 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
3309 AddToWorkList(Ops.back().Val);
3310 assert((Ops.back().getOpcode() == ISD::UNDEF ||
3311 Ops.back().getOpcode() == ISD::Constant ||
3312 Ops.back().getOpcode() == ISD::ConstantFP) &&
3313 "Scalar binop didn't fold!");
3316 if (Ops.size() == LHS.getNumOperands()-2) {
3317 Ops.push_back(*(LHS.Val->op_end()-2));
3318 Ops.push_back(*(LHS.Val->op_end()-1));
3319 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
3326 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
3327 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
3329 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
3330 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3331 // If we got a simplified select_cc node back from SimplifySelectCC, then
3332 // break it down into a new SETCC node, and a new SELECT node, and then return
3333 // the SELECT node, since we were called with a SELECT node.
3335 // Check to see if we got a select_cc back (to turn into setcc/select).
3336 // Otherwise, just return whatever node we got back, like fabs.
3337 if (SCC.getOpcode() == ISD::SELECT_CC) {
3338 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
3339 SCC.getOperand(0), SCC.getOperand(1),
3341 AddToWorkList(SETCC.Val);
3342 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
3343 SCC.getOperand(3), SETCC);
3350 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
3351 /// are the two values being selected between, see if we can simplify the
3352 /// select. Callers of this should assume that TheSelect is deleted if this
3353 /// returns true. As such, they should return the appropriate thing (e.g. the
3354 /// node) back to the top-level of the DAG combiner loop to avoid it being
3357 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
3360 // If this is a select from two identical things, try to pull the operation
3361 // through the select.
3362 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
3363 // If this is a load and the token chain is identical, replace the select
3364 // of two loads with a load through a select of the address to load from.
3365 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3366 // constants have been dropped into the constant pool.
3367 if (LHS.getOpcode() == ISD::LOAD &&
3368 // Token chains must be identical.
3369 LHS.getOperand(0) == RHS.getOperand(0)) {
3370 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
3371 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
3373 // If this is an EXTLOAD, the VT's must match.
3374 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
3375 // FIXME: this conflates two src values, discarding one. This is not
3376 // the right thing to do, but nothing uses srcvalues now. When they do,
3377 // turn SrcValue into a list of locations.
3379 if (TheSelect->getOpcode() == ISD::SELECT)
3380 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
3381 TheSelect->getOperand(0), LLD->getBasePtr(),
3384 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
3385 TheSelect->getOperand(0),
3386 TheSelect->getOperand(1),
3387 LLD->getBasePtr(), RLD->getBasePtr(),
3388 TheSelect->getOperand(4));
3391 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
3392 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
3393 Addr,LLD->getSrcValue(), LLD->getSrcValueOffset());
3395 Load = DAG.getExtLoad(LLD->getExtensionType(),
3396 TheSelect->getValueType(0),
3397 LLD->getChain(), Addr, LLD->getSrcValue(),
3398 LLD->getSrcValueOffset(),
3399 LLD->getLoadedVT());
3401 // Users of the select now use the result of the load.
3402 CombineTo(TheSelect, Load);
3404 // Users of the old loads now use the new load's chain. We know the
3405 // old-load value is dead now.
3406 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
3407 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
3416 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
3417 SDOperand N2, SDOperand N3,
3420 MVT::ValueType VT = N2.getValueType();
3421 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
3422 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
3423 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
3425 // Determine if the condition we're dealing with is constant
3426 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
3427 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
3429 // fold select_cc true, x, y -> x
3430 if (SCCC && SCCC->getValue())
3432 // fold select_cc false, x, y -> y
3433 if (SCCC && SCCC->getValue() == 0)
3436 // Check to see if we can simplify the select into an fabs node
3437 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
3438 // Allow either -0.0 or 0.0
3439 if (CFP->getValue() == 0.0) {
3440 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
3441 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
3442 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
3443 N2 == N3.getOperand(0))
3444 return DAG.getNode(ISD::FABS, VT, N0);
3446 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
3447 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
3448 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
3449 N2.getOperand(0) == N3)
3450 return DAG.getNode(ISD::FABS, VT, N3);
3454 // Check to see if we can perform the "gzip trick", transforming
3455 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
3456 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
3457 MVT::isInteger(N0.getValueType()) &&
3458 MVT::isInteger(N2.getValueType()) &&
3459 (N1C->isNullValue() || // (a < 0) ? b : 0
3460 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
3461 MVT::ValueType XType = N0.getValueType();
3462 MVT::ValueType AType = N2.getValueType();
3463 if (XType >= AType) {
3464 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
3465 // single-bit constant.
3466 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
3467 unsigned ShCtV = Log2_64(N2C->getValue());
3468 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
3469 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
3470 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
3471 AddToWorkList(Shift.Val);
3472 if (XType > AType) {
3473 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3474 AddToWorkList(Shift.Val);
3476 return DAG.getNode(ISD::AND, AType, Shift, N2);
3478 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3479 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3480 TLI.getShiftAmountTy()));
3481 AddToWorkList(Shift.Val);
3482 if (XType > AType) {
3483 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3484 AddToWorkList(Shift.Val);
3486 return DAG.getNode(ISD::AND, AType, Shift, N2);
3490 // fold select C, 16, 0 -> shl C, 4
3491 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
3492 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
3493 // Get a SetCC of the condition
3494 // FIXME: Should probably make sure that setcc is legal if we ever have a
3495 // target where it isn't.
3496 SDOperand Temp, SCC;
3497 // cast from setcc result type to select result type
3498 if (AfterLegalize) {
3499 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3500 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
3502 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
3503 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3505 AddToWorkList(SCC.Val);
3506 AddToWorkList(Temp.Val);
3507 // shl setcc result by log2 n2c
3508 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
3509 DAG.getConstant(Log2_64(N2C->getValue()),
3510 TLI.getShiftAmountTy()));
3513 // Check to see if this is the equivalent of setcc
3514 // FIXME: Turn all of these into setcc if setcc if setcc is legal
3515 // otherwise, go ahead with the folds.
3516 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
3517 MVT::ValueType XType = N0.getValueType();
3518 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
3519 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3520 if (Res.getValueType() != VT)
3521 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
3525 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
3526 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
3527 TLI.isOperationLegal(ISD::CTLZ, XType)) {
3528 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
3529 return DAG.getNode(ISD::SRL, XType, Ctlz,
3530 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
3531 TLI.getShiftAmountTy()));
3533 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
3534 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
3535 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
3537 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
3538 DAG.getConstant(~0ULL, XType));
3539 return DAG.getNode(ISD::SRL, XType,
3540 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
3541 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3542 TLI.getShiftAmountTy()));
3544 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
3545 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
3546 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
3547 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3548 TLI.getShiftAmountTy()));
3549 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
3553 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
3554 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
3555 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
3556 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
3557 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
3558 MVT::ValueType XType = N0.getValueType();
3559 if (SubC->isNullValue() && MVT::isInteger(XType)) {
3560 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3561 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3562 TLI.getShiftAmountTy()));
3563 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
3564 AddToWorkList(Shift.Val);
3565 AddToWorkList(Add.Val);
3566 return DAG.getNode(ISD::XOR, XType, Add, Shift);
3574 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
3575 SDOperand N1, ISD::CondCode Cond,
3576 bool foldBooleans) {
3577 // These setcc operations always fold.
3581 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
3583 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
3586 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
3587 uint64_t C1 = N1C->getValue();
3588 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
3589 uint64_t C0 = N0C->getValue();
3591 // Sign extend the operands if required
3592 if (ISD::isSignedIntSetCC(Cond)) {
3593 C0 = N0C->getSignExtended();
3594 C1 = N1C->getSignExtended();
3598 default: assert(0 && "Unknown integer setcc!");
3599 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3600 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3601 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
3602 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
3603 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
3604 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
3605 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
3606 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
3607 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
3608 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
3611 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
3612 // equality comparison, then we're just comparing whether X itself is
3614 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
3615 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
3616 N0.getOperand(1).getOpcode() == ISD::Constant) {
3617 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
3618 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3619 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
3620 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
3621 // (srl (ctlz x), 5) == 0 -> X != 0
3622 // (srl (ctlz x), 5) != 1 -> X != 0
3625 // (srl (ctlz x), 5) != 0 -> X == 0
3626 // (srl (ctlz x), 5) == 1 -> X == 0
3629 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
3630 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
3635 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3636 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3637 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
3639 // If the comparison constant has bits in the upper part, the
3640 // zero-extended value could never match.
3641 if (C1 & (~0ULL << InSize)) {
3642 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
3646 case ISD::SETEQ: return DAG.getConstant(0, VT);
3649 case ISD::SETNE: return DAG.getConstant(1, VT);
3652 // True if the sign bit of C1 is set.
3653 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
3656 // True if the sign bit of C1 isn't set.
3657 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
3663 // Otherwise, we can perform the comparison with the low bits.
3671 return DAG.getSetCC(VT, N0.getOperand(0),
3672 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
3675 break; // todo, be more careful with signed comparisons
3677 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3678 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3679 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3680 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
3681 MVT::ValueType ExtDstTy = N0.getValueType();
3682 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
3684 // If the extended part has any inconsistent bits, it cannot ever
3685 // compare equal. In other words, they have to be all ones or all
3688 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
3689 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
3690 return DAG.getConstant(Cond == ISD::SETNE, VT);
3693 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
3694 if (Op0Ty == ExtSrcTy) {
3695 ZextOp = N0.getOperand(0);
3697 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
3698 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
3699 DAG.getConstant(Imm, Op0Ty));
3701 AddToWorkList(ZextOp.Val);
3702 // Otherwise, make this a use of a zext.
3703 return DAG.getSetCC(VT, ZextOp,
3704 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
3707 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
3708 (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3709 (N0.getOpcode() == ISD::XOR ||
3710 (N0.getOpcode() == ISD::AND &&
3711 N0.getOperand(0).getOpcode() == ISD::XOR &&
3712 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3713 isa<ConstantSDNode>(N0.getOperand(1)) &&
3714 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
3715 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can
3716 // only do this if the top bits are known zero.
3717 if (TLI.MaskedValueIsZero(N1,
3718 MVT::getIntVTBitMask(N0.getValueType())-1)) {
3719 // Okay, get the un-inverted input value.
3721 if (N0.getOpcode() == ISD::XOR)
3722 Val = N0.getOperand(0);
3724 assert(N0.getOpcode() == ISD::AND &&
3725 N0.getOperand(0).getOpcode() == ISD::XOR);
3726 // ((X^1)&1)^1 -> X & 1
3727 Val = DAG.getNode(ISD::AND, N0.getValueType(),
3728 N0.getOperand(0).getOperand(0), N0.getOperand(1));
3730 return DAG.getSetCC(VT, Val, N1,
3731 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3735 uint64_t MinVal, MaxVal;
3736 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
3737 if (ISD::isSignedIntSetCC(Cond)) {
3738 MinVal = 1ULL << (OperandBitSize-1);
3739 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
3740 MaxVal = ~0ULL >> (65-OperandBitSize);
3745 MaxVal = ~0ULL >> (64-OperandBitSize);
3748 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
3749 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3750 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
3751 --C1; // X >= C0 --> X > (C0-1)
3752 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3753 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
3756 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
3757 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
3758 ++C1; // X <= C0 --> X < (C0+1)
3759 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3760 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
3763 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
3764 return DAG.getConstant(0, VT); // X < MIN --> false
3766 // Canonicalize setgt X, Min --> setne X, Min
3767 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
3768 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3769 // Canonicalize setlt X, Max --> setne X, Max
3770 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
3771 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3773 // If we have setult X, 1, turn it into seteq X, 0
3774 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
3775 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
3777 // If we have setugt X, Max-1, turn it into seteq X, Max
3778 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
3779 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
3782 // If we have "setcc X, C0", check to see if we can shrink the immediate
3785 // SETUGT X, SINTMAX -> SETLT X, 0
3786 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
3787 C1 == (~0ULL >> (65-OperandBitSize)))
3788 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
3791 // FIXME: Implement the rest of these.
3793 // Fold bit comparisons when we can.
3794 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3795 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
3796 if (ConstantSDNode *AndRHS =
3797 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3798 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
3799 // Perform the xform if the AND RHS is a single bit.
3800 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
3801 return DAG.getNode(ISD::SRL, VT, N0,
3802 DAG.getConstant(Log2_64(AndRHS->getValue()),
3803 TLI.getShiftAmountTy()));
3805 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
3806 // (X & 8) == 8 --> (X & 8) >> 3
3807 // Perform the xform if C1 is a single bit.
3808 if ((C1 & (C1-1)) == 0) {
3809 return DAG.getNode(ISD::SRL, VT, N0,
3810 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
3815 } else if (isa<ConstantSDNode>(N0.Val)) {
3816 // Ensure that the constant occurs on the RHS.
3817 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3820 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
3821 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
3822 double C0 = N0C->getValue(), C1 = N1C->getValue();
3825 default: break; // FIXME: Implement the rest of these!
3826 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3827 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3828 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
3829 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
3830 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
3831 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
3834 // Ensure that the constant occurs on the RHS.
3835 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3839 // We can always fold X == Y for integer setcc's.
3840 if (MVT::isInteger(N0.getValueType()))
3841 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3842 unsigned UOF = ISD::getUnorderedFlavor(Cond);
3843 if (UOF == 2) // FP operators that are undefined on NaNs.
3844 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3845 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
3846 return DAG.getConstant(UOF, VT);
3847 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
3848 // if it is not already.
3849 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
3850 if (NewCond != Cond)
3851 return DAG.getSetCC(VT, N0, N1, NewCond);
3854 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3855 MVT::isInteger(N0.getValueType())) {
3856 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3857 N0.getOpcode() == ISD::XOR) {
3858 // Simplify (X+Y) == (X+Z) --> Y == Z
3859 if (N0.getOpcode() == N1.getOpcode()) {
3860 if (N0.getOperand(0) == N1.getOperand(0))
3861 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
3862 if (N0.getOperand(1) == N1.getOperand(1))
3863 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
3864 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
3865 // If X op Y == Y op X, try other combinations.
3866 if (N0.getOperand(0) == N1.getOperand(1))
3867 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
3868 if (N0.getOperand(1) == N1.getOperand(0))
3869 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
3873 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
3874 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3875 // Turn (X+C1) == C2 --> X == C2-C1
3876 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
3877 return DAG.getSetCC(VT, N0.getOperand(0),
3878 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
3879 N0.getValueType()), Cond);
3882 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
3883 if (N0.getOpcode() == ISD::XOR)
3884 // If we know that all of the inverted bits are zero, don't bother
3885 // performing the inversion.
3886 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
3887 return DAG.getSetCC(VT, N0.getOperand(0),
3888 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
3889 N0.getValueType()), Cond);
3892 // Turn (C1-X) == C2 --> X == C1-C2
3893 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
3894 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
3895 return DAG.getSetCC(VT, N0.getOperand(1),
3896 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
3897 N0.getValueType()), Cond);
3902 // Simplify (X+Z) == X --> Z == 0
3903 if (N0.getOperand(0) == N1)
3904 return DAG.getSetCC(VT, N0.getOperand(1),
3905 DAG.getConstant(0, N0.getValueType()), Cond);
3906 if (N0.getOperand(1) == N1) {
3907 if (DAG.isCommutativeBinOp(N0.getOpcode()))
3908 return DAG.getSetCC(VT, N0.getOperand(0),
3909 DAG.getConstant(0, N0.getValueType()), Cond);
3911 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
3912 // (Z-X) == X --> Z == X<<1
3913 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
3915 DAG.getConstant(1,TLI.getShiftAmountTy()));
3916 AddToWorkList(SH.Val);
3917 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
3922 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3923 N1.getOpcode() == ISD::XOR) {
3924 // Simplify X == (X+Z) --> Z == 0
3925 if (N1.getOperand(0) == N0) {
3926 return DAG.getSetCC(VT, N1.getOperand(1),
3927 DAG.getConstant(0, N1.getValueType()), Cond);
3928 } else if (N1.getOperand(1) == N0) {
3929 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
3930 return DAG.getSetCC(VT, N1.getOperand(0),
3931 DAG.getConstant(0, N1.getValueType()), Cond);
3933 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
3934 // X == (Z-X) --> X<<1 == Z
3935 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
3936 DAG.getConstant(1,TLI.getShiftAmountTy()));
3937 AddToWorkList(SH.Val);
3938 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
3944 // Fold away ALL boolean setcc's.
3946 if (N0.getValueType() == MVT::i1 && foldBooleans) {
3948 default: assert(0 && "Unknown integer setcc!");
3949 case ISD::SETEQ: // X == Y -> (X^Y)^1
3950 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3951 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
3952 AddToWorkList(Temp.Val);
3954 case ISD::SETNE: // X != Y --> (X^Y)
3955 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3957 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
3958 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
3959 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3960 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
3961 AddToWorkList(Temp.Val);
3963 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
3964 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
3965 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3966 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
3967 AddToWorkList(Temp.Val);
3969 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
3970 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
3971 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3972 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
3973 AddToWorkList(Temp.Val);
3975 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
3976 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
3977 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3978 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
3981 if (VT != MVT::i1) {
3982 AddToWorkList(N0.Val);
3983 // FIXME: If running after legalize, we probably can't do this.
3984 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
3989 // Could not fold it.
3993 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3994 /// return a DAG expression to select that will generate the same value by
3995 /// multiplying by a magic number. See:
3996 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3997 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
3998 std::vector<SDNode*> Built;
3999 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
4001 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4007 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
4008 /// return a DAG expression to select that will generate the same value by
4009 /// multiplying by a magic number. See:
4010 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4011 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
4012 std::vector<SDNode*> Built;
4013 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
4015 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4021 /// FindBaseOffset - Return true if base is known not to alias with anything
4022 /// but itself. Provides base object and offset as results.
4023 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4024 // Assume it is a primitive operation.
4025 Base = Ptr; Offset = 0;
4027 // If it's an adding a simple constant then integrate the offset.
4028 if (Base.getOpcode() == ISD::ADD) {
4029 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4030 Base = Base.getOperand(0);
4031 Offset += C->getValue();
4035 // If it's any of the following then it can't alias with anything but itself.
4036 return isa<FrameIndexSDNode>(Base) ||
4037 isa<ConstantPoolSDNode>(Base) ||
4038 isa<GlobalAddressSDNode>(Base);
4041 /// isAlias - Return true if there is any possibility that the two addresses
4043 static bool isAlias(SDOperand Ptr1, int64_t Size1, const Value *SrcValue1,
4044 SDOperand Ptr2, int64_t Size2, const Value *SrcValue2) {
4045 // If they are the same then they must be aliases.
4046 if (Ptr1 == Ptr2) return true;
4048 // Gather base node and offset information.
4049 SDOperand Base1, Base2;
4050 int64_t Offset1, Offset2;
4051 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4052 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4054 // If they have a same base address then...
4055 if (Base1 == Base2) {
4056 // Check to see if the addresses overlap.
4057 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4060 // Otherwise they alias if either is unknown.
4061 return !KnownBase1 || !KnownBase2;
4064 /// FindAliasInfo - Extracts the relevant alias information from the memory
4065 /// node. Returns true if the operand was a load.
4066 bool DAGCombiner::FindAliasInfo(SDNode *N,
4067 SDOperand &Ptr, int64_t &Size, const Value *&SrcValue) {
4068 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4069 Ptr = LD->getBasePtr();
4070 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4071 SrcValue = LD->getSrcValue();
4073 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4074 Ptr = ST->getBasePtr();
4075 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4076 SrcValue = ST->getSrcValue();
4078 assert(0 && "FindAliasInfo expected a memory operand");
4084 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4085 /// looking for aliasing nodes and adding them to the Aliases vector.
4086 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4087 SmallVector<SDOperand, 8> &Aliases) {
4088 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4089 std::set<SDNode *> Visited; // Visited node set.
4091 // Get alias information for node.
4094 const Value *SrcValue;
4095 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue);
4098 Chains.push_back(OriginalChain);
4100 // Look at each chain and determine if it is an alias. If so, add it to the
4101 // aliases list. If not, then continue up the chain looking for the next
4103 while (!Chains.empty()) {
4104 SDOperand Chain = Chains.back();
4107 // Don't bother if we've been before.
4108 if (Visited.find(Chain.Val) != Visited.end()) continue;
4109 Visited.insert(Chain.Val);
4111 switch (Chain.getOpcode()) {
4112 case ISD::EntryToken:
4113 // Entry token is ideal chain operand, but handled in FindBetterChain.
4118 // Get alias information for Chain.
4121 const Value *OpSrcValue;
4122 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, OpSrcValue);
4124 // If chain is alias then stop here.
4125 if (!(IsLoad && IsOpLoad) &&
4126 isAlias(Ptr, Size, SrcValue, OpPtr, OpSize, OpSrcValue)) {
4127 Aliases.push_back(Chain);
4129 // Look further up the chain.
4130 Chains.push_back(Chain.getOperand(0));
4131 // Clean up old chain.
4132 AddToWorkList(Chain.Val);
4137 case ISD::TokenFactor:
4138 // We have to check each of the operands of the token factor, so we queue
4139 // then up. Adding the operands to the queue (stack) in reverse order
4140 // maintains the original order and increases the likelihood that getNode
4141 // will find a matching token factor (CSE.)
4142 for (unsigned n = Chain.getNumOperands(); n;)
4143 Chains.push_back(Chain.getOperand(--n));
4144 // Eliminate the token factor if we can.
4145 AddToWorkList(Chain.Val);
4149 // For all other instructions we will just have to take what we can get.
4150 Aliases.push_back(Chain);
4156 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4157 /// for a better chain (aliasing node.)
4158 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4159 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4161 // Accumulate all the aliases to this node.
4162 GatherAllAliases(N, OldChain, Aliases);
4164 if (Aliases.size() == 0) {
4165 // If no operands then chain to entry token.
4166 return DAG.getEntryNode();
4167 } else if (Aliases.size() == 1) {
4168 // If a single operand then chain to it. We don't need to revisit it.
4172 // Construct a custom tailored token factor.
4173 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4174 &Aliases[0], Aliases.size());
4176 // Make sure the old chain gets cleaned up.
4177 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4182 // SelectionDAG::Combine - This is the entry point for the file.
4184 void SelectionDAG::Combine(bool RunningAfterLegalize) {
4185 /// run - This is the main entry point to this class.
4187 DAGCombiner(*this).Run(RunningAfterLegalize);