1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/SmallPtrSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
42 STATISTIC(NodesCombined , "Number of dag nodes combined");
43 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
44 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
45 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
49 CombinerAA("combiner-alias-analysis", cl::Hidden,
50 cl::desc("Turn on alias analysis during testing"));
53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
54 cl::desc("Include global information in alias analysis"));
56 //------------------------------ DAGCombiner ---------------------------------//
60 const TargetLowering &TLI;
62 CodeGenOpt::Level OptLevel;
66 // Worklist of all of the nodes that need to be simplified.
67 std::vector<SDNode*> WorkList;
69 // AA - Used for DAG load/store alias analysis.
72 /// AddUsersToWorkList - When an instruction is simplified, add all users of
73 /// the instruction to the work lists because they might get more simplified
76 void AddUsersToWorkList(SDNode *N) {
77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
82 /// visit - call the node-specific routine that knows how to fold each
83 /// particular type of node.
84 SDValue visit(SDNode *N);
87 /// AddToWorkList - Add to the work list making sure it's instance is at the
88 /// the back (next to be processed.)
89 void AddToWorkList(SDNode *N) {
90 removeFromWorkList(N);
91 WorkList.push_back(N);
94 /// removeFromWorkList - remove all instances of N from the worklist.
96 void removeFromWorkList(SDNode *N) {
97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
105 return CombineTo(N, &Res, 1, AddTo);
108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
110 SDValue To[] = { Res0, Res1 };
111 return CombineTo(N, To, 2, AddTo);
114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
118 /// SimplifyDemandedBits - Check the specified integer node value to see if
119 /// it can be simplified or if things it uses can be simplified by bit
120 /// propagation. If so, return true.
121 bool SimplifyDemandedBits(SDValue Op) {
122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
123 APInt Demanded = APInt::getAllOnesValue(BitWidth);
124 return SimplifyDemandedBits(Op, Demanded);
127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
129 bool CombineToPreIndexedLoadStore(SDNode *N);
130 bool CombineToPostIndexedLoadStore(SDNode *N);
132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
136 SDValue PromoteIntBinOp(SDValue Op);
137 SDValue PromoteIntShiftOp(SDValue Op);
138 SDValue PromoteExtend(SDValue Op);
139 bool PromoteLoad(SDValue Op);
141 /// combine - call the node-specific routine that knows how to fold each
142 /// particular type of node. If that doesn't do anything, try the
143 /// target-specific DAG combines.
144 SDValue combine(SDNode *N);
146 // Visitation implementation - Implement dag node combining for different
147 // node types. The semantics are as follows:
149 // SDValue.getNode() == 0 - No change was made
150 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
151 // otherwise - N should be replaced by the returned Operand.
153 SDValue visitTokenFactor(SDNode *N);
154 SDValue visitMERGE_VALUES(SDNode *N);
155 SDValue visitADD(SDNode *N);
156 SDValue visitSUB(SDNode *N);
157 SDValue visitADDC(SDNode *N);
158 SDValue visitADDE(SDNode *N);
159 SDValue visitMUL(SDNode *N);
160 SDValue visitSDIV(SDNode *N);
161 SDValue visitUDIV(SDNode *N);
162 SDValue visitSREM(SDNode *N);
163 SDValue visitUREM(SDNode *N);
164 SDValue visitMULHU(SDNode *N);
165 SDValue visitMULHS(SDNode *N);
166 SDValue visitSMUL_LOHI(SDNode *N);
167 SDValue visitUMUL_LOHI(SDNode *N);
168 SDValue visitSDIVREM(SDNode *N);
169 SDValue visitUDIVREM(SDNode *N);
170 SDValue visitAND(SDNode *N);
171 SDValue visitOR(SDNode *N);
172 SDValue visitXOR(SDNode *N);
173 SDValue SimplifyVBinOp(SDNode *N);
174 SDValue visitSHL(SDNode *N);
175 SDValue visitSRA(SDNode *N);
176 SDValue visitSRL(SDNode *N);
177 SDValue visitCTLZ(SDNode *N);
178 SDValue visitCTTZ(SDNode *N);
179 SDValue visitCTPOP(SDNode *N);
180 SDValue visitSELECT(SDNode *N);
181 SDValue visitSELECT_CC(SDNode *N);
182 SDValue visitSETCC(SDNode *N);
183 SDValue visitSIGN_EXTEND(SDNode *N);
184 SDValue visitZERO_EXTEND(SDNode *N);
185 SDValue visitANY_EXTEND(SDNode *N);
186 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
187 SDValue visitTRUNCATE(SDNode *N);
188 SDValue visitBIT_CONVERT(SDNode *N);
189 SDValue visitBUILD_PAIR(SDNode *N);
190 SDValue visitFADD(SDNode *N);
191 SDValue visitFSUB(SDNode *N);
192 SDValue visitFMUL(SDNode *N);
193 SDValue visitFDIV(SDNode *N);
194 SDValue visitFREM(SDNode *N);
195 SDValue visitFCOPYSIGN(SDNode *N);
196 SDValue visitSINT_TO_FP(SDNode *N);
197 SDValue visitUINT_TO_FP(SDNode *N);
198 SDValue visitFP_TO_SINT(SDNode *N);
199 SDValue visitFP_TO_UINT(SDNode *N);
200 SDValue visitFP_ROUND(SDNode *N);
201 SDValue visitFP_ROUND_INREG(SDNode *N);
202 SDValue visitFP_EXTEND(SDNode *N);
203 SDValue visitFNEG(SDNode *N);
204 SDValue visitFABS(SDNode *N);
205 SDValue visitBRCOND(SDNode *N);
206 SDValue visitBR_CC(SDNode *N);
207 SDValue visitLOAD(SDNode *N);
208 SDValue visitSTORE(SDNode *N);
209 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
210 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
211 SDValue visitBUILD_VECTOR(SDNode *N);
212 SDValue visitCONCAT_VECTORS(SDNode *N);
213 SDValue visitVECTOR_SHUFFLE(SDNode *N);
214 SDValue visitMEMBARRIER(SDNode *N);
216 SDValue XformToShuffleWithZero(SDNode *N);
217 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
219 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
221 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
222 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
223 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
224 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
225 SDValue N3, ISD::CondCode CC,
226 bool NotExtCompare = false);
227 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
228 DebugLoc DL, bool foldBooleans = true);
229 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
231 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
232 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT);
233 SDValue BuildSDIV(SDNode *N);
234 SDValue BuildUDIV(SDNode *N);
235 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
236 SDValue ReduceLoadWidth(SDNode *N);
237 SDValue ReduceLoadOpStoreWidth(SDNode *N);
239 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
241 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
242 /// looking for aliasing nodes and adding them to the Aliases vector.
243 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
244 SmallVector<SDValue, 8> &Aliases);
246 /// isAlias - Return true if there is any possibility that the two addresses
248 bool isAlias(SDValue Ptr1, int64_t Size1,
249 const Value *SrcValue1, int SrcValueOffset1,
250 unsigned SrcValueAlign1,
251 SDValue Ptr2, int64_t Size2,
252 const Value *SrcValue2, int SrcValueOffset2,
253 unsigned SrcValueAlign2) const;
255 /// FindAliasInfo - Extracts the relevant alias information from the memory
256 /// node. Returns true if the operand was a load.
257 bool FindAliasInfo(SDNode *N,
258 SDValue &Ptr, int64_t &Size,
259 const Value *&SrcValue, int &SrcValueOffset,
260 unsigned &SrcValueAlignment) const;
262 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
263 /// looking for a better chain (aliasing node.)
264 SDValue FindBetterChain(SDNode *N, SDValue Chain);
267 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
268 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted),
269 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
271 /// Run - runs the dag combiner on all nodes in the work list
272 void Run(CombineLevel AtLevel);
274 SelectionDAG &getDAG() const { return DAG; }
276 /// getShiftAmountTy - Returns a type large enough to hold any valid
277 /// shift amount - before type legalization these can be huge.
278 EVT getShiftAmountTy() {
279 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
282 /// isTypeLegal - This method returns true if we are running before type
283 /// legalization or if the specified VT is legal.
284 bool isTypeLegal(const EVT &VT) {
285 if (!LegalTypes) return true;
286 return TLI.isTypeLegal(VT);
293 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
294 /// nodes from the worklist.
295 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
298 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
300 virtual void NodeDeleted(SDNode *N, SDNode *E) {
301 DC.removeFromWorkList(N);
304 virtual void NodeUpdated(SDNode *N) {
310 //===----------------------------------------------------------------------===//
311 // TargetLowering::DAGCombinerInfo implementation
312 //===----------------------------------------------------------------------===//
314 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
315 ((DAGCombiner*)DC)->AddToWorkList(N);
318 SDValue TargetLowering::DAGCombinerInfo::
319 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
320 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
323 SDValue TargetLowering::DAGCombinerInfo::
324 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
325 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
329 SDValue TargetLowering::DAGCombinerInfo::
330 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
331 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
334 void TargetLowering::DAGCombinerInfo::
335 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
336 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
339 //===----------------------------------------------------------------------===//
341 //===----------------------------------------------------------------------===//
343 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
344 /// specified expression for the same cost as the expression itself, or 2 if we
345 /// can compute the negated form more cheaply than the expression itself.
346 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
347 unsigned Depth = 0) {
348 // No compile time optimizations on this type.
349 if (Op.getValueType() == MVT::ppcf128)
352 // fneg is removable even if it has multiple uses.
353 if (Op.getOpcode() == ISD::FNEG) return 2;
355 // Don't allow anything with multiple uses.
356 if (!Op.hasOneUse()) return 0;
358 // Don't recurse exponentially.
359 if (Depth > 6) return 0;
361 switch (Op.getOpcode()) {
362 default: return false;
363 case ISD::ConstantFP:
364 // Don't invert constant FP values after legalize. The negated constant
365 // isn't necessarily legal.
366 return LegalOperations ? 0 : 1;
368 // FIXME: determine better conditions for this xform.
369 if (!UnsafeFPMath) return 0;
371 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
372 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
374 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
375 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
377 // We can't turn -(A-B) into B-A when we honor signed zeros.
378 if (!UnsafeFPMath) return 0;
380 // fold (fneg (fsub A, B)) -> (fsub B, A)
385 if (HonorSignDependentRoundingFPMath()) return 0;
387 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
388 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
391 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
396 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
400 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
401 /// returns the newly negated expression.
402 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
403 bool LegalOperations, unsigned Depth = 0) {
404 // fneg is removable even if it has multiple uses.
405 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
407 // Don't allow anything with multiple uses.
408 assert(Op.hasOneUse() && "Unknown reuse!");
410 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
411 switch (Op.getOpcode()) {
412 default: llvm_unreachable("Unknown code");
413 case ISD::ConstantFP: {
414 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
416 return DAG.getConstantFP(V, Op.getValueType());
419 // FIXME: determine better conditions for this xform.
420 assert(UnsafeFPMath);
422 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
423 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
424 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
425 GetNegatedExpression(Op.getOperand(0), DAG,
426 LegalOperations, Depth+1),
428 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
429 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
430 GetNegatedExpression(Op.getOperand(1), DAG,
431 LegalOperations, Depth+1),
434 // We can't turn -(A-B) into B-A when we honor signed zeros.
435 assert(UnsafeFPMath);
437 // fold (fneg (fsub 0, B)) -> B
438 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
439 if (N0CFP->getValueAPF().isZero())
440 return Op.getOperand(1);
442 // fold (fneg (fsub A, B)) -> (fsub B, A)
443 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
444 Op.getOperand(1), Op.getOperand(0));
448 assert(!HonorSignDependentRoundingFPMath());
450 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
451 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
452 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
453 GetNegatedExpression(Op.getOperand(0), DAG,
454 LegalOperations, Depth+1),
457 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
458 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
460 GetNegatedExpression(Op.getOperand(1), DAG,
461 LegalOperations, Depth+1));
465 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
466 GetNegatedExpression(Op.getOperand(0), DAG,
467 LegalOperations, Depth+1));
469 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
470 GetNegatedExpression(Op.getOperand(0), DAG,
471 LegalOperations, Depth+1),
477 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
478 // that selects between the values 1 and 0, making it equivalent to a setcc.
479 // Also, set the incoming LHS, RHS, and CC references to the appropriate
480 // nodes based on the type of node we are checking. This simplifies life a
481 // bit for the callers.
482 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
484 if (N.getOpcode() == ISD::SETCC) {
485 LHS = N.getOperand(0);
486 RHS = N.getOperand(1);
487 CC = N.getOperand(2);
490 if (N.getOpcode() == ISD::SELECT_CC &&
491 N.getOperand(2).getOpcode() == ISD::Constant &&
492 N.getOperand(3).getOpcode() == ISD::Constant &&
493 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
494 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
495 LHS = N.getOperand(0);
496 RHS = N.getOperand(1);
497 CC = N.getOperand(4);
503 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
504 // one use. If this is true, it allows the users to invert the operation for
505 // free when it is profitable to do so.
506 static bool isOneUseSetCC(SDValue N) {
508 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
513 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
514 SDValue N0, SDValue N1) {
515 EVT VT = N0.getValueType();
516 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
517 if (isa<ConstantSDNode>(N1)) {
518 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
520 DAG.FoldConstantArithmetic(Opc, VT,
521 cast<ConstantSDNode>(N0.getOperand(1)),
522 cast<ConstantSDNode>(N1));
523 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
524 } else if (N0.hasOneUse()) {
525 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
526 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
527 N0.getOperand(0), N1);
528 AddToWorkList(OpNode.getNode());
529 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
533 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
534 if (isa<ConstantSDNode>(N0)) {
535 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
537 DAG.FoldConstantArithmetic(Opc, VT,
538 cast<ConstantSDNode>(N1.getOperand(1)),
539 cast<ConstantSDNode>(N0));
540 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
541 } else if (N1.hasOneUse()) {
542 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
543 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
544 N1.getOperand(0), N0);
545 AddToWorkList(OpNode.getNode());
546 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
553 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
555 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
557 DEBUG(dbgs() << "\nReplacing.1 ";
559 dbgs() << "\nWith: ";
560 To[0].getNode()->dump(&DAG);
561 dbgs() << " and " << NumTo-1 << " other values\n";
562 for (unsigned i = 0, e = NumTo; i != e; ++i)
563 assert((!To[i].getNode() ||
564 N->getValueType(i) == To[i].getValueType()) &&
565 "Cannot combine value to value of different type!"));
566 WorkListRemover DeadNodes(*this);
567 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
570 // Push the new nodes and any users onto the worklist
571 for (unsigned i = 0, e = NumTo; i != e; ++i) {
572 if (To[i].getNode()) {
573 AddToWorkList(To[i].getNode());
574 AddUsersToWorkList(To[i].getNode());
579 // Finally, if the node is now dead, remove it from the graph. The node
580 // may not be dead if the replacement process recursively simplified to
581 // something else needing this node.
582 if (N->use_empty()) {
583 // Nodes can be reintroduced into the worklist. Make sure we do not
584 // process a node that has been replaced.
585 removeFromWorkList(N);
587 // Finally, since the node is now dead, remove it from the graph.
590 return SDValue(N, 0);
594 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
595 // Replace all uses. If any nodes become isomorphic to other nodes and
596 // are deleted, make sure to remove them from our worklist.
597 WorkListRemover DeadNodes(*this);
598 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
600 // Push the new node and any (possibly new) users onto the worklist.
601 AddToWorkList(TLO.New.getNode());
602 AddUsersToWorkList(TLO.New.getNode());
604 // Finally, if the node is now dead, remove it from the graph. The node
605 // may not be dead if the replacement process recursively simplified to
606 // something else needing this node.
607 if (TLO.Old.getNode()->use_empty()) {
608 removeFromWorkList(TLO.Old.getNode());
610 // If the operands of this node are only used by the node, they will now
611 // be dead. Make sure to visit them first to delete dead nodes early.
612 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
613 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
614 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
616 DAG.DeleteNode(TLO.Old.getNode());
620 /// SimplifyDemandedBits - Check the specified integer node value to see if
621 /// it can be simplified or if things it uses can be simplified by bit
622 /// propagation. If so, return true.
623 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
624 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
625 APInt KnownZero, KnownOne;
626 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
630 AddToWorkList(Op.getNode());
632 // Replace the old value with the new one.
634 DEBUG(dbgs() << "\nReplacing.2 ";
635 TLO.Old.getNode()->dump(&DAG);
636 dbgs() << "\nWith: ";
637 TLO.New.getNode()->dump(&DAG);
640 CommitTargetLoweringOpt(TLO);
644 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
645 DebugLoc dl = Load->getDebugLoc();
646 EVT VT = Load->getValueType(0);
647 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
649 DEBUG(dbgs() << "\nReplacing.9 ";
651 dbgs() << "\nWith: ";
652 Trunc.getNode()->dump(&DAG);
654 WorkListRemover DeadNodes(*this);
655 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes);
656 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1),
658 removeFromWorkList(Load);
659 DAG.DeleteNode(Load);
660 AddToWorkList(Trunc.getNode());
663 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
665 DebugLoc dl = Op.getDebugLoc();
666 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
667 EVT MemVT = LD->getMemoryVT();
668 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
669 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD)
670 : LD->getExtensionType();
672 return DAG.getExtLoad(ExtType, dl, PVT,
673 LD->getChain(), LD->getBasePtr(),
674 LD->getSrcValue(), LD->getSrcValueOffset(),
675 MemVT, LD->isVolatile(),
676 LD->isNonTemporal(), LD->getAlignment());
679 unsigned Opc = Op.getOpcode();
682 case ISD::AssertSext:
683 return DAG.getNode(ISD::AssertSext, dl, PVT,
684 SExtPromoteOperand(Op.getOperand(0), PVT),
686 case ISD::AssertZext:
687 return DAG.getNode(ISD::AssertZext, dl, PVT,
688 ZExtPromoteOperand(Op.getOperand(0), PVT),
690 case ISD::Constant: {
692 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
693 return DAG.getNode(ExtOpc, dl, PVT, Op);
697 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
699 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
702 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
703 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
705 EVT OldVT = Op.getValueType();
706 DebugLoc dl = Op.getDebugLoc();
707 bool Replace = false;
708 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
709 if (NewOp.getNode() == 0)
711 AddToWorkList(NewOp.getNode());
714 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
715 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
716 DAG.getValueType(OldVT));
719 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
720 EVT OldVT = Op.getValueType();
721 DebugLoc dl = Op.getDebugLoc();
722 bool Replace = false;
723 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
724 if (NewOp.getNode() == 0)
726 AddToWorkList(NewOp.getNode());
729 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
730 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
733 /// PromoteIntBinOp - Promote the specified integer binary operation if the
734 /// target indicates it is beneficial. e.g. On x86, it's usually better to
735 /// promote i16 operations to i32 since i16 instructions are longer.
736 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
737 if (!LegalOperations)
740 EVT VT = Op.getValueType();
741 if (VT.isVector() || !VT.isInteger())
744 // If operation type is 'undesirable', e.g. i16 on x86, consider
746 unsigned Opc = Op.getOpcode();
747 if (TLI.isTypeDesirableForOp(Opc, VT))
751 // Consult target whether it is a good idea to promote this operation and
752 // what's the right type to promote it to.
753 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
754 assert(PVT != VT && "Don't know what type to promote to!");
756 bool Replace0 = false;
757 SDValue N0 = Op.getOperand(0);
758 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
759 if (NN0.getNode() == 0)
762 bool Replace1 = false;
763 SDValue N1 = Op.getOperand(1);
768 NN1 = PromoteOperand(N1, PVT, Replace1);
769 if (NN1.getNode() == 0)
773 AddToWorkList(NN0.getNode());
775 AddToWorkList(NN1.getNode());
778 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
780 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
782 DEBUG(dbgs() << "\nPromoting ";
783 Op.getNode()->dump(&DAG));
784 DebugLoc dl = Op.getDebugLoc();
785 return DAG.getNode(ISD::TRUNCATE, dl, VT,
786 DAG.getNode(Opc, dl, PVT, NN0, NN1));
791 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
792 /// target indicates it is beneficial. e.g. On x86, it's usually better to
793 /// promote i16 operations to i32 since i16 instructions are longer.
794 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
795 if (!LegalOperations)
798 EVT VT = Op.getValueType();
799 if (VT.isVector() || !VT.isInteger())
802 // If operation type is 'undesirable', e.g. i16 on x86, consider
804 unsigned Opc = Op.getOpcode();
805 if (TLI.isTypeDesirableForOp(Opc, VT))
809 // Consult target whether it is a good idea to promote this operation and
810 // what's the right type to promote it to.
811 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
812 assert(PVT != VT && "Don't know what type to promote to!");
814 bool Replace = false;
815 SDValue N0 = Op.getOperand(0);
817 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
818 else if (Opc == ISD::SRL)
819 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
821 N0 = PromoteOperand(N0, PVT, Replace);
822 if (N0.getNode() == 0)
825 AddToWorkList(N0.getNode());
827 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
829 DEBUG(dbgs() << "\nPromoting ";
830 Op.getNode()->dump(&DAG));
831 DebugLoc dl = Op.getDebugLoc();
832 return DAG.getNode(ISD::TRUNCATE, dl, VT,
833 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
838 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
839 if (!LegalOperations)
842 EVT VT = Op.getValueType();
843 if (VT.isVector() || !VT.isInteger())
846 // If operation type is 'undesirable', e.g. i16 on x86, consider
848 unsigned Opc = Op.getOpcode();
849 if (TLI.isTypeDesirableForOp(Opc, VT))
853 // Consult target whether it is a good idea to promote this operation and
854 // what's the right type to promote it to.
855 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
856 assert(PVT != VT && "Don't know what type to promote to!");
857 // fold (aext (aext x)) -> (aext x)
858 // fold (aext (zext x)) -> (zext x)
859 // fold (aext (sext x)) -> (sext x)
860 DEBUG(dbgs() << "\nPromoting ";
861 Op.getNode()->dump(&DAG));
862 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
867 bool DAGCombiner::PromoteLoad(SDValue Op) {
868 if (!LegalOperations)
871 EVT VT = Op.getValueType();
872 if (VT.isVector() || !VT.isInteger())
875 // If operation type is 'undesirable', e.g. i16 on x86, consider
877 unsigned Opc = Op.getOpcode();
878 if (TLI.isTypeDesirableForOp(Opc, VT))
882 // Consult target whether it is a good idea to promote this operation and
883 // what's the right type to promote it to.
884 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
885 assert(PVT != VT && "Don't know what type to promote to!");
887 DebugLoc dl = Op.getDebugLoc();
888 SDNode *N = Op.getNode();
889 LoadSDNode *LD = cast<LoadSDNode>(N);
890 EVT MemVT = LD->getMemoryVT();
891 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
892 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD)
893 : LD->getExtensionType();
894 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
895 LD->getChain(), LD->getBasePtr(),
896 LD->getSrcValue(), LD->getSrcValueOffset(),
897 MemVT, LD->isVolatile(),
898 LD->isNonTemporal(), LD->getAlignment());
899 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
901 DEBUG(dbgs() << "\nPromoting ";
904 Result.getNode()->dump(&DAG);
906 WorkListRemover DeadNodes(*this);
907 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes);
908 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes);
909 removeFromWorkList(N);
911 AddToWorkList(Result.getNode());
918 //===----------------------------------------------------------------------===//
919 // Main DAG Combiner implementation
920 //===----------------------------------------------------------------------===//
922 void DAGCombiner::Run(CombineLevel AtLevel) {
923 // set the instance variables, so that the various visit routines may use it.
925 LegalOperations = Level >= NoIllegalOperations;
926 LegalTypes = Level >= NoIllegalTypes;
928 // Add all the dag nodes to the worklist.
929 WorkList.reserve(DAG.allnodes_size());
930 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
931 E = DAG.allnodes_end(); I != E; ++I)
932 WorkList.push_back(I);
934 // Create a dummy node (which is not added to allnodes), that adds a reference
935 // to the root node, preventing it from being deleted, and tracking any
936 // changes of the root.
937 HandleSDNode Dummy(DAG.getRoot());
939 // The root of the dag may dangle to deleted nodes until the dag combiner is
940 // done. Set it to null to avoid confusion.
941 DAG.setRoot(SDValue());
943 // while the worklist isn't empty, inspect the node on the end of it and
944 // try and combine it.
945 while (!WorkList.empty()) {
946 SDNode *N = WorkList.back();
949 // If N has no uses, it is dead. Make sure to revisit all N's operands once
950 // N is deleted from the DAG, since they too may now be dead or may have a
951 // reduced number of uses, allowing other xforms.
952 if (N->use_empty() && N != &Dummy) {
953 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
954 AddToWorkList(N->getOperand(i).getNode());
960 SDValue RV = combine(N);
962 if (RV.getNode() == 0)
967 // If we get back the same node we passed in, rather than a new node or
968 // zero, we know that the node must have defined multiple values and
969 // CombineTo was used. Since CombineTo takes care of the worklist
970 // mechanics for us, we have no work to do in this case.
971 if (RV.getNode() == N)
974 assert(N->getOpcode() != ISD::DELETED_NODE &&
975 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
976 "Node was deleted but visit returned new node!");
978 DEBUG(dbgs() << "\nReplacing.3 ";
980 dbgs() << "\nWith: ";
981 RV.getNode()->dump(&DAG);
983 WorkListRemover DeadNodes(*this);
984 if (N->getNumValues() == RV.getNode()->getNumValues())
985 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
987 assert(N->getValueType(0) == RV.getValueType() &&
988 N->getNumValues() == 1 && "Type mismatch");
990 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
993 // Push the new node and any users onto the worklist
994 AddToWorkList(RV.getNode());
995 AddUsersToWorkList(RV.getNode());
997 // Add any uses of the old node to the worklist in case this node is the
998 // last one that uses them. They may become dead after this node is
1000 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1001 AddToWorkList(N->getOperand(i).getNode());
1003 // Finally, if the node is now dead, remove it from the graph. The node
1004 // may not be dead if the replacement process recursively simplified to
1005 // something else needing this node.
1006 if (N->use_empty()) {
1007 // Nodes can be reintroduced into the worklist. Make sure we do not
1008 // process a node that has been replaced.
1009 removeFromWorkList(N);
1011 // Finally, since the node is now dead, remove it from the graph.
1016 // If the root changed (e.g. it was a dead load, update the root).
1017 DAG.setRoot(Dummy.getValue());
1020 SDValue DAGCombiner::visit(SDNode *N) {
1021 switch (N->getOpcode()) {
1023 case ISD::TokenFactor: return visitTokenFactor(N);
1024 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1025 case ISD::ADD: return visitADD(N);
1026 case ISD::SUB: return visitSUB(N);
1027 case ISD::ADDC: return visitADDC(N);
1028 case ISD::ADDE: return visitADDE(N);
1029 case ISD::MUL: return visitMUL(N);
1030 case ISD::SDIV: return visitSDIV(N);
1031 case ISD::UDIV: return visitUDIV(N);
1032 case ISD::SREM: return visitSREM(N);
1033 case ISD::UREM: return visitUREM(N);
1034 case ISD::MULHU: return visitMULHU(N);
1035 case ISD::MULHS: return visitMULHS(N);
1036 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1037 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1038 case ISD::SDIVREM: return visitSDIVREM(N);
1039 case ISD::UDIVREM: return visitUDIVREM(N);
1040 case ISD::AND: return visitAND(N);
1041 case ISD::OR: return visitOR(N);
1042 case ISD::XOR: return visitXOR(N);
1043 case ISD::SHL: return visitSHL(N);
1044 case ISD::SRA: return visitSRA(N);
1045 case ISD::SRL: return visitSRL(N);
1046 case ISD::CTLZ: return visitCTLZ(N);
1047 case ISD::CTTZ: return visitCTTZ(N);
1048 case ISD::CTPOP: return visitCTPOP(N);
1049 case ISD::SELECT: return visitSELECT(N);
1050 case ISD::SELECT_CC: return visitSELECT_CC(N);
1051 case ISD::SETCC: return visitSETCC(N);
1052 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1053 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1054 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1055 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1056 case ISD::TRUNCATE: return visitTRUNCATE(N);
1057 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
1058 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1059 case ISD::FADD: return visitFADD(N);
1060 case ISD::FSUB: return visitFSUB(N);
1061 case ISD::FMUL: return visitFMUL(N);
1062 case ISD::FDIV: return visitFDIV(N);
1063 case ISD::FREM: return visitFREM(N);
1064 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1065 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1066 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1067 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1068 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1069 case ISD::FP_ROUND: return visitFP_ROUND(N);
1070 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1071 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1072 case ISD::FNEG: return visitFNEG(N);
1073 case ISD::FABS: return visitFABS(N);
1074 case ISD::BRCOND: return visitBRCOND(N);
1075 case ISD::BR_CC: return visitBR_CC(N);
1076 case ISD::LOAD: return visitLOAD(N);
1077 case ISD::STORE: return visitSTORE(N);
1078 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1079 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1080 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1081 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1082 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1083 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1088 SDValue DAGCombiner::combine(SDNode *N) {
1089 SDValue RV = visit(N);
1091 // If nothing happened, try a target-specific DAG combine.
1092 if (RV.getNode() == 0) {
1093 assert(N->getOpcode() != ISD::DELETED_NODE &&
1094 "Node was deleted but visit returned NULL!");
1096 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1097 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1099 // Expose the DAG combiner to the target combiner impls.
1100 TargetLowering::DAGCombinerInfo
1101 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1103 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1107 // If nothing happened still, try promoting the operation.
1108 if (RV.getNode() == 0) {
1109 switch (N->getOpcode()) {
1117 RV = PromoteIntBinOp(SDValue(N, 0));
1122 RV = PromoteIntShiftOp(SDValue(N, 0));
1124 case ISD::SIGN_EXTEND:
1125 case ISD::ZERO_EXTEND:
1126 case ISD::ANY_EXTEND:
1127 RV = PromoteExtend(SDValue(N, 0));
1130 if (PromoteLoad(SDValue(N, 0)))
1136 // If N is a commutative binary node, try commuting it to enable more
1138 if (RV.getNode() == 0 &&
1139 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1140 N->getNumValues() == 1) {
1141 SDValue N0 = N->getOperand(0);
1142 SDValue N1 = N->getOperand(1);
1144 // Constant operands are canonicalized to RHS.
1145 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1146 SDValue Ops[] = { N1, N0 };
1147 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1150 return SDValue(CSENode, 0);
1157 /// getInputChainForNode - Given a node, return its input chain if it has one,
1158 /// otherwise return a null sd operand.
1159 static SDValue getInputChainForNode(SDNode *N) {
1160 if (unsigned NumOps = N->getNumOperands()) {
1161 if (N->getOperand(0).getValueType() == MVT::Other)
1162 return N->getOperand(0);
1163 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1164 return N->getOperand(NumOps-1);
1165 for (unsigned i = 1; i < NumOps-1; ++i)
1166 if (N->getOperand(i).getValueType() == MVT::Other)
1167 return N->getOperand(i);
1172 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1173 // If N has two operands, where one has an input chain equal to the other,
1174 // the 'other' chain is redundant.
1175 if (N->getNumOperands() == 2) {
1176 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1177 return N->getOperand(0);
1178 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1179 return N->getOperand(1);
1182 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1183 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1184 SmallPtrSet<SDNode*, 16> SeenOps;
1185 bool Changed = false; // If we should replace this token factor.
1187 // Start out with this token factor.
1190 // Iterate through token factors. The TFs grows when new token factors are
1192 for (unsigned i = 0; i < TFs.size(); ++i) {
1193 SDNode *TF = TFs[i];
1195 // Check each of the operands.
1196 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1197 SDValue Op = TF->getOperand(i);
1199 switch (Op.getOpcode()) {
1200 case ISD::EntryToken:
1201 // Entry tokens don't need to be added to the list. They are
1206 case ISD::TokenFactor:
1207 if (Op.hasOneUse() &&
1208 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1209 // Queue up for processing.
1210 TFs.push_back(Op.getNode());
1211 // Clean up in case the token factor is removed.
1212 AddToWorkList(Op.getNode());
1219 // Only add if it isn't already in the list.
1220 if (SeenOps.insert(Op.getNode()))
1231 // If we've change things around then replace token factor.
1234 // The entry token is the only possible outcome.
1235 Result = DAG.getEntryNode();
1237 // New and improved token factor.
1238 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1239 MVT::Other, &Ops[0], Ops.size());
1242 // Don't add users to work list.
1243 return CombineTo(N, Result, false);
1249 /// MERGE_VALUES can always be eliminated.
1250 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1251 WorkListRemover DeadNodes(*this);
1252 // Replacing results may cause a different MERGE_VALUES to suddenly
1253 // be CSE'd with N, and carry its uses with it. Iterate until no
1254 // uses remain, to ensure that the node can be safely deleted.
1256 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1257 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
1259 } while (!N->use_empty());
1260 removeFromWorkList(N);
1262 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1266 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1267 SelectionDAG &DAG) {
1268 EVT VT = N0.getValueType();
1269 SDValue N00 = N0.getOperand(0);
1270 SDValue N01 = N0.getOperand(1);
1271 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1273 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1274 isa<ConstantSDNode>(N00.getOperand(1))) {
1275 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1276 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1277 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1278 N00.getOperand(0), N01),
1279 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1280 N00.getOperand(1), N01));
1281 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1287 SDValue DAGCombiner::visitADD(SDNode *N) {
1288 SDValue N0 = N->getOperand(0);
1289 SDValue N1 = N->getOperand(1);
1290 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1291 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1292 EVT VT = N0.getValueType();
1295 if (VT.isVector()) {
1296 SDValue FoldedVOp = SimplifyVBinOp(N);
1297 if (FoldedVOp.getNode()) return FoldedVOp;
1300 // fold (add x, undef) -> undef
1301 if (N0.getOpcode() == ISD::UNDEF)
1303 if (N1.getOpcode() == ISD::UNDEF)
1305 // fold (add c1, c2) -> c1+c2
1307 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1308 // canonicalize constant to RHS
1310 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1311 // fold (add x, 0) -> x
1312 if (N1C && N1C->isNullValue())
1314 // fold (add Sym, c) -> Sym+c
1315 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1316 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1317 GA->getOpcode() == ISD::GlobalAddress)
1318 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1320 (uint64_t)N1C->getSExtValue());
1321 // fold ((c1-A)+c2) -> (c1+c2)-A
1322 if (N1C && N0.getOpcode() == ISD::SUB)
1323 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1324 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1325 DAG.getConstant(N1C->getAPIntValue()+
1326 N0C->getAPIntValue(), VT),
1329 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1330 if (RADD.getNode() != 0)
1332 // fold ((0-A) + B) -> B-A
1333 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1334 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1335 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1336 // fold (A + (0-B)) -> A-B
1337 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1338 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1339 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1340 // fold (A+(B-A)) -> B
1341 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1342 return N1.getOperand(0);
1343 // fold ((B-A)+A) -> B
1344 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1345 return N0.getOperand(0);
1346 // fold (A+(B-(A+C))) to (B-C)
1347 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1348 N0 == N1.getOperand(1).getOperand(0))
1349 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1350 N1.getOperand(1).getOperand(1));
1351 // fold (A+(B-(C+A))) to (B-C)
1352 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1353 N0 == N1.getOperand(1).getOperand(1))
1354 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1355 N1.getOperand(1).getOperand(0));
1356 // fold (A+((B-A)+or-C)) to (B+or-C)
1357 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1358 N1.getOperand(0).getOpcode() == ISD::SUB &&
1359 N0 == N1.getOperand(0).getOperand(1))
1360 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1361 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1363 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1364 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1365 SDValue N00 = N0.getOperand(0);
1366 SDValue N01 = N0.getOperand(1);
1367 SDValue N10 = N1.getOperand(0);
1368 SDValue N11 = N1.getOperand(1);
1370 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1371 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1372 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1373 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1376 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1377 return SDValue(N, 0);
1379 // fold (a+b) -> (a|b) iff a and b share no bits.
1380 if (VT.isInteger() && !VT.isVector()) {
1381 APInt LHSZero, LHSOne;
1382 APInt RHSZero, RHSOne;
1383 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1384 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1386 if (LHSZero.getBoolValue()) {
1387 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1389 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1390 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1391 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1392 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1393 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1397 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1398 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1399 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1400 if (Result.getNode()) return Result;
1402 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1403 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1404 if (Result.getNode()) return Result;
1407 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1408 if (N1.getOpcode() == ISD::SHL &&
1409 N1.getOperand(0).getOpcode() == ISD::SUB)
1410 if (ConstantSDNode *C =
1411 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1412 if (C->getAPIntValue() == 0)
1413 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1414 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1415 N1.getOperand(0).getOperand(1),
1417 if (N0.getOpcode() == ISD::SHL &&
1418 N0.getOperand(0).getOpcode() == ISD::SUB)
1419 if (ConstantSDNode *C =
1420 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1421 if (C->getAPIntValue() == 0)
1422 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1423 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1424 N0.getOperand(0).getOperand(1),
1430 SDValue DAGCombiner::visitADDC(SDNode *N) {
1431 SDValue N0 = N->getOperand(0);
1432 SDValue N1 = N->getOperand(1);
1433 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1434 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1435 EVT VT = N0.getValueType();
1437 // If the flag result is dead, turn this into an ADD.
1438 if (N->hasNUsesOfValue(0, 1))
1439 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1440 DAG.getNode(ISD::CARRY_FALSE,
1441 N->getDebugLoc(), MVT::Flag));
1443 // canonicalize constant to RHS.
1445 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1447 // fold (addc x, 0) -> x + no carry out
1448 if (N1C && N1C->isNullValue())
1449 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1450 N->getDebugLoc(), MVT::Flag));
1452 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1453 APInt LHSZero, LHSOne;
1454 APInt RHSZero, RHSOne;
1455 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1456 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1458 if (LHSZero.getBoolValue()) {
1459 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1461 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1462 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1463 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1464 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1465 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1466 DAG.getNode(ISD::CARRY_FALSE,
1467 N->getDebugLoc(), MVT::Flag));
1473 SDValue DAGCombiner::visitADDE(SDNode *N) {
1474 SDValue N0 = N->getOperand(0);
1475 SDValue N1 = N->getOperand(1);
1476 SDValue CarryIn = N->getOperand(2);
1477 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1478 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1480 // canonicalize constant to RHS
1482 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1485 // fold (adde x, y, false) -> (addc x, y)
1486 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1487 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1492 SDValue DAGCombiner::visitSUB(SDNode *N) {
1493 SDValue N0 = N->getOperand(0);
1494 SDValue N1 = N->getOperand(1);
1495 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1496 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1497 EVT VT = N0.getValueType();
1500 if (VT.isVector()) {
1501 SDValue FoldedVOp = SimplifyVBinOp(N);
1502 if (FoldedVOp.getNode()) return FoldedVOp;
1505 // fold (sub x, x) -> 0
1507 return DAG.getConstant(0, N->getValueType(0));
1508 // fold (sub c1, c2) -> c1-c2
1510 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1511 // fold (sub x, c) -> (add x, -c)
1513 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1514 DAG.getConstant(-N1C->getAPIntValue(), VT));
1515 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1516 if (N0C && N0C->isAllOnesValue())
1517 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1518 // fold (A+B)-A -> B
1519 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1520 return N0.getOperand(1);
1521 // fold (A+B)-B -> A
1522 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1523 return N0.getOperand(0);
1524 // fold ((A+(B+or-C))-B) -> A+or-C
1525 if (N0.getOpcode() == ISD::ADD &&
1526 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1527 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1528 N0.getOperand(1).getOperand(0) == N1)
1529 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1530 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1531 // fold ((A+(C+B))-B) -> A+C
1532 if (N0.getOpcode() == ISD::ADD &&
1533 N0.getOperand(1).getOpcode() == ISD::ADD &&
1534 N0.getOperand(1).getOperand(1) == N1)
1535 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1536 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1537 // fold ((A-(B-C))-C) -> A-B
1538 if (N0.getOpcode() == ISD::SUB &&
1539 N0.getOperand(1).getOpcode() == ISD::SUB &&
1540 N0.getOperand(1).getOperand(1) == N1)
1541 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1542 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1544 // If either operand of a sub is undef, the result is undef
1545 if (N0.getOpcode() == ISD::UNDEF)
1547 if (N1.getOpcode() == ISD::UNDEF)
1550 // If the relocation model supports it, consider symbol offsets.
1551 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1552 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1553 // fold (sub Sym, c) -> Sym-c
1554 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1555 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1557 (uint64_t)N1C->getSExtValue());
1558 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1559 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1560 if (GA->getGlobal() == GB->getGlobal())
1561 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1568 SDValue DAGCombiner::visitMUL(SDNode *N) {
1569 SDValue N0 = N->getOperand(0);
1570 SDValue N1 = N->getOperand(1);
1571 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1572 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1573 EVT VT = N0.getValueType();
1576 if (VT.isVector()) {
1577 SDValue FoldedVOp = SimplifyVBinOp(N);
1578 if (FoldedVOp.getNode()) return FoldedVOp;
1581 // fold (mul x, undef) -> 0
1582 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1583 return DAG.getConstant(0, VT);
1584 // fold (mul c1, c2) -> c1*c2
1586 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1587 // canonicalize constant to RHS
1589 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1590 // fold (mul x, 0) -> 0
1591 if (N1C && N1C->isNullValue())
1593 // fold (mul x, -1) -> 0-x
1594 if (N1C && N1C->isAllOnesValue())
1595 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1596 DAG.getConstant(0, VT), N0);
1597 // fold (mul x, (1 << c)) -> x << c
1598 if (N1C && N1C->getAPIntValue().isPowerOf2())
1599 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1600 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1601 getShiftAmountTy()));
1602 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1603 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1604 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1605 // FIXME: If the input is something that is easily negated (e.g. a
1606 // single-use add), we should put the negate there.
1607 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1608 DAG.getConstant(0, VT),
1609 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1610 DAG.getConstant(Log2Val, getShiftAmountTy())));
1612 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1613 if (N1C && N0.getOpcode() == ISD::SHL &&
1614 isa<ConstantSDNode>(N0.getOperand(1))) {
1615 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1616 N1, N0.getOperand(1));
1617 AddToWorkList(C3.getNode());
1618 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1619 N0.getOperand(0), C3);
1622 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1625 SDValue Sh(0,0), Y(0,0);
1626 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1627 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1628 N0.getNode()->hasOneUse()) {
1630 } else if (N1.getOpcode() == ISD::SHL &&
1631 isa<ConstantSDNode>(N1.getOperand(1)) &&
1632 N1.getNode()->hasOneUse()) {
1637 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1638 Sh.getOperand(0), Y);
1639 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1640 Mul, Sh.getOperand(1));
1644 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1645 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1646 isa<ConstantSDNode>(N0.getOperand(1)))
1647 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1648 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1649 N0.getOperand(0), N1),
1650 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1651 N0.getOperand(1), N1));
1654 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1655 if (RMUL.getNode() != 0)
1661 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1662 SDValue N0 = N->getOperand(0);
1663 SDValue N1 = N->getOperand(1);
1664 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1665 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1666 EVT VT = N->getValueType(0);
1669 if (VT.isVector()) {
1670 SDValue FoldedVOp = SimplifyVBinOp(N);
1671 if (FoldedVOp.getNode()) return FoldedVOp;
1674 // fold (sdiv c1, c2) -> c1/c2
1675 if (N0C && N1C && !N1C->isNullValue())
1676 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1677 // fold (sdiv X, 1) -> X
1678 if (N1C && N1C->getSExtValue() == 1LL)
1680 // fold (sdiv X, -1) -> 0-X
1681 if (N1C && N1C->isAllOnesValue())
1682 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1683 DAG.getConstant(0, VT), N0);
1684 // If we know the sign bits of both operands are zero, strength reduce to a
1685 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1686 if (!VT.isVector()) {
1687 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1688 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1691 // fold (sdiv X, pow2) -> simple ops after legalize
1692 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1693 (isPowerOf2_64(N1C->getSExtValue()) ||
1694 isPowerOf2_64(-N1C->getSExtValue()))) {
1695 // If dividing by powers of two is cheap, then don't perform the following
1697 if (TLI.isPow2DivCheap())
1700 int64_t pow2 = N1C->getSExtValue();
1701 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1702 unsigned lg2 = Log2_64(abs2);
1704 // Splat the sign bit into the register
1705 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1706 DAG.getConstant(VT.getSizeInBits()-1,
1707 getShiftAmountTy()));
1708 AddToWorkList(SGN.getNode());
1710 // Add (N0 < 0) ? abs2 - 1 : 0;
1711 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1712 DAG.getConstant(VT.getSizeInBits() - lg2,
1713 getShiftAmountTy()));
1714 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1715 AddToWorkList(SRL.getNode());
1716 AddToWorkList(ADD.getNode()); // Divide by pow2
1717 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1718 DAG.getConstant(lg2, getShiftAmountTy()));
1720 // If we're dividing by a positive value, we're done. Otherwise, we must
1721 // negate the result.
1725 AddToWorkList(SRA.getNode());
1726 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1727 DAG.getConstant(0, VT), SRA);
1730 // if integer divide is expensive and we satisfy the requirements, emit an
1731 // alternate sequence.
1732 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1733 !TLI.isIntDivCheap()) {
1734 SDValue Op = BuildSDIV(N);
1735 if (Op.getNode()) return Op;
1739 if (N0.getOpcode() == ISD::UNDEF)
1740 return DAG.getConstant(0, VT);
1741 // X / undef -> undef
1742 if (N1.getOpcode() == ISD::UNDEF)
1748 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1749 SDValue N0 = N->getOperand(0);
1750 SDValue N1 = N->getOperand(1);
1751 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1752 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1753 EVT VT = N->getValueType(0);
1756 if (VT.isVector()) {
1757 SDValue FoldedVOp = SimplifyVBinOp(N);
1758 if (FoldedVOp.getNode()) return FoldedVOp;
1761 // fold (udiv c1, c2) -> c1/c2
1762 if (N0C && N1C && !N1C->isNullValue())
1763 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1764 // fold (udiv x, (1 << c)) -> x >>u c
1765 if (N1C && N1C->getAPIntValue().isPowerOf2())
1766 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1767 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1768 getShiftAmountTy()));
1769 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1770 if (N1.getOpcode() == ISD::SHL) {
1771 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1772 if (SHC->getAPIntValue().isPowerOf2()) {
1773 EVT ADDVT = N1.getOperand(1).getValueType();
1774 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1776 DAG.getConstant(SHC->getAPIntValue()
1779 AddToWorkList(Add.getNode());
1780 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1784 // fold (udiv x, c) -> alternate
1785 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1786 SDValue Op = BuildUDIV(N);
1787 if (Op.getNode()) return Op;
1791 if (N0.getOpcode() == ISD::UNDEF)
1792 return DAG.getConstant(0, VT);
1793 // X / undef -> undef
1794 if (N1.getOpcode() == ISD::UNDEF)
1800 SDValue DAGCombiner::visitSREM(SDNode *N) {
1801 SDValue N0 = N->getOperand(0);
1802 SDValue N1 = N->getOperand(1);
1803 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1804 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1805 EVT VT = N->getValueType(0);
1807 // fold (srem c1, c2) -> c1%c2
1808 if (N0C && N1C && !N1C->isNullValue())
1809 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1810 // If we know the sign bits of both operands are zero, strength reduce to a
1811 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1812 if (!VT.isVector()) {
1813 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1814 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1817 // If X/C can be simplified by the division-by-constant logic, lower
1818 // X%C to the equivalent of X-X/C*C.
1819 if (N1C && !N1C->isNullValue()) {
1820 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1821 AddToWorkList(Div.getNode());
1822 SDValue OptimizedDiv = combine(Div.getNode());
1823 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1824 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1826 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1827 AddToWorkList(Mul.getNode());
1833 if (N0.getOpcode() == ISD::UNDEF)
1834 return DAG.getConstant(0, VT);
1835 // X % undef -> undef
1836 if (N1.getOpcode() == ISD::UNDEF)
1842 SDValue DAGCombiner::visitUREM(SDNode *N) {
1843 SDValue N0 = N->getOperand(0);
1844 SDValue N1 = N->getOperand(1);
1845 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1846 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1847 EVT VT = N->getValueType(0);
1849 // fold (urem c1, c2) -> c1%c2
1850 if (N0C && N1C && !N1C->isNullValue())
1851 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1852 // fold (urem x, pow2) -> (and x, pow2-1)
1853 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1854 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1855 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1856 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1857 if (N1.getOpcode() == ISD::SHL) {
1858 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1859 if (SHC->getAPIntValue().isPowerOf2()) {
1861 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1862 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1864 AddToWorkList(Add.getNode());
1865 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1870 // If X/C can be simplified by the division-by-constant logic, lower
1871 // X%C to the equivalent of X-X/C*C.
1872 if (N1C && !N1C->isNullValue()) {
1873 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1874 AddToWorkList(Div.getNode());
1875 SDValue OptimizedDiv = combine(Div.getNode());
1876 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1877 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1879 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1880 AddToWorkList(Mul.getNode());
1886 if (N0.getOpcode() == ISD::UNDEF)
1887 return DAG.getConstant(0, VT);
1888 // X % undef -> undef
1889 if (N1.getOpcode() == ISD::UNDEF)
1895 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1896 SDValue N0 = N->getOperand(0);
1897 SDValue N1 = N->getOperand(1);
1898 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1899 EVT VT = N->getValueType(0);
1901 // fold (mulhs x, 0) -> 0
1902 if (N1C && N1C->isNullValue())
1904 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1905 if (N1C && N1C->getAPIntValue() == 1)
1906 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1907 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1908 getShiftAmountTy()));
1909 // fold (mulhs x, undef) -> 0
1910 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1911 return DAG.getConstant(0, VT);
1916 SDValue DAGCombiner::visitMULHU(SDNode *N) {
1917 SDValue N0 = N->getOperand(0);
1918 SDValue N1 = N->getOperand(1);
1919 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1920 EVT VT = N->getValueType(0);
1922 // fold (mulhu x, 0) -> 0
1923 if (N1C && N1C->isNullValue())
1925 // fold (mulhu x, 1) -> 0
1926 if (N1C && N1C->getAPIntValue() == 1)
1927 return DAG.getConstant(0, N0.getValueType());
1928 // fold (mulhu x, undef) -> 0
1929 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1930 return DAG.getConstant(0, VT);
1935 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1936 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1937 /// that are being performed. Return true if a simplification was made.
1939 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1941 // If the high half is not needed, just compute the low half.
1942 bool HiExists = N->hasAnyUseOfValue(1);
1944 (!LegalOperations ||
1945 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1946 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1947 N->op_begin(), N->getNumOperands());
1948 return CombineTo(N, Res, Res);
1951 // If the low half is not needed, just compute the high half.
1952 bool LoExists = N->hasAnyUseOfValue(0);
1954 (!LegalOperations ||
1955 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1956 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1957 N->op_begin(), N->getNumOperands());
1958 return CombineTo(N, Res, Res);
1961 // If both halves are used, return as it is.
1962 if (LoExists && HiExists)
1965 // If the two computed results can be simplified separately, separate them.
1967 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1968 N->op_begin(), N->getNumOperands());
1969 AddToWorkList(Lo.getNode());
1970 SDValue LoOpt = combine(Lo.getNode());
1971 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
1972 (!LegalOperations ||
1973 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
1974 return CombineTo(N, LoOpt, LoOpt);
1978 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1979 N->op_begin(), N->getNumOperands());
1980 AddToWorkList(Hi.getNode());
1981 SDValue HiOpt = combine(Hi.getNode());
1982 if (HiOpt.getNode() && HiOpt != Hi &&
1983 (!LegalOperations ||
1984 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
1985 return CombineTo(N, HiOpt, HiOpt);
1991 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1992 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1993 if (Res.getNode()) return Res;
1998 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1999 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2000 if (Res.getNode()) return Res;
2005 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2006 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2007 if (Res.getNode()) return Res;
2012 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2013 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2014 if (Res.getNode()) return Res;
2019 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2020 /// two operands of the same opcode, try to simplify it.
2021 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2022 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2023 EVT VT = N0.getValueType();
2024 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2026 // Bail early if none of these transforms apply.
2027 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2029 // For each of OP in AND/OR/XOR:
2030 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2031 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2032 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2033 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2035 // do not sink logical op inside of a vector extend, since it may combine
2037 EVT Op0VT = N0.getOperand(0).getValueType();
2038 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2039 N0.getOpcode() == ISD::SIGN_EXTEND ||
2040 // Avoid infinite looping with PromoteIntBinOp.
2041 (N0.getOpcode() == ISD::ANY_EXTEND &&
2042 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2043 (N0.getOpcode() == ISD::TRUNCATE &&
2044 (!TLI.isZExtFree(VT, Op0VT) ||
2045 !TLI.isTruncateFree(Op0VT, VT)) &&
2046 TLI.isTypeLegal(Op0VT))) &&
2048 Op0VT == N1.getOperand(0).getValueType() &&
2049 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2050 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2051 N0.getOperand(0).getValueType(),
2052 N0.getOperand(0), N1.getOperand(0));
2053 AddToWorkList(ORNode.getNode());
2054 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2057 // For each of OP in SHL/SRL/SRA/AND...
2058 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2059 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2060 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2061 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2062 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2063 N0.getOperand(1) == N1.getOperand(1)) {
2064 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2065 N0.getOperand(0).getValueType(),
2066 N0.getOperand(0), N1.getOperand(0));
2067 AddToWorkList(ORNode.getNode());
2068 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2069 ORNode, N0.getOperand(1));
2075 SDValue DAGCombiner::visitAND(SDNode *N) {
2076 SDValue N0 = N->getOperand(0);
2077 SDValue N1 = N->getOperand(1);
2078 SDValue LL, LR, RL, RR, CC0, CC1;
2079 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2080 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2081 EVT VT = N1.getValueType();
2082 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2085 if (VT.isVector()) {
2086 SDValue FoldedVOp = SimplifyVBinOp(N);
2087 if (FoldedVOp.getNode()) return FoldedVOp;
2090 // fold (and x, undef) -> 0
2091 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2092 return DAG.getConstant(0, VT);
2093 // fold (and c1, c2) -> c1&c2
2095 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2096 // canonicalize constant to RHS
2098 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2099 // fold (and x, -1) -> x
2100 if (N1C && N1C->isAllOnesValue())
2102 // if (and x, c) is known to be zero, return 0
2103 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2104 APInt::getAllOnesValue(BitWidth)))
2105 return DAG.getConstant(0, VT);
2107 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2108 if (RAND.getNode() != 0)
2110 // fold (and (or x, C), D) -> D if (C & D) == D
2111 if (N1C && N0.getOpcode() == ISD::OR)
2112 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2113 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2115 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2116 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2117 SDValue N0Op0 = N0.getOperand(0);
2118 APInt Mask = ~N1C->getAPIntValue();
2119 Mask.trunc(N0Op0.getValueSizeInBits());
2120 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2121 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2122 N0.getValueType(), N0Op0);
2124 // Replace uses of the AND with uses of the Zero extend node.
2127 // We actually want to replace all uses of the any_extend with the
2128 // zero_extend, to avoid duplicating things. This will later cause this
2129 // AND to be folded.
2130 CombineTo(N0.getNode(), Zext);
2131 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2134 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2135 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2136 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2137 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2139 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2140 LL.getValueType().isInteger()) {
2141 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2142 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2143 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2144 LR.getValueType(), LL, RL);
2145 AddToWorkList(ORNode.getNode());
2146 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2148 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2149 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2150 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2151 LR.getValueType(), LL, RL);
2152 AddToWorkList(ANDNode.getNode());
2153 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2155 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2156 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2157 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2158 LR.getValueType(), LL, RL);
2159 AddToWorkList(ORNode.getNode());
2160 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2163 // canonicalize equivalent to ll == rl
2164 if (LL == RR && LR == RL) {
2165 Op1 = ISD::getSetCCSwappedOperands(Op1);
2168 if (LL == RL && LR == RR) {
2169 bool isInteger = LL.getValueType().isInteger();
2170 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2171 if (Result != ISD::SETCC_INVALID &&
2172 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2173 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2178 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2179 if (N0.getOpcode() == N1.getOpcode()) {
2180 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2181 if (Tmp.getNode()) return Tmp;
2184 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2185 // fold (and (sra)) -> (and (srl)) when possible.
2186 if (!VT.isVector() &&
2187 SimplifyDemandedBits(SDValue(N, 0)))
2188 return SDValue(N, 0);
2190 // fold (zext_inreg (extload x)) -> (zextload x)
2191 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2192 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2193 EVT MemVT = LN0->getMemoryVT();
2194 // If we zero all the possible extended bits, then we can turn this into
2195 // a zextload if we are running before legalize or the operation is legal.
2196 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2197 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2198 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2199 ((!LegalOperations && !LN0->isVolatile()) ||
2200 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2201 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2202 LN0->getChain(), LN0->getBasePtr(),
2204 LN0->getSrcValueOffset(), MemVT,
2205 LN0->isVolatile(), LN0->isNonTemporal(),
2206 LN0->getAlignment());
2208 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2209 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2212 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2213 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2215 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2216 EVT MemVT = LN0->getMemoryVT();
2217 // If we zero all the possible extended bits, then we can turn this into
2218 // a zextload if we are running before legalize or the operation is legal.
2219 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2220 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2221 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2222 ((!LegalOperations && !LN0->isVolatile()) ||
2223 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2224 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2226 LN0->getBasePtr(), LN0->getSrcValue(),
2227 LN0->getSrcValueOffset(), MemVT,
2228 LN0->isVolatile(), LN0->isNonTemporal(),
2229 LN0->getAlignment());
2231 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2232 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2236 // fold (and (load x), 255) -> (zextload x, i8)
2237 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2238 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2239 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2240 (N0.getOpcode() == ISD::ANY_EXTEND &&
2241 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2242 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2243 LoadSDNode *LN0 = HasAnyExt
2244 ? cast<LoadSDNode>(N0.getOperand(0))
2245 : cast<LoadSDNode>(N0);
2246 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2247 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2248 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2249 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2250 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2251 EVT LoadedVT = LN0->getMemoryVT();
2253 if (ExtVT == LoadedVT &&
2254 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2255 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2258 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2259 LN0->getChain(), LN0->getBasePtr(),
2260 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2261 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2262 LN0->getAlignment());
2264 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2265 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2268 // Do not change the width of a volatile load.
2269 // Do not generate loads of non-round integer types since these can
2270 // be expensive (and would be wrong if the type is not byte sized).
2271 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2272 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2273 EVT PtrType = LN0->getOperand(1).getValueType();
2275 unsigned Alignment = LN0->getAlignment();
2276 SDValue NewPtr = LN0->getBasePtr();
2278 // For big endian targets, we need to add an offset to the pointer
2279 // to load the correct bytes. For little endian systems, we merely
2280 // need to read fewer bytes from the same pointer.
2281 if (TLI.isBigEndian()) {
2282 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2283 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2284 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2285 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2286 NewPtr, DAG.getConstant(PtrOff, PtrType));
2287 Alignment = MinAlign(Alignment, PtrOff);
2290 AddToWorkList(NewPtr.getNode());
2292 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2294 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2295 LN0->getChain(), NewPtr,
2296 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2297 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2300 CombineTo(LN0, Load, Load.getValue(1));
2301 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2310 SDValue DAGCombiner::visitOR(SDNode *N) {
2311 SDValue N0 = N->getOperand(0);
2312 SDValue N1 = N->getOperand(1);
2313 SDValue LL, LR, RL, RR, CC0, CC1;
2314 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2315 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2316 EVT VT = N1.getValueType();
2319 if (VT.isVector()) {
2320 SDValue FoldedVOp = SimplifyVBinOp(N);
2321 if (FoldedVOp.getNode()) return FoldedVOp;
2324 // fold (or x, undef) -> -1
2325 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) {
2326 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2327 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2329 // fold (or c1, c2) -> c1|c2
2331 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2332 // canonicalize constant to RHS
2334 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2335 // fold (or x, 0) -> x
2336 if (N1C && N1C->isNullValue())
2338 // fold (or x, -1) -> -1
2339 if (N1C && N1C->isAllOnesValue())
2341 // fold (or x, c) -> c iff (x & ~c) == 0
2342 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2345 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2346 if (ROR.getNode() != 0)
2348 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2349 // iff (c1 & c2) == 0.
2350 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2351 isa<ConstantSDNode>(N0.getOperand(1))) {
2352 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2353 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2354 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2355 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2356 N0.getOperand(0), N1),
2357 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2359 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2360 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2361 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2362 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2364 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2365 LL.getValueType().isInteger()) {
2366 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2367 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2368 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2369 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2370 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2371 LR.getValueType(), LL, RL);
2372 AddToWorkList(ORNode.getNode());
2373 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2375 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2376 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2377 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2378 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2379 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2380 LR.getValueType(), LL, RL);
2381 AddToWorkList(ANDNode.getNode());
2382 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2385 // canonicalize equivalent to ll == rl
2386 if (LL == RR && LR == RL) {
2387 Op1 = ISD::getSetCCSwappedOperands(Op1);
2390 if (LL == RL && LR == RR) {
2391 bool isInteger = LL.getValueType().isInteger();
2392 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2393 if (Result != ISD::SETCC_INVALID &&
2394 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2395 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2400 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2401 if (N0.getOpcode() == N1.getOpcode()) {
2402 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2403 if (Tmp.getNode()) return Tmp;
2406 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2407 if (N0.getOpcode() == ISD::AND &&
2408 N1.getOpcode() == ISD::AND &&
2409 N0.getOperand(1).getOpcode() == ISD::Constant &&
2410 N1.getOperand(1).getOpcode() == ISD::Constant &&
2411 // Don't increase # computations.
2412 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2413 // We can only do this xform if we know that bits from X that are set in C2
2414 // but not in C1 are already zero. Likewise for Y.
2415 const APInt &LHSMask =
2416 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2417 const APInt &RHSMask =
2418 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2420 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2421 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2422 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2423 N0.getOperand(0), N1.getOperand(0));
2424 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2425 DAG.getConstant(LHSMask | RHSMask, VT));
2429 // See if this is some rotate idiom.
2430 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2431 return SDValue(Rot, 0);
2433 // Simplify the operands using demanded-bits information.
2434 if (!VT.isVector() &&
2435 SimplifyDemandedBits(SDValue(N, 0)))
2436 return SDValue(N, 0);
2441 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2442 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2443 if (Op.getOpcode() == ISD::AND) {
2444 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2445 Mask = Op.getOperand(1);
2446 Op = Op.getOperand(0);
2452 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2460 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2461 // idioms for rotate, and if the target supports rotation instructions, generate
2463 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2464 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2465 EVT VT = LHS.getValueType();
2466 if (!TLI.isTypeLegal(VT)) return 0;
2468 // The target must have at least one rotate flavor.
2469 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2470 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2471 if (!HasROTL && !HasROTR) return 0;
2473 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2474 SDValue LHSShift; // The shift.
2475 SDValue LHSMask; // AND value if any.
2476 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2477 return 0; // Not part of a rotate.
2479 SDValue RHSShift; // The shift.
2480 SDValue RHSMask; // AND value if any.
2481 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2482 return 0; // Not part of a rotate.
2484 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2485 return 0; // Not shifting the same value.
2487 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2488 return 0; // Shifts must disagree.
2490 // Canonicalize shl to left side in a shl/srl pair.
2491 if (RHSShift.getOpcode() == ISD::SHL) {
2492 std::swap(LHS, RHS);
2493 std::swap(LHSShift, RHSShift);
2494 std::swap(LHSMask , RHSMask );
2497 unsigned OpSizeInBits = VT.getSizeInBits();
2498 SDValue LHSShiftArg = LHSShift.getOperand(0);
2499 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2500 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2502 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2503 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2504 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2505 RHSShiftAmt.getOpcode() == ISD::Constant) {
2506 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2507 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2508 if ((LShVal + RShVal) != OpSizeInBits)
2513 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2515 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2517 // If there is an AND of either shifted operand, apply it to the result.
2518 if (LHSMask.getNode() || RHSMask.getNode()) {
2519 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2521 if (LHSMask.getNode()) {
2522 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2523 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2525 if (RHSMask.getNode()) {
2526 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2527 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2530 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2533 return Rot.getNode();
2536 // If there is a mask here, and we have a variable shift, we can't be sure
2537 // that we're masking out the right stuff.
2538 if (LHSMask.getNode() || RHSMask.getNode())
2541 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2542 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2543 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2544 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2545 if (ConstantSDNode *SUBC =
2546 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2547 if (SUBC->getAPIntValue() == OpSizeInBits) {
2549 return DAG.getNode(ISD::ROTL, DL, VT,
2550 LHSShiftArg, LHSShiftAmt).getNode();
2552 return DAG.getNode(ISD::ROTR, DL, VT,
2553 LHSShiftArg, RHSShiftAmt).getNode();
2558 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2559 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2560 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2561 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2562 if (ConstantSDNode *SUBC =
2563 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2564 if (SUBC->getAPIntValue() == OpSizeInBits) {
2566 return DAG.getNode(ISD::ROTR, DL, VT,
2567 LHSShiftArg, RHSShiftAmt).getNode();
2569 return DAG.getNode(ISD::ROTL, DL, VT,
2570 LHSShiftArg, LHSShiftAmt).getNode();
2575 // Look for sign/zext/any-extended or truncate cases:
2576 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2577 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2578 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2579 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2580 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2581 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2582 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2583 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2584 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2585 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2586 if (RExtOp0.getOpcode() == ISD::SUB &&
2587 RExtOp0.getOperand(1) == LExtOp0) {
2588 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2590 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2591 // (rotr x, (sub 32, y))
2592 if (ConstantSDNode *SUBC =
2593 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2594 if (SUBC->getAPIntValue() == OpSizeInBits) {
2595 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2597 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2600 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2601 RExtOp0 == LExtOp0.getOperand(1)) {
2602 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2604 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2605 // (rotl x, (sub 32, y))
2606 if (ConstantSDNode *SUBC =
2607 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2608 if (SUBC->getAPIntValue() == OpSizeInBits) {
2609 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2611 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2620 SDValue DAGCombiner::visitXOR(SDNode *N) {
2621 SDValue N0 = N->getOperand(0);
2622 SDValue N1 = N->getOperand(1);
2623 SDValue LHS, RHS, CC;
2624 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2625 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2626 EVT VT = N0.getValueType();
2629 if (VT.isVector()) {
2630 SDValue FoldedVOp = SimplifyVBinOp(N);
2631 if (FoldedVOp.getNode()) return FoldedVOp;
2634 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2635 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2636 return DAG.getConstant(0, VT);
2637 // fold (xor x, undef) -> undef
2638 if (N0.getOpcode() == ISD::UNDEF)
2640 if (N1.getOpcode() == ISD::UNDEF)
2642 // fold (xor c1, c2) -> c1^c2
2644 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2645 // canonicalize constant to RHS
2647 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2648 // fold (xor x, 0) -> x
2649 if (N1C && N1C->isNullValue())
2652 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2653 if (RXOR.getNode() != 0)
2656 // fold !(x cc y) -> (x !cc y)
2657 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2658 bool isInt = LHS.getValueType().isInteger();
2659 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2662 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2663 switch (N0.getOpcode()) {
2665 llvm_unreachable("Unhandled SetCC Equivalent!");
2667 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2668 case ISD::SELECT_CC:
2669 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2670 N0.getOperand(3), NotCC);
2675 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2676 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2677 N0.getNode()->hasOneUse() &&
2678 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2679 SDValue V = N0.getOperand(0);
2680 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2681 DAG.getConstant(1, V.getValueType()));
2682 AddToWorkList(V.getNode());
2683 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2686 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2687 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2688 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2689 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2690 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2691 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2692 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2693 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2694 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2695 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2698 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2699 if (N1C && N1C->isAllOnesValue() &&
2700 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2701 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2702 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2703 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2704 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2705 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2706 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2707 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2710 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2711 if (N1C && N0.getOpcode() == ISD::XOR) {
2712 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2713 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2715 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2716 DAG.getConstant(N1C->getAPIntValue() ^
2717 N00C->getAPIntValue(), VT));
2719 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2720 DAG.getConstant(N1C->getAPIntValue() ^
2721 N01C->getAPIntValue(), VT));
2723 // fold (xor x, x) -> 0
2725 if (!VT.isVector()) {
2726 return DAG.getConstant(0, VT);
2727 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){
2728 // Produce a vector of zeros.
2729 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
2730 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
2731 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
2732 &Ops[0], Ops.size());
2736 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2737 if (N0.getOpcode() == N1.getOpcode()) {
2738 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2739 if (Tmp.getNode()) return Tmp;
2742 // Simplify the expression using non-local knowledge.
2743 if (!VT.isVector() &&
2744 SimplifyDemandedBits(SDValue(N, 0)))
2745 return SDValue(N, 0);
2750 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2751 /// the shift amount is a constant.
2752 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2753 SDNode *LHS = N->getOperand(0).getNode();
2754 if (!LHS->hasOneUse()) return SDValue();
2756 // We want to pull some binops through shifts, so that we have (and (shift))
2757 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2758 // thing happens with address calculations, so it's important to canonicalize
2760 bool HighBitSet = false; // Can we transform this if the high bit is set?
2762 switch (LHS->getOpcode()) {
2763 default: return SDValue();
2766 HighBitSet = false; // We can only transform sra if the high bit is clear.
2769 HighBitSet = true; // We can only transform sra if the high bit is set.
2772 if (N->getOpcode() != ISD::SHL)
2773 return SDValue(); // only shl(add) not sr[al](add).
2774 HighBitSet = false; // We can only transform sra if the high bit is clear.
2778 // We require the RHS of the binop to be a constant as well.
2779 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2780 if (!BinOpCst) return SDValue();
2782 // FIXME: disable this unless the input to the binop is a shift by a constant.
2783 // If it is not a shift, it pessimizes some common cases like:
2785 // void foo(int *X, int i) { X[i & 1235] = 1; }
2786 // int bar(int *X, int i) { return X[i & 255]; }
2787 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2788 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2789 BinOpLHSVal->getOpcode() != ISD::SRA &&
2790 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2791 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2794 EVT VT = N->getValueType(0);
2796 // If this is a signed shift right, and the high bit is modified by the
2797 // logical operation, do not perform the transformation. The highBitSet
2798 // boolean indicates the value of the high bit of the constant which would
2799 // cause it to be modified for this operation.
2800 if (N->getOpcode() == ISD::SRA) {
2801 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2802 if (BinOpRHSSignSet != HighBitSet)
2806 // Fold the constants, shifting the binop RHS by the shift amount.
2807 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
2809 LHS->getOperand(1), N->getOperand(1));
2811 // Create the new shift.
2812 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(),
2813 VT, LHS->getOperand(0), N->getOperand(1));
2815 // Create the new binop.
2816 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
2819 SDValue DAGCombiner::visitSHL(SDNode *N) {
2820 SDValue N0 = N->getOperand(0);
2821 SDValue N1 = N->getOperand(1);
2822 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2823 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2824 EVT VT = N0.getValueType();
2825 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2827 // fold (shl c1, c2) -> c1<<c2
2829 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
2830 // fold (shl 0, x) -> 0
2831 if (N0C && N0C->isNullValue())
2833 // fold (shl x, c >= size(x)) -> undef
2834 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2835 return DAG.getUNDEF(VT);
2836 // fold (shl x, 0) -> x
2837 if (N1C && N1C->isNullValue())
2839 // if (shl x, c) is known to be zero, return 0
2840 if (DAG.MaskedValueIsZero(SDValue(N, 0),
2841 APInt::getAllOnesValue(OpSizeInBits)))
2842 return DAG.getConstant(0, VT);
2843 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
2844 if (N1.getOpcode() == ISD::TRUNCATE &&
2845 N1.getOperand(0).getOpcode() == ISD::AND &&
2846 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2847 SDValue N101 = N1.getOperand(0).getOperand(1);
2848 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2849 EVT TruncVT = N1.getValueType();
2850 SDValue N100 = N1.getOperand(0).getOperand(0);
2851 APInt TruncC = N101C->getAPIntValue();
2852 TruncC.trunc(TruncVT.getSizeInBits());
2853 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
2854 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
2855 DAG.getNode(ISD::TRUNCATE,
2858 DAG.getConstant(TruncC, TruncVT)));
2862 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2863 return SDValue(N, 0);
2865 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
2866 if (N1C && N0.getOpcode() == ISD::SHL &&
2867 N0.getOperand(1).getOpcode() == ISD::Constant) {
2868 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2869 uint64_t c2 = N1C->getZExtValue();
2870 if (c1 + c2 > OpSizeInBits)
2871 return DAG.getConstant(0, VT);
2872 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
2873 DAG.getConstant(c1 + c2, N1.getValueType()));
2875 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
2876 // (srl (and x, (shl -1, c1)), (sub c1, c2))
2877 if (N1C && N0.getOpcode() == ISD::SRL &&
2878 N0.getOperand(1).getOpcode() == ISD::Constant) {
2879 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2880 if (c1 < VT.getSizeInBits()) {
2881 uint64_t c2 = N1C->getZExtValue();
2882 SDValue HiBitsMask =
2883 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2884 VT.getSizeInBits() - c1),
2886 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT,
2890 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
2891 DAG.getConstant(c2-c1, N1.getValueType()));
2893 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
2894 DAG.getConstant(c1-c2, N1.getValueType()));
2897 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
2898 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
2899 SDValue HiBitsMask =
2900 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2901 VT.getSizeInBits() -
2902 N1C->getZExtValue()),
2904 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
2909 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
2910 if (NewSHL.getNode())
2917 SDValue DAGCombiner::visitSRA(SDNode *N) {
2918 SDValue N0 = N->getOperand(0);
2919 SDValue N1 = N->getOperand(1);
2920 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2921 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2922 EVT VT = N0.getValueType();
2923 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2925 // fold (sra c1, c2) -> (sra c1, c2)
2927 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
2928 // fold (sra 0, x) -> 0
2929 if (N0C && N0C->isNullValue())
2931 // fold (sra -1, x) -> -1
2932 if (N0C && N0C->isAllOnesValue())
2934 // fold (sra x, (setge c, size(x))) -> undef
2935 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2936 return DAG.getUNDEF(VT);
2937 // fold (sra x, 0) -> x
2938 if (N1C && N1C->isNullValue())
2940 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2942 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2943 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
2944 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
2946 ExtVT = EVT::getVectorVT(*DAG.getContext(),
2947 ExtVT, VT.getVectorNumElements());
2948 if ((!LegalOperations ||
2949 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
2950 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
2951 N0.getOperand(0), DAG.getValueType(ExtVT));
2954 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
2955 if (N1C && N0.getOpcode() == ISD::SRA) {
2956 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2957 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
2958 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
2959 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
2960 DAG.getConstant(Sum, N1C->getValueType(0)));
2964 // fold (sra (shl X, m), (sub result_size, n))
2965 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
2966 // result_size - n != m.
2967 // If truncate is free for the target sext(shl) is likely to result in better
2969 if (N0.getOpcode() == ISD::SHL) {
2970 // Get the two constanst of the shifts, CN0 = m, CN = n.
2971 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2973 // Determine what the truncate's result bitsize and type would be.
2975 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue());
2976 // Determine the residual right-shift amount.
2977 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
2979 // If the shift is not a no-op (in which case this should be just a sign
2980 // extend already), the truncated to type is legal, sign_extend is legal
2981 // on that type, and the truncate to that type is both legal and free,
2982 // perform the transform.
2983 if ((ShiftAmt > 0) &&
2984 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
2985 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
2986 TLI.isTruncateFree(VT, TruncVT)) {
2988 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy());
2989 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
2990 N0.getOperand(0), Amt);
2991 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
2993 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
2994 N->getValueType(0), Trunc);
2999 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3000 if (N1.getOpcode() == ISD::TRUNCATE &&
3001 N1.getOperand(0).getOpcode() == ISD::AND &&
3002 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3003 SDValue N101 = N1.getOperand(0).getOperand(1);
3004 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3005 EVT TruncVT = N1.getValueType();
3006 SDValue N100 = N1.getOperand(0).getOperand(0);
3007 APInt TruncC = N101C->getAPIntValue();
3008 TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3009 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3010 DAG.getNode(ISD::AND, N->getDebugLoc(),
3012 DAG.getNode(ISD::TRUNCATE,
3015 DAG.getConstant(TruncC, TruncVT)));
3019 // Simplify, based on bits shifted out of the LHS.
3020 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3021 return SDValue(N, 0);
3024 // If the sign bit is known to be zero, switch this to a SRL.
3025 if (DAG.SignBitIsZero(N0))
3026 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3029 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3030 if (NewSRA.getNode())
3037 SDValue DAGCombiner::visitSRL(SDNode *N) {
3038 SDValue N0 = N->getOperand(0);
3039 SDValue N1 = N->getOperand(1);
3040 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3041 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3042 EVT VT = N0.getValueType();
3043 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3045 // fold (srl c1, c2) -> c1 >>u c2
3047 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3048 // fold (srl 0, x) -> 0
3049 if (N0C && N0C->isNullValue())
3051 // fold (srl x, c >= size(x)) -> undef
3052 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3053 return DAG.getUNDEF(VT);
3054 // fold (srl x, 0) -> x
3055 if (N1C && N1C->isNullValue())
3057 // if (srl x, c) is known to be zero, return 0
3058 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3059 APInt::getAllOnesValue(OpSizeInBits)))
3060 return DAG.getConstant(0, VT);
3062 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3063 if (N1C && N0.getOpcode() == ISD::SRL &&
3064 N0.getOperand(1).getOpcode() == ISD::Constant) {
3065 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3066 uint64_t c2 = N1C->getZExtValue();
3067 if (c1 + c2 > OpSizeInBits)
3068 return DAG.getConstant(0, VT);
3069 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3070 DAG.getConstant(c1 + c2, N1.getValueType()));
3073 // fold (srl (shl x, c), c) -> (and x, cst2)
3074 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3075 N0.getValueSizeInBits() <= 64) {
3076 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3077 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3078 DAG.getConstant(~0ULL >> ShAmt, VT));
3082 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3083 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3084 // Shifting in all undef bits?
3085 EVT SmallVT = N0.getOperand(0).getValueType();
3086 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3087 return DAG.getUNDEF(VT);
3089 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3090 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3091 N0.getOperand(0), N1);
3092 AddToWorkList(SmallShift.getNode());
3093 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3097 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3098 // bit, which is unmodified by sra.
3099 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3100 if (N0.getOpcode() == ISD::SRA)
3101 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3104 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3105 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3106 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3107 APInt KnownZero, KnownOne;
3108 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
3109 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
3111 // If any of the input bits are KnownOne, then the input couldn't be all
3112 // zeros, thus the result of the srl will always be zero.
3113 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3115 // If all of the bits input the to ctlz node are known to be zero, then
3116 // the result of the ctlz is "32" and the result of the shift is one.
3117 APInt UnknownBits = ~KnownZero & Mask;
3118 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3120 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3121 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3122 // Okay, we know that only that the single bit specified by UnknownBits
3123 // could be set on input to the CTLZ node. If this bit is set, the SRL
3124 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3125 // to an SRL/XOR pair, which is likely to simplify more.
3126 unsigned ShAmt = UnknownBits.countTrailingZeros();
3127 SDValue Op = N0.getOperand(0);
3130 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3131 DAG.getConstant(ShAmt, getShiftAmountTy()));
3132 AddToWorkList(Op.getNode());
3135 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3136 Op, DAG.getConstant(1, VT));
3140 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3141 if (N1.getOpcode() == ISD::TRUNCATE &&
3142 N1.getOperand(0).getOpcode() == ISD::AND &&
3143 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3144 SDValue N101 = N1.getOperand(0).getOperand(1);
3145 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3146 EVT TruncVT = N1.getValueType();
3147 SDValue N100 = N1.getOperand(0).getOperand(0);
3148 APInt TruncC = N101C->getAPIntValue();
3149 TruncC.trunc(TruncVT.getSizeInBits());
3150 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3151 DAG.getNode(ISD::AND, N->getDebugLoc(),
3153 DAG.getNode(ISD::TRUNCATE,
3156 DAG.getConstant(TruncC, TruncVT)));
3160 // fold operands of srl based on knowledge that the low bits are not
3162 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3163 return SDValue(N, 0);
3166 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3167 if (NewSRL.getNode())
3171 // Attempt to convert a srl of a load into a narrower zero-extending load.
3172 SDValue NarrowLoad = ReduceLoadWidth(N);
3173 if (NarrowLoad.getNode())
3176 // Here is a common situation. We want to optimize:
3179 // %b = and i32 %a, 2
3180 // %c = srl i32 %b, 1
3181 // brcond i32 %c ...
3187 // %c = setcc eq %b, 0
3190 // However when after the source operand of SRL is optimized into AND, the SRL
3191 // itself may not be optimized further. Look for it and add the BRCOND into
3193 if (N->hasOneUse()) {
3194 SDNode *Use = *N->use_begin();
3195 if (Use->getOpcode() == ISD::BRCOND)
3197 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3198 // Also look pass the truncate.
3199 Use = *Use->use_begin();
3200 if (Use->getOpcode() == ISD::BRCOND)
3208 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3209 SDValue N0 = N->getOperand(0);
3210 EVT VT = N->getValueType(0);
3212 // fold (ctlz c1) -> c2
3213 if (isa<ConstantSDNode>(N0))
3214 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3218 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
3219 SDValue N0 = N->getOperand(0);
3220 EVT VT = N->getValueType(0);
3222 // fold (cttz c1) -> c2
3223 if (isa<ConstantSDNode>(N0))
3224 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3228 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
3229 SDValue N0 = N->getOperand(0);
3230 EVT VT = N->getValueType(0);
3232 // fold (ctpop c1) -> c2
3233 if (isa<ConstantSDNode>(N0))
3234 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3238 SDValue DAGCombiner::visitSELECT(SDNode *N) {
3239 SDValue N0 = N->getOperand(0);
3240 SDValue N1 = N->getOperand(1);
3241 SDValue N2 = N->getOperand(2);
3242 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3243 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3244 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
3245 EVT VT = N->getValueType(0);
3246 EVT VT0 = N0.getValueType();
3248 // fold (select C, X, X) -> X
3251 // fold (select true, X, Y) -> X
3252 if (N0C && !N0C->isNullValue())
3254 // fold (select false, X, Y) -> Y
3255 if (N0C && N0C->isNullValue())
3257 // fold (select C, 1, X) -> (or C, X)
3258 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
3259 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3260 // fold (select C, 0, 1) -> (xor C, 1)
3261 if (VT.isInteger() &&
3264 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
3265 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
3268 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
3269 N0, DAG.getConstant(1, VT0));
3270 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
3271 N0, DAG.getConstant(1, VT0));
3272 AddToWorkList(XORNode.getNode());
3274 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
3275 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
3277 // fold (select C, 0, X) -> (and (not C), X)
3278 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
3279 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3280 AddToWorkList(NOTNode.getNode());
3281 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
3283 // fold (select C, X, 1) -> (or (not C), X)
3284 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
3285 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3286 AddToWorkList(NOTNode.getNode());
3287 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
3289 // fold (select C, X, 0) -> (and C, X)
3290 if (VT == MVT::i1 && N2C && N2C->isNullValue())
3291 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3292 // fold (select X, X, Y) -> (or X, Y)
3293 // fold (select X, 1, Y) -> (or X, Y)
3294 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
3295 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3296 // fold (select X, Y, X) -> (and X, Y)
3297 // fold (select X, Y, 0) -> (and X, Y)
3298 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
3299 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3301 // If we can fold this based on the true/false value, do so.
3302 if (SimplifySelectOps(N, N1, N2))
3303 return SDValue(N, 0); // Don't revisit N.
3305 // fold selects based on a setcc into other things, such as min/max/abs
3306 if (N0.getOpcode() == ISD::SETCC) {
3308 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
3309 // having to say they don't support SELECT_CC on every type the DAG knows
3310 // about, since there is no way to mark an opcode illegal at all value types
3311 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
3312 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
3313 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
3314 N0.getOperand(0), N0.getOperand(1),
3315 N1, N2, N0.getOperand(2));
3316 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
3322 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
3323 SDValue N0 = N->getOperand(0);
3324 SDValue N1 = N->getOperand(1);
3325 SDValue N2 = N->getOperand(2);
3326 SDValue N3 = N->getOperand(3);
3327 SDValue N4 = N->getOperand(4);
3328 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
3330 // fold select_cc lhs, rhs, x, x, cc -> x
3334 // Determine if the condition we're dealing with is constant
3335 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
3336 N0, N1, CC, N->getDebugLoc(), false);
3337 if (SCC.getNode()) AddToWorkList(SCC.getNode());
3339 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
3340 if (!SCCC->isNullValue())
3341 return N2; // cond always true -> true val
3343 return N3; // cond always false -> false val
3346 // Fold to a simpler select_cc
3347 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
3348 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
3349 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
3352 // If we can fold this based on the true/false value, do so.
3353 if (SimplifySelectOps(N, N2, N3))
3354 return SDValue(N, 0); // Don't revisit N.
3356 // fold select_cc into other things, such as min/max/abs
3357 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
3360 SDValue DAGCombiner::visitSETCC(SDNode *N) {
3361 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
3362 cast<CondCodeSDNode>(N->getOperand(2))->get(),
3366 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
3367 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
3368 // transformation. Returns true if extension are possible and the above
3369 // mentioned transformation is profitable.
3370 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
3372 SmallVector<SDNode*, 4> &ExtendNodes,
3373 const TargetLowering &TLI) {
3374 bool HasCopyToRegUses = false;
3375 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
3376 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3377 UE = N0.getNode()->use_end();
3382 if (UI.getUse().getResNo() != N0.getResNo())
3384 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
3385 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
3386 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
3387 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
3388 // Sign bits will be lost after a zext.
3391 for (unsigned i = 0; i != 2; ++i) {
3392 SDValue UseOp = User->getOperand(i);
3395 if (!isa<ConstantSDNode>(UseOp))
3400 ExtendNodes.push_back(User);
3403 // If truncates aren't free and there are users we can't
3404 // extend, it isn't worthwhile.
3407 // Remember if this value is live-out.
3408 if (User->getOpcode() == ISD::CopyToReg)
3409 HasCopyToRegUses = true;
3412 if (HasCopyToRegUses) {
3413 bool BothLiveOut = false;
3414 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3416 SDUse &Use = UI.getUse();
3417 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
3423 // Both unextended and extended values are live out. There had better be
3424 // good a reason for the transformation.
3425 return ExtendNodes.size();
3430 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3431 SDValue N0 = N->getOperand(0);
3432 EVT VT = N->getValueType(0);
3434 // fold (sext c1) -> c1
3435 if (isa<ConstantSDNode>(N0))
3436 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3438 // fold (sext (sext x)) -> (sext x)
3439 // fold (sext (aext x)) -> (sext x)
3440 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3441 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3444 if (N0.getOpcode() == ISD::TRUNCATE) {
3445 // fold (sext (truncate (load x))) -> (sext (smaller load x))
3446 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3447 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3448 if (NarrowLoad.getNode()) {
3449 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3450 if (NarrowLoad.getNode() != N0.getNode()) {
3451 CombineTo(N0.getNode(), NarrowLoad);
3452 // CombineTo deleted the truncate, if needed, but not what's under it.
3455 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3458 // See if the value being truncated is already sign extended. If so, just
3459 // eliminate the trunc/sext pair.
3460 SDValue Op = N0.getOperand(0);
3461 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
3462 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
3463 unsigned DestBits = VT.getScalarType().getSizeInBits();
3464 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3466 if (OpBits == DestBits) {
3467 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3468 // bits, it is already ready.
3469 if (NumSignBits > DestBits-MidBits)
3471 } else if (OpBits < DestBits) {
3472 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3473 // bits, just sext from i32.
3474 if (NumSignBits > OpBits-MidBits)
3475 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3477 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
3478 // bits, just truncate to i32.
3479 if (NumSignBits > OpBits-MidBits)
3480 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3483 // fold (sext (truncate x)) -> (sextinreg x).
3484 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
3485 N0.getValueType())) {
3486 if (OpBits < DestBits)
3487 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
3488 else if (OpBits > DestBits)
3489 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
3490 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
3491 DAG.getValueType(N0.getValueType()));
3495 // fold (sext (load x)) -> (sext (truncate (sextload x)))
3496 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3497 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3498 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3499 bool DoXform = true;
3500 SmallVector<SDNode*, 4> SetCCs;
3501 if (!N0.hasOneUse())
3502 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3504 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3505 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3507 LN0->getBasePtr(), LN0->getSrcValue(),
3508 LN0->getSrcValueOffset(),
3510 LN0->isVolatile(), LN0->isNonTemporal(),
3511 LN0->getAlignment());
3512 CombineTo(N, ExtLoad);
3513 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3514 N0.getValueType(), ExtLoad);
3515 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3517 // Extend SetCC uses if necessary.
3518 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3519 SDNode *SetCC = SetCCs[i];
3520 SmallVector<SDValue, 4> Ops;
3522 for (unsigned j = 0; j != 2; ++j) {
3523 SDValue SOp = SetCC->getOperand(j);
3525 Ops.push_back(ExtLoad);
3527 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND,
3528 N->getDebugLoc(), VT, SOp));
3531 Ops.push_back(SetCC->getOperand(2));
3532 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3533 SetCC->getValueType(0),
3534 &Ops[0], Ops.size()));
3537 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3541 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3542 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3543 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3544 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3545 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3546 EVT MemVT = LN0->getMemoryVT();
3547 if ((!LegalOperations && !LN0->isVolatile()) ||
3548 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
3549 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3551 LN0->getBasePtr(), LN0->getSrcValue(),
3552 LN0->getSrcValueOffset(), MemVT,
3553 LN0->isVolatile(), LN0->isNonTemporal(),
3554 LN0->getAlignment());
3555 CombineTo(N, ExtLoad);
3556 CombineTo(N0.getNode(),
3557 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3558 N0.getValueType(), ExtLoad),
3559 ExtLoad.getValue(1));
3560 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3564 if (N0.getOpcode() == ISD::SETCC) {
3565 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
3566 // Only do this before legalize for now.
3567 if (VT.isVector() && !LegalOperations) {
3568 EVT N0VT = N0.getOperand(0).getValueType();
3569 // We know that the # elements of the results is the same as the
3570 // # elements of the compare (and the # elements of the compare result
3571 // for that matter). Check to see that they are the same size. If so,
3572 // we know that the element size of the sext'd result matches the
3573 // element size of the compare operands.
3574 if (VT.getSizeInBits() == N0VT.getSizeInBits())
3575 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3577 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3578 // If the desired elements are smaller or larger than the source
3579 // elements we can use a matching integer vector type and then
3580 // truncate/sign extend
3582 EVT MatchingElementType =
3583 EVT::getIntegerVT(*DAG.getContext(),
3584 N0VT.getScalarType().getSizeInBits());
3585 EVT MatchingVectorType =
3586 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
3587 N0VT.getVectorNumElements());
3589 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
3591 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3592 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
3596 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3597 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
3599 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
3601 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3602 NegOne, DAG.getConstant(0, VT),
3603 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3604 if (SCC.getNode()) return SCC;
3605 if (!LegalOperations ||
3606 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
3607 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3608 DAG.getSetCC(N->getDebugLoc(),
3609 TLI.getSetCCResultType(VT),
3610 N0.getOperand(0), N0.getOperand(1),
3611 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
3612 NegOne, DAG.getConstant(0, VT));
3615 // fold (sext x) -> (zext x) if the sign bit is known zero.
3616 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3617 DAG.SignBitIsZero(N0))
3618 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3623 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3624 SDValue N0 = N->getOperand(0);
3625 EVT VT = N->getValueType(0);
3627 // fold (zext c1) -> c1
3628 if (isa<ConstantSDNode>(N0))
3629 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3630 // fold (zext (zext x)) -> (zext x)
3631 // fold (zext (aext x)) -> (zext x)
3632 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3633 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3636 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3637 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3638 if (N0.getOpcode() == ISD::TRUNCATE) {
3639 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3640 if (NarrowLoad.getNode()) {
3641 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3642 if (NarrowLoad.getNode() != N0.getNode()) {
3643 CombineTo(N0.getNode(), NarrowLoad);
3644 // CombineTo deleted the truncate, if needed, but not what's under it.
3647 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3651 // fold (zext (truncate x)) -> (and x, mask)
3652 if (N0.getOpcode() == ISD::TRUNCATE &&
3653 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
3654 SDValue Op = N0.getOperand(0);
3655 if (Op.getValueType().bitsLT(VT)) {
3656 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
3657 } else if (Op.getValueType().bitsGT(VT)) {
3658 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3660 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
3661 N0.getValueType().getScalarType());
3664 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
3665 // if either of the casts is not free.
3666 if (N0.getOpcode() == ISD::AND &&
3667 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3668 N0.getOperand(1).getOpcode() == ISD::Constant &&
3669 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3670 N0.getValueType()) ||
3671 !TLI.isZExtFree(N0.getValueType(), VT))) {
3672 SDValue X = N0.getOperand(0).getOperand(0);
3673 if (X.getValueType().bitsLT(VT)) {
3674 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
3675 } else if (X.getValueType().bitsGT(VT)) {
3676 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3678 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3679 Mask.zext(VT.getSizeInBits());
3680 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3681 X, DAG.getConstant(Mask, VT));
3684 // fold (zext (load x)) -> (zext (truncate (zextload x)))
3685 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3686 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3687 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3688 bool DoXform = true;
3689 SmallVector<SDNode*, 4> SetCCs;
3690 if (!N0.hasOneUse())
3691 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3693 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3694 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3696 LN0->getBasePtr(), LN0->getSrcValue(),
3697 LN0->getSrcValueOffset(),
3699 LN0->isVolatile(), LN0->isNonTemporal(),
3700 LN0->getAlignment());
3701 CombineTo(N, ExtLoad);
3702 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3703 N0.getValueType(), ExtLoad);
3704 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3706 // Extend SetCC uses if necessary.
3707 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3708 SDNode *SetCC = SetCCs[i];
3709 SmallVector<SDValue, 4> Ops;
3711 for (unsigned j = 0; j != 2; ++j) {
3712 SDValue SOp = SetCC->getOperand(j);
3714 Ops.push_back(ExtLoad);
3716 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
3717 N->getDebugLoc(), VT, SOp));
3720 Ops.push_back(SetCC->getOperand(2));
3721 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3722 SetCC->getValueType(0),
3723 &Ops[0], Ops.size()));
3726 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3730 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
3731 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
3732 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3733 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3734 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3735 EVT MemVT = LN0->getMemoryVT();
3736 if ((!LegalOperations && !LN0->isVolatile()) ||
3737 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
3738 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3740 LN0->getBasePtr(), LN0->getSrcValue(),
3741 LN0->getSrcValueOffset(), MemVT,
3742 LN0->isVolatile(), LN0->isNonTemporal(),
3743 LN0->getAlignment());
3744 CombineTo(N, ExtLoad);
3745 CombineTo(N0.getNode(),
3746 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
3748 ExtLoad.getValue(1));
3749 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3753 if (N0.getOpcode() == ISD::SETCC) {
3754 if (!LegalOperations && VT.isVector()) {
3755 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
3756 // Only do this before legalize for now.
3757 EVT N0VT = N0.getOperand(0).getValueType();
3758 EVT EltVT = VT.getVectorElementType();
3759 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
3760 DAG.getConstant(1, EltVT));
3761 if (VT.getSizeInBits() == N0VT.getSizeInBits()) {
3762 // We know that the # elements of the results is the same as the
3763 // # elements of the compare (and the # elements of the compare result
3764 // for that matter). Check to see that they are the same size. If so,
3765 // we know that the element size of the sext'd result matches the
3766 // element size of the compare operands.
3767 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3768 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3770 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
3771 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
3772 &OneOps[0], OneOps.size()));
3774 // If the desired elements are smaller or larger than the source
3775 // elements we can use a matching integer vector type and then
3776 // truncate/sign extend
3777 EVT MatchingElementType =
3778 EVT::getIntegerVT(*DAG.getContext(),
3779 N0VT.getScalarType().getSizeInBits());
3780 EVT MatchingVectorType =
3781 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
3782 N0VT.getVectorNumElements());
3784 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
3786 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3787 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3788 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
3789 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
3790 &OneOps[0], OneOps.size()));
3794 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3796 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3797 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3798 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3799 if (SCC.getNode()) return SCC;
3802 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
3803 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
3804 isa<ConstantSDNode>(N0.getOperand(1)) &&
3805 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
3807 if (N0.getOpcode() == ISD::SHL) {
3808 // If the original shl may be shifting out bits, do not perform this
3810 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3811 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() -
3812 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits();
3813 if (ShAmt > KnownZeroBits)
3816 DebugLoc dl = N->getDebugLoc();
3817 return DAG.getNode(N0.getOpcode(), dl, VT,
3818 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)),
3819 DAG.getNode(ISD::ZERO_EXTEND, dl,
3820 N0.getOperand(1).getValueType(),
3827 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
3828 SDValue N0 = N->getOperand(0);
3829 EVT VT = N->getValueType(0);
3831 // fold (aext c1) -> c1
3832 if (isa<ConstantSDNode>(N0))
3833 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
3834 // fold (aext (aext x)) -> (aext x)
3835 // fold (aext (zext x)) -> (zext x)
3836 // fold (aext (sext x)) -> (sext x)
3837 if (N0.getOpcode() == ISD::ANY_EXTEND ||
3838 N0.getOpcode() == ISD::ZERO_EXTEND ||
3839 N0.getOpcode() == ISD::SIGN_EXTEND)
3840 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
3842 // fold (aext (truncate (load x))) -> (aext (smaller load x))
3843 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3844 if (N0.getOpcode() == ISD::TRUNCATE) {
3845 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3846 if (NarrowLoad.getNode()) {
3847 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3848 if (NarrowLoad.getNode() != N0.getNode()) {
3849 CombineTo(N0.getNode(), NarrowLoad);
3850 // CombineTo deleted the truncate, if needed, but not what's under it.
3853 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3857 // fold (aext (truncate x))
3858 if (N0.getOpcode() == ISD::TRUNCATE) {
3859 SDValue TruncOp = N0.getOperand(0);
3860 if (TruncOp.getValueType() == VT)
3861 return TruncOp; // x iff x size == zext size.
3862 if (TruncOp.getValueType().bitsGT(VT))
3863 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
3864 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
3867 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
3868 // if the trunc is not free.
3869 if (N0.getOpcode() == ISD::AND &&
3870 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3871 N0.getOperand(1).getOpcode() == ISD::Constant &&
3872 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3873 N0.getValueType())) {
3874 SDValue X = N0.getOperand(0).getOperand(0);
3875 if (X.getValueType().bitsLT(VT)) {
3876 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
3877 } else if (X.getValueType().bitsGT(VT)) {
3878 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
3880 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3881 Mask.zext(VT.getSizeInBits());
3882 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3883 X, DAG.getConstant(Mask, VT));
3886 // fold (aext (load x)) -> (aext (truncate (extload x)))
3887 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3888 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3889 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
3890 bool DoXform = true;
3891 SmallVector<SDNode*, 4> SetCCs;
3892 if (!N0.hasOneUse())
3893 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
3895 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3896 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
3898 LN0->getBasePtr(), LN0->getSrcValue(),
3899 LN0->getSrcValueOffset(),
3901 LN0->isVolatile(), LN0->isNonTemporal(),
3902 LN0->getAlignment());
3903 CombineTo(N, ExtLoad);
3904 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3905 N0.getValueType(), ExtLoad);
3906 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3908 // Extend SetCC uses if necessary.
3909 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3910 SDNode *SetCC = SetCCs[i];
3911 SmallVector<SDValue, 4> Ops;
3913 for (unsigned j = 0; j != 2; ++j) {
3914 SDValue SOp = SetCC->getOperand(j);
3916 Ops.push_back(ExtLoad);
3918 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND,
3919 N->getDebugLoc(), VT, SOp));
3922 Ops.push_back(SetCC->getOperand(2));
3923 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3924 SetCC->getValueType(0),
3925 &Ops[0], Ops.size()));
3928 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3932 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
3933 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
3934 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
3935 if (N0.getOpcode() == ISD::LOAD &&
3936 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3938 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3939 EVT MemVT = LN0->getMemoryVT();
3940 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
3941 VT, LN0->getChain(), LN0->getBasePtr(),
3943 LN0->getSrcValueOffset(), MemVT,
3944 LN0->isVolatile(), LN0->isNonTemporal(),
3945 LN0->getAlignment());
3946 CombineTo(N, ExtLoad);
3947 CombineTo(N0.getNode(),
3948 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3949 N0.getValueType(), ExtLoad),
3950 ExtLoad.getValue(1));
3951 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3954 if (N0.getOpcode() == ISD::SETCC) {
3955 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
3956 // Only do this before legalize for now.
3957 if (VT.isVector() && !LegalOperations) {
3958 EVT N0VT = N0.getOperand(0).getValueType();
3959 // We know that the # elements of the results is the same as the
3960 // # elements of the compare (and the # elements of the compare result
3961 // for that matter). Check to see that they are the same size. If so,
3962 // we know that the element size of the sext'd result matches the
3963 // element size of the compare operands.
3964 if (VT.getSizeInBits() == N0VT.getSizeInBits())
3965 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3967 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3968 // If the desired elements are smaller or larger than the source
3969 // elements we can use a matching integer vector type and then
3970 // truncate/sign extend
3972 EVT MatchingElementType =
3973 EVT::getIntegerVT(*DAG.getContext(),
3974 N0VT.getScalarType().getSizeInBits());
3975 EVT MatchingVectorType =
3976 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
3977 N0VT.getVectorNumElements());
3979 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
3981 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3982 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
3986 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3988 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3989 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3990 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3998 /// GetDemandedBits - See if the specified operand can be simplified with the
3999 /// knowledge that only the bits specified by Mask are used. If so, return the
4000 /// simpler operand, otherwise return a null SDValue.
4001 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4002 switch (V.getOpcode()) {
4006 // If the LHS or RHS don't contribute bits to the or, drop them.
4007 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4008 return V.getOperand(1);
4009 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4010 return V.getOperand(0);
4013 // Only look at single-use SRLs.
4014 if (!V.getNode()->hasOneUse())
4016 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4017 // See if we can recursively simplify the LHS.
4018 unsigned Amt = RHSC->getZExtValue();
4020 // Watch out for shift count overflow though.
4021 if (Amt >= Mask.getBitWidth()) break;
4022 APInt NewMask = Mask << Amt;
4023 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4024 if (SimplifyLHS.getNode())
4025 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4026 SimplifyLHS, V.getOperand(1));
4032 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4033 /// bits and then truncated to a narrower type and where N is a multiple
4034 /// of number of bits of the narrower type, transform it to a narrower load
4035 /// from address + N / num of bits of new type. If the result is to be
4036 /// extended, also fold the extension to form a extending load.
4037 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4038 unsigned Opc = N->getOpcode();
4040 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4041 SDValue N0 = N->getOperand(0);
4042 EVT VT = N->getValueType(0);
4045 // This transformation isn't valid for vector loads.
4049 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4051 if (Opc == ISD::SIGN_EXTEND_INREG) {
4052 ExtType = ISD::SEXTLOAD;
4053 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4054 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT))
4056 } else if (Opc == ISD::SRL) {
4057 // Annother special-case: SRL is basically zero-extending a narrower
4059 ExtType = ISD::ZEXTLOAD;
4061 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4062 if (!N01) return SDValue();
4063 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
4064 VT.getSizeInBits() - N01->getZExtValue());
4067 unsigned EVTBits = ExtVT.getSizeInBits();
4069 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) {
4070 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4071 ShAmt = N01->getZExtValue();
4072 // Is the shift amount a multiple of size of VT?
4073 if ((ShAmt & (EVTBits-1)) == 0) {
4074 N0 = N0.getOperand(0);
4075 // Is the load width a multiple of size of VT?
4076 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
4082 // Do not generate loads of non-round integer types since these can
4083 // be expensive (and would be wrong if the type is not byte sized).
4084 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() &&
4085 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() >= EVTBits &&
4086 // Do not change the width of a volatile load.
4087 !cast<LoadSDNode>(N0)->isVolatile()) {
4088 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4089 EVT PtrType = N0.getOperand(1).getValueType();
4091 // For big endian targets, we need to adjust the offset to the pointer to
4092 // load the correct bytes.
4093 if (TLI.isBigEndian()) {
4094 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
4095 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
4096 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
4099 uint64_t PtrOff = ShAmt / 8;
4100 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
4101 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
4102 PtrType, LN0->getBasePtr(),
4103 DAG.getConstant(PtrOff, PtrType));
4104 AddToWorkList(NewPtr.getNode());
4106 SDValue Load = (ExtType == ISD::NON_EXTLOAD)
4107 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4108 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
4109 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign)
4110 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr,
4111 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
4112 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
4115 // Replace the old load's chain with the new load's chain.
4116 WorkListRemover DeadNodes(*this);
4117 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
4120 // Return the new loaded value.
4127 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
4128 SDValue N0 = N->getOperand(0);
4129 SDValue N1 = N->getOperand(1);
4130 EVT VT = N->getValueType(0);
4131 EVT EVT = cast<VTSDNode>(N1)->getVT();
4132 unsigned VTBits = VT.getScalarType().getSizeInBits();
4133 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
4135 // fold (sext_in_reg c1) -> c1
4136 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
4137 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
4139 // If the input is already sign extended, just drop the extension.
4140 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
4143 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
4144 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4145 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
4146 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4147 N0.getOperand(0), N1);
4150 // fold (sext_in_reg (sext x)) -> (sext x)
4151 // fold (sext_in_reg (aext x)) -> (sext x)
4152 // if x is small enough.
4153 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
4154 SDValue N00 = N0.getOperand(0);
4155 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
4156 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
4157 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
4160 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
4161 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
4162 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
4164 // fold operands of sext_in_reg based on knowledge that the top bits are not
4166 if (SimplifyDemandedBits(SDValue(N, 0)))
4167 return SDValue(N, 0);
4169 // fold (sext_in_reg (load x)) -> (smaller sextload x)
4170 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
4171 SDValue NarrowLoad = ReduceLoadWidth(N);
4172 if (NarrowLoad.getNode())
4175 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
4176 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
4177 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
4178 if (N0.getOpcode() == ISD::SRL) {
4179 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
4180 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
4181 // We can turn this into an SRA iff the input to the SRL is already sign
4183 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
4184 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
4185 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
4186 N0.getOperand(0), N0.getOperand(1));
4190 // fold (sext_inreg (extload x)) -> (sextload x)
4191 if (ISD::isEXTLoad(N0.getNode()) &&
4192 ISD::isUNINDEXEDLoad(N0.getNode()) &&
4193 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4194 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4195 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4196 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4197 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4199 LN0->getBasePtr(), LN0->getSrcValue(),
4200 LN0->getSrcValueOffset(), EVT,
4201 LN0->isVolatile(), LN0->isNonTemporal(),
4202 LN0->getAlignment());
4203 CombineTo(N, ExtLoad);
4204 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4205 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4207 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
4208 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4210 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4211 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4212 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4213 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4214 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4216 LN0->getBasePtr(), LN0->getSrcValue(),
4217 LN0->getSrcValueOffset(), EVT,
4218 LN0->isVolatile(), LN0->isNonTemporal(),
4219 LN0->getAlignment());
4220 CombineTo(N, ExtLoad);
4221 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4222 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4227 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
4228 SDValue N0 = N->getOperand(0);
4229 EVT VT = N->getValueType(0);
4232 if (N0.getValueType() == N->getValueType(0))
4234 // fold (truncate c1) -> c1
4235 if (isa<ConstantSDNode>(N0))
4236 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
4237 // fold (truncate (truncate x)) -> (truncate x)
4238 if (N0.getOpcode() == ISD::TRUNCATE)
4239 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4240 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
4241 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
4242 N0.getOpcode() == ISD::SIGN_EXTEND ||
4243 N0.getOpcode() == ISD::ANY_EXTEND) {
4244 if (N0.getOperand(0).getValueType().bitsLT(VT))
4245 // if the source is smaller than the dest, we still need an extend
4246 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4248 else if (N0.getOperand(0).getValueType().bitsGT(VT))
4249 // if the source is larger than the dest, than we just need the truncate
4250 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4252 // if the source and dest are the same type, we can drop both the extend
4253 // and the truncate.
4254 return N0.getOperand(0);
4257 // See if we can simplify the input to this truncate through knowledge that
4258 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
4261 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
4262 VT.getSizeInBits()));
4263 if (Shorter.getNode())
4264 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
4266 // fold (truncate (load x)) -> (smaller load x)
4267 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
4268 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
4269 SDValue Reduced = ReduceLoadWidth(N);
4270 if (Reduced.getNode())
4274 // Simplify the operands using demanded-bits information.
4275 if (!VT.isVector() &&
4276 SimplifyDemandedBits(SDValue(N, 0)))
4277 return SDValue(N, 0);
4282 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
4283 SDValue Elt = N->getOperand(i);
4284 if (Elt.getOpcode() != ISD::MERGE_VALUES)
4285 return Elt.getNode();
4286 return Elt.getOperand(Elt.getResNo()).getNode();
4289 /// CombineConsecutiveLoads - build_pair (load, load) -> load
4290 /// if load locations are consecutive.
4291 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
4292 assert(N->getOpcode() == ISD::BUILD_PAIR);
4294 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
4295 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
4296 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
4298 EVT LD1VT = LD1->getValueType(0);
4300 if (ISD::isNON_EXTLoad(LD2) &&
4302 // If both are volatile this would reduce the number of volatile loads.
4303 // If one is volatile it might be ok, but play conservative and bail out.
4304 !LD1->isVolatile() &&
4305 !LD2->isVolatile() &&
4306 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
4307 unsigned Align = LD1->getAlignment();
4308 unsigned NewAlign = TLI.getTargetData()->
4309 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4311 if (NewAlign <= Align &&
4312 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
4313 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
4314 LD1->getBasePtr(), LD1->getSrcValue(),
4315 LD1->getSrcValueOffset(), false, false, Align);
4321 SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
4322 SDValue N0 = N->getOperand(0);
4323 EVT VT = N->getValueType(0);
4325 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
4326 // Only do this before legalize, since afterward the target may be depending
4327 // on the bitconvert.
4328 // First check to see if this is all constant.
4330 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
4332 bool isSimple = true;
4333 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
4334 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
4335 N0.getOperand(i).getOpcode() != ISD::Constant &&
4336 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
4341 EVT DestEltVT = N->getValueType(0).getVectorElementType();
4342 assert(!DestEltVT.isVector() &&
4343 "Element type of vector ValueType must not be vector!");
4345 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
4348 // If the input is a constant, let getNode fold it.
4349 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
4350 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0);
4351 if (Res.getNode() != N) {
4352 if (!LegalOperations ||
4353 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
4356 // Folding it resulted in an illegal node, and it's too late to
4357 // do that. Clean up the old node and forego the transformation.
4358 // Ideally this won't happen very often, because instcombine
4359 // and the earlier dagcombine runs (where illegal nodes are
4360 // permitted) should have folded most of them already.
4361 DAG.DeleteNode(Res.getNode());
4365 // (conv (conv x, t1), t2) -> (conv x, t2)
4366 if (N0.getOpcode() == ISD::BIT_CONVERT)
4367 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT,
4370 // fold (conv (load x)) -> (load (conv*)x)
4371 // If the resultant load doesn't need a higher alignment than the original!
4372 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
4373 // Do not change the width of a volatile load.
4374 !cast<LoadSDNode>(N0)->isVolatile() &&
4375 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
4376 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4377 unsigned Align = TLI.getTargetData()->
4378 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4379 unsigned OrigAlign = LN0->getAlignment();
4381 if (Align <= OrigAlign) {
4382 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
4384 LN0->getSrcValue(), LN0->getSrcValueOffset(),
4385 LN0->isVolatile(), LN0->isNonTemporal(),
4388 CombineTo(N0.getNode(),
4389 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4390 N0.getValueType(), Load),
4396 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
4397 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
4398 // This often reduces constant pool loads.
4399 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
4400 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
4401 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT,
4403 AddToWorkList(NewConv.getNode());
4405 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4406 if (N0.getOpcode() == ISD::FNEG)
4407 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
4408 NewConv, DAG.getConstant(SignBit, VT));
4409 assert(N0.getOpcode() == ISD::FABS);
4410 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4411 NewConv, DAG.getConstant(~SignBit, VT));
4414 // fold (bitconvert (fcopysign cst, x)) ->
4415 // (or (and (bitconvert x), sign), (and cst, (not sign)))
4416 // Note that we don't handle (copysign x, cst) because this can always be
4417 // folded to an fneg or fabs.
4418 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
4419 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
4420 VT.isInteger() && !VT.isVector()) {
4421 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
4422 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
4423 if (isTypeLegal(IntXVT)) {
4424 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4425 IntXVT, N0.getOperand(1));
4426 AddToWorkList(X.getNode());
4428 // If X has a different width than the result/lhs, sext it or truncate it.
4429 unsigned VTWidth = VT.getSizeInBits();
4430 if (OrigXWidth < VTWidth) {
4431 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
4432 AddToWorkList(X.getNode());
4433 } else if (OrigXWidth > VTWidth) {
4434 // To get the sign bit in the right place, we have to shift it right
4435 // before truncating.
4436 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
4437 X.getValueType(), X,
4438 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
4439 AddToWorkList(X.getNode());
4440 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4441 AddToWorkList(X.getNode());
4444 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4445 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
4446 X, DAG.getConstant(SignBit, VT));
4447 AddToWorkList(X.getNode());
4449 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4450 VT, N0.getOperand(0));
4451 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
4452 Cst, DAG.getConstant(~SignBit, VT));
4453 AddToWorkList(Cst.getNode());
4455 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
4459 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
4460 if (N0.getOpcode() == ISD::BUILD_PAIR) {
4461 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
4462 if (CombineLD.getNode())
4469 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
4470 EVT VT = N->getValueType(0);
4471 return CombineConsecutiveLoads(N, VT);
4474 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
4475 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
4476 /// destination element value type.
4477 SDValue DAGCombiner::
4478 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
4479 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
4481 // If this is already the right type, we're done.
4482 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
4484 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
4485 unsigned DstBitSize = DstEltVT.getSizeInBits();
4487 // If this is a conversion of N elements of one type to N elements of another
4488 // type, convert each element. This handles FP<->INT cases.
4489 if (SrcBitSize == DstBitSize) {
4490 SmallVector<SDValue, 8> Ops;
4491 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4492 SDValue Op = BV->getOperand(i);
4493 // If the vector element type is not legal, the BUILD_VECTOR operands
4494 // are promoted and implicitly truncated. Make that explicit here.
4495 if (Op.getValueType() != SrcEltVT)
4496 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
4497 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(),
4499 AddToWorkList(Ops.back().getNode());
4501 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4502 BV->getValueType(0).getVectorNumElements());
4503 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4504 &Ops[0], Ops.size());
4507 // Otherwise, we're growing or shrinking the elements. To avoid having to
4508 // handle annoying details of growing/shrinking FP values, we convert them to
4510 if (SrcEltVT.isFloatingPoint()) {
4511 // Convert the input float vector to a int vector where the elements are the
4513 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
4514 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
4515 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
4519 // Now we know the input is an integer vector. If the output is a FP type,
4520 // convert to integer first, then to FP of the right size.
4521 if (DstEltVT.isFloatingPoint()) {
4522 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
4523 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
4524 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
4526 // Next, convert to FP elements of the same size.
4527 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
4530 // Okay, we know the src/dst types are both integers of differing types.
4531 // Handling growing first.
4532 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
4533 if (SrcBitSize < DstBitSize) {
4534 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
4536 SmallVector<SDValue, 8> Ops;
4537 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
4538 i += NumInputsPerOutput) {
4539 bool isLE = TLI.isLittleEndian();
4540 APInt NewBits = APInt(DstBitSize, 0);
4541 bool EltIsUndef = true;
4542 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
4543 // Shift the previously computed bits over.
4544 NewBits <<= SrcBitSize;
4545 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
4546 if (Op.getOpcode() == ISD::UNDEF) continue;
4549 NewBits |= APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).
4550 zextOrTrunc(SrcBitSize).zext(DstBitSize);
4554 Ops.push_back(DAG.getUNDEF(DstEltVT));
4556 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
4559 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
4560 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4561 &Ops[0], Ops.size());
4564 // Finally, this must be the case where we are shrinking elements: each input
4565 // turns into multiple outputs.
4566 bool isS2V = ISD::isScalarToVector(BV);
4567 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
4568 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4569 NumOutputsPerInput*BV->getNumOperands());
4570 SmallVector<SDValue, 8> Ops;
4572 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4573 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
4574 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
4575 Ops.push_back(DAG.getUNDEF(DstEltVT));
4579 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))->
4580 getAPIntValue()).zextOrTrunc(SrcBitSize);
4582 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
4583 APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
4584 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
4585 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
4586 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
4587 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
4589 OpVal = OpVal.lshr(DstBitSize);
4592 // For big endian targets, swap the order of the pieces of each element.
4593 if (TLI.isBigEndian())
4594 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
4597 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4598 &Ops[0], Ops.size());
4601 SDValue DAGCombiner::visitFADD(SDNode *N) {
4602 SDValue N0 = N->getOperand(0);
4603 SDValue N1 = N->getOperand(1);
4604 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4605 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4606 EVT VT = N->getValueType(0);
4609 if (VT.isVector()) {
4610 SDValue FoldedVOp = SimplifyVBinOp(N);
4611 if (FoldedVOp.getNode()) return FoldedVOp;
4614 // fold (fadd c1, c2) -> (fadd c1, c2)
4615 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4616 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
4617 // canonicalize constant to RHS
4618 if (N0CFP && !N1CFP)
4619 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
4620 // fold (fadd A, 0) -> A
4621 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4623 // fold (fadd A, (fneg B)) -> (fsub A, B)
4624 if (isNegatibleForFree(N1, LegalOperations) == 2)
4625 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
4626 GetNegatedExpression(N1, DAG, LegalOperations));
4627 // fold (fadd (fneg A), B) -> (fsub B, A)
4628 if (isNegatibleForFree(N0, LegalOperations) == 2)
4629 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
4630 GetNegatedExpression(N0, DAG, LegalOperations));
4632 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
4633 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
4634 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4635 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
4636 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
4637 N0.getOperand(1), N1));
4642 SDValue DAGCombiner::visitFSUB(SDNode *N) {
4643 SDValue N0 = N->getOperand(0);
4644 SDValue N1 = N->getOperand(1);
4645 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4646 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4647 EVT VT = N->getValueType(0);
4650 if (VT.isVector()) {
4651 SDValue FoldedVOp = SimplifyVBinOp(N);
4652 if (FoldedVOp.getNode()) return FoldedVOp;
4655 // fold (fsub c1, c2) -> c1-c2
4656 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4657 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
4658 // fold (fsub A, 0) -> A
4659 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4661 // fold (fsub 0, B) -> -B
4662 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
4663 if (isNegatibleForFree(N1, LegalOperations))
4664 return GetNegatedExpression(N1, DAG, LegalOperations);
4665 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4666 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
4668 // fold (fsub A, (fneg B)) -> (fadd A, B)
4669 if (isNegatibleForFree(N1, LegalOperations))
4670 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
4671 GetNegatedExpression(N1, DAG, LegalOperations));
4676 SDValue DAGCombiner::visitFMUL(SDNode *N) {
4677 SDValue N0 = N->getOperand(0);
4678 SDValue N1 = N->getOperand(1);
4679 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4680 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4681 EVT VT = N->getValueType(0);
4684 if (VT.isVector()) {
4685 SDValue FoldedVOp = SimplifyVBinOp(N);
4686 if (FoldedVOp.getNode()) return FoldedVOp;
4689 // fold (fmul c1, c2) -> c1*c2
4690 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4691 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
4692 // canonicalize constant to RHS
4693 if (N0CFP && !N1CFP)
4694 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
4695 // fold (fmul A, 0) -> 0
4696 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4698 // fold (fmul A, 0) -> 0, vector edition.
4699 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
4701 // fold (fmul X, 2.0) -> (fadd X, X)
4702 if (N1CFP && N1CFP->isExactlyValue(+2.0))
4703 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
4704 // fold (fmul X, -1.0) -> (fneg X)
4705 if (N1CFP && N1CFP->isExactlyValue(-1.0))
4706 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4707 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
4709 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
4710 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4711 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4712 // Both can be negated for free, check to see if at least one is cheaper
4714 if (LHSNeg == 2 || RHSNeg == 2)
4715 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4716 GetNegatedExpression(N0, DAG, LegalOperations),
4717 GetNegatedExpression(N1, DAG, LegalOperations));
4721 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
4722 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
4723 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4724 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
4725 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4726 N0.getOperand(1), N1));
4731 SDValue DAGCombiner::visitFDIV(SDNode *N) {
4732 SDValue N0 = N->getOperand(0);
4733 SDValue N1 = N->getOperand(1);
4734 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4735 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4736 EVT VT = N->getValueType(0);
4739 if (VT.isVector()) {
4740 SDValue FoldedVOp = SimplifyVBinOp(N);
4741 if (FoldedVOp.getNode()) return FoldedVOp;
4744 // fold (fdiv c1, c2) -> c1/c2
4745 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4746 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
4749 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
4750 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4751 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4752 // Both can be negated for free, check to see if at least one is cheaper
4754 if (LHSNeg == 2 || RHSNeg == 2)
4755 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
4756 GetNegatedExpression(N0, DAG, LegalOperations),
4757 GetNegatedExpression(N1, DAG, LegalOperations));
4764 SDValue DAGCombiner::visitFREM(SDNode *N) {
4765 SDValue N0 = N->getOperand(0);
4766 SDValue N1 = N->getOperand(1);
4767 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4768 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4769 EVT VT = N->getValueType(0);
4771 // fold (frem c1, c2) -> fmod(c1,c2)
4772 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4773 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
4778 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
4779 SDValue N0 = N->getOperand(0);
4780 SDValue N1 = N->getOperand(1);
4781 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4782 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4783 EVT VT = N->getValueType(0);
4785 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
4786 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
4789 const APFloat& V = N1CFP->getValueAPF();
4790 // copysign(x, c1) -> fabs(x) iff ispos(c1)
4791 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
4792 if (!V.isNegative()) {
4793 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
4794 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4796 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4797 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
4798 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
4802 // copysign(fabs(x), y) -> copysign(x, y)
4803 // copysign(fneg(x), y) -> copysign(x, y)
4804 // copysign(copysign(x,z), y) -> copysign(x, y)
4805 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
4806 N0.getOpcode() == ISD::FCOPYSIGN)
4807 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4808 N0.getOperand(0), N1);
4810 // copysign(x, abs(y)) -> abs(x)
4811 if (N1.getOpcode() == ISD::FABS)
4812 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4814 // copysign(x, copysign(y,z)) -> copysign(x, z)
4815 if (N1.getOpcode() == ISD::FCOPYSIGN)
4816 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4817 N0, N1.getOperand(1));
4819 // copysign(x, fp_extend(y)) -> copysign(x, y)
4820 // copysign(x, fp_round(y)) -> copysign(x, y)
4821 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
4822 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4823 N0, N1.getOperand(0));
4828 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
4829 SDValue N0 = N->getOperand(0);
4830 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4831 EVT VT = N->getValueType(0);
4832 EVT OpVT = N0.getValueType();
4834 // fold (sint_to_fp c1) -> c1fp
4835 if (N0C && OpVT != MVT::ppcf128)
4836 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4838 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
4839 // but UINT_TO_FP is legal on this target, try to convert.
4840 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
4841 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
4842 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
4843 if (DAG.SignBitIsZero(N0))
4844 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4850 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
4851 SDValue N0 = N->getOperand(0);
4852 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4853 EVT VT = N->getValueType(0);
4854 EVT OpVT = N0.getValueType();
4856 // fold (uint_to_fp c1) -> c1fp
4857 if (N0C && OpVT != MVT::ppcf128)
4858 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4860 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
4861 // but SINT_TO_FP is legal on this target, try to convert.
4862 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
4863 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
4864 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
4865 if (DAG.SignBitIsZero(N0))
4866 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4872 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
4873 SDValue N0 = N->getOperand(0);
4874 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4875 EVT VT = N->getValueType(0);
4877 // fold (fp_to_sint c1fp) -> c1
4879 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
4884 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
4885 SDValue N0 = N->getOperand(0);
4886 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4887 EVT VT = N->getValueType(0);
4889 // fold (fp_to_uint c1fp) -> c1
4890 if (N0CFP && VT != MVT::ppcf128)
4891 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
4896 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
4897 SDValue N0 = N->getOperand(0);
4898 SDValue N1 = N->getOperand(1);
4899 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4900 EVT VT = N->getValueType(0);
4902 // fold (fp_round c1fp) -> c1fp
4903 if (N0CFP && N0.getValueType() != MVT::ppcf128)
4904 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
4906 // fold (fp_round (fp_extend x)) -> x
4907 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
4908 return N0.getOperand(0);
4910 // fold (fp_round (fp_round x)) -> (fp_round x)
4911 if (N0.getOpcode() == ISD::FP_ROUND) {
4912 // This is a value preserving truncation if both round's are.
4913 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
4914 N0.getNode()->getConstantOperandVal(1) == 1;
4915 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
4916 DAG.getIntPtrConstant(IsTrunc));
4919 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
4920 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
4921 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
4922 N0.getOperand(0), N1);
4923 AddToWorkList(Tmp.getNode());
4924 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4925 Tmp, N0.getOperand(1));
4931 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
4932 SDValue N0 = N->getOperand(0);
4933 EVT VT = N->getValueType(0);
4934 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4935 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4937 // fold (fp_round_inreg c1fp) -> c1fp
4938 if (N0CFP && isTypeLegal(EVT)) {
4939 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
4940 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
4946 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
4947 SDValue N0 = N->getOperand(0);
4948 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4949 EVT VT = N->getValueType(0);
4951 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
4952 if (N->hasOneUse() &&
4953 N->use_begin()->getOpcode() == ISD::FP_ROUND)
4956 // fold (fp_extend c1fp) -> c1fp
4957 if (N0CFP && VT != MVT::ppcf128)
4958 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
4960 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
4962 if (N0.getOpcode() == ISD::FP_ROUND
4963 && N0.getNode()->getConstantOperandVal(1) == 1) {
4964 SDValue In = N0.getOperand(0);
4965 if (In.getValueType() == VT) return In;
4966 if (VT.bitsLT(In.getValueType()))
4967 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
4968 In, N0.getOperand(1));
4969 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
4972 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
4973 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
4974 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4975 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4976 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4977 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4979 LN0->getBasePtr(), LN0->getSrcValue(),
4980 LN0->getSrcValueOffset(),
4982 LN0->isVolatile(), LN0->isNonTemporal(),
4983 LN0->getAlignment());
4984 CombineTo(N, ExtLoad);
4985 CombineTo(N0.getNode(),
4986 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
4987 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
4988 ExtLoad.getValue(1));
4989 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4995 SDValue DAGCombiner::visitFNEG(SDNode *N) {
4996 SDValue N0 = N->getOperand(0);
4997 EVT VT = N->getValueType(0);
4999 if (isNegatibleForFree(N0, LegalOperations))
5000 return GetNegatedExpression(N0, DAG, LegalOperations);
5002 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
5003 // constant pool values.
5004 if (N0.getOpcode() == ISD::BIT_CONVERT &&
5006 N0.getNode()->hasOneUse() &&
5007 N0.getOperand(0).getValueType().isInteger()) {
5008 SDValue Int = N0.getOperand(0);
5009 EVT IntVT = Int.getValueType();
5010 if (IntVT.isInteger() && !IntVT.isVector()) {
5011 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
5012 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5013 AddToWorkList(Int.getNode());
5014 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
5022 SDValue DAGCombiner::visitFABS(SDNode *N) {
5023 SDValue N0 = N->getOperand(0);
5024 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5025 EVT VT = N->getValueType(0);
5027 // fold (fabs c1) -> fabs(c1)
5028 if (N0CFP && VT != MVT::ppcf128)
5029 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5030 // fold (fabs (fabs x)) -> (fabs x)
5031 if (N0.getOpcode() == ISD::FABS)
5032 return N->getOperand(0);
5033 // fold (fabs (fneg x)) -> (fabs x)
5034 // fold (fabs (fcopysign x, y)) -> (fabs x)
5035 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
5036 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
5038 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
5039 // constant pool values.
5040 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
5041 N0.getOperand(0).getValueType().isInteger() &&
5042 !N0.getOperand(0).getValueType().isVector()) {
5043 SDValue Int = N0.getOperand(0);
5044 EVT IntVT = Int.getValueType();
5045 if (IntVT.isInteger() && !IntVT.isVector()) {
5046 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
5047 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5048 AddToWorkList(Int.getNode());
5049 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
5050 N->getValueType(0), Int);
5057 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
5058 SDValue Chain = N->getOperand(0);
5059 SDValue N1 = N->getOperand(1);
5060 SDValue N2 = N->getOperand(2);
5062 // If N is a constant we could fold this into a fallthrough or unconditional
5063 // branch. However that doesn't happen very often in normal code, because
5064 // Instcombine/SimplifyCFG should have handled the available opportunities.
5065 // If we did this folding here, it would be necessary to update the
5066 // MachineBasicBlock CFG, which is awkward.
5068 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
5070 if (N1.getOpcode() == ISD::SETCC &&
5071 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
5072 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5073 Chain, N1.getOperand(2),
5074 N1.getOperand(0), N1.getOperand(1), N2);
5078 if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) {
5079 // Look past truncate.
5080 Trunc = N1.getNode();
5081 N1 = N1.getOperand(0);
5084 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) {
5085 // Match this pattern so that we can generate simpler code:
5088 // %b = and i32 %a, 2
5089 // %c = srl i32 %b, 1
5090 // brcond i32 %c ...
5095 // %b = and i32 %a, 2
5096 // %c = setcc eq %b, 0
5099 // This applies only when the AND constant value has one bit set and the
5100 // SRL constant is equal to the log2 of the AND constant. The back-end is
5101 // smart enough to convert the result into a TEST/JMP sequence.
5102 SDValue Op0 = N1.getOperand(0);
5103 SDValue Op1 = N1.getOperand(1);
5105 if (Op0.getOpcode() == ISD::AND &&
5106 Op1.getOpcode() == ISD::Constant) {
5107 SDValue AndOp1 = Op0.getOperand(1);
5109 if (AndOp1.getOpcode() == ISD::Constant) {
5110 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
5112 if (AndConst.isPowerOf2() &&
5113 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
5115 DAG.getSetCC(N->getDebugLoc(),
5116 TLI.getSetCCResultType(Op0.getValueType()),
5117 Op0, DAG.getConstant(0, Op0.getValueType()),
5120 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5121 MVT::Other, Chain, SetCC, N2);
5122 // Don't add the new BRCond into the worklist or else SimplifySelectCC
5123 // will convert it back to (X & C1) >> C2.
5124 CombineTo(N, NewBRCond, false);
5125 // Truncate is dead.
5127 removeFromWorkList(Trunc);
5128 DAG.DeleteNode(Trunc);
5130 // Replace the uses of SRL with SETCC
5131 WorkListRemover DeadNodes(*this);
5132 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5133 removeFromWorkList(N1.getNode());
5134 DAG.DeleteNode(N1.getNode());
5135 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5141 // Transform br(xor(x, y)) -> br(x != y)
5142 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
5143 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
5144 SDNode *TheXor = N1.getNode();
5145 SDValue Op0 = TheXor->getOperand(0);
5146 SDValue Op1 = TheXor->getOperand(1);
5147 if (Op0.getOpcode() == Op1.getOpcode()) {
5148 // Avoid missing important xor optimizations.
5149 SDValue Tmp = visitXOR(TheXor);
5150 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
5151 DEBUG(dbgs() << "\nReplacing.8 ";
5153 dbgs() << "\nWith: ";
5154 Tmp.getNode()->dump(&DAG);
5156 WorkListRemover DeadNodes(*this);
5157 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
5158 removeFromWorkList(TheXor);
5159 DAG.DeleteNode(TheXor);
5160 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5161 MVT::Other, Chain, Tmp, N2);
5165 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
5167 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
5168 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
5169 Op0.getOpcode() == ISD::XOR) {
5170 TheXor = Op0.getNode();
5174 SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1;
5176 EVT SetCCVT = NodeToReplace.getValueType();
5178 SetCCVT = TLI.getSetCCResultType(SetCCVT);
5179 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
5182 Equal ? ISD::SETEQ : ISD::SETNE);
5183 // Replace the uses of XOR with SETCC
5184 WorkListRemover DeadNodes(*this);
5185 DAG.ReplaceAllUsesOfValueWith(NodeToReplace, SetCC, &DeadNodes);
5186 removeFromWorkList(NodeToReplace.getNode());
5187 DAG.DeleteNode(NodeToReplace.getNode());
5188 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5189 MVT::Other, Chain, SetCC, N2);
5196 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
5198 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
5199 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
5200 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
5202 // If N is a constant we could fold this into a fallthrough or unconditional
5203 // branch. However that doesn't happen very often in normal code, because
5204 // Instcombine/SimplifyCFG should have handled the available opportunities.
5205 // If we did this folding here, it would be necessary to update the
5206 // MachineBasicBlock CFG, which is awkward.
5208 // Use SimplifySetCC to simplify SETCC's.
5209 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
5210 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
5212 if (Simp.getNode()) AddToWorkList(Simp.getNode());
5214 // fold to a simpler setcc
5215 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
5216 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5217 N->getOperand(0), Simp.getOperand(2),
5218 Simp.getOperand(0), Simp.getOperand(1),
5224 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
5225 /// pre-indexed load / store when the base pointer is an add or subtract
5226 /// and it has other uses besides the load / store. After the
5227 /// transformation, the new indexed load / store has effectively folded
5228 /// the add / subtract in and all of its other uses are redirected to the
5229 /// new load / store.
5230 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
5231 if (!LegalOperations)
5237 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5238 if (LD->isIndexed())
5240 VT = LD->getMemoryVT();
5241 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
5242 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
5244 Ptr = LD->getBasePtr();
5245 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5246 if (ST->isIndexed())
5248 VT = ST->getMemoryVT();
5249 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
5250 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
5252 Ptr = ST->getBasePtr();
5258 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
5259 // out. There is no reason to make this a preinc/predec.
5260 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
5261 Ptr.getNode()->hasOneUse())
5264 // Ask the target to do addressing mode selection.
5267 ISD::MemIndexedMode AM = ISD::UNINDEXED;
5268 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
5270 // Don't create a indexed load / store with zero offset.
5271 if (isa<ConstantSDNode>(Offset) &&
5272 cast<ConstantSDNode>(Offset)->isNullValue())
5275 // Try turning it into a pre-indexed load / store except when:
5276 // 1) The new base ptr is a frame index.
5277 // 2) If N is a store and the new base ptr is either the same as or is a
5278 // predecessor of the value being stored.
5279 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
5280 // that would create a cycle.
5281 // 4) All uses are load / store ops that use it as old base ptr.
5283 // Check #1. Preinc'ing a frame index would require copying the stack pointer
5284 // (plus the implicit offset) to a register to preinc anyway.
5285 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5290 SDValue Val = cast<StoreSDNode>(N)->getValue();
5291 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
5295 // Now check for #3 and #4.
5296 bool RealUse = false;
5297 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5298 E = Ptr.getNode()->use_end(); I != E; ++I) {
5302 if (Use->isPredecessorOf(N))
5305 if (!((Use->getOpcode() == ISD::LOAD &&
5306 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
5307 (Use->getOpcode() == ISD::STORE &&
5308 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
5317 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5318 BasePtr, Offset, AM);
5320 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5321 BasePtr, Offset, AM);
5324 DEBUG(dbgs() << "\nReplacing.4 ";
5326 dbgs() << "\nWith: ";
5327 Result.getNode()->dump(&DAG);
5329 WorkListRemover DeadNodes(*this);
5331 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5333 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5336 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5340 // Finally, since the node is now dead, remove it from the graph.
5343 // Replace the uses of Ptr with uses of the updated base value.
5344 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
5346 removeFromWorkList(Ptr.getNode());
5347 DAG.DeleteNode(Ptr.getNode());
5352 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
5353 /// add / sub of the base pointer node into a post-indexed load / store.
5354 /// The transformation folded the add / subtract into the new indexed
5355 /// load / store effectively and all of its uses are redirected to the
5356 /// new load / store.
5357 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
5358 if (!LegalOperations)
5364 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5365 if (LD->isIndexed())
5367 VT = LD->getMemoryVT();
5368 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
5369 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
5371 Ptr = LD->getBasePtr();
5372 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5373 if (ST->isIndexed())
5375 VT = ST->getMemoryVT();
5376 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
5377 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
5379 Ptr = ST->getBasePtr();
5385 if (Ptr.getNode()->hasOneUse())
5388 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5389 E = Ptr.getNode()->use_end(); I != E; ++I) {
5392 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
5397 ISD::MemIndexedMode AM = ISD::UNINDEXED;
5398 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
5399 // Don't create a indexed load / store with zero offset.
5400 if (isa<ConstantSDNode>(Offset) &&
5401 cast<ConstantSDNode>(Offset)->isNullValue())
5404 // Try turning it into a post-indexed load / store except when
5405 // 1) All uses are load / store ops that use it as base ptr.
5406 // 2) Op must be independent of N, i.e. Op is neither a predecessor
5407 // nor a successor of N. Otherwise, if Op is folded that would
5410 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5414 bool TryNext = false;
5415 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
5416 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
5418 if (Use == Ptr.getNode())
5421 // If all the uses are load / store addresses, then don't do the
5423 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
5424 bool RealUse = false;
5425 for (SDNode::use_iterator III = Use->use_begin(),
5426 EEE = Use->use_end(); III != EEE; ++III) {
5427 SDNode *UseUse = *III;
5428 if (!((UseUse->getOpcode() == ISD::LOAD &&
5429 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
5430 (UseUse->getOpcode() == ISD::STORE &&
5431 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
5446 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
5447 SDValue Result = isLoad
5448 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5449 BasePtr, Offset, AM)
5450 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5451 BasePtr, Offset, AM);
5454 DEBUG(dbgs() << "\nReplacing.5 ";
5456 dbgs() << "\nWith: ";
5457 Result.getNode()->dump(&DAG);
5459 WorkListRemover DeadNodes(*this);
5461 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5463 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5466 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5470 // Finally, since the node is now dead, remove it from the graph.
5473 // Replace the uses of Use with uses of the updated base value.
5474 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
5475 Result.getValue(isLoad ? 1 : 0),
5477 removeFromWorkList(Op);
5487 SDValue DAGCombiner::visitLOAD(SDNode *N) {
5488 LoadSDNode *LD = cast<LoadSDNode>(N);
5489 SDValue Chain = LD->getChain();
5490 SDValue Ptr = LD->getBasePtr();
5492 // If load is not volatile and there are no uses of the loaded value (and
5493 // the updated indexed value in case of indexed loads), change uses of the
5494 // chain value into uses of the chain input (i.e. delete the dead load).
5495 if (!LD->isVolatile()) {
5496 if (N->getValueType(1) == MVT::Other) {
5498 if (N->hasNUsesOfValue(0, 0)) {
5499 // It's not safe to use the two value CombineTo variant here. e.g.
5500 // v1, chain2 = load chain1, loc
5501 // v2, chain3 = load chain2, loc
5503 // Now we replace use of chain2 with chain1. This makes the second load
5504 // isomorphic to the one we are deleting, and thus makes this load live.
5505 DEBUG(dbgs() << "\nReplacing.6 ";
5507 dbgs() << "\nWith chain: ";
5508 Chain.getNode()->dump(&DAG);
5510 WorkListRemover DeadNodes(*this);
5511 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
5513 if (N->use_empty()) {
5514 removeFromWorkList(N);
5518 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5522 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
5523 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
5524 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
5525 DEBUG(dbgs() << "\nReplacing.7 ";
5527 dbgs() << "\nWith: ";
5528 Undef.getNode()->dump(&DAG);
5529 dbgs() << " and 2 other values\n");
5530 WorkListRemover DeadNodes(*this);
5531 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
5532 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
5533 DAG.getUNDEF(N->getValueType(1)),
5535 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
5536 removeFromWorkList(N);
5538 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5543 // If this load is directly stored, replace the load value with the stored
5545 // TODO: Handle store large -> read small portion.
5546 // TODO: Handle TRUNCSTORE/LOADEXT
5547 if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
5548 !LD->isVolatile()) {
5549 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
5550 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
5551 if (PrevST->getBasePtr() == Ptr &&
5552 PrevST->getValue().getValueType() == N->getValueType(0))
5553 return CombineTo(N, Chain.getOperand(1), Chain);
5557 // Try to infer better alignment information than the load already has.
5558 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
5559 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5560 if (Align > LD->getAlignment())
5561 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
5562 LD->getValueType(0),
5563 Chain, Ptr, LD->getSrcValue(),
5564 LD->getSrcValueOffset(), LD->getMemoryVT(),
5565 LD->isVolatile(), LD->isNonTemporal(), Align);
5570 // Walk up chain skipping non-aliasing memory nodes.
5571 SDValue BetterChain = FindBetterChain(N, Chain);
5573 // If there is a better chain.
5574 if (Chain != BetterChain) {
5577 // Replace the chain to void dependency.
5578 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
5579 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
5581 LD->getSrcValue(), LD->getSrcValueOffset(),
5582 LD->isVolatile(), LD->isNonTemporal(),
5583 LD->getAlignment());
5585 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
5586 LD->getValueType(0),
5587 BetterChain, Ptr, LD->getSrcValue(),
5588 LD->getSrcValueOffset(),
5591 LD->isNonTemporal(),
5592 LD->getAlignment());
5595 // Create token factor to keep old chain connected.
5596 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5597 MVT::Other, Chain, ReplLoad.getValue(1));
5599 // Make sure the new and old chains are cleaned up.
5600 AddToWorkList(Token.getNode());
5602 // Replace uses with load result and token factor. Don't add users
5604 return CombineTo(N, ReplLoad.getValue(0), Token, false);
5608 // Try transforming N to an indexed load.
5609 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5610 return SDValue(N, 0);
5615 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
5616 /// load is having specific bytes cleared out. If so, return the byte size
5617 /// being masked out and the shift amount.
5618 static std::pair<unsigned, unsigned>
5619 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
5620 std::pair<unsigned, unsigned> Result(0, 0);
5622 // Check for the structure we're looking for.
5623 if (V->getOpcode() != ISD::AND ||
5624 !isa<ConstantSDNode>(V->getOperand(1)) ||
5625 !ISD::isNormalLoad(V->getOperand(0).getNode()))
5628 // Check the chain and pointer.
5629 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
5630 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
5632 // The store should be chained directly to the load or be an operand of a
5634 if (LD == Chain.getNode())
5636 else if (Chain->getOpcode() != ISD::TokenFactor)
5637 return Result; // Fail.
5640 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
5641 if (Chain->getOperand(i).getNode() == LD) {
5645 if (!isOk) return Result;
5648 // This only handles simple types.
5649 if (V.getValueType() != MVT::i16 &&
5650 V.getValueType() != MVT::i32 &&
5651 V.getValueType() != MVT::i64)
5654 // Check the constant mask. Invert it so that the bits being masked out are
5655 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
5656 // follow the sign bit for uniformity.
5657 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
5658 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
5659 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
5660 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
5661 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
5662 if (NotMaskLZ == 64) return Result; // All zero mask.
5664 // See if we have a continuous run of bits. If so, we have 0*1+0*
5665 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
5668 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
5669 if (V.getValueType() != MVT::i64 && NotMaskLZ)
5670 NotMaskLZ -= 64-V.getValueSizeInBits();
5672 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
5673 switch (MaskedBytes) {
5677 default: return Result; // All one mask, or 5-byte mask.
5680 // Verify that the first bit starts at a multiple of mask so that the access
5681 // is aligned the same as the access width.
5682 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
5684 Result.first = MaskedBytes;
5685 Result.second = NotMaskTZ/8;
5690 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
5691 /// provides a value as specified by MaskInfo. If so, replace the specified
5692 /// store with a narrower store of truncated IVal.
5694 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
5695 SDValue IVal, StoreSDNode *St,
5697 unsigned NumBytes = MaskInfo.first;
5698 unsigned ByteShift = MaskInfo.second;
5699 SelectionDAG &DAG = DC->getDAG();
5701 // Check to see if IVal is all zeros in the part being masked in by the 'or'
5702 // that uses this. If not, this is not a replacement.
5703 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
5704 ByteShift*8, (ByteShift+NumBytes)*8);
5705 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
5707 // Check that it is legal on the target to do this. It is legal if the new
5708 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
5710 MVT VT = MVT::getIntegerVT(NumBytes*8);
5711 if (!DC->isTypeLegal(VT))
5714 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
5715 // shifted by ByteShift and truncated down to NumBytes.
5717 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
5718 DAG.getConstant(ByteShift*8, DC->getShiftAmountTy()));
5720 // Figure out the offset for the store and the alignment of the access.
5722 unsigned NewAlign = St->getAlignment();
5724 if (DAG.getTargetLoweringInfo().isLittleEndian())
5725 StOffset = ByteShift;
5727 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
5729 SDValue Ptr = St->getBasePtr();
5731 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
5732 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
5733 NewAlign = MinAlign(NewAlign, StOffset);
5736 // Truncate down to the new size.
5737 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
5740 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
5741 St->getSrcValue(), St->getSrcValueOffset()+StOffset,
5742 false, false, NewAlign).getNode();
5746 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
5747 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
5748 /// of the loaded bits, try narrowing the load and store if it would end up
5749 /// being a win for performance or code size.
5750 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
5751 StoreSDNode *ST = cast<StoreSDNode>(N);
5752 if (ST->isVolatile())
5755 SDValue Chain = ST->getChain();
5756 SDValue Value = ST->getValue();
5757 SDValue Ptr = ST->getBasePtr();
5758 EVT VT = Value.getValueType();
5760 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
5763 unsigned Opc = Value.getOpcode();
5765 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
5766 // is a byte mask indicating a consecutive number of bytes, check to see if
5767 // Y is known to provide just those bytes. If so, we try to replace the
5768 // load + replace + store sequence with a single (narrower) store, which makes
5770 if (Opc == ISD::OR) {
5771 std::pair<unsigned, unsigned> MaskedLoad;
5772 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
5773 if (MaskedLoad.first)
5774 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
5775 Value.getOperand(1), ST,this))
5776 return SDValue(NewST, 0);
5778 // Or is commutative, so try swapping X and Y.
5779 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
5780 if (MaskedLoad.first)
5781 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
5782 Value.getOperand(0), ST,this))
5783 return SDValue(NewST, 0);
5786 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
5787 Value.getOperand(1).getOpcode() != ISD::Constant)
5790 SDValue N0 = Value.getOperand(0);
5791 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) {
5792 LoadSDNode *LD = cast<LoadSDNode>(N0);
5793 if (LD->getBasePtr() != Ptr)
5796 // Find the type to narrow it the load / op / store to.
5797 SDValue N1 = Value.getOperand(1);
5798 unsigned BitWidth = N1.getValueSizeInBits();
5799 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
5800 if (Opc == ISD::AND)
5801 Imm ^= APInt::getAllOnesValue(BitWidth);
5802 if (Imm == 0 || Imm.isAllOnesValue())
5804 unsigned ShAmt = Imm.countTrailingZeros();
5805 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
5806 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
5807 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5808 while (NewBW < BitWidth &&
5809 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
5810 TLI.isNarrowingProfitable(VT, NewVT))) {
5811 NewBW = NextPowerOf2(NewBW);
5812 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5814 if (NewBW >= BitWidth)
5817 // If the lsb changed does not start at the type bitwidth boundary,
5818 // start at the previous one.
5820 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
5821 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
5822 if ((Imm & Mask) == Imm) {
5823 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
5824 if (Opc == ISD::AND)
5825 NewImm ^= APInt::getAllOnesValue(NewBW);
5826 uint64_t PtrOff = ShAmt / 8;
5827 // For big endian targets, we need to adjust the offset to the pointer to
5828 // load the correct bytes.
5829 if (TLI.isBigEndian())
5830 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
5832 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
5833 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
5834 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
5837 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
5838 Ptr.getValueType(), Ptr,
5839 DAG.getConstant(PtrOff, Ptr.getValueType()));
5840 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
5841 LD->getChain(), NewPtr,
5842 LD->getSrcValue(), LD->getSrcValueOffset(),
5843 LD->isVolatile(), LD->isNonTemporal(),
5845 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
5846 DAG.getConstant(NewImm, NewVT));
5847 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
5849 ST->getSrcValue(), ST->getSrcValueOffset(),
5850 false, false, NewAlign);
5852 AddToWorkList(NewPtr.getNode());
5853 AddToWorkList(NewLD.getNode());
5854 AddToWorkList(NewVal.getNode());
5855 WorkListRemover DeadNodes(*this);
5856 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
5866 SDValue DAGCombiner::visitSTORE(SDNode *N) {
5867 StoreSDNode *ST = cast<StoreSDNode>(N);
5868 SDValue Chain = ST->getChain();
5869 SDValue Value = ST->getValue();
5870 SDValue Ptr = ST->getBasePtr();
5872 // If this is a store of a bit convert, store the input value if the
5873 // resultant store does not need a higher alignment than the original.
5874 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
5875 ST->isUnindexed()) {
5876 unsigned OrigAlign = ST->getAlignment();
5877 EVT SVT = Value.getOperand(0).getValueType();
5878 unsigned Align = TLI.getTargetData()->
5879 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
5880 if (Align <= OrigAlign &&
5881 ((!LegalOperations && !ST->isVolatile()) ||
5882 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
5883 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5884 Ptr, ST->getSrcValue(),
5885 ST->getSrcValueOffset(), ST->isVolatile(),
5886 ST->isNonTemporal(), OrigAlign);
5889 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
5890 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
5891 // NOTE: If the original store is volatile, this transform must not increase
5892 // the number of stores. For example, on x86-32 an f64 can be stored in one
5893 // processor operation but an i64 (which is not legal) requires two. So the
5894 // transform should not be done in this case.
5895 if (Value.getOpcode() != ISD::TargetConstantFP) {
5897 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
5898 default: llvm_unreachable("Unknown FP type");
5899 case MVT::f80: // We don't do this for these yet.
5904 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
5905 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5906 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
5907 bitcastToAPInt().getZExtValue(), MVT::i32);
5908 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5909 Ptr, ST->getSrcValue(),
5910 ST->getSrcValueOffset(), ST->isVolatile(),
5911 ST->isNonTemporal(), ST->getAlignment());
5915 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
5916 !ST->isVolatile()) ||
5917 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
5918 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
5919 getZExtValue(), MVT::i64);
5920 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5921 Ptr, ST->getSrcValue(),
5922 ST->getSrcValueOffset(), ST->isVolatile(),
5923 ST->isNonTemporal(), ST->getAlignment());
5924 } else if (!ST->isVolatile() &&
5925 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5926 // Many FP stores are not made apparent until after legalize, e.g. for
5927 // argument passing. Since this is so common, custom legalize the
5928 // 64-bit integer store into two 32-bit stores.
5929 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
5930 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
5931 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
5932 if (TLI.isBigEndian()) std::swap(Lo, Hi);
5934 int SVOffset = ST->getSrcValueOffset();
5935 unsigned Alignment = ST->getAlignment();
5936 bool isVolatile = ST->isVolatile();
5937 bool isNonTemporal = ST->isNonTemporal();
5939 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
5940 Ptr, ST->getSrcValue(),
5941 ST->getSrcValueOffset(),
5942 isVolatile, isNonTemporal,
5943 ST->getAlignment());
5944 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
5945 DAG.getConstant(4, Ptr.getValueType()));
5947 Alignment = MinAlign(Alignment, 4U);
5948 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
5949 Ptr, ST->getSrcValue(),
5950 SVOffset, isVolatile, isNonTemporal,
5952 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
5961 // Try to infer better alignment information than the store already has.
5962 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
5963 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5964 if (Align > ST->getAlignment())
5965 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
5966 Ptr, ST->getSrcValue(),
5967 ST->getSrcValueOffset(), ST->getMemoryVT(),
5968 ST->isVolatile(), ST->isNonTemporal(), Align);
5973 // Walk up chain skipping non-aliasing memory nodes.
5974 SDValue BetterChain = FindBetterChain(N, Chain);
5976 // If there is a better chain.
5977 if (Chain != BetterChain) {
5980 // Replace the chain to avoid dependency.
5981 if (ST->isTruncatingStore()) {
5982 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5983 ST->getSrcValue(),ST->getSrcValueOffset(),
5984 ST->getMemoryVT(), ST->isVolatile(),
5985 ST->isNonTemporal(), ST->getAlignment());
5987 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5988 ST->getSrcValue(), ST->getSrcValueOffset(),
5989 ST->isVolatile(), ST->isNonTemporal(),
5990 ST->getAlignment());
5993 // Create token to keep both nodes around.
5994 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5995 MVT::Other, Chain, ReplStore);
5997 // Make sure the new and old chains are cleaned up.
5998 AddToWorkList(Token.getNode());
6000 // Don't add users to work list.
6001 return CombineTo(N, Token, false);
6005 // Try transforming N to an indexed store.
6006 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6007 return SDValue(N, 0);
6009 // FIXME: is there such a thing as a truncating indexed store?
6010 if (ST->isTruncatingStore() && ST->isUnindexed() &&
6011 Value.getValueType().isInteger()) {
6012 // See if we can simplify the input to this truncstore with knowledge that
6013 // only the low bits are being used. For example:
6014 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
6016 GetDemandedBits(Value,
6017 APInt::getLowBitsSet(Value.getValueSizeInBits(),
6018 ST->getMemoryVT().getSizeInBits()));
6019 AddToWorkList(Value.getNode());
6020 if (Shorter.getNode())
6021 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
6022 Ptr, ST->getSrcValue(),
6023 ST->getSrcValueOffset(), ST->getMemoryVT(),
6024 ST->isVolatile(), ST->isNonTemporal(),
6025 ST->getAlignment());
6027 // Otherwise, see if we can simplify the operation with
6028 // SimplifyDemandedBits, which only works if the value has a single use.
6029 if (SimplifyDemandedBits(Value,
6030 APInt::getLowBitsSet(
6031 Value.getValueType().getScalarType().getSizeInBits(),
6032 ST->getMemoryVT().getScalarType().getSizeInBits())))
6033 return SDValue(N, 0);
6036 // If this is a load followed by a store to the same location, then the store
6038 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
6039 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
6040 ST->isUnindexed() && !ST->isVolatile() &&
6041 // There can't be any side effects between the load and store, such as
6043 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
6044 // The store is dead, remove it.
6049 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
6050 // truncating store. We can do this even if this is already a truncstore.
6051 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
6052 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
6053 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
6054 ST->getMemoryVT())) {
6055 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6056 Ptr, ST->getSrcValue(),
6057 ST->getSrcValueOffset(), ST->getMemoryVT(),
6058 ST->isVolatile(), ST->isNonTemporal(),
6059 ST->getAlignment());
6062 return ReduceLoadOpStoreWidth(N);
6065 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
6066 SDValue InVec = N->getOperand(0);
6067 SDValue InVal = N->getOperand(1);
6068 SDValue EltNo = N->getOperand(2);
6070 // If the inserted element is an UNDEF, just use the input vector.
6071 if (InVal.getOpcode() == ISD::UNDEF)
6074 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
6075 // vector with the inserted element.
6076 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
6077 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6078 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
6079 InVec.getNode()->op_end());
6080 if (Elt < Ops.size())
6082 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6083 InVec.getValueType(), &Ops[0], Ops.size());
6085 // If the invec is an UNDEF and if EltNo is a constant, create a new
6086 // BUILD_VECTOR with undef elements and the inserted element.
6087 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF &&
6088 isa<ConstantSDNode>(EltNo)) {
6089 EVT VT = InVec.getValueType();
6090 EVT EltVT = VT.getVectorElementType();
6091 unsigned NElts = VT.getVectorNumElements();
6092 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT));
6094 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6095 if (Elt < Ops.size())
6097 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6098 InVec.getValueType(), &Ops[0], Ops.size());
6103 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
6104 // (vextract (scalar_to_vector val, 0) -> val
6105 SDValue InVec = N->getOperand(0);
6107 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
6108 // Check if the result type doesn't match the inserted element type. A
6109 // SCALAR_TO_VECTOR may truncate the inserted element and the
6110 // EXTRACT_VECTOR_ELT may widen the extracted vector.
6111 EVT EltVT = InVec.getValueType().getVectorElementType();
6112 SDValue InOp = InVec.getOperand(0);
6113 EVT NVT = N->getValueType(0);
6114 if (InOp.getValueType() != NVT) {
6115 assert(InOp.getValueType().isInteger() && NVT.isInteger());
6116 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
6121 // Perform only after legalization to ensure build_vector / vector_shuffle
6122 // optimizations have already been done.
6123 if (!LegalOperations) return SDValue();
6125 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
6126 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
6127 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
6128 SDValue EltNo = N->getOperand(1);
6130 if (isa<ConstantSDNode>(EltNo)) {
6131 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6132 bool NewLoad = false;
6133 bool BCNumEltsChanged = false;
6134 EVT VT = InVec.getValueType();
6135 EVT ExtVT = VT.getVectorElementType();
6138 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
6139 EVT BCVT = InVec.getOperand(0).getValueType();
6140 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
6142 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
6143 BCNumEltsChanged = true;
6144 InVec = InVec.getOperand(0);
6145 ExtVT = BCVT.getVectorElementType();
6149 LoadSDNode *LN0 = NULL;
6150 const ShuffleVectorSDNode *SVN = NULL;
6151 if (ISD::isNormalLoad(InVec.getNode())) {
6152 LN0 = cast<LoadSDNode>(InVec);
6153 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6154 InVec.getOperand(0).getValueType() == ExtVT &&
6155 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
6156 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
6157 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
6158 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
6160 // (load $addr+1*size)
6162 // If the bit convert changed the number of elements, it is unsafe
6163 // to examine the mask.
6164 if (BCNumEltsChanged)
6167 // Select the input vector, guarding against out of range extract vector.
6168 unsigned NumElems = VT.getVectorNumElements();
6169 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt);
6170 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
6172 if (InVec.getOpcode() == ISD::BIT_CONVERT)
6173 InVec = InVec.getOperand(0);
6174 if (ISD::isNormalLoad(InVec.getNode())) {
6175 LN0 = cast<LoadSDNode>(InVec);
6176 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
6180 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
6183 unsigned Align = LN0->getAlignment();
6185 // Check the resultant load doesn't need a higher alignment than the
6188 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
6190 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
6196 SDValue NewPtr = LN0->getBasePtr();
6198 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
6199 EVT PtrType = NewPtr.getValueType();
6200 if (TLI.isBigEndian())
6201 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
6202 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
6203 DAG.getConstant(PtrOff, PtrType));
6206 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
6207 LN0->getSrcValue(), LN0->getSrcValueOffset(),
6208 LN0->isVolatile(), LN0->isNonTemporal(), Align);
6214 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
6215 unsigned NumInScalars = N->getNumOperands();
6216 EVT VT = N->getValueType(0);
6218 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
6219 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
6220 // at most two distinct vectors, turn this into a shuffle node.
6221 SDValue VecIn1, VecIn2;
6222 for (unsigned i = 0; i != NumInScalars; ++i) {
6223 // Ignore undef inputs.
6224 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6226 // If this input is something other than a EXTRACT_VECTOR_ELT with a
6227 // constant index, bail out.
6228 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6229 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
6230 VecIn1 = VecIn2 = SDValue(0, 0);
6234 // If the input vector type disagrees with the result of the build_vector,
6235 // we can't make a shuffle.
6236 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
6237 if (ExtractedFromVec.getValueType() != VT) {
6238 VecIn1 = VecIn2 = SDValue(0, 0);
6242 // Otherwise, remember this. We allow up to two distinct input vectors.
6243 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
6246 if (VecIn1.getNode() == 0) {
6247 VecIn1 = ExtractedFromVec;
6248 } else if (VecIn2.getNode() == 0) {
6249 VecIn2 = ExtractedFromVec;
6252 VecIn1 = VecIn2 = SDValue(0, 0);
6257 // If everything is good, we can make a shuffle operation.
6258 if (VecIn1.getNode()) {
6259 SmallVector<int, 8> Mask;
6260 for (unsigned i = 0; i != NumInScalars; ++i) {
6261 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
6266 // If extracting from the first vector, just use the index directly.
6267 SDValue Extract = N->getOperand(i);
6268 SDValue ExtVal = Extract.getOperand(1);
6269 if (Extract.getOperand(0) == VecIn1) {
6270 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6271 if (ExtIndex > VT.getVectorNumElements())
6274 Mask.push_back(ExtIndex);
6278 // Otherwise, use InIdx + VecSize
6279 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6280 Mask.push_back(Idx+NumInScalars);
6283 // Add count and size info.
6284 if (!isTypeLegal(VT))
6287 // Return the new VECTOR_SHUFFLE node.
6290 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6291 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
6297 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
6298 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
6299 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
6300 // inputs come from at most two distinct vectors, turn this into a shuffle
6303 // If we only have one input vector, we don't need to do any concatenation.
6304 if (N->getNumOperands() == 1)
6305 return N->getOperand(0);
6310 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
6313 EVT VT = N->getValueType(0);
6314 unsigned NumElts = VT.getVectorNumElements();
6316 SDValue N0 = N->getOperand(0);
6318 assert(N0.getValueType().getVectorNumElements() == NumElts &&
6319 "Vector shuffle must be normalized in DAG");
6321 // FIXME: implement canonicalizations from DAG.getVectorShuffle()
6323 // If it is a splat, check if the argument vector is a build_vector with
6324 // all scalar elements the same.
6325 if (cast<ShuffleVectorSDNode>(N)->isSplat()) {
6326 SDNode *V = N0.getNode();
6328 // If this is a bit convert that changes the element type of the vector but
6329 // not the number of vector elements, look through it. Be careful not to
6330 // look though conversions that change things like v4f32 to v2f64.
6331 if (V->getOpcode() == ISD::BIT_CONVERT) {
6332 SDValue ConvInput = V->getOperand(0);
6333 if (ConvInput.getValueType().isVector() &&
6334 ConvInput.getValueType().getVectorNumElements() == NumElts)
6335 V = ConvInput.getNode();
6338 if (V->getOpcode() == ISD::BUILD_VECTOR) {
6339 unsigned NumElems = V->getNumOperands();
6340 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex();
6341 if (NumElems > BaseIdx) {
6343 bool AllSame = true;
6344 for (unsigned i = 0; i != NumElems; ++i) {
6345 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
6346 Base = V->getOperand(i);
6350 // Splat of <u, u, u, u>, return <u, u, u, u>
6351 if (!Base.getNode())
6353 for (unsigned i = 0; i != NumElems; ++i) {
6354 if (V->getOperand(i) != Base) {
6359 // Splat of <x, x, x, x>, return <x, x, x, x>
6368 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
6369 if (!TLI.getShouldFoldAtomicFences())
6372 SDValue atomic = N->getOperand(0);
6373 switch (atomic.getOpcode()) {
6374 case ISD::ATOMIC_CMP_SWAP:
6375 case ISD::ATOMIC_SWAP:
6376 case ISD::ATOMIC_LOAD_ADD:
6377 case ISD::ATOMIC_LOAD_SUB:
6378 case ISD::ATOMIC_LOAD_AND:
6379 case ISD::ATOMIC_LOAD_OR:
6380 case ISD::ATOMIC_LOAD_XOR:
6381 case ISD::ATOMIC_LOAD_NAND:
6382 case ISD::ATOMIC_LOAD_MIN:
6383 case ISD::ATOMIC_LOAD_MAX:
6384 case ISD::ATOMIC_LOAD_UMIN:
6385 case ISD::ATOMIC_LOAD_UMAX:
6391 SDValue fence = atomic.getOperand(0);
6392 if (fence.getOpcode() != ISD::MEMBARRIER)
6395 switch (atomic.getOpcode()) {
6396 case ISD::ATOMIC_CMP_SWAP:
6397 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
6398 fence.getOperand(0),
6399 atomic.getOperand(1), atomic.getOperand(2),
6400 atomic.getOperand(3)), atomic.getResNo());
6401 case ISD::ATOMIC_SWAP:
6402 case ISD::ATOMIC_LOAD_ADD:
6403 case ISD::ATOMIC_LOAD_SUB:
6404 case ISD::ATOMIC_LOAD_AND:
6405 case ISD::ATOMIC_LOAD_OR:
6406 case ISD::ATOMIC_LOAD_XOR:
6407 case ISD::ATOMIC_LOAD_NAND:
6408 case ISD::ATOMIC_LOAD_MIN:
6409 case ISD::ATOMIC_LOAD_MAX:
6410 case ISD::ATOMIC_LOAD_UMIN:
6411 case ISD::ATOMIC_LOAD_UMAX:
6412 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
6413 fence.getOperand(0),
6414 atomic.getOperand(1), atomic.getOperand(2)),
6421 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
6422 /// an AND to a vector_shuffle with the destination vector and a zero vector.
6423 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
6424 /// vector_shuffle V, Zero, <0, 4, 2, 4>
6425 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
6426 EVT VT = N->getValueType(0);
6427 DebugLoc dl = N->getDebugLoc();
6428 SDValue LHS = N->getOperand(0);
6429 SDValue RHS = N->getOperand(1);
6430 if (N->getOpcode() == ISD::AND) {
6431 if (RHS.getOpcode() == ISD::BIT_CONVERT)
6432 RHS = RHS.getOperand(0);
6433 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
6434 SmallVector<int, 8> Indices;
6435 unsigned NumElts = RHS.getNumOperands();
6436 for (unsigned i = 0; i != NumElts; ++i) {
6437 SDValue Elt = RHS.getOperand(i);
6438 if (!isa<ConstantSDNode>(Elt))
6440 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
6441 Indices.push_back(i);
6442 else if (cast<ConstantSDNode>(Elt)->isNullValue())
6443 Indices.push_back(NumElts);
6448 // Let's see if the target supports this vector_shuffle.
6449 EVT RVT = RHS.getValueType();
6450 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
6453 // Return the new VECTOR_SHUFFLE node.
6454 EVT EltVT = RVT.getVectorElementType();
6455 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
6456 DAG.getConstant(0, EltVT));
6457 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6458 RVT, &ZeroOps[0], ZeroOps.size());
6459 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS);
6460 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
6461 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf);
6468 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
6469 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
6470 // After legalize, the target may be depending on adds and other
6471 // binary ops to provide legal ways to construct constants or other
6472 // things. Simplifying them may result in a loss of legality.
6473 if (LegalOperations) return SDValue();
6475 EVT VT = N->getValueType(0);
6476 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
6478 EVT EltType = VT.getVectorElementType();
6479 SDValue LHS = N->getOperand(0);
6480 SDValue RHS = N->getOperand(1);
6481 SDValue Shuffle = XformToShuffleWithZero(N);
6482 if (Shuffle.getNode()) return Shuffle;
6484 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
6486 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
6487 RHS.getOpcode() == ISD::BUILD_VECTOR) {
6488 SmallVector<SDValue, 8> Ops;
6489 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
6490 SDValue LHSOp = LHS.getOperand(i);
6491 SDValue RHSOp = RHS.getOperand(i);
6492 // If these two elements can't be folded, bail out.
6493 if ((LHSOp.getOpcode() != ISD::UNDEF &&
6494 LHSOp.getOpcode() != ISD::Constant &&
6495 LHSOp.getOpcode() != ISD::ConstantFP) ||
6496 (RHSOp.getOpcode() != ISD::UNDEF &&
6497 RHSOp.getOpcode() != ISD::Constant &&
6498 RHSOp.getOpcode() != ISD::ConstantFP))
6501 // Can't fold divide by zero.
6502 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
6503 N->getOpcode() == ISD::FDIV) {
6504 if ((RHSOp.getOpcode() == ISD::Constant &&
6505 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
6506 (RHSOp.getOpcode() == ISD::ConstantFP &&
6507 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
6511 // If the vector element type is not legal, the BUILD_VECTOR operands
6512 // are promoted and implicitly truncated. Make that explicit here.
6513 if (LHSOp.getValueType() != EltType)
6514 LHSOp = DAG.getNode(ISD::TRUNCATE, LHS.getDebugLoc(), EltType, LHSOp);
6515 if (RHSOp.getValueType() != EltType)
6516 RHSOp = DAG.getNode(ISD::TRUNCATE, RHS.getDebugLoc(), EltType, RHSOp);
6518 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), EltType,
6520 if (FoldOp.getOpcode() != ISD::UNDEF &&
6521 FoldOp.getOpcode() != ISD::Constant &&
6522 FoldOp.getOpcode() != ISD::ConstantFP)
6524 Ops.push_back(FoldOp);
6525 AddToWorkList(FoldOp.getNode());
6528 if (Ops.size() == LHS.getNumOperands()) {
6529 EVT VT = LHS.getValueType();
6530 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
6531 &Ops[0], Ops.size());
6538 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
6539 SDValue N1, SDValue N2){
6540 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
6542 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
6543 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6545 // If we got a simplified select_cc node back from SimplifySelectCC, then
6546 // break it down into a new SETCC node, and a new SELECT node, and then return
6547 // the SELECT node, since we were called with a SELECT node.
6548 if (SCC.getNode()) {
6549 // Check to see if we got a select_cc back (to turn into setcc/select).
6550 // Otherwise, just return whatever node we got back, like fabs.
6551 if (SCC.getOpcode() == ISD::SELECT_CC) {
6552 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
6554 SCC.getOperand(0), SCC.getOperand(1),
6556 AddToWorkList(SETCC.getNode());
6557 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
6558 SCC.getOperand(2), SCC.getOperand(3), SETCC);
6566 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
6567 /// are the two values being selected between, see if we can simplify the
6568 /// select. Callers of this should assume that TheSelect is deleted if this
6569 /// returns true. As such, they should return the appropriate thing (e.g. the
6570 /// node) back to the top-level of the DAG combiner loop to avoid it being
6572 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
6575 // If this is a select from two identical things, try to pull the operation
6576 // through the select.
6577 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
6578 // If this is a load and the token chain is identical, replace the select
6579 // of two loads with a load through a select of the address to load from.
6580 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
6581 // constants have been dropped into the constant pool.
6582 if (LHS.getOpcode() == ISD::LOAD &&
6583 // Do not let this transformation reduce the number of volatile loads.
6584 !cast<LoadSDNode>(LHS)->isVolatile() &&
6585 !cast<LoadSDNode>(RHS)->isVolatile() &&
6586 // Token chains must be identical.
6587 LHS.getOperand(0) == RHS.getOperand(0)) {
6588 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
6589 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
6591 // If this is an EXTLOAD, the VT's must match.
6592 if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
6593 // FIXME: this discards src value information. This is
6594 // over-conservative. It would be beneficial to be able to remember
6595 // both potential memory locations. Since we are discarding
6596 // src value info, don't do the transformation if the memory
6597 // locations are not in the default address space.
6598 unsigned LLDAddrSpace = 0, RLDAddrSpace = 0;
6599 if (const Value *LLDVal = LLD->getMemOperand()->getValue()) {
6600 if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType()))
6601 LLDAddrSpace = PT->getAddressSpace();
6603 if (const Value *RLDVal = RLD->getMemOperand()->getValue()) {
6604 if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType()))
6605 RLDAddrSpace = PT->getAddressSpace();
6608 if (LLDAddrSpace == 0 && RLDAddrSpace == 0) {
6609 if (TheSelect->getOpcode() == ISD::SELECT) {
6610 // Check that the condition doesn't reach either load. If so, folding
6611 // this will induce a cycle into the DAG.
6612 if ((!LLD->hasAnyUseOfValue(1) ||
6613 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) &&
6614 (!RLD->hasAnyUseOfValue(1) ||
6615 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) {
6616 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
6617 LLD->getBasePtr().getValueType(),
6618 TheSelect->getOperand(0), LLD->getBasePtr(),
6622 // Check that the condition doesn't reach either load. If so, folding
6623 // this will induce a cycle into the DAG.
6624 if ((!LLD->hasAnyUseOfValue(1) ||
6625 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
6626 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) &&
6627 (!RLD->hasAnyUseOfValue(1) ||
6628 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
6629 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) {
6630 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
6631 LLD->getBasePtr().getValueType(),
6632 TheSelect->getOperand(0),
6633 TheSelect->getOperand(1),
6634 LLD->getBasePtr(), RLD->getBasePtr(),
6635 TheSelect->getOperand(4));
6640 if (Addr.getNode()) {
6642 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
6643 Load = DAG.getLoad(TheSelect->getValueType(0),
6644 TheSelect->getDebugLoc(),
6648 LLD->isNonTemporal(),
6649 LLD->getAlignment());
6651 Load = DAG.getExtLoad(LLD->getExtensionType(),
6652 TheSelect->getDebugLoc(),
6653 TheSelect->getValueType(0),
6654 LLD->getChain(), Addr, 0, 0,
6657 LLD->isNonTemporal(),
6658 LLD->getAlignment());
6661 // Users of the select now use the result of the load.
6662 CombineTo(TheSelect, Load);
6664 // Users of the old loads now use the new load's chain. We know the
6665 // old-load value is dead now.
6666 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
6667 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
6677 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
6678 /// where 'cond' is the comparison specified by CC.
6679 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
6680 SDValue N2, SDValue N3,
6681 ISD::CondCode CC, bool NotExtCompare) {
6682 // (x ? y : y) -> y.
6683 if (N2 == N3) return N2;
6685 EVT VT = N2.getValueType();
6686 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
6687 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
6688 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
6690 // Determine if the condition we're dealing with is constant
6691 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
6692 N0, N1, CC, DL, false);
6693 if (SCC.getNode()) AddToWorkList(SCC.getNode());
6694 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
6696 // fold select_cc true, x, y -> x
6697 if (SCCC && !SCCC->isNullValue())
6699 // fold select_cc false, x, y -> y
6700 if (SCCC && SCCC->isNullValue())
6703 // Check to see if we can simplify the select into an fabs node
6704 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
6705 // Allow either -0.0 or 0.0
6706 if (CFP->getValueAPF().isZero()) {
6707 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
6708 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
6709 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
6710 N2 == N3.getOperand(0))
6711 return DAG.getNode(ISD::FABS, DL, VT, N0);
6713 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
6714 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
6715 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
6716 N2.getOperand(0) == N3)
6717 return DAG.getNode(ISD::FABS, DL, VT, N3);
6721 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
6722 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
6723 // in it. This is a win when the constant is not otherwise available because
6724 // it replaces two constant pool loads with one. We only do this if the FP
6725 // type is known to be legal, because if it isn't, then we are before legalize
6726 // types an we want the other legalization to happen first (e.g. to avoid
6727 // messing with soft float) and if the ConstantFP is not legal, because if
6728 // it is legal, we may not need to store the FP constant in a constant pool.
6729 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
6730 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
6731 if (TLI.isTypeLegal(N2.getValueType()) &&
6732 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
6733 TargetLowering::Legal) &&
6734 // If both constants have multiple uses, then we won't need to do an
6735 // extra load, they are likely around in registers for other users.
6736 (TV->hasOneUse() || FV->hasOneUse())) {
6737 Constant *Elts[] = {
6738 const_cast<ConstantFP*>(FV->getConstantFPValue()),
6739 const_cast<ConstantFP*>(TV->getConstantFPValue())
6741 const Type *FPTy = Elts[0]->getType();
6742 const TargetData &TD = *TLI.getTargetData();
6744 // Create a ConstantArray of the two constants.
6745 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2);
6746 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
6747 TD.getPrefTypeAlignment(FPTy));
6748 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6750 // Get the offsets to the 0 and 1 element of the array so that we can
6751 // select between them.
6752 SDValue Zero = DAG.getIntPtrConstant(0);
6753 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
6754 SDValue One = DAG.getIntPtrConstant(EltSize);
6756 SDValue Cond = DAG.getSetCC(DL,
6757 TLI.getSetCCResultType(N0.getValueType()),
6759 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
6761 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
6763 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
6764 PseudoSourceValue::getConstantPool(), 0, false,
6770 // Check to see if we can perform the "gzip trick", transforming
6771 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
6772 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
6773 N0.getValueType().isInteger() &&
6774 N2.getValueType().isInteger() &&
6775 (N1C->isNullValue() || // (a < 0) ? b : 0
6776 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
6777 EVT XType = N0.getValueType();
6778 EVT AType = N2.getValueType();
6779 if (XType.bitsGE(AType)) {
6780 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
6781 // single-bit constant.
6782 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
6783 unsigned ShCtV = N2C->getAPIntValue().logBase2();
6784 ShCtV = XType.getSizeInBits()-ShCtV-1;
6785 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy());
6786 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
6788 AddToWorkList(Shift.getNode());
6790 if (XType.bitsGT(AType)) {
6791 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
6792 AddToWorkList(Shift.getNode());
6795 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
6798 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
6800 DAG.getConstant(XType.getSizeInBits()-1,
6801 getShiftAmountTy()));
6802 AddToWorkList(Shift.getNode());
6804 if (XType.bitsGT(AType)) {
6805 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
6806 AddToWorkList(Shift.getNode());
6809 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
6813 // fold select C, 16, 0 -> shl C, 4
6814 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
6815 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
6817 // If the caller doesn't want us to simplify this into a zext of a compare,
6819 if (NotExtCompare && N2C->getAPIntValue() == 1)
6822 // Get a SetCC of the condition
6823 // FIXME: Should probably make sure that setcc is legal if we ever have a
6824 // target where it isn't.
6826 // cast from setcc result type to select result type
6828 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
6830 if (N2.getValueType().bitsLT(SCC.getValueType()))
6831 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
6833 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
6834 N2.getValueType(), SCC);
6836 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
6837 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
6838 N2.getValueType(), SCC);
6841 AddToWorkList(SCC.getNode());
6842 AddToWorkList(Temp.getNode());
6844 if (N2C->getAPIntValue() == 1)
6847 // shl setcc result by log2 n2c
6848 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
6849 DAG.getConstant(N2C->getAPIntValue().logBase2(),
6850 getShiftAmountTy()));
6853 // Check to see if this is the equivalent of setcc
6854 // FIXME: Turn all of these into setcc if setcc if setcc is legal
6855 // otherwise, go ahead with the folds.
6856 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
6857 EVT XType = N0.getValueType();
6858 if (!LegalOperations ||
6859 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
6860 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
6861 if (Res.getValueType() != VT)
6862 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
6866 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
6867 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
6868 (!LegalOperations ||
6869 TLI.isOperationLegal(ISD::CTLZ, XType))) {
6870 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
6871 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
6872 DAG.getConstant(Log2_32(XType.getSizeInBits()),
6873 getShiftAmountTy()));
6875 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
6876 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
6877 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
6878 XType, DAG.getConstant(0, XType), N0);
6879 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
6880 return DAG.getNode(ISD::SRL, DL, XType,
6881 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
6882 DAG.getConstant(XType.getSizeInBits()-1,
6883 getShiftAmountTy()));
6885 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
6886 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
6887 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
6888 DAG.getConstant(XType.getSizeInBits()-1,
6889 getShiftAmountTy()));
6890 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
6894 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
6895 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
6896 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
6897 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
6898 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
6899 EVT XType = N0.getValueType();
6900 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0,
6901 DAG.getConstant(XType.getSizeInBits()-1,
6902 getShiftAmountTy()));
6903 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType,
6905 AddToWorkList(Shift.getNode());
6906 AddToWorkList(Add.getNode());
6907 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
6909 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
6910 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
6911 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
6912 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
6913 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
6914 EVT XType = N0.getValueType();
6915 if (SubC->isNullValue() && XType.isInteger()) {
6916 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
6918 DAG.getConstant(XType.getSizeInBits()-1,
6919 getShiftAmountTy()));
6920 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
6922 AddToWorkList(Shift.getNode());
6923 AddToWorkList(Add.getNode());
6924 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
6932 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
6933 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
6934 SDValue N1, ISD::CondCode Cond,
6935 DebugLoc DL, bool foldBooleans) {
6936 TargetLowering::DAGCombinerInfo
6937 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
6938 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
6941 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
6942 /// return a DAG expression to select that will generate the same value by
6943 /// multiplying by a magic number. See:
6944 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6945 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
6946 std::vector<SDNode*> Built;
6947 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
6949 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6955 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
6956 /// return a DAG expression to select that will generate the same value by
6957 /// multiplying by a magic number. See:
6958 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6959 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
6960 std::vector<SDNode*> Built;
6961 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
6963 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6969 /// FindBaseOffset - Return true if base is a frame index, which is known not
6970 // to alias with anything but itself. Provides base object and offset as results.
6971 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
6972 const GlobalValue *&GV, void *&CV) {
6973 // Assume it is a primitive operation.
6974 Base = Ptr; Offset = 0; GV = 0; CV = 0;
6976 // If it's an adding a simple constant then integrate the offset.
6977 if (Base.getOpcode() == ISD::ADD) {
6978 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
6979 Base = Base.getOperand(0);
6980 Offset += C->getZExtValue();
6984 // Return the underlying GlobalValue, and update the Offset. Return false
6985 // for GlobalAddressSDNode since the same GlobalAddress may be represented
6986 // by multiple nodes with different offsets.
6987 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
6988 GV = G->getGlobal();
6989 Offset += G->getOffset();
6993 // Return the underlying Constant value, and update the Offset. Return false
6994 // for ConstantSDNodes since the same constant pool entry may be represented
6995 // by multiple nodes with different offsets.
6996 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
6997 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
6998 : (void *)C->getConstVal();
6999 Offset += C->getOffset();
7002 // If it's any of the following then it can't alias with anything but itself.
7003 return isa<FrameIndexSDNode>(Base);
7006 /// isAlias - Return true if there is any possibility that the two addresses
7008 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
7009 const Value *SrcValue1, int SrcValueOffset1,
7010 unsigned SrcValueAlign1,
7011 SDValue Ptr2, int64_t Size2,
7012 const Value *SrcValue2, int SrcValueOffset2,
7013 unsigned SrcValueAlign2) const {
7014 // If they are the same then they must be aliases.
7015 if (Ptr1 == Ptr2) return true;
7017 // Gather base node and offset information.
7018 SDValue Base1, Base2;
7019 int64_t Offset1, Offset2;
7020 const GlobalValue *GV1, *GV2;
7022 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
7023 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
7025 // If they have a same base address then check to see if they overlap.
7026 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
7027 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7029 // If we know what the bases are, and they aren't identical, then we know they
7031 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
7034 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
7035 // compared to the size and offset of the access, we may be able to prove they
7036 // do not alias. This check is conservative for now to catch cases created by
7037 // splitting vector types.
7038 if ((SrcValueAlign1 == SrcValueAlign2) &&
7039 (SrcValueOffset1 != SrcValueOffset2) &&
7040 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
7041 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
7042 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
7044 // There is no overlap between these relatively aligned accesses of similar
7045 // size, return no alias.
7046 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
7050 if (CombinerGlobalAA) {
7051 // Use alias analysis information.
7052 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
7053 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
7054 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
7055 AliasAnalysis::AliasResult AAResult =
7056 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
7057 if (AAResult == AliasAnalysis::NoAlias)
7061 // Otherwise we have to assume they alias.
7065 /// FindAliasInfo - Extracts the relevant alias information from the memory
7066 /// node. Returns true if the operand was a load.
7067 bool DAGCombiner::FindAliasInfo(SDNode *N,
7068 SDValue &Ptr, int64_t &Size,
7069 const Value *&SrcValue,
7070 int &SrcValueOffset,
7071 unsigned &SrcValueAlign) const {
7072 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7073 Ptr = LD->getBasePtr();
7074 Size = LD->getMemoryVT().getSizeInBits() >> 3;
7075 SrcValue = LD->getSrcValue();
7076 SrcValueOffset = LD->getSrcValueOffset();
7077 SrcValueAlign = LD->getOriginalAlignment();
7079 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7080 Ptr = ST->getBasePtr();
7081 Size = ST->getMemoryVT().getSizeInBits() >> 3;
7082 SrcValue = ST->getSrcValue();
7083 SrcValueOffset = ST->getSrcValueOffset();
7084 SrcValueAlign = ST->getOriginalAlignment();
7086 llvm_unreachable("FindAliasInfo expected a memory operand");
7092 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
7093 /// looking for aliasing nodes and adding them to the Aliases vector.
7094 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
7095 SmallVector<SDValue, 8> &Aliases) {
7096 SmallVector<SDValue, 8> Chains; // List of chains to visit.
7097 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
7099 // Get alias information for node.
7102 const Value *SrcValue;
7104 unsigned SrcValueAlign;
7105 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
7109 Chains.push_back(OriginalChain);
7112 // Look at each chain and determine if it is an alias. If so, add it to the
7113 // aliases list. If not, then continue up the chain looking for the next
7115 while (!Chains.empty()) {
7116 SDValue Chain = Chains.back();
7119 // For TokenFactor nodes, look at each operand and only continue up the
7120 // chain until we find two aliases. If we've seen two aliases, assume we'll
7121 // find more and revert to original chain since the xform is unlikely to be
7124 // FIXME: The depth check could be made to return the last non-aliasing
7125 // chain we found before we hit a tokenfactor rather than the original
7127 if (Depth > 6 || Aliases.size() == 2) {
7129 Aliases.push_back(OriginalChain);
7133 // Don't bother if we've been before.
7134 if (!Visited.insert(Chain.getNode()))
7137 switch (Chain.getOpcode()) {
7138 case ISD::EntryToken:
7139 // Entry token is ideal chain operand, but handled in FindBetterChain.
7144 // Get alias information for Chain.
7147 const Value *OpSrcValue;
7148 int OpSrcValueOffset;
7149 unsigned OpSrcValueAlign;
7150 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
7151 OpSrcValue, OpSrcValueOffset,
7154 // If chain is alias then stop here.
7155 if (!(IsLoad && IsOpLoad) &&
7156 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
7157 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
7159 Aliases.push_back(Chain);
7161 // Look further up the chain.
7162 Chains.push_back(Chain.getOperand(0));
7168 case ISD::TokenFactor:
7169 // We have to check each of the operands of the token factor for "small"
7170 // token factors, so we queue them up. Adding the operands to the queue
7171 // (stack) in reverse order maintains the original order and increases the
7172 // likelihood that getNode will find a matching token factor (CSE.)
7173 if (Chain.getNumOperands() > 16) {
7174 Aliases.push_back(Chain);
7177 for (unsigned n = Chain.getNumOperands(); n;)
7178 Chains.push_back(Chain.getOperand(--n));
7183 // For all other instructions we will just have to take what we can get.
7184 Aliases.push_back(Chain);
7190 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
7191 /// for a better chain (aliasing node.)
7192 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
7193 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
7195 // Accumulate all the aliases to this node.
7196 GatherAllAliases(N, OldChain, Aliases);
7198 if (Aliases.size() == 0) {
7199 // If no operands then chain to entry token.
7200 return DAG.getEntryNode();
7201 } else if (Aliases.size() == 1) {
7202 // If a single operand then chain to it. We don't need to revisit it.
7206 // Construct a custom tailored token factor.
7207 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
7208 &Aliases[0], Aliases.size());
7211 // SelectionDAG::Combine - This is the entry point for the file.
7213 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
7214 CodeGenOpt::Level OptLevel) {
7215 /// run - This is the main entry point to this class.
7217 DAGCombiner(*this, AA, OptLevel).Run(Level);