1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/CommandLine.h"
47 static Statistic<> NodesCombined ("dagcombiner",
48 "Number of dag nodes combined");
51 CombinerAA("combiner-alias-analysis", cl::Hidden,
52 cl::desc("Turn on alias analysis during testing"));
55 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
56 cl::desc("Include global information in alias analysis"));
58 //------------------------------ DAGCombiner ---------------------------------//
60 class VISIBILITY_HIDDEN DAGCombiner {
65 // Worklist of all of the nodes that need to be simplified.
66 std::vector<SDNode*> WorkList;
68 // AA - Used for DAG load/store alias analysis.
71 /// AddUsersToWorkList - When an instruction is simplified, add all users of
72 /// the instruction to the work lists because they might get more simplified
75 void AddUsersToWorkList(SDNode *N) {
76 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
81 /// removeFromWorkList - remove all instances of N from the worklist.
83 void removeFromWorkList(SDNode *N) {
84 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
89 /// AddToWorkList - Add to the work list making sure it's instance is at the
90 /// the back (next to be processed.)
91 void AddToWorkList(SDNode *N) {
92 removeFromWorkList(N);
93 WorkList.push_back(N);
96 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
98 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
100 DEBUG(std::cerr << "\nReplacing.1 "; N->dump();
101 std::cerr << "\nWith: "; To[0].Val->dump(&DAG);
102 std::cerr << " and " << NumTo-1 << " other values\n");
103 std::vector<SDNode*> NowDead;
104 DAG.ReplaceAllUsesWith(N, To, &NowDead);
107 // Push the new nodes and any users onto the worklist
108 for (unsigned i = 0, e = NumTo; i != e; ++i) {
109 AddToWorkList(To[i].Val);
110 AddUsersToWorkList(To[i].Val);
114 // Nodes can be reintroduced into the worklist. Make sure we do not
115 // process a node that has been replaced.
116 removeFromWorkList(N);
117 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
118 removeFromWorkList(NowDead[i]);
120 // Finally, since the node is now dead, remove it from the graph.
122 return SDOperand(N, 0);
125 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
126 return CombineTo(N, &Res, 1, AddTo);
129 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
131 SDOperand To[] = { Res0, Res1 };
132 return CombineTo(N, To, 2, AddTo);
136 /// SimplifyDemandedBits - Check the specified integer node value to see if
137 /// it can be simplified or if things it uses can be simplified by bit
138 /// propagation. If so, return true.
139 bool SimplifyDemandedBits(SDOperand Op) {
140 TargetLowering::TargetLoweringOpt TLO(DAG);
141 uint64_t KnownZero, KnownOne;
142 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
143 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
147 AddToWorkList(Op.Val);
149 // Replace the old value with the new one.
151 DEBUG(std::cerr << "\nReplacing.2 "; TLO.Old.Val->dump();
152 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG);
155 std::vector<SDNode*> NowDead;
156 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
158 // Push the new node and any (possibly new) users onto the worklist.
159 AddToWorkList(TLO.New.Val);
160 AddUsersToWorkList(TLO.New.Val);
162 // Nodes can end up on the worklist more than once. Make sure we do
163 // not process a node that has been replaced.
164 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
165 removeFromWorkList(NowDead[i]);
167 // Finally, if the node is now dead, remove it from the graph. The node
168 // may not be dead if the replacement process recursively simplified to
169 // something else needing this node.
170 if (TLO.Old.Val->use_empty()) {
171 removeFromWorkList(TLO.Old.Val);
172 DAG.DeleteNode(TLO.Old.Val);
177 bool CombineToIndexedLoadStore(SDNode *N) {
180 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
181 Ptr = LD->getBasePtr();
182 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
183 Ptr = ST->getBasePtr();
189 (Ptr.getOpcode() == ISD::ADD || Ptr.getOpcode() == ISD::SUB) &&
190 Ptr.Val->use_size() > 1) {
193 ISD::MemOpAddrMode AM = ISD::UNINDEXED;
194 if (TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) {
195 // Try turning it into a pre-indexed load / store except when
196 // 1) Another use of base ptr is a predecessor of N. If ptr is folded
197 // that would create a cycle.
198 // 2) All uses are load / store ops that use it as base ptr and offset
199 // is just an addressing mode immediate.
200 // 3) If the would-be new base may not to be dead at N. FIXME: The
201 // proper check is too expensive (in turns of compile time) to
202 // check. Just make sure other uses of the new base are not also
203 // themselves use of loads / stores.
205 bool OffIsAMImm = Offset.getOpcode() == ISD::Constant &&
206 TLI.isLegalAddressImmediate(
207 cast<ConstantSDNode>(Offset)->getValue());
210 if (OffIsAMImm && BasePtr.Val->use_size() > 1) {
211 for (SDNode::use_iterator I = BasePtr.Val->use_begin(),
212 E = BasePtr.Val->use_end(); I != E; ++I) {
216 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
217 for (SDNode::use_iterator II = Use->use_begin(),
218 EE = Use->use_end(); II != EE; ++II) {
219 SDNode *UseUse = *II;
220 if (UseUse->getOpcode() == ISD::LOAD &&
221 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use)
223 else if (UseUse->getOpcode() == ISD::STORE &&
224 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)
231 // Now check for #1 and #2.
232 unsigned NumRealUses = 0;
233 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
234 E = Ptr.Val->use_end(); I != E; ++I) {
238 if (Use->isPredecessor(N))
243 } else if (Use->getOpcode() == ISD::LOAD) {
244 if (cast<LoadSDNode>(Use)->getBasePtr().Val != Ptr.Val)
246 } else if (Use->getOpcode() == ISD::STORE) {
247 if (cast<StoreSDNode>(Use)->getBasePtr().Val != Ptr.Val)
252 if (NumRealUses == 0)
255 SDOperand Result = isLoad
256 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
257 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
259 DEBUG(std::cerr << "\nReplacing.4 "; N->dump();
260 std::cerr << "\nWith: "; Result.Val->dump(&DAG);
262 std::vector<SDNode*> NowDead;
264 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
266 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
269 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
273 // Nodes can end up on the worklist more than once. Make sure we do
274 // not process a node that has been replaced.
275 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
276 removeFromWorkList(NowDead[i]);
277 // Finally, since the node is now dead, remove it from the graph.
280 // Replace the uses of Ptr with uses of the updated base value.
281 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
283 removeFromWorkList(Ptr.Val);
284 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
285 removeFromWorkList(NowDead[i]);
286 DAG.DeleteNode(Ptr.Val);
295 /// visit - call the node-specific routine that knows how to fold each
296 /// particular type of node.
297 SDOperand visit(SDNode *N);
299 // Visitation implementation - Implement dag node combining for different
300 // node types. The semantics are as follows:
302 // SDOperand.Val == 0 - No change was made
303 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
304 // otherwise - N should be replaced by the returned Operand.
306 SDOperand visitTokenFactor(SDNode *N);
307 SDOperand visitADD(SDNode *N);
308 SDOperand visitSUB(SDNode *N);
309 SDOperand visitMUL(SDNode *N);
310 SDOperand visitSDIV(SDNode *N);
311 SDOperand visitUDIV(SDNode *N);
312 SDOperand visitSREM(SDNode *N);
313 SDOperand visitUREM(SDNode *N);
314 SDOperand visitMULHU(SDNode *N);
315 SDOperand visitMULHS(SDNode *N);
316 SDOperand visitAND(SDNode *N);
317 SDOperand visitOR(SDNode *N);
318 SDOperand visitXOR(SDNode *N);
319 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
320 SDOperand visitSHL(SDNode *N);
321 SDOperand visitSRA(SDNode *N);
322 SDOperand visitSRL(SDNode *N);
323 SDOperand visitCTLZ(SDNode *N);
324 SDOperand visitCTTZ(SDNode *N);
325 SDOperand visitCTPOP(SDNode *N);
326 SDOperand visitSELECT(SDNode *N);
327 SDOperand visitSELECT_CC(SDNode *N);
328 SDOperand visitSETCC(SDNode *N);
329 SDOperand visitSIGN_EXTEND(SDNode *N);
330 SDOperand visitZERO_EXTEND(SDNode *N);
331 SDOperand visitANY_EXTEND(SDNode *N);
332 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
333 SDOperand visitTRUNCATE(SDNode *N);
334 SDOperand visitBIT_CONVERT(SDNode *N);
335 SDOperand visitVBIT_CONVERT(SDNode *N);
336 SDOperand visitFADD(SDNode *N);
337 SDOperand visitFSUB(SDNode *N);
338 SDOperand visitFMUL(SDNode *N);
339 SDOperand visitFDIV(SDNode *N);
340 SDOperand visitFREM(SDNode *N);
341 SDOperand visitFCOPYSIGN(SDNode *N);
342 SDOperand visitSINT_TO_FP(SDNode *N);
343 SDOperand visitUINT_TO_FP(SDNode *N);
344 SDOperand visitFP_TO_SINT(SDNode *N);
345 SDOperand visitFP_TO_UINT(SDNode *N);
346 SDOperand visitFP_ROUND(SDNode *N);
347 SDOperand visitFP_ROUND_INREG(SDNode *N);
348 SDOperand visitFP_EXTEND(SDNode *N);
349 SDOperand visitFNEG(SDNode *N);
350 SDOperand visitFABS(SDNode *N);
351 SDOperand visitBRCOND(SDNode *N);
352 SDOperand visitBR_CC(SDNode *N);
353 SDOperand visitLOAD(SDNode *N);
354 SDOperand visitSTORE(SDNode *N);
355 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
356 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
357 SDOperand visitVBUILD_VECTOR(SDNode *N);
358 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
359 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
361 SDOperand XformToShuffleWithZero(SDNode *N);
362 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
364 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
365 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
366 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
367 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
368 SDOperand N3, ISD::CondCode CC);
369 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
370 ISD::CondCode Cond, bool foldBooleans = true);
371 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
372 SDOperand BuildSDIV(SDNode *N);
373 SDOperand BuildUDIV(SDNode *N);
374 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
376 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
377 /// looking for aliasing nodes and adding them to the Aliases vector.
378 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
379 SmallVector<SDOperand, 8> &Aliases);
381 /// isAlias - Return true if there is any possibility that the two addresses
383 bool isAlias(SDOperand Ptr1, int64_t Size1,
384 const Value *SrcValue1, int SrcValueOffset1,
385 SDOperand Ptr2, int64_t Size2,
386 const Value *SrcValue2, int SrcValueOffset1);
388 /// FindAliasInfo - Extracts the relevant alias information from the memory
389 /// node. Returns true if the operand was a load.
390 bool FindAliasInfo(SDNode *N,
391 SDOperand &Ptr, int64_t &Size,
392 const Value *&SrcValue, int &SrcValueOffset);
394 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
395 /// looking for a better chain (aliasing node.)
396 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
399 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
401 TLI(D.getTargetLoweringInfo()),
402 AfterLegalize(false),
405 /// Run - runs the dag combiner on all nodes in the work list
406 void Run(bool RunningAfterLegalize);
410 //===----------------------------------------------------------------------===//
411 // TargetLowering::DAGCombinerInfo implementation
412 //===----------------------------------------------------------------------===//
414 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
415 ((DAGCombiner*)DC)->AddToWorkList(N);
418 SDOperand TargetLowering::DAGCombinerInfo::
419 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
420 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
423 SDOperand TargetLowering::DAGCombinerInfo::
424 CombineTo(SDNode *N, SDOperand Res) {
425 return ((DAGCombiner*)DC)->CombineTo(N, Res);
429 SDOperand TargetLowering::DAGCombinerInfo::
430 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
431 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
437 //===----------------------------------------------------------------------===//
440 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
441 // that selects between the values 1 and 0, making it equivalent to a setcc.
442 // Also, set the incoming LHS, RHS, and CC references to the appropriate
443 // nodes based on the type of node we are checking. This simplifies life a
444 // bit for the callers.
445 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
447 if (N.getOpcode() == ISD::SETCC) {
448 LHS = N.getOperand(0);
449 RHS = N.getOperand(1);
450 CC = N.getOperand(2);
453 if (N.getOpcode() == ISD::SELECT_CC &&
454 N.getOperand(2).getOpcode() == ISD::Constant &&
455 N.getOperand(3).getOpcode() == ISD::Constant &&
456 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
457 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
458 LHS = N.getOperand(0);
459 RHS = N.getOperand(1);
460 CC = N.getOperand(4);
466 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
467 // one use. If this is true, it allows the users to invert the operation for
468 // free when it is profitable to do so.
469 static bool isOneUseSetCC(SDOperand N) {
470 SDOperand N0, N1, N2;
471 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
476 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
477 MVT::ValueType VT = N0.getValueType();
478 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
479 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
480 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
481 if (isa<ConstantSDNode>(N1)) {
482 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
483 AddToWorkList(OpNode.Val);
484 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
485 } else if (N0.hasOneUse()) {
486 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
487 AddToWorkList(OpNode.Val);
488 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
491 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
492 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
493 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
494 if (isa<ConstantSDNode>(N0)) {
495 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
496 AddToWorkList(OpNode.Val);
497 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
498 } else if (N1.hasOneUse()) {
499 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
500 AddToWorkList(OpNode.Val);
501 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
507 void DAGCombiner::Run(bool RunningAfterLegalize) {
508 // set the instance variable, so that the various visit routines may use it.
509 AfterLegalize = RunningAfterLegalize;
511 // Add all the dag nodes to the worklist.
512 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
513 E = DAG.allnodes_end(); I != E; ++I)
514 WorkList.push_back(I);
516 // Create a dummy node (which is not added to allnodes), that adds a reference
517 // to the root node, preventing it from being deleted, and tracking any
518 // changes of the root.
519 HandleSDNode Dummy(DAG.getRoot());
521 // The root of the dag may dangle to deleted nodes until the dag combiner is
522 // done. Set it to null to avoid confusion.
523 DAG.setRoot(SDOperand());
525 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
526 TargetLowering::DAGCombinerInfo
527 DagCombineInfo(DAG, !RunningAfterLegalize, this);
529 // while the worklist isn't empty, inspect the node on the end of it and
530 // try and combine it.
531 while (!WorkList.empty()) {
532 SDNode *N = WorkList.back();
535 // If N has no uses, it is dead. Make sure to revisit all N's operands once
536 // N is deleted from the DAG, since they too may now be dead or may have a
537 // reduced number of uses, allowing other xforms.
538 if (N->use_empty() && N != &Dummy) {
539 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
540 AddToWorkList(N->getOperand(i).Val);
546 SDOperand RV = visit(N);
548 // If nothing happened, try a target-specific DAG combine.
550 assert(N->getOpcode() != ISD::DELETED_NODE &&
551 "Node was deleted but visit returned NULL!");
552 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
553 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
554 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
559 // If we get back the same node we passed in, rather than a new node or
560 // zero, we know that the node must have defined multiple values and
561 // CombineTo was used. Since CombineTo takes care of the worklist
562 // mechanics for us, we have no work to do in this case.
564 assert(N->getOpcode() != ISD::DELETED_NODE &&
565 RV.Val->getOpcode() != ISD::DELETED_NODE &&
566 "Node was deleted but visit returned new node!");
568 DEBUG(std::cerr << "\nReplacing.3 "; N->dump();
569 std::cerr << "\nWith: "; RV.Val->dump(&DAG);
571 std::vector<SDNode*> NowDead;
572 if (N->getNumValues() == RV.Val->getNumValues())
573 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
575 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
577 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
580 // Push the new node and any users onto the worklist
581 AddToWorkList(RV.Val);
582 AddUsersToWorkList(RV.Val);
584 // Nodes can be reintroduced into the worklist. Make sure we do not
585 // process a node that has been replaced.
586 removeFromWorkList(N);
587 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
588 removeFromWorkList(NowDead[i]);
590 // Finally, since the node is now dead, remove it from the graph.
596 // If the root changed (e.g. it was a dead load, update the root).
597 DAG.setRoot(Dummy.getValue());
600 SDOperand DAGCombiner::visit(SDNode *N) {
601 switch(N->getOpcode()) {
603 case ISD::TokenFactor: return visitTokenFactor(N);
604 case ISD::ADD: return visitADD(N);
605 case ISD::SUB: return visitSUB(N);
606 case ISD::MUL: return visitMUL(N);
607 case ISD::SDIV: return visitSDIV(N);
608 case ISD::UDIV: return visitUDIV(N);
609 case ISD::SREM: return visitSREM(N);
610 case ISD::UREM: return visitUREM(N);
611 case ISD::MULHU: return visitMULHU(N);
612 case ISD::MULHS: return visitMULHS(N);
613 case ISD::AND: return visitAND(N);
614 case ISD::OR: return visitOR(N);
615 case ISD::XOR: return visitXOR(N);
616 case ISD::SHL: return visitSHL(N);
617 case ISD::SRA: return visitSRA(N);
618 case ISD::SRL: return visitSRL(N);
619 case ISD::CTLZ: return visitCTLZ(N);
620 case ISD::CTTZ: return visitCTTZ(N);
621 case ISD::CTPOP: return visitCTPOP(N);
622 case ISD::SELECT: return visitSELECT(N);
623 case ISD::SELECT_CC: return visitSELECT_CC(N);
624 case ISD::SETCC: return visitSETCC(N);
625 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
626 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
627 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
628 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
629 case ISD::TRUNCATE: return visitTRUNCATE(N);
630 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
631 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
632 case ISD::FADD: return visitFADD(N);
633 case ISD::FSUB: return visitFSUB(N);
634 case ISD::FMUL: return visitFMUL(N);
635 case ISD::FDIV: return visitFDIV(N);
636 case ISD::FREM: return visitFREM(N);
637 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
638 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
639 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
640 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
641 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
642 case ISD::FP_ROUND: return visitFP_ROUND(N);
643 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
644 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
645 case ISD::FNEG: return visitFNEG(N);
646 case ISD::FABS: return visitFABS(N);
647 case ISD::BRCOND: return visitBRCOND(N);
648 case ISD::BR_CC: return visitBR_CC(N);
649 case ISD::LOAD: return visitLOAD(N);
650 case ISD::STORE: return visitSTORE(N);
651 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
652 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
653 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
654 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
655 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
656 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
657 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
658 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
659 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
660 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
661 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
662 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
663 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
668 /// getInputChainForNode - Given a node, return its input chain if it has one,
669 /// otherwise return a null sd operand.
670 static SDOperand getInputChainForNode(SDNode *N) {
671 if (unsigned NumOps = N->getNumOperands()) {
672 if (N->getOperand(0).getValueType() == MVT::Other)
673 return N->getOperand(0);
674 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
675 return N->getOperand(NumOps-1);
676 for (unsigned i = 1; i < NumOps-1; ++i)
677 if (N->getOperand(i).getValueType() == MVT::Other)
678 return N->getOperand(i);
680 return SDOperand(0, 0);
683 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
684 // If N has two operands, where one has an input chain equal to the other,
685 // the 'other' chain is redundant.
686 if (N->getNumOperands() == 2) {
687 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
688 return N->getOperand(0);
689 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
690 return N->getOperand(1);
694 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
695 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
696 bool Changed = false; // If we should replace this token factor.
698 // Start out with this token factor.
701 // Iterate through token factors. The TFs grows when new token factors are
703 for (unsigned i = 0; i < TFs.size(); ++i) {
706 // Check each of the operands.
707 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
708 SDOperand Op = TF->getOperand(i);
710 switch (Op.getOpcode()) {
711 case ISD::EntryToken:
712 // Entry tokens don't need to be added to the list. They are
717 case ISD::TokenFactor:
718 if ((CombinerAA || Op.hasOneUse()) &&
719 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
720 // Queue up for processing.
721 TFs.push_back(Op.Val);
722 // Clean up in case the token factor is removed.
723 AddToWorkList(Op.Val);
730 // Only add if not there prior.
731 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end())
740 // If we've change things around then replace token factor.
742 if (Ops.size() == 0) {
743 // The entry token is the only possible outcome.
744 Result = DAG.getEntryNode();
746 // New and improved token factor.
747 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
750 // Don't add users to work list.
751 return CombineTo(N, Result, false);
757 SDOperand DAGCombiner::visitADD(SDNode *N) {
758 SDOperand N0 = N->getOperand(0);
759 SDOperand N1 = N->getOperand(1);
760 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
761 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
762 MVT::ValueType VT = N0.getValueType();
764 // fold (add c1, c2) -> c1+c2
766 return DAG.getNode(ISD::ADD, VT, N0, N1);
767 // canonicalize constant to RHS
769 return DAG.getNode(ISD::ADD, VT, N1, N0);
770 // fold (add x, 0) -> x
771 if (N1C && N1C->isNullValue())
773 // fold ((c1-A)+c2) -> (c1+c2)-A
774 if (N1C && N0.getOpcode() == ISD::SUB)
775 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
776 return DAG.getNode(ISD::SUB, VT,
777 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
780 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
783 // fold ((0-A) + B) -> B-A
784 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
785 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
786 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
787 // fold (A + (0-B)) -> A-B
788 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
789 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
790 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
791 // fold (A+(B-A)) -> B
792 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
793 return N1.getOperand(0);
795 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
796 return SDOperand(N, 0);
798 // fold (a+b) -> (a|b) iff a and b share no bits.
799 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
800 uint64_t LHSZero, LHSOne;
801 uint64_t RHSZero, RHSOne;
802 uint64_t Mask = MVT::getIntVTBitMask(VT);
803 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
805 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
807 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
808 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
809 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
810 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
811 return DAG.getNode(ISD::OR, VT, N0, N1);
818 SDOperand DAGCombiner::visitSUB(SDNode *N) {
819 SDOperand N0 = N->getOperand(0);
820 SDOperand N1 = N->getOperand(1);
821 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
822 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
823 MVT::ValueType VT = N0.getValueType();
825 // fold (sub x, x) -> 0
827 return DAG.getConstant(0, N->getValueType(0));
828 // fold (sub c1, c2) -> c1-c2
830 return DAG.getNode(ISD::SUB, VT, N0, N1);
831 // fold (sub x, c) -> (add x, -c)
833 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
835 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
836 return N0.getOperand(1);
838 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
839 return N0.getOperand(0);
843 SDOperand DAGCombiner::visitMUL(SDNode *N) {
844 SDOperand N0 = N->getOperand(0);
845 SDOperand N1 = N->getOperand(1);
846 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
847 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
848 MVT::ValueType VT = N0.getValueType();
850 // fold (mul c1, c2) -> c1*c2
852 return DAG.getNode(ISD::MUL, VT, N0, N1);
853 // canonicalize constant to RHS
855 return DAG.getNode(ISD::MUL, VT, N1, N0);
856 // fold (mul x, 0) -> 0
857 if (N1C && N1C->isNullValue())
859 // fold (mul x, -1) -> 0-x
860 if (N1C && N1C->isAllOnesValue())
861 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
862 // fold (mul x, (1 << c)) -> x << c
863 if (N1C && isPowerOf2_64(N1C->getValue()))
864 return DAG.getNode(ISD::SHL, VT, N0,
865 DAG.getConstant(Log2_64(N1C->getValue()),
866 TLI.getShiftAmountTy()));
867 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
868 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
869 // FIXME: If the input is something that is easily negated (e.g. a
870 // single-use add), we should put the negate there.
871 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
872 DAG.getNode(ISD::SHL, VT, N0,
873 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
874 TLI.getShiftAmountTy())));
877 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
878 if (N1C && N0.getOpcode() == ISD::SHL &&
879 isa<ConstantSDNode>(N0.getOperand(1))) {
880 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
881 AddToWorkList(C3.Val);
882 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
885 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
888 SDOperand Sh(0,0), Y(0,0);
889 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
890 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
891 N0.Val->hasOneUse()) {
893 } else if (N1.getOpcode() == ISD::SHL &&
894 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
898 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
899 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
902 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
903 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
904 isa<ConstantSDNode>(N0.getOperand(1))) {
905 return DAG.getNode(ISD::ADD, VT,
906 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
907 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
911 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
917 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
918 SDOperand N0 = N->getOperand(0);
919 SDOperand N1 = N->getOperand(1);
920 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
921 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
922 MVT::ValueType VT = N->getValueType(0);
924 // fold (sdiv c1, c2) -> c1/c2
925 if (N0C && N1C && !N1C->isNullValue())
926 return DAG.getNode(ISD::SDIV, VT, N0, N1);
927 // fold (sdiv X, 1) -> X
928 if (N1C && N1C->getSignExtended() == 1LL)
930 // fold (sdiv X, -1) -> 0-X
931 if (N1C && N1C->isAllOnesValue())
932 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
933 // If we know the sign bits of both operands are zero, strength reduce to a
934 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
935 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
936 if (TLI.MaskedValueIsZero(N1, SignBit) &&
937 TLI.MaskedValueIsZero(N0, SignBit))
938 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
939 // fold (sdiv X, pow2) -> simple ops after legalize
940 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
941 (isPowerOf2_64(N1C->getSignExtended()) ||
942 isPowerOf2_64(-N1C->getSignExtended()))) {
943 // If dividing by powers of two is cheap, then don't perform the following
945 if (TLI.isPow2DivCheap())
947 int64_t pow2 = N1C->getSignExtended();
948 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
949 unsigned lg2 = Log2_64(abs2);
950 // Splat the sign bit into the register
951 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
952 DAG.getConstant(MVT::getSizeInBits(VT)-1,
953 TLI.getShiftAmountTy()));
954 AddToWorkList(SGN.Val);
955 // Add (N0 < 0) ? abs2 - 1 : 0;
956 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
957 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
958 TLI.getShiftAmountTy()));
959 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
960 AddToWorkList(SRL.Val);
961 AddToWorkList(ADD.Val); // Divide by pow2
962 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
963 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
964 // If we're dividing by a positive value, we're done. Otherwise, we must
965 // negate the result.
968 AddToWorkList(SRA.Val);
969 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
971 // if integer divide is expensive and we satisfy the requirements, emit an
972 // alternate sequence.
973 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
974 !TLI.isIntDivCheap()) {
975 SDOperand Op = BuildSDIV(N);
976 if (Op.Val) return Op;
981 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
982 SDOperand N0 = N->getOperand(0);
983 SDOperand N1 = N->getOperand(1);
984 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
985 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
986 MVT::ValueType VT = N->getValueType(0);
988 // fold (udiv c1, c2) -> c1/c2
989 if (N0C && N1C && !N1C->isNullValue())
990 return DAG.getNode(ISD::UDIV, VT, N0, N1);
991 // fold (udiv x, (1 << c)) -> x >>u c
992 if (N1C && isPowerOf2_64(N1C->getValue()))
993 return DAG.getNode(ISD::SRL, VT, N0,
994 DAG.getConstant(Log2_64(N1C->getValue()),
995 TLI.getShiftAmountTy()));
996 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
997 if (N1.getOpcode() == ISD::SHL) {
998 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
999 if (isPowerOf2_64(SHC->getValue())) {
1000 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
1001 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
1002 DAG.getConstant(Log2_64(SHC->getValue()),
1004 AddToWorkList(Add.Val);
1005 return DAG.getNode(ISD::SRL, VT, N0, Add);
1009 // fold (udiv x, c) -> alternate
1010 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1011 SDOperand Op = BuildUDIV(N);
1012 if (Op.Val) return Op;
1017 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1018 SDOperand N0 = N->getOperand(0);
1019 SDOperand N1 = N->getOperand(1);
1020 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1021 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1022 MVT::ValueType VT = N->getValueType(0);
1024 // fold (srem c1, c2) -> c1%c2
1025 if (N0C && N1C && !N1C->isNullValue())
1026 return DAG.getNode(ISD::SREM, VT, N0, N1);
1027 // If we know the sign bits of both operands are zero, strength reduce to a
1028 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1029 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1030 if (TLI.MaskedValueIsZero(N1, SignBit) &&
1031 TLI.MaskedValueIsZero(N0, SignBit))
1032 return DAG.getNode(ISD::UREM, VT, N0, N1);
1034 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1035 // the remainder operation.
1036 if (N1C && !N1C->isNullValue()) {
1037 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1038 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1039 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1040 AddToWorkList(Div.Val);
1041 AddToWorkList(Mul.Val);
1048 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1049 SDOperand N0 = N->getOperand(0);
1050 SDOperand N1 = N->getOperand(1);
1051 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1052 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1053 MVT::ValueType VT = N->getValueType(0);
1055 // fold (urem c1, c2) -> c1%c2
1056 if (N0C && N1C && !N1C->isNullValue())
1057 return DAG.getNode(ISD::UREM, VT, N0, N1);
1058 // fold (urem x, pow2) -> (and x, pow2-1)
1059 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1060 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1061 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1062 if (N1.getOpcode() == ISD::SHL) {
1063 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1064 if (isPowerOf2_64(SHC->getValue())) {
1065 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1066 AddToWorkList(Add.Val);
1067 return DAG.getNode(ISD::AND, VT, N0, Add);
1072 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1073 // the remainder operation.
1074 if (N1C && !N1C->isNullValue()) {
1075 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1076 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1077 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1078 AddToWorkList(Div.Val);
1079 AddToWorkList(Mul.Val);
1086 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1087 SDOperand N0 = N->getOperand(0);
1088 SDOperand N1 = N->getOperand(1);
1089 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1091 // fold (mulhs x, 0) -> 0
1092 if (N1C && N1C->isNullValue())
1094 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1095 if (N1C && N1C->getValue() == 1)
1096 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1097 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1098 TLI.getShiftAmountTy()));
1102 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1103 SDOperand N0 = N->getOperand(0);
1104 SDOperand N1 = N->getOperand(1);
1105 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1107 // fold (mulhu x, 0) -> 0
1108 if (N1C && N1C->isNullValue())
1110 // fold (mulhu x, 1) -> 0
1111 if (N1C && N1C->getValue() == 1)
1112 return DAG.getConstant(0, N0.getValueType());
1116 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1117 /// two operands of the same opcode, try to simplify it.
1118 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1119 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1120 MVT::ValueType VT = N0.getValueType();
1121 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1123 // For each of OP in AND/OR/XOR:
1124 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1125 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1126 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1127 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1128 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1129 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1130 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1131 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1132 N0.getOperand(0).getValueType(),
1133 N0.getOperand(0), N1.getOperand(0));
1134 AddToWorkList(ORNode.Val);
1135 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1138 // For each of OP in SHL/SRL/SRA/AND...
1139 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1140 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1141 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1142 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1143 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1144 N0.getOperand(1) == N1.getOperand(1)) {
1145 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1146 N0.getOperand(0).getValueType(),
1147 N0.getOperand(0), N1.getOperand(0));
1148 AddToWorkList(ORNode.Val);
1149 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1155 SDOperand DAGCombiner::visitAND(SDNode *N) {
1156 SDOperand N0 = N->getOperand(0);
1157 SDOperand N1 = N->getOperand(1);
1158 SDOperand LL, LR, RL, RR, CC0, CC1;
1159 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1160 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1161 MVT::ValueType VT = N1.getValueType();
1163 // fold (and c1, c2) -> c1&c2
1165 return DAG.getNode(ISD::AND, VT, N0, N1);
1166 // canonicalize constant to RHS
1168 return DAG.getNode(ISD::AND, VT, N1, N0);
1169 // fold (and x, -1) -> x
1170 if (N1C && N1C->isAllOnesValue())
1172 // if (and x, c) is known to be zero, return 0
1173 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1174 return DAG.getConstant(0, VT);
1176 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1179 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1180 if (N1C && N0.getOpcode() == ISD::OR)
1181 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1182 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1184 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1185 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1186 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1187 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1188 ~N1C->getValue() & InMask)) {
1189 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1192 // Replace uses of the AND with uses of the Zero extend node.
1195 // We actually want to replace all uses of the any_extend with the
1196 // zero_extend, to avoid duplicating things. This will later cause this
1197 // AND to be folded.
1198 CombineTo(N0.Val, Zext);
1199 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1202 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1203 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1204 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1205 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1207 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1208 MVT::isInteger(LL.getValueType())) {
1209 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1210 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1211 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1212 AddToWorkList(ORNode.Val);
1213 return DAG.getSetCC(VT, ORNode, LR, Op1);
1215 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1216 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1217 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1218 AddToWorkList(ANDNode.Val);
1219 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1221 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1222 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1223 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1224 AddToWorkList(ORNode.Val);
1225 return DAG.getSetCC(VT, ORNode, LR, Op1);
1228 // canonicalize equivalent to ll == rl
1229 if (LL == RR && LR == RL) {
1230 Op1 = ISD::getSetCCSwappedOperands(Op1);
1233 if (LL == RL && LR == RR) {
1234 bool isInteger = MVT::isInteger(LL.getValueType());
1235 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1236 if (Result != ISD::SETCC_INVALID)
1237 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1241 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1242 if (N0.getOpcode() == N1.getOpcode()) {
1243 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1244 if (Tmp.Val) return Tmp;
1247 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1248 // fold (and (sra)) -> (and (srl)) when possible.
1249 if (!MVT::isVector(VT) &&
1250 SimplifyDemandedBits(SDOperand(N, 0)))
1251 return SDOperand(N, 0);
1252 // fold (zext_inreg (extload x)) -> (zextload x)
1253 if (ISD::isEXTLoad(N0.Val)) {
1254 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1255 MVT::ValueType EVT = LN0->getLoadedVT();
1256 // If we zero all the possible extended bits, then we can turn this into
1257 // a zextload if we are running before legalize or the operation is legal.
1258 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1259 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1260 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1261 LN0->getBasePtr(), LN0->getSrcValue(),
1262 LN0->getSrcValueOffset(), EVT);
1264 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1265 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1268 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1269 if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
1270 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1271 MVT::ValueType EVT = LN0->getLoadedVT();
1272 // If we zero all the possible extended bits, then we can turn this into
1273 // a zextload if we are running before legalize or the operation is legal.
1274 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1275 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1276 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1277 LN0->getBasePtr(), LN0->getSrcValue(),
1278 LN0->getSrcValueOffset(), EVT);
1280 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1281 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1285 // fold (and (load x), 255) -> (zextload x, i8)
1286 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1287 if (N1C && N0.getOpcode() == ISD::LOAD) {
1288 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1289 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1291 MVT::ValueType EVT, LoadedVT;
1292 if (N1C->getValue() == 255)
1294 else if (N1C->getValue() == 65535)
1296 else if (N1C->getValue() == ~0U)
1301 LoadedVT = LN0->getLoadedVT();
1302 if (EVT != MVT::Other && LoadedVT > EVT &&
1303 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1304 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1305 // For big endian targets, we need to add an offset to the pointer to
1306 // load the correct bytes. For little endian systems, we merely need to
1307 // read fewer bytes from the same pointer.
1309 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1310 SDOperand NewPtr = LN0->getBasePtr();
1311 if (!TLI.isLittleEndian())
1312 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1313 DAG.getConstant(PtrOff, PtrType));
1314 AddToWorkList(NewPtr.Val);
1316 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1317 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
1319 CombineTo(N0.Val, Load, Load.getValue(1));
1320 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1328 SDOperand DAGCombiner::visitOR(SDNode *N) {
1329 SDOperand N0 = N->getOperand(0);
1330 SDOperand N1 = N->getOperand(1);
1331 SDOperand LL, LR, RL, RR, CC0, CC1;
1332 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1333 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1334 MVT::ValueType VT = N1.getValueType();
1335 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1337 // fold (or c1, c2) -> c1|c2
1339 return DAG.getNode(ISD::OR, VT, N0, N1);
1340 // canonicalize constant to RHS
1342 return DAG.getNode(ISD::OR, VT, N1, N0);
1343 // fold (or x, 0) -> x
1344 if (N1C && N1C->isNullValue())
1346 // fold (or x, -1) -> -1
1347 if (N1C && N1C->isAllOnesValue())
1349 // fold (or x, c) -> c iff (x & ~c) == 0
1351 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1354 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1357 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1358 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1359 isa<ConstantSDNode>(N0.getOperand(1))) {
1360 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1361 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1363 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1365 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1366 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1367 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1368 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1370 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1371 MVT::isInteger(LL.getValueType())) {
1372 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1373 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1374 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1375 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1376 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1377 AddToWorkList(ORNode.Val);
1378 return DAG.getSetCC(VT, ORNode, LR, Op1);
1380 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1381 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1382 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1383 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1384 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1385 AddToWorkList(ANDNode.Val);
1386 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1389 // canonicalize equivalent to ll == rl
1390 if (LL == RR && LR == RL) {
1391 Op1 = ISD::getSetCCSwappedOperands(Op1);
1394 if (LL == RL && LR == RR) {
1395 bool isInteger = MVT::isInteger(LL.getValueType());
1396 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1397 if (Result != ISD::SETCC_INVALID)
1398 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1402 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1403 if (N0.getOpcode() == N1.getOpcode()) {
1404 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1405 if (Tmp.Val) return Tmp;
1408 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1409 if (N0.getOpcode() == ISD::AND &&
1410 N1.getOpcode() == ISD::AND &&
1411 N0.getOperand(1).getOpcode() == ISD::Constant &&
1412 N1.getOperand(1).getOpcode() == ISD::Constant &&
1413 // Don't increase # computations.
1414 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1415 // We can only do this xform if we know that bits from X that are set in C2
1416 // but not in C1 are already zero. Likewise for Y.
1417 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1418 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1420 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1421 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1422 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1423 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1428 // See if this is some rotate idiom.
1429 if (SDNode *Rot = MatchRotate(N0, N1))
1430 return SDOperand(Rot, 0);
1436 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1437 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1438 if (Op.getOpcode() == ISD::AND) {
1439 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1440 Mask = Op.getOperand(1);
1441 Op = Op.getOperand(0);
1447 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1455 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1456 // idioms for rotate, and if the target supports rotation instructions, generate
1458 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1459 // Must be a legal type. Expanded an promoted things won't work with rotates.
1460 MVT::ValueType VT = LHS.getValueType();
1461 if (!TLI.isTypeLegal(VT)) return 0;
1463 // The target must have at least one rotate flavor.
1464 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1465 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1466 if (!HasROTL && !HasROTR) return 0;
1468 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1469 SDOperand LHSShift; // The shift.
1470 SDOperand LHSMask; // AND value if any.
1471 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1472 return 0; // Not part of a rotate.
1474 SDOperand RHSShift; // The shift.
1475 SDOperand RHSMask; // AND value if any.
1476 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1477 return 0; // Not part of a rotate.
1479 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1480 return 0; // Not shifting the same value.
1482 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1483 return 0; // Shifts must disagree.
1485 // Canonicalize shl to left side in a shl/srl pair.
1486 if (RHSShift.getOpcode() == ISD::SHL) {
1487 std::swap(LHS, RHS);
1488 std::swap(LHSShift, RHSShift);
1489 std::swap(LHSMask , RHSMask );
1492 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1494 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1495 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1496 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
1497 RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
1498 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue();
1499 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue();
1500 if ((LShVal + RShVal) != OpSizeInBits)
1505 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1506 LHSShift.getOperand(1));
1508 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1509 RHSShift.getOperand(1));
1511 // If there is an AND of either shifted operand, apply it to the result.
1512 if (LHSMask.Val || RHSMask.Val) {
1513 uint64_t Mask = MVT::getIntVTBitMask(VT);
1516 uint64_t RHSBits = (1ULL << LShVal)-1;
1517 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1520 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1521 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1524 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1530 // If there is a mask here, and we have a variable shift, we can't be sure
1531 // that we're masking out the right stuff.
1532 if (LHSMask.Val || RHSMask.Val)
1535 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1536 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1537 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1538 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
1539 if (ConstantSDNode *SUBC =
1540 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) {
1541 if (SUBC->getValue() == OpSizeInBits)
1543 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1544 LHSShift.getOperand(1)).Val;
1546 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1547 LHSShift.getOperand(1)).Val;
1551 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1552 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1553 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1554 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
1555 if (ConstantSDNode *SUBC =
1556 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) {
1557 if (SUBC->getValue() == OpSizeInBits)
1559 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1560 LHSShift.getOperand(1)).Val;
1562 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1563 RHSShift.getOperand(1)).Val;
1571 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1572 SDOperand N0 = N->getOperand(0);
1573 SDOperand N1 = N->getOperand(1);
1574 SDOperand LHS, RHS, CC;
1575 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1576 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1577 MVT::ValueType VT = N0.getValueType();
1579 // fold (xor c1, c2) -> c1^c2
1581 return DAG.getNode(ISD::XOR, VT, N0, N1);
1582 // canonicalize constant to RHS
1584 return DAG.getNode(ISD::XOR, VT, N1, N0);
1585 // fold (xor x, 0) -> x
1586 if (N1C && N1C->isNullValue())
1589 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1592 // fold !(x cc y) -> (x !cc y)
1593 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1594 bool isInt = MVT::isInteger(LHS.getValueType());
1595 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1597 if (N0.getOpcode() == ISD::SETCC)
1598 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1599 if (N0.getOpcode() == ISD::SELECT_CC)
1600 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1601 assert(0 && "Unhandled SetCC Equivalent!");
1604 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1605 if (N1C && N1C->getValue() == 1 &&
1606 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1607 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1608 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1609 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1610 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1611 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1612 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1613 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1616 // fold !(x or y) -> (!x and !y) iff x or y are constants
1617 if (N1C && N1C->isAllOnesValue() &&
1618 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1619 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1620 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1621 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1622 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1623 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1624 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1625 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1628 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1629 if (N1C && N0.getOpcode() == ISD::XOR) {
1630 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1631 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1633 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1634 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1636 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1637 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1639 // fold (xor x, x) -> 0
1641 if (!MVT::isVector(VT)) {
1642 return DAG.getConstant(0, VT);
1643 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1644 // Produce a vector of zeros.
1645 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1646 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1647 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1651 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1652 if (N0.getOpcode() == N1.getOpcode()) {
1653 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1654 if (Tmp.Val) return Tmp;
1657 // Simplify the expression using non-local knowledge.
1658 if (!MVT::isVector(VT) &&
1659 SimplifyDemandedBits(SDOperand(N, 0)))
1660 return SDOperand(N, 0);
1665 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1666 SDOperand N0 = N->getOperand(0);
1667 SDOperand N1 = N->getOperand(1);
1668 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1669 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1670 MVT::ValueType VT = N0.getValueType();
1671 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1673 // fold (shl c1, c2) -> c1<<c2
1675 return DAG.getNode(ISD::SHL, VT, N0, N1);
1676 // fold (shl 0, x) -> 0
1677 if (N0C && N0C->isNullValue())
1679 // fold (shl x, c >= size(x)) -> undef
1680 if (N1C && N1C->getValue() >= OpSizeInBits)
1681 return DAG.getNode(ISD::UNDEF, VT);
1682 // fold (shl x, 0) -> x
1683 if (N1C && N1C->isNullValue())
1685 // if (shl x, c) is known to be zero, return 0
1686 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1687 return DAG.getConstant(0, VT);
1688 if (SimplifyDemandedBits(SDOperand(N, 0)))
1689 return SDOperand(N, 0);
1690 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1691 if (N1C && N0.getOpcode() == ISD::SHL &&
1692 N0.getOperand(1).getOpcode() == ISD::Constant) {
1693 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1694 uint64_t c2 = N1C->getValue();
1695 if (c1 + c2 > OpSizeInBits)
1696 return DAG.getConstant(0, VT);
1697 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1698 DAG.getConstant(c1 + c2, N1.getValueType()));
1700 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1701 // (srl (and x, -1 << c1), c1-c2)
1702 if (N1C && N0.getOpcode() == ISD::SRL &&
1703 N0.getOperand(1).getOpcode() == ISD::Constant) {
1704 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1705 uint64_t c2 = N1C->getValue();
1706 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1707 DAG.getConstant(~0ULL << c1, VT));
1709 return DAG.getNode(ISD::SHL, VT, Mask,
1710 DAG.getConstant(c2-c1, N1.getValueType()));
1712 return DAG.getNode(ISD::SRL, VT, Mask,
1713 DAG.getConstant(c1-c2, N1.getValueType()));
1715 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1716 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1717 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1718 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1719 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
1720 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1721 isa<ConstantSDNode>(N0.getOperand(1))) {
1722 return DAG.getNode(ISD::ADD, VT,
1723 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
1724 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
1729 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1730 SDOperand N0 = N->getOperand(0);
1731 SDOperand N1 = N->getOperand(1);
1732 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1733 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1734 MVT::ValueType VT = N0.getValueType();
1736 // fold (sra c1, c2) -> c1>>c2
1738 return DAG.getNode(ISD::SRA, VT, N0, N1);
1739 // fold (sra 0, x) -> 0
1740 if (N0C && N0C->isNullValue())
1742 // fold (sra -1, x) -> -1
1743 if (N0C && N0C->isAllOnesValue())
1745 // fold (sra x, c >= size(x)) -> undef
1746 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1747 return DAG.getNode(ISD::UNDEF, VT);
1748 // fold (sra x, 0) -> x
1749 if (N1C && N1C->isNullValue())
1751 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1753 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1754 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1757 default: EVT = MVT::Other; break;
1758 case 1: EVT = MVT::i1; break;
1759 case 8: EVT = MVT::i8; break;
1760 case 16: EVT = MVT::i16; break;
1761 case 32: EVT = MVT::i32; break;
1763 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1764 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1765 DAG.getValueType(EVT));
1768 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1769 if (N1C && N0.getOpcode() == ISD::SRA) {
1770 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1771 unsigned Sum = N1C->getValue() + C1->getValue();
1772 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1773 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1774 DAG.getConstant(Sum, N1C->getValueType(0)));
1778 // Simplify, based on bits shifted out of the LHS.
1779 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1780 return SDOperand(N, 0);
1783 // If the sign bit is known to be zero, switch this to a SRL.
1784 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1785 return DAG.getNode(ISD::SRL, VT, N0, N1);
1789 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1790 SDOperand N0 = N->getOperand(0);
1791 SDOperand N1 = N->getOperand(1);
1792 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1793 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1794 MVT::ValueType VT = N0.getValueType();
1795 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1797 // fold (srl c1, c2) -> c1 >>u c2
1799 return DAG.getNode(ISD::SRL, VT, N0, N1);
1800 // fold (srl 0, x) -> 0
1801 if (N0C && N0C->isNullValue())
1803 // fold (srl x, c >= size(x)) -> undef
1804 if (N1C && N1C->getValue() >= OpSizeInBits)
1805 return DAG.getNode(ISD::UNDEF, VT);
1806 // fold (srl x, 0) -> x
1807 if (N1C && N1C->isNullValue())
1809 // if (srl x, c) is known to be zero, return 0
1810 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1811 return DAG.getConstant(0, VT);
1812 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1813 if (N1C && N0.getOpcode() == ISD::SRL &&
1814 N0.getOperand(1).getOpcode() == ISD::Constant) {
1815 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1816 uint64_t c2 = N1C->getValue();
1817 if (c1 + c2 > OpSizeInBits)
1818 return DAG.getConstant(0, VT);
1819 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1820 DAG.getConstant(c1 + c2, N1.getValueType()));
1823 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1824 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1825 // Shifting in all undef bits?
1826 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1827 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1828 return DAG.getNode(ISD::UNDEF, VT);
1830 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1831 AddToWorkList(SmallShift.Val);
1832 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1835 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
1836 // bit, which is unmodified by sra.
1837 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
1838 if (N0.getOpcode() == ISD::SRA)
1839 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
1842 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1843 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1844 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1845 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1846 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1848 // If any of the input bits are KnownOne, then the input couldn't be all
1849 // zeros, thus the result of the srl will always be zero.
1850 if (KnownOne) return DAG.getConstant(0, VT);
1852 // If all of the bits input the to ctlz node are known to be zero, then
1853 // the result of the ctlz is "32" and the result of the shift is one.
1854 uint64_t UnknownBits = ~KnownZero & Mask;
1855 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1857 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1858 if ((UnknownBits & (UnknownBits-1)) == 0) {
1859 // Okay, we know that only that the single bit specified by UnknownBits
1860 // could be set on input to the CTLZ node. If this bit is set, the SRL
1861 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1862 // to an SRL,XOR pair, which is likely to simplify more.
1863 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1864 SDOperand Op = N0.getOperand(0);
1866 Op = DAG.getNode(ISD::SRL, VT, Op,
1867 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1868 AddToWorkList(Op.Val);
1870 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1877 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1878 SDOperand N0 = N->getOperand(0);
1879 MVT::ValueType VT = N->getValueType(0);
1881 // fold (ctlz c1) -> c2
1882 if (isa<ConstantSDNode>(N0))
1883 return DAG.getNode(ISD::CTLZ, VT, N0);
1887 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1888 SDOperand N0 = N->getOperand(0);
1889 MVT::ValueType VT = N->getValueType(0);
1891 // fold (cttz c1) -> c2
1892 if (isa<ConstantSDNode>(N0))
1893 return DAG.getNode(ISD::CTTZ, VT, N0);
1897 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1898 SDOperand N0 = N->getOperand(0);
1899 MVT::ValueType VT = N->getValueType(0);
1901 // fold (ctpop c1) -> c2
1902 if (isa<ConstantSDNode>(N0))
1903 return DAG.getNode(ISD::CTPOP, VT, N0);
1907 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1908 SDOperand N0 = N->getOperand(0);
1909 SDOperand N1 = N->getOperand(1);
1910 SDOperand N2 = N->getOperand(2);
1911 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1912 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1913 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1914 MVT::ValueType VT = N->getValueType(0);
1916 // fold select C, X, X -> X
1919 // fold select true, X, Y -> X
1920 if (N0C && !N0C->isNullValue())
1922 // fold select false, X, Y -> Y
1923 if (N0C && N0C->isNullValue())
1925 // fold select C, 1, X -> C | X
1926 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1927 return DAG.getNode(ISD::OR, VT, N0, N2);
1928 // fold select C, 0, X -> ~C & X
1929 // FIXME: this should check for C type == X type, not i1?
1930 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1931 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1932 AddToWorkList(XORNode.Val);
1933 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1935 // fold select C, X, 1 -> ~C | X
1936 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1937 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1938 AddToWorkList(XORNode.Val);
1939 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1941 // fold select C, X, 0 -> C & X
1942 // FIXME: this should check for C type == X type, not i1?
1943 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1944 return DAG.getNode(ISD::AND, VT, N0, N1);
1945 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1946 if (MVT::i1 == VT && N0 == N1)
1947 return DAG.getNode(ISD::OR, VT, N0, N2);
1948 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1949 if (MVT::i1 == VT && N0 == N2)
1950 return DAG.getNode(ISD::AND, VT, N0, N1);
1952 // If we can fold this based on the true/false value, do so.
1953 if (SimplifySelectOps(N, N1, N2))
1954 return SDOperand(N, 0); // Don't revisit N.
1956 // fold selects based on a setcc into other things, such as min/max/abs
1957 if (N0.getOpcode() == ISD::SETCC)
1959 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1960 // having to say they don't support SELECT_CC on every type the DAG knows
1961 // about, since there is no way to mark an opcode illegal at all value types
1962 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1963 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1964 N1, N2, N0.getOperand(2));
1966 return SimplifySelect(N0, N1, N2);
1970 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1971 SDOperand N0 = N->getOperand(0);
1972 SDOperand N1 = N->getOperand(1);
1973 SDOperand N2 = N->getOperand(2);
1974 SDOperand N3 = N->getOperand(3);
1975 SDOperand N4 = N->getOperand(4);
1976 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1978 // fold select_cc lhs, rhs, x, x, cc -> x
1982 // Determine if the condition we're dealing with is constant
1983 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1984 if (SCC.Val) AddToWorkList(SCC.Val);
1986 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
1987 if (SCCC->getValue())
1988 return N2; // cond always true -> true val
1990 return N3; // cond always false -> false val
1993 // Fold to a simpler select_cc
1994 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1995 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
1996 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
1999 // If we can fold this based on the true/false value, do so.
2000 if (SimplifySelectOps(N, N2, N3))
2001 return SDOperand(N, 0); // Don't revisit N.
2003 // fold select_cc into other things, such as min/max/abs
2004 return SimplifySelectCC(N0, N1, N2, N3, CC);
2007 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
2008 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2009 cast<CondCodeSDNode>(N->getOperand(2))->get());
2012 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2013 SDOperand N0 = N->getOperand(0);
2014 MVT::ValueType VT = N->getValueType(0);
2016 // fold (sext c1) -> c1
2017 if (isa<ConstantSDNode>(N0))
2018 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2020 // fold (sext (sext x)) -> (sext x)
2021 // fold (sext (aext x)) -> (sext x)
2022 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2023 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2025 // fold (sext (truncate x)) -> (sextinreg x).
2026 if (N0.getOpcode() == ISD::TRUNCATE &&
2027 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2028 N0.getValueType()))) {
2029 SDOperand Op = N0.getOperand(0);
2030 if (Op.getValueType() < VT) {
2031 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2032 } else if (Op.getValueType() > VT) {
2033 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2035 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2036 DAG.getValueType(N0.getValueType()));
2039 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2040 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2041 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2042 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2043 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2044 LN0->getBasePtr(), LN0->getSrcValue(),
2045 LN0->getSrcValueOffset(),
2047 CombineTo(N, ExtLoad);
2048 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2049 ExtLoad.getValue(1));
2050 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2053 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2054 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2055 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
2056 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2057 MVT::ValueType EVT = LN0->getLoadedVT();
2058 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2059 LN0->getBasePtr(), LN0->getSrcValue(),
2060 LN0->getSrcValueOffset(), EVT);
2061 CombineTo(N, ExtLoad);
2062 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2063 ExtLoad.getValue(1));
2064 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2070 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2071 SDOperand N0 = N->getOperand(0);
2072 MVT::ValueType VT = N->getValueType(0);
2074 // fold (zext c1) -> c1
2075 if (isa<ConstantSDNode>(N0))
2076 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2077 // fold (zext (zext x)) -> (zext x)
2078 // fold (zext (aext x)) -> (zext x)
2079 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2080 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2082 // fold (zext (truncate x)) -> (and x, mask)
2083 if (N0.getOpcode() == ISD::TRUNCATE &&
2084 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2085 SDOperand Op = N0.getOperand(0);
2086 if (Op.getValueType() < VT) {
2087 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2088 } else if (Op.getValueType() > VT) {
2089 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2091 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2094 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2095 if (N0.getOpcode() == ISD::AND &&
2096 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2097 N0.getOperand(1).getOpcode() == ISD::Constant) {
2098 SDOperand X = N0.getOperand(0).getOperand(0);
2099 if (X.getValueType() < VT) {
2100 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2101 } else if (X.getValueType() > VT) {
2102 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2104 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2105 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2108 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2109 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2110 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2111 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2112 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2113 LN0->getBasePtr(), LN0->getSrcValue(),
2114 LN0->getSrcValueOffset(),
2116 CombineTo(N, ExtLoad);
2117 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2118 ExtLoad.getValue(1));
2119 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2122 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2123 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2124 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
2125 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2126 MVT::ValueType EVT = LN0->getLoadedVT();
2127 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2128 LN0->getBasePtr(), LN0->getSrcValue(),
2129 LN0->getSrcValueOffset(), EVT);
2130 CombineTo(N, ExtLoad);
2131 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2132 ExtLoad.getValue(1));
2133 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2138 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2139 SDOperand N0 = N->getOperand(0);
2140 MVT::ValueType VT = N->getValueType(0);
2142 // fold (aext c1) -> c1
2143 if (isa<ConstantSDNode>(N0))
2144 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2145 // fold (aext (aext x)) -> (aext x)
2146 // fold (aext (zext x)) -> (zext x)
2147 // fold (aext (sext x)) -> (sext x)
2148 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2149 N0.getOpcode() == ISD::ZERO_EXTEND ||
2150 N0.getOpcode() == ISD::SIGN_EXTEND)
2151 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2153 // fold (aext (truncate x))
2154 if (N0.getOpcode() == ISD::TRUNCATE) {
2155 SDOperand TruncOp = N0.getOperand(0);
2156 if (TruncOp.getValueType() == VT)
2157 return TruncOp; // x iff x size == zext size.
2158 if (TruncOp.getValueType() > VT)
2159 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2160 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2163 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2164 if (N0.getOpcode() == ISD::AND &&
2165 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2166 N0.getOperand(1).getOpcode() == ISD::Constant) {
2167 SDOperand X = N0.getOperand(0).getOperand(0);
2168 if (X.getValueType() < VT) {
2169 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2170 } else if (X.getValueType() > VT) {
2171 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2173 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2174 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2177 // fold (aext (load x)) -> (aext (truncate (extload x)))
2178 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2179 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2180 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2181 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2182 LN0->getBasePtr(), LN0->getSrcValue(),
2183 LN0->getSrcValueOffset(),
2185 CombineTo(N, ExtLoad);
2186 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2187 ExtLoad.getValue(1));
2188 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2191 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2192 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2193 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2194 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) &&
2196 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2197 MVT::ValueType EVT = LN0->getLoadedVT();
2198 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2199 LN0->getChain(), LN0->getBasePtr(),
2201 LN0->getSrcValueOffset(), EVT);
2202 CombineTo(N, ExtLoad);
2203 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2204 ExtLoad.getValue(1));
2205 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2211 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2212 SDOperand N0 = N->getOperand(0);
2213 SDOperand N1 = N->getOperand(1);
2214 MVT::ValueType VT = N->getValueType(0);
2215 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2216 unsigned EVTBits = MVT::getSizeInBits(EVT);
2218 // fold (sext_in_reg c1) -> c1
2219 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2220 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2222 // If the input is already sign extended, just drop the extension.
2223 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2226 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2227 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2228 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2229 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2232 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
2233 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2234 return DAG.getZeroExtendInReg(N0, EVT);
2236 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2237 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2238 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2239 if (N0.getOpcode() == ISD::SRL) {
2240 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2241 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2242 // We can turn this into an SRA iff the input to the SRL is already sign
2244 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
2245 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2246 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2250 // fold (sext_inreg (extload x)) -> (sextload x)
2251 if (ISD::isEXTLoad(N0.Val) &&
2252 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2253 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2254 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2255 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2256 LN0->getBasePtr(), LN0->getSrcValue(),
2257 LN0->getSrcValueOffset(), EVT);
2258 CombineTo(N, ExtLoad);
2259 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2260 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2262 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2263 if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
2264 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2265 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2266 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2267 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2268 LN0->getBasePtr(), LN0->getSrcValue(),
2269 LN0->getSrcValueOffset(), EVT);
2270 CombineTo(N, ExtLoad);
2271 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2272 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2277 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2278 SDOperand N0 = N->getOperand(0);
2279 MVT::ValueType VT = N->getValueType(0);
2282 if (N0.getValueType() == N->getValueType(0))
2284 // fold (truncate c1) -> c1
2285 if (isa<ConstantSDNode>(N0))
2286 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2287 // fold (truncate (truncate x)) -> (truncate x)
2288 if (N0.getOpcode() == ISD::TRUNCATE)
2289 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2290 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2291 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2292 N0.getOpcode() == ISD::ANY_EXTEND) {
2293 if (N0.getValueType() < VT)
2294 // if the source is smaller than the dest, we still need an extend
2295 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2296 else if (N0.getValueType() > VT)
2297 // if the source is larger than the dest, than we just need the truncate
2298 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2300 // if the source and dest are the same type, we can drop both the extend
2302 return N0.getOperand(0);
2304 // fold (truncate (load x)) -> (smaller load x)
2305 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2306 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
2307 "Cannot truncate to larger type!");
2308 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2309 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2310 // For big endian targets, we need to add an offset to the pointer to load
2311 // the correct bytes. For little endian systems, we merely need to read
2312 // fewer bytes from the same pointer.
2314 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
2315 SDOperand NewPtr = TLI.isLittleEndian() ? LN0->getBasePtr() :
2316 DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2317 DAG.getConstant(PtrOff, PtrType));
2318 AddToWorkList(NewPtr.Val);
2319 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr,
2320 LN0->getSrcValue(), LN0->getSrcValueOffset());
2322 CombineTo(N0.Val, Load, Load.getValue(1));
2323 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2328 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2329 SDOperand N0 = N->getOperand(0);
2330 MVT::ValueType VT = N->getValueType(0);
2332 // If the input is a constant, let getNode() fold it.
2333 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2334 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2335 if (Res.Val != N) return Res;
2338 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2339 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2341 // fold (conv (load x)) -> (load (conv*)x)
2342 // FIXME: These xforms need to know that the resultant load doesn't need a
2343 // higher alignment than the original!
2344 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2345 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2346 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2347 LN0->getSrcValue(), LN0->getSrcValueOffset());
2349 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2357 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2358 SDOperand N0 = N->getOperand(0);
2359 MVT::ValueType VT = N->getValueType(0);
2361 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2362 // First check to see if this is all constant.
2363 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2364 VT == MVT::Vector) {
2365 bool isSimple = true;
2366 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2367 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2368 N0.getOperand(i).getOpcode() != ISD::Constant &&
2369 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2374 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2375 if (isSimple && !MVT::isVector(DestEltVT)) {
2376 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2383 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2384 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2385 /// destination element value type.
2386 SDOperand DAGCombiner::
2387 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2388 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2390 // If this is already the right type, we're done.
2391 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2393 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2394 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2396 // If this is a conversion of N elements of one type to N elements of another
2397 // type, convert each element. This handles FP<->INT cases.
2398 if (SrcBitSize == DstBitSize) {
2399 SmallVector<SDOperand, 8> Ops;
2400 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2401 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2402 AddToWorkList(Ops.back().Val);
2404 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2405 Ops.push_back(DAG.getValueType(DstEltVT));
2406 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2409 // Otherwise, we're growing or shrinking the elements. To avoid having to
2410 // handle annoying details of growing/shrinking FP values, we convert them to
2412 if (MVT::isFloatingPoint(SrcEltVT)) {
2413 // Convert the input float vector to a int vector where the elements are the
2415 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2416 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2417 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2421 // Now we know the input is an integer vector. If the output is a FP type,
2422 // convert to integer first, then to FP of the right size.
2423 if (MVT::isFloatingPoint(DstEltVT)) {
2424 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2425 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2426 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2428 // Next, convert to FP elements of the same size.
2429 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2432 // Okay, we know the src/dst types are both integers of differing types.
2433 // Handling growing first.
2434 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2435 if (SrcBitSize < DstBitSize) {
2436 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2438 SmallVector<SDOperand, 8> Ops;
2439 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2440 i += NumInputsPerOutput) {
2441 bool isLE = TLI.isLittleEndian();
2442 uint64_t NewBits = 0;
2443 bool EltIsUndef = true;
2444 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2445 // Shift the previously computed bits over.
2446 NewBits <<= SrcBitSize;
2447 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2448 if (Op.getOpcode() == ISD::UNDEF) continue;
2451 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2455 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2457 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2460 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2461 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2462 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2465 // Finally, this must be the case where we are shrinking elements: each input
2466 // turns into multiple outputs.
2467 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2468 SmallVector<SDOperand, 8> Ops;
2469 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2470 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2471 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2472 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2475 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2477 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2478 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2479 OpVal >>= DstBitSize;
2480 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2483 // For big endian targets, swap the order of the pieces of each element.
2484 if (!TLI.isLittleEndian())
2485 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2487 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2488 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2489 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2494 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2495 SDOperand N0 = N->getOperand(0);
2496 SDOperand N1 = N->getOperand(1);
2497 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2498 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2499 MVT::ValueType VT = N->getValueType(0);
2501 // fold (fadd c1, c2) -> c1+c2
2503 return DAG.getNode(ISD::FADD, VT, N0, N1);
2504 // canonicalize constant to RHS
2505 if (N0CFP && !N1CFP)
2506 return DAG.getNode(ISD::FADD, VT, N1, N0);
2507 // fold (A + (-B)) -> A-B
2508 if (N1.getOpcode() == ISD::FNEG)
2509 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2510 // fold ((-A) + B) -> B-A
2511 if (N0.getOpcode() == ISD::FNEG)
2512 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2516 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2517 SDOperand N0 = N->getOperand(0);
2518 SDOperand N1 = N->getOperand(1);
2519 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2520 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2521 MVT::ValueType VT = N->getValueType(0);
2523 // fold (fsub c1, c2) -> c1-c2
2525 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2526 // fold (A-(-B)) -> A+B
2527 if (N1.getOpcode() == ISD::FNEG)
2528 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2532 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2533 SDOperand N0 = N->getOperand(0);
2534 SDOperand N1 = N->getOperand(1);
2535 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2536 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2537 MVT::ValueType VT = N->getValueType(0);
2539 // fold (fmul c1, c2) -> c1*c2
2541 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2542 // canonicalize constant to RHS
2543 if (N0CFP && !N1CFP)
2544 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2545 // fold (fmul X, 2.0) -> (fadd X, X)
2546 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2547 return DAG.getNode(ISD::FADD, VT, N0, N0);
2551 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2552 SDOperand N0 = N->getOperand(0);
2553 SDOperand N1 = N->getOperand(1);
2554 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2555 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2556 MVT::ValueType VT = N->getValueType(0);
2558 // fold (fdiv c1, c2) -> c1/c2
2560 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2564 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2565 SDOperand N0 = N->getOperand(0);
2566 SDOperand N1 = N->getOperand(1);
2567 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2568 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2569 MVT::ValueType VT = N->getValueType(0);
2571 // fold (frem c1, c2) -> fmod(c1,c2)
2573 return DAG.getNode(ISD::FREM, VT, N0, N1);
2577 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2578 SDOperand N0 = N->getOperand(0);
2579 SDOperand N1 = N->getOperand(1);
2580 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2581 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2582 MVT::ValueType VT = N->getValueType(0);
2584 if (N0CFP && N1CFP) // Constant fold
2585 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2588 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2589 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2594 u.d = N1CFP->getValue();
2596 return DAG.getNode(ISD::FABS, VT, N0);
2598 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2601 // copysign(fabs(x), y) -> copysign(x, y)
2602 // copysign(fneg(x), y) -> copysign(x, y)
2603 // copysign(copysign(x,z), y) -> copysign(x, y)
2604 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2605 N0.getOpcode() == ISD::FCOPYSIGN)
2606 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2608 // copysign(x, abs(y)) -> abs(x)
2609 if (N1.getOpcode() == ISD::FABS)
2610 return DAG.getNode(ISD::FABS, VT, N0);
2612 // copysign(x, copysign(y,z)) -> copysign(x, z)
2613 if (N1.getOpcode() == ISD::FCOPYSIGN)
2614 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2616 // copysign(x, fp_extend(y)) -> copysign(x, y)
2617 // copysign(x, fp_round(y)) -> copysign(x, y)
2618 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2619 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2626 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2627 SDOperand N0 = N->getOperand(0);
2628 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2629 MVT::ValueType VT = N->getValueType(0);
2631 // fold (sint_to_fp c1) -> c1fp
2633 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2637 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2638 SDOperand N0 = N->getOperand(0);
2639 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2640 MVT::ValueType VT = N->getValueType(0);
2642 // fold (uint_to_fp c1) -> c1fp
2644 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2648 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2649 SDOperand N0 = N->getOperand(0);
2650 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2651 MVT::ValueType VT = N->getValueType(0);
2653 // fold (fp_to_sint c1fp) -> c1
2655 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2659 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2660 SDOperand N0 = N->getOperand(0);
2661 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2662 MVT::ValueType VT = N->getValueType(0);
2664 // fold (fp_to_uint c1fp) -> c1
2666 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2670 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2671 SDOperand N0 = N->getOperand(0);
2672 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2673 MVT::ValueType VT = N->getValueType(0);
2675 // fold (fp_round c1fp) -> c1fp
2677 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2679 // fold (fp_round (fp_extend x)) -> x
2680 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2681 return N0.getOperand(0);
2683 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2684 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2685 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2686 AddToWorkList(Tmp.Val);
2687 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2693 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2694 SDOperand N0 = N->getOperand(0);
2695 MVT::ValueType VT = N->getValueType(0);
2696 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2697 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2699 // fold (fp_round_inreg c1fp) -> c1fp
2701 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2702 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2707 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2708 SDOperand N0 = N->getOperand(0);
2709 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2710 MVT::ValueType VT = N->getValueType(0);
2712 // fold (fp_extend c1fp) -> c1fp
2714 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2716 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2717 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2718 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2719 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2720 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2721 LN0->getBasePtr(), LN0->getSrcValue(),
2722 LN0->getSrcValueOffset(),
2724 CombineTo(N, ExtLoad);
2725 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2726 ExtLoad.getValue(1));
2727 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2734 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2735 SDOperand N0 = N->getOperand(0);
2736 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2737 MVT::ValueType VT = N->getValueType(0);
2739 // fold (fneg c1) -> -c1
2741 return DAG.getNode(ISD::FNEG, VT, N0);
2742 // fold (fneg (sub x, y)) -> (sub y, x)
2743 if (N0.getOpcode() == ISD::SUB)
2744 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2745 // fold (fneg (fneg x)) -> x
2746 if (N0.getOpcode() == ISD::FNEG)
2747 return N0.getOperand(0);
2751 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2752 SDOperand N0 = N->getOperand(0);
2753 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2754 MVT::ValueType VT = N->getValueType(0);
2756 // fold (fabs c1) -> fabs(c1)
2758 return DAG.getNode(ISD::FABS, VT, N0);
2759 // fold (fabs (fabs x)) -> (fabs x)
2760 if (N0.getOpcode() == ISD::FABS)
2761 return N->getOperand(0);
2762 // fold (fabs (fneg x)) -> (fabs x)
2763 // fold (fabs (fcopysign x, y)) -> (fabs x)
2764 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2765 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2770 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2771 SDOperand Chain = N->getOperand(0);
2772 SDOperand N1 = N->getOperand(1);
2773 SDOperand N2 = N->getOperand(2);
2774 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2776 // never taken branch, fold to chain
2777 if (N1C && N1C->isNullValue())
2779 // unconditional branch
2780 if (N1C && N1C->getValue() == 1)
2781 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2782 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2784 if (N1.getOpcode() == ISD::SETCC &&
2785 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2786 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2787 N1.getOperand(0), N1.getOperand(1), N2);
2792 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2794 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2795 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2796 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2798 // Use SimplifySetCC to simplify SETCC's.
2799 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2800 if (Simp.Val) AddToWorkList(Simp.Val);
2802 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2804 // fold br_cc true, dest -> br dest (unconditional branch)
2805 if (SCCC && SCCC->getValue())
2806 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2808 // fold br_cc false, dest -> unconditional fall through
2809 if (SCCC && SCCC->isNullValue())
2810 return N->getOperand(0);
2812 // fold to a simpler setcc
2813 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2814 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2815 Simp.getOperand(2), Simp.getOperand(0),
2816 Simp.getOperand(1), N->getOperand(4));
2820 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2821 LoadSDNode *LD = cast<LoadSDNode>(N);
2822 SDOperand Chain = LD->getChain();
2823 SDOperand Ptr = LD->getBasePtr();
2825 // If there are no uses of the loaded value, change uses of the chain value
2826 // into uses of the chain input (i.e. delete the dead load).
2827 if (N->hasNUsesOfValue(0, 0))
2828 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2830 // If this load is directly stored, replace the load value with the stored
2832 // TODO: Handle store large -> read small portion.
2833 // TODO: Handle TRUNCSTORE/LOADEXT
2834 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
2835 if (ISD::isNON_TRUNCStore(Chain.Val)) {
2836 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
2837 if (PrevST->getBasePtr() == Ptr &&
2838 PrevST->getValue().getValueType() == N->getValueType(0))
2839 return CombineTo(N, Chain.getOperand(1), Chain);
2844 // Walk up chain skipping non-aliasing memory nodes.
2845 SDOperand BetterChain = FindBetterChain(N, Chain);
2847 // If there is a better chain.
2848 if (Chain != BetterChain) {
2851 // Replace the chain to void dependency.
2852 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
2853 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
2854 LD->getSrcValue(), LD->getSrcValueOffset());
2856 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
2857 LD->getValueType(0),
2858 BetterChain, Ptr, LD->getSrcValue(),
2859 LD->getSrcValueOffset(),
2863 // Create token factor to keep old chain connected.
2864 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
2865 Chain, ReplLoad.getValue(1));
2867 // Replace uses with load result and token factor. Don't add users
2869 return CombineTo(N, ReplLoad.getValue(0), Token, false);
2873 // Try transforming N to an indexed load.
2874 if (CombineToIndexedLoadStore(N))
2875 return SDOperand(N, 0);
2880 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2881 StoreSDNode *ST = cast<StoreSDNode>(N);
2882 SDOperand Chain = ST->getChain();
2883 SDOperand Value = ST->getValue();
2884 SDOperand Ptr = ST->getBasePtr();
2886 // If this is a store of a bit convert, store the input value.
2887 // FIXME: This needs to know that the resultant store does not need a
2888 // higher alignment than the original.
2889 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
2890 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
2891 ST->getSrcValueOffset());
2895 // Walk up chain skipping non-aliasing memory nodes.
2896 SDOperand BetterChain = FindBetterChain(N, Chain);
2898 // If there is a better chain.
2899 if (Chain != BetterChain) {
2900 // Replace the chain to avoid dependency.
2901 SDOperand ReplStore;
2902 if (ST->isTruncatingStore()) {
2903 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
2904 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT());
2906 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
2907 ST->getSrcValue(), ST->getSrcValueOffset());
2910 // Create token to keep both nodes around.
2912 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
2914 // Don't add users to work list.
2915 return CombineTo(N, Token, false);
2919 // Try transforming N to an indexed store.
2920 if (CombineToIndexedLoadStore(N))
2921 return SDOperand(N, 0);
2926 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
2927 SDOperand InVec = N->getOperand(0);
2928 SDOperand InVal = N->getOperand(1);
2929 SDOperand EltNo = N->getOperand(2);
2931 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
2932 // vector with the inserted element.
2933 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2934 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2935 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2936 if (Elt < Ops.size())
2938 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
2939 &Ops[0], Ops.size());
2945 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
2946 SDOperand InVec = N->getOperand(0);
2947 SDOperand InVal = N->getOperand(1);
2948 SDOperand EltNo = N->getOperand(2);
2949 SDOperand NumElts = N->getOperand(3);
2950 SDOperand EltType = N->getOperand(4);
2952 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
2953 // vector with the inserted element.
2954 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2955 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2956 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2957 if (Elt < Ops.size()-2)
2959 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
2960 &Ops[0], Ops.size());
2966 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
2967 unsigned NumInScalars = N->getNumOperands()-2;
2968 SDOperand NumElts = N->getOperand(NumInScalars);
2969 SDOperand EltType = N->getOperand(NumInScalars+1);
2971 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
2972 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
2973 // two distinct vectors, turn this into a shuffle node.
2974 SDOperand VecIn1, VecIn2;
2975 for (unsigned i = 0; i != NumInScalars; ++i) {
2976 // Ignore undef inputs.
2977 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
2979 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
2980 // constant index, bail out.
2981 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
2982 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
2983 VecIn1 = VecIn2 = SDOperand(0, 0);
2987 // If the input vector type disagrees with the result of the vbuild_vector,
2988 // we can't make a shuffle.
2989 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
2990 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
2991 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
2992 VecIn1 = VecIn2 = SDOperand(0, 0);
2996 // Otherwise, remember this. We allow up to two distinct input vectors.
2997 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
3000 if (VecIn1.Val == 0) {
3001 VecIn1 = ExtractedFromVec;
3002 } else if (VecIn2.Val == 0) {
3003 VecIn2 = ExtractedFromVec;
3006 VecIn1 = VecIn2 = SDOperand(0, 0);
3011 // If everything is good, we can make a shuffle operation.
3013 SmallVector<SDOperand, 8> BuildVecIndices;
3014 for (unsigned i = 0; i != NumInScalars; ++i) {
3015 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
3016 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
3020 SDOperand Extract = N->getOperand(i);
3022 // If extracting from the first vector, just use the index directly.
3023 if (Extract.getOperand(0) == VecIn1) {
3024 BuildVecIndices.push_back(Extract.getOperand(1));
3028 // Otherwise, use InIdx + VecSize
3029 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
3030 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
3033 // Add count and size info.
3034 BuildVecIndices.push_back(NumElts);
3035 BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
3037 // Return the new VVECTOR_SHUFFLE node.
3043 // Use an undef vbuild_vector as input for the second operand.
3044 std::vector<SDOperand> UnOps(NumInScalars,
3045 DAG.getNode(ISD::UNDEF,
3046 cast<VTSDNode>(EltType)->getVT()));
3047 UnOps.push_back(NumElts);
3048 UnOps.push_back(EltType);
3049 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3050 &UnOps[0], UnOps.size());
3051 AddToWorkList(Ops[1].Val);
3053 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3054 &BuildVecIndices[0], BuildVecIndices.size());
3057 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
3063 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
3064 SDOperand ShufMask = N->getOperand(2);
3065 unsigned NumElts = ShufMask.getNumOperands();
3067 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3068 bool isIdentity = true;
3069 for (unsigned i = 0; i != NumElts; ++i) {
3070 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3071 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3076 if (isIdentity) return N->getOperand(0);
3078 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3080 for (unsigned i = 0; i != NumElts; ++i) {
3081 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3082 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3087 if (isIdentity) return N->getOperand(1);
3089 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3091 bool isUnary = true;
3092 bool isSplat = true;
3094 unsigned BaseIdx = 0;
3095 for (unsigned i = 0; i != NumElts; ++i)
3096 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3097 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3098 int V = (Idx < NumElts) ? 0 : 1;
3112 SDOperand N0 = N->getOperand(0);
3113 SDOperand N1 = N->getOperand(1);
3114 // Normalize unary shuffle so the RHS is undef.
3115 if (isUnary && VecNum == 1)
3118 // If it is a splat, check if the argument vector is a build_vector with
3119 // all scalar elements the same.
3122 if (V->getOpcode() == ISD::BIT_CONVERT)
3123 V = V->getOperand(0).Val;
3124 if (V->getOpcode() == ISD::BUILD_VECTOR) {
3125 unsigned NumElems = V->getNumOperands()-2;
3126 if (NumElems > BaseIdx) {
3128 bool AllSame = true;
3129 for (unsigned i = 0; i != NumElems; ++i) {
3130 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3131 Base = V->getOperand(i);
3135 // Splat of <u, u, u, u>, return <u, u, u, u>
3138 for (unsigned i = 0; i != NumElems; ++i) {
3139 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3140 V->getOperand(i) != Base) {
3145 // Splat of <x, x, x, x>, return <x, x, x, x>
3152 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3154 if (isUnary || N0 == N1) {
3155 if (N0.getOpcode() == ISD::UNDEF)
3156 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
3157 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3159 SmallVector<SDOperand, 8> MappedOps;
3160 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
3161 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3162 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3163 MappedOps.push_back(ShufMask.getOperand(i));
3166 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3167 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3170 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
3171 &MappedOps[0], MappedOps.size());
3172 AddToWorkList(ShufMask.Val);
3173 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
3175 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
3182 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
3183 SDOperand ShufMask = N->getOperand(2);
3184 unsigned NumElts = ShufMask.getNumOperands()-2;
3186 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3187 bool isIdentity = true;
3188 for (unsigned i = 0; i != NumElts; ++i) {
3189 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3190 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3195 if (isIdentity) return N->getOperand(0);
3197 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3199 for (unsigned i = 0; i != NumElts; ++i) {
3200 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3201 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3206 if (isIdentity) return N->getOperand(1);
3208 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3210 bool isUnary = true;
3211 bool isSplat = true;
3213 unsigned BaseIdx = 0;
3214 for (unsigned i = 0; i != NumElts; ++i)
3215 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3216 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3217 int V = (Idx < NumElts) ? 0 : 1;
3231 SDOperand N0 = N->getOperand(0);
3232 SDOperand N1 = N->getOperand(1);
3233 // Normalize unary shuffle so the RHS is undef.
3234 if (isUnary && VecNum == 1)
3237 // If it is a splat, check if the argument vector is a build_vector with
3238 // all scalar elements the same.
3242 // If this is a vbit convert that changes the element type of the vector but
3243 // not the number of vector elements, look through it. Be careful not to
3244 // look though conversions that change things like v4f32 to v2f64.
3245 if (V->getOpcode() == ISD::VBIT_CONVERT) {
3246 SDOperand ConvInput = V->getOperand(0);
3247 if (ConvInput.getValueType() == MVT::Vector &&
3249 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2))
3253 if (V->getOpcode() == ISD::VBUILD_VECTOR) {
3254 unsigned NumElems = V->getNumOperands()-2;
3255 if (NumElems > BaseIdx) {
3257 bool AllSame = true;
3258 for (unsigned i = 0; i != NumElems; ++i) {
3259 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3260 Base = V->getOperand(i);
3264 // Splat of <u, u, u, u>, return <u, u, u, u>
3267 for (unsigned i = 0; i != NumElems; ++i) {
3268 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3269 V->getOperand(i) != Base) {
3274 // Splat of <x, x, x, x>, return <x, x, x, x>
3281 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3283 if (isUnary || N0 == N1) {
3284 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3286 SmallVector<SDOperand, 8> MappedOps;
3287 for (unsigned i = 0; i != NumElts; ++i) {
3288 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3289 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3290 MappedOps.push_back(ShufMask.getOperand(i));
3293 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3294 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3297 // Add the type/#elts values.
3298 MappedOps.push_back(ShufMask.getOperand(NumElts));
3299 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
3301 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
3302 &MappedOps[0], MappedOps.size());
3303 AddToWorkList(ShufMask.Val);
3305 // Build the undef vector.
3306 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
3307 for (unsigned i = 0; i != NumElts; ++i)
3308 MappedOps[i] = UDVal;
3309 MappedOps[NumElts ] = *(N0.Val->op_end()-2);
3310 MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
3311 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3312 &MappedOps[0], MappedOps.size());
3314 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3315 N0, UDVal, ShufMask,
3316 MappedOps[NumElts], MappedOps[NumElts+1]);
3322 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
3323 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
3324 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
3325 /// vector_shuffle V, Zero, <0, 4, 2, 4>
3326 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
3327 SDOperand LHS = N->getOperand(0);
3328 SDOperand RHS = N->getOperand(1);
3329 if (N->getOpcode() == ISD::VAND) {
3330 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
3331 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
3332 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
3333 RHS = RHS.getOperand(0);
3334 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3335 std::vector<SDOperand> IdxOps;
3336 unsigned NumOps = RHS.getNumOperands();
3337 unsigned NumElts = NumOps-2;
3338 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
3339 for (unsigned i = 0; i != NumElts; ++i) {
3340 SDOperand Elt = RHS.getOperand(i);
3341 if (!isa<ConstantSDNode>(Elt))
3343 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
3344 IdxOps.push_back(DAG.getConstant(i, EVT));
3345 else if (cast<ConstantSDNode>(Elt)->isNullValue())
3346 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
3351 // Let's see if the target supports this vector_shuffle.
3352 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
3355 // Return the new VVECTOR_SHUFFLE node.
3356 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
3357 SDOperand EVTNode = DAG.getValueType(EVT);
3358 std::vector<SDOperand> Ops;
3359 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode,
3362 AddToWorkList(LHS.Val);
3363 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
3364 ZeroOps.push_back(NumEltsNode);
3365 ZeroOps.push_back(EVTNode);
3366 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3367 &ZeroOps[0], ZeroOps.size()));
3368 IdxOps.push_back(NumEltsNode);
3369 IdxOps.push_back(EVTNode);
3370 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3371 &IdxOps[0], IdxOps.size()));
3372 Ops.push_back(NumEltsNode);
3373 Ops.push_back(EVTNode);
3374 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3375 &Ops[0], Ops.size());
3376 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
3377 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
3378 DstVecSize, DstVecEVT);
3386 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
3387 /// the scalar operation of the vop if it is operating on an integer vector
3388 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
3389 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
3390 ISD::NodeType FPOp) {
3391 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
3392 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
3393 SDOperand LHS = N->getOperand(0);
3394 SDOperand RHS = N->getOperand(1);
3395 SDOperand Shuffle = XformToShuffleWithZero(N);
3396 if (Shuffle.Val) return Shuffle;
3398 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
3400 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
3401 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3402 SmallVector<SDOperand, 8> Ops;
3403 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
3404 SDOperand LHSOp = LHS.getOperand(i);
3405 SDOperand RHSOp = RHS.getOperand(i);
3406 // If these two elements can't be folded, bail out.
3407 if ((LHSOp.getOpcode() != ISD::UNDEF &&
3408 LHSOp.getOpcode() != ISD::Constant &&
3409 LHSOp.getOpcode() != ISD::ConstantFP) ||
3410 (RHSOp.getOpcode() != ISD::UNDEF &&
3411 RHSOp.getOpcode() != ISD::Constant &&
3412 RHSOp.getOpcode() != ISD::ConstantFP))
3414 // Can't fold divide by zero.
3415 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
3416 if ((RHSOp.getOpcode() == ISD::Constant &&
3417 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
3418 (RHSOp.getOpcode() == ISD::ConstantFP &&
3419 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
3422 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
3423 AddToWorkList(Ops.back().Val);
3424 assert((Ops.back().getOpcode() == ISD::UNDEF ||
3425 Ops.back().getOpcode() == ISD::Constant ||
3426 Ops.back().getOpcode() == ISD::ConstantFP) &&
3427 "Scalar binop didn't fold!");
3430 if (Ops.size() == LHS.getNumOperands()-2) {
3431 Ops.push_back(*(LHS.Val->op_end()-2));
3432 Ops.push_back(*(LHS.Val->op_end()-1));
3433 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
3440 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
3441 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
3443 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
3444 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3445 // If we got a simplified select_cc node back from SimplifySelectCC, then
3446 // break it down into a new SETCC node, and a new SELECT node, and then return
3447 // the SELECT node, since we were called with a SELECT node.
3449 // Check to see if we got a select_cc back (to turn into setcc/select).
3450 // Otherwise, just return whatever node we got back, like fabs.
3451 if (SCC.getOpcode() == ISD::SELECT_CC) {
3452 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
3453 SCC.getOperand(0), SCC.getOperand(1),
3455 AddToWorkList(SETCC.Val);
3456 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
3457 SCC.getOperand(3), SETCC);
3464 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
3465 /// are the two values being selected between, see if we can simplify the
3466 /// select. Callers of this should assume that TheSelect is deleted if this
3467 /// returns true. As such, they should return the appropriate thing (e.g. the
3468 /// node) back to the top-level of the DAG combiner loop to avoid it being
3471 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
3474 // If this is a select from two identical things, try to pull the operation
3475 // through the select.
3476 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
3477 // If this is a load and the token chain is identical, replace the select
3478 // of two loads with a load through a select of the address to load from.
3479 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3480 // constants have been dropped into the constant pool.
3481 if (LHS.getOpcode() == ISD::LOAD &&
3482 // Token chains must be identical.
3483 LHS.getOperand(0) == RHS.getOperand(0)) {
3484 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
3485 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
3487 // If this is an EXTLOAD, the VT's must match.
3488 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
3489 // FIXME: this conflates two src values, discarding one. This is not
3490 // the right thing to do, but nothing uses srcvalues now. When they do,
3491 // turn SrcValue into a list of locations.
3493 if (TheSelect->getOpcode() == ISD::SELECT)
3494 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
3495 TheSelect->getOperand(0), LLD->getBasePtr(),
3498 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
3499 TheSelect->getOperand(0),
3500 TheSelect->getOperand(1),
3501 LLD->getBasePtr(), RLD->getBasePtr(),
3502 TheSelect->getOperand(4));
3505 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
3506 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
3507 Addr,LLD->getSrcValue(), LLD->getSrcValueOffset());
3509 Load = DAG.getExtLoad(LLD->getExtensionType(),
3510 TheSelect->getValueType(0),
3511 LLD->getChain(), Addr, LLD->getSrcValue(),
3512 LLD->getSrcValueOffset(),
3513 LLD->getLoadedVT());
3515 // Users of the select now use the result of the load.
3516 CombineTo(TheSelect, Load);
3518 // Users of the old loads now use the new load's chain. We know the
3519 // old-load value is dead now.
3520 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
3521 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
3530 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
3531 SDOperand N2, SDOperand N3,
3534 MVT::ValueType VT = N2.getValueType();
3535 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
3536 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
3537 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
3539 // Determine if the condition we're dealing with is constant
3540 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
3541 if (SCC.Val) AddToWorkList(SCC.Val);
3542 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
3544 // fold select_cc true, x, y -> x
3545 if (SCCC && SCCC->getValue())
3547 // fold select_cc false, x, y -> y
3548 if (SCCC && SCCC->getValue() == 0)
3551 // Check to see if we can simplify the select into an fabs node
3552 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
3553 // Allow either -0.0 or 0.0
3554 if (CFP->getValue() == 0.0) {
3555 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
3556 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
3557 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
3558 N2 == N3.getOperand(0))
3559 return DAG.getNode(ISD::FABS, VT, N0);
3561 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
3562 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
3563 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
3564 N2.getOperand(0) == N3)
3565 return DAG.getNode(ISD::FABS, VT, N3);
3569 // Check to see if we can perform the "gzip trick", transforming
3570 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
3571 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
3572 MVT::isInteger(N0.getValueType()) &&
3573 MVT::isInteger(N2.getValueType()) &&
3574 (N1C->isNullValue() || // (a < 0) ? b : 0
3575 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
3576 MVT::ValueType XType = N0.getValueType();
3577 MVT::ValueType AType = N2.getValueType();
3578 if (XType >= AType) {
3579 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
3580 // single-bit constant.
3581 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
3582 unsigned ShCtV = Log2_64(N2C->getValue());
3583 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
3584 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
3585 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
3586 AddToWorkList(Shift.Val);
3587 if (XType > AType) {
3588 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3589 AddToWorkList(Shift.Val);
3591 return DAG.getNode(ISD::AND, AType, Shift, N2);
3593 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3594 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3595 TLI.getShiftAmountTy()));
3596 AddToWorkList(Shift.Val);
3597 if (XType > AType) {
3598 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3599 AddToWorkList(Shift.Val);
3601 return DAG.getNode(ISD::AND, AType, Shift, N2);
3605 // fold select C, 16, 0 -> shl C, 4
3606 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
3607 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
3608 // Get a SetCC of the condition
3609 // FIXME: Should probably make sure that setcc is legal if we ever have a
3610 // target where it isn't.
3611 SDOperand Temp, SCC;
3612 // cast from setcc result type to select result type
3613 if (AfterLegalize) {
3614 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3615 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
3617 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
3618 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3620 AddToWorkList(SCC.Val);
3621 AddToWorkList(Temp.Val);
3622 // shl setcc result by log2 n2c
3623 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
3624 DAG.getConstant(Log2_64(N2C->getValue()),
3625 TLI.getShiftAmountTy()));
3628 // Check to see if this is the equivalent of setcc
3629 // FIXME: Turn all of these into setcc if setcc if setcc is legal
3630 // otherwise, go ahead with the folds.
3631 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
3632 MVT::ValueType XType = N0.getValueType();
3633 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
3634 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3635 if (Res.getValueType() != VT)
3636 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
3640 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
3641 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
3642 TLI.isOperationLegal(ISD::CTLZ, XType)) {
3643 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
3644 return DAG.getNode(ISD::SRL, XType, Ctlz,
3645 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
3646 TLI.getShiftAmountTy()));
3648 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
3649 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
3650 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
3652 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
3653 DAG.getConstant(~0ULL, XType));
3654 return DAG.getNode(ISD::SRL, XType,
3655 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
3656 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3657 TLI.getShiftAmountTy()));
3659 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
3660 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
3661 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
3662 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3663 TLI.getShiftAmountTy()));
3664 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
3668 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
3669 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
3670 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
3671 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
3672 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
3673 MVT::ValueType XType = N0.getValueType();
3674 if (SubC->isNullValue() && MVT::isInteger(XType)) {
3675 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3676 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3677 TLI.getShiftAmountTy()));
3678 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
3679 AddToWorkList(Shift.Val);
3680 AddToWorkList(Add.Val);
3681 return DAG.getNode(ISD::XOR, XType, Add, Shift);
3689 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
3690 SDOperand N1, ISD::CondCode Cond,
3691 bool foldBooleans) {
3692 // These setcc operations always fold.
3696 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
3698 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
3701 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
3702 uint64_t C1 = N1C->getValue();
3703 if (isa<ConstantSDNode>(N0.Val)) {
3704 return DAG.FoldSetCC(VT, N0, N1, Cond);
3706 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
3707 // equality comparison, then we're just comparing whether X itself is
3709 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
3710 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
3711 N0.getOperand(1).getOpcode() == ISD::Constant) {
3712 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
3713 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3714 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
3715 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
3716 // (srl (ctlz x), 5) == 0 -> X != 0
3717 // (srl (ctlz x), 5) != 1 -> X != 0
3720 // (srl (ctlz x), 5) != 0 -> X == 0
3721 // (srl (ctlz x), 5) == 1 -> X == 0
3724 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
3725 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
3730 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3731 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3732 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
3734 // If the comparison constant has bits in the upper part, the
3735 // zero-extended value could never match.
3736 if (C1 & (~0ULL << InSize)) {
3737 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
3741 case ISD::SETEQ: return DAG.getConstant(0, VT);
3744 case ISD::SETNE: return DAG.getConstant(1, VT);
3747 // True if the sign bit of C1 is set.
3748 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
3751 // True if the sign bit of C1 isn't set.
3752 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
3758 // Otherwise, we can perform the comparison with the low bits.
3766 return DAG.getSetCC(VT, N0.getOperand(0),
3767 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
3770 break; // todo, be more careful with signed comparisons
3772 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3773 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3774 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3775 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
3776 MVT::ValueType ExtDstTy = N0.getValueType();
3777 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
3779 // If the extended part has any inconsistent bits, it cannot ever
3780 // compare equal. In other words, they have to be all ones or all
3783 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
3784 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
3785 return DAG.getConstant(Cond == ISD::SETNE, VT);
3788 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
3789 if (Op0Ty == ExtSrcTy) {
3790 ZextOp = N0.getOperand(0);
3792 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
3793 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
3794 DAG.getConstant(Imm, Op0Ty));
3796 AddToWorkList(ZextOp.Val);
3797 // Otherwise, make this a use of a zext.
3798 return DAG.getSetCC(VT, ZextOp,
3799 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
3802 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
3803 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3805 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
3806 if (N0.getOpcode() == ISD::SETCC) {
3807 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1);
3811 // Invert the condition.
3812 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
3813 CC = ISD::getSetCCInverse(CC,
3814 MVT::isInteger(N0.getOperand(0).getValueType()));
3815 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
3818 if ((N0.getOpcode() == ISD::XOR ||
3819 (N0.getOpcode() == ISD::AND &&
3820 N0.getOperand(0).getOpcode() == ISD::XOR &&
3821 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3822 isa<ConstantSDNode>(N0.getOperand(1)) &&
3823 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
3824 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
3825 // can only do this if the top bits are known zero.
3826 if (TLI.MaskedValueIsZero(N0,
3827 MVT::getIntVTBitMask(N0.getValueType())-1)){
3828 // Okay, get the un-inverted input value.
3830 if (N0.getOpcode() == ISD::XOR)
3831 Val = N0.getOperand(0);
3833 assert(N0.getOpcode() == ISD::AND &&
3834 N0.getOperand(0).getOpcode() == ISD::XOR);
3835 // ((X^1)&1)^1 -> X & 1
3836 Val = DAG.getNode(ISD::AND, N0.getValueType(),
3837 N0.getOperand(0).getOperand(0),
3840 return DAG.getSetCC(VT, Val, N1,
3841 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3846 uint64_t MinVal, MaxVal;
3847 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
3848 if (ISD::isSignedIntSetCC(Cond)) {
3849 MinVal = 1ULL << (OperandBitSize-1);
3850 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
3851 MaxVal = ~0ULL >> (65-OperandBitSize);
3856 MaxVal = ~0ULL >> (64-OperandBitSize);
3859 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
3860 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3861 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
3862 --C1; // X >= C0 --> X > (C0-1)
3863 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3864 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
3867 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
3868 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
3869 ++C1; // X <= C0 --> X < (C0+1)
3870 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3871 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
3874 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
3875 return DAG.getConstant(0, VT); // X < MIN --> false
3877 // Canonicalize setgt X, Min --> setne X, Min
3878 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
3879 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3880 // Canonicalize setlt X, Max --> setne X, Max
3881 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
3882 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3884 // If we have setult X, 1, turn it into seteq X, 0
3885 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
3886 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
3888 // If we have setugt X, Max-1, turn it into seteq X, Max
3889 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
3890 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
3893 // If we have "setcc X, C0", check to see if we can shrink the immediate
3896 // SETUGT X, SINTMAX -> SETLT X, 0
3897 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
3898 C1 == (~0ULL >> (65-OperandBitSize)))
3899 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
3902 // FIXME: Implement the rest of these.
3904 // Fold bit comparisons when we can.
3905 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3906 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
3907 if (ConstantSDNode *AndRHS =
3908 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3909 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
3910 // Perform the xform if the AND RHS is a single bit.
3911 if (isPowerOf2_64(AndRHS->getValue())) {
3912 return DAG.getNode(ISD::SRL, VT, N0,
3913 DAG.getConstant(Log2_64(AndRHS->getValue()),
3914 TLI.getShiftAmountTy()));
3916 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
3917 // (X & 8) == 8 --> (X & 8) >> 3
3918 // Perform the xform if C1 is a single bit.
3919 if (isPowerOf2_64(C1)) {
3920 return DAG.getNode(ISD::SRL, VT, N0,
3921 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
3926 } else if (isa<ConstantSDNode>(N0.Val)) {
3927 // Ensure that the constant occurs on the RHS.
3928 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3931 if (isa<ConstantFPSDNode>(N0.Val)) {
3932 // Constant fold or commute setcc.
3933 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
3934 if (O.Val) return O;
3938 // We can always fold X == X for integer setcc's.
3939 if (MVT::isInteger(N0.getValueType()))
3940 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3941 unsigned UOF = ISD::getUnorderedFlavor(Cond);
3942 if (UOF == 2) // FP operators that are undefined on NaNs.
3943 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3944 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
3945 return DAG.getConstant(UOF, VT);
3946 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
3947 // if it is not already.
3948 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
3949 if (NewCond != Cond)
3950 return DAG.getSetCC(VT, N0, N1, NewCond);
3953 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3954 MVT::isInteger(N0.getValueType())) {
3955 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3956 N0.getOpcode() == ISD::XOR) {
3957 // Simplify (X+Y) == (X+Z) --> Y == Z
3958 if (N0.getOpcode() == N1.getOpcode()) {
3959 if (N0.getOperand(0) == N1.getOperand(0))
3960 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
3961 if (N0.getOperand(1) == N1.getOperand(1))
3962 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
3963 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
3964 // If X op Y == Y op X, try other combinations.
3965 if (N0.getOperand(0) == N1.getOperand(1))
3966 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
3967 if (N0.getOperand(1) == N1.getOperand(0))
3968 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
3972 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
3973 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3974 // Turn (X+C1) == C2 --> X == C2-C1
3975 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
3976 return DAG.getSetCC(VT, N0.getOperand(0),
3977 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
3978 N0.getValueType()), Cond);
3981 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
3982 if (N0.getOpcode() == ISD::XOR)
3983 // If we know that all of the inverted bits are zero, don't bother
3984 // performing the inversion.
3985 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
3986 return DAG.getSetCC(VT, N0.getOperand(0),
3987 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
3988 N0.getValueType()), Cond);
3991 // Turn (C1-X) == C2 --> X == C1-C2
3992 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
3993 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
3994 return DAG.getSetCC(VT, N0.getOperand(1),
3995 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
3996 N0.getValueType()), Cond);
4001 // Simplify (X+Z) == X --> Z == 0
4002 if (N0.getOperand(0) == N1)
4003 return DAG.getSetCC(VT, N0.getOperand(1),
4004 DAG.getConstant(0, N0.getValueType()), Cond);
4005 if (N0.getOperand(1) == N1) {
4006 if (DAG.isCommutativeBinOp(N0.getOpcode()))
4007 return DAG.getSetCC(VT, N0.getOperand(0),
4008 DAG.getConstant(0, N0.getValueType()), Cond);
4010 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
4011 // (Z-X) == X --> Z == X<<1
4012 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
4014 DAG.getConstant(1,TLI.getShiftAmountTy()));
4015 AddToWorkList(SH.Val);
4016 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
4021 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
4022 N1.getOpcode() == ISD::XOR) {
4023 // Simplify X == (X+Z) --> Z == 0
4024 if (N1.getOperand(0) == N0) {
4025 return DAG.getSetCC(VT, N1.getOperand(1),
4026 DAG.getConstant(0, N1.getValueType()), Cond);
4027 } else if (N1.getOperand(1) == N0) {
4028 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
4029 return DAG.getSetCC(VT, N1.getOperand(0),
4030 DAG.getConstant(0, N1.getValueType()), Cond);
4032 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
4033 // X == (Z-X) --> X<<1 == Z
4034 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
4035 DAG.getConstant(1,TLI.getShiftAmountTy()));
4036 AddToWorkList(SH.Val);
4037 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
4043 // Fold away ALL boolean setcc's.
4045 if (N0.getValueType() == MVT::i1 && foldBooleans) {
4047 default: assert(0 && "Unknown integer setcc!");
4048 case ISD::SETEQ: // X == Y -> (X^Y)^1
4049 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
4050 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
4051 AddToWorkList(Temp.Val);
4053 case ISD::SETNE: // X != Y --> (X^Y)
4054 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
4056 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
4057 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
4058 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
4059 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
4060 AddToWorkList(Temp.Val);
4062 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
4063 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
4064 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
4065 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
4066 AddToWorkList(Temp.Val);
4068 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
4069 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
4070 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
4071 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
4072 AddToWorkList(Temp.Val);
4074 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
4075 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
4076 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
4077 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
4080 if (VT != MVT::i1) {
4081 AddToWorkList(N0.Val);
4082 // FIXME: If running after legalize, we probably can't do this.
4083 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
4088 // Could not fold it.
4092 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
4093 /// return a DAG expression to select that will generate the same value by
4094 /// multiplying by a magic number. See:
4095 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4096 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
4097 std::vector<SDNode*> Built;
4098 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
4100 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4106 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
4107 /// return a DAG expression to select that will generate the same value by
4108 /// multiplying by a magic number. See:
4109 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4110 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
4111 std::vector<SDNode*> Built;
4112 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
4114 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4120 /// FindBaseOffset - Return true if base is known not to alias with anything
4121 /// but itself. Provides base object and offset as results.
4122 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4123 // Assume it is a primitive operation.
4124 Base = Ptr; Offset = 0;
4126 // If it's an adding a simple constant then integrate the offset.
4127 if (Base.getOpcode() == ISD::ADD) {
4128 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4129 Base = Base.getOperand(0);
4130 Offset += C->getValue();
4134 // If it's any of the following then it can't alias with anything but itself.
4135 return isa<FrameIndexSDNode>(Base) ||
4136 isa<ConstantPoolSDNode>(Base) ||
4137 isa<GlobalAddressSDNode>(Base);
4140 /// isAlias - Return true if there is any possibility that the two addresses
4142 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4143 const Value *SrcValue1, int SrcValueOffset1,
4144 SDOperand Ptr2, int64_t Size2,
4145 const Value *SrcValue2, int SrcValueOffset2)
4147 // If they are the same then they must be aliases.
4148 if (Ptr1 == Ptr2) return true;
4150 // Gather base node and offset information.
4151 SDOperand Base1, Base2;
4152 int64_t Offset1, Offset2;
4153 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4154 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4156 // If they have a same base address then...
4157 if (Base1 == Base2) {
4158 // Check to see if the addresses overlap.
4159 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4162 // If we know both bases then they can't alias.
4163 if (KnownBase1 && KnownBase2) return false;
4165 if (CombinerGlobalAA) {
4166 // Use alias analysis information.
4167 int Overlap1 = Size1 + SrcValueOffset1 + Offset1;
4168 int Overlap2 = Size2 + SrcValueOffset2 + Offset2;
4169 AliasAnalysis::AliasResult AAResult =
4170 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
4171 if (AAResult == AliasAnalysis::NoAlias)
4175 // Otherwise we have to assume they alias.
4179 /// FindAliasInfo - Extracts the relevant alias information from the memory
4180 /// node. Returns true if the operand was a load.
4181 bool DAGCombiner::FindAliasInfo(SDNode *N,
4182 SDOperand &Ptr, int64_t &Size,
4183 const Value *&SrcValue, int &SrcValueOffset) {
4184 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4185 Ptr = LD->getBasePtr();
4186 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4187 SrcValue = LD->getSrcValue();
4188 SrcValueOffset = LD->getSrcValueOffset();
4190 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4191 Ptr = ST->getBasePtr();
4192 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4193 SrcValue = ST->getSrcValue();
4194 SrcValueOffset = ST->getSrcValueOffset();
4196 assert(0 && "FindAliasInfo expected a memory operand");
4202 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4203 /// looking for aliasing nodes and adding them to the Aliases vector.
4204 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4205 SmallVector<SDOperand, 8> &Aliases) {
4206 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4207 std::set<SDNode *> Visited; // Visited node set.
4209 // Get alias information for node.
4212 const Value *SrcValue;
4214 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
4217 Chains.push_back(OriginalChain);
4219 // Look at each chain and determine if it is an alias. If so, add it to the
4220 // aliases list. If not, then continue up the chain looking for the next
4222 while (!Chains.empty()) {
4223 SDOperand Chain = Chains.back();
4226 // Don't bother if we've been before.
4227 if (Visited.find(Chain.Val) != Visited.end()) continue;
4228 Visited.insert(Chain.Val);
4230 switch (Chain.getOpcode()) {
4231 case ISD::EntryToken:
4232 // Entry token is ideal chain operand, but handled in FindBetterChain.
4237 // Get alias information for Chain.
4240 const Value *OpSrcValue;
4241 int OpSrcValueOffset;
4242 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
4243 OpSrcValue, OpSrcValueOffset);
4245 // If chain is alias then stop here.
4246 if (!(IsLoad && IsOpLoad) &&
4247 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
4248 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
4249 Aliases.push_back(Chain);
4251 // Look further up the chain.
4252 Chains.push_back(Chain.getOperand(0));
4253 // Clean up old chain.
4254 AddToWorkList(Chain.Val);
4259 case ISD::TokenFactor:
4260 // We have to check each of the operands of the token factor, so we queue
4261 // then up. Adding the operands to the queue (stack) in reverse order
4262 // maintains the original order and increases the likelihood that getNode
4263 // will find a matching token factor (CSE.)
4264 for (unsigned n = Chain.getNumOperands(); n;)
4265 Chains.push_back(Chain.getOperand(--n));
4266 // Eliminate the token factor if we can.
4267 AddToWorkList(Chain.Val);
4271 // For all other instructions we will just have to take what we can get.
4272 Aliases.push_back(Chain);
4278 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4279 /// for a better chain (aliasing node.)
4280 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4281 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4283 // Accumulate all the aliases to this node.
4284 GatherAllAliases(N, OldChain, Aliases);
4286 if (Aliases.size() == 0) {
4287 // If no operands then chain to entry token.
4288 return DAG.getEntryNode();
4289 } else if (Aliases.size() == 1) {
4290 // If a single operand then chain to it. We don't need to revisit it.
4294 // Construct a custom tailored token factor.
4295 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4296 &Aliases[0], Aliases.size());
4298 // Make sure the old chain gets cleaned up.
4299 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4304 // SelectionDAG::Combine - This is the entry point for the file.
4306 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
4307 /// run - This is the main entry point to this class.
4309 DAGCombiner(*this, AA).Run(RunningAfterLegalize);