1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/DataLayout.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
40 STATISTIC(NodesCombined , "Number of dag nodes combined");
41 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
42 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
43 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
44 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
48 CombinerAA("combiner-alias-analysis", cl::Hidden,
49 cl::desc("Turn on alias analysis during testing"));
52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
53 cl::desc("Include global information in alias analysis"));
55 //------------------------------ DAGCombiner ---------------------------------//
59 const TargetLowering &TLI;
61 CodeGenOpt::Level OptLevel;
65 // Worklist of all of the nodes that need to be simplified.
67 // This has the semantics that when adding to the worklist,
68 // the item added must be next to be processed. It should
69 // also only appear once. The naive approach to this takes
72 // To reduce the insert/remove time to logarithmic, we use
73 // a set and a vector to maintain our worklist.
75 // The set contains the items on the worklist, but does not
76 // maintain the order they should be visited.
78 // The vector maintains the order nodes should be visited, but may
79 // contain duplicate or removed nodes. When choosing a node to
80 // visit, we pop off the order stack until we find an item that is
81 // also in the contents set. All operations are O(log N).
82 SmallPtrSet<SDNode*, 64> WorkListContents;
83 SmallVector<SDNode*, 64> WorkListOrder;
85 // AA - Used for DAG load/store alias analysis.
88 /// AddUsersToWorkList - When an instruction is simplified, add all users of
89 /// the instruction to the work lists because they might get more simplified
92 void AddUsersToWorkList(SDNode *N) {
93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
98 /// visit - call the node-specific routine that knows how to fold each
99 /// particular type of node.
100 SDValue visit(SDNode *N);
103 /// AddToWorkList - Add to the work list making sure its instance is at the
104 /// back (next to be processed.)
105 void AddToWorkList(SDNode *N) {
106 WorkListContents.insert(N);
107 WorkListOrder.push_back(N);
110 /// removeFromWorkList - remove all instances of N from the worklist.
112 void removeFromWorkList(SDNode *N) {
113 WorkListContents.erase(N);
116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
120 return CombineTo(N, &Res, 1, AddTo);
123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
125 SDValue To[] = { Res0, Res1 };
126 return CombineTo(N, To, 2, AddTo);
129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
133 /// SimplifyDemandedBits - Check the specified integer node value to see if
134 /// it can be simplified or if things it uses can be simplified by bit
135 /// propagation. If so, return true.
136 bool SimplifyDemandedBits(SDValue Op) {
137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
138 APInt Demanded = APInt::getAllOnesValue(BitWidth);
139 return SimplifyDemandedBits(Op, Demanded);
142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
144 bool CombineToPreIndexedLoadStore(SDNode *N);
145 bool CombineToPostIndexedLoadStore(SDNode *N);
147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
151 SDValue PromoteIntBinOp(SDValue Op);
152 SDValue PromoteIntShiftOp(SDValue Op);
153 SDValue PromoteExtend(SDValue Op);
154 bool PromoteLoad(SDValue Op);
156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
158 ISD::NodeType ExtType);
160 /// combine - call the node-specific routine that knows how to fold each
161 /// particular type of node. If that doesn't do anything, try the
162 /// target-specific DAG combines.
163 SDValue combine(SDNode *N);
165 // Visitation implementation - Implement dag node combining for different
166 // node types. The semantics are as follows:
168 // SDValue.getNode() == 0 - No change was made
169 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
170 // otherwise - N should be replaced by the returned Operand.
172 SDValue visitTokenFactor(SDNode *N);
173 SDValue visitMERGE_VALUES(SDNode *N);
174 SDValue visitADD(SDNode *N);
175 SDValue visitSUB(SDNode *N);
176 SDValue visitADDC(SDNode *N);
177 SDValue visitSUBC(SDNode *N);
178 SDValue visitADDE(SDNode *N);
179 SDValue visitSUBE(SDNode *N);
180 SDValue visitMUL(SDNode *N);
181 SDValue visitSDIV(SDNode *N);
182 SDValue visitUDIV(SDNode *N);
183 SDValue visitSREM(SDNode *N);
184 SDValue visitUREM(SDNode *N);
185 SDValue visitMULHU(SDNode *N);
186 SDValue visitMULHS(SDNode *N);
187 SDValue visitSMUL_LOHI(SDNode *N);
188 SDValue visitUMUL_LOHI(SDNode *N);
189 SDValue visitSMULO(SDNode *N);
190 SDValue visitUMULO(SDNode *N);
191 SDValue visitSDIVREM(SDNode *N);
192 SDValue visitUDIVREM(SDNode *N);
193 SDValue visitAND(SDNode *N);
194 SDValue visitOR(SDNode *N);
195 SDValue visitXOR(SDNode *N);
196 SDValue SimplifyVBinOp(SDNode *N);
197 SDValue SimplifyVUnaryOp(SDNode *N);
198 SDValue visitSHL(SDNode *N);
199 SDValue visitSRA(SDNode *N);
200 SDValue visitSRL(SDNode *N);
201 SDValue visitCTLZ(SDNode *N);
202 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
203 SDValue visitCTTZ(SDNode *N);
204 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
205 SDValue visitCTPOP(SDNode *N);
206 SDValue visitSELECT(SDNode *N);
207 SDValue visitSELECT_CC(SDNode *N);
208 SDValue visitSETCC(SDNode *N);
209 SDValue visitSIGN_EXTEND(SDNode *N);
210 SDValue visitZERO_EXTEND(SDNode *N);
211 SDValue visitANY_EXTEND(SDNode *N);
212 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
213 SDValue visitTRUNCATE(SDNode *N);
214 SDValue visitBITCAST(SDNode *N);
215 SDValue visitBUILD_PAIR(SDNode *N);
216 SDValue visitFADD(SDNode *N);
217 SDValue visitFSUB(SDNode *N);
218 SDValue visitFMUL(SDNode *N);
219 SDValue visitFMA(SDNode *N);
220 SDValue visitFDIV(SDNode *N);
221 SDValue visitFREM(SDNode *N);
222 SDValue visitFCOPYSIGN(SDNode *N);
223 SDValue visitSINT_TO_FP(SDNode *N);
224 SDValue visitUINT_TO_FP(SDNode *N);
225 SDValue visitFP_TO_SINT(SDNode *N);
226 SDValue visitFP_TO_UINT(SDNode *N);
227 SDValue visitFP_ROUND(SDNode *N);
228 SDValue visitFP_ROUND_INREG(SDNode *N);
229 SDValue visitFP_EXTEND(SDNode *N);
230 SDValue visitFNEG(SDNode *N);
231 SDValue visitFABS(SDNode *N);
232 SDValue visitFCEIL(SDNode *N);
233 SDValue visitFTRUNC(SDNode *N);
234 SDValue visitFFLOOR(SDNode *N);
235 SDValue visitBRCOND(SDNode *N);
236 SDValue visitBR_CC(SDNode *N);
237 SDValue visitLOAD(SDNode *N);
238 SDValue visitSTORE(SDNode *N);
239 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
240 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
241 SDValue visitBUILD_VECTOR(SDNode *N);
242 SDValue visitCONCAT_VECTORS(SDNode *N);
243 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
244 SDValue visitVECTOR_SHUFFLE(SDNode *N);
245 SDValue visitMEMBARRIER(SDNode *N);
247 SDValue XformToShuffleWithZero(SDNode *N);
248 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
250 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
252 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
253 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
254 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
255 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
256 SDValue N3, ISD::CondCode CC,
257 bool NotExtCompare = false);
258 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
259 DebugLoc DL, bool foldBooleans = true);
260 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
262 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
263 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
264 SDValue BuildSDIV(SDNode *N);
265 SDValue BuildUDIV(SDNode *N);
266 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
267 bool DemandHighBits = true);
268 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
269 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
270 SDValue ReduceLoadWidth(SDNode *N);
271 SDValue ReduceLoadOpStoreWidth(SDNode *N);
272 SDValue TransformFPLoadStorePair(SDNode *N);
273 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
274 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N);
276 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
278 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
279 /// looking for aliasing nodes and adding them to the Aliases vector.
280 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
281 SmallVector<SDValue, 8> &Aliases);
283 /// isAlias - Return true if there is any possibility that the two addresses
285 bool isAlias(SDValue Ptr1, int64_t Size1,
286 const Value *SrcValue1, int SrcValueOffset1,
287 unsigned SrcValueAlign1,
288 const MDNode *TBAAInfo1,
289 SDValue Ptr2, int64_t Size2,
290 const Value *SrcValue2, int SrcValueOffset2,
291 unsigned SrcValueAlign2,
292 const MDNode *TBAAInfo2) const;
294 /// isAlias - Return true if there is any possibility that the two addresses
296 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1);
298 /// FindAliasInfo - Extracts the relevant alias information from the memory
299 /// node. Returns true if the operand was a load.
300 bool FindAliasInfo(SDNode *N,
301 SDValue &Ptr, int64_t &Size,
302 const Value *&SrcValue, int &SrcValueOffset,
303 unsigned &SrcValueAlignment,
304 const MDNode *&TBAAInfo) const;
306 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
307 /// looking for a better chain (aliasing node.)
308 SDValue FindBetterChain(SDNode *N, SDValue Chain);
310 /// Merge consecutive store operations into a wide store.
311 /// This optimization uses wide integers or vectors when possible.
312 /// \return True if some memory operations were changed.
313 bool MergeConsecutiveStores(StoreSDNode *N);
316 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
317 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
318 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
320 /// Run - runs the dag combiner on all nodes in the work list
321 void Run(CombineLevel AtLevel);
323 SelectionDAG &getDAG() const { return DAG; }
325 /// getShiftAmountTy - Returns a type large enough to hold any valid
326 /// shift amount - before type legalization these can be huge.
327 EVT getShiftAmountTy(EVT LHSTy) {
328 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
331 /// isTypeLegal - This method returns true if we are running before type
332 /// legalization or if the specified VT is legal.
333 bool isTypeLegal(const EVT &VT) {
334 if (!LegalTypes) return true;
335 return TLI.isTypeLegal(VT);
342 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
343 /// nodes from the worklist.
344 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
347 explicit WorkListRemover(DAGCombiner &dc)
348 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
350 virtual void NodeDeleted(SDNode *N, SDNode *E) {
351 DC.removeFromWorkList(N);
356 //===----------------------------------------------------------------------===//
357 // TargetLowering::DAGCombinerInfo implementation
358 //===----------------------------------------------------------------------===//
360 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
361 ((DAGCombiner*)DC)->AddToWorkList(N);
364 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
365 ((DAGCombiner*)DC)->removeFromWorkList(N);
368 SDValue TargetLowering::DAGCombinerInfo::
369 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
370 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
373 SDValue TargetLowering::DAGCombinerInfo::
374 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
375 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
379 SDValue TargetLowering::DAGCombinerInfo::
380 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
381 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
384 void TargetLowering::DAGCombinerInfo::
385 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
386 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
389 //===----------------------------------------------------------------------===//
391 //===----------------------------------------------------------------------===//
393 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
394 /// specified expression for the same cost as the expression itself, or 2 if we
395 /// can compute the negated form more cheaply than the expression itself.
396 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
397 const TargetLowering &TLI,
398 const TargetOptions *Options,
399 unsigned Depth = 0) {
400 // fneg is removable even if it has multiple uses.
401 if (Op.getOpcode() == ISD::FNEG) return 2;
403 // Don't allow anything with multiple uses.
404 if (!Op.hasOneUse()) return 0;
406 // Don't recurse exponentially.
407 if (Depth > 6) return 0;
409 switch (Op.getOpcode()) {
410 default: return false;
411 case ISD::ConstantFP:
412 // Don't invert constant FP values after legalize. The negated constant
413 // isn't necessarily legal.
414 return LegalOperations ? 0 : 1;
416 // FIXME: determine better conditions for this xform.
417 if (!Options->UnsafeFPMath) return 0;
419 // After operation legalization, it might not be legal to create new FSUBs.
420 if (LegalOperations &&
421 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
424 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
425 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
428 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
429 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
432 // We can't turn -(A-B) into B-A when we honor signed zeros.
433 if (!Options->UnsafeFPMath) return 0;
435 // fold (fneg (fsub A, B)) -> (fsub B, A)
440 if (Options->HonorSignDependentRoundingFPMath()) return 0;
442 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
443 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
447 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
453 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
458 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
459 /// returns the newly negated expression.
460 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
461 bool LegalOperations, unsigned Depth = 0) {
462 // fneg is removable even if it has multiple uses.
463 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
465 // Don't allow anything with multiple uses.
466 assert(Op.hasOneUse() && "Unknown reuse!");
468 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
469 switch (Op.getOpcode()) {
470 default: llvm_unreachable("Unknown code");
471 case ISD::ConstantFP: {
472 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
474 return DAG.getConstantFP(V, Op.getValueType());
477 // FIXME: determine better conditions for this xform.
478 assert(DAG.getTarget().Options.UnsafeFPMath);
480 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
481 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
482 DAG.getTargetLoweringInfo(),
483 &DAG.getTarget().Options, Depth+1))
484 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
485 GetNegatedExpression(Op.getOperand(0), DAG,
486 LegalOperations, Depth+1),
488 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
489 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
490 GetNegatedExpression(Op.getOperand(1), DAG,
491 LegalOperations, Depth+1),
494 // We can't turn -(A-B) into B-A when we honor signed zeros.
495 assert(DAG.getTarget().Options.UnsafeFPMath);
497 // fold (fneg (fsub 0, B)) -> B
498 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
499 if (N0CFP->getValueAPF().isZero())
500 return Op.getOperand(1);
502 // fold (fneg (fsub A, B)) -> (fsub B, A)
503 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
504 Op.getOperand(1), Op.getOperand(0));
508 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath());
510 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
511 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
512 DAG.getTargetLoweringInfo(),
513 &DAG.getTarget().Options, Depth+1))
514 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
515 GetNegatedExpression(Op.getOperand(0), DAG,
516 LegalOperations, Depth+1),
519 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
520 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
522 GetNegatedExpression(Op.getOperand(1), DAG,
523 LegalOperations, Depth+1));
527 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
528 GetNegatedExpression(Op.getOperand(0), DAG,
529 LegalOperations, Depth+1));
531 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
532 GetNegatedExpression(Op.getOperand(0), DAG,
533 LegalOperations, Depth+1),
539 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
540 // that selects between the values 1 and 0, making it equivalent to a setcc.
541 // Also, set the incoming LHS, RHS, and CC references to the appropriate
542 // nodes based on the type of node we are checking. This simplifies life a
543 // bit for the callers.
544 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
546 if (N.getOpcode() == ISD::SETCC) {
547 LHS = N.getOperand(0);
548 RHS = N.getOperand(1);
549 CC = N.getOperand(2);
552 if (N.getOpcode() == ISD::SELECT_CC &&
553 N.getOperand(2).getOpcode() == ISD::Constant &&
554 N.getOperand(3).getOpcode() == ISD::Constant &&
555 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
556 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
557 LHS = N.getOperand(0);
558 RHS = N.getOperand(1);
559 CC = N.getOperand(4);
565 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
566 // one use. If this is true, it allows the users to invert the operation for
567 // free when it is profitable to do so.
568 static bool isOneUseSetCC(SDValue N) {
570 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
575 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
576 SDValue N0, SDValue N1) {
577 EVT VT = N0.getValueType();
578 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
579 if (isa<ConstantSDNode>(N1)) {
580 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
582 DAG.FoldConstantArithmetic(Opc, VT,
583 cast<ConstantSDNode>(N0.getOperand(1)),
584 cast<ConstantSDNode>(N1));
585 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
587 if (N0.hasOneUse()) {
588 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
589 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
590 N0.getOperand(0), N1);
591 AddToWorkList(OpNode.getNode());
592 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
596 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
597 if (isa<ConstantSDNode>(N0)) {
598 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
600 DAG.FoldConstantArithmetic(Opc, VT,
601 cast<ConstantSDNode>(N1.getOperand(1)),
602 cast<ConstantSDNode>(N0));
603 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
605 if (N1.hasOneUse()) {
606 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
607 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
608 N1.getOperand(0), N0);
609 AddToWorkList(OpNode.getNode());
610 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
617 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
619 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
621 DEBUG(dbgs() << "\nReplacing.1 ";
623 dbgs() << "\nWith: ";
624 To[0].getNode()->dump(&DAG);
625 dbgs() << " and " << NumTo-1 << " other values\n";
626 for (unsigned i = 0, e = NumTo; i != e; ++i)
627 assert((!To[i].getNode() ||
628 N->getValueType(i) == To[i].getValueType()) &&
629 "Cannot combine value to value of different type!"));
630 WorkListRemover DeadNodes(*this);
631 DAG.ReplaceAllUsesWith(N, To);
633 // Push the new nodes and any users onto the worklist
634 for (unsigned i = 0, e = NumTo; i != e; ++i) {
635 if (To[i].getNode()) {
636 AddToWorkList(To[i].getNode());
637 AddUsersToWorkList(To[i].getNode());
642 // Finally, if the node is now dead, remove it from the graph. The node
643 // may not be dead if the replacement process recursively simplified to
644 // something else needing this node.
645 if (N->use_empty()) {
646 // Nodes can be reintroduced into the worklist. Make sure we do not
647 // process a node that has been replaced.
648 removeFromWorkList(N);
650 // Finally, since the node is now dead, remove it from the graph.
653 return SDValue(N, 0);
657 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
658 // Replace all uses. If any nodes become isomorphic to other nodes and
659 // are deleted, make sure to remove them from our worklist.
660 WorkListRemover DeadNodes(*this);
661 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
663 // Push the new node and any (possibly new) users onto the worklist.
664 AddToWorkList(TLO.New.getNode());
665 AddUsersToWorkList(TLO.New.getNode());
667 // Finally, if the node is now dead, remove it from the graph. The node
668 // may not be dead if the replacement process recursively simplified to
669 // something else needing this node.
670 if (TLO.Old.getNode()->use_empty()) {
671 removeFromWorkList(TLO.Old.getNode());
673 // If the operands of this node are only used by the node, they will now
674 // be dead. Make sure to visit them first to delete dead nodes early.
675 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
676 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
677 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
679 DAG.DeleteNode(TLO.Old.getNode());
683 /// SimplifyDemandedBits - Check the specified integer node value to see if
684 /// it can be simplified or if things it uses can be simplified by bit
685 /// propagation. If so, return true.
686 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
687 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
688 APInt KnownZero, KnownOne;
689 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
693 AddToWorkList(Op.getNode());
695 // Replace the old value with the new one.
697 DEBUG(dbgs() << "\nReplacing.2 ";
698 TLO.Old.getNode()->dump(&DAG);
699 dbgs() << "\nWith: ";
700 TLO.New.getNode()->dump(&DAG);
703 CommitTargetLoweringOpt(TLO);
707 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
708 DebugLoc dl = Load->getDebugLoc();
709 EVT VT = Load->getValueType(0);
710 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
712 DEBUG(dbgs() << "\nReplacing.9 ";
714 dbgs() << "\nWith: ";
715 Trunc.getNode()->dump(&DAG);
717 WorkListRemover DeadNodes(*this);
718 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
719 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
720 removeFromWorkList(Load);
721 DAG.DeleteNode(Load);
722 AddToWorkList(Trunc.getNode());
725 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
727 DebugLoc dl = Op.getDebugLoc();
728 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
729 EVT MemVT = LD->getMemoryVT();
730 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
731 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
733 : LD->getExtensionType();
735 return DAG.getExtLoad(ExtType, dl, PVT,
736 LD->getChain(), LD->getBasePtr(),
737 LD->getPointerInfo(),
738 MemVT, LD->isVolatile(),
739 LD->isNonTemporal(), LD->getAlignment());
742 unsigned Opc = Op.getOpcode();
745 case ISD::AssertSext:
746 return DAG.getNode(ISD::AssertSext, dl, PVT,
747 SExtPromoteOperand(Op.getOperand(0), PVT),
749 case ISD::AssertZext:
750 return DAG.getNode(ISD::AssertZext, dl, PVT,
751 ZExtPromoteOperand(Op.getOperand(0), PVT),
753 case ISD::Constant: {
755 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
756 return DAG.getNode(ExtOpc, dl, PVT, Op);
760 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
762 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
765 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
766 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
768 EVT OldVT = Op.getValueType();
769 DebugLoc dl = Op.getDebugLoc();
770 bool Replace = false;
771 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
772 if (NewOp.getNode() == 0)
774 AddToWorkList(NewOp.getNode());
777 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
778 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
779 DAG.getValueType(OldVT));
782 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
783 EVT OldVT = Op.getValueType();
784 DebugLoc dl = Op.getDebugLoc();
785 bool Replace = false;
786 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
787 if (NewOp.getNode() == 0)
789 AddToWorkList(NewOp.getNode());
792 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
793 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
796 /// PromoteIntBinOp - Promote the specified integer binary operation if the
797 /// target indicates it is beneficial. e.g. On x86, it's usually better to
798 /// promote i16 operations to i32 since i16 instructions are longer.
799 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
800 if (!LegalOperations)
803 EVT VT = Op.getValueType();
804 if (VT.isVector() || !VT.isInteger())
807 // If operation type is 'undesirable', e.g. i16 on x86, consider
809 unsigned Opc = Op.getOpcode();
810 if (TLI.isTypeDesirableForOp(Opc, VT))
814 // Consult target whether it is a good idea to promote this operation and
815 // what's the right type to promote it to.
816 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
817 assert(PVT != VT && "Don't know what type to promote to!");
819 bool Replace0 = false;
820 SDValue N0 = Op.getOperand(0);
821 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
822 if (NN0.getNode() == 0)
825 bool Replace1 = false;
826 SDValue N1 = Op.getOperand(1);
831 NN1 = PromoteOperand(N1, PVT, Replace1);
832 if (NN1.getNode() == 0)
836 AddToWorkList(NN0.getNode());
838 AddToWorkList(NN1.getNode());
841 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
843 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
845 DEBUG(dbgs() << "\nPromoting ";
846 Op.getNode()->dump(&DAG));
847 DebugLoc dl = Op.getDebugLoc();
848 return DAG.getNode(ISD::TRUNCATE, dl, VT,
849 DAG.getNode(Opc, dl, PVT, NN0, NN1));
854 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
855 /// target indicates it is beneficial. e.g. On x86, it's usually better to
856 /// promote i16 operations to i32 since i16 instructions are longer.
857 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
858 if (!LegalOperations)
861 EVT VT = Op.getValueType();
862 if (VT.isVector() || !VT.isInteger())
865 // If operation type is 'undesirable', e.g. i16 on x86, consider
867 unsigned Opc = Op.getOpcode();
868 if (TLI.isTypeDesirableForOp(Opc, VT))
872 // Consult target whether it is a good idea to promote this operation and
873 // what's the right type to promote it to.
874 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
875 assert(PVT != VT && "Don't know what type to promote to!");
877 bool Replace = false;
878 SDValue N0 = Op.getOperand(0);
880 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
881 else if (Opc == ISD::SRL)
882 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
884 N0 = PromoteOperand(N0, PVT, Replace);
885 if (N0.getNode() == 0)
888 AddToWorkList(N0.getNode());
890 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
892 DEBUG(dbgs() << "\nPromoting ";
893 Op.getNode()->dump(&DAG));
894 DebugLoc dl = Op.getDebugLoc();
895 return DAG.getNode(ISD::TRUNCATE, dl, VT,
896 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
901 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
902 if (!LegalOperations)
905 EVT VT = Op.getValueType();
906 if (VT.isVector() || !VT.isInteger())
909 // If operation type is 'undesirable', e.g. i16 on x86, consider
911 unsigned Opc = Op.getOpcode();
912 if (TLI.isTypeDesirableForOp(Opc, VT))
916 // Consult target whether it is a good idea to promote this operation and
917 // what's the right type to promote it to.
918 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
919 assert(PVT != VT && "Don't know what type to promote to!");
920 // fold (aext (aext x)) -> (aext x)
921 // fold (aext (zext x)) -> (zext x)
922 // fold (aext (sext x)) -> (sext x)
923 DEBUG(dbgs() << "\nPromoting ";
924 Op.getNode()->dump(&DAG));
925 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
930 bool DAGCombiner::PromoteLoad(SDValue Op) {
931 if (!LegalOperations)
934 EVT VT = Op.getValueType();
935 if (VT.isVector() || !VT.isInteger())
938 // If operation type is 'undesirable', e.g. i16 on x86, consider
940 unsigned Opc = Op.getOpcode();
941 if (TLI.isTypeDesirableForOp(Opc, VT))
945 // Consult target whether it is a good idea to promote this operation and
946 // what's the right type to promote it to.
947 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
948 assert(PVT != VT && "Don't know what type to promote to!");
950 DebugLoc dl = Op.getDebugLoc();
951 SDNode *N = Op.getNode();
952 LoadSDNode *LD = cast<LoadSDNode>(N);
953 EVT MemVT = LD->getMemoryVT();
954 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
955 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
957 : LD->getExtensionType();
958 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
959 LD->getChain(), LD->getBasePtr(),
960 LD->getPointerInfo(),
961 MemVT, LD->isVolatile(),
962 LD->isNonTemporal(), LD->getAlignment());
963 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
965 DEBUG(dbgs() << "\nPromoting ";
968 Result.getNode()->dump(&DAG);
970 WorkListRemover DeadNodes(*this);
971 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
972 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
973 removeFromWorkList(N);
975 AddToWorkList(Result.getNode());
982 //===----------------------------------------------------------------------===//
983 // Main DAG Combiner implementation
984 //===----------------------------------------------------------------------===//
986 void DAGCombiner::Run(CombineLevel AtLevel) {
987 // set the instance variables, so that the various visit routines may use it.
989 LegalOperations = Level >= AfterLegalizeVectorOps;
990 LegalTypes = Level >= AfterLegalizeTypes;
992 // Add all the dag nodes to the worklist.
993 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
994 E = DAG.allnodes_end(); I != E; ++I)
997 // Create a dummy node (which is not added to allnodes), that adds a reference
998 // to the root node, preventing it from being deleted, and tracking any
999 // changes of the root.
1000 HandleSDNode Dummy(DAG.getRoot());
1002 // The root of the dag may dangle to deleted nodes until the dag combiner is
1003 // done. Set it to null to avoid confusion.
1004 DAG.setRoot(SDValue());
1006 // while the worklist isn't empty, find a node and
1007 // try and combine it.
1008 while (!WorkListContents.empty()) {
1010 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates.
1011 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the
1012 // worklist *should* contain, and check the node we want to visit is should
1013 // actually be visited.
1015 N = WorkListOrder.pop_back_val();
1016 } while (!WorkListContents.erase(N));
1018 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1019 // N is deleted from the DAG, since they too may now be dead or may have a
1020 // reduced number of uses, allowing other xforms.
1021 if (N->use_empty() && N != &Dummy) {
1022 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1023 AddToWorkList(N->getOperand(i).getNode());
1029 SDValue RV = combine(N);
1031 if (RV.getNode() == 0)
1036 // If we get back the same node we passed in, rather than a new node or
1037 // zero, we know that the node must have defined multiple values and
1038 // CombineTo was used. Since CombineTo takes care of the worklist
1039 // mechanics for us, we have no work to do in this case.
1040 if (RV.getNode() == N)
1043 assert(N->getOpcode() != ISD::DELETED_NODE &&
1044 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1045 "Node was deleted but visit returned new node!");
1047 DEBUG(dbgs() << "\nReplacing.3 ";
1049 dbgs() << "\nWith: ";
1050 RV.getNode()->dump(&DAG);
1053 // Transfer debug value.
1054 DAG.TransferDbgValues(SDValue(N, 0), RV);
1055 WorkListRemover DeadNodes(*this);
1056 if (N->getNumValues() == RV.getNode()->getNumValues())
1057 DAG.ReplaceAllUsesWith(N, RV.getNode());
1059 assert(N->getValueType(0) == RV.getValueType() &&
1060 N->getNumValues() == 1 && "Type mismatch");
1062 DAG.ReplaceAllUsesWith(N, &OpV);
1065 // Push the new node and any users onto the worklist
1066 AddToWorkList(RV.getNode());
1067 AddUsersToWorkList(RV.getNode());
1069 // Add any uses of the old node to the worklist in case this node is the
1070 // last one that uses them. They may become dead after this node is
1072 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1073 AddToWorkList(N->getOperand(i).getNode());
1075 // Finally, if the node is now dead, remove it from the graph. The node
1076 // may not be dead if the replacement process recursively simplified to
1077 // something else needing this node.
1078 if (N->use_empty()) {
1079 // Nodes can be reintroduced into the worklist. Make sure we do not
1080 // process a node that has been replaced.
1081 removeFromWorkList(N);
1083 // Finally, since the node is now dead, remove it from the graph.
1088 // If the root changed (e.g. it was a dead load, update the root).
1089 DAG.setRoot(Dummy.getValue());
1090 DAG.RemoveDeadNodes();
1093 SDValue DAGCombiner::visit(SDNode *N) {
1094 switch (N->getOpcode()) {
1096 case ISD::TokenFactor: return visitTokenFactor(N);
1097 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1098 case ISD::ADD: return visitADD(N);
1099 case ISD::SUB: return visitSUB(N);
1100 case ISD::ADDC: return visitADDC(N);
1101 case ISD::SUBC: return visitSUBC(N);
1102 case ISD::ADDE: return visitADDE(N);
1103 case ISD::SUBE: return visitSUBE(N);
1104 case ISD::MUL: return visitMUL(N);
1105 case ISD::SDIV: return visitSDIV(N);
1106 case ISD::UDIV: return visitUDIV(N);
1107 case ISD::SREM: return visitSREM(N);
1108 case ISD::UREM: return visitUREM(N);
1109 case ISD::MULHU: return visitMULHU(N);
1110 case ISD::MULHS: return visitMULHS(N);
1111 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1112 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1113 case ISD::SMULO: return visitSMULO(N);
1114 case ISD::UMULO: return visitUMULO(N);
1115 case ISD::SDIVREM: return visitSDIVREM(N);
1116 case ISD::UDIVREM: return visitUDIVREM(N);
1117 case ISD::AND: return visitAND(N);
1118 case ISD::OR: return visitOR(N);
1119 case ISD::XOR: return visitXOR(N);
1120 case ISD::SHL: return visitSHL(N);
1121 case ISD::SRA: return visitSRA(N);
1122 case ISD::SRL: return visitSRL(N);
1123 case ISD::CTLZ: return visitCTLZ(N);
1124 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1125 case ISD::CTTZ: return visitCTTZ(N);
1126 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1127 case ISD::CTPOP: return visitCTPOP(N);
1128 case ISD::SELECT: return visitSELECT(N);
1129 case ISD::SELECT_CC: return visitSELECT_CC(N);
1130 case ISD::SETCC: return visitSETCC(N);
1131 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1132 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1133 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1134 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1135 case ISD::TRUNCATE: return visitTRUNCATE(N);
1136 case ISD::BITCAST: return visitBITCAST(N);
1137 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1138 case ISD::FADD: return visitFADD(N);
1139 case ISD::FSUB: return visitFSUB(N);
1140 case ISD::FMUL: return visitFMUL(N);
1141 case ISD::FMA: return visitFMA(N);
1142 case ISD::FDIV: return visitFDIV(N);
1143 case ISD::FREM: return visitFREM(N);
1144 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1145 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1146 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1147 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1148 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1149 case ISD::FP_ROUND: return visitFP_ROUND(N);
1150 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1151 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1152 case ISD::FNEG: return visitFNEG(N);
1153 case ISD::FABS: return visitFABS(N);
1154 case ISD::FFLOOR: return visitFFLOOR(N);
1155 case ISD::FCEIL: return visitFCEIL(N);
1156 case ISD::FTRUNC: return visitFTRUNC(N);
1157 case ISD::BRCOND: return visitBRCOND(N);
1158 case ISD::BR_CC: return visitBR_CC(N);
1159 case ISD::LOAD: return visitLOAD(N);
1160 case ISD::STORE: return visitSTORE(N);
1161 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1162 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1163 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1164 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1165 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1166 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1167 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1172 SDValue DAGCombiner::combine(SDNode *N) {
1173 SDValue RV = visit(N);
1175 // If nothing happened, try a target-specific DAG combine.
1176 if (RV.getNode() == 0) {
1177 assert(N->getOpcode() != ISD::DELETED_NODE &&
1178 "Node was deleted but visit returned NULL!");
1180 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1181 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1183 // Expose the DAG combiner to the target combiner impls.
1184 TargetLowering::DAGCombinerInfo
1185 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1187 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1191 // If nothing happened still, try promoting the operation.
1192 if (RV.getNode() == 0) {
1193 switch (N->getOpcode()) {
1201 RV = PromoteIntBinOp(SDValue(N, 0));
1206 RV = PromoteIntShiftOp(SDValue(N, 0));
1208 case ISD::SIGN_EXTEND:
1209 case ISD::ZERO_EXTEND:
1210 case ISD::ANY_EXTEND:
1211 RV = PromoteExtend(SDValue(N, 0));
1214 if (PromoteLoad(SDValue(N, 0)))
1220 // If N is a commutative binary node, try commuting it to enable more
1222 if (RV.getNode() == 0 &&
1223 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1224 N->getNumValues() == 1) {
1225 SDValue N0 = N->getOperand(0);
1226 SDValue N1 = N->getOperand(1);
1228 // Constant operands are canonicalized to RHS.
1229 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1230 SDValue Ops[] = { N1, N0 };
1231 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1234 return SDValue(CSENode, 0);
1241 /// getInputChainForNode - Given a node, return its input chain if it has one,
1242 /// otherwise return a null sd operand.
1243 static SDValue getInputChainForNode(SDNode *N) {
1244 if (unsigned NumOps = N->getNumOperands()) {
1245 if (N->getOperand(0).getValueType() == MVT::Other)
1246 return N->getOperand(0);
1247 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1248 return N->getOperand(NumOps-1);
1249 for (unsigned i = 1; i < NumOps-1; ++i)
1250 if (N->getOperand(i).getValueType() == MVT::Other)
1251 return N->getOperand(i);
1256 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1257 // If N has two operands, where one has an input chain equal to the other,
1258 // the 'other' chain is redundant.
1259 if (N->getNumOperands() == 2) {
1260 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1261 return N->getOperand(0);
1262 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1263 return N->getOperand(1);
1266 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1267 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1268 SmallPtrSet<SDNode*, 16> SeenOps;
1269 bool Changed = false; // If we should replace this token factor.
1271 // Start out with this token factor.
1274 // Iterate through token factors. The TFs grows when new token factors are
1276 for (unsigned i = 0; i < TFs.size(); ++i) {
1277 SDNode *TF = TFs[i];
1279 // Check each of the operands.
1280 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1281 SDValue Op = TF->getOperand(i);
1283 switch (Op.getOpcode()) {
1284 case ISD::EntryToken:
1285 // Entry tokens don't need to be added to the list. They are
1290 case ISD::TokenFactor:
1291 if (Op.hasOneUse() &&
1292 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1293 // Queue up for processing.
1294 TFs.push_back(Op.getNode());
1295 // Clean up in case the token factor is removed.
1296 AddToWorkList(Op.getNode());
1303 // Only add if it isn't already in the list.
1304 if (SeenOps.insert(Op.getNode()))
1315 // If we've change things around then replace token factor.
1318 // The entry token is the only possible outcome.
1319 Result = DAG.getEntryNode();
1321 // New and improved token factor.
1322 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1323 MVT::Other, &Ops[0], Ops.size());
1326 // Don't add users to work list.
1327 return CombineTo(N, Result, false);
1333 /// MERGE_VALUES can always be eliminated.
1334 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1335 WorkListRemover DeadNodes(*this);
1336 // Replacing results may cause a different MERGE_VALUES to suddenly
1337 // be CSE'd with N, and carry its uses with it. Iterate until no
1338 // uses remain, to ensure that the node can be safely deleted.
1339 // First add the users of this node to the work list so that they
1340 // can be tried again once they have new operands.
1341 AddUsersToWorkList(N);
1343 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1344 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1345 } while (!N->use_empty());
1346 removeFromWorkList(N);
1348 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1352 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1353 SelectionDAG &DAG) {
1354 EVT VT = N0.getValueType();
1355 SDValue N00 = N0.getOperand(0);
1356 SDValue N01 = N0.getOperand(1);
1357 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1359 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1360 isa<ConstantSDNode>(N00.getOperand(1))) {
1361 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1362 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1363 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1364 N00.getOperand(0), N01),
1365 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1366 N00.getOperand(1), N01));
1367 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1373 SDValue DAGCombiner::visitADD(SDNode *N) {
1374 SDValue N0 = N->getOperand(0);
1375 SDValue N1 = N->getOperand(1);
1376 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1377 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1378 EVT VT = N0.getValueType();
1381 if (VT.isVector()) {
1382 SDValue FoldedVOp = SimplifyVBinOp(N);
1383 if (FoldedVOp.getNode()) return FoldedVOp;
1386 // fold (add x, undef) -> undef
1387 if (N0.getOpcode() == ISD::UNDEF)
1389 if (N1.getOpcode() == ISD::UNDEF)
1391 // fold (add c1, c2) -> c1+c2
1393 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1394 // canonicalize constant to RHS
1396 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1397 // fold (add x, 0) -> x
1398 if (N1C && N1C->isNullValue())
1400 // fold (add Sym, c) -> Sym+c
1401 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1402 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1403 GA->getOpcode() == ISD::GlobalAddress)
1404 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1406 (uint64_t)N1C->getSExtValue());
1407 // fold ((c1-A)+c2) -> (c1+c2)-A
1408 if (N1C && N0.getOpcode() == ISD::SUB)
1409 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1410 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1411 DAG.getConstant(N1C->getAPIntValue()+
1412 N0C->getAPIntValue(), VT),
1415 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1416 if (RADD.getNode() != 0)
1418 // fold ((0-A) + B) -> B-A
1419 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1420 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1421 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1422 // fold (A + (0-B)) -> A-B
1423 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1424 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1425 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1426 // fold (A+(B-A)) -> B
1427 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1428 return N1.getOperand(0);
1429 // fold ((B-A)+A) -> B
1430 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1431 return N0.getOperand(0);
1432 // fold (A+(B-(A+C))) to (B-C)
1433 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1434 N0 == N1.getOperand(1).getOperand(0))
1435 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1436 N1.getOperand(1).getOperand(1));
1437 // fold (A+(B-(C+A))) to (B-C)
1438 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1439 N0 == N1.getOperand(1).getOperand(1))
1440 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1441 N1.getOperand(1).getOperand(0));
1442 // fold (A+((B-A)+or-C)) to (B+or-C)
1443 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1444 N1.getOperand(0).getOpcode() == ISD::SUB &&
1445 N0 == N1.getOperand(0).getOperand(1))
1446 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1447 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1449 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1450 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1451 SDValue N00 = N0.getOperand(0);
1452 SDValue N01 = N0.getOperand(1);
1453 SDValue N10 = N1.getOperand(0);
1454 SDValue N11 = N1.getOperand(1);
1456 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1457 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1458 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1459 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1462 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1463 return SDValue(N, 0);
1465 // fold (a+b) -> (a|b) iff a and b share no bits.
1466 if (VT.isInteger() && !VT.isVector()) {
1467 APInt LHSZero, LHSOne;
1468 APInt RHSZero, RHSOne;
1469 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1471 if (LHSZero.getBoolValue()) {
1472 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1474 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1475 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1476 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1477 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1481 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1482 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1483 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1484 if (Result.getNode()) return Result;
1486 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1487 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1488 if (Result.getNode()) return Result;
1491 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1492 if (N1.getOpcode() == ISD::SHL &&
1493 N1.getOperand(0).getOpcode() == ISD::SUB)
1494 if (ConstantSDNode *C =
1495 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1496 if (C->getAPIntValue() == 0)
1497 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1498 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1499 N1.getOperand(0).getOperand(1),
1501 if (N0.getOpcode() == ISD::SHL &&
1502 N0.getOperand(0).getOpcode() == ISD::SUB)
1503 if (ConstantSDNode *C =
1504 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1505 if (C->getAPIntValue() == 0)
1506 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1507 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1508 N0.getOperand(0).getOperand(1),
1511 if (N1.getOpcode() == ISD::AND) {
1512 SDValue AndOp0 = N1.getOperand(0);
1513 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1514 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1515 unsigned DestBits = VT.getScalarType().getSizeInBits();
1517 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1518 // and similar xforms where the inner op is either ~0 or 0.
1519 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1520 DebugLoc DL = N->getDebugLoc();
1521 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1525 // add (sext i1), X -> sub X, (zext i1)
1526 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1527 N0.getOperand(0).getValueType() == MVT::i1 &&
1528 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1529 DebugLoc DL = N->getDebugLoc();
1530 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1531 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1537 SDValue DAGCombiner::visitADDC(SDNode *N) {
1538 SDValue N0 = N->getOperand(0);
1539 SDValue N1 = N->getOperand(1);
1540 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1541 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1542 EVT VT = N0.getValueType();
1544 // If the flag result is dead, turn this into an ADD.
1545 if (!N->hasAnyUseOfValue(1))
1546 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1),
1547 DAG.getNode(ISD::CARRY_FALSE,
1548 N->getDebugLoc(), MVT::Glue));
1550 // canonicalize constant to RHS.
1552 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1554 // fold (addc x, 0) -> x + no carry out
1555 if (N1C && N1C->isNullValue())
1556 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1557 N->getDebugLoc(), MVT::Glue));
1559 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1560 APInt LHSZero, LHSOne;
1561 APInt RHSZero, RHSOne;
1562 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1564 if (LHSZero.getBoolValue()) {
1565 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1567 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1568 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1569 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1570 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1571 DAG.getNode(ISD::CARRY_FALSE,
1572 N->getDebugLoc(), MVT::Glue));
1578 SDValue DAGCombiner::visitADDE(SDNode *N) {
1579 SDValue N0 = N->getOperand(0);
1580 SDValue N1 = N->getOperand(1);
1581 SDValue CarryIn = N->getOperand(2);
1582 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1583 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1585 // canonicalize constant to RHS
1587 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1590 // fold (adde x, y, false) -> (addc x, y)
1591 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1592 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1);
1597 // Since it may not be valid to emit a fold to zero for vector initializers
1598 // check if we can before folding.
1599 static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1600 SelectionDAG &DAG, bool LegalOperations) {
1601 if (!VT.isVector()) {
1602 return DAG.getConstant(0, VT);
1604 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1605 // Produce a vector of zeros.
1606 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1607 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1608 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1609 &Ops[0], Ops.size());
1614 SDValue DAGCombiner::visitSUB(SDNode *N) {
1615 SDValue N0 = N->getOperand(0);
1616 SDValue N1 = N->getOperand(1);
1617 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1618 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1619 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1620 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1621 EVT VT = N0.getValueType();
1624 if (VT.isVector()) {
1625 SDValue FoldedVOp = SimplifyVBinOp(N);
1626 if (FoldedVOp.getNode()) return FoldedVOp;
1629 // fold (sub x, x) -> 0
1630 // FIXME: Refactor this and xor and other similar operations together.
1632 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1633 // fold (sub c1, c2) -> c1-c2
1635 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1636 // fold (sub x, c) -> (add x, -c)
1638 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1639 DAG.getConstant(-N1C->getAPIntValue(), VT));
1640 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1641 if (N0C && N0C->isAllOnesValue())
1642 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1643 // fold A-(A-B) -> B
1644 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1645 return N1.getOperand(1);
1646 // fold (A+B)-A -> B
1647 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1648 return N0.getOperand(1);
1649 // fold (A+B)-B -> A
1650 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1651 return N0.getOperand(0);
1652 // fold C2-(A+C1) -> (C2-C1)-A
1653 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1654 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
1656 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
1659 // fold ((A+(B+or-C))-B) -> A+or-C
1660 if (N0.getOpcode() == ISD::ADD &&
1661 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1662 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1663 N0.getOperand(1).getOperand(0) == N1)
1664 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1665 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1666 // fold ((A+(C+B))-B) -> A+C
1667 if (N0.getOpcode() == ISD::ADD &&
1668 N0.getOperand(1).getOpcode() == ISD::ADD &&
1669 N0.getOperand(1).getOperand(1) == N1)
1670 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1671 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1672 // fold ((A-(B-C))-C) -> A-B
1673 if (N0.getOpcode() == ISD::SUB &&
1674 N0.getOperand(1).getOpcode() == ISD::SUB &&
1675 N0.getOperand(1).getOperand(1) == N1)
1676 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1677 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1679 // If either operand of a sub is undef, the result is undef
1680 if (N0.getOpcode() == ISD::UNDEF)
1682 if (N1.getOpcode() == ISD::UNDEF)
1685 // If the relocation model supports it, consider symbol offsets.
1686 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1687 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1688 // fold (sub Sym, c) -> Sym-c
1689 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1690 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1692 (uint64_t)N1C->getSExtValue());
1693 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1694 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1695 if (GA->getGlobal() == GB->getGlobal())
1696 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1703 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1704 SDValue N0 = N->getOperand(0);
1705 SDValue N1 = N->getOperand(1);
1706 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1707 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1708 EVT VT = N0.getValueType();
1710 // If the flag result is dead, turn this into an SUB.
1711 if (!N->hasAnyUseOfValue(1))
1712 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1),
1713 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1716 // fold (subc x, x) -> 0 + no borrow
1718 return CombineTo(N, DAG.getConstant(0, VT),
1719 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1722 // fold (subc x, 0) -> x + no borrow
1723 if (N1C && N1C->isNullValue())
1724 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1727 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1728 if (N0C && N0C->isAllOnesValue())
1729 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0),
1730 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1736 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1737 SDValue N0 = N->getOperand(0);
1738 SDValue N1 = N->getOperand(1);
1739 SDValue CarryIn = N->getOperand(2);
1741 // fold (sube x, y, false) -> (subc x, y)
1742 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1743 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1);
1748 SDValue DAGCombiner::visitMUL(SDNode *N) {
1749 SDValue N0 = N->getOperand(0);
1750 SDValue N1 = N->getOperand(1);
1751 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1752 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1753 EVT VT = N0.getValueType();
1756 if (VT.isVector()) {
1757 SDValue FoldedVOp = SimplifyVBinOp(N);
1758 if (FoldedVOp.getNode()) return FoldedVOp;
1761 // fold (mul x, undef) -> 0
1762 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1763 return DAG.getConstant(0, VT);
1764 // fold (mul c1, c2) -> c1*c2
1766 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1767 // canonicalize constant to RHS
1769 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1770 // fold (mul x, 0) -> 0
1771 if (N1C && N1C->isNullValue())
1773 // fold (mul x, -1) -> 0-x
1774 if (N1C && N1C->isAllOnesValue())
1775 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1776 DAG.getConstant(0, VT), N0);
1777 // fold (mul x, (1 << c)) -> x << c
1778 if (N1C && N1C->getAPIntValue().isPowerOf2())
1779 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1780 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1781 getShiftAmountTy(N0.getValueType())));
1782 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1783 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1784 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1785 // FIXME: If the input is something that is easily negated (e.g. a
1786 // single-use add), we should put the negate there.
1787 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1788 DAG.getConstant(0, VT),
1789 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1790 DAG.getConstant(Log2Val,
1791 getShiftAmountTy(N0.getValueType()))));
1793 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1794 if (N1C && N0.getOpcode() == ISD::SHL &&
1795 isa<ConstantSDNode>(N0.getOperand(1))) {
1796 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1797 N1, N0.getOperand(1));
1798 AddToWorkList(C3.getNode());
1799 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1800 N0.getOperand(0), C3);
1803 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1806 SDValue Sh(0,0), Y(0,0);
1807 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1808 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1809 N0.getNode()->hasOneUse()) {
1811 } else if (N1.getOpcode() == ISD::SHL &&
1812 isa<ConstantSDNode>(N1.getOperand(1)) &&
1813 N1.getNode()->hasOneUse()) {
1818 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1819 Sh.getOperand(0), Y);
1820 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1821 Mul, Sh.getOperand(1));
1825 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1826 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1827 isa<ConstantSDNode>(N0.getOperand(1)))
1828 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1829 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1830 N0.getOperand(0), N1),
1831 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1832 N0.getOperand(1), N1));
1835 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1836 if (RMUL.getNode() != 0)
1842 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1843 SDValue N0 = N->getOperand(0);
1844 SDValue N1 = N->getOperand(1);
1845 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1846 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1847 EVT VT = N->getValueType(0);
1850 if (VT.isVector()) {
1851 SDValue FoldedVOp = SimplifyVBinOp(N);
1852 if (FoldedVOp.getNode()) return FoldedVOp;
1855 // fold (sdiv c1, c2) -> c1/c2
1856 if (N0C && N1C && !N1C->isNullValue())
1857 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1858 // fold (sdiv X, 1) -> X
1859 if (N1C && N1C->getAPIntValue() == 1LL)
1861 // fold (sdiv X, -1) -> 0-X
1862 if (N1C && N1C->isAllOnesValue())
1863 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1864 DAG.getConstant(0, VT), N0);
1865 // If we know the sign bits of both operands are zero, strength reduce to a
1866 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1867 if (!VT.isVector()) {
1868 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1869 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1872 // fold (sdiv X, pow2) -> simple ops after legalize
1873 if (N1C && !N1C->isNullValue() &&
1874 (N1C->getAPIntValue().isPowerOf2() ||
1875 (-N1C->getAPIntValue()).isPowerOf2())) {
1876 // If dividing by powers of two is cheap, then don't perform the following
1878 if (TLI.isPow2DivCheap())
1881 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
1883 // Splat the sign bit into the register
1884 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1885 DAG.getConstant(VT.getSizeInBits()-1,
1886 getShiftAmountTy(N0.getValueType())));
1887 AddToWorkList(SGN.getNode());
1889 // Add (N0 < 0) ? abs2 - 1 : 0;
1890 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1891 DAG.getConstant(VT.getSizeInBits() - lg2,
1892 getShiftAmountTy(SGN.getValueType())));
1893 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1894 AddToWorkList(SRL.getNode());
1895 AddToWorkList(ADD.getNode()); // Divide by pow2
1896 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1897 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1899 // If we're dividing by a positive value, we're done. Otherwise, we must
1900 // negate the result.
1901 if (N1C->getAPIntValue().isNonNegative())
1904 AddToWorkList(SRA.getNode());
1905 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1906 DAG.getConstant(0, VT), SRA);
1909 // if integer divide is expensive and we satisfy the requirements, emit an
1910 // alternate sequence.
1911 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1912 SDValue Op = BuildSDIV(N);
1913 if (Op.getNode()) return Op;
1917 if (N0.getOpcode() == ISD::UNDEF)
1918 return DAG.getConstant(0, VT);
1919 // X / undef -> undef
1920 if (N1.getOpcode() == ISD::UNDEF)
1926 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1927 SDValue N0 = N->getOperand(0);
1928 SDValue N1 = N->getOperand(1);
1929 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1930 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1931 EVT VT = N->getValueType(0);
1934 if (VT.isVector()) {
1935 SDValue FoldedVOp = SimplifyVBinOp(N);
1936 if (FoldedVOp.getNode()) return FoldedVOp;
1939 // fold (udiv c1, c2) -> c1/c2
1940 if (N0C && N1C && !N1C->isNullValue())
1941 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1942 // fold (udiv x, (1 << c)) -> x >>u c
1943 if (N1C && N1C->getAPIntValue().isPowerOf2())
1944 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1945 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1946 getShiftAmountTy(N0.getValueType())));
1947 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1948 if (N1.getOpcode() == ISD::SHL) {
1949 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1950 if (SHC->getAPIntValue().isPowerOf2()) {
1951 EVT ADDVT = N1.getOperand(1).getValueType();
1952 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1954 DAG.getConstant(SHC->getAPIntValue()
1957 AddToWorkList(Add.getNode());
1958 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1962 // fold (udiv x, c) -> alternate
1963 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1964 SDValue Op = BuildUDIV(N);
1965 if (Op.getNode()) return Op;
1969 if (N0.getOpcode() == ISD::UNDEF)
1970 return DAG.getConstant(0, VT);
1971 // X / undef -> undef
1972 if (N1.getOpcode() == ISD::UNDEF)
1978 SDValue DAGCombiner::visitSREM(SDNode *N) {
1979 SDValue N0 = N->getOperand(0);
1980 SDValue N1 = N->getOperand(1);
1981 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1982 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1983 EVT VT = N->getValueType(0);
1985 // fold (srem c1, c2) -> c1%c2
1986 if (N0C && N1C && !N1C->isNullValue())
1987 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1988 // If we know the sign bits of both operands are zero, strength reduce to a
1989 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1990 if (!VT.isVector()) {
1991 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1992 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1995 // If X/C can be simplified by the division-by-constant logic, lower
1996 // X%C to the equivalent of X-X/C*C.
1997 if (N1C && !N1C->isNullValue()) {
1998 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1999 AddToWorkList(Div.getNode());
2000 SDValue OptimizedDiv = combine(Div.getNode());
2001 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2002 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2004 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2005 AddToWorkList(Mul.getNode());
2011 if (N0.getOpcode() == ISD::UNDEF)
2012 return DAG.getConstant(0, VT);
2013 // X % undef -> undef
2014 if (N1.getOpcode() == ISD::UNDEF)
2020 SDValue DAGCombiner::visitUREM(SDNode *N) {
2021 SDValue N0 = N->getOperand(0);
2022 SDValue N1 = N->getOperand(1);
2023 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2024 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2025 EVT VT = N->getValueType(0);
2027 // fold (urem c1, c2) -> c1%c2
2028 if (N0C && N1C && !N1C->isNullValue())
2029 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2030 // fold (urem x, pow2) -> (and x, pow2-1)
2031 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2032 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
2033 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2034 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2035 if (N1.getOpcode() == ISD::SHL) {
2036 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2037 if (SHC->getAPIntValue().isPowerOf2()) {
2039 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
2040 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2042 AddToWorkList(Add.getNode());
2043 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
2048 // If X/C can be simplified by the division-by-constant logic, lower
2049 // X%C to the equivalent of X-X/C*C.
2050 if (N1C && !N1C->isNullValue()) {
2051 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
2052 AddToWorkList(Div.getNode());
2053 SDValue OptimizedDiv = combine(Div.getNode());
2054 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2055 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2057 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2058 AddToWorkList(Mul.getNode());
2064 if (N0.getOpcode() == ISD::UNDEF)
2065 return DAG.getConstant(0, VT);
2066 // X % undef -> undef
2067 if (N1.getOpcode() == ISD::UNDEF)
2073 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2074 SDValue N0 = N->getOperand(0);
2075 SDValue N1 = N->getOperand(1);
2076 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2077 EVT VT = N->getValueType(0);
2078 DebugLoc DL = N->getDebugLoc();
2080 // fold (mulhs x, 0) -> 0
2081 if (N1C && N1C->isNullValue())
2083 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2084 if (N1C && N1C->getAPIntValue() == 1)
2085 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
2086 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2087 getShiftAmountTy(N0.getValueType())));
2088 // fold (mulhs x, undef) -> 0
2089 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2090 return DAG.getConstant(0, VT);
2092 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2094 if (VT.isSimple() && !VT.isVector()) {
2095 MVT Simple = VT.getSimpleVT();
2096 unsigned SimpleSize = Simple.getSizeInBits();
2097 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2098 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2099 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2100 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2101 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2102 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2103 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2104 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2111 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2112 SDValue N0 = N->getOperand(0);
2113 SDValue N1 = N->getOperand(1);
2114 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2115 EVT VT = N->getValueType(0);
2116 DebugLoc DL = N->getDebugLoc();
2118 // fold (mulhu x, 0) -> 0
2119 if (N1C && N1C->isNullValue())
2121 // fold (mulhu x, 1) -> 0
2122 if (N1C && N1C->getAPIntValue() == 1)
2123 return DAG.getConstant(0, N0.getValueType());
2124 // fold (mulhu x, undef) -> 0
2125 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2126 return DAG.getConstant(0, VT);
2128 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2130 if (VT.isSimple() && !VT.isVector()) {
2131 MVT Simple = VT.getSimpleVT();
2132 unsigned SimpleSize = Simple.getSizeInBits();
2133 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2134 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2135 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2136 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2137 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2138 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2139 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2140 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2147 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2148 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2149 /// that are being performed. Return true if a simplification was made.
2151 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2153 // If the high half is not needed, just compute the low half.
2154 bool HiExists = N->hasAnyUseOfValue(1);
2156 (!LegalOperations ||
2157 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2158 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2159 N->op_begin(), N->getNumOperands());
2160 return CombineTo(N, Res, Res);
2163 // If the low half is not needed, just compute the high half.
2164 bool LoExists = N->hasAnyUseOfValue(0);
2166 (!LegalOperations ||
2167 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2168 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2169 N->op_begin(), N->getNumOperands());
2170 return CombineTo(N, Res, Res);
2173 // If both halves are used, return as it is.
2174 if (LoExists && HiExists)
2177 // If the two computed results can be simplified separately, separate them.
2179 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2180 N->op_begin(), N->getNumOperands());
2181 AddToWorkList(Lo.getNode());
2182 SDValue LoOpt = combine(Lo.getNode());
2183 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2184 (!LegalOperations ||
2185 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2186 return CombineTo(N, LoOpt, LoOpt);
2190 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2191 N->op_begin(), N->getNumOperands());
2192 AddToWorkList(Hi.getNode());
2193 SDValue HiOpt = combine(Hi.getNode());
2194 if (HiOpt.getNode() && HiOpt != Hi &&
2195 (!LegalOperations ||
2196 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2197 return CombineTo(N, HiOpt, HiOpt);
2203 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2204 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2205 if (Res.getNode()) return Res;
2207 EVT VT = N->getValueType(0);
2208 DebugLoc DL = N->getDebugLoc();
2210 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2212 if (VT.isSimple() && !VT.isVector()) {
2213 MVT Simple = VT.getSimpleVT();
2214 unsigned SimpleSize = Simple.getSizeInBits();
2215 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2216 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2217 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2218 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2219 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2220 // Compute the high part as N1.
2221 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2222 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2223 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2224 // Compute the low part as N0.
2225 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2226 return CombineTo(N, Lo, Hi);
2233 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2234 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2235 if (Res.getNode()) return Res;
2237 EVT VT = N->getValueType(0);
2238 DebugLoc DL = N->getDebugLoc();
2240 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2242 if (VT.isSimple() && !VT.isVector()) {
2243 MVT Simple = VT.getSimpleVT();
2244 unsigned SimpleSize = Simple.getSizeInBits();
2245 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2246 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2247 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2248 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2249 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2250 // Compute the high part as N1.
2251 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2252 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2253 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2254 // Compute the low part as N0.
2255 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2256 return CombineTo(N, Lo, Hi);
2263 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2264 // (smulo x, 2) -> (saddo x, x)
2265 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2266 if (C2->getAPIntValue() == 2)
2267 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2268 N->getOperand(0), N->getOperand(0));
2273 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2274 // (umulo x, 2) -> (uaddo x, x)
2275 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2276 if (C2->getAPIntValue() == 2)
2277 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2278 N->getOperand(0), N->getOperand(0));
2283 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2284 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2285 if (Res.getNode()) return Res;
2290 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2291 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2292 if (Res.getNode()) return Res;
2297 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2298 /// two operands of the same opcode, try to simplify it.
2299 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2300 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2301 EVT VT = N0.getValueType();
2302 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2304 // Bail early if none of these transforms apply.
2305 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2307 // For each of OP in AND/OR/XOR:
2308 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2309 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2310 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2311 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2313 // do not sink logical op inside of a vector extend, since it may combine
2315 EVT Op0VT = N0.getOperand(0).getValueType();
2316 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2317 N0.getOpcode() == ISD::SIGN_EXTEND ||
2318 // Avoid infinite looping with PromoteIntBinOp.
2319 (N0.getOpcode() == ISD::ANY_EXTEND &&
2320 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2321 (N0.getOpcode() == ISD::TRUNCATE &&
2322 (!TLI.isZExtFree(VT, Op0VT) ||
2323 !TLI.isTruncateFree(Op0VT, VT)) &&
2324 TLI.isTypeLegal(Op0VT))) &&
2326 Op0VT == N1.getOperand(0).getValueType() &&
2327 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2328 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2329 N0.getOperand(0).getValueType(),
2330 N0.getOperand(0), N1.getOperand(0));
2331 AddToWorkList(ORNode.getNode());
2332 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2335 // For each of OP in SHL/SRL/SRA/AND...
2336 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2337 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2338 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2339 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2340 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2341 N0.getOperand(1) == N1.getOperand(1)) {
2342 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2343 N0.getOperand(0).getValueType(),
2344 N0.getOperand(0), N1.getOperand(0));
2345 AddToWorkList(ORNode.getNode());
2346 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2347 ORNode, N0.getOperand(1));
2350 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2351 // Only perform this optimization after type legalization and before
2352 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2353 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2354 // we don't want to undo this promotion.
2355 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2357 if ((N0.getOpcode() == ISD::BITCAST ||
2358 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2359 Level == AfterLegalizeTypes) {
2360 SDValue In0 = N0.getOperand(0);
2361 SDValue In1 = N1.getOperand(0);
2362 EVT In0Ty = In0.getValueType();
2363 EVT In1Ty = In1.getValueType();
2364 DebugLoc DL = N->getDebugLoc();
2365 // If both incoming values are integers, and the original types are the
2367 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2368 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2369 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2370 AddToWorkList(Op.getNode());
2375 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2376 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2377 // If both shuffles use the same mask, and both shuffle within a single
2378 // vector, then it is worthwhile to move the swizzle after the operation.
2379 // The type-legalizer generates this pattern when loading illegal
2380 // vector types from memory. In many cases this allows additional shuffle
2382 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
2383 N0.getOperand(1).getOpcode() == ISD::UNDEF &&
2384 N1.getOperand(1).getOpcode() == ISD::UNDEF) {
2385 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2386 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2388 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() &&
2389 "Inputs to shuffles are not the same type");
2391 unsigned NumElts = VT.getVectorNumElements();
2393 // Check that both shuffles use the same mask. The masks are known to be of
2394 // the same length because the result vector type is the same.
2395 bool SameMask = true;
2396 for (unsigned i = 0; i != NumElts; ++i) {
2397 int Idx0 = SVN0->getMaskElt(i);
2398 int Idx1 = SVN1->getMaskElt(i);
2406 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT,
2407 N0.getOperand(0), N1.getOperand(0));
2408 AddToWorkList(Op.getNode());
2409 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op,
2410 DAG.getUNDEF(VT), &SVN0->getMask()[0]);
2417 SDValue DAGCombiner::visitAND(SDNode *N) {
2418 SDValue N0 = N->getOperand(0);
2419 SDValue N1 = N->getOperand(1);
2420 SDValue LL, LR, RL, RR, CC0, CC1;
2421 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2422 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2423 EVT VT = N1.getValueType();
2424 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2427 if (VT.isVector()) {
2428 SDValue FoldedVOp = SimplifyVBinOp(N);
2429 if (FoldedVOp.getNode()) return FoldedVOp;
2432 // fold (and x, undef) -> 0
2433 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2434 return DAG.getConstant(0, VT);
2435 // fold (and c1, c2) -> c1&c2
2437 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2438 // canonicalize constant to RHS
2440 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2441 // fold (and x, -1) -> x
2442 if (N1C && N1C->isAllOnesValue())
2444 // if (and x, c) is known to be zero, return 0
2445 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2446 APInt::getAllOnesValue(BitWidth)))
2447 return DAG.getConstant(0, VT);
2449 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2450 if (RAND.getNode() != 0)
2452 // fold (and (or x, C), D) -> D if (C & D) == D
2453 if (N1C && N0.getOpcode() == ISD::OR)
2454 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2455 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2457 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2458 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2459 SDValue N0Op0 = N0.getOperand(0);
2460 APInt Mask = ~N1C->getAPIntValue();
2461 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2462 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2463 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2464 N0.getValueType(), N0Op0);
2466 // Replace uses of the AND with uses of the Zero extend node.
2469 // We actually want to replace all uses of the any_extend with the
2470 // zero_extend, to avoid duplicating things. This will later cause this
2471 // AND to be folded.
2472 CombineTo(N0.getNode(), Zext);
2473 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2476 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2477 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2478 // already be zero by virtue of the width of the base type of the load.
2480 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2482 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2483 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2484 N0.getOpcode() == ISD::LOAD) {
2485 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2486 N0 : N0.getOperand(0) );
2488 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2489 // This can be a pure constant or a vector splat, in which case we treat the
2490 // vector as a scalar and use the splat value.
2491 APInt Constant = APInt::getNullValue(1);
2492 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2493 Constant = C->getAPIntValue();
2494 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2495 APInt SplatValue, SplatUndef;
2496 unsigned SplatBitSize;
2498 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2499 SplatBitSize, HasAnyUndefs);
2501 // Undef bits can contribute to a possible optimisation if set, so
2503 SplatValue |= SplatUndef;
2505 // The splat value may be something like "0x00FFFFFF", which means 0 for
2506 // the first vector value and FF for the rest, repeating. We need a mask
2507 // that will apply equally to all members of the vector, so AND all the
2508 // lanes of the constant together.
2509 EVT VT = Vector->getValueType(0);
2510 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2512 // If the splat value has been compressed to a bitlength lower
2513 // than the size of the vector lane, we need to re-expand it to
2515 if (BitWidth > SplatBitSize)
2516 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
2517 SplatBitSize < BitWidth;
2518 SplatBitSize = SplatBitSize * 2)
2519 SplatValue |= SplatValue.shl(SplatBitSize);
2521 Constant = APInt::getAllOnesValue(BitWidth);
2522 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
2523 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2527 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2528 // actually legal and isn't going to get expanded, else this is a false
2530 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2531 Load->getMemoryVT());
2533 // Resize the constant to the same size as the original memory access before
2534 // extension. If it is still the AllOnesValue then this AND is completely
2537 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2540 switch (Load->getExtensionType()) {
2541 default: B = false; break;
2542 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2544 case ISD::NON_EXTLOAD: B = true; break;
2547 if (B && Constant.isAllOnesValue()) {
2548 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2549 // preserve semantics once we get rid of the AND.
2550 SDValue NewLoad(Load, 0);
2551 if (Load->getExtensionType() == ISD::EXTLOAD) {
2552 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2553 Load->getValueType(0), Load->getDebugLoc(),
2554 Load->getChain(), Load->getBasePtr(),
2555 Load->getOffset(), Load->getMemoryVT(),
2556 Load->getMemOperand());
2557 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2558 if (Load->getNumValues() == 3) {
2559 // PRE/POST_INC loads have 3 values.
2560 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
2561 NewLoad.getValue(2) };
2562 CombineTo(Load, To, 3, true);
2564 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2568 // Fold the AND away, taking care not to fold to the old load node if we
2570 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2572 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2575 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2576 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2577 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2578 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2580 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2581 LL.getValueType().isInteger()) {
2582 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2583 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2584 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2585 LR.getValueType(), LL, RL);
2586 AddToWorkList(ORNode.getNode());
2587 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2589 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2590 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2591 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2592 LR.getValueType(), LL, RL);
2593 AddToWorkList(ANDNode.getNode());
2594 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2596 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2597 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2598 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2599 LR.getValueType(), LL, RL);
2600 AddToWorkList(ORNode.getNode());
2601 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2604 // canonicalize equivalent to ll == rl
2605 if (LL == RR && LR == RL) {
2606 Op1 = ISD::getSetCCSwappedOperands(Op1);
2609 if (LL == RL && LR == RR) {
2610 bool isInteger = LL.getValueType().isInteger();
2611 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2612 if (Result != ISD::SETCC_INVALID &&
2613 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2614 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2619 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2620 if (N0.getOpcode() == N1.getOpcode()) {
2621 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2622 if (Tmp.getNode()) return Tmp;
2625 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2626 // fold (and (sra)) -> (and (srl)) when possible.
2627 if (!VT.isVector() &&
2628 SimplifyDemandedBits(SDValue(N, 0)))
2629 return SDValue(N, 0);
2631 // fold (zext_inreg (extload x)) -> (zextload x)
2632 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2633 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2634 EVT MemVT = LN0->getMemoryVT();
2635 // If we zero all the possible extended bits, then we can turn this into
2636 // a zextload if we are running before legalize or the operation is legal.
2637 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2638 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2639 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2640 ((!LegalOperations && !LN0->isVolatile()) ||
2641 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2642 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2643 LN0->getChain(), LN0->getBasePtr(),
2644 LN0->getPointerInfo(), MemVT,
2645 LN0->isVolatile(), LN0->isNonTemporal(),
2646 LN0->getAlignment());
2648 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2649 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2652 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2653 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2655 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2656 EVT MemVT = LN0->getMemoryVT();
2657 // If we zero all the possible extended bits, then we can turn this into
2658 // a zextload if we are running before legalize or the operation is legal.
2659 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2660 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2661 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2662 ((!LegalOperations && !LN0->isVolatile()) ||
2663 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2664 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2666 LN0->getBasePtr(), LN0->getPointerInfo(),
2668 LN0->isVolatile(), LN0->isNonTemporal(),
2669 LN0->getAlignment());
2671 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2672 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2676 // fold (and (load x), 255) -> (zextload x, i8)
2677 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2678 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2679 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2680 (N0.getOpcode() == ISD::ANY_EXTEND &&
2681 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2682 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2683 LoadSDNode *LN0 = HasAnyExt
2684 ? cast<LoadSDNode>(N0.getOperand(0))
2685 : cast<LoadSDNode>(N0);
2686 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2687 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2688 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2689 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2690 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2691 EVT LoadedVT = LN0->getMemoryVT();
2693 if (ExtVT == LoadedVT &&
2694 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2695 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2698 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2699 LN0->getChain(), LN0->getBasePtr(),
2700 LN0->getPointerInfo(),
2701 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2702 LN0->getAlignment());
2704 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2705 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2708 // Do not change the width of a volatile load.
2709 // Do not generate loads of non-round integer types since these can
2710 // be expensive (and would be wrong if the type is not byte sized).
2711 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2712 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2713 EVT PtrType = LN0->getOperand(1).getValueType();
2715 unsigned Alignment = LN0->getAlignment();
2716 SDValue NewPtr = LN0->getBasePtr();
2718 // For big endian targets, we need to add an offset to the pointer
2719 // to load the correct bytes. For little endian systems, we merely
2720 // need to read fewer bytes from the same pointer.
2721 if (TLI.isBigEndian()) {
2722 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2723 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2724 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2725 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2726 NewPtr, DAG.getConstant(PtrOff, PtrType));
2727 Alignment = MinAlign(Alignment, PtrOff);
2730 AddToWorkList(NewPtr.getNode());
2732 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2734 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2735 LN0->getChain(), NewPtr,
2736 LN0->getPointerInfo(),
2737 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2740 CombineTo(LN0, Load, Load.getValue(1));
2741 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2747 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2748 VT.getSizeInBits() <= 64) {
2749 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2750 APInt ADDC = ADDI->getAPIntValue();
2751 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2752 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
2753 // immediate for an add, but it is legal if its top c2 bits are set,
2754 // transform the ADD so the immediate doesn't need to be materialized
2756 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
2757 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
2758 SRLI->getZExtValue());
2759 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
2761 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2763 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
2764 N0.getOperand(0), DAG.getConstant(ADDC, VT));
2765 CombineTo(N0.getNode(), NewAdd);
2766 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2778 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2780 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2781 bool DemandHighBits) {
2782 if (!LegalOperations)
2785 EVT VT = N->getValueType(0);
2786 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2788 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2791 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2792 bool LookPassAnd0 = false;
2793 bool LookPassAnd1 = false;
2794 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2796 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2798 if (N0.getOpcode() == ISD::AND) {
2799 if (!N0.getNode()->hasOneUse())
2801 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2802 if (!N01C || N01C->getZExtValue() != 0xFF00)
2804 N0 = N0.getOperand(0);
2805 LookPassAnd0 = true;
2808 if (N1.getOpcode() == ISD::AND) {
2809 if (!N1.getNode()->hasOneUse())
2811 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2812 if (!N11C || N11C->getZExtValue() != 0xFF)
2814 N1 = N1.getOperand(0);
2815 LookPassAnd1 = true;
2818 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2820 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2822 if (!N0.getNode()->hasOneUse() ||
2823 !N1.getNode()->hasOneUse())
2826 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2827 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2830 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2833 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2834 SDValue N00 = N0->getOperand(0);
2835 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2836 if (!N00.getNode()->hasOneUse())
2838 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2839 if (!N001C || N001C->getZExtValue() != 0xFF)
2841 N00 = N00.getOperand(0);
2842 LookPassAnd0 = true;
2845 SDValue N10 = N1->getOperand(0);
2846 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2847 if (!N10.getNode()->hasOneUse())
2849 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2850 if (!N101C || N101C->getZExtValue() != 0xFF00)
2852 N10 = N10.getOperand(0);
2853 LookPassAnd1 = true;
2859 // Make sure everything beyond the low halfword is zero since the SRL 16
2860 // will clear the top bits.
2861 unsigned OpSizeInBits = VT.getSizeInBits();
2862 if (DemandHighBits && OpSizeInBits > 16 &&
2863 (!LookPassAnd0 || !LookPassAnd1) &&
2864 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
2867 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
2868 if (OpSizeInBits > 16)
2869 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2870 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2874 /// isBSwapHWordElement - Return true if the specified node is an element
2875 /// that makes up a 32-bit packed halfword byteswap. i.e.
2876 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2877 static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
2878 if (!N.getNode()->hasOneUse())
2881 unsigned Opc = N.getOpcode();
2882 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2885 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2890 switch (N1C->getZExtValue()) {
2893 case 0xFF: Num = 0; break;
2894 case 0xFF00: Num = 1; break;
2895 case 0xFF0000: Num = 2; break;
2896 case 0xFF000000: Num = 3; break;
2899 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
2900 SDValue N0 = N.getOperand(0);
2901 if (Opc == ISD::AND) {
2902 if (Num == 0 || Num == 2) {
2904 // (x >> 8) & 0xff0000
2905 if (N0.getOpcode() != ISD::SRL)
2907 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2908 if (!C || C->getZExtValue() != 8)
2911 // (x << 8) & 0xff00
2912 // (x << 8) & 0xff000000
2913 if (N0.getOpcode() != ISD::SHL)
2915 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2916 if (!C || C->getZExtValue() != 8)
2919 } else if (Opc == ISD::SHL) {
2921 // (x & 0xff0000) << 8
2922 if (Num != 0 && Num != 2)
2924 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2925 if (!C || C->getZExtValue() != 8)
2927 } else { // Opc == ISD::SRL
2928 // (x & 0xff00) >> 8
2929 // (x & 0xff000000) >> 8
2930 if (Num != 1 && Num != 3)
2932 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2933 if (!C || C->getZExtValue() != 8)
2940 Parts[Num] = N0.getOperand(0).getNode();
2944 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
2945 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2946 /// => (rotl (bswap x), 16)
2947 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2948 if (!LegalOperations)
2951 EVT VT = N->getValueType(0);
2954 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2957 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
2959 // (or (or (and), (and)), (or (and), (and)))
2960 // (or (or (or (and), (and)), (and)), (and))
2961 if (N0.getOpcode() != ISD::OR)
2963 SDValue N00 = N0.getOperand(0);
2964 SDValue N01 = N0.getOperand(1);
2966 if (N1.getOpcode() == ISD::OR) {
2967 // (or (or (and), (and)), (or (and), (and)))
2968 SDValue N000 = N00.getOperand(0);
2969 if (!isBSwapHWordElement(N000, Parts))
2972 SDValue N001 = N00.getOperand(1);
2973 if (!isBSwapHWordElement(N001, Parts))
2975 SDValue N010 = N01.getOperand(0);
2976 if (!isBSwapHWordElement(N010, Parts))
2978 SDValue N011 = N01.getOperand(1);
2979 if (!isBSwapHWordElement(N011, Parts))
2982 // (or (or (or (and), (and)), (and)), (and))
2983 if (!isBSwapHWordElement(N1, Parts))
2985 if (!isBSwapHWordElement(N01, Parts))
2987 if (N00.getOpcode() != ISD::OR)
2989 SDValue N000 = N00.getOperand(0);
2990 if (!isBSwapHWordElement(N000, Parts))
2992 SDValue N001 = N00.getOperand(1);
2993 if (!isBSwapHWordElement(N001, Parts))
2997 // Make sure the parts are all coming from the same node.
2998 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
3001 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
3002 SDValue(Parts[0],0));
3004 // Result of the bswap should be rotated by 16. If it's not legal, than
3005 // do (x << 16) | (x >> 16).
3006 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
3007 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3008 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
3009 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3010 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
3011 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
3012 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
3013 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
3016 SDValue DAGCombiner::visitOR(SDNode *N) {
3017 SDValue N0 = N->getOperand(0);
3018 SDValue N1 = N->getOperand(1);
3019 SDValue LL, LR, RL, RR, CC0, CC1;
3020 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3021 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3022 EVT VT = N1.getValueType();
3025 if (VT.isVector()) {
3026 SDValue FoldedVOp = SimplifyVBinOp(N);
3027 if (FoldedVOp.getNode()) return FoldedVOp;
3030 // fold (or x, undef) -> -1
3031 if (!LegalOperations &&
3032 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3033 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3034 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
3036 // fold (or c1, c2) -> c1|c2
3038 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
3039 // canonicalize constant to RHS
3041 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
3042 // fold (or x, 0) -> x
3043 if (N1C && N1C->isNullValue())
3045 // fold (or x, -1) -> -1
3046 if (N1C && N1C->isAllOnesValue())
3048 // fold (or x, c) -> c iff (x & ~c) == 0
3049 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3052 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3053 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3054 if (BSwap.getNode() != 0)
3056 BSwap = MatchBSwapHWordLow(N, N0, N1);
3057 if (BSwap.getNode() != 0)
3061 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
3062 if (ROR.getNode() != 0)
3064 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3065 // iff (c1 & c2) == 0.
3066 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3067 isa<ConstantSDNode>(N0.getOperand(1))) {
3068 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3069 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
3070 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3071 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3072 N0.getOperand(0), N1),
3073 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
3075 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3076 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3077 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3078 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3080 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3081 LL.getValueType().isInteger()) {
3082 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3083 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3084 if (cast<ConstantSDNode>(LR)->isNullValue() &&
3085 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3086 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
3087 LR.getValueType(), LL, RL);
3088 AddToWorkList(ORNode.getNode());
3089 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
3091 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3092 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3093 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
3094 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3095 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
3096 LR.getValueType(), LL, RL);
3097 AddToWorkList(ANDNode.getNode());
3098 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
3101 // canonicalize equivalent to ll == rl
3102 if (LL == RR && LR == RL) {
3103 Op1 = ISD::getSetCCSwappedOperands(Op1);
3106 if (LL == RL && LR == RR) {
3107 bool isInteger = LL.getValueType().isInteger();
3108 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3109 if (Result != ISD::SETCC_INVALID &&
3110 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
3111 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
3116 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3117 if (N0.getOpcode() == N1.getOpcode()) {
3118 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3119 if (Tmp.getNode()) return Tmp;
3122 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3123 if (N0.getOpcode() == ISD::AND &&
3124 N1.getOpcode() == ISD::AND &&
3125 N0.getOperand(1).getOpcode() == ISD::Constant &&
3126 N1.getOperand(1).getOpcode() == ISD::Constant &&
3127 // Don't increase # computations.
3128 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3129 // We can only do this xform if we know that bits from X that are set in C2
3130 // but not in C1 are already zero. Likewise for Y.
3131 const APInt &LHSMask =
3132 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3133 const APInt &RHSMask =
3134 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3136 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3137 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3138 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3139 N0.getOperand(0), N1.getOperand(0));
3140 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
3141 DAG.getConstant(LHSMask | RHSMask, VT));
3145 // See if this is some rotate idiom.
3146 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
3147 return SDValue(Rot, 0);
3149 // Simplify the operands using demanded-bits information.
3150 if (!VT.isVector() &&
3151 SimplifyDemandedBits(SDValue(N, 0)))
3152 return SDValue(N, 0);
3157 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
3158 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3159 if (Op.getOpcode() == ISD::AND) {
3160 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3161 Mask = Op.getOperand(1);
3162 Op = Op.getOperand(0);
3168 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3176 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3177 // idioms for rotate, and if the target supports rotation instructions, generate
3179 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
3180 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3181 EVT VT = LHS.getValueType();
3182 if (!TLI.isTypeLegal(VT)) return 0;
3184 // The target must have at least one rotate flavor.
3185 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3186 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3187 if (!HasROTL && !HasROTR) return 0;
3189 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3190 SDValue LHSShift; // The shift.
3191 SDValue LHSMask; // AND value if any.
3192 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3193 return 0; // Not part of a rotate.
3195 SDValue RHSShift; // The shift.
3196 SDValue RHSMask; // AND value if any.
3197 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3198 return 0; // Not part of a rotate.
3200 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3201 return 0; // Not shifting the same value.
3203 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3204 return 0; // Shifts must disagree.
3206 // Canonicalize shl to left side in a shl/srl pair.
3207 if (RHSShift.getOpcode() == ISD::SHL) {
3208 std::swap(LHS, RHS);
3209 std::swap(LHSShift, RHSShift);
3210 std::swap(LHSMask , RHSMask );
3213 unsigned OpSizeInBits = VT.getSizeInBits();
3214 SDValue LHSShiftArg = LHSShift.getOperand(0);
3215 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3216 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3218 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3219 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3220 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3221 RHSShiftAmt.getOpcode() == ISD::Constant) {
3222 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3223 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3224 if ((LShVal + RShVal) != OpSizeInBits)
3227 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3228 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
3230 // If there is an AND of either shifted operand, apply it to the result.
3231 if (LHSMask.getNode() || RHSMask.getNode()) {
3232 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3234 if (LHSMask.getNode()) {
3235 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3236 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3238 if (RHSMask.getNode()) {
3239 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3240 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3243 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3246 return Rot.getNode();
3249 // If there is a mask here, and we have a variable shift, we can't be sure
3250 // that we're masking out the right stuff.
3251 if (LHSMask.getNode() || RHSMask.getNode())
3254 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
3255 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
3256 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
3257 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
3258 if (ConstantSDNode *SUBC =
3259 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
3260 if (SUBC->getAPIntValue() == OpSizeInBits) {
3261 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg,
3262 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3267 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
3268 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
3269 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
3270 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
3271 if (ConstantSDNode *SUBC =
3272 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
3273 if (SUBC->getAPIntValue() == OpSizeInBits) {
3274 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg,
3275 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3280 // Look for sign/zext/any-extended or truncate cases:
3281 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3282 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3283 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3284 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3285 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3286 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3287 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3288 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3289 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
3290 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
3291 if (RExtOp0.getOpcode() == ISD::SUB &&
3292 RExtOp0.getOperand(1) == LExtOp0) {
3293 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3295 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3296 // (rotr x, (sub 32, y))
3297 if (ConstantSDNode *SUBC =
3298 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3299 if (SUBC->getAPIntValue() == OpSizeInBits) {
3300 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3302 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3305 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3306 RExtOp0 == LExtOp0.getOperand(1)) {
3307 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3309 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3310 // (rotl x, (sub 32, y))
3311 if (ConstantSDNode *SUBC =
3312 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3313 if (SUBC->getAPIntValue() == OpSizeInBits) {
3314 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3316 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3325 SDValue DAGCombiner::visitXOR(SDNode *N) {
3326 SDValue N0 = N->getOperand(0);
3327 SDValue N1 = N->getOperand(1);
3328 SDValue LHS, RHS, CC;
3329 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3330 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3331 EVT VT = N0.getValueType();
3334 if (VT.isVector()) {
3335 SDValue FoldedVOp = SimplifyVBinOp(N);
3336 if (FoldedVOp.getNode()) return FoldedVOp;
3339 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3340 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3341 return DAG.getConstant(0, VT);
3342 // fold (xor x, undef) -> undef
3343 if (N0.getOpcode() == ISD::UNDEF)
3345 if (N1.getOpcode() == ISD::UNDEF)
3347 // fold (xor c1, c2) -> c1^c2
3349 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3350 // canonicalize constant to RHS
3352 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3353 // fold (xor x, 0) -> x
3354 if (N1C && N1C->isNullValue())
3357 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3358 if (RXOR.getNode() != 0)
3361 // fold !(x cc y) -> (x !cc y)
3362 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3363 bool isInt = LHS.getValueType().isInteger();
3364 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3367 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
3368 switch (N0.getOpcode()) {
3370 llvm_unreachable("Unhandled SetCC Equivalent!");
3372 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
3373 case ISD::SELECT_CC:
3374 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
3375 N0.getOperand(3), NotCC);
3380 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3381 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3382 N0.getNode()->hasOneUse() &&
3383 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3384 SDValue V = N0.getOperand(0);
3385 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3386 DAG.getConstant(1, V.getValueType()));
3387 AddToWorkList(V.getNode());
3388 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
3391 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3392 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3393 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3394 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3395 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3396 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3397 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3398 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3399 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3400 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3403 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3404 if (N1C && N1C->isAllOnesValue() &&
3405 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3406 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3407 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3408 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3409 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3410 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3411 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3412 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3415 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3416 if (N1C && N0.getOpcode() == ISD::XOR) {
3417 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3418 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3420 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3421 DAG.getConstant(N1C->getAPIntValue() ^
3422 N00C->getAPIntValue(), VT));
3424 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3425 DAG.getConstant(N1C->getAPIntValue() ^
3426 N01C->getAPIntValue(), VT));
3428 // fold (xor x, x) -> 0
3430 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
3432 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3433 if (N0.getOpcode() == N1.getOpcode()) {
3434 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3435 if (Tmp.getNode()) return Tmp;
3438 // Simplify the expression using non-local knowledge.
3439 if (!VT.isVector() &&
3440 SimplifyDemandedBits(SDValue(N, 0)))
3441 return SDValue(N, 0);
3446 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3447 /// the shift amount is a constant.
3448 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3449 SDNode *LHS = N->getOperand(0).getNode();
3450 if (!LHS->hasOneUse()) return SDValue();
3452 // We want to pull some binops through shifts, so that we have (and (shift))
3453 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3454 // thing happens with address calculations, so it's important to canonicalize
3456 bool HighBitSet = false; // Can we transform this if the high bit is set?
3458 switch (LHS->getOpcode()) {
3459 default: return SDValue();
3462 HighBitSet = false; // We can only transform sra if the high bit is clear.
3465 HighBitSet = true; // We can only transform sra if the high bit is set.
3468 if (N->getOpcode() != ISD::SHL)
3469 return SDValue(); // only shl(add) not sr[al](add).
3470 HighBitSet = false; // We can only transform sra if the high bit is clear.
3474 // We require the RHS of the binop to be a constant as well.
3475 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3476 if (!BinOpCst) return SDValue();
3478 // FIXME: disable this unless the input to the binop is a shift by a constant.
3479 // If it is not a shift, it pessimizes some common cases like:
3481 // void foo(int *X, int i) { X[i & 1235] = 1; }
3482 // int bar(int *X, int i) { return X[i & 255]; }
3483 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3484 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3485 BinOpLHSVal->getOpcode() != ISD::SRA &&
3486 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3487 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3490 EVT VT = N->getValueType(0);
3492 // If this is a signed shift right, and the high bit is modified by the
3493 // logical operation, do not perform the transformation. The highBitSet
3494 // boolean indicates the value of the high bit of the constant which would
3495 // cause it to be modified for this operation.
3496 if (N->getOpcode() == ISD::SRA) {
3497 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3498 if (BinOpRHSSignSet != HighBitSet)
3502 // Fold the constants, shifting the binop RHS by the shift amount.
3503 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
3505 LHS->getOperand(1), N->getOperand(1));
3507 // Create the new shift.
3508 SDValue NewShift = DAG.getNode(N->getOpcode(),
3509 LHS->getOperand(0).getDebugLoc(),
3510 VT, LHS->getOperand(0), N->getOperand(1));
3512 // Create the new binop.
3513 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
3516 SDValue DAGCombiner::visitSHL(SDNode *N) {
3517 SDValue N0 = N->getOperand(0);
3518 SDValue N1 = N->getOperand(1);
3519 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3520 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3521 EVT VT = N0.getValueType();
3522 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3524 // fold (shl c1, c2) -> c1<<c2
3526 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3527 // fold (shl 0, x) -> 0
3528 if (N0C && N0C->isNullValue())
3530 // fold (shl x, c >= size(x)) -> undef
3531 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3532 return DAG.getUNDEF(VT);
3533 // fold (shl x, 0) -> x
3534 if (N1C && N1C->isNullValue())
3536 // fold (shl undef, x) -> 0
3537 if (N0.getOpcode() == ISD::UNDEF)
3538 return DAG.getConstant(0, VT);
3539 // if (shl x, c) is known to be zero, return 0
3540 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3541 APInt::getAllOnesValue(OpSizeInBits)))
3542 return DAG.getConstant(0, VT);
3543 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3544 if (N1.getOpcode() == ISD::TRUNCATE &&
3545 N1.getOperand(0).getOpcode() == ISD::AND &&
3546 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3547 SDValue N101 = N1.getOperand(0).getOperand(1);
3548 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3549 EVT TruncVT = N1.getValueType();
3550 SDValue N100 = N1.getOperand(0).getOperand(0);
3551 APInt TruncC = N101C->getAPIntValue();
3552 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3553 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3554 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3555 DAG.getNode(ISD::TRUNCATE,
3558 DAG.getConstant(TruncC, TruncVT)));
3562 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3563 return SDValue(N, 0);
3565 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3566 if (N1C && N0.getOpcode() == ISD::SHL &&
3567 N0.getOperand(1).getOpcode() == ISD::Constant) {
3568 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3569 uint64_t c2 = N1C->getZExtValue();
3570 if (c1 + c2 >= OpSizeInBits)
3571 return DAG.getConstant(0, VT);
3572 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3573 DAG.getConstant(c1 + c2, N1.getValueType()));
3576 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3577 // For this to be valid, the second form must not preserve any of the bits
3578 // that are shifted out by the inner shift in the first form. This means
3579 // the outer shift size must be >= the number of bits added by the ext.
3580 // As a corollary, we don't care what kind of ext it is.
3581 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3582 N0.getOpcode() == ISD::ANY_EXTEND ||
3583 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3584 N0.getOperand(0).getOpcode() == ISD::SHL &&
3585 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3587 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3588 uint64_t c2 = N1C->getZExtValue();
3589 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3590 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3591 if (c2 >= OpSizeInBits - InnerShiftSize) {
3592 if (c1 + c2 >= OpSizeInBits)
3593 return DAG.getConstant(0, VT);
3594 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3595 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3596 N0.getOperand(0)->getOperand(0)),
3597 DAG.getConstant(c1 + c2, N1.getValueType()));
3601 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3602 // (and (srl x, (sub c1, c2), MASK)
3603 // Only fold this if the inner shift has no other uses -- if it does, folding
3604 // this will increase the total number of instructions.
3605 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3606 N0.getOperand(1).getOpcode() == ISD::Constant) {
3607 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3608 if (c1 < VT.getSizeInBits()) {
3609 uint64_t c2 = N1C->getZExtValue();
3610 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3611 VT.getSizeInBits() - c1);
3614 Mask = Mask.shl(c2-c1);
3615 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3616 DAG.getConstant(c2-c1, N1.getValueType()));
3618 Mask = Mask.lshr(c1-c2);
3619 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3620 DAG.getConstant(c1-c2, N1.getValueType()));
3622 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3623 DAG.getConstant(Mask, VT));
3626 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3627 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3628 SDValue HiBitsMask =
3629 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3630 VT.getSizeInBits() -
3631 N1C->getZExtValue()),
3633 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3638 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3639 if (NewSHL.getNode())
3646 SDValue DAGCombiner::visitSRA(SDNode *N) {
3647 SDValue N0 = N->getOperand(0);
3648 SDValue N1 = N->getOperand(1);
3649 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3650 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3651 EVT VT = N0.getValueType();
3652 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3654 // fold (sra c1, c2) -> (sra c1, c2)
3656 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3657 // fold (sra 0, x) -> 0
3658 if (N0C && N0C->isNullValue())
3660 // fold (sra -1, x) -> -1
3661 if (N0C && N0C->isAllOnesValue())
3663 // fold (sra x, (setge c, size(x))) -> undef
3664 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3665 return DAG.getUNDEF(VT);
3666 // fold (sra x, 0) -> x
3667 if (N1C && N1C->isNullValue())
3669 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3671 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3672 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3673 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3675 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3676 ExtVT, VT.getVectorNumElements());
3677 if ((!LegalOperations ||
3678 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3679 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3680 N0.getOperand(0), DAG.getValueType(ExtVT));
3683 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3684 if (N1C && N0.getOpcode() == ISD::SRA) {
3685 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3686 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3687 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3688 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3689 DAG.getConstant(Sum, N1C->getValueType(0)));
3693 // fold (sra (shl X, m), (sub result_size, n))
3694 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3695 // result_size - n != m.
3696 // If truncate is free for the target sext(shl) is likely to result in better
3698 if (N0.getOpcode() == ISD::SHL) {
3699 // Get the two constanst of the shifts, CN0 = m, CN = n.
3700 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3702 // Determine what the truncate's result bitsize and type would be.
3704 EVT::getIntegerVT(*DAG.getContext(),
3705 OpSizeInBits - N1C->getZExtValue());
3706 // Determine the residual right-shift amount.
3707 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3709 // If the shift is not a no-op (in which case this should be just a sign
3710 // extend already), the truncated to type is legal, sign_extend is legal
3711 // on that type, and the truncate to that type is both legal and free,
3712 // perform the transform.
3713 if ((ShiftAmt > 0) &&
3714 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3715 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3716 TLI.isTruncateFree(VT, TruncVT)) {
3718 SDValue Amt = DAG.getConstant(ShiftAmt,
3719 getShiftAmountTy(N0.getOperand(0).getValueType()));
3720 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3721 N0.getOperand(0), Amt);
3722 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3724 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3725 N->getValueType(0), Trunc);
3730 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3731 if (N1.getOpcode() == ISD::TRUNCATE &&
3732 N1.getOperand(0).getOpcode() == ISD::AND &&
3733 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3734 SDValue N101 = N1.getOperand(0).getOperand(1);
3735 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3736 EVT TruncVT = N1.getValueType();
3737 SDValue N100 = N1.getOperand(0).getOperand(0);
3738 APInt TruncC = N101C->getAPIntValue();
3739 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3740 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3741 DAG.getNode(ISD::AND, N->getDebugLoc(),
3743 DAG.getNode(ISD::TRUNCATE,
3746 DAG.getConstant(TruncC, TruncVT)));
3750 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3751 // if c1 is equal to the number of bits the trunc removes
3752 if (N0.getOpcode() == ISD::TRUNCATE &&
3753 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3754 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3755 N0.getOperand(0).hasOneUse() &&
3756 N0.getOperand(0).getOperand(1).hasOneUse() &&
3757 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3758 EVT LargeVT = N0.getOperand(0).getValueType();
3759 ConstantSDNode *LargeShiftAmt =
3760 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3762 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3763 LargeShiftAmt->getZExtValue()) {
3765 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3766 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3767 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3768 N0.getOperand(0).getOperand(0), Amt);
3769 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3773 // Simplify, based on bits shifted out of the LHS.
3774 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3775 return SDValue(N, 0);
3778 // If the sign bit is known to be zero, switch this to a SRL.
3779 if (DAG.SignBitIsZero(N0))
3780 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3783 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3784 if (NewSRA.getNode())
3791 SDValue DAGCombiner::visitSRL(SDNode *N) {
3792 SDValue N0 = N->getOperand(0);
3793 SDValue N1 = N->getOperand(1);
3794 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3795 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3796 EVT VT = N0.getValueType();
3797 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3799 // fold (srl c1, c2) -> c1 >>u c2
3801 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3802 // fold (srl 0, x) -> 0
3803 if (N0C && N0C->isNullValue())
3805 // fold (srl x, c >= size(x)) -> undef
3806 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3807 return DAG.getUNDEF(VT);
3808 // fold (srl x, 0) -> x
3809 if (N1C && N1C->isNullValue())
3811 // if (srl x, c) is known to be zero, return 0
3812 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3813 APInt::getAllOnesValue(OpSizeInBits)))
3814 return DAG.getConstant(0, VT);
3816 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3817 if (N1C && N0.getOpcode() == ISD::SRL &&
3818 N0.getOperand(1).getOpcode() == ISD::Constant) {
3819 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3820 uint64_t c2 = N1C->getZExtValue();
3821 if (c1 + c2 >= OpSizeInBits)
3822 return DAG.getConstant(0, VT);
3823 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3824 DAG.getConstant(c1 + c2, N1.getValueType()));
3827 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3828 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3829 N0.getOperand(0).getOpcode() == ISD::SRL &&
3830 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3832 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3833 uint64_t c2 = N1C->getZExtValue();
3834 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3835 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3836 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3837 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3838 if (c1 + OpSizeInBits == InnerShiftSize) {
3839 if (c1 + c2 >= InnerShiftSize)
3840 return DAG.getConstant(0, VT);
3841 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3842 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3843 N0.getOperand(0)->getOperand(0),
3844 DAG.getConstant(c1 + c2, ShiftCountVT)));
3848 // fold (srl (shl x, c), c) -> (and x, cst2)
3849 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3850 N0.getValueSizeInBits() <= 64) {
3851 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3852 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3853 DAG.getConstant(~0ULL >> ShAmt, VT));
3857 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3858 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3859 // Shifting in all undef bits?
3860 EVT SmallVT = N0.getOperand(0).getValueType();
3861 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3862 return DAG.getUNDEF(VT);
3864 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3865 uint64_t ShiftAmt = N1C->getZExtValue();
3866 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3868 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3869 AddToWorkList(SmallShift.getNode());
3870 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3874 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3875 // bit, which is unmodified by sra.
3876 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3877 if (N0.getOpcode() == ISD::SRA)
3878 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3881 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3882 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3883 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3884 APInt KnownZero, KnownOne;
3885 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne);
3887 // If any of the input bits are KnownOne, then the input couldn't be all
3888 // zeros, thus the result of the srl will always be zero.
3889 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3891 // If all of the bits input the to ctlz node are known to be zero, then
3892 // the result of the ctlz is "32" and the result of the shift is one.
3893 APInt UnknownBits = ~KnownZero;
3894 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3896 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3897 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3898 // Okay, we know that only that the single bit specified by UnknownBits
3899 // could be set on input to the CTLZ node. If this bit is set, the SRL
3900 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3901 // to an SRL/XOR pair, which is likely to simplify more.
3902 unsigned ShAmt = UnknownBits.countTrailingZeros();
3903 SDValue Op = N0.getOperand(0);
3906 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3907 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3908 AddToWorkList(Op.getNode());
3911 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3912 Op, DAG.getConstant(1, VT));
3916 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3917 if (N1.getOpcode() == ISD::TRUNCATE &&
3918 N1.getOperand(0).getOpcode() == ISD::AND &&
3919 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3920 SDValue N101 = N1.getOperand(0).getOperand(1);
3921 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3922 EVT TruncVT = N1.getValueType();
3923 SDValue N100 = N1.getOperand(0).getOperand(0);
3924 APInt TruncC = N101C->getAPIntValue();
3925 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3926 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3927 DAG.getNode(ISD::AND, N->getDebugLoc(),
3929 DAG.getNode(ISD::TRUNCATE,
3932 DAG.getConstant(TruncC, TruncVT)));
3936 // fold operands of srl based on knowledge that the low bits are not
3938 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3939 return SDValue(N, 0);
3942 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3943 if (NewSRL.getNode())
3947 // Attempt to convert a srl of a load into a narrower zero-extending load.
3948 SDValue NarrowLoad = ReduceLoadWidth(N);
3949 if (NarrowLoad.getNode())
3952 // Here is a common situation. We want to optimize:
3955 // %b = and i32 %a, 2
3956 // %c = srl i32 %b, 1
3957 // brcond i32 %c ...
3963 // %c = setcc eq %b, 0
3966 // However when after the source operand of SRL is optimized into AND, the SRL
3967 // itself may not be optimized further. Look for it and add the BRCOND into
3969 if (N->hasOneUse()) {
3970 SDNode *Use = *N->use_begin();
3971 if (Use->getOpcode() == ISD::BRCOND)
3973 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3974 // Also look pass the truncate.
3975 Use = *Use->use_begin();
3976 if (Use->getOpcode() == ISD::BRCOND)
3984 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3985 SDValue N0 = N->getOperand(0);
3986 EVT VT = N->getValueType(0);
3988 // fold (ctlz c1) -> c2
3989 if (isa<ConstantSDNode>(N0))
3990 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3994 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
3995 SDValue N0 = N->getOperand(0);
3996 EVT VT = N->getValueType(0);
3998 // fold (ctlz_zero_undef c1) -> c2
3999 if (isa<ConstantSDNode>(N0))
4000 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
4004 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
4005 SDValue N0 = N->getOperand(0);
4006 EVT VT = N->getValueType(0);
4008 // fold (cttz c1) -> c2
4009 if (isa<ConstantSDNode>(N0))
4010 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
4014 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
4015 SDValue N0 = N->getOperand(0);
4016 EVT VT = N->getValueType(0);
4018 // fold (cttz_zero_undef c1) -> c2
4019 if (isa<ConstantSDNode>(N0))
4020 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
4024 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4025 SDValue N0 = N->getOperand(0);
4026 EVT VT = N->getValueType(0);
4028 // fold (ctpop c1) -> c2
4029 if (isa<ConstantSDNode>(N0))
4030 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
4034 SDValue DAGCombiner::visitSELECT(SDNode *N) {
4035 SDValue N0 = N->getOperand(0);
4036 SDValue N1 = N->getOperand(1);
4037 SDValue N2 = N->getOperand(2);
4038 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4039 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4040 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
4041 EVT VT = N->getValueType(0);
4042 EVT VT0 = N0.getValueType();
4044 // fold (select C, X, X) -> X
4047 // fold (select true, X, Y) -> X
4048 if (N0C && !N0C->isNullValue())
4050 // fold (select false, X, Y) -> Y
4051 if (N0C && N0C->isNullValue())
4053 // fold (select C, 1, X) -> (or C, X)
4054 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
4055 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4056 // fold (select C, 0, 1) -> (xor C, 1)
4057 if (VT.isInteger() &&
4060 TLI.getBooleanContents(false) ==
4061 TargetLowering::ZeroOrOneBooleanContent)) &&
4062 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
4065 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
4066 N0, DAG.getConstant(1, VT0));
4067 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
4068 N0, DAG.getConstant(1, VT0));
4069 AddToWorkList(XORNode.getNode());
4071 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
4072 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
4074 // fold (select C, 0, X) -> (and (not C), X)
4075 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
4076 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
4077 AddToWorkList(NOTNode.getNode());
4078 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
4080 // fold (select C, X, 1) -> (or (not C), X)
4081 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
4082 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
4083 AddToWorkList(NOTNode.getNode());
4084 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
4086 // fold (select C, X, 0) -> (and C, X)
4087 if (VT == MVT::i1 && N2C && N2C->isNullValue())
4088 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4089 // fold (select X, X, Y) -> (or X, Y)
4090 // fold (select X, 1, Y) -> (or X, Y)
4091 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4092 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4093 // fold (select X, Y, X) -> (and X, Y)
4094 // fold (select X, Y, 0) -> (and X, Y)
4095 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4096 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4098 // If we can fold this based on the true/false value, do so.
4099 if (SimplifySelectOps(N, N1, N2))
4100 return SDValue(N, 0); // Don't revisit N.
4102 // fold selects based on a setcc into other things, such as min/max/abs
4103 if (N0.getOpcode() == ISD::SETCC) {
4105 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
4106 // having to say they don't support SELECT_CC on every type the DAG knows
4107 // about, since there is no way to mark an opcode illegal at all value types
4108 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
4109 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
4110 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
4111 N0.getOperand(0), N0.getOperand(1),
4112 N1, N2, N0.getOperand(2));
4113 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
4119 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
4120 SDValue N0 = N->getOperand(0);
4121 SDValue N1 = N->getOperand(1);
4122 SDValue N2 = N->getOperand(2);
4123 SDValue N3 = N->getOperand(3);
4124 SDValue N4 = N->getOperand(4);
4125 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
4127 // fold select_cc lhs, rhs, x, x, cc -> x
4131 // Determine if the condition we're dealing with is constant
4132 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
4133 N0, N1, CC, N->getDebugLoc(), false);
4134 if (SCC.getNode()) AddToWorkList(SCC.getNode());
4136 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
4137 if (!SCCC->isNullValue())
4138 return N2; // cond always true -> true val
4140 return N3; // cond always false -> false val
4143 // Fold to a simpler select_cc
4144 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
4145 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
4146 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
4149 // If we can fold this based on the true/false value, do so.
4150 if (SimplifySelectOps(N, N2, N3))
4151 return SDValue(N, 0); // Don't revisit N.
4153 // fold select_cc into other things, such as min/max/abs
4154 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
4157 SDValue DAGCombiner::visitSETCC(SDNode *N) {
4158 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
4159 cast<CondCodeSDNode>(N->getOperand(2))->get(),
4163 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
4164 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
4165 // transformation. Returns true if extension are possible and the above
4166 // mentioned transformation is profitable.
4167 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
4169 SmallVector<SDNode*, 4> &ExtendNodes,
4170 const TargetLowering &TLI) {
4171 bool HasCopyToRegUses = false;
4172 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
4173 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4174 UE = N0.getNode()->use_end();
4179 if (UI.getUse().getResNo() != N0.getResNo())
4181 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
4182 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4183 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
4184 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
4185 // Sign bits will be lost after a zext.
4188 for (unsigned i = 0; i != 2; ++i) {
4189 SDValue UseOp = User->getOperand(i);
4192 if (!isa<ConstantSDNode>(UseOp))
4197 ExtendNodes.push_back(User);
4200 // If truncates aren't free and there are users we can't
4201 // extend, it isn't worthwhile.
4204 // Remember if this value is live-out.
4205 if (User->getOpcode() == ISD::CopyToReg)
4206 HasCopyToRegUses = true;
4209 if (HasCopyToRegUses) {
4210 bool BothLiveOut = false;
4211 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4213 SDUse &Use = UI.getUse();
4214 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4220 // Both unextended and extended values are live out. There had better be
4221 // a good reason for the transformation.
4222 return ExtendNodes.size();
4227 void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
4228 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
4229 ISD::NodeType ExtType) {
4230 // Extend SetCC uses if necessary.
4231 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4232 SDNode *SetCC = SetCCs[i];
4233 SmallVector<SDValue, 4> Ops;
4235 for (unsigned j = 0; j != 2; ++j) {
4236 SDValue SOp = SetCC->getOperand(j);
4238 Ops.push_back(ExtLoad);
4240 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
4243 Ops.push_back(SetCC->getOperand(2));
4244 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
4245 &Ops[0], Ops.size()));
4249 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
4250 SDValue N0 = N->getOperand(0);
4251 EVT VT = N->getValueType(0);
4253 // fold (sext c1) -> c1
4254 if (isa<ConstantSDNode>(N0))
4255 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
4257 // fold (sext (sext x)) -> (sext x)
4258 // fold (sext (aext x)) -> (sext x)
4259 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4260 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
4263 if (N0.getOpcode() == ISD::TRUNCATE) {
4264 // fold (sext (truncate (load x))) -> (sext (smaller load x))
4265 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
4266 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4267 if (NarrowLoad.getNode()) {
4268 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4269 if (NarrowLoad.getNode() != N0.getNode()) {
4270 CombineTo(N0.getNode(), NarrowLoad);
4271 // CombineTo deleted the truncate, if needed, but not what's under it.
4274 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4277 // See if the value being truncated is already sign extended. If so, just
4278 // eliminate the trunc/sext pair.
4279 SDValue Op = N0.getOperand(0);
4280 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
4281 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
4282 unsigned DestBits = VT.getScalarType().getSizeInBits();
4283 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
4285 if (OpBits == DestBits) {
4286 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
4287 // bits, it is already ready.
4288 if (NumSignBits > DestBits-MidBits)
4290 } else if (OpBits < DestBits) {
4291 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
4292 // bits, just sext from i32.
4293 if (NumSignBits > OpBits-MidBits)
4294 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
4296 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
4297 // bits, just truncate to i32.
4298 if (NumSignBits > OpBits-MidBits)
4299 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4302 // fold (sext (truncate x)) -> (sextinreg x).
4303 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4304 N0.getValueType())) {
4305 if (OpBits < DestBits)
4306 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4307 else if (OpBits > DestBits)
4308 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4309 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
4310 DAG.getValueType(N0.getValueType()));
4314 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4315 // None of the supported targets knows how to perform load and sign extend
4316 // on vectors in one instruction. We only perform this transformation on
4318 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4319 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4320 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4321 bool DoXform = true;
4322 SmallVector<SDNode*, 4> SetCCs;
4323 if (!N0.hasOneUse())
4324 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4326 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4327 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4329 LN0->getBasePtr(), LN0->getPointerInfo(),
4331 LN0->isVolatile(), LN0->isNonTemporal(),
4332 LN0->getAlignment());
4333 CombineTo(N, ExtLoad);
4334 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4335 N0.getValueType(), ExtLoad);
4336 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4337 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4339 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4343 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4344 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4345 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4346 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4347 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4348 EVT MemVT = LN0->getMemoryVT();
4349 if ((!LegalOperations && !LN0->isVolatile()) ||
4350 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4351 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4353 LN0->getBasePtr(), LN0->getPointerInfo(),
4355 LN0->isVolatile(), LN0->isNonTemporal(),
4356 LN0->getAlignment());
4357 CombineTo(N, ExtLoad);
4358 CombineTo(N0.getNode(),
4359 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4360 N0.getValueType(), ExtLoad),
4361 ExtLoad.getValue(1));
4362 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4366 // fold (sext (and/or/xor (load x), cst)) ->
4367 // (and/or/xor (sextload x), (sext cst))
4368 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4369 N0.getOpcode() == ISD::XOR) &&
4370 isa<LoadSDNode>(N0.getOperand(0)) &&
4371 N0.getOperand(1).getOpcode() == ISD::Constant &&
4372 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4373 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4374 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4375 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4376 bool DoXform = true;
4377 SmallVector<SDNode*, 4> SetCCs;
4378 if (!N0.hasOneUse())
4379 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4382 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4383 LN0->getChain(), LN0->getBasePtr(),
4384 LN0->getPointerInfo(),
4387 LN0->isNonTemporal(),
4388 LN0->getAlignment());
4389 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4390 Mask = Mask.sext(VT.getSizeInBits());
4391 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4392 ExtLoad, DAG.getConstant(Mask, VT));
4393 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4394 N0.getOperand(0).getDebugLoc(),
4395 N0.getOperand(0).getValueType(), ExtLoad);
4397 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4398 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4400 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4405 if (N0.getOpcode() == ISD::SETCC) {
4406 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4407 // Only do this before legalize for now.
4408 if (VT.isVector() && !LegalOperations) {
4409 EVT N0VT = N0.getOperand(0).getValueType();
4410 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
4411 // of the same size as the compared operands. Only optimize sext(setcc())
4412 // if this is the case.
4413 EVT SVT = TLI.getSetCCResultType(N0VT);
4415 // We know that the # elements of the results is the same as the
4416 // # elements of the compare (and the # elements of the compare result
4417 // for that matter). Check to see that they are the same size. If so,
4418 // we know that the element size of the sext'd result matches the
4419 // element size of the compare operands.
4420 if (VT.getSizeInBits() == SVT.getSizeInBits())
4421 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4423 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4424 // If the desired elements are smaller or larger than the source
4425 // elements we can use a matching integer vector type and then
4426 // truncate/sign extend
4427 EVT MatchingElementType =
4428 EVT::getIntegerVT(*DAG.getContext(),
4429 N0VT.getScalarType().getSizeInBits());
4430 EVT MatchingVectorType =
4431 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4432 N0VT.getVectorNumElements());
4434 if (SVT == MatchingVectorType) {
4435 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType,
4436 N0.getOperand(0), N0.getOperand(1),
4437 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4438 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4442 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4443 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4445 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4447 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4448 NegOne, DAG.getConstant(0, VT),
4449 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4450 if (SCC.getNode()) return SCC;
4451 if (!LegalOperations ||
4452 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
4453 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4454 DAG.getSetCC(N->getDebugLoc(),
4455 TLI.getSetCCResultType(VT),
4456 N0.getOperand(0), N0.getOperand(1),
4457 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4458 NegOne, DAG.getConstant(0, VT));
4461 // fold (sext x) -> (zext x) if the sign bit is known zero.
4462 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4463 DAG.SignBitIsZero(N0))
4464 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4469 // isTruncateOf - If N is a truncate of some other value, return true, record
4470 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
4471 // This function computes KnownZero to avoid a duplicated call to
4472 // ComputeMaskedBits in the caller.
4473 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
4476 if (N->getOpcode() == ISD::TRUNCATE) {
4477 Op = N->getOperand(0);
4478 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4482 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
4483 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
4486 SDValue Op0 = N->getOperand(0);
4487 SDValue Op1 = N->getOperand(1);
4488 assert(Op0.getValueType() == Op1.getValueType());
4490 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0);
4491 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
4492 if (COp0 && COp0->isNullValue())
4494 else if (COp1 && COp1->isNullValue())
4499 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4501 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
4507 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4508 SDValue N0 = N->getOperand(0);
4509 EVT VT = N->getValueType(0);
4511 // fold (zext c1) -> c1
4512 if (isa<ConstantSDNode>(N0))
4513 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4514 // fold (zext (zext x)) -> (zext x)
4515 // fold (zext (aext x)) -> (zext x)
4516 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4517 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
4520 // fold (zext (truncate x)) -> (zext x) or
4521 // (zext (truncate x)) -> (truncate x)
4522 // This is valid when the truncated bits of x are already zero.
4523 // FIXME: We should extend this to work for vectors too.
4526 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
4527 APInt TruncatedBits =
4528 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
4529 APInt(Op.getValueSizeInBits(), 0) :
4530 APInt::getBitsSet(Op.getValueSizeInBits(),
4531 N0.getValueSizeInBits(),
4532 std::min(Op.getValueSizeInBits(),
4533 VT.getSizeInBits()));
4534 if (TruncatedBits == (KnownZero & TruncatedBits)) {
4535 if (VT.bitsGT(Op.getValueType()))
4536 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op);
4537 if (VT.bitsLT(Op.getValueType()))
4538 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4544 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4545 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4546 if (N0.getOpcode() == ISD::TRUNCATE) {
4547 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4548 if (NarrowLoad.getNode()) {
4549 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4550 if (NarrowLoad.getNode() != N0.getNode()) {
4551 CombineTo(N0.getNode(), NarrowLoad);
4552 // CombineTo deleted the truncate, if needed, but not what's under it.
4555 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4559 // fold (zext (truncate x)) -> (and x, mask)
4560 if (N0.getOpcode() == ISD::TRUNCATE &&
4561 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4563 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4564 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4565 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4566 if (NarrowLoad.getNode()) {
4567 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4568 if (NarrowLoad.getNode() != N0.getNode()) {
4569 CombineTo(N0.getNode(), NarrowLoad);
4570 // CombineTo deleted the truncate, if needed, but not what's under it.
4573 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4576 SDValue Op = N0.getOperand(0);
4577 if (Op.getValueType().bitsLT(VT)) {
4578 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
4579 AddToWorkList(Op.getNode());
4580 } else if (Op.getValueType().bitsGT(VT)) {
4581 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4582 AddToWorkList(Op.getNode());
4584 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
4585 N0.getValueType().getScalarType());
4588 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4589 // if either of the casts is not free.
4590 if (N0.getOpcode() == ISD::AND &&
4591 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4592 N0.getOperand(1).getOpcode() == ISD::Constant &&
4593 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4594 N0.getValueType()) ||
4595 !TLI.isZExtFree(N0.getValueType(), VT))) {
4596 SDValue X = N0.getOperand(0).getOperand(0);
4597 if (X.getValueType().bitsLT(VT)) {
4598 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
4599 } else if (X.getValueType().bitsGT(VT)) {
4600 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4602 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4603 Mask = Mask.zext(VT.getSizeInBits());
4604 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4605 X, DAG.getConstant(Mask, VT));
4608 // fold (zext (load x)) -> (zext (truncate (zextload x)))
4609 // None of the supported targets knows how to perform load and vector_zext
4610 // on vectors in one instruction. We only perform this transformation on
4612 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4613 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4614 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4615 bool DoXform = true;
4616 SmallVector<SDNode*, 4> SetCCs;
4617 if (!N0.hasOneUse())
4618 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4620 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4621 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4623 LN0->getBasePtr(), LN0->getPointerInfo(),
4625 LN0->isVolatile(), LN0->isNonTemporal(),
4626 LN0->getAlignment());
4627 CombineTo(N, ExtLoad);
4628 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4629 N0.getValueType(), ExtLoad);
4630 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4632 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4634 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4638 // fold (zext (and/or/xor (load x), cst)) ->
4639 // (and/or/xor (zextload x), (zext cst))
4640 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4641 N0.getOpcode() == ISD::XOR) &&
4642 isa<LoadSDNode>(N0.getOperand(0)) &&
4643 N0.getOperand(1).getOpcode() == ISD::Constant &&
4644 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4645 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4646 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4647 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4648 bool DoXform = true;
4649 SmallVector<SDNode*, 4> SetCCs;
4650 if (!N0.hasOneUse())
4651 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4654 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
4655 LN0->getChain(), LN0->getBasePtr(),
4656 LN0->getPointerInfo(),
4659 LN0->isNonTemporal(),
4660 LN0->getAlignment());
4661 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4662 Mask = Mask.zext(VT.getSizeInBits());
4663 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4664 ExtLoad, DAG.getConstant(Mask, VT));
4665 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4666 N0.getOperand(0).getDebugLoc(),
4667 N0.getOperand(0).getValueType(), ExtLoad);
4669 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4670 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4672 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4677 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4678 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4679 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4680 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4681 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4682 EVT MemVT = LN0->getMemoryVT();
4683 if ((!LegalOperations && !LN0->isVolatile()) ||
4684 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4685 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4687 LN0->getBasePtr(), LN0->getPointerInfo(),
4689 LN0->isVolatile(), LN0->isNonTemporal(),
4690 LN0->getAlignment());
4691 CombineTo(N, ExtLoad);
4692 CombineTo(N0.getNode(),
4693 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4695 ExtLoad.getValue(1));
4696 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4700 if (N0.getOpcode() == ISD::SETCC) {
4701 if (!LegalOperations && VT.isVector()) {
4702 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4703 // Only do this before legalize for now.
4704 EVT N0VT = N0.getOperand(0).getValueType();
4705 EVT EltVT = VT.getVectorElementType();
4706 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4707 DAG.getConstant(1, EltVT));
4708 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4709 // We know that the # elements of the results is the same as the
4710 // # elements of the compare (and the # elements of the compare result
4711 // for that matter). Check to see that they are the same size. If so,
4712 // we know that the element size of the sext'd result matches the
4713 // element size of the compare operands.
4714 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4715 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4717 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4718 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4719 &OneOps[0], OneOps.size()));
4721 // If the desired elements are smaller or larger than the source
4722 // elements we can use a matching integer vector type and then
4723 // truncate/sign extend
4724 EVT MatchingElementType =
4725 EVT::getIntegerVT(*DAG.getContext(),
4726 N0VT.getScalarType().getSizeInBits());
4727 EVT MatchingVectorType =
4728 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4729 N0VT.getVectorNumElements());
4731 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4733 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4734 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4735 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4736 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4737 &OneOps[0], OneOps.size()));
4740 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4742 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4743 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4744 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4745 if (SCC.getNode()) return SCC;
4748 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4749 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4750 isa<ConstantSDNode>(N0.getOperand(1)) &&
4751 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4753 SDValue ShAmt = N0.getOperand(1);
4754 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4755 if (N0.getOpcode() == ISD::SHL) {
4756 SDValue InnerZExt = N0.getOperand(0);
4757 // If the original shl may be shifting out bits, do not perform this
4759 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4760 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4761 if (ShAmtVal > KnownZeroBits)
4765 DebugLoc DL = N->getDebugLoc();
4767 // Ensure that the shift amount is wide enough for the shifted value.
4768 if (VT.getSizeInBits() >= 256)
4769 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4771 return DAG.getNode(N0.getOpcode(), DL, VT,
4772 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4779 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4780 SDValue N0 = N->getOperand(0);
4781 EVT VT = N->getValueType(0);
4783 // fold (aext c1) -> c1
4784 if (isa<ConstantSDNode>(N0))
4785 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4786 // fold (aext (aext x)) -> (aext x)
4787 // fold (aext (zext x)) -> (zext x)
4788 // fold (aext (sext x)) -> (sext x)
4789 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4790 N0.getOpcode() == ISD::ZERO_EXTEND ||
4791 N0.getOpcode() == ISD::SIGN_EXTEND)
4792 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4794 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4795 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4796 if (N0.getOpcode() == ISD::TRUNCATE) {
4797 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4798 if (NarrowLoad.getNode()) {
4799 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4800 if (NarrowLoad.getNode() != N0.getNode()) {
4801 CombineTo(N0.getNode(), NarrowLoad);
4802 // CombineTo deleted the truncate, if needed, but not what's under it.
4805 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4809 // fold (aext (truncate x))
4810 if (N0.getOpcode() == ISD::TRUNCATE) {
4811 SDValue TruncOp = N0.getOperand(0);
4812 if (TruncOp.getValueType() == VT)
4813 return TruncOp; // x iff x size == zext size.
4814 if (TruncOp.getValueType().bitsGT(VT))
4815 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4816 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4819 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4820 // if the trunc is not free.
4821 if (N0.getOpcode() == ISD::AND &&
4822 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4823 N0.getOperand(1).getOpcode() == ISD::Constant &&
4824 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4825 N0.getValueType())) {
4826 SDValue X = N0.getOperand(0).getOperand(0);
4827 if (X.getValueType().bitsLT(VT)) {
4828 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4829 } else if (X.getValueType().bitsGT(VT)) {
4830 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4832 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4833 Mask = Mask.zext(VT.getSizeInBits());
4834 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4835 X, DAG.getConstant(Mask, VT));
4838 // fold (aext (load x)) -> (aext (truncate (extload x)))
4839 // None of the supported targets knows how to perform load and any_ext
4840 // on vectors in one instruction. We only perform this transformation on
4842 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4843 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4844 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4845 bool DoXform = true;
4846 SmallVector<SDNode*, 4> SetCCs;
4847 if (!N0.hasOneUse())
4848 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4850 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4851 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4853 LN0->getBasePtr(), LN0->getPointerInfo(),
4855 LN0->isVolatile(), LN0->isNonTemporal(),
4856 LN0->getAlignment());
4857 CombineTo(N, ExtLoad);
4858 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4859 N0.getValueType(), ExtLoad);
4860 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4861 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4863 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4867 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4868 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4869 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4870 if (N0.getOpcode() == ISD::LOAD &&
4871 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4873 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4874 EVT MemVT = LN0->getMemoryVT();
4875 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4876 VT, LN0->getChain(), LN0->getBasePtr(),
4877 LN0->getPointerInfo(), MemVT,
4878 LN0->isVolatile(), LN0->isNonTemporal(),
4879 LN0->getAlignment());
4880 CombineTo(N, ExtLoad);
4881 CombineTo(N0.getNode(),
4882 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4883 N0.getValueType(), ExtLoad),
4884 ExtLoad.getValue(1));
4885 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4888 if (N0.getOpcode() == ISD::SETCC) {
4889 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4890 // Only do this before legalize for now.
4891 if (VT.isVector() && !LegalOperations) {
4892 EVT N0VT = N0.getOperand(0).getValueType();
4893 // We know that the # elements of the results is the same as the
4894 // # elements of the compare (and the # elements of the compare result
4895 // for that matter). Check to see that they are the same size. If so,
4896 // we know that the element size of the sext'd result matches the
4897 // element size of the compare operands.
4898 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4899 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4901 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4902 // If the desired elements are smaller or larger than the source
4903 // elements we can use a matching integer vector type and then
4904 // truncate/sign extend
4906 EVT MatchingElementType =
4907 EVT::getIntegerVT(*DAG.getContext(),
4908 N0VT.getScalarType().getSizeInBits());
4909 EVT MatchingVectorType =
4910 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4911 N0VT.getVectorNumElements());
4913 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4915 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4916 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4920 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4922 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4923 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4924 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4932 /// GetDemandedBits - See if the specified operand can be simplified with the
4933 /// knowledge that only the bits specified by Mask are used. If so, return the
4934 /// simpler operand, otherwise return a null SDValue.
4935 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4936 switch (V.getOpcode()) {
4938 case ISD::Constant: {
4939 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
4940 assert(CV != 0 && "Const value should be ConstSDNode.");
4941 const APInt &CVal = CV->getAPIntValue();
4942 APInt NewVal = CVal & Mask;
4943 if (NewVal != CVal) {
4944 return DAG.getConstant(NewVal, V.getValueType());
4950 // If the LHS or RHS don't contribute bits to the or, drop them.
4951 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4952 return V.getOperand(1);
4953 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4954 return V.getOperand(0);
4957 // Only look at single-use SRLs.
4958 if (!V.getNode()->hasOneUse())
4960 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4961 // See if we can recursively simplify the LHS.
4962 unsigned Amt = RHSC->getZExtValue();
4964 // Watch out for shift count overflow though.
4965 if (Amt >= Mask.getBitWidth()) break;
4966 APInt NewMask = Mask << Amt;
4967 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4968 if (SimplifyLHS.getNode())
4969 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4970 SimplifyLHS, V.getOperand(1));
4976 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4977 /// bits and then truncated to a narrower type and where N is a multiple
4978 /// of number of bits of the narrower type, transform it to a narrower load
4979 /// from address + N / num of bits of new type. If the result is to be
4980 /// extended, also fold the extension to form a extending load.
4981 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4982 unsigned Opc = N->getOpcode();
4984 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4985 SDValue N0 = N->getOperand(0);
4986 EVT VT = N->getValueType(0);
4989 // This transformation isn't valid for vector loads.
4993 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4995 if (Opc == ISD::SIGN_EXTEND_INREG) {
4996 ExtType = ISD::SEXTLOAD;
4997 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4998 } else if (Opc == ISD::SRL) {
4999 // Another special-case: SRL is basically zero-extending a narrower value.
5000 ExtType = ISD::ZEXTLOAD;
5002 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5003 if (!N01) return SDValue();
5004 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
5005 VT.getSizeInBits() - N01->getZExtValue());
5007 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
5010 unsigned EVTBits = ExtVT.getSizeInBits();
5012 // Do not generate loads of non-round integer types since these can
5013 // be expensive (and would be wrong if the type is not byte sized).
5014 if (!ExtVT.isRound())
5018 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5019 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5020 ShAmt = N01->getZExtValue();
5021 // Is the shift amount a multiple of size of VT?
5022 if ((ShAmt & (EVTBits-1)) == 0) {
5023 N0 = N0.getOperand(0);
5024 // Is the load width a multiple of size of VT?
5025 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
5029 // At this point, we must have a load or else we can't do the transform.
5030 if (!isa<LoadSDNode>(N0)) return SDValue();
5032 // If the shift amount is larger than the input type then we're not
5033 // accessing any of the loaded bytes. If the load was a zextload/extload
5034 // then the result of the shift+trunc is zero/undef (handled elsewhere).
5035 // If the load was a sextload then the result is a splat of the sign bit
5036 // of the extended byte. This is not worth optimizing for.
5037 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
5042 // If the load is shifted left (and the result isn't shifted back right),
5043 // we can fold the truncate through the shift.
5044 unsigned ShLeftAmt = 0;
5045 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
5046 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
5047 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5048 ShLeftAmt = N01->getZExtValue();
5049 N0 = N0.getOperand(0);
5053 // If we haven't found a load, we can't narrow it. Don't transform one with
5054 // multiple uses, this would require adding a new load.
5055 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
5056 // Don't change the width of a volatile load.
5057 cast<LoadSDNode>(N0)->isVolatile())
5060 // Verify that we are actually reducing a load width here.
5061 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
5064 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5065 EVT PtrType = N0.getOperand(1).getValueType();
5067 if (PtrType == MVT::Untyped || PtrType.isExtended())
5068 // It's not possible to generate a constant of extended or untyped type.
5071 // For big endian targets, we need to adjust the offset to the pointer to
5072 // load the correct bytes.
5073 if (TLI.isBigEndian()) {
5074 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
5075 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
5076 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
5079 uint64_t PtrOff = ShAmt / 8;
5080 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
5081 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
5082 PtrType, LN0->getBasePtr(),
5083 DAG.getConstant(PtrOff, PtrType));
5084 AddToWorkList(NewPtr.getNode());
5087 if (ExtType == ISD::NON_EXTLOAD)
5088 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
5089 LN0->getPointerInfo().getWithOffset(PtrOff),
5090 LN0->isVolatile(), LN0->isNonTemporal(),
5091 LN0->isInvariant(), NewAlign);
5093 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
5094 LN0->getPointerInfo().getWithOffset(PtrOff),
5095 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
5098 // Replace the old load's chain with the new load's chain.
5099 WorkListRemover DeadNodes(*this);
5100 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
5102 // Shift the result left, if we've swallowed a left shift.
5103 SDValue Result = Load;
5104 if (ShLeftAmt != 0) {
5105 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
5106 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
5108 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
5109 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
5112 // Return the new loaded value.
5116 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
5117 SDValue N0 = N->getOperand(0);
5118 SDValue N1 = N->getOperand(1);
5119 EVT VT = N->getValueType(0);
5120 EVT EVT = cast<VTSDNode>(N1)->getVT();
5121 unsigned VTBits = VT.getScalarType().getSizeInBits();
5122 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
5124 // fold (sext_in_reg c1) -> c1
5125 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
5126 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
5128 // If the input is already sign extended, just drop the extension.
5129 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
5132 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
5133 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5134 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
5135 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5136 N0.getOperand(0), N1);
5139 // fold (sext_in_reg (sext x)) -> (sext x)
5140 // fold (sext_in_reg (aext x)) -> (sext x)
5141 // if x is small enough.
5142 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
5143 SDValue N00 = N0.getOperand(0);
5144 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
5145 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
5146 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
5149 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
5150 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
5151 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
5153 // fold operands of sext_in_reg based on knowledge that the top bits are not
5155 if (SimplifyDemandedBits(SDValue(N, 0)))
5156 return SDValue(N, 0);
5158 // fold (sext_in_reg (load x)) -> (smaller sextload x)
5159 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
5160 SDValue NarrowLoad = ReduceLoadWidth(N);
5161 if (NarrowLoad.getNode())
5164 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
5165 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
5166 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
5167 if (N0.getOpcode() == ISD::SRL) {
5168 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
5169 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
5170 // We can turn this into an SRA iff the input to the SRL is already sign
5172 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
5173 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
5174 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
5175 N0.getOperand(0), N0.getOperand(1));
5179 // fold (sext_inreg (extload x)) -> (sextload x)
5180 if (ISD::isEXTLoad(N0.getNode()) &&
5181 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5182 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5183 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5184 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5185 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5186 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5188 LN0->getBasePtr(), LN0->getPointerInfo(),
5190 LN0->isVolatile(), LN0->isNonTemporal(),
5191 LN0->getAlignment());
5192 CombineTo(N, ExtLoad);
5193 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5194 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5196 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
5197 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5199 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5200 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5201 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5202 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5203 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5205 LN0->getBasePtr(), LN0->getPointerInfo(),
5207 LN0->isVolatile(), LN0->isNonTemporal(),
5208 LN0->getAlignment());
5209 CombineTo(N, ExtLoad);
5210 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5211 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5214 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
5215 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5216 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5217 N0.getOperand(1), false);
5218 if (BSwap.getNode() != 0)
5219 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5226 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
5227 SDValue N0 = N->getOperand(0);
5228 EVT VT = N->getValueType(0);
5229 bool isLE = TLI.isLittleEndian();
5232 if (N0.getValueType() == N->getValueType(0))
5234 // fold (truncate c1) -> c1
5235 if (isa<ConstantSDNode>(N0))
5236 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
5237 // fold (truncate (truncate x)) -> (truncate x)
5238 if (N0.getOpcode() == ISD::TRUNCATE)
5239 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5240 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
5241 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
5242 N0.getOpcode() == ISD::SIGN_EXTEND ||
5243 N0.getOpcode() == ISD::ANY_EXTEND) {
5244 if (N0.getOperand(0).getValueType().bitsLT(VT))
5245 // if the source is smaller than the dest, we still need an extend
5246 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
5248 if (N0.getOperand(0).getValueType().bitsGT(VT))
5249 // if the source is larger than the dest, than we just need the truncate
5250 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5251 // if the source and dest are the same type, we can drop both the extend
5252 // and the truncate.
5253 return N0.getOperand(0);
5256 // Fold extract-and-trunc into a narrow extract. For example:
5257 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
5258 // i32 y = TRUNCATE(i64 x)
5260 // v16i8 b = BITCAST (v2i64 val)
5261 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
5263 // Note: We only run this optimization after type legalization (which often
5264 // creates this pattern) and before operation legalization after which
5265 // we need to be more careful about the vector instructions that we generate.
5266 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5267 LegalTypes && !LegalOperations && N0->hasOneUse()) {
5269 EVT VecTy = N0.getOperand(0).getValueType();
5270 EVT ExTy = N0.getValueType();
5271 EVT TrTy = N->getValueType(0);
5273 unsigned NumElem = VecTy.getVectorNumElements();
5274 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
5276 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
5277 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
5279 SDValue EltNo = N0->getOperand(1);
5280 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
5281 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5282 EVT IndexTy = N0->getOperand(1).getValueType();
5283 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
5285 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5286 NVT, N0.getOperand(0));
5288 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
5289 N->getDebugLoc(), TrTy, V,
5290 DAG.getConstant(Index, IndexTy));
5294 // See if we can simplify the input to this truncate through knowledge that
5295 // only the low bits are being used.
5296 // For example "trunc (or (shl x, 8), y)" // -> trunc y
5297 // Currently we only perform this optimization on scalars because vectors
5298 // may have different active low bits.
5299 if (!VT.isVector()) {
5301 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
5302 VT.getSizeInBits()));
5303 if (Shorter.getNode())
5304 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
5306 // fold (truncate (load x)) -> (smaller load x)
5307 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
5308 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
5309 SDValue Reduced = ReduceLoadWidth(N);
5310 if (Reduced.getNode())
5313 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)),
5314 // where ... are all 'undef'.
5315 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
5316 SmallVector<EVT, 8> VTs;
5319 unsigned NumDefs = 0;
5321 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
5322 SDValue X = N0.getOperand(i);
5323 if (X.getOpcode() != ISD::UNDEF) {
5328 // Stop if more than one members are non-undef.
5331 VTs.push_back(EVT::getVectorVT(*DAG.getContext(),
5332 VT.getVectorElementType(),
5333 X.getValueType().getVectorNumElements()));
5337 return DAG.getUNDEF(VT);
5340 assert(V.getNode() && "The single defined operand is empty!");
5341 SmallVector<SDValue, 8> Opnds;
5342 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
5344 Opnds.push_back(DAG.getUNDEF(VTs[i]));
5347 SDValue NV = DAG.getNode(ISD::TRUNCATE, V.getDebugLoc(), VTs[i], V);
5348 AddToWorkList(NV.getNode());
5349 Opnds.push_back(NV);
5351 return DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
5352 &Opnds[0], Opnds.size());
5356 // Simplify the operands using demanded-bits information.
5357 if (!VT.isVector() &&
5358 SimplifyDemandedBits(SDValue(N, 0)))
5359 return SDValue(N, 0);
5364 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
5365 SDValue Elt = N->getOperand(i);
5366 if (Elt.getOpcode() != ISD::MERGE_VALUES)
5367 return Elt.getNode();
5368 return Elt.getOperand(Elt.getResNo()).getNode();
5371 /// CombineConsecutiveLoads - build_pair (load, load) -> load
5372 /// if load locations are consecutive.
5373 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
5374 assert(N->getOpcode() == ISD::BUILD_PAIR);
5376 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
5377 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
5378 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
5379 LD1->getPointerInfo().getAddrSpace() !=
5380 LD2->getPointerInfo().getAddrSpace())
5382 EVT LD1VT = LD1->getValueType(0);
5384 if (ISD::isNON_EXTLoad(LD2) &&
5386 // If both are volatile this would reduce the number of volatile loads.
5387 // If one is volatile it might be ok, but play conservative and bail out.
5388 !LD1->isVolatile() &&
5389 !LD2->isVolatile() &&
5390 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
5391 unsigned Align = LD1->getAlignment();
5392 unsigned NewAlign = TLI.getDataLayout()->
5393 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5395 if (NewAlign <= Align &&
5396 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
5397 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
5398 LD1->getBasePtr(), LD1->getPointerInfo(),
5399 false, false, false, Align);
5405 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
5406 SDValue N0 = N->getOperand(0);
5407 EVT VT = N->getValueType(0);
5409 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
5410 // Only do this before legalize, since afterward the target may be depending
5411 // on the bitconvert.
5412 // First check to see if this is all constant.
5414 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
5416 bool isSimple = true;
5417 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
5418 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
5419 N0.getOperand(i).getOpcode() != ISD::Constant &&
5420 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
5425 EVT DestEltVT = N->getValueType(0).getVectorElementType();
5426 assert(!DestEltVT.isVector() &&
5427 "Element type of vector ValueType must not be vector!");
5429 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
5432 // If the input is a constant, let getNode fold it.
5433 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
5434 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
5435 if (Res.getNode() != N) {
5436 if (!LegalOperations ||
5437 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
5440 // Folding it resulted in an illegal node, and it's too late to
5441 // do that. Clean up the old node and forego the transformation.
5442 // Ideally this won't happen very often, because instcombine
5443 // and the earlier dagcombine runs (where illegal nodes are
5444 // permitted) should have folded most of them already.
5445 DAG.DeleteNode(Res.getNode());
5449 // (conv (conv x, t1), t2) -> (conv x, t2)
5450 if (N0.getOpcode() == ISD::BITCAST)
5451 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
5454 // fold (conv (load x)) -> (load (conv*)x)
5455 // If the resultant load doesn't need a higher alignment than the original!
5456 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5457 // Do not change the width of a volatile load.
5458 !cast<LoadSDNode>(N0)->isVolatile() &&
5459 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
5460 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5461 unsigned Align = TLI.getDataLayout()->
5462 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5463 unsigned OrigAlign = LN0->getAlignment();
5465 if (Align <= OrigAlign) {
5466 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
5467 LN0->getBasePtr(), LN0->getPointerInfo(),
5468 LN0->isVolatile(), LN0->isNonTemporal(),
5469 LN0->isInvariant(), OrigAlign);
5471 CombineTo(N0.getNode(),
5472 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5473 N0.getValueType(), Load),
5479 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5480 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5481 // This often reduces constant pool loads.
5482 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) ||
5483 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) &&
5484 N0.getNode()->hasOneUse() && VT.isInteger() &&
5485 !VT.isVector() && !N0.getValueType().isVector()) {
5486 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5488 AddToWorkList(NewConv.getNode());
5490 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5491 if (N0.getOpcode() == ISD::FNEG)
5492 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
5493 NewConv, DAG.getConstant(SignBit, VT));
5494 assert(N0.getOpcode() == ISD::FABS);
5495 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
5496 NewConv, DAG.getConstant(~SignBit, VT));
5499 // fold (bitconvert (fcopysign cst, x)) ->
5500 // (or (and (bitconvert x), sign), (and cst, (not sign)))
5501 // Note that we don't handle (copysign x, cst) because this can always be
5502 // folded to an fneg or fabs.
5503 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5504 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5505 VT.isInteger() && !VT.isVector()) {
5506 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5507 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5508 if (isTypeLegal(IntXVT)) {
5509 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5510 IntXVT, N0.getOperand(1));
5511 AddToWorkList(X.getNode());
5513 // If X has a different width than the result/lhs, sext it or truncate it.
5514 unsigned VTWidth = VT.getSizeInBits();
5515 if (OrigXWidth < VTWidth) {
5516 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
5517 AddToWorkList(X.getNode());
5518 } else if (OrigXWidth > VTWidth) {
5519 // To get the sign bit in the right place, we have to shift it right
5520 // before truncating.
5521 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5522 X.getValueType(), X,
5523 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5524 AddToWorkList(X.getNode());
5525 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
5526 AddToWorkList(X.getNode());
5529 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5530 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
5531 X, DAG.getConstant(SignBit, VT));
5532 AddToWorkList(X.getNode());
5534 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5535 VT, N0.getOperand(0));
5536 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
5537 Cst, DAG.getConstant(~SignBit, VT));
5538 AddToWorkList(Cst.getNode());
5540 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
5544 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5545 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5546 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5547 if (CombineLD.getNode())
5554 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5555 EVT VT = N->getValueType(0);
5556 return CombineConsecutiveLoads(N, VT);
5559 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5560 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
5561 /// destination element value type.
5562 SDValue DAGCombiner::
5563 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5564 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5566 // If this is already the right type, we're done.
5567 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5569 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5570 unsigned DstBitSize = DstEltVT.getSizeInBits();
5572 // If this is a conversion of N elements of one type to N elements of another
5573 // type, convert each element. This handles FP<->INT cases.
5574 if (SrcBitSize == DstBitSize) {
5575 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5576 BV->getValueType(0).getVectorNumElements());
5578 // Due to the FP element handling below calling this routine recursively,
5579 // we can end up with a scalar-to-vector node here.
5580 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5581 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5582 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5583 DstEltVT, BV->getOperand(0)));
5585 SmallVector<SDValue, 8> Ops;
5586 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5587 SDValue Op = BV->getOperand(i);
5588 // If the vector element type is not legal, the BUILD_VECTOR operands
5589 // are promoted and implicitly truncated. Make that explicit here.
5590 if (Op.getValueType() != SrcEltVT)
5591 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
5592 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5594 AddToWorkList(Ops.back().getNode());
5596 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5597 &Ops[0], Ops.size());
5600 // Otherwise, we're growing or shrinking the elements. To avoid having to
5601 // handle annoying details of growing/shrinking FP values, we convert them to
5603 if (SrcEltVT.isFloatingPoint()) {
5604 // Convert the input float vector to a int vector where the elements are the
5606 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5607 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5608 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5612 // Now we know the input is an integer vector. If the output is a FP type,
5613 // convert to integer first, then to FP of the right size.
5614 if (DstEltVT.isFloatingPoint()) {
5615 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5616 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5617 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5619 // Next, convert to FP elements of the same size.
5620 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5623 // Okay, we know the src/dst types are both integers of differing types.
5624 // Handling growing first.
5625 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5626 if (SrcBitSize < DstBitSize) {
5627 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5629 SmallVector<SDValue, 8> Ops;
5630 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5631 i += NumInputsPerOutput) {
5632 bool isLE = TLI.isLittleEndian();
5633 APInt NewBits = APInt(DstBitSize, 0);
5634 bool EltIsUndef = true;
5635 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5636 // Shift the previously computed bits over.
5637 NewBits <<= SrcBitSize;
5638 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
5639 if (Op.getOpcode() == ISD::UNDEF) continue;
5642 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
5643 zextOrTrunc(SrcBitSize).zext(DstBitSize);
5647 Ops.push_back(DAG.getUNDEF(DstEltVT));
5649 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
5652 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
5653 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5654 &Ops[0], Ops.size());
5657 // Finally, this must be the case where we are shrinking elements: each input
5658 // turns into multiple outputs.
5659 bool isS2V = ISD::isScalarToVector(BV);
5660 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
5661 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5662 NumOutputsPerInput*BV->getNumOperands());
5663 SmallVector<SDValue, 8> Ops;
5665 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5666 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5667 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
5668 Ops.push_back(DAG.getUNDEF(DstEltVT));
5672 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
5673 getAPIntValue().zextOrTrunc(SrcBitSize);
5675 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
5676 APInt ThisVal = OpVal.trunc(DstBitSize);
5677 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
5678 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
5679 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
5680 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5682 OpVal = OpVal.lshr(DstBitSize);
5685 // For big endian targets, swap the order of the pieces of each element.
5686 if (TLI.isBigEndian())
5687 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
5690 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5691 &Ops[0], Ops.size());
5694 SDValue DAGCombiner::visitFADD(SDNode *N) {
5695 SDValue N0 = N->getOperand(0);
5696 SDValue N1 = N->getOperand(1);
5697 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5698 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5699 EVT VT = N->getValueType(0);
5702 if (VT.isVector()) {
5703 SDValue FoldedVOp = SimplifyVBinOp(N);
5704 if (FoldedVOp.getNode()) return FoldedVOp;
5707 // fold (fadd c1, c2) -> c1 + c2
5709 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5710 // canonicalize constant to RHS
5711 if (N0CFP && !N1CFP)
5712 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5713 // fold (fadd A, 0) -> A
5714 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5715 N1CFP->getValueAPF().isZero())
5717 // fold (fadd A, (fneg B)) -> (fsub A, B)
5718 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5719 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5720 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5721 GetNegatedExpression(N1, DAG, LegalOperations));
5722 // fold (fadd (fneg A), B) -> (fsub B, A)
5723 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5724 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5725 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
5726 GetNegatedExpression(N0, DAG, LegalOperations));
5728 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5729 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5730 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
5731 isa<ConstantFPSDNode>(N0.getOperand(1)))
5732 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5733 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5734 N0.getOperand(1), N1));
5736 // If allow, fold (fadd (fneg x), x) -> 0.0
5737 if (DAG.getTarget().Options.UnsafeFPMath &&
5738 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) {
5739 return DAG.getConstantFP(0.0, VT);
5742 // If allow, fold (fadd x, (fneg x)) -> 0.0
5743 if (DAG.getTarget().Options.UnsafeFPMath &&
5744 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) {
5745 return DAG.getConstantFP(0.0, VT);
5748 // In unsafe math mode, we can fold chains of FADD's of the same value
5749 // into multiplications. This transform is not safe in general because
5750 // we are reducing the number of rounding steps.
5751 if (DAG.getTarget().Options.UnsafeFPMath &&
5752 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) &&
5754 if (N0.getOpcode() == ISD::FMUL) {
5755 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
5756 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
5758 // (fadd (fmul c, x), x) -> (fmul c+1, x)
5759 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) {
5760 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5762 DAG.getConstantFP(1.0, VT));
5763 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5767 // (fadd (fmul x, c), x) -> (fmul c+1, x)
5768 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
5769 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5771 DAG.getConstantFP(1.0, VT));
5772 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5776 // (fadd (fadd x, x), x) -> (fmul 3.0, x)
5777 if (!CFP00 && !CFP01 && N0.getOperand(0) == N0.getOperand(1) &&
5778 N0.getOperand(0) == N1) {
5779 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5780 N1, DAG.getConstantFP(3.0, VT));
5783 // (fadd (fmul c, x), (fadd x, x)) -> (fmul c+2, x)
5784 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD &&
5785 N1.getOperand(0) == N1.getOperand(1) &&
5786 N0.getOperand(1) == N1.getOperand(0)) {
5787 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5789 DAG.getConstantFP(2.0, VT));
5790 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5791 N0.getOperand(1), NewCFP);
5794 // (fadd (fmul x, c), (fadd x, x)) -> (fmul c+2, x)
5795 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
5796 N1.getOperand(0) == N1.getOperand(1) &&
5797 N0.getOperand(0) == N1.getOperand(0)) {
5798 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5800 DAG.getConstantFP(2.0, VT));
5801 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5802 N0.getOperand(0), NewCFP);
5806 if (N1.getOpcode() == ISD::FMUL) {
5807 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
5808 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1));
5810 // (fadd x, (fmul c, x)) -> (fmul c+1, x)
5811 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) {
5812 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5814 DAG.getConstantFP(1.0, VT));
5815 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5819 // (fadd x, (fmul x, c)) -> (fmul c+1, x)
5820 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
5821 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5823 DAG.getConstantFP(1.0, VT));
5824 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5828 // (fadd x, (fadd x, x)) -> (fmul 3.0, x)
5829 if (!CFP10 && !CFP11 && N1.getOperand(0) == N1.getOperand(1) &&
5830 N1.getOperand(0) == N0) {
5831 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5832 N0, DAG.getConstantFP(3.0, VT));
5835 // (fadd (fadd x, x), (fmul c, x)) -> (fmul c+2, x)
5836 if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD &&
5837 N1.getOperand(0) == N1.getOperand(1) &&
5838 N0.getOperand(1) == N1.getOperand(0)) {
5839 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5841 DAG.getConstantFP(2.0, VT));
5842 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5843 N0.getOperand(1), NewCFP);
5846 // (fadd (fadd x, x), (fmul x, c)) -> (fmul c+2, x)
5847 if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD &&
5848 N1.getOperand(0) == N1.getOperand(1) &&
5849 N0.getOperand(0) == N1.getOperand(0)) {
5850 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5852 DAG.getConstantFP(2.0, VT));
5853 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5854 N0.getOperand(0), NewCFP);
5858 // (fadd (fadd x, x), (fadd x, x)) -> (fmul 4.0, x)
5859 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
5860 N0.getOperand(0) == N0.getOperand(1) &&
5861 N1.getOperand(0) == N1.getOperand(1) &&
5862 N0.getOperand(0) == N1.getOperand(0)) {
5863 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5865 DAG.getConstantFP(4.0, VT));
5869 // FADD -> FMA combines:
5870 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
5871 DAG.getTarget().Options.UnsafeFPMath) &&
5872 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) &&
5873 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) {
5875 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
5876 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) {
5877 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT,
5878 N0.getOperand(0), N0.getOperand(1), N1);
5881 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
5882 // Note: Commutes FADD operands.
5883 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) {
5884 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT,
5885 N1.getOperand(0), N1.getOperand(1), N0);
5892 SDValue DAGCombiner::visitFSUB(SDNode *N) {
5893 SDValue N0 = N->getOperand(0);
5894 SDValue N1 = N->getOperand(1);
5895 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5896 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5897 EVT VT = N->getValueType(0);
5898 DebugLoc dl = N->getDebugLoc();
5901 if (VT.isVector()) {
5902 SDValue FoldedVOp = SimplifyVBinOp(N);
5903 if (FoldedVOp.getNode()) return FoldedVOp;
5906 // fold (fsub c1, c2) -> c1-c2
5908 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5909 // fold (fsub A, 0) -> A
5910 if (DAG.getTarget().Options.UnsafeFPMath &&
5911 N1CFP && N1CFP->getValueAPF().isZero())
5913 // fold (fsub 0, B) -> -B
5914 if (DAG.getTarget().Options.UnsafeFPMath &&
5915 N0CFP && N0CFP->getValueAPF().isZero()) {
5916 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
5917 return GetNegatedExpression(N1, DAG, LegalOperations);
5918 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5919 return DAG.getNode(ISD::FNEG, dl, VT, N1);
5921 // fold (fsub A, (fneg B)) -> (fadd A, B)
5922 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
5923 return DAG.getNode(ISD::FADD, dl, VT, N0,
5924 GetNegatedExpression(N1, DAG, LegalOperations));
5926 // If 'unsafe math' is enabled, fold
5927 // (fsub x, x) -> 0.0 &
5928 // (fsub x, (fadd x, y)) -> (fneg y) &
5929 // (fsub x, (fadd y, x)) -> (fneg y)
5930 if (DAG.getTarget().Options.UnsafeFPMath) {
5932 return DAG.getConstantFP(0.0f, VT);
5934 if (N1.getOpcode() == ISD::FADD) {
5935 SDValue N10 = N1->getOperand(0);
5936 SDValue N11 = N1->getOperand(1);
5938 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI,
5939 &DAG.getTarget().Options))
5940 return GetNegatedExpression(N11, DAG, LegalOperations);
5941 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI,
5942 &DAG.getTarget().Options))
5943 return GetNegatedExpression(N10, DAG, LegalOperations);
5947 // FSUB -> FMA combines:
5948 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
5949 DAG.getTarget().Options.UnsafeFPMath) &&
5950 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) &&
5951 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) {
5953 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
5954 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) {
5955 return DAG.getNode(ISD::FMA, dl, VT,
5956 N0.getOperand(0), N0.getOperand(1),
5957 DAG.getNode(ISD::FNEG, dl, VT, N1));
5960 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
5961 // Note: Commutes FSUB operands.
5962 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) {
5963 return DAG.getNode(ISD::FMA, dl, VT,
5964 DAG.getNode(ISD::FNEG, dl, VT,
5966 N1.getOperand(1), N0);
5969 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
5970 if (N0.getOpcode() == ISD::FNEG &&
5971 N0.getOperand(0).getOpcode() == ISD::FMUL &&
5972 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) {
5973 SDValue N00 = N0.getOperand(0).getOperand(0);
5974 SDValue N01 = N0.getOperand(0).getOperand(1);
5975 return DAG.getNode(ISD::FMA, dl, VT,
5976 DAG.getNode(ISD::FNEG, dl, VT, N00), N01,
5977 DAG.getNode(ISD::FNEG, dl, VT, N1));
5984 SDValue DAGCombiner::visitFMUL(SDNode *N) {
5985 SDValue N0 = N->getOperand(0);
5986 SDValue N1 = N->getOperand(1);
5987 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5988 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5989 EVT VT = N->getValueType(0);
5990 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5993 if (VT.isVector()) {
5994 SDValue FoldedVOp = SimplifyVBinOp(N);
5995 if (FoldedVOp.getNode()) return FoldedVOp;
5998 // fold (fmul c1, c2) -> c1*c2
6000 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
6001 // canonicalize constant to RHS
6002 if (N0CFP && !N1CFP)
6003 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
6004 // fold (fmul A, 0) -> 0
6005 if (DAG.getTarget().Options.UnsafeFPMath &&
6006 N1CFP && N1CFP->getValueAPF().isZero())
6008 // fold (fmul A, 0) -> 0, vector edition.
6009 if (DAG.getTarget().Options.UnsafeFPMath &&
6010 ISD::isBuildVectorAllZeros(N1.getNode()))
6012 // fold (fmul A, 1.0) -> A
6013 if (N1CFP && N1CFP->isExactlyValue(1.0))
6015 // fold (fmul X, 2.0) -> (fadd X, X)
6016 if (N1CFP && N1CFP->isExactlyValue(+2.0))
6017 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
6018 // fold (fmul X, -1.0) -> (fneg X)
6019 if (N1CFP && N1CFP->isExactlyValue(-1.0))
6020 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6021 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
6023 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
6024 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6025 &DAG.getTarget().Options)) {
6026 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
6027 &DAG.getTarget().Options)) {
6028 // Both can be negated for free, check to see if at least one is cheaper
6030 if (LHSNeg == 2 || RHSNeg == 2)
6031 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
6032 GetNegatedExpression(N0, DAG, LegalOperations),
6033 GetNegatedExpression(N1, DAG, LegalOperations));
6037 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
6038 if (DAG.getTarget().Options.UnsafeFPMath &&
6039 N1CFP && N0.getOpcode() == ISD::FMUL &&
6040 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
6041 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
6042 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
6043 N0.getOperand(1), N1));
6048 SDValue DAGCombiner::visitFMA(SDNode *N) {
6049 SDValue N0 = N->getOperand(0);
6050 SDValue N1 = N->getOperand(1);
6051 SDValue N2 = N->getOperand(2);
6052 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6053 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6054 EVT VT = N->getValueType(0);
6055 DebugLoc dl = N->getDebugLoc();
6057 if (DAG.getTarget().Options.UnsafeFPMath) {
6058 if (N0CFP && N0CFP->isZero())
6060 if (N1CFP && N1CFP->isZero())
6063 if (N0CFP && N0CFP->isExactlyValue(1.0))
6064 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2);
6065 if (N1CFP && N1CFP->isExactlyValue(1.0))
6066 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2);
6068 // Canonicalize (fma c, x, y) -> (fma x, c, y)
6069 if (N0CFP && !N1CFP)
6070 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2);
6072 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
6073 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6074 N2.getOpcode() == ISD::FMUL &&
6075 N0 == N2.getOperand(0) &&
6076 N2.getOperand(1).getOpcode() == ISD::ConstantFP) {
6077 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6078 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1)));
6082 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
6083 if (DAG.getTarget().Options.UnsafeFPMath &&
6084 N0.getOpcode() == ISD::FMUL && N1CFP &&
6085 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
6086 return DAG.getNode(ISD::FMA, dl, VT,
6088 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
6092 // (fma x, 1, y) -> (fadd x, y)
6093 // (fma x, -1, y) -> (fadd (fneg x), y)
6095 if (N1CFP->isExactlyValue(1.0))
6096 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
6098 if (N1CFP->isExactlyValue(-1.0) &&
6099 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
6100 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
6101 AddToWorkList(RHSNeg.getNode());
6102 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
6106 // (fma x, c, x) -> (fmul x, (c+1))
6107 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) {
6108 return DAG.getNode(ISD::FMUL, dl, VT,
6110 DAG.getNode(ISD::FADD, dl, VT,
6111 N1, DAG.getConstantFP(1.0, VT)));
6114 // (fma x, c, (fneg x)) -> (fmul x, (c-1))
6115 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6116 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) {
6117 return DAG.getNode(ISD::FMUL, dl, VT,
6119 DAG.getNode(ISD::FADD, dl, VT,
6120 N1, DAG.getConstantFP(-1.0, VT)));
6127 SDValue DAGCombiner::visitFDIV(SDNode *N) {
6128 SDValue N0 = N->getOperand(0);
6129 SDValue N1 = N->getOperand(1);
6130 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6131 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6132 EVT VT = N->getValueType(0);
6133 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6136 if (VT.isVector()) {
6137 SDValue FoldedVOp = SimplifyVBinOp(N);
6138 if (FoldedVOp.getNode()) return FoldedVOp;
6141 // fold (fdiv c1, c2) -> c1/c2
6143 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
6145 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
6146 if (N1CFP && DAG.getTarget().Options.UnsafeFPMath) {
6147 // Compute the reciprocal 1.0 / c2.
6148 APFloat N1APF = N1CFP->getValueAPF();
6149 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
6150 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
6151 // Only do the transform if the reciprocal is a legal fp immediate that
6152 // isn't too nasty (eg NaN, denormal, ...).
6153 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
6154 (!LegalOperations ||
6155 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
6156 // backend)... we should handle this gracefully after Legalize.
6157 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
6158 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
6159 TLI.isFPImmLegal(Recip, VT)))
6160 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0,
6161 DAG.getConstantFP(Recip, VT));
6164 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
6165 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6166 &DAG.getTarget().Options)) {
6167 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
6168 &DAG.getTarget().Options)) {
6169 // Both can be negated for free, check to see if at least one is cheaper
6171 if (LHSNeg == 2 || RHSNeg == 2)
6172 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
6173 GetNegatedExpression(N0, DAG, LegalOperations),
6174 GetNegatedExpression(N1, DAG, LegalOperations));
6181 SDValue DAGCombiner::visitFREM(SDNode *N) {
6182 SDValue N0 = N->getOperand(0);
6183 SDValue N1 = N->getOperand(1);
6184 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6185 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6186 EVT VT = N->getValueType(0);
6188 // fold (frem c1, c2) -> fmod(c1,c2)
6190 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
6195 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
6196 SDValue N0 = N->getOperand(0);
6197 SDValue N1 = N->getOperand(1);
6198 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6199 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6200 EVT VT = N->getValueType(0);
6202 if (N0CFP && N1CFP) // Constant fold
6203 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
6206 const APFloat& V = N1CFP->getValueAPF();
6207 // copysign(x, c1) -> fabs(x) iff ispos(c1)
6208 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
6209 if (!V.isNegative()) {
6210 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
6211 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6213 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6214 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
6215 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
6219 // copysign(fabs(x), y) -> copysign(x, y)
6220 // copysign(fneg(x), y) -> copysign(x, y)
6221 // copysign(copysign(x,z), y) -> copysign(x, y)
6222 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
6223 N0.getOpcode() == ISD::FCOPYSIGN)
6224 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6225 N0.getOperand(0), N1);
6227 // copysign(x, abs(y)) -> abs(x)
6228 if (N1.getOpcode() == ISD::FABS)
6229 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6231 // copysign(x, copysign(y,z)) -> copysign(x, z)
6232 if (N1.getOpcode() == ISD::FCOPYSIGN)
6233 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6234 N0, N1.getOperand(1));
6236 // copysign(x, fp_extend(y)) -> copysign(x, y)
6237 // copysign(x, fp_round(y)) -> copysign(x, y)
6238 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
6239 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6240 N0, N1.getOperand(0));
6245 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
6246 SDValue N0 = N->getOperand(0);
6247 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6248 EVT VT = N->getValueType(0);
6249 EVT OpVT = N0.getValueType();
6251 // fold (sint_to_fp c1) -> c1fp
6253 // ...but only if the target supports immediate floating-point values
6254 (!LegalOperations ||
6255 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6256 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
6258 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
6259 // but UINT_TO_FP is legal on this target, try to convert.
6260 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
6261 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
6262 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
6263 if (DAG.SignBitIsZero(N0))
6264 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
6267 // The next optimizations are desireable only if SELECT_CC can be lowered.
6268 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
6269 // having to say they don't support SELECT_CC on every type the DAG knows
6270 // about, since there is no way to mark an opcode illegal at all value types
6271 // (See also visitSELECT)
6272 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
6273 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6274 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
6276 (!LegalOperations ||
6277 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6279 { N0.getOperand(0), N0.getOperand(1),
6280 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT),
6282 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6285 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
6286 // (select_cc x, y, 1.0, 0.0,, cc)
6287 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
6288 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
6289 (!LegalOperations ||
6290 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6292 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
6293 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT),
6294 N0.getOperand(0).getOperand(2) };
6295 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6302 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
6303 SDValue N0 = N->getOperand(0);
6304 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6305 EVT VT = N->getValueType(0);
6306 EVT OpVT = N0.getValueType();
6308 // fold (uint_to_fp c1) -> c1fp
6310 // ...but only if the target supports immediate floating-point values
6311 (!LegalOperations ||
6312 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6313 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
6315 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
6316 // but SINT_TO_FP is legal on this target, try to convert.
6317 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
6318 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
6319 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
6320 if (DAG.SignBitIsZero(N0))
6321 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
6324 // The next optimizations are desireable only if SELECT_CC can be lowered.
6325 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
6326 // having to say they don't support SELECT_CC on every type the DAG knows
6327 // about, since there is no way to mark an opcode illegal at all value types
6328 // (See also visitSELECT)
6329 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
6330 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6332 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
6333 (!LegalOperations ||
6334 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6336 { N0.getOperand(0), N0.getOperand(1),
6337 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT),
6339 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6346 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
6347 SDValue N0 = N->getOperand(0);
6348 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6349 EVT VT = N->getValueType(0);
6351 // fold (fp_to_sint c1fp) -> c1
6353 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
6358 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
6359 SDValue N0 = N->getOperand(0);
6360 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6361 EVT VT = N->getValueType(0);
6363 // fold (fp_to_uint c1fp) -> c1
6365 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
6370 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
6371 SDValue N0 = N->getOperand(0);
6372 SDValue N1 = N->getOperand(1);
6373 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6374 EVT VT = N->getValueType(0);
6376 // fold (fp_round c1fp) -> c1fp
6378 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
6380 // fold (fp_round (fp_extend x)) -> x
6381 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
6382 return N0.getOperand(0);
6384 // fold (fp_round (fp_round x)) -> (fp_round x)
6385 if (N0.getOpcode() == ISD::FP_ROUND) {
6386 // This is a value preserving truncation if both round's are.
6387 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
6388 N0.getNode()->getConstantOperandVal(1) == 1;
6389 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
6390 DAG.getIntPtrConstant(IsTrunc));
6393 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
6394 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
6395 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
6396 N0.getOperand(0), N1);
6397 AddToWorkList(Tmp.getNode());
6398 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6399 Tmp, N0.getOperand(1));
6405 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
6406 SDValue N0 = N->getOperand(0);
6407 EVT VT = N->getValueType(0);
6408 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
6409 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6411 // fold (fp_round_inreg c1fp) -> c1fp
6412 if (N0CFP && isTypeLegal(EVT)) {
6413 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
6414 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
6420 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
6421 SDValue N0 = N->getOperand(0);
6422 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6423 EVT VT = N->getValueType(0);
6425 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
6426 if (N->hasOneUse() &&
6427 N->use_begin()->getOpcode() == ISD::FP_ROUND)
6430 // fold (fp_extend c1fp) -> c1fp
6432 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
6434 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
6436 if (N0.getOpcode() == ISD::FP_ROUND
6437 && N0.getNode()->getConstantOperandVal(1) == 1) {
6438 SDValue In = N0.getOperand(0);
6439 if (In.getValueType() == VT) return In;
6440 if (VT.bitsLT(In.getValueType()))
6441 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
6442 In, N0.getOperand(1));
6443 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
6446 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
6447 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
6448 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6449 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
6450 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6451 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
6453 LN0->getBasePtr(), LN0->getPointerInfo(),
6455 LN0->isVolatile(), LN0->isNonTemporal(),
6456 LN0->getAlignment());
6457 CombineTo(N, ExtLoad);
6458 CombineTo(N0.getNode(),
6459 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
6460 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
6461 ExtLoad.getValue(1));
6462 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6468 SDValue DAGCombiner::visitFNEG(SDNode *N) {
6469 SDValue N0 = N->getOperand(0);
6470 EVT VT = N->getValueType(0);
6472 if (VT.isVector()) {
6473 SDValue FoldedVOp = SimplifyVUnaryOp(N);
6474 if (FoldedVOp.getNode()) return FoldedVOp;
6477 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
6478 &DAG.getTarget().Options))
6479 return GetNegatedExpression(N0, DAG, LegalOperations);
6481 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
6482 // constant pool values.
6483 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST &&
6485 N0.getNode()->hasOneUse() &&
6486 N0.getOperand(0).getValueType().isInteger()) {
6487 SDValue Int = N0.getOperand(0);
6488 EVT IntVT = Int.getValueType();
6489 if (IntVT.isInteger() && !IntVT.isVector()) {
6490 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
6491 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6492 AddToWorkList(Int.getNode());
6493 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6498 // (fneg (fmul c, x)) -> (fmul -c, x)
6499 if (N0.getOpcode() == ISD::FMUL) {
6500 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
6502 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
6504 DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
6512 SDValue DAGCombiner::visitFCEIL(SDNode *N) {
6513 SDValue N0 = N->getOperand(0);
6514 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6515 EVT VT = N->getValueType(0);
6517 // fold (fceil c1) -> fceil(c1)
6519 return DAG.getNode(ISD::FCEIL, N->getDebugLoc(), VT, N0);
6524 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
6525 SDValue N0 = N->getOperand(0);
6526 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6527 EVT VT = N->getValueType(0);
6529 // fold (ftrunc c1) -> ftrunc(c1)
6531 return DAG.getNode(ISD::FTRUNC, N->getDebugLoc(), VT, N0);
6536 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
6537 SDValue N0 = N->getOperand(0);
6538 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6539 EVT VT = N->getValueType(0);
6541 // fold (ffloor c1) -> ffloor(c1)
6543 return DAG.getNode(ISD::FFLOOR, N->getDebugLoc(), VT, N0);
6548 SDValue DAGCombiner::visitFABS(SDNode *N) {
6549 SDValue N0 = N->getOperand(0);
6550 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6551 EVT VT = N->getValueType(0);
6553 if (VT.isVector()) {
6554 SDValue FoldedVOp = SimplifyVUnaryOp(N);
6555 if (FoldedVOp.getNode()) return FoldedVOp;
6558 // fold (fabs c1) -> fabs(c1)
6560 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6561 // fold (fabs (fabs x)) -> (fabs x)
6562 if (N0.getOpcode() == ISD::FABS)
6563 return N->getOperand(0);
6564 // fold (fabs (fneg x)) -> (fabs x)
6565 // fold (fabs (fcopysign x, y)) -> (fabs x)
6566 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
6567 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
6569 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
6570 // constant pool values.
6571 if (!TLI.isFAbsFree(VT) &&
6572 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
6573 N0.getOperand(0).getValueType().isInteger() &&
6574 !N0.getOperand(0).getValueType().isVector()) {
6575 SDValue Int = N0.getOperand(0);
6576 EVT IntVT = Int.getValueType();
6577 if (IntVT.isInteger() && !IntVT.isVector()) {
6578 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
6579 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6580 AddToWorkList(Int.getNode());
6581 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6582 N->getValueType(0), Int);
6589 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
6590 SDValue Chain = N->getOperand(0);
6591 SDValue N1 = N->getOperand(1);
6592 SDValue N2 = N->getOperand(2);
6594 // If N is a constant we could fold this into a fallthrough or unconditional
6595 // branch. However that doesn't happen very often in normal code, because
6596 // Instcombine/SimplifyCFG should have handled the available opportunities.
6597 // If we did this folding here, it would be necessary to update the
6598 // MachineBasicBlock CFG, which is awkward.
6600 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
6602 if (N1.getOpcode() == ISD::SETCC &&
6603 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
6604 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6605 Chain, N1.getOperand(2),
6606 N1.getOperand(0), N1.getOperand(1), N2);
6609 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
6610 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
6611 (N1.getOperand(0).hasOneUse() &&
6612 N1.getOperand(0).getOpcode() == ISD::SRL))) {
6614 if (N1.getOpcode() == ISD::TRUNCATE) {
6615 // Look pass the truncate.
6616 Trunc = N1.getNode();
6617 N1 = N1.getOperand(0);
6620 // Match this pattern so that we can generate simpler code:
6623 // %b = and i32 %a, 2
6624 // %c = srl i32 %b, 1
6625 // brcond i32 %c ...
6630 // %b = and i32 %a, 2
6631 // %c = setcc eq %b, 0
6634 // This applies only when the AND constant value has one bit set and the
6635 // SRL constant is equal to the log2 of the AND constant. The back-end is
6636 // smart enough to convert the result into a TEST/JMP sequence.
6637 SDValue Op0 = N1.getOperand(0);
6638 SDValue Op1 = N1.getOperand(1);
6640 if (Op0.getOpcode() == ISD::AND &&
6641 Op1.getOpcode() == ISD::Constant) {
6642 SDValue AndOp1 = Op0.getOperand(1);
6644 if (AndOp1.getOpcode() == ISD::Constant) {
6645 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
6647 if (AndConst.isPowerOf2() &&
6648 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
6650 DAG.getSetCC(N->getDebugLoc(),
6651 TLI.getSetCCResultType(Op0.getValueType()),
6652 Op0, DAG.getConstant(0, Op0.getValueType()),
6655 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6656 MVT::Other, Chain, SetCC, N2);
6657 // Don't add the new BRCond into the worklist or else SimplifySelectCC
6658 // will convert it back to (X & C1) >> C2.
6659 CombineTo(N, NewBRCond, false);
6660 // Truncate is dead.
6662 removeFromWorkList(Trunc);
6663 DAG.DeleteNode(Trunc);
6665 // Replace the uses of SRL with SETCC
6666 WorkListRemover DeadNodes(*this);
6667 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6668 removeFromWorkList(N1.getNode());
6669 DAG.DeleteNode(N1.getNode());
6670 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6676 // Restore N1 if the above transformation doesn't match.
6677 N1 = N->getOperand(1);
6680 // Transform br(xor(x, y)) -> br(x != y)
6681 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
6682 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
6683 SDNode *TheXor = N1.getNode();
6684 SDValue Op0 = TheXor->getOperand(0);
6685 SDValue Op1 = TheXor->getOperand(1);
6686 if (Op0.getOpcode() == Op1.getOpcode()) {
6687 // Avoid missing important xor optimizations.
6688 SDValue Tmp = visitXOR(TheXor);
6689 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
6690 DEBUG(dbgs() << "\nReplacing.8 ";
6692 dbgs() << "\nWith: ";
6693 Tmp.getNode()->dump(&DAG);
6695 WorkListRemover DeadNodes(*this);
6696 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
6697 removeFromWorkList(TheXor);
6698 DAG.DeleteNode(TheXor);
6699 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6700 MVT::Other, Chain, Tmp, N2);
6704 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
6706 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
6707 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
6708 Op0.getOpcode() == ISD::XOR) {
6709 TheXor = Op0.getNode();
6713 EVT SetCCVT = N1.getValueType();
6715 SetCCVT = TLI.getSetCCResultType(SetCCVT);
6716 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
6719 Equal ? ISD::SETEQ : ISD::SETNE);
6720 // Replace the uses of XOR with SETCC
6721 WorkListRemover DeadNodes(*this);
6722 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6723 removeFromWorkList(N1.getNode());
6724 DAG.DeleteNode(N1.getNode());
6725 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6726 MVT::Other, Chain, SetCC, N2);
6733 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
6735 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
6736 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
6737 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
6739 // If N is a constant we could fold this into a fallthrough or unconditional
6740 // branch. However that doesn't happen very often in normal code, because
6741 // Instcombine/SimplifyCFG should have handled the available opportunities.
6742 // If we did this folding here, it would be necessary to update the
6743 // MachineBasicBlock CFG, which is awkward.
6745 // Use SimplifySetCC to simplify SETCC's.
6746 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
6747 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
6749 if (Simp.getNode()) AddToWorkList(Simp.getNode());
6751 // fold to a simpler setcc
6752 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
6753 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6754 N->getOperand(0), Simp.getOperand(2),
6755 Simp.getOperand(0), Simp.getOperand(1),
6761 /// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
6762 /// uses N as its base pointer and that N may be folded in the load / store
6763 /// addressing mode.
6764 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
6766 const TargetLowering &TLI) {
6768 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
6769 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
6771 VT = Use->getValueType(0);
6772 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
6773 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
6775 VT = ST->getValue().getValueType();
6780 if (N->getOpcode() == ISD::ADD) {
6781 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6784 AM.BaseOffs = Offset->getSExtValue();
6788 } else if (N->getOpcode() == ISD::SUB) {
6789 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6792 AM.BaseOffs = -Offset->getSExtValue();
6799 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
6802 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
6803 /// pre-indexed load / store when the base pointer is an add or subtract
6804 /// and it has other uses besides the load / store. After the
6805 /// transformation, the new indexed load / store has effectively folded
6806 /// the add / subtract in and all of its other uses are redirected to the
6807 /// new load / store.
6808 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
6809 if (Level < AfterLegalizeDAG)
6815 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6816 if (LD->isIndexed())
6818 VT = LD->getMemoryVT();
6819 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
6820 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
6822 Ptr = LD->getBasePtr();
6823 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6824 if (ST->isIndexed())
6826 VT = ST->getMemoryVT();
6827 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
6828 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
6830 Ptr = ST->getBasePtr();
6836 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
6837 // out. There is no reason to make this a preinc/predec.
6838 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
6839 Ptr.getNode()->hasOneUse())
6842 // Ask the target to do addressing mode selection.
6845 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6846 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
6848 // Don't create a indexed load / store with zero offset.
6849 if (isa<ConstantSDNode>(Offset) &&
6850 cast<ConstantSDNode>(Offset)->isNullValue())
6853 // Try turning it into a pre-indexed load / store except when:
6854 // 1) The new base ptr is a frame index.
6855 // 2) If N is a store and the new base ptr is either the same as or is a
6856 // predecessor of the value being stored.
6857 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
6858 // that would create a cycle.
6859 // 4) All uses are load / store ops that use it as old base ptr.
6861 // Check #1. Preinc'ing a frame index would require copying the stack pointer
6862 // (plus the implicit offset) to a register to preinc anyway.
6863 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6868 SDValue Val = cast<StoreSDNode>(N)->getValue();
6869 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
6873 // Now check for #3 and #4.
6874 bool RealUse = false;
6876 // Caches for hasPredecessorHelper
6877 SmallPtrSet<const SDNode *, 32> Visited;
6878 SmallVector<const SDNode *, 16> Worklist;
6880 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6881 E = Ptr.getNode()->use_end(); I != E; ++I) {
6885 if (N->hasPredecessorHelper(Use, Visited, Worklist))
6888 // If Ptr may be folded in addressing mode of other use, then it's
6889 // not profitable to do this transformation.
6890 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
6899 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6900 BasePtr, Offset, AM);
6902 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6903 BasePtr, Offset, AM);
6906 DEBUG(dbgs() << "\nReplacing.4 ";
6908 dbgs() << "\nWith: ";
6909 Result.getNode()->dump(&DAG);
6911 WorkListRemover DeadNodes(*this);
6913 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
6914 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
6916 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
6919 // Finally, since the node is now dead, remove it from the graph.
6922 // Replace the uses of Ptr with uses of the updated base value.
6923 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
6924 removeFromWorkList(Ptr.getNode());
6925 DAG.DeleteNode(Ptr.getNode());
6930 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
6931 /// add / sub of the base pointer node into a post-indexed load / store.
6932 /// The transformation folded the add / subtract into the new indexed
6933 /// load / store effectively and all of its uses are redirected to the
6934 /// new load / store.
6935 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
6936 if (Level < AfterLegalizeDAG)
6942 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6943 if (LD->isIndexed())
6945 VT = LD->getMemoryVT();
6946 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
6947 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
6949 Ptr = LD->getBasePtr();
6950 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6951 if (ST->isIndexed())
6953 VT = ST->getMemoryVT();
6954 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
6955 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
6957 Ptr = ST->getBasePtr();
6963 if (Ptr.getNode()->hasOneUse())
6966 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6967 E = Ptr.getNode()->use_end(); I != E; ++I) {
6970 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
6975 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6976 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
6977 // Don't create a indexed load / store with zero offset.
6978 if (isa<ConstantSDNode>(Offset) &&
6979 cast<ConstantSDNode>(Offset)->isNullValue())
6982 // Try turning it into a post-indexed load / store except when
6983 // 1) All uses are load / store ops that use it as base ptr (and
6984 // it may be folded as addressing mmode).
6985 // 2) Op must be independent of N, i.e. Op is neither a predecessor
6986 // nor a successor of N. Otherwise, if Op is folded that would
6989 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6993 bool TryNext = false;
6994 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
6995 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
6997 if (Use == Ptr.getNode())
7000 // If all the uses are load / store addresses, then don't do the
7002 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
7003 bool RealUse = false;
7004 for (SDNode::use_iterator III = Use->use_begin(),
7005 EEE = Use->use_end(); III != EEE; ++III) {
7006 SDNode *UseUse = *III;
7007 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
7022 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
7023 SDValue Result = isLoad
7024 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
7025 BasePtr, Offset, AM)
7026 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
7027 BasePtr, Offset, AM);
7030 DEBUG(dbgs() << "\nReplacing.5 ";
7032 dbgs() << "\nWith: ";
7033 Result.getNode()->dump(&DAG);
7035 WorkListRemover DeadNodes(*this);
7037 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
7038 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
7040 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
7043 // Finally, since the node is now dead, remove it from the graph.
7046 // Replace the uses of Use with uses of the updated base value.
7047 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
7048 Result.getValue(isLoad ? 1 : 0));
7049 removeFromWorkList(Op);
7059 SDValue DAGCombiner::visitLOAD(SDNode *N) {
7060 LoadSDNode *LD = cast<LoadSDNode>(N);
7061 SDValue Chain = LD->getChain();
7062 SDValue Ptr = LD->getBasePtr();
7064 // If load is not volatile and there are no uses of the loaded value (and
7065 // the updated indexed value in case of indexed loads), change uses of the
7066 // chain value into uses of the chain input (i.e. delete the dead load).
7067 if (!LD->isVolatile()) {
7068 if (N->getValueType(1) == MVT::Other) {
7070 if (!N->hasAnyUseOfValue(0)) {
7071 // It's not safe to use the two value CombineTo variant here. e.g.
7072 // v1, chain2 = load chain1, loc
7073 // v2, chain3 = load chain2, loc
7075 // Now we replace use of chain2 with chain1. This makes the second load
7076 // isomorphic to the one we are deleting, and thus makes this load live.
7077 DEBUG(dbgs() << "\nReplacing.6 ";
7079 dbgs() << "\nWith chain: ";
7080 Chain.getNode()->dump(&DAG);
7082 WorkListRemover DeadNodes(*this);
7083 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
7085 if (N->use_empty()) {
7086 removeFromWorkList(N);
7090 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7094 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
7095 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) {
7096 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
7097 DEBUG(dbgs() << "\nReplacing.7 ";
7099 dbgs() << "\nWith: ";
7100 Undef.getNode()->dump(&DAG);
7101 dbgs() << " and 2 other values\n");
7102 WorkListRemover DeadNodes(*this);
7103 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
7104 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
7105 DAG.getUNDEF(N->getValueType(1)));
7106 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
7107 removeFromWorkList(N);
7109 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7114 // If this load is directly stored, replace the load value with the stored
7116 // TODO: Handle store large -> read small portion.
7117 // TODO: Handle TRUNCSTORE/LOADEXT
7118 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
7119 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
7120 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
7121 if (PrevST->getBasePtr() == Ptr &&
7122 PrevST->getValue().getValueType() == N->getValueType(0))
7123 return CombineTo(N, Chain.getOperand(1), Chain);
7127 // Try to infer better alignment information than the load already has.
7128 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
7129 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
7130 if (Align > LD->getAlignment())
7131 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
7132 LD->getValueType(0),
7133 Chain, Ptr, LD->getPointerInfo(),
7135 LD->isVolatile(), LD->isNonTemporal(), Align);
7140 // Walk up chain skipping non-aliasing memory nodes.
7141 SDValue BetterChain = FindBetterChain(N, Chain);
7143 // If there is a better chain.
7144 if (Chain != BetterChain) {
7147 // Replace the chain to void dependency.
7148 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
7149 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
7150 BetterChain, Ptr, LD->getPointerInfo(),
7151 LD->isVolatile(), LD->isNonTemporal(),
7152 LD->isInvariant(), LD->getAlignment());
7154 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
7155 LD->getValueType(0),
7156 BetterChain, Ptr, LD->getPointerInfo(),
7159 LD->isNonTemporal(),
7160 LD->getAlignment());
7163 // Create token factor to keep old chain connected.
7164 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
7165 MVT::Other, Chain, ReplLoad.getValue(1));
7167 // Make sure the new and old chains are cleaned up.
7168 AddToWorkList(Token.getNode());
7170 // Replace uses with load result and token factor. Don't add users
7172 return CombineTo(N, ReplLoad.getValue(0), Token, false);
7176 // Try transforming N to an indexed load.
7177 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
7178 return SDValue(N, 0);
7183 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
7184 /// load is having specific bytes cleared out. If so, return the byte size
7185 /// being masked out and the shift amount.
7186 static std::pair<unsigned, unsigned>
7187 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
7188 std::pair<unsigned, unsigned> Result(0, 0);
7190 // Check for the structure we're looking for.
7191 if (V->getOpcode() != ISD::AND ||
7192 !isa<ConstantSDNode>(V->getOperand(1)) ||
7193 !ISD::isNormalLoad(V->getOperand(0).getNode()))
7196 // Check the chain and pointer.
7197 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
7198 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
7200 // The store should be chained directly to the load or be an operand of a
7202 if (LD == Chain.getNode())
7204 else if (Chain->getOpcode() != ISD::TokenFactor)
7205 return Result; // Fail.
7208 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
7209 if (Chain->getOperand(i).getNode() == LD) {
7213 if (!isOk) return Result;
7216 // This only handles simple types.
7217 if (V.getValueType() != MVT::i16 &&
7218 V.getValueType() != MVT::i32 &&
7219 V.getValueType() != MVT::i64)
7222 // Check the constant mask. Invert it so that the bits being masked out are
7223 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
7224 // follow the sign bit for uniformity.
7225 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
7226 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
7227 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
7228 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
7229 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
7230 if (NotMaskLZ == 64) return Result; // All zero mask.
7232 // See if we have a continuous run of bits. If so, we have 0*1+0*
7233 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
7236 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
7237 if (V.getValueType() != MVT::i64 && NotMaskLZ)
7238 NotMaskLZ -= 64-V.getValueSizeInBits();
7240 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
7241 switch (MaskedBytes) {
7245 default: return Result; // All one mask, or 5-byte mask.
7248 // Verify that the first bit starts at a multiple of mask so that the access
7249 // is aligned the same as the access width.
7250 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
7252 Result.first = MaskedBytes;
7253 Result.second = NotMaskTZ/8;
7258 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
7259 /// provides a value as specified by MaskInfo. If so, replace the specified
7260 /// store with a narrower store of truncated IVal.
7262 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
7263 SDValue IVal, StoreSDNode *St,
7265 unsigned NumBytes = MaskInfo.first;
7266 unsigned ByteShift = MaskInfo.second;
7267 SelectionDAG &DAG = DC->getDAG();
7269 // Check to see if IVal is all zeros in the part being masked in by the 'or'
7270 // that uses this. If not, this is not a replacement.
7271 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
7272 ByteShift*8, (ByteShift+NumBytes)*8);
7273 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
7275 // Check that it is legal on the target to do this. It is legal if the new
7276 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
7278 MVT VT = MVT::getIntegerVT(NumBytes*8);
7279 if (!DC->isTypeLegal(VT))
7282 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
7283 // shifted by ByteShift and truncated down to NumBytes.
7285 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
7286 DAG.getConstant(ByteShift*8,
7287 DC->getShiftAmountTy(IVal.getValueType())));
7289 // Figure out the offset for the store and the alignment of the access.
7291 unsigned NewAlign = St->getAlignment();
7293 if (DAG.getTargetLoweringInfo().isLittleEndian())
7294 StOffset = ByteShift;
7296 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
7298 SDValue Ptr = St->getBasePtr();
7300 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
7301 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
7302 NewAlign = MinAlign(NewAlign, StOffset);
7305 // Truncate down to the new size.
7306 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
7309 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
7310 St->getPointerInfo().getWithOffset(StOffset),
7311 false, false, NewAlign).getNode();
7315 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
7316 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
7317 /// of the loaded bits, try narrowing the load and store if it would end up
7318 /// being a win for performance or code size.
7319 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
7320 StoreSDNode *ST = cast<StoreSDNode>(N);
7321 if (ST->isVolatile())
7324 SDValue Chain = ST->getChain();
7325 SDValue Value = ST->getValue();
7326 SDValue Ptr = ST->getBasePtr();
7327 EVT VT = Value.getValueType();
7329 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
7332 unsigned Opc = Value.getOpcode();
7334 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
7335 // is a byte mask indicating a consecutive number of bytes, check to see if
7336 // Y is known to provide just those bytes. If so, we try to replace the
7337 // load + replace + store sequence with a single (narrower) store, which makes
7339 if (Opc == ISD::OR) {
7340 std::pair<unsigned, unsigned> MaskedLoad;
7341 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
7342 if (MaskedLoad.first)
7343 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
7344 Value.getOperand(1), ST,this))
7345 return SDValue(NewST, 0);
7347 // Or is commutative, so try swapping X and Y.
7348 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
7349 if (MaskedLoad.first)
7350 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
7351 Value.getOperand(0), ST,this))
7352 return SDValue(NewST, 0);
7355 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
7356 Value.getOperand(1).getOpcode() != ISD::Constant)
7359 SDValue N0 = Value.getOperand(0);
7360 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7361 Chain == SDValue(N0.getNode(), 1)) {
7362 LoadSDNode *LD = cast<LoadSDNode>(N0);
7363 if (LD->getBasePtr() != Ptr ||
7364 LD->getPointerInfo().getAddrSpace() !=
7365 ST->getPointerInfo().getAddrSpace())
7368 // Find the type to narrow it the load / op / store to.
7369 SDValue N1 = Value.getOperand(1);
7370 unsigned BitWidth = N1.getValueSizeInBits();
7371 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
7372 if (Opc == ISD::AND)
7373 Imm ^= APInt::getAllOnesValue(BitWidth);
7374 if (Imm == 0 || Imm.isAllOnesValue())
7376 unsigned ShAmt = Imm.countTrailingZeros();
7377 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
7378 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
7379 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
7380 while (NewBW < BitWidth &&
7381 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
7382 TLI.isNarrowingProfitable(VT, NewVT))) {
7383 NewBW = NextPowerOf2(NewBW);
7384 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
7386 if (NewBW >= BitWidth)
7389 // If the lsb changed does not start at the type bitwidth boundary,
7390 // start at the previous one.
7392 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
7393 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
7394 if ((Imm & Mask) == Imm) {
7395 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
7396 if (Opc == ISD::AND)
7397 NewImm ^= APInt::getAllOnesValue(NewBW);
7398 uint64_t PtrOff = ShAmt / 8;
7399 // For big endian targets, we need to adjust the offset to the pointer to
7400 // load the correct bytes.
7401 if (TLI.isBigEndian())
7402 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
7404 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
7405 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
7406 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy))
7409 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
7410 Ptr.getValueType(), Ptr,
7411 DAG.getConstant(PtrOff, Ptr.getValueType()));
7412 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
7413 LD->getChain(), NewPtr,
7414 LD->getPointerInfo().getWithOffset(PtrOff),
7415 LD->isVolatile(), LD->isNonTemporal(),
7416 LD->isInvariant(), NewAlign);
7417 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
7418 DAG.getConstant(NewImm, NewVT));
7419 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
7421 ST->getPointerInfo().getWithOffset(PtrOff),
7422 false, false, NewAlign);
7424 AddToWorkList(NewPtr.getNode());
7425 AddToWorkList(NewLD.getNode());
7426 AddToWorkList(NewVal.getNode());
7427 WorkListRemover DeadNodes(*this);
7428 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
7437 /// TransformFPLoadStorePair - For a given floating point load / store pair,
7438 /// if the load value isn't used by any other operations, then consider
7439 /// transforming the pair to integer load / store operations if the target
7440 /// deems the transformation profitable.
7441 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
7442 StoreSDNode *ST = cast<StoreSDNode>(N);
7443 SDValue Chain = ST->getChain();
7444 SDValue Value = ST->getValue();
7445 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
7446 Value.hasOneUse() &&
7447 Chain == SDValue(Value.getNode(), 1)) {
7448 LoadSDNode *LD = cast<LoadSDNode>(Value);
7449 EVT VT = LD->getMemoryVT();
7450 if (!VT.isFloatingPoint() ||
7451 VT != ST->getMemoryVT() ||
7452 LD->isNonTemporal() ||
7453 ST->isNonTemporal() ||
7454 LD->getPointerInfo().getAddrSpace() != 0 ||
7455 ST->getPointerInfo().getAddrSpace() != 0)
7458 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
7459 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
7460 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
7461 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
7462 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
7465 unsigned LDAlign = LD->getAlignment();
7466 unsigned STAlign = ST->getAlignment();
7467 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
7468 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy);
7469 if (LDAlign < ABIAlign || STAlign < ABIAlign)
7472 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
7473 LD->getChain(), LD->getBasePtr(),
7474 LD->getPointerInfo(),
7475 false, false, false, LDAlign);
7477 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
7478 NewLD, ST->getBasePtr(),
7479 ST->getPointerInfo(),
7480 false, false, STAlign);
7482 AddToWorkList(NewLD.getNode());
7483 AddToWorkList(NewST.getNode());
7484 WorkListRemover DeadNodes(*this);
7485 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
7493 /// Returns the base pointer and an integer offset from that object.
7494 static std::pair<SDValue, int64_t> GetPointerBaseAndOffset(SDValue Ptr) {
7495 if (Ptr->getOpcode() == ISD::ADD && isa<ConstantSDNode>(Ptr->getOperand(1))) {
7496 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
7497 SDValue Base = Ptr->getOperand(0);
7498 return std::make_pair(Base, Offset);
7501 return std::make_pair(Ptr, 0);
7504 /// Holds a pointer to an LSBaseSDNode as well as information on where it
7505 /// is located in a sequence of memory operations connected by a chain.
7507 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq):
7508 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { }
7509 // Ptr to the mem node.
7510 LSBaseSDNode *MemNode;
7511 // Offset from the base ptr.
7512 int64_t OffsetFromBase;
7513 // What is the sequence number of this mem node.
7514 // Lowest mem operand in the DAG starts at zero.
7515 unsigned SequenceNum;
7518 /// Sorts store nodes in a link according to their offset from a shared
7520 struct ConsecutiveMemoryChainSorter {
7521 bool operator()(MemOpLink LHS, MemOpLink RHS) {
7522 return LHS.OffsetFromBase < RHS.OffsetFromBase;
7526 bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
7527 EVT MemVT = St->getMemoryVT();
7528 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8;
7530 // Don't merge vectors into wider inputs.
7531 if (MemVT.isVector() || !MemVT.isSimple())
7534 // Perform an early exit check. Do not bother looking at stored values that
7535 // are not constants or loads.
7536 SDValue StoredVal = St->getValue();
7537 bool IsLoadSrc = isa<LoadSDNode>(StoredVal);
7538 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) &&
7542 // Only look at ends of store sequences.
7543 SDValue Chain = SDValue(St, 1);
7544 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
7547 // This holds the base pointer and the offset in bytes from the base pointer.
7548 std::pair<SDValue, int64_t> BasePtr =
7549 GetPointerBaseAndOffset(St->getBasePtr());
7551 // We must have a base and an offset.
7552 if (!BasePtr.first.getNode())
7555 // Do not handle stores to undef base pointers.
7556 if (BasePtr.first.getOpcode() == ISD::UNDEF)
7559 // Save the LoadSDNodes that we find in the chain.
7560 // We need to make sure that these nodes do not interfere with
7561 // any of the store nodes.
7562 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
7564 // Save the StoreSDNodes that we find in the chain.
7565 SmallVector<MemOpLink, 8> StoreNodes;
7567 // Walk up the chain and look for nodes with offsets from the same
7568 // base pointer. Stop when reaching an instruction with a different kind
7569 // or instruction which has a different base pointer.
7571 StoreSDNode *Index = St;
7573 // If the chain has more than one use, then we can't reorder the mem ops.
7574 if (Index != St && !SDValue(Index, 1)->hasOneUse())
7577 // Find the base pointer and offset for this memory node.
7578 std::pair<SDValue, int64_t> Ptr =
7579 GetPointerBaseAndOffset(Index->getBasePtr());
7581 // Check that the base pointer is the same as the original one.
7582 if (Ptr.first.getNode() != BasePtr.first.getNode())
7585 // Check that the alignment is the same.
7586 if (Index->getAlignment() != St->getAlignment())
7589 // The memory operands must not be volatile.
7590 if (Index->isVolatile() || Index->isIndexed())
7594 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index))
7595 if (St->isTruncatingStore())
7598 // The stored memory type must be the same.
7599 if (Index->getMemoryVT() != MemVT)
7602 // We do not allow unaligned stores because we want to prevent overriding
7604 if (Index->getAlignment()*8 != MemVT.getSizeInBits())
7607 // We found a potential memory operand to merge.
7608 StoreNodes.push_back(MemOpLink(Index, Ptr.second, Seq++));
7610 // Find the next memory operand in the chain. If the next operand in the
7611 // chain is a store then move up and continue the scan with the next
7612 // memory operand. If the next operand is a load save it and use alias
7613 // information to check if it interferes with anything.
7614 SDNode *NextInChain = Index->getChain().getNode();
7616 if (isa<StoreSDNode>(NextInChain)) {
7617 // We found a store node. Use it for the next iteration.
7618 Index = cast<StoreSDNode>(NextInChain);
7620 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) {
7621 // Save the load node for later. Continue the scan.
7622 AliasLoadNodes.push_back(Ldn);
7623 NextInChain = Ldn->getChain().getNode();
7632 // Check if there is anything to merge.
7633 if (StoreNodes.size() < 2)
7636 // Sort the memory operands according to their distance from the base pointer.
7637 std::sort(StoreNodes.begin(), StoreNodes.end(),
7638 ConsecutiveMemoryChainSorter());
7640 // Scan the memory operations on the chain and find the first non-consecutive
7641 // store memory address.
7642 unsigned LastConsecutiveStore = 0;
7643 int64_t StartAddress = StoreNodes[0].OffsetFromBase;
7644 for (unsigned i = 1, e = StoreNodes.size(); i < e; ++i) {
7645 int64_t CurrAddress = StoreNodes[i].OffsetFromBase;
7646 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
7650 // Check if this store interferes with any of the loads that we found.
7651 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld)
7652 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) {
7657 // We found a load that alias with this store. Stop the sequence.
7661 // Mark this node as useful.
7662 LastConsecutiveStore = i;
7665 // The node with the lowest store address.
7666 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
7668 // Store the constants into memory as one consecutive store.
7670 unsigned LastLegalType = 0;
7671 unsigned LastLegalVectorType = 0;
7672 bool NonZero = false;
7673 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
7674 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7675 SDValue StoredVal = St->getValue();
7677 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) {
7678 NonZero |= !C->isNullValue();
7679 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
7680 NonZero |= !C->getConstantFPValue()->isNullValue();
7686 // Find a legal type for the constant store.
7687 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
7688 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7689 if (TLI.isTypeLegal(StoreTy))
7690 LastLegalType = i+1;
7692 // Find a legal type for the vector store.
7693 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
7694 if (TLI.isTypeLegal(Ty))
7695 LastLegalVectorType = i + 1;
7698 // We only use vectors if the constant is known to be zero.
7700 LastLegalVectorType = 0;
7702 // Check if we found a legal integer type to store.
7703 if (LastLegalType == 0 && LastLegalVectorType == 0)
7706 bool UseVector = LastLegalVectorType > LastLegalType;
7707 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType;
7709 // Make sure we have something to merge.
7713 unsigned EarliestNodeUsed = 0;
7714 for (unsigned i=0; i < NumElem; ++i) {
7715 // Find a chain for the new wide-store operand. Notice that some
7716 // of the store nodes that we found may not be selected for inclusion
7717 // in the wide store. The chain we use needs to be the chain of the
7718 // earliest store node which is *used* and replaced by the wide store.
7719 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
7720 EarliestNodeUsed = i;
7723 // The earliest Node in the DAG.
7724 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
7725 DebugLoc DL = StoreNodes[0].MemNode->getDebugLoc();
7729 // Find a legal type for the vector store.
7730 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
7731 assert(TLI.isTypeLegal(Ty) && "Illegal vector store");
7732 StoredVal = DAG.getConstant(0, Ty);
7734 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
7735 APInt StoreInt(StoreBW, 0);
7737 // Construct a single integer constant which is made of the smaller
7739 bool IsLE = TLI.isLittleEndian();
7740 for (unsigned i = 0; i < NumElem ; ++i) {
7741 unsigned Idx = IsLE ?(NumElem - 1 - i) : i;
7742 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode);
7743 SDValue Val = St->getValue();
7744 StoreInt<<=ElementSizeBytes*8;
7745 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) {
7746 StoreInt|=C->getAPIntValue().zext(StoreBW);
7747 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
7748 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW);
7750 assert(false && "Invalid constant element type");
7754 // Create the new Load and Store operations.
7755 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7756 StoredVal = DAG.getConstant(StoreInt, StoreTy);
7759 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal,
7760 FirstInChain->getBasePtr(),
7761 FirstInChain->getPointerInfo(),
7763 FirstInChain->getAlignment());
7765 // Replace the first store with the new store
7766 CombineTo(EarliestOp, NewStore);
7767 // Erase all other stores.
7768 for (unsigned i = 0; i < NumElem ; ++i) {
7769 if (StoreNodes[i].MemNode == EarliestOp)
7771 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7772 // ReplaceAllUsesWith will replace all uses that existed when it was
7773 // called, but graph optimizations may cause new ones to appear. For
7774 // example, the case in pr14333 looks like
7776 // St's chain -> St -> another store -> X
7778 // And the only difference from St to the other store is the chain.
7779 // When we change it's chain to be St's chain they become identical,
7780 // get CSEed and the net result is that X is now a use of St.
7781 // Since we know that St is redundant, just iterate.
7782 while (!St->use_empty())
7783 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain());
7784 removeFromWorkList(St);
7791 // Below we handle the case of multiple consecutive stores that
7792 // come from multiple consecutive loads. We merge them into a single
7793 // wide load and a single wide store.
7795 // Look for load nodes which are used by the stored values.
7796 SmallVector<MemOpLink, 8> LoadNodes;
7798 // Find acceptable loads. Loads need to have the same chain (token factor),
7799 // must not be zext, volatile, indexed, and they must be consecutive.
7801 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
7802 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7803 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
7806 // Loads must only have one use.
7807 if (!Ld->hasNUsesOfValue(1, 0))
7810 // Check that the alignment is the same as the stores.
7811 if (Ld->getAlignment() != St->getAlignment())
7814 // The memory operands must not be volatile.
7815 if (Ld->isVolatile() || Ld->isIndexed())
7818 // We do not accept ext loads.
7819 if (Ld->getExtensionType() != ISD::NON_EXTLOAD)
7822 // The stored memory type must be the same.
7823 if (Ld->getMemoryVT() != MemVT)
7826 std::pair<SDValue, int64_t> LdPtr =
7827 GetPointerBaseAndOffset(Ld->getBasePtr());
7829 // If this is not the first ptr that we check.
7830 if (LdBasePtr.getNode()) {
7831 // The base ptr must be the same.
7832 if (LdPtr.first != LdBasePtr)
7835 // Check that all other base pointers are the same as this one.
7836 LdBasePtr = LdPtr.first;
7839 // We found a potential memory operand to merge.
7840 LoadNodes.push_back(MemOpLink(Ld, LdPtr.second, 0));
7843 if (LoadNodes.size() < 2)
7846 // Scan the memory operations on the chain and find the first non-consecutive
7847 // load memory address. These variables hold the index in the store node
7849 unsigned LastConsecutiveLoad = 0;
7850 // This variable refers to the size and not index in the array.
7851 unsigned LastLegalVectorType = 0;
7852 unsigned LastLegalIntegerType = 0;
7853 StartAddress = LoadNodes[0].OffsetFromBase;
7854 SDValue FirstChain = LoadNodes[0].MemNode->getChain();
7855 for (unsigned i = 1; i < LoadNodes.size(); ++i) {
7856 // All loads much share the same chain.
7857 if (LoadNodes[i].MemNode->getChain() != FirstChain)
7860 int64_t CurrAddress = LoadNodes[i].OffsetFromBase;
7861 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
7863 LastConsecutiveLoad = i;
7865 // Find a legal type for the vector store.
7866 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
7867 if (TLI.isTypeLegal(StoreTy))
7868 LastLegalVectorType = i + 1;
7870 // Find a legal type for the integer store.
7871 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
7872 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7873 if (TLI.isTypeLegal(StoreTy))
7874 LastLegalIntegerType = i + 1;
7877 // Only use vector types if the vector type is larger than the integer type.
7878 // If they are the same, use integers.
7879 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType;
7880 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType);
7882 // We add +1 here because the LastXXX variables refer to location while
7883 // the NumElem refers to array/index size.
7884 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1;
7885 NumElem = std::min(LastLegalType, NumElem);
7890 // The earliest Node in the DAG.
7891 unsigned EarliestNodeUsed = 0;
7892 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
7893 for (unsigned i=1; i<NumElem; ++i) {
7894 // Find a chain for the new wide-store operand. Notice that some
7895 // of the store nodes that we found may not be selected for inclusion
7896 // in the wide store. The chain we use needs to be the chain of the
7897 // earliest store node which is *used* and replaced by the wide store.
7898 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
7899 EarliestNodeUsed = i;
7902 // Find if it is better to use vectors or integers to load and store
7906 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
7908 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
7909 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7912 DebugLoc LoadDL = LoadNodes[0].MemNode->getDebugLoc();
7913 DebugLoc StoreDL = StoreNodes[0].MemNode->getDebugLoc();
7915 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode);
7916 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL,
7917 FirstLoad->getChain(),
7918 FirstLoad->getBasePtr(),
7919 FirstLoad->getPointerInfo(),
7920 false, false, false,
7921 FirstLoad->getAlignment());
7923 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad,
7924 FirstInChain->getBasePtr(),
7925 FirstInChain->getPointerInfo(), false, false,
7926 FirstInChain->getAlignment());
7928 // Replace one of the loads with the new load.
7929 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode);
7930 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1),
7931 SDValue(NewLoad.getNode(), 1));
7933 // Remove the rest of the load chains.
7934 for (unsigned i = 1; i < NumElem ; ++i) {
7935 // Replace all chain users of the old load nodes with the chain of the new
7937 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode);
7938 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain());
7941 // Replace the first store with the new store.
7942 CombineTo(EarliestOp, NewStore);
7943 // Erase all other stores.
7944 for (unsigned i = 0; i < NumElem ; ++i) {
7945 // Remove all Store nodes.
7946 if (StoreNodes[i].MemNode == EarliestOp)
7948 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7949 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
7950 removeFromWorkList(St);
7957 SDValue DAGCombiner::visitSTORE(SDNode *N) {
7958 StoreSDNode *ST = cast<StoreSDNode>(N);
7959 SDValue Chain = ST->getChain();
7960 SDValue Value = ST->getValue();
7961 SDValue Ptr = ST->getBasePtr();
7963 // If this is a store of a bit convert, store the input value if the
7964 // resultant store does not need a higher alignment than the original.
7965 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
7966 ST->isUnindexed()) {
7967 unsigned OrigAlign = ST->getAlignment();
7968 EVT SVT = Value.getOperand(0).getValueType();
7969 unsigned Align = TLI.getDataLayout()->
7970 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
7971 if (Align <= OrigAlign &&
7972 ((!LegalOperations && !ST->isVolatile()) ||
7973 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
7974 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
7975 Ptr, ST->getPointerInfo(), ST->isVolatile(),
7976 ST->isNonTemporal(), OrigAlign);
7979 // Turn 'store undef, Ptr' -> nothing.
7980 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
7983 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
7984 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
7985 // NOTE: If the original store is volatile, this transform must not increase
7986 // the number of stores. For example, on x86-32 an f64 can be stored in one
7987 // processor operation but an i64 (which is not legal) requires two. So the
7988 // transform should not be done in this case.
7989 if (Value.getOpcode() != ISD::TargetConstantFP) {
7991 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
7992 default: llvm_unreachable("Unknown FP type");
7993 case MVT::f16: // We don't do this for these yet.
7999 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
8000 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
8001 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
8002 bitcastToAPInt().getZExtValue(), MVT::i32);
8003 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
8004 Ptr, ST->getPointerInfo(), ST->isVolatile(),
8005 ST->isNonTemporal(), ST->getAlignment());
8009 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
8010 !ST->isVolatile()) ||
8011 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
8012 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
8013 getZExtValue(), MVT::i64);
8014 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
8015 Ptr, ST->getPointerInfo(), ST->isVolatile(),
8016 ST->isNonTemporal(), ST->getAlignment());
8019 if (!ST->isVolatile() &&
8020 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
8021 // Many FP stores are not made apparent until after legalize, e.g. for
8022 // argument passing. Since this is so common, custom legalize the
8023 // 64-bit integer store into two 32-bit stores.
8024 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
8025 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
8026 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
8027 if (TLI.isBigEndian()) std::swap(Lo, Hi);
8029 unsigned Alignment = ST->getAlignment();
8030 bool isVolatile = ST->isVolatile();
8031 bool isNonTemporal = ST->isNonTemporal();
8033 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
8034 Ptr, ST->getPointerInfo(),
8035 isVolatile, isNonTemporal,
8036 ST->getAlignment());
8037 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
8038 DAG.getConstant(4, Ptr.getValueType()));
8039 Alignment = MinAlign(Alignment, 4U);
8040 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
8041 Ptr, ST->getPointerInfo().getWithOffset(4),
8042 isVolatile, isNonTemporal,
8044 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
8053 // Try to infer better alignment information than the store already has.
8054 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
8055 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
8056 if (Align > ST->getAlignment())
8057 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
8058 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8059 ST->isVolatile(), ST->isNonTemporal(), Align);
8063 // Try transforming a pair floating point load / store ops to integer
8064 // load / store ops.
8065 SDValue NewST = TransformFPLoadStorePair(N);
8066 if (NewST.getNode())
8070 // Walk up chain skipping non-aliasing memory nodes.
8071 SDValue BetterChain = FindBetterChain(N, Chain);
8073 // If there is a better chain.
8074 if (Chain != BetterChain) {
8077 // Replace the chain to avoid dependency.
8078 if (ST->isTruncatingStore()) {
8079 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
8080 ST->getPointerInfo(),
8081 ST->getMemoryVT(), ST->isVolatile(),
8082 ST->isNonTemporal(), ST->getAlignment());
8084 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
8085 ST->getPointerInfo(),
8086 ST->isVolatile(), ST->isNonTemporal(),
8087 ST->getAlignment());
8090 // Create token to keep both nodes around.
8091 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
8092 MVT::Other, Chain, ReplStore);
8094 // Make sure the new and old chains are cleaned up.
8095 AddToWorkList(Token.getNode());
8097 // Don't add users to work list.
8098 return CombineTo(N, Token, false);
8102 // Try transforming N to an indexed store.
8103 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
8104 return SDValue(N, 0);
8106 // FIXME: is there such a thing as a truncating indexed store?
8107 if (ST->isTruncatingStore() && ST->isUnindexed() &&
8108 Value.getValueType().isInteger()) {
8109 // See if we can simplify the input to this truncstore with knowledge that
8110 // only the low bits are being used. For example:
8111 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
8113 GetDemandedBits(Value,
8114 APInt::getLowBitsSet(
8115 Value.getValueType().getScalarType().getSizeInBits(),
8116 ST->getMemoryVT().getScalarType().getSizeInBits()));
8117 AddToWorkList(Value.getNode());
8118 if (Shorter.getNode())
8119 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
8120 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8121 ST->isVolatile(), ST->isNonTemporal(),
8122 ST->getAlignment());
8124 // Otherwise, see if we can simplify the operation with
8125 // SimplifyDemandedBits, which only works if the value has a single use.
8126 if (SimplifyDemandedBits(Value,
8127 APInt::getLowBitsSet(
8128 Value.getValueType().getScalarType().getSizeInBits(),
8129 ST->getMemoryVT().getScalarType().getSizeInBits())))
8130 return SDValue(N, 0);
8133 // If this is a load followed by a store to the same location, then the store
8135 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
8136 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
8137 ST->isUnindexed() && !ST->isVolatile() &&
8138 // There can't be any side effects between the load and store, such as
8140 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
8141 // The store is dead, remove it.
8146 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
8147 // truncating store. We can do this even if this is already a truncstore.
8148 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
8149 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
8150 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
8151 ST->getMemoryVT())) {
8152 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
8153 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8154 ST->isVolatile(), ST->isNonTemporal(),
8155 ST->getAlignment());
8158 // Only perform this optimization before the types are legal, because we
8159 // don't want to perform this optimization on every DAGCombine invocation.
8161 bool EverChanged = false;
8164 // There can be multiple store sequences on the same chain.
8165 // Keep trying to merge store sequences until we are unable to do so
8166 // or until we merge the last store on the chain.
8167 bool Changed = MergeConsecutiveStores(ST);
8168 EverChanged |= Changed;
8169 if (!Changed) break;
8170 } while (ST->getOpcode() != ISD::DELETED_NODE);
8173 return SDValue(N, 0);
8176 return ReduceLoadOpStoreWidth(N);
8179 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
8180 SDValue InVec = N->getOperand(0);
8181 SDValue InVal = N->getOperand(1);
8182 SDValue EltNo = N->getOperand(2);
8183 DebugLoc dl = N->getDebugLoc();
8185 // If the inserted element is an UNDEF, just use the input vector.
8186 if (InVal.getOpcode() == ISD::UNDEF)
8189 EVT VT = InVec.getValueType();
8191 // If we can't generate a legal BUILD_VECTOR, exit
8192 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
8195 // Check that we know which element is being inserted
8196 if (!isa<ConstantSDNode>(EltNo))
8198 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8200 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
8201 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
8203 SmallVector<SDValue, 8> Ops;
8204 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
8205 Ops.append(InVec.getNode()->op_begin(),
8206 InVec.getNode()->op_end());
8207 } else if (InVec.getOpcode() == ISD::UNDEF) {
8208 unsigned NElts = VT.getVectorNumElements();
8209 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
8214 // Insert the element
8215 if (Elt < Ops.size()) {
8216 // All the operands of BUILD_VECTOR must have the same type;
8217 // we enforce that here.
8218 EVT OpVT = Ops[0].getValueType();
8219 if (InVal.getValueType() != OpVT)
8220 InVal = OpVT.bitsGT(InVal.getValueType()) ?
8221 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
8222 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
8226 // Return the new vector
8227 return DAG.getNode(ISD::BUILD_VECTOR, dl,
8228 VT, &Ops[0], Ops.size());
8231 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
8232 // (vextract (scalar_to_vector val, 0) -> val
8233 SDValue InVec = N->getOperand(0);
8234 EVT VT = InVec.getValueType();
8235 EVT NVT = N->getValueType(0);
8237 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
8238 // Check if the result type doesn't match the inserted element type. A
8239 // SCALAR_TO_VECTOR may truncate the inserted element and the
8240 // EXTRACT_VECTOR_ELT may widen the extracted vector.
8241 SDValue InOp = InVec.getOperand(0);
8242 if (InOp.getValueType() != NVT) {
8243 assert(InOp.getValueType().isInteger() && NVT.isInteger());
8244 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
8249 SDValue EltNo = N->getOperand(1);
8250 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
8252 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
8253 // We only perform this optimization before the op legalization phase because
8254 // we may introduce new vector instructions which are not backed by TD
8255 // patterns. For example on AVX, extracting elements from a wide vector
8256 // without using extract_subvector.
8257 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
8258 && ConstEltNo && !LegalOperations) {
8259 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8260 int NumElem = VT.getVectorNumElements();
8261 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
8262 // Find the new index to extract from.
8263 int OrigElt = SVOp->getMaskElt(Elt);
8265 // Extracting an undef index is undef.
8267 return DAG.getUNDEF(NVT);
8269 // Select the right vector half to extract from.
8270 if (OrigElt < NumElem) {
8271 InVec = InVec->getOperand(0);
8273 InVec = InVec->getOperand(1);
8277 EVT IndexTy = N->getOperand(1).getValueType();
8278 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT,
8279 InVec, DAG.getConstant(OrigElt, IndexTy));
8282 // Perform only after legalization to ensure build_vector / vector_shuffle
8283 // optimizations have already been done.
8284 if (!LegalOperations) return SDValue();
8286 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
8287 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
8288 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
8291 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8292 bool NewLoad = false;
8293 bool BCNumEltsChanged = false;
8294 EVT ExtVT = VT.getVectorElementType();
8297 // If the result of load has to be truncated, then it's not necessarily
8299 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
8302 if (InVec.getOpcode() == ISD::BITCAST) {
8303 // Don't duplicate a load with other uses.
8304 if (!InVec.hasOneUse())
8307 EVT BCVT = InVec.getOperand(0).getValueType();
8308 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
8310 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
8311 BCNumEltsChanged = true;
8312 InVec = InVec.getOperand(0);
8313 ExtVT = BCVT.getVectorElementType();
8317 LoadSDNode *LN0 = NULL;
8318 const ShuffleVectorSDNode *SVN = NULL;
8319 if (ISD::isNormalLoad(InVec.getNode())) {
8320 LN0 = cast<LoadSDNode>(InVec);
8321 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
8322 InVec.getOperand(0).getValueType() == ExtVT &&
8323 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
8324 // Don't duplicate a load with other uses.
8325 if (!InVec.hasOneUse())
8328 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
8329 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
8330 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
8332 // (load $addr+1*size)
8334 // Don't duplicate a load with other uses.
8335 if (!InVec.hasOneUse())
8338 // If the bit convert changed the number of elements, it is unsafe
8339 // to examine the mask.
8340 if (BCNumEltsChanged)
8343 // Select the input vector, guarding against out of range extract vector.
8344 unsigned NumElems = VT.getVectorNumElements();
8345 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
8346 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
8348 if (InVec.getOpcode() == ISD::BITCAST) {
8349 // Don't duplicate a load with other uses.
8350 if (!InVec.hasOneUse())
8353 InVec = InVec.getOperand(0);
8355 if (ISD::isNormalLoad(InVec.getNode())) {
8356 LN0 = cast<LoadSDNode>(InVec);
8357 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
8361 // Make sure we found a non-volatile load and the extractelement is
8363 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
8366 // If Idx was -1 above, Elt is going to be -1, so just return undef.
8368 return DAG.getUNDEF(LVT);
8370 unsigned Align = LN0->getAlignment();
8372 // Check the resultant load doesn't need a higher alignment than the
8376 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
8378 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
8384 SDValue NewPtr = LN0->getBasePtr();
8385 unsigned PtrOff = 0;
8388 PtrOff = LVT.getSizeInBits() * Elt / 8;
8389 EVT PtrType = NewPtr.getValueType();
8390 if (TLI.isBigEndian())
8391 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
8392 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
8393 DAG.getConstant(PtrOff, PtrType));
8396 // The replacement we need to do here is a little tricky: we need to
8397 // replace an extractelement of a load with a load.
8398 // Use ReplaceAllUsesOfValuesWith to do the replacement.
8399 // Note that this replacement assumes that the extractvalue is the only
8400 // use of the load; that's okay because we don't want to perform this
8401 // transformation in other cases anyway.
8404 if (NVT.bitsGT(LVT)) {
8405 // If the result type of vextract is wider than the load, then issue an
8406 // extending load instead.
8407 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT)
8408 ? ISD::ZEXTLOAD : ISD::EXTLOAD;
8409 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(),
8410 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff),
8411 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align);
8412 Chain = Load.getValue(1);
8414 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
8415 LN0->getPointerInfo().getWithOffset(PtrOff),
8416 LN0->isVolatile(), LN0->isNonTemporal(),
8417 LN0->isInvariant(), Align);
8418 Chain = Load.getValue(1);
8419 if (NVT.bitsLT(LVT))
8420 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load);
8422 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load);
8424 WorkListRemover DeadNodes(*this);
8425 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) };
8426 SDValue To[] = { Load, Chain };
8427 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
8428 // Since we're explcitly calling ReplaceAllUses, add the new node to the
8429 // worklist explicitly as well.
8430 AddToWorkList(Load.getNode());
8431 AddUsersToWorkList(Load.getNode()); // Add users too
8432 // Make sure to revisit this node to clean it up; it will usually be dead.
8434 return SDValue(N, 0);
8440 // Simplify (build_vec (ext )) to (bitcast (build_vec ))
8441 SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) {
8442 // We perform this optimization post type-legalization because
8443 // the type-legalizer often scalarizes integer-promoted vectors.
8444 // Performing this optimization before may create bit-casts which
8445 // will be type-legalized to complex code sequences.
8446 // We perform this optimization only before the operation legalizer because we
8447 // may introduce illegal operations.
8448 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes)
8451 unsigned NumInScalars = N->getNumOperands();
8452 DebugLoc dl = N->getDebugLoc();
8453 EVT VT = N->getValueType(0);
8455 // Check to see if this is a BUILD_VECTOR of a bunch of values
8456 // which come from any_extend or zero_extend nodes. If so, we can create
8457 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
8458 // optimizations. We do not handle sign-extend because we can't fill the sign
8460 EVT SourceType = MVT::Other;
8461 bool AllAnyExt = true;
8463 for (unsigned i = 0; i != NumInScalars; ++i) {
8464 SDValue In = N->getOperand(i);
8465 // Ignore undef inputs.
8466 if (In.getOpcode() == ISD::UNDEF) continue;
8468 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
8469 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
8471 // Abort if the element is not an extension.
8472 if (!ZeroExt && !AnyExt) {
8473 SourceType = MVT::Other;
8477 // The input is a ZeroExt or AnyExt. Check the original type.
8478 EVT InTy = In.getOperand(0).getValueType();
8480 // Check that all of the widened source types are the same.
8481 if (SourceType == MVT::Other)
8484 else if (InTy != SourceType) {
8485 // Multiple income types. Abort.
8486 SourceType = MVT::Other;
8490 // Check if all of the extends are ANY_EXTENDs.
8491 AllAnyExt &= AnyExt;
8494 // In order to have valid types, all of the inputs must be extended from the
8495 // same source type and all of the inputs must be any or zero extend.
8496 // Scalar sizes must be a power of two.
8497 EVT OutScalarTy = VT.getScalarType();
8498 bool ValidTypes = SourceType != MVT::Other &&
8499 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
8500 isPowerOf2_32(SourceType.getSizeInBits());
8502 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
8503 // turn into a single shuffle instruction.
8507 bool isLE = TLI.isLittleEndian();
8508 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
8509 assert(ElemRatio > 1 && "Invalid element size ratio");
8510 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
8511 DAG.getConstant(0, SourceType);
8513 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements();
8514 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
8516 // Populate the new build_vector
8517 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
8518 SDValue Cast = N->getOperand(i);
8519 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
8520 Cast.getOpcode() == ISD::ZERO_EXTEND ||
8521 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
8523 if (Cast.getOpcode() == ISD::UNDEF)
8524 In = DAG.getUNDEF(SourceType);
8526 In = Cast->getOperand(0);
8527 unsigned Index = isLE ? (i * ElemRatio) :
8528 (i * ElemRatio + (ElemRatio - 1));
8530 assert(Index < Ops.size() && "Invalid index");
8534 // The type of the new BUILD_VECTOR node.
8535 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
8536 assert(VecVT.getSizeInBits() == VT.getSizeInBits() &&
8537 "Invalid vector size");
8538 // Check if the new vector type is legal.
8539 if (!isTypeLegal(VecVT)) return SDValue();
8541 // Make the new BUILD_VECTOR.
8542 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], Ops.size());
8544 // The new BUILD_VECTOR node has the potential to be further optimized.
8545 AddToWorkList(BV.getNode());
8546 // Bitcast to the desired type.
8547 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8550 SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
8551 EVT VT = N->getValueType(0);
8553 unsigned NumInScalars = N->getNumOperands();
8554 DebugLoc dl = N->getDebugLoc();
8556 EVT SrcVT = MVT::Other;
8557 unsigned Opcode = ISD::DELETED_NODE;
8558 unsigned NumDefs = 0;
8560 for (unsigned i = 0; i != NumInScalars; ++i) {
8561 SDValue In = N->getOperand(i);
8562 unsigned Opc = In.getOpcode();
8564 if (Opc == ISD::UNDEF)
8567 // If all scalar values are floats and converted from integers.
8568 if (Opcode == ISD::DELETED_NODE &&
8569 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
8571 // If not supported by target, bail out.
8572 if (TLI.getOperationAction(Opcode, VT) != TargetLowering::Legal &&
8573 TLI.getOperationAction(Opcode, VT) != TargetLowering::Custom)
8579 EVT InVT = In.getOperand(0).getValueType();
8581 // If all scalar values are typed differently, bail out. It's chosen to
8582 // simplify BUILD_VECTOR of integer types.
8583 if (SrcVT == MVT::Other)
8590 // If the vector has just one element defined, it's not worth to fold it into
8591 // a vectorized one.
8595 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP)
8596 && "Should only handle conversion from integer to float.");
8597 assert(SrcVT != MVT::Other && "Cannot determine source type!");
8599 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
8600 SmallVector<SDValue, 8> Opnds;
8601 for (unsigned i = 0; i != NumInScalars; ++i) {
8602 SDValue In = N->getOperand(i);
8604 if (In.getOpcode() == ISD::UNDEF)
8605 Opnds.push_back(DAG.getUNDEF(SrcVT));
8607 Opnds.push_back(In.getOperand(0));
8609 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT,
8610 &Opnds[0], Opnds.size());
8611 AddToWorkList(BV.getNode());
8613 return DAG.getNode(Opcode, dl, VT, BV);
8616 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
8617 unsigned NumInScalars = N->getNumOperands();
8618 DebugLoc dl = N->getDebugLoc();
8619 EVT VT = N->getValueType(0);
8621 // A vector built entirely of undefs is undef.
8622 if (ISD::allOperandsUndef(N))
8623 return DAG.getUNDEF(VT);
8625 SDValue V = reduceBuildVecExtToExtBuildVec(N);
8629 V = reduceBuildVecConvertToConvertBuildVec(N);
8633 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
8634 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
8635 // at most two distinct vectors, turn this into a shuffle node.
8637 // May only combine to shuffle after legalize if shuffle is legal.
8638 if (LegalOperations &&
8639 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))
8642 SDValue VecIn1, VecIn2;
8643 for (unsigned i = 0; i != NumInScalars; ++i) {
8644 // Ignore undef inputs.
8645 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
8647 // If this input is something other than a EXTRACT_VECTOR_ELT with a
8648 // constant index, bail out.
8649 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8650 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
8651 VecIn1 = VecIn2 = SDValue(0, 0);
8655 // We allow up to two distinct input vectors.
8656 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
8657 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
8660 if (VecIn1.getNode() == 0) {
8661 VecIn1 = ExtractedFromVec;
8662 } else if (VecIn2.getNode() == 0) {
8663 VecIn2 = ExtractedFromVec;
8666 VecIn1 = VecIn2 = SDValue(0, 0);
8671 // If everything is good, we can make a shuffle operation.
8672 if (VecIn1.getNode()) {
8673 SmallVector<int, 8> Mask;
8674 for (unsigned i = 0; i != NumInScalars; ++i) {
8675 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
8680 // If extracting from the first vector, just use the index directly.
8681 SDValue Extract = N->getOperand(i);
8682 SDValue ExtVal = Extract.getOperand(1);
8683 if (Extract.getOperand(0) == VecIn1) {
8684 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
8685 if (ExtIndex > VT.getVectorNumElements())
8688 Mask.push_back(ExtIndex);
8692 // Otherwise, use InIdx + VecSize
8693 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
8694 Mask.push_back(Idx+NumInScalars);
8697 // We can't generate a shuffle node with mismatched input and output types.
8698 // Attempt to transform a single input vector to the correct type.
8699 if ((VT != VecIn1.getValueType())) {
8700 // We don't support shuffeling between TWO values of different types.
8701 if (VecIn2.getNode() != 0)
8704 // We only support widening of vectors which are half the size of the
8705 // output registers. For example XMM->YMM widening on X86 with AVX.
8706 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
8709 // If the input vector type has a different base type to the output
8710 // vector type, bail out.
8711 if (VecIn1.getValueType().getVectorElementType() !=
8712 VT.getVectorElementType())
8715 // Widen the input vector by adding undef values.
8716 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8717 VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
8720 // If VecIn2 is unused then change it to undef.
8721 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
8723 // Check that we were able to transform all incoming values to the same
8725 if (VecIn2.getValueType() != VecIn1.getValueType() ||
8726 VecIn1.getValueType() != VT)
8729 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
8730 if (!isTypeLegal(VT))
8733 // Return the new VECTOR_SHUFFLE node.
8737 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]);
8743 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
8744 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
8745 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
8746 // inputs come from at most two distinct vectors, turn this into a shuffle
8749 // If we only have one input vector, we don't need to do any concatenation.
8750 if (N->getNumOperands() == 1)
8751 return N->getOperand(0);
8753 // Check if all of the operands are undefs.
8754 if (ISD::allOperandsUndef(N))
8755 return DAG.getUNDEF(N->getValueType(0));
8760 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
8761 EVT NVT = N->getValueType(0);
8762 SDValue V = N->getOperand(0);
8764 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
8765 // Handle only simple case where vector being inserted and vector
8766 // being extracted are of same type, and are half size of larger vectors.
8767 EVT BigVT = V->getOperand(0).getValueType();
8768 EVT SmallVT = V->getOperand(1).getValueType();
8769 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
8772 // Only handle cases where both indexes are constants with the same type.
8773 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
8774 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
8776 if (InsIdx && ExtIdx &&
8777 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
8778 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
8780 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
8782 // indices are equal => V1
8783 // otherwise => (extract_subvec V1, ExtIdx)
8784 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue())
8785 return V->getOperand(1);
8786 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT,
8787 V->getOperand(0), N->getOperand(1));
8791 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
8793 // (extract_subvec (concat V1, V2, ...), i)
8796 // Only operand 0 is checked as 'concat' assumes all inputs of the same type.
8797 if (V->getOperand(0).getValueType() != NVT)
8799 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8800 unsigned NumElems = NVT.getVectorNumElements();
8801 assert((Idx % NumElems) == 0 &&
8802 "IDX in concat is not a multiple of the result vector length.");
8803 return V->getOperand(Idx / NumElems);
8809 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
8810 EVT VT = N->getValueType(0);
8811 unsigned NumElts = VT.getVectorNumElements();
8813 SDValue N0 = N->getOperand(0);
8814 SDValue N1 = N->getOperand(1);
8816 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
8818 // Canonicalize shuffle undef, undef -> undef
8819 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
8820 return DAG.getUNDEF(VT);
8822 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8824 // Canonicalize shuffle v, v -> v, undef
8826 SmallVector<int, 8> NewMask;
8827 for (unsigned i = 0; i != NumElts; ++i) {
8828 int Idx = SVN->getMaskElt(i);
8829 if (Idx >= (int)NumElts) Idx -= NumElts;
8830 NewMask.push_back(Idx);
8832 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT),
8836 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
8837 if (N0.getOpcode() == ISD::UNDEF) {
8838 SmallVector<int, 8> NewMask;
8839 for (unsigned i = 0; i != NumElts; ++i) {
8840 int Idx = SVN->getMaskElt(i);
8842 if (Idx < (int)NumElts)
8847 NewMask.push_back(Idx);
8849 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT),
8853 // Remove references to rhs if it is undef
8854 if (N1.getOpcode() == ISD::UNDEF) {
8855 bool Changed = false;
8856 SmallVector<int, 8> NewMask;
8857 for (unsigned i = 0; i != NumElts; ++i) {
8858 int Idx = SVN->getMaskElt(i);
8859 if (Idx >= (int)NumElts) {
8863 NewMask.push_back(Idx);
8866 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]);
8869 // If it is a splat, check if the argument vector is another splat or a
8870 // build_vector with all scalar elements the same.
8871 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
8872 SDNode *V = N0.getNode();
8874 // If this is a bit convert that changes the element type of the vector but
8875 // not the number of vector elements, look through it. Be careful not to
8876 // look though conversions that change things like v4f32 to v2f64.
8877 if (V->getOpcode() == ISD::BITCAST) {
8878 SDValue ConvInput = V->getOperand(0);
8879 if (ConvInput.getValueType().isVector() &&
8880 ConvInput.getValueType().getVectorNumElements() == NumElts)
8881 V = ConvInput.getNode();
8884 if (V->getOpcode() == ISD::BUILD_VECTOR) {
8885 assert(V->getNumOperands() == NumElts &&
8886 "BUILD_VECTOR has wrong number of operands");
8888 bool AllSame = true;
8889 for (unsigned i = 0; i != NumElts; ++i) {
8890 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
8891 Base = V->getOperand(i);
8895 // Splat of <u, u, u, u>, return <u, u, u, u>
8896 if (!Base.getNode())
8898 for (unsigned i = 0; i != NumElts; ++i) {
8899 if (V->getOperand(i) != Base) {
8904 // Splat of <x, x, x, x>, return <x, x, x, x>
8910 // If this shuffle node is simply a swizzle of another shuffle node,
8911 // and it reverses the swizzle of the previous shuffle then we can
8912 // optimize shuffle(shuffle(x, undef), undef) -> x.
8913 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
8914 N1.getOpcode() == ISD::UNDEF) {
8916 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
8918 // Shuffle nodes can only reverse shuffles with a single non-undef value.
8919 if (N0.getOperand(1).getOpcode() != ISD::UNDEF)
8922 // The incoming shuffle must be of the same type as the result of the
8924 assert(OtherSV->getOperand(0).getValueType() == VT &&
8925 "Shuffle types don't match");
8927 for (unsigned i = 0; i != NumElts; ++i) {
8928 int Idx = SVN->getMaskElt(i);
8929 assert(Idx < (int)NumElts && "Index references undef operand");
8930 // Next, this index comes from the first value, which is the incoming
8931 // shuffle. Adopt the incoming index.
8933 Idx = OtherSV->getMaskElt(Idx);
8935 // The combined shuffle must map each index to itself.
8936 if (Idx >= 0 && (unsigned)Idx != i)
8940 return OtherSV->getOperand(0);
8946 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
8947 if (!TLI.getShouldFoldAtomicFences())
8950 SDValue atomic = N->getOperand(0);
8951 switch (atomic.getOpcode()) {
8952 case ISD::ATOMIC_CMP_SWAP:
8953 case ISD::ATOMIC_SWAP:
8954 case ISD::ATOMIC_LOAD_ADD:
8955 case ISD::ATOMIC_LOAD_SUB:
8956 case ISD::ATOMIC_LOAD_AND:
8957 case ISD::ATOMIC_LOAD_OR:
8958 case ISD::ATOMIC_LOAD_XOR:
8959 case ISD::ATOMIC_LOAD_NAND:
8960 case ISD::ATOMIC_LOAD_MIN:
8961 case ISD::ATOMIC_LOAD_MAX:
8962 case ISD::ATOMIC_LOAD_UMIN:
8963 case ISD::ATOMIC_LOAD_UMAX:
8969 SDValue fence = atomic.getOperand(0);
8970 if (fence.getOpcode() != ISD::MEMBARRIER)
8973 switch (atomic.getOpcode()) {
8974 case ISD::ATOMIC_CMP_SWAP:
8975 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
8976 fence.getOperand(0),
8977 atomic.getOperand(1), atomic.getOperand(2),
8978 atomic.getOperand(3)), atomic.getResNo());
8979 case ISD::ATOMIC_SWAP:
8980 case ISD::ATOMIC_LOAD_ADD:
8981 case ISD::ATOMIC_LOAD_SUB:
8982 case ISD::ATOMIC_LOAD_AND:
8983 case ISD::ATOMIC_LOAD_OR:
8984 case ISD::ATOMIC_LOAD_XOR:
8985 case ISD::ATOMIC_LOAD_NAND:
8986 case ISD::ATOMIC_LOAD_MIN:
8987 case ISD::ATOMIC_LOAD_MAX:
8988 case ISD::ATOMIC_LOAD_UMIN:
8989 case ISD::ATOMIC_LOAD_UMAX:
8990 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
8991 fence.getOperand(0),
8992 atomic.getOperand(1), atomic.getOperand(2)),
8999 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
9000 /// an AND to a vector_shuffle with the destination vector and a zero vector.
9001 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
9002 /// vector_shuffle V, Zero, <0, 4, 2, 4>
9003 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
9004 EVT VT = N->getValueType(0);
9005 DebugLoc dl = N->getDebugLoc();
9006 SDValue LHS = N->getOperand(0);
9007 SDValue RHS = N->getOperand(1);
9008 if (N->getOpcode() == ISD::AND) {
9009 if (RHS.getOpcode() == ISD::BITCAST)
9010 RHS = RHS.getOperand(0);
9011 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
9012 SmallVector<int, 8> Indices;
9013 unsigned NumElts = RHS.getNumOperands();
9014 for (unsigned i = 0; i != NumElts; ++i) {
9015 SDValue Elt = RHS.getOperand(i);
9016 if (!isa<ConstantSDNode>(Elt))
9019 if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
9020 Indices.push_back(i);
9021 else if (cast<ConstantSDNode>(Elt)->isNullValue())
9022 Indices.push_back(NumElts);
9027 // Let's see if the target supports this vector_shuffle.
9028 EVT RVT = RHS.getValueType();
9029 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
9032 // Return the new VECTOR_SHUFFLE node.
9033 EVT EltVT = RVT.getVectorElementType();
9034 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
9035 DAG.getConstant(0, EltVT));
9036 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
9037 RVT, &ZeroOps[0], ZeroOps.size());
9038 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
9039 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
9040 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
9047 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
9048 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
9049 // After legalize, the target may be depending on adds and other
9050 // binary ops to provide legal ways to construct constants or other
9051 // things. Simplifying them may result in a loss of legality.
9052 if (LegalOperations) return SDValue();
9054 assert(N->getValueType(0).isVector() &&
9055 "SimplifyVBinOp only works on vectors!");
9057 SDValue LHS = N->getOperand(0);
9058 SDValue RHS = N->getOperand(1);
9059 SDValue Shuffle = XformToShuffleWithZero(N);
9060 if (Shuffle.getNode()) return Shuffle;
9062 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
9064 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
9065 RHS.getOpcode() == ISD::BUILD_VECTOR) {
9066 SmallVector<SDValue, 8> Ops;
9067 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
9068 SDValue LHSOp = LHS.getOperand(i);
9069 SDValue RHSOp = RHS.getOperand(i);
9070 // If these two elements can't be folded, bail out.
9071 if ((LHSOp.getOpcode() != ISD::UNDEF &&
9072 LHSOp.getOpcode() != ISD::Constant &&
9073 LHSOp.getOpcode() != ISD::ConstantFP) ||
9074 (RHSOp.getOpcode() != ISD::UNDEF &&
9075 RHSOp.getOpcode() != ISD::Constant &&
9076 RHSOp.getOpcode() != ISD::ConstantFP))
9079 // Can't fold divide by zero.
9080 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
9081 N->getOpcode() == ISD::FDIV) {
9082 if ((RHSOp.getOpcode() == ISD::Constant &&
9083 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
9084 (RHSOp.getOpcode() == ISD::ConstantFP &&
9085 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
9089 EVT VT = LHSOp.getValueType();
9090 EVT RVT = RHSOp.getValueType();
9092 // Integer BUILD_VECTOR operands may have types larger than the element
9093 // size (e.g., when the element type is not legal). Prior to type
9094 // legalization, the types may not match between the two BUILD_VECTORS.
9095 // Truncate one of the operands to make them match.
9096 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
9097 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp);
9099 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp);
9103 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
9105 if (FoldOp.getOpcode() != ISD::UNDEF &&
9106 FoldOp.getOpcode() != ISD::Constant &&
9107 FoldOp.getOpcode() != ISD::ConstantFP)
9109 Ops.push_back(FoldOp);
9110 AddToWorkList(FoldOp.getNode());
9113 if (Ops.size() == LHS.getNumOperands())
9114 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
9115 LHS.getValueType(), &Ops[0], Ops.size());
9121 /// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG.
9122 SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) {
9123 // After legalize, the target may be depending on adds and other
9124 // binary ops to provide legal ways to construct constants or other
9125 // things. Simplifying them may result in a loss of legality.
9126 if (LegalOperations) return SDValue();
9128 assert(N->getValueType(0).isVector() &&
9129 "SimplifyVUnaryOp only works on vectors!");
9131 SDValue N0 = N->getOperand(0);
9133 if (N0.getOpcode() != ISD::BUILD_VECTOR)
9136 // Operand is a BUILD_VECTOR node, see if we can constant fold it.
9137 SmallVector<SDValue, 8> Ops;
9138 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
9139 SDValue Op = N0.getOperand(i);
9140 if (Op.getOpcode() != ISD::UNDEF &&
9141 Op.getOpcode() != ISD::ConstantFP)
9143 EVT EltVT = Op.getValueType();
9144 SDValue FoldOp = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), EltVT, Op);
9145 if (FoldOp.getOpcode() != ISD::UNDEF &&
9146 FoldOp.getOpcode() != ISD::ConstantFP)
9148 Ops.push_back(FoldOp);
9149 AddToWorkList(FoldOp.getNode());
9152 if (Ops.size() != N0.getNumOperands())
9155 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
9156 N0.getValueType(), &Ops[0], Ops.size());
9159 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
9160 SDValue N1, SDValue N2){
9161 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
9163 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
9164 cast<CondCodeSDNode>(N0.getOperand(2))->get());
9166 // If we got a simplified select_cc node back from SimplifySelectCC, then
9167 // break it down into a new SETCC node, and a new SELECT node, and then return
9168 // the SELECT node, since we were called with a SELECT node.
9169 if (SCC.getNode()) {
9170 // Check to see if we got a select_cc back (to turn into setcc/select).
9171 // Otherwise, just return whatever node we got back, like fabs.
9172 if (SCC.getOpcode() == ISD::SELECT_CC) {
9173 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
9175 SCC.getOperand(0), SCC.getOperand(1),
9177 AddToWorkList(SETCC.getNode());
9178 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
9179 SCC.getOperand(2), SCC.getOperand(3), SETCC);
9187 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
9188 /// are the two values being selected between, see if we can simplify the
9189 /// select. Callers of this should assume that TheSelect is deleted if this
9190 /// returns true. As such, they should return the appropriate thing (e.g. the
9191 /// node) back to the top-level of the DAG combiner loop to avoid it being
9193 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
9196 // Cannot simplify select with vector condition
9197 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
9199 // If this is a select from two identical things, try to pull the operation
9200 // through the select.
9201 if (LHS.getOpcode() != RHS.getOpcode() ||
9202 !LHS.hasOneUse() || !RHS.hasOneUse())
9205 // If this is a load and the token chain is identical, replace the select
9206 // of two loads with a load through a select of the address to load from.
9207 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
9208 // constants have been dropped into the constant pool.
9209 if (LHS.getOpcode() == ISD::LOAD) {
9210 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
9211 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
9213 // Token chains must be identical.
9214 if (LHS.getOperand(0) != RHS.getOperand(0) ||
9215 // Do not let this transformation reduce the number of volatile loads.
9216 LLD->isVolatile() || RLD->isVolatile() ||
9217 // If this is an EXTLOAD, the VT's must match.
9218 LLD->getMemoryVT() != RLD->getMemoryVT() ||
9219 // If this is an EXTLOAD, the kind of extension must match.
9220 (LLD->getExtensionType() != RLD->getExtensionType() &&
9221 // The only exception is if one of the extensions is anyext.
9222 LLD->getExtensionType() != ISD::EXTLOAD &&
9223 RLD->getExtensionType() != ISD::EXTLOAD) ||
9224 // FIXME: this discards src value information. This is
9225 // over-conservative. It would be beneficial to be able to remember
9226 // both potential memory locations. Since we are discarding
9227 // src value info, don't do the transformation if the memory
9228 // locations are not in the default address space.
9229 LLD->getPointerInfo().getAddrSpace() != 0 ||
9230 RLD->getPointerInfo().getAddrSpace() != 0)
9233 // Check that the select condition doesn't reach either load. If so,
9234 // folding this will induce a cycle into the DAG. If not, this is safe to
9235 // xform, so create a select of the addresses.
9237 if (TheSelect->getOpcode() == ISD::SELECT) {
9238 SDNode *CondNode = TheSelect->getOperand(0).getNode();
9239 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
9240 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
9242 // The loads must not depend on one another.
9243 if (LLD->isPredecessorOf(RLD) ||
9244 RLD->isPredecessorOf(LLD))
9246 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
9247 LLD->getBasePtr().getValueType(),
9248 TheSelect->getOperand(0), LLD->getBasePtr(),
9250 } else { // Otherwise SELECT_CC
9251 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
9252 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
9254 if ((LLD->hasAnyUseOfValue(1) &&
9255 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
9256 (RLD->hasAnyUseOfValue(1) &&
9257 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
9260 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
9261 LLD->getBasePtr().getValueType(),
9262 TheSelect->getOperand(0),
9263 TheSelect->getOperand(1),
9264 LLD->getBasePtr(), RLD->getBasePtr(),
9265 TheSelect->getOperand(4));
9269 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
9270 Load = DAG.getLoad(TheSelect->getValueType(0),
9271 TheSelect->getDebugLoc(),
9272 // FIXME: Discards pointer info.
9273 LLD->getChain(), Addr, MachinePointerInfo(),
9274 LLD->isVolatile(), LLD->isNonTemporal(),
9275 LLD->isInvariant(), LLD->getAlignment());
9277 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
9278 RLD->getExtensionType() : LLD->getExtensionType(),
9279 TheSelect->getDebugLoc(),
9280 TheSelect->getValueType(0),
9281 // FIXME: Discards pointer info.
9282 LLD->getChain(), Addr, MachinePointerInfo(),
9283 LLD->getMemoryVT(), LLD->isVolatile(),
9284 LLD->isNonTemporal(), LLD->getAlignment());
9287 // Users of the select now use the result of the load.
9288 CombineTo(TheSelect, Load);
9290 // Users of the old loads now use the new load's chain. We know the
9291 // old-load value is dead now.
9292 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
9293 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
9300 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
9301 /// where 'cond' is the comparison specified by CC.
9302 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
9303 SDValue N2, SDValue N3,
9304 ISD::CondCode CC, bool NotExtCompare) {
9305 // (x ? y : y) -> y.
9306 if (N2 == N3) return N2;
9308 EVT VT = N2.getValueType();
9309 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
9310 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
9311 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
9313 // Determine if the condition we're dealing with is constant
9314 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
9315 N0, N1, CC, DL, false);
9316 if (SCC.getNode()) AddToWorkList(SCC.getNode());
9317 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
9319 // fold select_cc true, x, y -> x
9320 if (SCCC && !SCCC->isNullValue())
9322 // fold select_cc false, x, y -> y
9323 if (SCCC && SCCC->isNullValue())
9326 // Check to see if we can simplify the select into an fabs node
9327 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
9328 // Allow either -0.0 or 0.0
9329 if (CFP->getValueAPF().isZero()) {
9330 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
9331 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
9332 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
9333 N2 == N3.getOperand(0))
9334 return DAG.getNode(ISD::FABS, DL, VT, N0);
9336 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
9337 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
9338 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
9339 N2.getOperand(0) == N3)
9340 return DAG.getNode(ISD::FABS, DL, VT, N3);
9344 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
9345 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
9346 // in it. This is a win when the constant is not otherwise available because
9347 // it replaces two constant pool loads with one. We only do this if the FP
9348 // type is known to be legal, because if it isn't, then we are before legalize
9349 // types an we want the other legalization to happen first (e.g. to avoid
9350 // messing with soft float) and if the ConstantFP is not legal, because if
9351 // it is legal, we may not need to store the FP constant in a constant pool.
9352 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
9353 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
9354 if (TLI.isTypeLegal(N2.getValueType()) &&
9355 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
9356 TargetLowering::Legal) &&
9357 // If both constants have multiple uses, then we won't need to do an
9358 // extra load, they are likely around in registers for other users.
9359 (TV->hasOneUse() || FV->hasOneUse())) {
9360 Constant *Elts[] = {
9361 const_cast<ConstantFP*>(FV->getConstantFPValue()),
9362 const_cast<ConstantFP*>(TV->getConstantFPValue())
9364 Type *FPTy = Elts[0]->getType();
9365 const DataLayout &TD = *TLI.getDataLayout();
9367 // Create a ConstantArray of the two constants.
9368 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
9369 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
9370 TD.getPrefTypeAlignment(FPTy));
9371 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9373 // Get the offsets to the 0 and 1 element of the array so that we can
9374 // select between them.
9375 SDValue Zero = DAG.getIntPtrConstant(0);
9376 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
9377 SDValue One = DAG.getIntPtrConstant(EltSize);
9379 SDValue Cond = DAG.getSetCC(DL,
9380 TLI.getSetCCResultType(N0.getValueType()),
9382 AddToWorkList(Cond.getNode());
9383 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
9385 AddToWorkList(CstOffset.getNode());
9386 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
9388 AddToWorkList(CPIdx.getNode());
9389 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
9390 MachinePointerInfo::getConstantPool(), false,
9391 false, false, Alignment);
9396 // Check to see if we can perform the "gzip trick", transforming
9397 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
9398 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
9399 (N1C->isNullValue() || // (a < 0) ? b : 0
9400 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
9401 EVT XType = N0.getValueType();
9402 EVT AType = N2.getValueType();
9403 if (XType.bitsGE(AType)) {
9404 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
9405 // single-bit constant.
9406 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
9407 unsigned ShCtV = N2C->getAPIntValue().logBase2();
9408 ShCtV = XType.getSizeInBits()-ShCtV-1;
9409 SDValue ShCt = DAG.getConstant(ShCtV,
9410 getShiftAmountTy(N0.getValueType()));
9411 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
9413 AddToWorkList(Shift.getNode());
9415 if (XType.bitsGT(AType)) {
9416 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
9417 AddToWorkList(Shift.getNode());
9420 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
9423 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
9425 DAG.getConstant(XType.getSizeInBits()-1,
9426 getShiftAmountTy(N0.getValueType())));
9427 AddToWorkList(Shift.getNode());
9429 if (XType.bitsGT(AType)) {
9430 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
9431 AddToWorkList(Shift.getNode());
9434 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
9438 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
9439 // where y is has a single bit set.
9440 // A plaintext description would be, we can turn the SELECT_CC into an AND
9441 // when the condition can be materialized as an all-ones register. Any
9442 // single bit-test can be materialized as an all-ones register with
9443 // shift-left and shift-right-arith.
9444 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
9445 N0->getValueType(0) == VT &&
9446 N1C && N1C->isNullValue() &&
9447 N2C && N2C->isNullValue()) {
9448 SDValue AndLHS = N0->getOperand(0);
9449 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
9450 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
9451 // Shift the tested bit over the sign bit.
9452 APInt AndMask = ConstAndRHS->getAPIntValue();
9454 DAG.getConstant(AndMask.countLeadingZeros(),
9455 getShiftAmountTy(AndLHS.getValueType()));
9456 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
9458 // Now arithmetic right shift it all the way over, so the result is either
9459 // all-ones, or zero.
9461 DAG.getConstant(AndMask.getBitWidth()-1,
9462 getShiftAmountTy(Shl.getValueType()));
9463 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
9465 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
9469 // fold select C, 16, 0 -> shl C, 4
9470 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
9471 TLI.getBooleanContents(N0.getValueType().isVector()) ==
9472 TargetLowering::ZeroOrOneBooleanContent) {
9474 // If the caller doesn't want us to simplify this into a zext of a compare,
9476 if (NotExtCompare && N2C->getAPIntValue() == 1)
9479 // Get a SetCC of the condition
9480 // NOTE: Don't create a SETCC if it's not legal on this target.
9481 if (!LegalOperations ||
9482 TLI.isOperationLegal(ISD::SETCC,
9483 LegalTypes ? TLI.getSetCCResultType(N0.getValueType()) : MVT::i1)) {
9485 // cast from setcc result type to select result type
9487 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
9489 if (N2.getValueType().bitsLT(SCC.getValueType()))
9490 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(),
9493 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
9494 N2.getValueType(), SCC);
9496 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
9497 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
9498 N2.getValueType(), SCC);
9501 AddToWorkList(SCC.getNode());
9502 AddToWorkList(Temp.getNode());
9504 if (N2C->getAPIntValue() == 1)
9507 // shl setcc result by log2 n2c
9508 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
9509 DAG.getConstant(N2C->getAPIntValue().logBase2(),
9510 getShiftAmountTy(Temp.getValueType())));
9514 // Check to see if this is the equivalent of setcc
9515 // FIXME: Turn all of these into setcc if setcc if setcc is legal
9516 // otherwise, go ahead with the folds.
9517 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
9518 EVT XType = N0.getValueType();
9519 if (!LegalOperations ||
9520 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
9521 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
9522 if (Res.getValueType() != VT)
9523 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
9527 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
9528 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
9529 (!LegalOperations ||
9530 TLI.isOperationLegal(ISD::CTLZ, XType))) {
9531 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
9532 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
9533 DAG.getConstant(Log2_32(XType.getSizeInBits()),
9534 getShiftAmountTy(Ctlz.getValueType())));
9536 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
9537 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
9538 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
9539 XType, DAG.getConstant(0, XType), N0);
9540 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
9541 return DAG.getNode(ISD::SRL, DL, XType,
9542 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
9543 DAG.getConstant(XType.getSizeInBits()-1,
9544 getShiftAmountTy(XType)));
9546 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
9547 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
9548 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
9549 DAG.getConstant(XType.getSizeInBits()-1,
9550 getShiftAmountTy(N0.getValueType())));
9551 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
9555 // Check to see if this is an integer abs.
9556 // select_cc setg[te] X, 0, X, -X ->
9557 // select_cc setgt X, -1, X, -X ->
9558 // select_cc setl[te] X, 0, -X, X ->
9559 // select_cc setlt X, 1, -X, X ->
9560 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
9562 ConstantSDNode *SubC = NULL;
9563 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
9564 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
9565 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
9566 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
9567 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
9568 (N1C->isOne() && CC == ISD::SETLT)) &&
9569 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
9570 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
9572 EVT XType = N0.getValueType();
9573 if (SubC && SubC->isNullValue() && XType.isInteger()) {
9574 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
9576 DAG.getConstant(XType.getSizeInBits()-1,
9577 getShiftAmountTy(N0.getValueType())));
9578 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
9580 AddToWorkList(Shift.getNode());
9581 AddToWorkList(Add.getNode());
9582 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
9589 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
9590 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
9591 SDValue N1, ISD::CondCode Cond,
9592 DebugLoc DL, bool foldBooleans) {
9593 TargetLowering::DAGCombinerInfo
9594 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
9595 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
9598 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
9599 /// return a DAG expression to select that will generate the same value by
9600 /// multiplying by a magic number. See:
9601 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
9602 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
9603 std::vector<SDNode*> Built;
9604 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built);
9606 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
9612 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
9613 /// return a DAG expression to select that will generate the same value by
9614 /// multiplying by a magic number. See:
9615 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
9616 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
9617 std::vector<SDNode*> Built;
9618 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built);
9620 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
9626 /// FindBaseOffset - Return true if base is a frame index, which is known not
9627 // to alias with anything but itself. Provides base object and offset as
9629 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
9630 const GlobalValue *&GV, const void *&CV) {
9631 // Assume it is a primitive operation.
9632 Base = Ptr; Offset = 0; GV = 0; CV = 0;
9634 // If it's an adding a simple constant then integrate the offset.
9635 if (Base.getOpcode() == ISD::ADD) {
9636 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
9637 Base = Base.getOperand(0);
9638 Offset += C->getZExtValue();
9642 // Return the underlying GlobalValue, and update the Offset. Return false
9643 // for GlobalAddressSDNode since the same GlobalAddress may be represented
9644 // by multiple nodes with different offsets.
9645 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
9646 GV = G->getGlobal();
9647 Offset += G->getOffset();
9651 // Return the underlying Constant value, and update the Offset. Return false
9652 // for ConstantSDNodes since the same constant pool entry may be represented
9653 // by multiple nodes with different offsets.
9654 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
9655 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
9656 : (const void *)C->getConstVal();
9657 Offset += C->getOffset();
9660 // If it's any of the following then it can't alias with anything but itself.
9661 return isa<FrameIndexSDNode>(Base);
9664 /// isAlias - Return true if there is any possibility that the two addresses
9666 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
9667 const Value *SrcValue1, int SrcValueOffset1,
9668 unsigned SrcValueAlign1,
9669 const MDNode *TBAAInfo1,
9670 SDValue Ptr2, int64_t Size2,
9671 const Value *SrcValue2, int SrcValueOffset2,
9672 unsigned SrcValueAlign2,
9673 const MDNode *TBAAInfo2) const {
9674 // If they are the same then they must be aliases.
9675 if (Ptr1 == Ptr2) return true;
9677 // Gather base node and offset information.
9678 SDValue Base1, Base2;
9679 int64_t Offset1, Offset2;
9680 const GlobalValue *GV1, *GV2;
9681 const void *CV1, *CV2;
9682 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
9683 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
9685 // If they have a same base address then check to see if they overlap.
9686 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
9687 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
9689 // It is possible for different frame indices to alias each other, mostly
9690 // when tail call optimization reuses return address slots for arguments.
9691 // To catch this case, look up the actual index of frame indices to compute
9692 // the real alias relationship.
9693 if (isFrameIndex1 && isFrameIndex2) {
9694 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9695 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
9696 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
9697 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
9700 // Otherwise, if we know what the bases are, and they aren't identical, then
9701 // we know they cannot alias.
9702 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
9705 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
9706 // compared to the size and offset of the access, we may be able to prove they
9707 // do not alias. This check is conservative for now to catch cases created by
9708 // splitting vector types.
9709 if ((SrcValueAlign1 == SrcValueAlign2) &&
9710 (SrcValueOffset1 != SrcValueOffset2) &&
9711 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
9712 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
9713 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
9715 // There is no overlap between these relatively aligned accesses of similar
9716 // size, return no alias.
9717 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
9721 if (CombinerGlobalAA) {
9722 // Use alias analysis information.
9723 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
9724 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
9725 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
9726 AliasAnalysis::AliasResult AAResult =
9727 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
9728 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
9729 if (AAResult == AliasAnalysis::NoAlias)
9733 // Otherwise we have to assume they alias.
9737 bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) {
9739 int64_t Size0, Size1;
9740 const Value *SrcValue0, *SrcValue1;
9741 int SrcValueOffset0, SrcValueOffset1;
9742 unsigned SrcValueAlign0, SrcValueAlign1;
9743 const MDNode *SrcTBAAInfo0, *SrcTBAAInfo1;
9744 FindAliasInfo(Op0, Ptr0, Size0, SrcValue0, SrcValueOffset0,
9745 SrcValueAlign0, SrcTBAAInfo0);
9746 FindAliasInfo(Op1, Ptr1, Size1, SrcValue1, SrcValueOffset1,
9747 SrcValueAlign1, SrcTBAAInfo1);
9748 return isAlias(Ptr0, Size0, SrcValue0, SrcValueOffset0,
9749 SrcValueAlign0, SrcTBAAInfo0,
9750 Ptr1, Size1, SrcValue1, SrcValueOffset1,
9751 SrcValueAlign1, SrcTBAAInfo1);
9754 /// FindAliasInfo - Extracts the relevant alias information from the memory
9755 /// node. Returns true if the operand was a load.
9756 bool DAGCombiner::FindAliasInfo(SDNode *N,
9757 SDValue &Ptr, int64_t &Size,
9758 const Value *&SrcValue,
9759 int &SrcValueOffset,
9760 unsigned &SrcValueAlign,
9761 const MDNode *&TBAAInfo) const {
9762 LSBaseSDNode *LS = cast<LSBaseSDNode>(N);
9764 Ptr = LS->getBasePtr();
9765 Size = LS->getMemoryVT().getSizeInBits() >> 3;
9766 SrcValue = LS->getSrcValue();
9767 SrcValueOffset = LS->getSrcValueOffset();
9768 SrcValueAlign = LS->getOriginalAlignment();
9769 TBAAInfo = LS->getTBAAInfo();
9770 return isa<LoadSDNode>(LS);
9773 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
9774 /// looking for aliasing nodes and adding them to the Aliases vector.
9775 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
9776 SmallVector<SDValue, 8> &Aliases) {
9777 SmallVector<SDValue, 8> Chains; // List of chains to visit.
9778 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
9780 // Get alias information for node.
9783 const Value *SrcValue;
9785 unsigned SrcValueAlign;
9786 const MDNode *SrcTBAAInfo;
9787 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
9788 SrcValueAlign, SrcTBAAInfo);
9791 Chains.push_back(OriginalChain);
9794 // Look at each chain and determine if it is an alias. If so, add it to the
9795 // aliases list. If not, then continue up the chain looking for the next
9797 while (!Chains.empty()) {
9798 SDValue Chain = Chains.back();
9801 // For TokenFactor nodes, look at each operand and only continue up the
9802 // chain until we find two aliases. If we've seen two aliases, assume we'll
9803 // find more and revert to original chain since the xform is unlikely to be
9806 // FIXME: The depth check could be made to return the last non-aliasing
9807 // chain we found before we hit a tokenfactor rather than the original
9809 if (Depth > 6 || Aliases.size() == 2) {
9811 Aliases.push_back(OriginalChain);
9815 // Don't bother if we've been before.
9816 if (!Visited.insert(Chain.getNode()))
9819 switch (Chain.getOpcode()) {
9820 case ISD::EntryToken:
9821 // Entry token is ideal chain operand, but handled in FindBetterChain.
9826 // Get alias information for Chain.
9829 const Value *OpSrcValue;
9830 int OpSrcValueOffset;
9831 unsigned OpSrcValueAlign;
9832 const MDNode *OpSrcTBAAInfo;
9833 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
9834 OpSrcValue, OpSrcValueOffset,
9838 // If chain is alias then stop here.
9839 if (!(IsLoad && IsOpLoad) &&
9840 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
9842 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
9843 OpSrcValueAlign, OpSrcTBAAInfo)) {
9844 Aliases.push_back(Chain);
9846 // Look further up the chain.
9847 Chains.push_back(Chain.getOperand(0));
9853 case ISD::TokenFactor:
9854 // We have to check each of the operands of the token factor for "small"
9855 // token factors, so we queue them up. Adding the operands to the queue
9856 // (stack) in reverse order maintains the original order and increases the
9857 // likelihood that getNode will find a matching token factor (CSE.)
9858 if (Chain.getNumOperands() > 16) {
9859 Aliases.push_back(Chain);
9862 for (unsigned n = Chain.getNumOperands(); n;)
9863 Chains.push_back(Chain.getOperand(--n));
9868 // For all other instructions we will just have to take what we can get.
9869 Aliases.push_back(Chain);
9875 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
9876 /// for a better chain (aliasing node.)
9877 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
9878 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
9880 // Accumulate all the aliases to this node.
9881 GatherAllAliases(N, OldChain, Aliases);
9883 // If no operands then chain to entry token.
9884 if (Aliases.size() == 0)
9885 return DAG.getEntryNode();
9887 // If a single operand then chain to it. We don't need to revisit it.
9888 if (Aliases.size() == 1)
9891 // Construct a custom tailored token factor.
9892 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
9893 &Aliases[0], Aliases.size());
9896 // SelectionDAG::Combine - This is the entry point for the file.
9898 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
9899 CodeGenOpt::Level OptLevel) {
9900 /// run - This is the main entry point to this class.
9902 DAGCombiner(*this, AA, OptLevel).Run(Level);