1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/SmallPtrSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
43 STATISTIC(NodesCombined , "Number of dag nodes combined");
44 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
45 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
46 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
50 CombinerAA("combiner-alias-analysis", cl::Hidden,
51 cl::desc("Turn on alias analysis during testing"));
54 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
55 cl::desc("Include global information in alias analysis"));
57 //------------------------------ DAGCombiner ---------------------------------//
59 class VISIBILITY_HIDDEN DAGCombiner {
61 const TargetLowering &TLI;
63 CodeGenOpt::Level OptLevel;
67 // Worklist of all of the nodes that need to be simplified.
68 std::vector<SDNode*> WorkList;
70 // AA - Used for DAG load/store alias analysis.
73 /// AddUsersToWorkList - When an instruction is simplified, add all users of
74 /// the instruction to the work lists because they might get more simplified
77 void AddUsersToWorkList(SDNode *N) {
78 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
83 /// visit - call the node-specific routine that knows how to fold each
84 /// particular type of node.
85 SDValue visit(SDNode *N);
88 /// AddToWorkList - Add to the work list making sure it's instance is at the
89 /// the back (next to be processed.)
90 void AddToWorkList(SDNode *N) {
91 removeFromWorkList(N);
92 WorkList.push_back(N);
95 /// removeFromWorkList - remove all instances of N from the worklist.
97 void removeFromWorkList(SDNode *N) {
98 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
102 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
105 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
106 return CombineTo(N, &Res, 1, AddTo);
109 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
111 SDValue To[] = { Res0, Res1 };
112 return CombineTo(N, To, 2, AddTo);
115 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
119 /// SimplifyDemandedBits - Check the specified integer node value to see if
120 /// it can be simplified or if things it uses can be simplified by bit
121 /// propagation. If so, return true.
122 bool SimplifyDemandedBits(SDValue Op) {
123 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits());
124 return SimplifyDemandedBits(Op, Demanded);
127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
129 bool CombineToPreIndexedLoadStore(SDNode *N);
130 bool CombineToPostIndexedLoadStore(SDNode *N);
133 /// combine - call the node-specific routine that knows how to fold each
134 /// particular type of node. If that doesn't do anything, try the
135 /// target-specific DAG combines.
136 SDValue combine(SDNode *N);
138 // Visitation implementation - Implement dag node combining for different
139 // node types. The semantics are as follows:
141 // SDValue.getNode() == 0 - No change was made
142 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
143 // otherwise - N should be replaced by the returned Operand.
145 SDValue visitTokenFactor(SDNode *N);
146 SDValue visitMERGE_VALUES(SDNode *N);
147 SDValue visitADD(SDNode *N);
148 SDValue visitSUB(SDNode *N);
149 SDValue visitADDC(SDNode *N);
150 SDValue visitADDE(SDNode *N);
151 SDValue visitMUL(SDNode *N);
152 SDValue visitSDIV(SDNode *N);
153 SDValue visitUDIV(SDNode *N);
154 SDValue visitSREM(SDNode *N);
155 SDValue visitUREM(SDNode *N);
156 SDValue visitMULHU(SDNode *N);
157 SDValue visitMULHS(SDNode *N);
158 SDValue visitSMUL_LOHI(SDNode *N);
159 SDValue visitUMUL_LOHI(SDNode *N);
160 SDValue visitSDIVREM(SDNode *N);
161 SDValue visitUDIVREM(SDNode *N);
162 SDValue visitAND(SDNode *N);
163 SDValue visitOR(SDNode *N);
164 SDValue visitXOR(SDNode *N);
165 SDValue SimplifyVBinOp(SDNode *N);
166 SDValue visitSHL(SDNode *N);
167 SDValue visitSRA(SDNode *N);
168 SDValue visitSRL(SDNode *N);
169 SDValue visitCTLZ(SDNode *N);
170 SDValue visitCTTZ(SDNode *N);
171 SDValue visitCTPOP(SDNode *N);
172 SDValue visitSELECT(SDNode *N);
173 SDValue visitSELECT_CC(SDNode *N);
174 SDValue visitSETCC(SDNode *N);
175 SDValue visitSIGN_EXTEND(SDNode *N);
176 SDValue visitZERO_EXTEND(SDNode *N);
177 SDValue visitANY_EXTEND(SDNode *N);
178 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
179 SDValue visitTRUNCATE(SDNode *N);
180 SDValue visitBIT_CONVERT(SDNode *N);
181 SDValue visitBUILD_PAIR(SDNode *N);
182 SDValue visitFADD(SDNode *N);
183 SDValue visitFSUB(SDNode *N);
184 SDValue visitFMUL(SDNode *N);
185 SDValue visitFDIV(SDNode *N);
186 SDValue visitFREM(SDNode *N);
187 SDValue visitFCOPYSIGN(SDNode *N);
188 SDValue visitSINT_TO_FP(SDNode *N);
189 SDValue visitUINT_TO_FP(SDNode *N);
190 SDValue visitFP_TO_SINT(SDNode *N);
191 SDValue visitFP_TO_UINT(SDNode *N);
192 SDValue visitFP_ROUND(SDNode *N);
193 SDValue visitFP_ROUND_INREG(SDNode *N);
194 SDValue visitFP_EXTEND(SDNode *N);
195 SDValue visitFNEG(SDNode *N);
196 SDValue visitFABS(SDNode *N);
197 SDValue visitBRCOND(SDNode *N);
198 SDValue visitBR_CC(SDNode *N);
199 SDValue visitLOAD(SDNode *N);
200 SDValue visitSTORE(SDNode *N);
201 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
202 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
203 SDValue visitBUILD_VECTOR(SDNode *N);
204 SDValue visitCONCAT_VECTORS(SDNode *N);
205 SDValue visitVECTOR_SHUFFLE(SDNode *N);
207 SDValue XformToShuffleWithZero(SDNode *N);
208 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
210 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
212 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
213 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
214 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
215 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
216 SDValue N3, ISD::CondCode CC,
217 bool NotExtCompare = false);
218 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
219 DebugLoc DL, bool foldBooleans = true);
220 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
222 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
223 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT);
224 SDValue BuildSDIV(SDNode *N);
225 SDValue BuildUDIV(SDNode *N);
226 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
227 SDValue ReduceLoadWidth(SDNode *N);
228 SDValue ReduceLoadOpStoreWidth(SDNode *N);
230 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
232 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
233 /// looking for aliasing nodes and adding them to the Aliases vector.
234 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
235 SmallVector<SDValue, 8> &Aliases);
237 /// isAlias - Return true if there is any possibility that the two addresses
239 bool isAlias(SDValue Ptr1, int64_t Size1,
240 const Value *SrcValue1, int SrcValueOffset1,
241 SDValue Ptr2, int64_t Size2,
242 const Value *SrcValue2, int SrcValueOffset2) const;
244 /// FindAliasInfo - Extracts the relevant alias information from the memory
245 /// node. Returns true if the operand was a load.
246 bool FindAliasInfo(SDNode *N,
247 SDValue &Ptr, int64_t &Size,
248 const Value *&SrcValue, int &SrcValueOffset) const;
250 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
251 /// looking for a better chain (aliasing node.)
252 SDValue FindBetterChain(SDNode *N, SDValue Chain);
254 /// getShiftAmountTy - Returns a type large enough to hold any valid
255 /// shift amount - before type legalization these can be huge.
256 EVT getShiftAmountTy() {
257 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
261 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
263 TLI(D.getTargetLoweringInfo()),
266 LegalOperations(false),
270 /// Run - runs the dag combiner on all nodes in the work list
271 void Run(CombineLevel AtLevel);
277 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
278 /// nodes from the worklist.
279 class VISIBILITY_HIDDEN WorkListRemover :
280 public SelectionDAG::DAGUpdateListener {
283 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
285 virtual void NodeDeleted(SDNode *N, SDNode *E) {
286 DC.removeFromWorkList(N);
289 virtual void NodeUpdated(SDNode *N) {
295 //===----------------------------------------------------------------------===//
296 // TargetLowering::DAGCombinerInfo implementation
297 //===----------------------------------------------------------------------===//
299 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
300 ((DAGCombiner*)DC)->AddToWorkList(N);
303 SDValue TargetLowering::DAGCombinerInfo::
304 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
305 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
308 SDValue TargetLowering::DAGCombinerInfo::
309 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
310 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
314 SDValue TargetLowering::DAGCombinerInfo::
315 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
316 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
319 void TargetLowering::DAGCombinerInfo::
320 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
321 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
324 //===----------------------------------------------------------------------===//
326 //===----------------------------------------------------------------------===//
328 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
329 /// specified expression for the same cost as the expression itself, or 2 if we
330 /// can compute the negated form more cheaply than the expression itself.
331 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
332 unsigned Depth = 0) {
333 // No compile time optimizations on this type.
334 if (Op.getValueType() == MVT::ppcf128)
337 // fneg is removable even if it has multiple uses.
338 if (Op.getOpcode() == ISD::FNEG) return 2;
340 // Don't allow anything with multiple uses.
341 if (!Op.hasOneUse()) return 0;
343 // Don't recurse exponentially.
344 if (Depth > 6) return 0;
346 switch (Op.getOpcode()) {
347 default: return false;
348 case ISD::ConstantFP:
349 // Don't invert constant FP values after legalize. The negated constant
350 // isn't necessarily legal.
351 return LegalOperations ? 0 : 1;
353 // FIXME: determine better conditions for this xform.
354 if (!UnsafeFPMath) return 0;
356 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
357 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
359 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
360 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
362 // We can't turn -(A-B) into B-A when we honor signed zeros.
363 if (!UnsafeFPMath) return 0;
365 // fold (fneg (fsub A, B)) -> (fsub B, A)
370 if (HonorSignDependentRoundingFPMath()) return 0;
372 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
373 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
376 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
381 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
385 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
386 /// returns the newly negated expression.
387 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
388 bool LegalOperations, unsigned Depth = 0) {
389 // fneg is removable even if it has multiple uses.
390 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
392 // Don't allow anything with multiple uses.
393 assert(Op.hasOneUse() && "Unknown reuse!");
395 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
396 switch (Op.getOpcode()) {
397 default: llvm_unreachable("Unknown code");
398 case ISD::ConstantFP: {
399 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
401 return DAG.getConstantFP(V, Op.getValueType());
404 // FIXME: determine better conditions for this xform.
405 assert(UnsafeFPMath);
407 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
408 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
409 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
410 GetNegatedExpression(Op.getOperand(0), DAG,
411 LegalOperations, Depth+1),
413 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
414 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
415 GetNegatedExpression(Op.getOperand(1), DAG,
416 LegalOperations, Depth+1),
419 // We can't turn -(A-B) into B-A when we honor signed zeros.
420 assert(UnsafeFPMath);
422 // fold (fneg (fsub 0, B)) -> B
423 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
424 if (N0CFP->getValueAPF().isZero())
425 return Op.getOperand(1);
427 // fold (fneg (fsub A, B)) -> (fsub B, A)
428 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
429 Op.getOperand(1), Op.getOperand(0));
433 assert(!HonorSignDependentRoundingFPMath());
435 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
436 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
437 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
438 GetNegatedExpression(Op.getOperand(0), DAG,
439 LegalOperations, Depth+1),
442 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
443 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
445 GetNegatedExpression(Op.getOperand(1), DAG,
446 LegalOperations, Depth+1));
450 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
451 GetNegatedExpression(Op.getOperand(0), DAG,
452 LegalOperations, Depth+1));
454 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
455 GetNegatedExpression(Op.getOperand(0), DAG,
456 LegalOperations, Depth+1),
462 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
463 // that selects between the values 1 and 0, making it equivalent to a setcc.
464 // Also, set the incoming LHS, RHS, and CC references to the appropriate
465 // nodes based on the type of node we are checking. This simplifies life a
466 // bit for the callers.
467 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
469 if (N.getOpcode() == ISD::SETCC) {
470 LHS = N.getOperand(0);
471 RHS = N.getOperand(1);
472 CC = N.getOperand(2);
475 if (N.getOpcode() == ISD::SELECT_CC &&
476 N.getOperand(2).getOpcode() == ISD::Constant &&
477 N.getOperand(3).getOpcode() == ISD::Constant &&
478 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
479 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
480 LHS = N.getOperand(0);
481 RHS = N.getOperand(1);
482 CC = N.getOperand(4);
488 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
489 // one use. If this is true, it allows the users to invert the operation for
490 // free when it is profitable to do so.
491 static bool isOneUseSetCC(SDValue N) {
493 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
498 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
499 SDValue N0, SDValue N1) {
500 EVT VT = N0.getValueType();
501 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
502 if (isa<ConstantSDNode>(N1)) {
503 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
505 DAG.FoldConstantArithmetic(Opc, VT,
506 cast<ConstantSDNode>(N0.getOperand(1)),
507 cast<ConstantSDNode>(N1));
508 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
509 } else if (N0.hasOneUse()) {
510 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
511 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
512 N0.getOperand(0), N1);
513 AddToWorkList(OpNode.getNode());
514 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
518 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
519 if (isa<ConstantSDNode>(N0)) {
520 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
522 DAG.FoldConstantArithmetic(Opc, VT,
523 cast<ConstantSDNode>(N1.getOperand(1)),
524 cast<ConstantSDNode>(N0));
525 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
526 } else if (N1.hasOneUse()) {
527 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
528 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
529 N1.getOperand(0), N0);
530 AddToWorkList(OpNode.getNode());
531 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
538 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
540 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
542 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
543 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG));
544 DOUT << " and " << NumTo-1 << " other values\n";
545 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i)
546 assert(N->getValueType(i) == To[i].getValueType() &&
547 "Cannot combine value to value of different type!"));
548 WorkListRemover DeadNodes(*this);
549 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
552 // Push the new nodes and any users onto the worklist
553 for (unsigned i = 0, e = NumTo; i != e; ++i) {
554 if (To[i].getNode()) {
555 AddToWorkList(To[i].getNode());
556 AddUsersToWorkList(To[i].getNode());
561 // Finally, if the node is now dead, remove it from the graph. The node
562 // may not be dead if the replacement process recursively simplified to
563 // something else needing this node.
564 if (N->use_empty()) {
565 // Nodes can be reintroduced into the worklist. Make sure we do not
566 // process a node that has been replaced.
567 removeFromWorkList(N);
569 // Finally, since the node is now dead, remove it from the graph.
572 return SDValue(N, 0);
576 DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &
578 // Replace all uses. If any nodes become isomorphic to other nodes and
579 // are deleted, make sure to remove them from our worklist.
580 WorkListRemover DeadNodes(*this);
581 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
583 // Push the new node and any (possibly new) users onto the worklist.
584 AddToWorkList(TLO.New.getNode());
585 AddUsersToWorkList(TLO.New.getNode());
587 // Finally, if the node is now dead, remove it from the graph. The node
588 // may not be dead if the replacement process recursively simplified to
589 // something else needing this node.
590 if (TLO.Old.getNode()->use_empty()) {
591 removeFromWorkList(TLO.Old.getNode());
593 // If the operands of this node are only used by the node, they will now
594 // be dead. Make sure to visit them first to delete dead nodes early.
595 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
596 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
597 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
599 DAG.DeleteNode(TLO.Old.getNode());
603 /// SimplifyDemandedBits - Check the specified integer node value to see if
604 /// it can be simplified or if things it uses can be simplified by bit
605 /// propagation. If so, return true.
606 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
607 TargetLowering::TargetLoweringOpt TLO(DAG);
608 APInt KnownZero, KnownOne;
609 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
613 AddToWorkList(Op.getNode());
615 // Replace the old value with the new one.
617 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
618 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
621 CommitTargetLoweringOpt(TLO);
625 //===----------------------------------------------------------------------===//
626 // Main DAG Combiner implementation
627 //===----------------------------------------------------------------------===//
629 void DAGCombiner::Run(CombineLevel AtLevel) {
630 // set the instance variables, so that the various visit routines may use it.
632 LegalOperations = Level >= NoIllegalOperations;
633 LegalTypes = Level >= NoIllegalTypes;
635 // Add all the dag nodes to the worklist.
636 WorkList.reserve(DAG.allnodes_size());
637 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
638 E = DAG.allnodes_end(); I != E; ++I)
639 WorkList.push_back(I);
641 // Create a dummy node (which is not added to allnodes), that adds a reference
642 // to the root node, preventing it from being deleted, and tracking any
643 // changes of the root.
644 HandleSDNode Dummy(DAG.getRoot());
646 // The root of the dag may dangle to deleted nodes until the dag combiner is
647 // done. Set it to null to avoid confusion.
648 DAG.setRoot(SDValue());
650 // while the worklist isn't empty, inspect the node on the end of it and
651 // try and combine it.
652 while (!WorkList.empty()) {
653 SDNode *N = WorkList.back();
656 // If N has no uses, it is dead. Make sure to revisit all N's operands once
657 // N is deleted from the DAG, since they too may now be dead or may have a
658 // reduced number of uses, allowing other xforms.
659 if (N->use_empty() && N != &Dummy) {
660 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
661 AddToWorkList(N->getOperand(i).getNode());
667 SDValue RV = combine(N);
669 if (RV.getNode() == 0)
674 // If we get back the same node we passed in, rather than a new node or
675 // zero, we know that the node must have defined multiple values and
676 // CombineTo was used. Since CombineTo takes care of the worklist
677 // mechanics for us, we have no work to do in this case.
678 if (RV.getNode() == N)
681 assert(N->getOpcode() != ISD::DELETED_NODE &&
682 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
683 "Node was deleted but visit returned new node!");
685 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
686 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG));
688 WorkListRemover DeadNodes(*this);
689 if (N->getNumValues() == RV.getNode()->getNumValues())
690 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
692 assert(N->getValueType(0) == RV.getValueType() &&
693 N->getNumValues() == 1 && "Type mismatch");
695 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
698 // Push the new node and any users onto the worklist
699 AddToWorkList(RV.getNode());
700 AddUsersToWorkList(RV.getNode());
702 // Add any uses of the old node to the worklist in case this node is the
703 // last one that uses them. They may become dead after this node is
705 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
706 AddToWorkList(N->getOperand(i).getNode());
708 // Finally, if the node is now dead, remove it from the graph. The node
709 // may not be dead if the replacement process recursively simplified to
710 // something else needing this node.
711 if (N->use_empty()) {
712 // Nodes can be reintroduced into the worklist. Make sure we do not
713 // process a node that has been replaced.
714 removeFromWorkList(N);
716 // Finally, since the node is now dead, remove it from the graph.
721 // If the root changed (e.g. it was a dead load, update the root).
722 DAG.setRoot(Dummy.getValue());
725 SDValue DAGCombiner::visit(SDNode *N) {
726 switch(N->getOpcode()) {
728 case ISD::TokenFactor: return visitTokenFactor(N);
729 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
730 case ISD::ADD: return visitADD(N);
731 case ISD::SUB: return visitSUB(N);
732 case ISD::ADDC: return visitADDC(N);
733 case ISD::ADDE: return visitADDE(N);
734 case ISD::MUL: return visitMUL(N);
735 case ISD::SDIV: return visitSDIV(N);
736 case ISD::UDIV: return visitUDIV(N);
737 case ISD::SREM: return visitSREM(N);
738 case ISD::UREM: return visitUREM(N);
739 case ISD::MULHU: return visitMULHU(N);
740 case ISD::MULHS: return visitMULHS(N);
741 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
742 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
743 case ISD::SDIVREM: return visitSDIVREM(N);
744 case ISD::UDIVREM: return visitUDIVREM(N);
745 case ISD::AND: return visitAND(N);
746 case ISD::OR: return visitOR(N);
747 case ISD::XOR: return visitXOR(N);
748 case ISD::SHL: return visitSHL(N);
749 case ISD::SRA: return visitSRA(N);
750 case ISD::SRL: return visitSRL(N);
751 case ISD::CTLZ: return visitCTLZ(N);
752 case ISD::CTTZ: return visitCTTZ(N);
753 case ISD::CTPOP: return visitCTPOP(N);
754 case ISD::SELECT: return visitSELECT(N);
755 case ISD::SELECT_CC: return visitSELECT_CC(N);
756 case ISD::SETCC: return visitSETCC(N);
757 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
758 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
759 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
760 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
761 case ISD::TRUNCATE: return visitTRUNCATE(N);
762 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
763 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
764 case ISD::FADD: return visitFADD(N);
765 case ISD::FSUB: return visitFSUB(N);
766 case ISD::FMUL: return visitFMUL(N);
767 case ISD::FDIV: return visitFDIV(N);
768 case ISD::FREM: return visitFREM(N);
769 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
770 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
771 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
772 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
773 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
774 case ISD::FP_ROUND: return visitFP_ROUND(N);
775 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
776 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
777 case ISD::FNEG: return visitFNEG(N);
778 case ISD::FABS: return visitFABS(N);
779 case ISD::BRCOND: return visitBRCOND(N);
780 case ISD::BR_CC: return visitBR_CC(N);
781 case ISD::LOAD: return visitLOAD(N);
782 case ISD::STORE: return visitSTORE(N);
783 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
784 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
785 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
786 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
787 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
792 SDValue DAGCombiner::combine(SDNode *N) {
793 SDValue RV = visit(N);
795 // If nothing happened, try a target-specific DAG combine.
796 if (RV.getNode() == 0) {
797 assert(N->getOpcode() != ISD::DELETED_NODE &&
798 "Node was deleted but visit returned NULL!");
800 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
801 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
803 // Expose the DAG combiner to the target combiner impls.
804 TargetLowering::DAGCombinerInfo
805 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
807 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
811 // If N is a commutative binary node, try commuting it to enable more
813 if (RV.getNode() == 0 &&
814 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
815 N->getNumValues() == 1) {
816 SDValue N0 = N->getOperand(0);
817 SDValue N1 = N->getOperand(1);
819 // Constant operands are canonicalized to RHS.
820 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
821 SDValue Ops[] = { N1, N0 };
822 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
825 return SDValue(CSENode, 0);
832 /// getInputChainForNode - Given a node, return its input chain if it has one,
833 /// otherwise return a null sd operand.
834 static SDValue getInputChainForNode(SDNode *N) {
835 if (unsigned NumOps = N->getNumOperands()) {
836 if (N->getOperand(0).getValueType() == MVT::Other)
837 return N->getOperand(0);
838 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
839 return N->getOperand(NumOps-1);
840 for (unsigned i = 1; i < NumOps-1; ++i)
841 if (N->getOperand(i).getValueType() == MVT::Other)
842 return N->getOperand(i);
847 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
848 // If N has two operands, where one has an input chain equal to the other,
849 // the 'other' chain is redundant.
850 if (N->getNumOperands() == 2) {
851 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
852 return N->getOperand(0);
853 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
854 return N->getOperand(1);
857 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
858 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
859 SmallPtrSet<SDNode*, 16> SeenOps;
860 bool Changed = false; // If we should replace this token factor.
862 // Start out with this token factor.
865 // Iterate through token factors. The TFs grows when new token factors are
867 for (unsigned i = 0; i < TFs.size(); ++i) {
870 // Check each of the operands.
871 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
872 SDValue Op = TF->getOperand(i);
874 switch (Op.getOpcode()) {
875 case ISD::EntryToken:
876 // Entry tokens don't need to be added to the list. They are
881 case ISD::TokenFactor:
882 if ((CombinerAA || Op.hasOneUse()) &&
883 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
884 // Queue up for processing.
885 TFs.push_back(Op.getNode());
886 // Clean up in case the token factor is removed.
887 AddToWorkList(Op.getNode());
894 // Only add if it isn't already in the list.
895 if (SeenOps.insert(Op.getNode()))
906 // If we've change things around then replace token factor.
909 // The entry token is the only possible outcome.
910 Result = DAG.getEntryNode();
912 // New and improved token factor.
913 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
914 MVT::Other, &Ops[0], Ops.size());
917 // Don't add users to work list.
918 return CombineTo(N, Result, false);
924 /// MERGE_VALUES can always be eliminated.
925 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
926 WorkListRemover DeadNodes(*this);
927 // Replacing results may cause a different MERGE_VALUES to suddenly
928 // be CSE'd with N, and carry its uses with it. Iterate until no
929 // uses remain, to ensure that the node can be safely deleted.
931 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
932 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
934 } while (!N->use_empty());
935 removeFromWorkList(N);
937 return SDValue(N, 0); // Return N so it doesn't get rechecked!
941 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
943 EVT VT = N0.getValueType();
944 SDValue N00 = N0.getOperand(0);
945 SDValue N01 = N0.getOperand(1);
946 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
948 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
949 isa<ConstantSDNode>(N00.getOperand(1))) {
950 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
951 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
952 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
953 N00.getOperand(0), N01),
954 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
955 N00.getOperand(1), N01));
956 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
962 SDValue DAGCombiner::visitADD(SDNode *N) {
963 SDValue N0 = N->getOperand(0);
964 SDValue N1 = N->getOperand(1);
965 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
966 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
967 EVT VT = N0.getValueType();
971 SDValue FoldedVOp = SimplifyVBinOp(N);
972 if (FoldedVOp.getNode()) return FoldedVOp;
975 // fold (add x, undef) -> undef
976 if (N0.getOpcode() == ISD::UNDEF)
978 if (N1.getOpcode() == ISD::UNDEF)
980 // fold (add c1, c2) -> c1+c2
982 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
983 // canonicalize constant to RHS
985 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
986 // fold (add x, 0) -> x
987 if (N1C && N1C->isNullValue())
989 // fold (add Sym, c) -> Sym+c
990 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
991 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
992 GA->getOpcode() == ISD::GlobalAddress)
993 return DAG.getGlobalAddress(GA->getGlobal(), VT,
995 (uint64_t)N1C->getSExtValue());
996 // fold ((c1-A)+c2) -> (c1+c2)-A
997 if (N1C && N0.getOpcode() == ISD::SUB)
998 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
999 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1000 DAG.getConstant(N1C->getAPIntValue()+
1001 N0C->getAPIntValue(), VT),
1004 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1005 if (RADD.getNode() != 0)
1007 // fold ((0-A) + B) -> B-A
1008 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1009 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1010 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1011 // fold (A + (0-B)) -> A-B
1012 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1013 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1014 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1015 // fold (A+(B-A)) -> B
1016 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1017 return N1.getOperand(0);
1018 // fold ((B-A)+A) -> B
1019 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1020 return N0.getOperand(0);
1021 // fold (A+(B-(A+C))) to (B-C)
1022 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1023 N0 == N1.getOperand(1).getOperand(0))
1024 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1025 N1.getOperand(1).getOperand(1));
1026 // fold (A+(B-(C+A))) to (B-C)
1027 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1028 N0 == N1.getOperand(1).getOperand(1))
1029 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1030 N1.getOperand(1).getOperand(0));
1031 // fold (A+((B-A)+or-C)) to (B+or-C)
1032 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1033 N1.getOperand(0).getOpcode() == ISD::SUB &&
1034 N0 == N1.getOperand(0).getOperand(1))
1035 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1036 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1038 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1039 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1040 SDValue N00 = N0.getOperand(0);
1041 SDValue N01 = N0.getOperand(1);
1042 SDValue N10 = N1.getOperand(0);
1043 SDValue N11 = N1.getOperand(1);
1045 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1046 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1047 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1048 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1051 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1052 return SDValue(N, 0);
1054 // fold (a+b) -> (a|b) iff a and b share no bits.
1055 if (VT.isInteger() && !VT.isVector()) {
1056 APInt LHSZero, LHSOne;
1057 APInt RHSZero, RHSOne;
1058 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1059 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1061 if (LHSZero.getBoolValue()) {
1062 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1064 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1065 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1066 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1067 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1068 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1072 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1073 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1074 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1075 if (Result.getNode()) return Result;
1077 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1078 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1079 if (Result.getNode()) return Result;
1085 SDValue DAGCombiner::visitADDC(SDNode *N) {
1086 SDValue N0 = N->getOperand(0);
1087 SDValue N1 = N->getOperand(1);
1088 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1089 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1090 EVT VT = N0.getValueType();
1092 // If the flag result is dead, turn this into an ADD.
1093 if (N->hasNUsesOfValue(0, 1))
1094 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1095 DAG.getNode(ISD::CARRY_FALSE,
1096 N->getDebugLoc(), MVT::Flag));
1098 // canonicalize constant to RHS.
1100 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1102 // fold (addc x, 0) -> x + no carry out
1103 if (N1C && N1C->isNullValue())
1104 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1105 N->getDebugLoc(), MVT::Flag));
1107 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1108 APInt LHSZero, LHSOne;
1109 APInt RHSZero, RHSOne;
1110 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1111 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1113 if (LHSZero.getBoolValue()) {
1114 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1116 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1117 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1118 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1119 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1120 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1121 DAG.getNode(ISD::CARRY_FALSE,
1122 N->getDebugLoc(), MVT::Flag));
1128 SDValue DAGCombiner::visitADDE(SDNode *N) {
1129 SDValue N0 = N->getOperand(0);
1130 SDValue N1 = N->getOperand(1);
1131 SDValue CarryIn = N->getOperand(2);
1132 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1133 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1135 // canonicalize constant to RHS
1137 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1140 // fold (adde x, y, false) -> (addc x, y)
1141 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1142 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1147 SDValue DAGCombiner::visitSUB(SDNode *N) {
1148 SDValue N0 = N->getOperand(0);
1149 SDValue N1 = N->getOperand(1);
1150 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1151 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1152 EVT VT = N0.getValueType();
1155 if (VT.isVector()) {
1156 SDValue FoldedVOp = SimplifyVBinOp(N);
1157 if (FoldedVOp.getNode()) return FoldedVOp;
1160 // fold (sub x, x) -> 0
1162 return DAG.getConstant(0, N->getValueType(0));
1163 // fold (sub c1, c2) -> c1-c2
1165 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1166 // fold (sub x, c) -> (add x, -c)
1168 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1169 DAG.getConstant(-N1C->getAPIntValue(), VT));
1170 // fold (A+B)-A -> B
1171 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1172 return N0.getOperand(1);
1173 // fold (A+B)-B -> A
1174 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1175 return N0.getOperand(0);
1176 // fold ((A+(B+or-C))-B) -> A+or-C
1177 if (N0.getOpcode() == ISD::ADD &&
1178 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1179 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1180 N0.getOperand(1).getOperand(0) == N1)
1181 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1182 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1183 // fold ((A+(C+B))-B) -> A+C
1184 if (N0.getOpcode() == ISD::ADD &&
1185 N0.getOperand(1).getOpcode() == ISD::ADD &&
1186 N0.getOperand(1).getOperand(1) == N1)
1187 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1188 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1189 // fold ((A-(B-C))-C) -> A-B
1190 if (N0.getOpcode() == ISD::SUB &&
1191 N0.getOperand(1).getOpcode() == ISD::SUB &&
1192 N0.getOperand(1).getOperand(1) == N1)
1193 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1194 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1196 // If either operand of a sub is undef, the result is undef
1197 if (N0.getOpcode() == ISD::UNDEF)
1199 if (N1.getOpcode() == ISD::UNDEF)
1202 // If the relocation model supports it, consider symbol offsets.
1203 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1204 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1205 // fold (sub Sym, c) -> Sym-c
1206 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1207 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1209 (uint64_t)N1C->getSExtValue());
1210 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1211 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1212 if (GA->getGlobal() == GB->getGlobal())
1213 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1220 SDValue DAGCombiner::visitMUL(SDNode *N) {
1221 SDValue N0 = N->getOperand(0);
1222 SDValue N1 = N->getOperand(1);
1223 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1224 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1225 EVT VT = N0.getValueType();
1228 if (VT.isVector()) {
1229 SDValue FoldedVOp = SimplifyVBinOp(N);
1230 if (FoldedVOp.getNode()) return FoldedVOp;
1233 // fold (mul x, undef) -> 0
1234 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1235 return DAG.getConstant(0, VT);
1236 // fold (mul c1, c2) -> c1*c2
1238 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1239 // canonicalize constant to RHS
1241 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1242 // fold (mul x, 0) -> 0
1243 if (N1C && N1C->isNullValue())
1245 // fold (mul x, -1) -> 0-x
1246 if (N1C && N1C->isAllOnesValue())
1247 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1248 DAG.getConstant(0, VT), N0);
1249 // fold (mul x, (1 << c)) -> x << c
1250 if (N1C && N1C->getAPIntValue().isPowerOf2())
1251 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1252 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1253 getShiftAmountTy()));
1254 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1255 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1256 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1257 // FIXME: If the input is something that is easily negated (e.g. a
1258 // single-use add), we should put the negate there.
1259 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1260 DAG.getConstant(0, VT),
1261 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1262 DAG.getConstant(Log2Val, getShiftAmountTy())));
1264 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1265 if (N1C && N0.getOpcode() == ISD::SHL &&
1266 isa<ConstantSDNode>(N0.getOperand(1))) {
1267 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1268 N1, N0.getOperand(1));
1269 AddToWorkList(C3.getNode());
1270 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1271 N0.getOperand(0), C3);
1274 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1277 SDValue Sh(0,0), Y(0,0);
1278 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1279 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1280 N0.getNode()->hasOneUse()) {
1282 } else if (N1.getOpcode() == ISD::SHL &&
1283 isa<ConstantSDNode>(N1.getOperand(1)) &&
1284 N1.getNode()->hasOneUse()) {
1289 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1290 Sh.getOperand(0), Y);
1291 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1292 Mul, Sh.getOperand(1));
1296 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1297 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1298 isa<ConstantSDNode>(N0.getOperand(1)))
1299 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1300 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1301 N0.getOperand(0), N1),
1302 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1303 N0.getOperand(1), N1));
1306 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1307 if (RMUL.getNode() != 0)
1313 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1314 SDValue N0 = N->getOperand(0);
1315 SDValue N1 = N->getOperand(1);
1316 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1317 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1318 EVT VT = N->getValueType(0);
1321 if (VT.isVector()) {
1322 SDValue FoldedVOp = SimplifyVBinOp(N);
1323 if (FoldedVOp.getNode()) return FoldedVOp;
1326 // fold (sdiv c1, c2) -> c1/c2
1327 if (N0C && N1C && !N1C->isNullValue())
1328 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1329 // fold (sdiv X, 1) -> X
1330 if (N1C && N1C->getSExtValue() == 1LL)
1332 // fold (sdiv X, -1) -> 0-X
1333 if (N1C && N1C->isAllOnesValue())
1334 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1335 DAG.getConstant(0, VT), N0);
1336 // If we know the sign bits of both operands are zero, strength reduce to a
1337 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1338 if (!VT.isVector()) {
1339 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1340 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1343 // fold (sdiv X, pow2) -> simple ops after legalize
1344 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1345 (isPowerOf2_64(N1C->getSExtValue()) ||
1346 isPowerOf2_64(-N1C->getSExtValue()))) {
1347 // If dividing by powers of two is cheap, then don't perform the following
1349 if (TLI.isPow2DivCheap())
1352 int64_t pow2 = N1C->getSExtValue();
1353 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1354 unsigned lg2 = Log2_64(abs2);
1356 // Splat the sign bit into the register
1357 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1358 DAG.getConstant(VT.getSizeInBits()-1,
1359 getShiftAmountTy()));
1360 AddToWorkList(SGN.getNode());
1362 // Add (N0 < 0) ? abs2 - 1 : 0;
1363 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1364 DAG.getConstant(VT.getSizeInBits() - lg2,
1365 getShiftAmountTy()));
1366 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1367 AddToWorkList(SRL.getNode());
1368 AddToWorkList(ADD.getNode()); // Divide by pow2
1369 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1370 DAG.getConstant(lg2, getShiftAmountTy()));
1372 // If we're dividing by a positive value, we're done. Otherwise, we must
1373 // negate the result.
1377 AddToWorkList(SRA.getNode());
1378 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1379 DAG.getConstant(0, VT), SRA);
1382 // if integer divide is expensive and we satisfy the requirements, emit an
1383 // alternate sequence.
1384 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1385 !TLI.isIntDivCheap()) {
1386 SDValue Op = BuildSDIV(N);
1387 if (Op.getNode()) return Op;
1391 if (N0.getOpcode() == ISD::UNDEF)
1392 return DAG.getConstant(0, VT);
1393 // X / undef -> undef
1394 if (N1.getOpcode() == ISD::UNDEF)
1400 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1401 SDValue N0 = N->getOperand(0);
1402 SDValue N1 = N->getOperand(1);
1403 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1404 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1405 EVT VT = N->getValueType(0);
1408 if (VT.isVector()) {
1409 SDValue FoldedVOp = SimplifyVBinOp(N);
1410 if (FoldedVOp.getNode()) return FoldedVOp;
1413 // fold (udiv c1, c2) -> c1/c2
1414 if (N0C && N1C && !N1C->isNullValue())
1415 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1416 // fold (udiv x, (1 << c)) -> x >>u c
1417 if (N1C && N1C->getAPIntValue().isPowerOf2())
1418 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1419 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1420 getShiftAmountTy()));
1421 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1422 if (N1.getOpcode() == ISD::SHL) {
1423 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1424 if (SHC->getAPIntValue().isPowerOf2()) {
1425 EVT ADDVT = N1.getOperand(1).getValueType();
1426 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1428 DAG.getConstant(SHC->getAPIntValue()
1431 AddToWorkList(Add.getNode());
1432 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1436 // fold (udiv x, c) -> alternate
1437 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1438 SDValue Op = BuildUDIV(N);
1439 if (Op.getNode()) return Op;
1443 if (N0.getOpcode() == ISD::UNDEF)
1444 return DAG.getConstant(0, VT);
1445 // X / undef -> undef
1446 if (N1.getOpcode() == ISD::UNDEF)
1452 SDValue DAGCombiner::visitSREM(SDNode *N) {
1453 SDValue N0 = N->getOperand(0);
1454 SDValue N1 = N->getOperand(1);
1455 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1456 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1457 EVT VT = N->getValueType(0);
1459 // fold (srem c1, c2) -> c1%c2
1460 if (N0C && N1C && !N1C->isNullValue())
1461 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1462 // If we know the sign bits of both operands are zero, strength reduce to a
1463 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1464 if (!VT.isVector()) {
1465 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1466 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1469 // If X/C can be simplified by the division-by-constant logic, lower
1470 // X%C to the equivalent of X-X/C*C.
1471 if (N1C && !N1C->isNullValue()) {
1472 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1473 AddToWorkList(Div.getNode());
1474 SDValue OptimizedDiv = combine(Div.getNode());
1475 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1476 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1478 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1479 AddToWorkList(Mul.getNode());
1485 if (N0.getOpcode() == ISD::UNDEF)
1486 return DAG.getConstant(0, VT);
1487 // X % undef -> undef
1488 if (N1.getOpcode() == ISD::UNDEF)
1494 SDValue DAGCombiner::visitUREM(SDNode *N) {
1495 SDValue N0 = N->getOperand(0);
1496 SDValue N1 = N->getOperand(1);
1497 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1498 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1499 EVT VT = N->getValueType(0);
1501 // fold (urem c1, c2) -> c1%c2
1502 if (N0C && N1C && !N1C->isNullValue())
1503 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1504 // fold (urem x, pow2) -> (and x, pow2-1)
1505 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1506 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1507 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1508 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1509 if (N1.getOpcode() == ISD::SHL) {
1510 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1511 if (SHC->getAPIntValue().isPowerOf2()) {
1513 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1514 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1516 AddToWorkList(Add.getNode());
1517 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1522 // If X/C can be simplified by the division-by-constant logic, lower
1523 // X%C to the equivalent of X-X/C*C.
1524 if (N1C && !N1C->isNullValue()) {
1525 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1526 AddToWorkList(Div.getNode());
1527 SDValue OptimizedDiv = combine(Div.getNode());
1528 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1529 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1531 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1532 AddToWorkList(Mul.getNode());
1538 if (N0.getOpcode() == ISD::UNDEF)
1539 return DAG.getConstant(0, VT);
1540 // X % undef -> undef
1541 if (N1.getOpcode() == ISD::UNDEF)
1547 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1548 SDValue N0 = N->getOperand(0);
1549 SDValue N1 = N->getOperand(1);
1550 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1551 EVT VT = N->getValueType(0);
1553 // fold (mulhs x, 0) -> 0
1554 if (N1C && N1C->isNullValue())
1556 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1557 if (N1C && N1C->getAPIntValue() == 1)
1558 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1559 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1560 getShiftAmountTy()));
1561 // fold (mulhs x, undef) -> 0
1562 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1563 return DAG.getConstant(0, VT);
1568 SDValue DAGCombiner::visitMULHU(SDNode *N) {
1569 SDValue N0 = N->getOperand(0);
1570 SDValue N1 = N->getOperand(1);
1571 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1572 EVT VT = N->getValueType(0);
1574 // fold (mulhu x, 0) -> 0
1575 if (N1C && N1C->isNullValue())
1577 // fold (mulhu x, 1) -> 0
1578 if (N1C && N1C->getAPIntValue() == 1)
1579 return DAG.getConstant(0, N0.getValueType());
1580 // fold (mulhu x, undef) -> 0
1581 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1582 return DAG.getConstant(0, VT);
1587 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1588 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1589 /// that are being performed. Return true if a simplification was made.
1591 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1593 // If the high half is not needed, just compute the low half.
1594 bool HiExists = N->hasAnyUseOfValue(1);
1596 (!LegalOperations ||
1597 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1598 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1599 N->op_begin(), N->getNumOperands());
1600 return CombineTo(N, Res, Res);
1603 // If the low half is not needed, just compute the high half.
1604 bool LoExists = N->hasAnyUseOfValue(0);
1606 (!LegalOperations ||
1607 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1608 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1609 N->op_begin(), N->getNumOperands());
1610 return CombineTo(N, Res, Res);
1613 // If both halves are used, return as it is.
1614 if (LoExists && HiExists)
1617 // If the two computed results can be simplified separately, separate them.
1619 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1620 N->op_begin(), N->getNumOperands());
1621 AddToWorkList(Lo.getNode());
1622 SDValue LoOpt = combine(Lo.getNode());
1623 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
1624 (!LegalOperations ||
1625 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
1626 return CombineTo(N, LoOpt, LoOpt);
1630 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1631 N->op_begin(), N->getNumOperands());
1632 AddToWorkList(Hi.getNode());
1633 SDValue HiOpt = combine(Hi.getNode());
1634 if (HiOpt.getNode() && HiOpt != Hi &&
1635 (!LegalOperations ||
1636 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
1637 return CombineTo(N, HiOpt, HiOpt);
1643 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1644 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1645 if (Res.getNode()) return Res;
1650 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1651 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
1652 if (Res.getNode()) return Res;
1657 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
1658 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
1659 if (Res.getNode()) return Res;
1664 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
1665 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
1666 if (Res.getNode()) return Res;
1671 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1672 /// two operands of the same opcode, try to simplify it.
1673 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1674 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1675 EVT VT = N0.getValueType();
1676 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1678 // For each of OP in AND/OR/XOR:
1679 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1680 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1681 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1682 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
1683 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1684 N0.getOpcode() == ISD::SIGN_EXTEND ||
1685 (N0.getOpcode() == ISD::TRUNCATE &&
1686 !TLI.isTruncateFree(N0.getOperand(0).getValueType(), VT))) &&
1687 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() &&
1688 (!LegalOperations ||
1689 TLI.isOperationLegal(N->getOpcode(), N0.getOperand(0).getValueType()))) {
1690 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1691 N0.getOperand(0).getValueType(),
1692 N0.getOperand(0), N1.getOperand(0));
1693 AddToWorkList(ORNode.getNode());
1694 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
1697 // For each of OP in SHL/SRL/SRA/AND...
1698 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1699 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1700 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1701 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1702 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1703 N0.getOperand(1) == N1.getOperand(1)) {
1704 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1705 N0.getOperand(0).getValueType(),
1706 N0.getOperand(0), N1.getOperand(0));
1707 AddToWorkList(ORNode.getNode());
1708 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
1709 ORNode, N0.getOperand(1));
1715 SDValue DAGCombiner::visitAND(SDNode *N) {
1716 SDValue N0 = N->getOperand(0);
1717 SDValue N1 = N->getOperand(1);
1718 SDValue LL, LR, RL, RR, CC0, CC1;
1719 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1720 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1721 EVT VT = N1.getValueType();
1722 unsigned BitWidth = VT.getSizeInBits();
1725 if (VT.isVector()) {
1726 SDValue FoldedVOp = SimplifyVBinOp(N);
1727 if (FoldedVOp.getNode()) return FoldedVOp;
1730 // fold (and x, undef) -> 0
1731 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1732 return DAG.getConstant(0, VT);
1733 // fold (and c1, c2) -> c1&c2
1735 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
1736 // canonicalize constant to RHS
1738 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
1739 // fold (and x, -1) -> x
1740 if (N1C && N1C->isAllOnesValue())
1742 // if (and x, c) is known to be zero, return 0
1743 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
1744 APInt::getAllOnesValue(BitWidth)))
1745 return DAG.getConstant(0, VT);
1747 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
1748 if (RAND.getNode() != 0)
1750 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1751 if (N1C && N0.getOpcode() == ISD::OR)
1752 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1753 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
1755 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1756 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1757 SDValue N0Op0 = N0.getOperand(0);
1758 APInt Mask = ~N1C->getAPIntValue();
1759 Mask.trunc(N0Op0.getValueSizeInBits());
1760 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
1761 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
1762 N0.getValueType(), N0Op0);
1764 // Replace uses of the AND with uses of the Zero extend node.
1767 // We actually want to replace all uses of the any_extend with the
1768 // zero_extend, to avoid duplicating things. This will later cause this
1769 // AND to be folded.
1770 CombineTo(N0.getNode(), Zext);
1771 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1774 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1775 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1776 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1777 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1779 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1780 LL.getValueType().isInteger()) {
1781 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
1782 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
1783 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1784 LR.getValueType(), LL, RL);
1785 AddToWorkList(ORNode.getNode());
1786 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1788 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
1789 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1790 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
1791 LR.getValueType(), LL, RL);
1792 AddToWorkList(ANDNode.getNode());
1793 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
1795 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
1796 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1797 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1798 LR.getValueType(), LL, RL);
1799 AddToWorkList(ORNode.getNode());
1800 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1803 // canonicalize equivalent to ll == rl
1804 if (LL == RR && LR == RL) {
1805 Op1 = ISD::getSetCCSwappedOperands(Op1);
1808 if (LL == RL && LR == RR) {
1809 bool isInteger = LL.getValueType().isInteger();
1810 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1811 if (Result != ISD::SETCC_INVALID &&
1812 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
1813 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
1818 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
1819 if (N0.getOpcode() == N1.getOpcode()) {
1820 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1821 if (Tmp.getNode()) return Tmp;
1824 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1825 // fold (and (sra)) -> (and (srl)) when possible.
1826 if (!VT.isVector() &&
1827 SimplifyDemandedBits(SDValue(N, 0)))
1828 return SDValue(N, 0);
1829 // fold (zext_inreg (extload x)) -> (zextload x)
1830 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
1831 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1832 EVT EVT = LN0->getMemoryVT();
1833 // If we zero all the possible extended bits, then we can turn this into
1834 // a zextload if we are running before legalize or the operation is legal.
1835 unsigned BitWidth = N1.getValueSizeInBits();
1836 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1837 BitWidth - EVT.getSizeInBits())) &&
1838 ((!LegalOperations && !LN0->isVolatile()) ||
1839 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1840 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1841 LN0->getChain(), LN0->getBasePtr(),
1843 LN0->getSrcValueOffset(), EVT,
1844 LN0->isVolatile(), LN0->getAlignment());
1846 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1847 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1850 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1851 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
1853 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1854 EVT EVT = LN0->getMemoryVT();
1855 // If we zero all the possible extended bits, then we can turn this into
1856 // a zextload if we are running before legalize or the operation is legal.
1857 unsigned BitWidth = N1.getValueSizeInBits();
1858 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1859 BitWidth - EVT.getSizeInBits())) &&
1860 ((!LegalOperations && !LN0->isVolatile()) ||
1861 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1862 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1864 LN0->getBasePtr(), LN0->getSrcValue(),
1865 LN0->getSrcValueOffset(), EVT,
1866 LN0->isVolatile(), LN0->getAlignment());
1868 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1869 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1873 // fold (and (load x), 255) -> (zextload x, i8)
1874 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1875 if (N1C && N0.getOpcode() == ISD::LOAD) {
1876 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1877 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1878 LN0->isUnindexed() && N0.hasOneUse() &&
1879 // Do not change the width of a volatile load.
1880 !LN0->isVolatile()) {
1881 EVT ExtVT = MVT::Other;
1882 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
1883 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
1884 ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
1886 EVT LoadedVT = LN0->getMemoryVT();
1888 // Do not generate loads of non-round integer types since these can
1889 // be expensive (and would be wrong if the type is not byte sized).
1890 if (ExtVT != MVT::Other && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
1891 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
1892 EVT PtrType = N0.getOperand(1).getValueType();
1894 // For big endian targets, we need to add an offset to the pointer to
1895 // load the correct bytes. For little endian systems, we merely need to
1896 // read fewer bytes from the same pointer.
1897 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8;
1898 unsigned EVTStoreBytes = ExtVT.getStoreSizeInBits()/8;
1899 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
1900 unsigned Alignment = LN0->getAlignment();
1901 SDValue NewPtr = LN0->getBasePtr();
1903 if (TLI.isBigEndian()) {
1904 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
1905 NewPtr, DAG.getConstant(PtrOff, PtrType));
1906 Alignment = MinAlign(Alignment, PtrOff);
1909 AddToWorkList(NewPtr.getNode());
1911 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(),
1912 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(),
1913 ExtVT, LN0->isVolatile(), Alignment);
1915 CombineTo(N0.getNode(), Load, Load.getValue(1));
1916 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1924 SDValue DAGCombiner::visitOR(SDNode *N) {
1925 SDValue N0 = N->getOperand(0);
1926 SDValue N1 = N->getOperand(1);
1927 SDValue LL, LR, RL, RR, CC0, CC1;
1928 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1929 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1930 EVT VT = N1.getValueType();
1933 if (VT.isVector()) {
1934 SDValue FoldedVOp = SimplifyVBinOp(N);
1935 if (FoldedVOp.getNode()) return FoldedVOp;
1938 // fold (or x, undef) -> -1
1939 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1940 return DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
1941 // fold (or c1, c2) -> c1|c2
1943 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
1944 // canonicalize constant to RHS
1946 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
1947 // fold (or x, 0) -> x
1948 if (N1C && N1C->isNullValue())
1950 // fold (or x, -1) -> -1
1951 if (N1C && N1C->isAllOnesValue())
1953 // fold (or x, c) -> c iff (x & ~c) == 0
1954 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
1957 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
1958 if (ROR.getNode() != 0)
1960 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1961 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
1962 isa<ConstantSDNode>(N0.getOperand(1))) {
1963 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1964 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
1965 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
1966 N0.getOperand(0), N1),
1967 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
1969 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1970 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1971 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1972 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1974 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1975 LL.getValueType().isInteger()) {
1976 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
1977 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
1978 if (cast<ConstantSDNode>(LR)->isNullValue() &&
1979 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1980 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
1981 LR.getValueType(), LL, RL);
1982 AddToWorkList(ORNode.getNode());
1983 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1985 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
1986 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
1987 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1988 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1989 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
1990 LR.getValueType(), LL, RL);
1991 AddToWorkList(ANDNode.getNode());
1992 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
1995 // canonicalize equivalent to ll == rl
1996 if (LL == RR && LR == RL) {
1997 Op1 = ISD::getSetCCSwappedOperands(Op1);
2000 if (LL == RL && LR == RR) {
2001 bool isInteger = LL.getValueType().isInteger();
2002 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2003 if (Result != ISD::SETCC_INVALID &&
2004 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2005 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2010 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2011 if (N0.getOpcode() == N1.getOpcode()) {
2012 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2013 if (Tmp.getNode()) return Tmp;
2016 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2017 if (N0.getOpcode() == ISD::AND &&
2018 N1.getOpcode() == ISD::AND &&
2019 N0.getOperand(1).getOpcode() == ISD::Constant &&
2020 N1.getOperand(1).getOpcode() == ISD::Constant &&
2021 // Don't increase # computations.
2022 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2023 // We can only do this xform if we know that bits from X that are set in C2
2024 // but not in C1 are already zero. Likewise for Y.
2025 const APInt &LHSMask =
2026 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2027 const APInt &RHSMask =
2028 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2030 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2031 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2032 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2033 N0.getOperand(0), N1.getOperand(0));
2034 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2035 DAG.getConstant(LHSMask | RHSMask, VT));
2039 // See if this is some rotate idiom.
2040 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2041 return SDValue(Rot, 0);
2046 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2047 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2048 if (Op.getOpcode() == ISD::AND) {
2049 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2050 Mask = Op.getOperand(1);
2051 Op = Op.getOperand(0);
2057 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2065 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2066 // idioms for rotate, and if the target supports rotation instructions, generate
2068 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2069 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2070 EVT VT = LHS.getValueType();
2071 if (!TLI.isTypeLegal(VT)) return 0;
2073 // The target must have at least one rotate flavor.
2074 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2075 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2076 if (!HasROTL && !HasROTR) return 0;
2078 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2079 SDValue LHSShift; // The shift.
2080 SDValue LHSMask; // AND value if any.
2081 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2082 return 0; // Not part of a rotate.
2084 SDValue RHSShift; // The shift.
2085 SDValue RHSMask; // AND value if any.
2086 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2087 return 0; // Not part of a rotate.
2089 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2090 return 0; // Not shifting the same value.
2092 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2093 return 0; // Shifts must disagree.
2095 // Canonicalize shl to left side in a shl/srl pair.
2096 if (RHSShift.getOpcode() == ISD::SHL) {
2097 std::swap(LHS, RHS);
2098 std::swap(LHSShift, RHSShift);
2099 std::swap(LHSMask , RHSMask );
2102 unsigned OpSizeInBits = VT.getSizeInBits();
2103 SDValue LHSShiftArg = LHSShift.getOperand(0);
2104 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2105 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2107 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2108 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2109 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2110 RHSShiftAmt.getOpcode() == ISD::Constant) {
2111 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2112 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2113 if ((LShVal + RShVal) != OpSizeInBits)
2118 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2120 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2122 // If there is an AND of either shifted operand, apply it to the result.
2123 if (LHSMask.getNode() || RHSMask.getNode()) {
2124 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2126 if (LHSMask.getNode()) {
2127 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2128 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2130 if (RHSMask.getNode()) {
2131 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2132 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2135 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2138 return Rot.getNode();
2141 // If there is a mask here, and we have a variable shift, we can't be sure
2142 // that we're masking out the right stuff.
2143 if (LHSMask.getNode() || RHSMask.getNode())
2146 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2147 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2148 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2149 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2150 if (ConstantSDNode *SUBC =
2151 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2152 if (SUBC->getAPIntValue() == OpSizeInBits) {
2154 return DAG.getNode(ISD::ROTL, DL, VT,
2155 LHSShiftArg, LHSShiftAmt).getNode();
2157 return DAG.getNode(ISD::ROTR, DL, VT,
2158 LHSShiftArg, RHSShiftAmt).getNode();
2163 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2164 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2165 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2166 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2167 if (ConstantSDNode *SUBC =
2168 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2169 if (SUBC->getAPIntValue() == OpSizeInBits) {
2171 return DAG.getNode(ISD::ROTR, DL, VT,
2172 LHSShiftArg, RHSShiftAmt).getNode();
2174 return DAG.getNode(ISD::ROTL, DL, VT,
2175 LHSShiftArg, LHSShiftAmt).getNode();
2180 // Look for sign/zext/any-extended or truncate cases:
2181 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2182 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2183 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2184 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2185 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2186 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2187 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2188 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2189 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2190 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2191 if (RExtOp0.getOpcode() == ISD::SUB &&
2192 RExtOp0.getOperand(1) == LExtOp0) {
2193 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2195 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2196 // (rotr x, (sub 32, y))
2197 if (ConstantSDNode *SUBC =
2198 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2199 if (SUBC->getAPIntValue() == OpSizeInBits) {
2200 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2202 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2205 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2206 RExtOp0 == LExtOp0.getOperand(1)) {
2207 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2209 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2210 // (rotl x, (sub 32, y))
2211 if (ConstantSDNode *SUBC =
2212 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2213 if (SUBC->getAPIntValue() == OpSizeInBits) {
2214 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2216 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2225 SDValue DAGCombiner::visitXOR(SDNode *N) {
2226 SDValue N0 = N->getOperand(0);
2227 SDValue N1 = N->getOperand(1);
2228 SDValue LHS, RHS, CC;
2229 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2230 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2231 EVT VT = N0.getValueType();
2234 if (VT.isVector()) {
2235 SDValue FoldedVOp = SimplifyVBinOp(N);
2236 if (FoldedVOp.getNode()) return FoldedVOp;
2239 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2240 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2241 return DAG.getConstant(0, VT);
2242 // fold (xor x, undef) -> undef
2243 if (N0.getOpcode() == ISD::UNDEF)
2245 if (N1.getOpcode() == ISD::UNDEF)
2247 // fold (xor c1, c2) -> c1^c2
2249 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2250 // canonicalize constant to RHS
2252 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2253 // fold (xor x, 0) -> x
2254 if (N1C && N1C->isNullValue())
2257 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2258 if (RXOR.getNode() != 0)
2261 // fold !(x cc y) -> (x !cc y)
2262 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2263 bool isInt = LHS.getValueType().isInteger();
2264 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2267 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2268 switch (N0.getOpcode()) {
2270 llvm_unreachable("Unhandled SetCC Equivalent!");
2272 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2273 case ISD::SELECT_CC:
2274 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2275 N0.getOperand(3), NotCC);
2280 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2281 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2282 N0.getNode()->hasOneUse() &&
2283 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2284 SDValue V = N0.getOperand(0);
2285 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2286 DAG.getConstant(1, V.getValueType()));
2287 AddToWorkList(V.getNode());
2288 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2291 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2292 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2293 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2294 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2295 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2296 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2297 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2298 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2299 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2300 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2303 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2304 if (N1C && N1C->isAllOnesValue() &&
2305 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2306 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2307 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2308 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2309 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2310 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2311 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2312 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2315 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2316 if (N1C && N0.getOpcode() == ISD::XOR) {
2317 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2318 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2320 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2321 DAG.getConstant(N1C->getAPIntValue() ^
2322 N00C->getAPIntValue(), VT));
2324 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2325 DAG.getConstant(N1C->getAPIntValue() ^
2326 N01C->getAPIntValue(), VT));
2328 // fold (xor x, x) -> 0
2330 if (!VT.isVector()) {
2331 return DAG.getConstant(0, VT);
2332 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){
2333 // Produce a vector of zeros.
2334 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
2335 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
2336 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
2337 &Ops[0], Ops.size());
2341 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2342 if (N0.getOpcode() == N1.getOpcode()) {
2343 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2344 if (Tmp.getNode()) return Tmp;
2347 // Simplify the expression using non-local knowledge.
2348 if (!VT.isVector() &&
2349 SimplifyDemandedBits(SDValue(N, 0)))
2350 return SDValue(N, 0);
2355 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2356 /// the shift amount is a constant.
2357 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2358 SDNode *LHS = N->getOperand(0).getNode();
2359 if (!LHS->hasOneUse()) return SDValue();
2361 // We want to pull some binops through shifts, so that we have (and (shift))
2362 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2363 // thing happens with address calculations, so it's important to canonicalize
2365 bool HighBitSet = false; // Can we transform this if the high bit is set?
2367 switch (LHS->getOpcode()) {
2368 default: return SDValue();
2371 HighBitSet = false; // We can only transform sra if the high bit is clear.
2374 HighBitSet = true; // We can only transform sra if the high bit is set.
2377 if (N->getOpcode() != ISD::SHL)
2378 return SDValue(); // only shl(add) not sr[al](add).
2379 HighBitSet = false; // We can only transform sra if the high bit is clear.
2383 // We require the RHS of the binop to be a constant as well.
2384 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2385 if (!BinOpCst) return SDValue();
2387 // FIXME: disable this unless the input to the binop is a shift by a constant.
2388 // If it is not a shift, it pessimizes some common cases like:
2390 // void foo(int *X, int i) { X[i & 1235] = 1; }
2391 // int bar(int *X, int i) { return X[i & 255]; }
2392 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2393 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2394 BinOpLHSVal->getOpcode() != ISD::SRA &&
2395 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2396 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2399 EVT VT = N->getValueType(0);
2401 // If this is a signed shift right, and the high bit is modified by the
2402 // logical operation, do not perform the transformation. The highBitSet
2403 // boolean indicates the value of the high bit of the constant which would
2404 // cause it to be modified for this operation.
2405 if (N->getOpcode() == ISD::SRA) {
2406 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2407 if (BinOpRHSSignSet != HighBitSet)
2411 // Fold the constants, shifting the binop RHS by the shift amount.
2412 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
2414 LHS->getOperand(1), N->getOperand(1));
2416 // Create the new shift.
2417 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(),
2418 VT, LHS->getOperand(0), N->getOperand(1));
2420 // Create the new binop.
2421 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
2424 SDValue DAGCombiner::visitSHL(SDNode *N) {
2425 SDValue N0 = N->getOperand(0);
2426 SDValue N1 = N->getOperand(1);
2427 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2428 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2429 EVT VT = N0.getValueType();
2430 unsigned OpSizeInBits = VT.getSizeInBits();
2432 // fold (shl c1, c2) -> c1<<c2
2434 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
2435 // fold (shl 0, x) -> 0
2436 if (N0C && N0C->isNullValue())
2438 // fold (shl x, c >= size(x)) -> undef
2439 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2440 return DAG.getUNDEF(VT);
2441 // fold (shl x, 0) -> x
2442 if (N1C && N1C->isNullValue())
2444 // if (shl x, c) is known to be zero, return 0
2445 if (DAG.MaskedValueIsZero(SDValue(N, 0),
2446 APInt::getAllOnesValue(VT.getSizeInBits())))
2447 return DAG.getConstant(0, VT);
2448 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
2449 if (N1.getOpcode() == ISD::TRUNCATE &&
2450 N1.getOperand(0).getOpcode() == ISD::AND &&
2451 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2452 SDValue N101 = N1.getOperand(0).getOperand(1);
2453 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2454 EVT TruncVT = N1.getValueType();
2455 SDValue N100 = N1.getOperand(0).getOperand(0);
2456 APInt TruncC = N101C->getAPIntValue();
2457 TruncC.trunc(TruncVT.getSizeInBits());
2458 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
2459 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
2460 DAG.getNode(ISD::TRUNCATE,
2463 DAG.getConstant(TruncC, TruncVT)));
2467 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2468 return SDValue(N, 0);
2470 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
2471 if (N1C && N0.getOpcode() == ISD::SHL &&
2472 N0.getOperand(1).getOpcode() == ISD::Constant) {
2473 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2474 uint64_t c2 = N1C->getZExtValue();
2475 if (c1 + c2 > OpSizeInBits)
2476 return DAG.getConstant(0, VT);
2477 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
2478 DAG.getConstant(c1 + c2, N1.getValueType()));
2480 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
2481 // (srl (and x, (shl -1, c1)), (sub c1, c2))
2482 if (N1C && N0.getOpcode() == ISD::SRL &&
2483 N0.getOperand(1).getOpcode() == ISD::Constant) {
2484 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2485 if (c1 < VT.getSizeInBits()) {
2486 uint64_t c2 = N1C->getZExtValue();
2487 SDValue HiBitsMask =
2488 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2489 VT.getSizeInBits() - c1),
2491 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT,
2495 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
2496 DAG.getConstant(c2-c1, N1.getValueType()));
2498 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
2499 DAG.getConstant(c1-c2, N1.getValueType()));
2502 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
2503 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
2504 SDValue HiBitsMask =
2505 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2506 VT.getSizeInBits() -
2507 N1C->getZExtValue()),
2509 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
2513 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2516 SDValue DAGCombiner::visitSRA(SDNode *N) {
2517 SDValue N0 = N->getOperand(0);
2518 SDValue N1 = N->getOperand(1);
2519 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2520 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2521 EVT VT = N0.getValueType();
2523 // fold (sra c1, c2) -> (sra c1, c2)
2525 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
2526 // fold (sra 0, x) -> 0
2527 if (N0C && N0C->isNullValue())
2529 // fold (sra -1, x) -> -1
2530 if (N0C && N0C->isAllOnesValue())
2532 // fold (sra x, (setge c, size(x))) -> undef
2533 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits())
2534 return DAG.getUNDEF(VT);
2535 // fold (sra x, 0) -> x
2536 if (N1C && N1C->isNullValue())
2538 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2540 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2541 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue();
2542 EVT EVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
2543 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)))
2544 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
2545 N0.getOperand(0), DAG.getValueType(EVT));
2548 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
2549 if (N1C && N0.getOpcode() == ISD::SRA) {
2550 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2551 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
2552 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1;
2553 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
2554 DAG.getConstant(Sum, N1C->getValueType(0)));
2558 // fold (sra (shl X, m), (sub result_size, n))
2559 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
2560 // result_size - n != m.
2561 // If truncate is free for the target sext(shl) is likely to result in better
2563 if (N0.getOpcode() == ISD::SHL) {
2564 // Get the two constanst of the shifts, CN0 = m, CN = n.
2565 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2567 // Determine what the truncate's result bitsize and type would be.
2568 unsigned VTValSize = VT.getSizeInBits();
2570 EVT::getIntegerVT(*DAG.getContext(), VTValSize - N1C->getZExtValue());
2571 // Determine the residual right-shift amount.
2572 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
2574 // If the shift is not a no-op (in which case this should be just a sign
2575 // extend already), the truncated to type is legal, sign_extend is legal
2576 // on that type, and the the truncate to that type is both legal and free,
2577 // perform the transform.
2578 if ((ShiftAmt > 0) &&
2579 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
2580 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
2581 TLI.isTruncateFree(VT, TruncVT)) {
2583 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy());
2584 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
2585 N0.getOperand(0), Amt);
2586 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
2588 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
2589 N->getValueType(0), Trunc);
2594 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
2595 if (N1.getOpcode() == ISD::TRUNCATE &&
2596 N1.getOperand(0).getOpcode() == ISD::AND &&
2597 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2598 SDValue N101 = N1.getOperand(0).getOperand(1);
2599 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2600 EVT TruncVT = N1.getValueType();
2601 SDValue N100 = N1.getOperand(0).getOperand(0);
2602 APInt TruncC = N101C->getAPIntValue();
2603 TruncC.trunc(TruncVT.getSizeInBits());
2604 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
2605 DAG.getNode(ISD::AND, N->getDebugLoc(),
2607 DAG.getNode(ISD::TRUNCATE,
2610 DAG.getConstant(TruncC, TruncVT)));
2614 // Simplify, based on bits shifted out of the LHS.
2615 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2616 return SDValue(N, 0);
2619 // If the sign bit is known to be zero, switch this to a SRL.
2620 if (DAG.SignBitIsZero(N0))
2621 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
2623 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2626 SDValue DAGCombiner::visitSRL(SDNode *N) {
2627 SDValue N0 = N->getOperand(0);
2628 SDValue N1 = N->getOperand(1);
2629 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2630 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2631 EVT VT = N0.getValueType();
2632 unsigned OpSizeInBits = VT.getSizeInBits();
2634 // fold (srl c1, c2) -> c1 >>u c2
2636 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
2637 // fold (srl 0, x) -> 0
2638 if (N0C && N0C->isNullValue())
2640 // fold (srl x, c >= size(x)) -> undef
2641 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2642 return DAG.getUNDEF(VT);
2643 // fold (srl x, 0) -> x
2644 if (N1C && N1C->isNullValue())
2646 // if (srl x, c) is known to be zero, return 0
2647 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2648 APInt::getAllOnesValue(OpSizeInBits)))
2649 return DAG.getConstant(0, VT);
2651 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
2652 if (N1C && N0.getOpcode() == ISD::SRL &&
2653 N0.getOperand(1).getOpcode() == ISD::Constant) {
2654 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2655 uint64_t c2 = N1C->getZExtValue();
2656 if (c1 + c2 > OpSizeInBits)
2657 return DAG.getConstant(0, VT);
2658 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
2659 DAG.getConstant(c1 + c2, N1.getValueType()));
2662 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2663 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2664 // Shifting in all undef bits?
2665 EVT SmallVT = N0.getOperand(0).getValueType();
2666 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
2667 return DAG.getUNDEF(VT);
2669 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
2670 N0.getOperand(0), N1);
2671 AddToWorkList(SmallShift.getNode());
2672 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
2675 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2676 // bit, which is unmodified by sra.
2677 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
2678 if (N0.getOpcode() == ISD::SRA)
2679 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
2682 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2683 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2684 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
2685 APInt KnownZero, KnownOne;
2686 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
2687 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2689 // If any of the input bits are KnownOne, then the input couldn't be all
2690 // zeros, thus the result of the srl will always be zero.
2691 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
2693 // If all of the bits input the to ctlz node are known to be zero, then
2694 // the result of the ctlz is "32" and the result of the shift is one.
2695 APInt UnknownBits = ~KnownZero & Mask;
2696 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2698 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2699 if ((UnknownBits & (UnknownBits - 1)) == 0) {
2700 // Okay, we know that only that the single bit specified by UnknownBits
2701 // could be set on input to the CTLZ node. If this bit is set, the SRL
2702 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2703 // to an SRL/XOR pair, which is likely to simplify more.
2704 unsigned ShAmt = UnknownBits.countTrailingZeros();
2705 SDValue Op = N0.getOperand(0);
2708 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
2709 DAG.getConstant(ShAmt, getShiftAmountTy()));
2710 AddToWorkList(Op.getNode());
2713 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
2714 Op, DAG.getConstant(1, VT));
2718 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
2719 if (N1.getOpcode() == ISD::TRUNCATE &&
2720 N1.getOperand(0).getOpcode() == ISD::AND &&
2721 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2722 SDValue N101 = N1.getOperand(0).getOperand(1);
2723 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2724 EVT TruncVT = N1.getValueType();
2725 SDValue N100 = N1.getOperand(0).getOperand(0);
2726 APInt TruncC = N101C->getAPIntValue();
2727 TruncC.trunc(TruncVT.getSizeInBits());
2728 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
2729 DAG.getNode(ISD::AND, N->getDebugLoc(),
2731 DAG.getNode(ISD::TRUNCATE,
2734 DAG.getConstant(TruncC, TruncVT)));
2738 // fold operands of srl based on knowledge that the low bits are not
2740 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2741 return SDValue(N, 0);
2743 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2746 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
2747 SDValue N0 = N->getOperand(0);
2748 EVT VT = N->getValueType(0);
2750 // fold (ctlz c1) -> c2
2751 if (isa<ConstantSDNode>(N0))
2752 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
2756 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
2757 SDValue N0 = N->getOperand(0);
2758 EVT VT = N->getValueType(0);
2760 // fold (cttz c1) -> c2
2761 if (isa<ConstantSDNode>(N0))
2762 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
2766 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
2767 SDValue N0 = N->getOperand(0);
2768 EVT VT = N->getValueType(0);
2770 // fold (ctpop c1) -> c2
2771 if (isa<ConstantSDNode>(N0))
2772 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
2776 SDValue DAGCombiner::visitSELECT(SDNode *N) {
2777 SDValue N0 = N->getOperand(0);
2778 SDValue N1 = N->getOperand(1);
2779 SDValue N2 = N->getOperand(2);
2780 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2781 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2782 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2783 EVT VT = N->getValueType(0);
2784 EVT VT0 = N0.getValueType();
2786 // fold (select C, X, X) -> X
2789 // fold (select true, X, Y) -> X
2790 if (N0C && !N0C->isNullValue())
2792 // fold (select false, X, Y) -> Y
2793 if (N0C && N0C->isNullValue())
2795 // fold (select C, 1, X) -> (or C, X)
2796 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
2797 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2798 // fold (select C, 0, 1) -> (xor C, 1)
2799 if (VT.isInteger() &&
2802 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
2803 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
2806 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
2807 N0, DAG.getConstant(1, VT0));
2808 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
2809 N0, DAG.getConstant(1, VT0));
2810 AddToWorkList(XORNode.getNode());
2812 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
2813 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
2815 // fold (select C, 0, X) -> (and (not C), X)
2816 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2817 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2818 AddToWorkList(NOTNode.getNode());
2819 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
2821 // fold (select C, X, 1) -> (or (not C), X)
2822 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
2823 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2824 AddToWorkList(NOTNode.getNode());
2825 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
2827 // fold (select C, X, 0) -> (and C, X)
2828 if (VT == MVT::i1 && N2C && N2C->isNullValue())
2829 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2830 // fold (select X, X, Y) -> (or X, Y)
2831 // fold (select X, 1, Y) -> (or X, Y)
2832 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
2833 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2834 // fold (select X, Y, X) -> (and X, Y)
2835 // fold (select X, Y, 0) -> (and X, Y)
2836 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
2837 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2839 // If we can fold this based on the true/false value, do so.
2840 if (SimplifySelectOps(N, N1, N2))
2841 return SDValue(N, 0); // Don't revisit N.
2843 // fold selects based on a setcc into other things, such as min/max/abs
2844 if (N0.getOpcode() == ISD::SETCC) {
2846 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2847 // having to say they don't support SELECT_CC on every type the DAG knows
2848 // about, since there is no way to mark an opcode illegal at all value types
2849 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
2850 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
2851 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
2852 N0.getOperand(0), N0.getOperand(1),
2853 N1, N2, N0.getOperand(2));
2854 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
2860 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
2861 SDValue N0 = N->getOperand(0);
2862 SDValue N1 = N->getOperand(1);
2863 SDValue N2 = N->getOperand(2);
2864 SDValue N3 = N->getOperand(3);
2865 SDValue N4 = N->getOperand(4);
2866 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2868 // fold select_cc lhs, rhs, x, x, cc -> x
2872 // Determine if the condition we're dealing with is constant
2873 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
2874 N0, N1, CC, N->getDebugLoc(), false);
2875 if (SCC.getNode()) AddToWorkList(SCC.getNode());
2877 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
2878 if (!SCCC->isNullValue())
2879 return N2; // cond always true -> true val
2881 return N3; // cond always false -> false val
2884 // Fold to a simpler select_cc
2885 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
2886 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
2887 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2890 // If we can fold this based on the true/false value, do so.
2891 if (SimplifySelectOps(N, N2, N3))
2892 return SDValue(N, 0); // Don't revisit N.
2894 // fold select_cc into other things, such as min/max/abs
2895 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
2898 SDValue DAGCombiner::visitSETCC(SDNode *N) {
2899 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2900 cast<CondCodeSDNode>(N->getOperand(2))->get(),
2904 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
2905 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
2906 // transformation. Returns true if extension are possible and the above
2907 // mentioned transformation is profitable.
2908 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
2910 SmallVector<SDNode*, 4> &ExtendNodes,
2911 const TargetLowering &TLI) {
2912 bool HasCopyToRegUses = false;
2913 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
2914 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
2915 UE = N0.getNode()->use_end();
2920 if (UI.getUse().getResNo() != N0.getResNo())
2922 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
2923 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
2924 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
2925 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
2926 // Sign bits will be lost after a zext.
2929 for (unsigned i = 0; i != 2; ++i) {
2930 SDValue UseOp = User->getOperand(i);
2933 if (!isa<ConstantSDNode>(UseOp))
2938 ExtendNodes.push_back(User);
2941 // If truncates aren't free and there are users we can't
2942 // extend, it isn't worthwhile.
2945 // Remember if this value is live-out.
2946 if (User->getOpcode() == ISD::CopyToReg)
2947 HasCopyToRegUses = true;
2950 if (HasCopyToRegUses) {
2951 bool BothLiveOut = false;
2952 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
2954 SDUse &Use = UI.getUse();
2955 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
2961 // Both unextended and extended values are live out. There had better be
2962 // good a reason for the transformation.
2963 return ExtendNodes.size();
2968 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2969 SDValue N0 = N->getOperand(0);
2970 EVT VT = N->getValueType(0);
2972 // fold (sext c1) -> c1
2973 if (isa<ConstantSDNode>(N0))
2974 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
2976 // fold (sext (sext x)) -> (sext x)
2977 // fold (sext (aext x)) -> (sext x)
2978 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2979 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
2982 if (N0.getOpcode() == ISD::TRUNCATE) {
2983 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2984 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2985 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
2986 if (NarrowLoad.getNode()) {
2987 if (NarrowLoad.getNode() != N0.getNode())
2988 CombineTo(N0.getNode(), NarrowLoad);
2989 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2992 // See if the value being truncated is already sign extended. If so, just
2993 // eliminate the trunc/sext pair.
2994 SDValue Op = N0.getOperand(0);
2995 unsigned OpBits = Op.getValueType().getSizeInBits();
2996 unsigned MidBits = N0.getValueType().getSizeInBits();
2997 unsigned DestBits = VT.getSizeInBits();
2998 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3000 if (OpBits == DestBits) {
3001 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3002 // bits, it is already ready.
3003 if (NumSignBits > DestBits-MidBits)
3005 } else if (OpBits < DestBits) {
3006 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3007 // bits, just sext from i32.
3008 if (NumSignBits > OpBits-MidBits)
3009 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3011 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
3012 // bits, just truncate to i32.
3013 if (NumSignBits > OpBits-MidBits)
3014 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3017 // fold (sext (truncate x)) -> (sextinreg x).
3018 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
3019 N0.getValueType())) {
3020 if (Op.getValueType().bitsLT(VT))
3021 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
3022 else if (Op.getValueType().bitsGT(VT))
3023 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
3024 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
3025 DAG.getValueType(N0.getValueType()));
3029 // fold (sext (load x)) -> (sext (truncate (sextload x)))
3030 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3031 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3032 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3033 bool DoXform = true;
3034 SmallVector<SDNode*, 4> SetCCs;
3035 if (!N0.hasOneUse())
3036 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3038 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3039 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3041 LN0->getBasePtr(), LN0->getSrcValue(),
3042 LN0->getSrcValueOffset(),
3044 LN0->isVolatile(), LN0->getAlignment());
3045 CombineTo(N, ExtLoad);
3046 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3047 N0.getValueType(), ExtLoad);
3048 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3050 // Extend SetCC uses if necessary.
3051 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3052 SDNode *SetCC = SetCCs[i];
3053 SmallVector<SDValue, 4> Ops;
3055 for (unsigned j = 0; j != 2; ++j) {
3056 SDValue SOp = SetCC->getOperand(j);
3058 Ops.push_back(ExtLoad);
3060 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND,
3061 N->getDebugLoc(), VT, SOp));
3064 Ops.push_back(SetCC->getOperand(2));
3065 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3066 SetCC->getValueType(0),
3067 &Ops[0], Ops.size()));
3070 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3074 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3075 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3076 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3077 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3078 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3079 EVT EVT = LN0->getMemoryVT();
3080 if ((!LegalOperations && !LN0->isVolatile()) ||
3081 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) {
3082 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3084 LN0->getBasePtr(), LN0->getSrcValue(),
3085 LN0->getSrcValueOffset(), EVT,
3086 LN0->isVolatile(), LN0->getAlignment());
3087 CombineTo(N, ExtLoad);
3088 CombineTo(N0.getNode(),
3089 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3090 N0.getValueType(), ExtLoad),
3091 ExtLoad.getValue(1));
3092 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3096 if (N0.getOpcode() == ISD::SETCC) {
3097 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
3098 if (VT.isVector() &&
3099 // We know that the # elements of the results is the same as the
3100 // # elements of the compare (and the # elements of the compare result
3101 // for that matter). Check to see that they are the same size. If so,
3102 // we know that the element size of the sext'd result matches the
3103 // element size of the compare operands.
3104 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() &&
3106 // Only do this before legalize for now.
3108 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3110 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3113 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3115 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
3117 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3118 NegOne, DAG.getConstant(0, VT),
3119 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3120 if (SCC.getNode()) return SCC;
3125 // fold (sext x) -> (zext x) if the sign bit is known zero.
3126 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3127 DAG.SignBitIsZero(N0))
3128 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3133 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3134 SDValue N0 = N->getOperand(0);
3135 EVT VT = N->getValueType(0);
3137 // fold (zext c1) -> c1
3138 if (isa<ConstantSDNode>(N0))
3139 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3140 // fold (zext (zext x)) -> (zext x)
3141 // fold (zext (aext x)) -> (zext x)
3142 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3143 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3146 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3147 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3148 if (N0.getOpcode() == ISD::TRUNCATE) {
3149 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3150 if (NarrowLoad.getNode()) {
3151 if (NarrowLoad.getNode() != N0.getNode())
3152 CombineTo(N0.getNode(), NarrowLoad);
3153 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3157 // fold (zext (truncate x)) -> (and x, mask)
3158 if (N0.getOpcode() == ISD::TRUNCATE &&
3159 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
3160 SDValue Op = N0.getOperand(0);
3161 if (Op.getValueType().bitsLT(VT)) {
3162 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
3163 } else if (Op.getValueType().bitsGT(VT)) {
3164 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3166 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType());
3169 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
3170 // if either of the casts is not free.
3171 if (N0.getOpcode() == ISD::AND &&
3172 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3173 N0.getOperand(1).getOpcode() == ISD::Constant &&
3174 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3175 N0.getValueType()) ||
3176 !TLI.isZExtFree(N0.getValueType(), VT))) {
3177 SDValue X = N0.getOperand(0).getOperand(0);
3178 if (X.getValueType().bitsLT(VT)) {
3179 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
3180 } else if (X.getValueType().bitsGT(VT)) {
3181 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3183 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3184 Mask.zext(VT.getSizeInBits());
3185 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3186 X, DAG.getConstant(Mask, VT));
3189 // fold (zext (load x)) -> (zext (truncate (zextload x)))
3190 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3191 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3192 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3193 bool DoXform = true;
3194 SmallVector<SDNode*, 4> SetCCs;
3195 if (!N0.hasOneUse())
3196 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3198 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3199 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3201 LN0->getBasePtr(), LN0->getSrcValue(),
3202 LN0->getSrcValueOffset(),
3204 LN0->isVolatile(), LN0->getAlignment());
3205 CombineTo(N, ExtLoad);
3206 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3207 N0.getValueType(), ExtLoad);
3208 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3210 // Extend SetCC uses if necessary.
3211 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3212 SDNode *SetCC = SetCCs[i];
3213 SmallVector<SDValue, 4> Ops;
3215 for (unsigned j = 0; j != 2; ++j) {
3216 SDValue SOp = SetCC->getOperand(j);
3218 Ops.push_back(ExtLoad);
3220 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
3221 N->getDebugLoc(), VT, SOp));
3224 Ops.push_back(SetCC->getOperand(2));
3225 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3226 SetCC->getValueType(0),
3227 &Ops[0], Ops.size()));
3230 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3234 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
3235 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
3236 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3237 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3238 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3239 EVT EVT = LN0->getMemoryVT();
3240 if ((!LegalOperations && !LN0->isVolatile()) ||
3241 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) {
3242 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3244 LN0->getBasePtr(), LN0->getSrcValue(),
3245 LN0->getSrcValueOffset(), EVT,
3246 LN0->isVolatile(), LN0->getAlignment());
3247 CombineTo(N, ExtLoad);
3248 CombineTo(N0.getNode(),
3249 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
3251 ExtLoad.getValue(1));
3252 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3256 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3257 if (N0.getOpcode() == ISD::SETCC) {
3259 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3260 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3261 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3262 if (SCC.getNode()) return SCC;
3268 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
3269 SDValue N0 = N->getOperand(0);
3270 EVT VT = N->getValueType(0);
3272 // fold (aext c1) -> c1
3273 if (isa<ConstantSDNode>(N0))
3274 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
3275 // fold (aext (aext x)) -> (aext x)
3276 // fold (aext (zext x)) -> (zext x)
3277 // fold (aext (sext x)) -> (sext x)
3278 if (N0.getOpcode() == ISD::ANY_EXTEND ||
3279 N0.getOpcode() == ISD::ZERO_EXTEND ||
3280 N0.getOpcode() == ISD::SIGN_EXTEND)
3281 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
3283 // fold (aext (truncate (load x))) -> (aext (smaller load x))
3284 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3285 if (N0.getOpcode() == ISD::TRUNCATE) {
3286 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3287 if (NarrowLoad.getNode()) {
3288 if (NarrowLoad.getNode() != N0.getNode())
3289 CombineTo(N0.getNode(), NarrowLoad);
3290 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3294 // fold (aext (truncate x))
3295 if (N0.getOpcode() == ISD::TRUNCATE) {
3296 SDValue TruncOp = N0.getOperand(0);
3297 if (TruncOp.getValueType() == VT)
3298 return TruncOp; // x iff x size == zext size.
3299 if (TruncOp.getValueType().bitsGT(VT))
3300 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
3301 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
3304 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
3305 // if the trunc is not free.
3306 if (N0.getOpcode() == ISD::AND &&
3307 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3308 N0.getOperand(1).getOpcode() == ISD::Constant &&
3309 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3310 N0.getValueType())) {
3311 SDValue X = N0.getOperand(0).getOperand(0);
3312 if (X.getValueType().bitsLT(VT)) {
3313 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
3314 } else if (X.getValueType().bitsGT(VT)) {
3315 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
3317 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3318 Mask.zext(VT.getSizeInBits());
3319 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3320 X, DAG.getConstant(Mask, VT));
3323 // fold (aext (load x)) -> (aext (truncate (extload x)))
3324 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3325 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3326 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
3327 bool DoXform = true;
3328 SmallVector<SDNode*, 4> SetCCs;
3329 if (!N0.hasOneUse())
3330 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
3332 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3333 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
3335 LN0->getBasePtr(), LN0->getSrcValue(),
3336 LN0->getSrcValueOffset(),
3338 LN0->isVolatile(), LN0->getAlignment());
3339 CombineTo(N, ExtLoad);
3340 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3341 N0.getValueType(), ExtLoad);
3342 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3344 // Extend SetCC uses if necessary.
3345 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3346 SDNode *SetCC = SetCCs[i];
3347 SmallVector<SDValue, 4> Ops;
3349 for (unsigned j = 0; j != 2; ++j) {
3350 SDValue SOp = SetCC->getOperand(j);
3352 Ops.push_back(ExtLoad);
3354 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND,
3355 N->getDebugLoc(), VT, SOp));
3358 Ops.push_back(SetCC->getOperand(2));
3359 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3360 SetCC->getValueType(0),
3361 &Ops[0], Ops.size()));
3364 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3368 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
3369 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
3370 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
3371 if (N0.getOpcode() == ISD::LOAD &&
3372 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3374 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3375 EVT EVT = LN0->getMemoryVT();
3376 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
3377 VT, LN0->getChain(), LN0->getBasePtr(),
3379 LN0->getSrcValueOffset(), EVT,
3380 LN0->isVolatile(), LN0->getAlignment());
3381 CombineTo(N, ExtLoad);
3382 CombineTo(N0.getNode(),
3383 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3384 N0.getValueType(), ExtLoad),
3385 ExtLoad.getValue(1));
3386 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3389 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3390 if (N0.getOpcode() == ISD::SETCC) {
3392 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3393 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3394 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3402 /// GetDemandedBits - See if the specified operand can be simplified with the
3403 /// knowledge that only the bits specified by Mask are used. If so, return the
3404 /// simpler operand, otherwise return a null SDValue.
3405 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
3406 switch (V.getOpcode()) {
3410 // If the LHS or RHS don't contribute bits to the or, drop them.
3411 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
3412 return V.getOperand(1);
3413 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
3414 return V.getOperand(0);
3417 // Only look at single-use SRLs.
3418 if (!V.getNode()->hasOneUse())
3420 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3421 // See if we can recursively simplify the LHS.
3422 unsigned Amt = RHSC->getZExtValue();
3424 // Watch out for shift count overflow though.
3425 if (Amt >= Mask.getBitWidth()) break;
3426 APInt NewMask = Mask << Amt;
3427 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
3428 if (SimplifyLHS.getNode())
3429 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
3430 SimplifyLHS, V.getOperand(1));
3436 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3437 /// bits and then truncated to a narrower type and where N is a multiple
3438 /// of number of bits of the narrower type, transform it to a narrower load
3439 /// from address + N / num of bits of new type. If the result is to be
3440 /// extended, also fold the extension to form a extending load.
3441 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
3442 unsigned Opc = N->getOpcode();
3443 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3444 SDValue N0 = N->getOperand(0);
3445 EVT VT = N->getValueType(0);
3448 // This transformation isn't valid for vector loads.
3452 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
3454 if (Opc == ISD::SIGN_EXTEND_INREG) {
3455 ExtType = ISD::SEXTLOAD;
3456 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3457 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT))
3461 unsigned EVTBits = ExtVT.getSizeInBits();
3463 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
3464 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3465 ShAmt = N01->getZExtValue();
3466 // Is the shift amount a multiple of size of VT?
3467 if ((ShAmt & (EVTBits-1)) == 0) {
3468 N0 = N0.getOperand(0);
3469 // Is the load width a multiple of size of VT?
3470 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
3476 // Do not generate loads of non-round integer types since these can
3477 // be expensive (and would be wrong if the type is not byte sized).
3478 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() &&
3479 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
3480 // Do not change the width of a volatile load.
3481 !cast<LoadSDNode>(N0)->isVolatile()) {
3482 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3483 EVT PtrType = N0.getOperand(1).getValueType();
3485 // For big endian targets, we need to adjust the offset to the pointer to
3486 // load the correct bytes.
3487 if (TLI.isBigEndian()) {
3488 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
3489 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
3490 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3493 uint64_t PtrOff = ShAmt / 8;
3494 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3495 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
3496 PtrType, LN0->getBasePtr(),
3497 DAG.getConstant(PtrOff, PtrType));
3498 AddToWorkList(NewPtr.getNode());
3500 SDValue Load = (ExtType == ISD::NON_EXTLOAD)
3501 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
3502 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3503 LN0->isVolatile(), NewAlign)
3504 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr,
3505 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3506 ExtVT, LN0->isVolatile(), NewAlign);
3508 // Replace the old load's chain with the new load's chain.
3509 WorkListRemover DeadNodes(*this);
3510 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
3513 // Return the new loaded value.
3520 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3521 SDValue N0 = N->getOperand(0);
3522 SDValue N1 = N->getOperand(1);
3523 EVT VT = N->getValueType(0);
3524 EVT EVT = cast<VTSDNode>(N1)->getVT();
3525 unsigned VTBits = VT.getSizeInBits();
3526 unsigned EVTBits = EVT.getSizeInBits();
3528 // fold (sext_in_reg c1) -> c1
3529 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3530 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
3532 // If the input is already sign extended, just drop the extension.
3533 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1)
3536 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3537 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3538 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
3539 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3540 N0.getOperand(0), N1);
3543 // fold (sext_in_reg (sext x)) -> (sext x)
3544 // fold (sext_in_reg (aext x)) -> (sext x)
3545 // if x is small enough.
3546 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
3547 SDValue N00 = N0.getOperand(0);
3548 if (N00.getValueType().getSizeInBits() < EVTBits)
3549 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
3552 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3553 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
3554 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
3556 // fold operands of sext_in_reg based on knowledge that the top bits are not
3558 if (SimplifyDemandedBits(SDValue(N, 0)))
3559 return SDValue(N, 0);
3561 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3562 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3563 SDValue NarrowLoad = ReduceLoadWidth(N);
3564 if (NarrowLoad.getNode())
3567 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
3568 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
3569 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3570 if (N0.getOpcode() == ISD::SRL) {
3571 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3572 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) {
3573 // We can turn this into an SRA iff the input to the SRL is already sign
3575 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3576 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
3577 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
3578 N0.getOperand(0), N0.getOperand(1));
3582 // fold (sext_inreg (extload x)) -> (sextload x)
3583 if (ISD::isEXTLoad(N0.getNode()) &&
3584 ISD::isUNINDEXEDLoad(N0.getNode()) &&
3585 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3586 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3587 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3588 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3589 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3591 LN0->getBasePtr(), LN0->getSrcValue(),
3592 LN0->getSrcValueOffset(), EVT,
3593 LN0->isVolatile(), LN0->getAlignment());
3594 CombineTo(N, ExtLoad);
3595 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3596 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3598 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3599 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3601 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3602 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3603 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3604 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3605 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3607 LN0->getBasePtr(), LN0->getSrcValue(),
3608 LN0->getSrcValueOffset(), EVT,
3609 LN0->isVolatile(), LN0->getAlignment());
3610 CombineTo(N, ExtLoad);
3611 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3612 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3617 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
3618 SDValue N0 = N->getOperand(0);
3619 EVT VT = N->getValueType(0);
3622 if (N0.getValueType() == N->getValueType(0))
3624 // fold (truncate c1) -> c1
3625 if (isa<ConstantSDNode>(N0))
3626 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
3627 // fold (truncate (truncate x)) -> (truncate x)
3628 if (N0.getOpcode() == ISD::TRUNCATE)
3629 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3630 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3631 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
3632 N0.getOpcode() == ISD::ANY_EXTEND) {
3633 if (N0.getOperand(0).getValueType().bitsLT(VT))
3634 // if the source is smaller than the dest, we still need an extend
3635 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
3637 else if (N0.getOperand(0).getValueType().bitsGT(VT))
3638 // if the source is larger than the dest, than we just need the truncate
3639 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3641 // if the source and dest are the same type, we can drop both the extend
3643 return N0.getOperand(0);
3646 // See if we can simplify the input to this truncate through knowledge that
3647 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3650 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
3651 VT.getSizeInBits()));
3652 if (Shorter.getNode())
3653 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
3655 // fold (truncate (load x)) -> (smaller load x)
3656 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3657 return ReduceLoadWidth(N);
3660 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
3661 SDValue Elt = N->getOperand(i);
3662 if (Elt.getOpcode() != ISD::MERGE_VALUES)
3663 return Elt.getNode();
3664 return Elt.getOperand(Elt.getResNo()).getNode();
3667 /// CombineConsecutiveLoads - build_pair (load, load) -> load
3668 /// if load locations are consecutive.
3669 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
3670 assert(N->getOpcode() == ISD::BUILD_PAIR);
3672 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
3673 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
3674 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
3676 EVT LD1VT = LD1->getValueType(0);
3677 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3679 if (ISD::isNON_EXTLoad(LD2) &&
3681 // If both are volatile this would reduce the number of volatile loads.
3682 // If one is volatile it might be ok, but play conservative and bail out.
3683 !LD1->isVolatile() &&
3684 !LD2->isVolatile() &&
3685 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
3686 unsigned Align = LD1->getAlignment();
3687 unsigned NewAlign = TLI.getTargetData()->
3688 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
3690 if (NewAlign <= Align &&
3691 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
3692 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
3693 LD1->getBasePtr(), LD1->getSrcValue(),
3694 LD1->getSrcValueOffset(), false, Align);
3700 SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3701 SDValue N0 = N->getOperand(0);
3702 EVT VT = N->getValueType(0);
3704 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3705 // Only do this before legalize, since afterward the target may be depending
3706 // on the bitconvert.
3707 // First check to see if this is all constant.
3709 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
3711 bool isSimple = true;
3712 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3713 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3714 N0.getOperand(i).getOpcode() != ISD::Constant &&
3715 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3720 EVT DestEltVT = N->getValueType(0).getVectorElementType();
3721 assert(!DestEltVT.isVector() &&
3722 "Element type of vector ValueType must not be vector!");
3724 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
3727 // If the input is a constant, let getNode fold it.
3728 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3729 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0);
3730 if (Res.getNode() != N) {
3731 if (!LegalOperations ||
3732 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
3735 // Folding it resulted in an illegal node, and it's too late to
3736 // do that. Clean up the old node and forego the transformation.
3737 // Ideally this won't happen very often, because instcombine
3738 // and the earlier dagcombine runs (where illegal nodes are
3739 // permitted) should have folded most of them already.
3740 DAG.DeleteNode(Res.getNode());
3744 // (conv (conv x, t1), t2) -> (conv x, t2)
3745 if (N0.getOpcode() == ISD::BIT_CONVERT)
3746 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT,
3749 // fold (conv (load x)) -> (load (conv*)x)
3750 // If the resultant load doesn't need a higher alignment than the original!
3751 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
3752 // Do not change the width of a volatile load.
3753 !cast<LoadSDNode>(N0)->isVolatile() &&
3754 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
3755 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3756 unsigned Align = TLI.getTargetData()->
3757 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
3758 unsigned OrigAlign = LN0->getAlignment();
3760 if (Align <= OrigAlign) {
3761 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
3763 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3764 LN0->isVolatile(), OrigAlign);
3766 CombineTo(N0.getNode(),
3767 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3768 N0.getValueType(), Load),
3774 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
3775 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
3776 // This often reduces constant pool loads.
3777 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
3778 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
3779 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT,
3781 AddToWorkList(NewConv.getNode());
3783 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3784 if (N0.getOpcode() == ISD::FNEG)
3785 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3786 NewConv, DAG.getConstant(SignBit, VT));
3787 assert(N0.getOpcode() == ISD::FABS);
3788 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3789 NewConv, DAG.getConstant(~SignBit, VT));
3792 // fold (bitconvert (fcopysign cst, x)) ->
3793 // (or (and (bitconvert x), sign), (and cst, (not sign)))
3794 // Note that we don't handle (copysign x, cst) because this can always be
3795 // folded to an fneg or fabs.
3796 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
3797 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
3798 VT.isInteger() && !VT.isVector()) {
3799 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
3800 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
3801 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) {
3802 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3803 IntXVT, N0.getOperand(1));
3804 AddToWorkList(X.getNode());
3806 // If X has a different width than the result/lhs, sext it or truncate it.
3807 unsigned VTWidth = VT.getSizeInBits();
3808 if (OrigXWidth < VTWidth) {
3809 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
3810 AddToWorkList(X.getNode());
3811 } else if (OrigXWidth > VTWidth) {
3812 // To get the sign bit in the right place, we have to shift it right
3813 // before truncating.
3814 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
3815 X.getValueType(), X,
3816 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
3817 AddToWorkList(X.getNode());
3818 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3819 AddToWorkList(X.getNode());
3822 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3823 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
3824 X, DAG.getConstant(SignBit, VT));
3825 AddToWorkList(X.getNode());
3827 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3828 VT, N0.getOperand(0));
3829 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
3830 Cst, DAG.getConstant(~SignBit, VT));
3831 AddToWorkList(Cst.getNode());
3833 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
3837 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
3838 if (N0.getOpcode() == ISD::BUILD_PAIR) {
3839 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
3840 if (CombineLD.getNode())
3847 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
3848 EVT VT = N->getValueType(0);
3849 return CombineConsecutiveLoads(N, VT);
3852 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3853 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3854 /// destination element value type.
3855 SDValue DAGCombiner::
3856 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
3857 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
3859 // If this is already the right type, we're done.
3860 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
3862 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
3863 unsigned DstBitSize = DstEltVT.getSizeInBits();
3865 // If this is a conversion of N elements of one type to N elements of another
3866 // type, convert each element. This handles FP<->INT cases.
3867 if (SrcBitSize == DstBitSize) {
3868 SmallVector<SDValue, 8> Ops;
3869 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3870 SDValue Op = BV->getOperand(i);
3871 // If the vector element type is not legal, the BUILD_VECTOR operands
3872 // are promoted and implicitly truncated. Make that explicit here.
3873 if (Op.getValueType() != SrcEltVT)
3874 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
3875 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(),
3877 AddToWorkList(Ops.back().getNode());
3879 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
3880 BV->getValueType(0).getVectorNumElements());
3881 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3882 &Ops[0], Ops.size());
3885 // Otherwise, we're growing or shrinking the elements. To avoid having to
3886 // handle annoying details of growing/shrinking FP values, we convert them to
3888 if (SrcEltVT.isFloatingPoint()) {
3889 // Convert the input float vector to a int vector where the elements are the
3891 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3892 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
3893 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
3897 // Now we know the input is an integer vector. If the output is a FP type,
3898 // convert to integer first, then to FP of the right size.
3899 if (DstEltVT.isFloatingPoint()) {
3900 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3901 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
3902 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
3904 // Next, convert to FP elements of the same size.
3905 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3908 // Okay, we know the src/dst types are both integers of differing types.
3909 // Handling growing first.
3910 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
3911 if (SrcBitSize < DstBitSize) {
3912 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3914 SmallVector<SDValue, 8> Ops;
3915 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3916 i += NumInputsPerOutput) {
3917 bool isLE = TLI.isLittleEndian();
3918 APInt NewBits = APInt(DstBitSize, 0);
3919 bool EltIsUndef = true;
3920 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3921 // Shift the previously computed bits over.
3922 NewBits <<= SrcBitSize;
3923 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3924 if (Op.getOpcode() == ISD::UNDEF) continue;
3927 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).
3928 zextOrTrunc(SrcBitSize).zext(DstBitSize));
3932 Ops.push_back(DAG.getUNDEF(DstEltVT));
3934 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3937 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
3938 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3939 &Ops[0], Ops.size());
3942 // Finally, this must be the case where we are shrinking elements: each input
3943 // turns into multiple outputs.
3944 bool isS2V = ISD::isScalarToVector(BV);
3945 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3946 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
3947 NumOutputsPerInput*BV->getNumOperands());
3948 SmallVector<SDValue, 8> Ops;
3950 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3951 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3952 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3953 Ops.push_back(DAG.getUNDEF(DstEltVT));
3957 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))->
3958 getAPIntValue()).zextOrTrunc(SrcBitSize);
3960 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3961 APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
3962 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3963 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
3964 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
3965 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
3967 OpVal = OpVal.lshr(DstBitSize);
3970 // For big endian targets, swap the order of the pieces of each element.
3971 if (TLI.isBigEndian())
3972 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3975 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3976 &Ops[0], Ops.size());
3979 SDValue DAGCombiner::visitFADD(SDNode *N) {
3980 SDValue N0 = N->getOperand(0);
3981 SDValue N1 = N->getOperand(1);
3982 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3983 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3984 EVT VT = N->getValueType(0);
3987 if (VT.isVector()) {
3988 SDValue FoldedVOp = SimplifyVBinOp(N);
3989 if (FoldedVOp.getNode()) return FoldedVOp;
3992 // fold (fadd c1, c2) -> (fadd c1, c2)
3993 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3994 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
3995 // canonicalize constant to RHS
3996 if (N0CFP && !N1CFP)
3997 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
3998 // fold (fadd A, 0) -> A
3999 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4001 // fold (fadd A, (fneg B)) -> (fsub A, B)
4002 if (isNegatibleForFree(N1, LegalOperations) == 2)
4003 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
4004 GetNegatedExpression(N1, DAG, LegalOperations));
4005 // fold (fadd (fneg A), B) -> (fsub B, A)
4006 if (isNegatibleForFree(N0, LegalOperations) == 2)
4007 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
4008 GetNegatedExpression(N0, DAG, LegalOperations));
4010 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
4011 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
4012 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4013 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
4014 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
4015 N0.getOperand(1), N1));
4020 SDValue DAGCombiner::visitFSUB(SDNode *N) {
4021 SDValue N0 = N->getOperand(0);
4022 SDValue N1 = N->getOperand(1);
4023 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4024 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4025 EVT VT = N->getValueType(0);
4028 if (VT.isVector()) {
4029 SDValue FoldedVOp = SimplifyVBinOp(N);
4030 if (FoldedVOp.getNode()) return FoldedVOp;
4033 // fold (fsub c1, c2) -> c1-c2
4034 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4035 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
4036 // fold (fsub A, 0) -> A
4037 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4039 // fold (fsub 0, B) -> -B
4040 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
4041 if (isNegatibleForFree(N1, LegalOperations))
4042 return GetNegatedExpression(N1, DAG, LegalOperations);
4043 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4044 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
4046 // fold (fsub A, (fneg B)) -> (fadd A, B)
4047 if (isNegatibleForFree(N1, LegalOperations))
4048 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
4049 GetNegatedExpression(N1, DAG, LegalOperations));
4054 SDValue DAGCombiner::visitFMUL(SDNode *N) {
4055 SDValue N0 = N->getOperand(0);
4056 SDValue N1 = N->getOperand(1);
4057 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4058 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4059 EVT VT = N->getValueType(0);
4062 if (VT.isVector()) {
4063 SDValue FoldedVOp = SimplifyVBinOp(N);
4064 if (FoldedVOp.getNode()) return FoldedVOp;
4067 // fold (fmul c1, c2) -> c1*c2
4068 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4069 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
4070 // canonicalize constant to RHS
4071 if (N0CFP && !N1CFP)
4072 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
4073 // fold (fmul A, 0) -> 0
4074 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4076 // fold (fmul A, 0) -> 0, vector edition.
4077 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
4079 // fold (fmul X, 2.0) -> (fadd X, X)
4080 if (N1CFP && N1CFP->isExactlyValue(+2.0))
4081 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
4082 // fold (fmul X, -1.0) -> (fneg X)
4083 if (N1CFP && N1CFP->isExactlyValue(-1.0))
4084 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4085 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
4087 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
4088 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4089 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4090 // Both can be negated for free, check to see if at least one is cheaper
4092 if (LHSNeg == 2 || RHSNeg == 2)
4093 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4094 GetNegatedExpression(N0, DAG, LegalOperations),
4095 GetNegatedExpression(N1, DAG, LegalOperations));
4099 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
4100 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
4101 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4102 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
4103 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4104 N0.getOperand(1), N1));
4109 SDValue DAGCombiner::visitFDIV(SDNode *N) {
4110 SDValue N0 = N->getOperand(0);
4111 SDValue N1 = N->getOperand(1);
4112 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4113 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4114 EVT VT = N->getValueType(0);
4117 if (VT.isVector()) {
4118 SDValue FoldedVOp = SimplifyVBinOp(N);
4119 if (FoldedVOp.getNode()) return FoldedVOp;
4122 // fold (fdiv c1, c2) -> c1/c2
4123 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4124 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
4127 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
4128 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4129 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4130 // Both can be negated for free, check to see if at least one is cheaper
4132 if (LHSNeg == 2 || RHSNeg == 2)
4133 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
4134 GetNegatedExpression(N0, DAG, LegalOperations),
4135 GetNegatedExpression(N1, DAG, LegalOperations));
4142 SDValue DAGCombiner::visitFREM(SDNode *N) {
4143 SDValue N0 = N->getOperand(0);
4144 SDValue N1 = N->getOperand(1);
4145 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4146 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4147 EVT VT = N->getValueType(0);
4149 // fold (frem c1, c2) -> fmod(c1,c2)
4150 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4151 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
4156 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
4157 SDValue N0 = N->getOperand(0);
4158 SDValue N1 = N->getOperand(1);
4159 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4160 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4161 EVT VT = N->getValueType(0);
4163 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
4164 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
4167 const APFloat& V = N1CFP->getValueAPF();
4168 // copysign(x, c1) -> fabs(x) iff ispos(c1)
4169 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
4170 if (!V.isNegative()) {
4171 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
4172 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4174 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4175 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
4176 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
4180 // copysign(fabs(x), y) -> copysign(x, y)
4181 // copysign(fneg(x), y) -> copysign(x, y)
4182 // copysign(copysign(x,z), y) -> copysign(x, y)
4183 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
4184 N0.getOpcode() == ISD::FCOPYSIGN)
4185 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4186 N0.getOperand(0), N1);
4188 // copysign(x, abs(y)) -> abs(x)
4189 if (N1.getOpcode() == ISD::FABS)
4190 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4192 // copysign(x, copysign(y,z)) -> copysign(x, z)
4193 if (N1.getOpcode() == ISD::FCOPYSIGN)
4194 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4195 N0, N1.getOperand(1));
4197 // copysign(x, fp_extend(y)) -> copysign(x, y)
4198 // copysign(x, fp_round(y)) -> copysign(x, y)
4199 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
4200 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4201 N0, N1.getOperand(0));
4206 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
4207 SDValue N0 = N->getOperand(0);
4208 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4209 EVT VT = N->getValueType(0);
4210 EVT OpVT = N0.getValueType();
4212 // fold (sint_to_fp c1) -> c1fp
4213 if (N0C && OpVT != MVT::ppcf128)
4214 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4216 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
4217 // but UINT_TO_FP is legal on this target, try to convert.
4218 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
4219 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
4220 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
4221 if (DAG.SignBitIsZero(N0))
4222 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4228 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
4229 SDValue N0 = N->getOperand(0);
4230 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4231 EVT VT = N->getValueType(0);
4232 EVT OpVT = N0.getValueType();
4234 // fold (uint_to_fp c1) -> c1fp
4235 if (N0C && OpVT != MVT::ppcf128)
4236 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4238 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
4239 // but SINT_TO_FP is legal on this target, try to convert.
4240 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
4241 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
4242 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
4243 if (DAG.SignBitIsZero(N0))
4244 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4250 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
4251 SDValue N0 = N->getOperand(0);
4252 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4253 EVT VT = N->getValueType(0);
4255 // fold (fp_to_sint c1fp) -> c1
4257 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
4262 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
4263 SDValue N0 = N->getOperand(0);
4264 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4265 EVT VT = N->getValueType(0);
4267 // fold (fp_to_uint c1fp) -> c1
4268 if (N0CFP && VT != MVT::ppcf128)
4269 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
4274 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
4275 SDValue N0 = N->getOperand(0);
4276 SDValue N1 = N->getOperand(1);
4277 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4278 EVT VT = N->getValueType(0);
4280 // fold (fp_round c1fp) -> c1fp
4281 if (N0CFP && N0.getValueType() != MVT::ppcf128)
4282 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
4284 // fold (fp_round (fp_extend x)) -> x
4285 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
4286 return N0.getOperand(0);
4288 // fold (fp_round (fp_round x)) -> (fp_round x)
4289 if (N0.getOpcode() == ISD::FP_ROUND) {
4290 // This is a value preserving truncation if both round's are.
4291 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
4292 N0.getNode()->getConstantOperandVal(1) == 1;
4293 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
4294 DAG.getIntPtrConstant(IsTrunc));
4297 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
4298 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
4299 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
4300 N0.getOperand(0), N1);
4301 AddToWorkList(Tmp.getNode());
4302 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4303 Tmp, N0.getOperand(1));
4309 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
4310 SDValue N0 = N->getOperand(0);
4311 EVT VT = N->getValueType(0);
4312 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4313 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4315 // fold (fp_round_inreg c1fp) -> c1fp
4316 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) {
4317 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
4318 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
4324 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
4325 SDValue N0 = N->getOperand(0);
4326 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4327 EVT VT = N->getValueType(0);
4329 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
4330 if (N->hasOneUse() &&
4331 N->use_begin()->getOpcode() == ISD::FP_ROUND)
4334 // fold (fp_extend c1fp) -> c1fp
4335 if (N0CFP && VT != MVT::ppcf128)
4336 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
4338 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
4340 if (N0.getOpcode() == ISD::FP_ROUND
4341 && N0.getNode()->getConstantOperandVal(1) == 1) {
4342 SDValue In = N0.getOperand(0);
4343 if (In.getValueType() == VT) return In;
4344 if (VT.bitsLT(In.getValueType()))
4345 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
4346 In, N0.getOperand(1));
4347 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
4350 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
4351 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
4352 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4353 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4354 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4355 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4357 LN0->getBasePtr(), LN0->getSrcValue(),
4358 LN0->getSrcValueOffset(),
4360 LN0->isVolatile(), LN0->getAlignment());
4361 CombineTo(N, ExtLoad);
4362 CombineTo(N0.getNode(),
4363 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
4364 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
4365 ExtLoad.getValue(1));
4366 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4372 SDValue DAGCombiner::visitFNEG(SDNode *N) {
4373 SDValue N0 = N->getOperand(0);
4375 if (isNegatibleForFree(N0, LegalOperations))
4376 return GetNegatedExpression(N0, DAG, LegalOperations);
4378 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
4379 // constant pool values.
4380 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4381 N0.getOperand(0).getValueType().isInteger() &&
4382 !N0.getOperand(0).getValueType().isVector()) {
4383 SDValue Int = N0.getOperand(0);
4384 EVT IntVT = Int.getValueType();
4385 if (IntVT.isInteger() && !IntVT.isVector()) {
4386 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
4387 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4388 AddToWorkList(Int.getNode());
4389 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4390 N->getValueType(0), Int);
4397 SDValue DAGCombiner::visitFABS(SDNode *N) {
4398 SDValue N0 = N->getOperand(0);
4399 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4400 EVT VT = N->getValueType(0);
4402 // fold (fabs c1) -> fabs(c1)
4403 if (N0CFP && VT != MVT::ppcf128)
4404 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4405 // fold (fabs (fabs x)) -> (fabs x)
4406 if (N0.getOpcode() == ISD::FABS)
4407 return N->getOperand(0);
4408 // fold (fabs (fneg x)) -> (fabs x)
4409 // fold (fabs (fcopysign x, y)) -> (fabs x)
4410 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
4411 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
4413 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
4414 // constant pool values.
4415 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4416 N0.getOperand(0).getValueType().isInteger() &&
4417 !N0.getOperand(0).getValueType().isVector()) {
4418 SDValue Int = N0.getOperand(0);
4419 EVT IntVT = Int.getValueType();
4420 if (IntVT.isInteger() && !IntVT.isVector()) {
4421 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
4422 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4423 AddToWorkList(Int.getNode());
4424 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4425 N->getValueType(0), Int);
4432 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
4433 SDValue Chain = N->getOperand(0);
4434 SDValue N1 = N->getOperand(1);
4435 SDValue N2 = N->getOperand(2);
4436 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4438 // never taken branch, fold to chain
4439 if (N1C && N1C->isNullValue())
4441 // unconditional branch
4442 if (N1C && N1C->getAPIntValue() == 1)
4443 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2);
4444 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
4446 if (N1.getOpcode() == ISD::SETCC &&
4447 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
4448 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4449 Chain, N1.getOperand(2),
4450 N1.getOperand(0), N1.getOperand(1), N2);
4453 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) {
4454 // Match this pattern so that we can generate simpler code:
4457 // %b = and i32 %a, 2
4458 // %c = srl i32 %b, 1
4459 // brcond i32 %c ...
4465 // %c = setcc eq %b, 0
4468 // This applies only when the AND constant value has one bit set and the
4469 // SRL constant is equal to the log2 of the AND constant. The back-end is
4470 // smart enough to convert the result into a TEST/JMP sequence.
4471 SDValue Op0 = N1.getOperand(0);
4472 SDValue Op1 = N1.getOperand(1);
4474 if (Op0.getOpcode() == ISD::AND &&
4476 Op1.getOpcode() == ISD::Constant) {
4477 SDValue AndOp0 = Op0.getOperand(0);
4478 SDValue AndOp1 = Op0.getOperand(1);
4480 if (AndOp1.getOpcode() == ISD::Constant) {
4481 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
4483 if (AndConst.isPowerOf2() &&
4484 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
4486 DAG.getSetCC(N->getDebugLoc(),
4487 TLI.getSetCCResultType(Op0.getValueType()),
4488 Op0, DAG.getConstant(0, Op0.getValueType()),
4491 // Replace the uses of SRL with SETCC
4492 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
4493 removeFromWorkList(N1.getNode());
4494 DAG.DeleteNode(N1.getNode());
4495 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
4496 MVT::Other, Chain, SetCC, N2);
4505 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
4507 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
4508 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
4509 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
4511 // Use SimplifySetCC to simplify SETCC's.
4512 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
4513 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
4515 if (Simp.getNode()) AddToWorkList(Simp.getNode());
4517 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode());
4519 // fold br_cc true, dest -> br dest (unconditional branch)
4520 if (SCCC && !SCCC->isNullValue())
4521 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other,
4522 N->getOperand(0), N->getOperand(4));
4523 // fold br_cc false, dest -> unconditional fall through
4524 if (SCCC && SCCC->isNullValue())
4525 return N->getOperand(0);
4527 // fold to a simpler setcc
4528 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
4529 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4530 N->getOperand(0), Simp.getOperand(2),
4531 Simp.getOperand(0), Simp.getOperand(1),
4537 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
4538 /// pre-indexed load / store when the base pointer is an add or subtract
4539 /// and it has other uses besides the load / store. After the
4540 /// transformation, the new indexed load / store has effectively folded
4541 /// the add / subtract in and all of its other uses are redirected to the
4542 /// new load / store.
4543 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
4544 if (!LegalOperations)
4550 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4551 if (LD->isIndexed())
4553 VT = LD->getMemoryVT();
4554 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
4555 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
4557 Ptr = LD->getBasePtr();
4558 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4559 if (ST->isIndexed())
4561 VT = ST->getMemoryVT();
4562 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
4563 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
4565 Ptr = ST->getBasePtr();
4571 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
4572 // out. There is no reason to make this a preinc/predec.
4573 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
4574 Ptr.getNode()->hasOneUse())
4577 // Ask the target to do addressing mode selection.
4580 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4581 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
4583 // Don't create a indexed load / store with zero offset.
4584 if (isa<ConstantSDNode>(Offset) &&
4585 cast<ConstantSDNode>(Offset)->isNullValue())
4588 // Try turning it into a pre-indexed load / store except when:
4589 // 1) The new base ptr is a frame index.
4590 // 2) If N is a store and the new base ptr is either the same as or is a
4591 // predecessor of the value being stored.
4592 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
4593 // that would create a cycle.
4594 // 4) All uses are load / store ops that use it as old base ptr.
4596 // Check #1. Preinc'ing a frame index would require copying the stack pointer
4597 // (plus the implicit offset) to a register to preinc anyway.
4598 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
4603 SDValue Val = cast<StoreSDNode>(N)->getValue();
4604 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
4608 // Now check for #3 and #4.
4609 bool RealUse = false;
4610 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4611 E = Ptr.getNode()->use_end(); I != E; ++I) {
4615 if (Use->isPredecessorOf(N))
4618 if (!((Use->getOpcode() == ISD::LOAD &&
4619 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
4620 (Use->getOpcode() == ISD::STORE &&
4621 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
4630 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
4631 BasePtr, Offset, AM);
4633 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
4634 BasePtr, Offset, AM);
4637 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
4638 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
4640 WorkListRemover DeadNodes(*this);
4642 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4644 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4647 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4651 // Finally, since the node is now dead, remove it from the graph.
4654 // Replace the uses of Ptr with uses of the updated base value.
4655 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
4657 removeFromWorkList(Ptr.getNode());
4658 DAG.DeleteNode(Ptr.getNode());
4663 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
4664 /// add / sub of the base pointer node into a post-indexed load / store.
4665 /// The transformation folded the add / subtract into the new indexed
4666 /// load / store effectively and all of its uses are redirected to the
4667 /// new load / store.
4668 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
4669 if (!LegalOperations)
4675 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4676 if (LD->isIndexed())
4678 VT = LD->getMemoryVT();
4679 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
4680 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
4682 Ptr = LD->getBasePtr();
4683 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4684 if (ST->isIndexed())
4686 VT = ST->getMemoryVT();
4687 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
4688 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
4690 Ptr = ST->getBasePtr();
4696 if (Ptr.getNode()->hasOneUse())
4699 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4700 E = Ptr.getNode()->use_end(); I != E; ++I) {
4703 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
4708 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4709 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
4711 std::swap(BasePtr, Offset);
4714 // Don't create a indexed load / store with zero offset.
4715 if (isa<ConstantSDNode>(Offset) &&
4716 cast<ConstantSDNode>(Offset)->isNullValue())
4719 // Try turning it into a post-indexed load / store except when
4720 // 1) All uses are load / store ops that use it as base ptr.
4721 // 2) Op must be independent of N, i.e. Op is neither a predecessor
4722 // nor a successor of N. Otherwise, if Op is folded that would
4725 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
4729 bool TryNext = false;
4730 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
4731 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
4733 if (Use == Ptr.getNode())
4736 // If all the uses are load / store addresses, then don't do the
4738 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
4739 bool RealUse = false;
4740 for (SDNode::use_iterator III = Use->use_begin(),
4741 EEE = Use->use_end(); III != EEE; ++III) {
4742 SDNode *UseUse = *III;
4743 if (!((UseUse->getOpcode() == ISD::LOAD &&
4744 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
4745 (UseUse->getOpcode() == ISD::STORE &&
4746 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
4761 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
4762 SDValue Result = isLoad
4763 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
4764 BasePtr, Offset, AM)
4765 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
4766 BasePtr, Offset, AM);
4769 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
4770 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
4772 WorkListRemover DeadNodes(*this);
4774 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4776 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4779 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4783 // Finally, since the node is now dead, remove it from the graph.
4786 // Replace the uses of Use with uses of the updated base value.
4787 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
4788 Result.getValue(isLoad ? 1 : 0),
4790 removeFromWorkList(Op);
4800 /// InferAlignment - If we can infer some alignment information from this
4801 /// pointer, return it.
4802 static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) {
4803 // If this is a direct reference to a stack slot, use information about the
4804 // stack slot's alignment.
4805 int FrameIdx = 1 << 31;
4806 int64_t FrameOffset = 0;
4807 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) {
4808 FrameIdx = FI->getIndex();
4809 } else if (Ptr.getOpcode() == ISD::ADD &&
4810 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4811 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4812 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4813 FrameOffset = Ptr.getConstantOperandVal(1);
4816 if (FrameIdx != (1 << 31)) {
4817 // FIXME: Handle FI+CST.
4818 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
4819 if (MFI.isFixedObjectIndex(FrameIdx)) {
4820 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset;
4822 // The alignment of the frame index can be determined from its offset from
4823 // the incoming frame position. If the frame object is at offset 32 and
4824 // the stack is guaranteed to be 16-byte aligned, then we know that the
4825 // object is 16-byte aligned.
4826 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment();
4827 unsigned Align = MinAlign(ObjectOffset, StackAlign);
4829 // Finally, the frame object itself may have a known alignment. Factor
4830 // the alignment + offset into a new alignment. For example, if we know
4831 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a
4832 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte
4833 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc.
4834 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx),
4836 return std::max(Align, FIInfoAlign);
4843 SDValue DAGCombiner::visitLOAD(SDNode *N) {
4844 LoadSDNode *LD = cast<LoadSDNode>(N);
4845 SDValue Chain = LD->getChain();
4846 SDValue Ptr = LD->getBasePtr();
4848 // Try to infer better alignment information than the load already has.
4849 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
4850 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4851 if (Align > LD->getAlignment())
4852 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
4853 LD->getValueType(0),
4854 Chain, Ptr, LD->getSrcValue(),
4855 LD->getSrcValueOffset(), LD->getMemoryVT(),
4856 LD->isVolatile(), Align);
4860 // If load is not volatile and there are no uses of the loaded value (and
4861 // the updated indexed value in case of indexed loads), change uses of the
4862 // chain value into uses of the chain input (i.e. delete the dead load).
4863 if (!LD->isVolatile()) {
4864 if (N->getValueType(1) == MVT::Other) {
4866 if (N->hasNUsesOfValue(0, 0)) {
4867 // It's not safe to use the two value CombineTo variant here. e.g.
4868 // v1, chain2 = load chain1, loc
4869 // v2, chain3 = load chain2, loc
4871 // Now we replace use of chain2 with chain1. This makes the second load
4872 // isomorphic to the one we are deleting, and thus makes this load live.
4873 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4874 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG));
4876 WorkListRemover DeadNodes(*this);
4877 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
4879 if (N->use_empty()) {
4880 removeFromWorkList(N);
4884 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4888 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
4889 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
4890 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
4891 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4892 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG));
4893 DOUT << " and 2 other values\n";
4894 WorkListRemover DeadNodes(*this);
4895 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
4896 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
4897 DAG.getUNDEF(N->getValueType(1)),
4899 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
4900 removeFromWorkList(N);
4902 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4907 // If this load is directly stored, replace the load value with the stored
4909 // TODO: Handle store large -> read small portion.
4910 // TODO: Handle TRUNCSTORE/LOADEXT
4911 if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
4912 !LD->isVolatile()) {
4913 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
4914 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
4915 if (PrevST->getBasePtr() == Ptr &&
4916 PrevST->getValue().getValueType() == N->getValueType(0))
4917 return CombineTo(N, Chain.getOperand(1), Chain);
4922 // Walk up chain skipping non-aliasing memory nodes.
4923 SDValue BetterChain = FindBetterChain(N, Chain);
4925 // If there is a better chain.
4926 if (Chain != BetterChain) {
4929 // Replace the chain to void dependency.
4930 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4931 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
4933 LD->getSrcValue(), LD->getSrcValueOffset(),
4934 LD->isVolatile(), LD->getAlignment());
4936 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
4937 LD->getValueType(0),
4938 BetterChain, Ptr, LD->getSrcValue(),
4939 LD->getSrcValueOffset(),
4942 LD->getAlignment());
4945 // Create token factor to keep old chain connected.
4946 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
4947 MVT::Other, Chain, ReplLoad.getValue(1));
4949 // Replace uses with load result and token factor. Don't add users
4951 return CombineTo(N, ReplLoad.getValue(0), Token, false);
4955 // Try transforming N to an indexed load.
4956 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4957 return SDValue(N, 0);
4963 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
4964 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
4965 /// of the loaded bits, try narrowing the load and store if it would end up
4966 /// being a win for performance or code size.
4967 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
4968 StoreSDNode *ST = cast<StoreSDNode>(N);
4969 if (ST->isVolatile())
4972 SDValue Chain = ST->getChain();
4973 SDValue Value = ST->getValue();
4974 SDValue Ptr = ST->getBasePtr();
4975 EVT VT = Value.getValueType();
4977 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
4980 unsigned Opc = Value.getOpcode();
4981 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
4982 Value.getOperand(1).getOpcode() != ISD::Constant)
4985 SDValue N0 = Value.getOperand(0);
4986 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) {
4987 LoadSDNode *LD = cast<LoadSDNode>(N0);
4988 if (LD->getBasePtr() != Ptr)
4991 // Find the type to narrow it the load / op / store to.
4992 SDValue N1 = Value.getOperand(1);
4993 unsigned BitWidth = N1.getValueSizeInBits();
4994 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
4995 if (Opc == ISD::AND)
4996 Imm ^= APInt::getAllOnesValue(BitWidth);
4997 if (Imm == 0 || Imm.isAllOnesValue())
4999 unsigned ShAmt = Imm.countTrailingZeros();
5000 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
5001 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
5002 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5003 while (NewBW < BitWidth &&
5004 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
5005 TLI.isNarrowingProfitable(VT, NewVT))) {
5006 NewBW = NextPowerOf2(NewBW);
5007 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5009 if (NewBW >= BitWidth)
5012 // If the lsb changed does not start at the type bitwidth boundary,
5013 // start at the previous one.
5015 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
5016 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
5017 if ((Imm & Mask) == Imm) {
5018 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
5019 if (Opc == ISD::AND)
5020 NewImm ^= APInt::getAllOnesValue(NewBW);
5021 uint64_t PtrOff = ShAmt / 8;
5022 // For big endian targets, we need to adjust the offset to the pointer to
5023 // load the correct bytes.
5024 if (TLI.isBigEndian())
5025 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
5027 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
5029 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForEVT(*DAG.getContext())))
5032 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
5033 Ptr.getValueType(), Ptr,
5034 DAG.getConstant(PtrOff, Ptr.getValueType()));
5035 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
5036 LD->getChain(), NewPtr,
5037 LD->getSrcValue(), LD->getSrcValueOffset(),
5038 LD->isVolatile(), NewAlign);
5039 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
5040 DAG.getConstant(NewImm, NewVT));
5041 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
5043 ST->getSrcValue(), ST->getSrcValueOffset(),
5046 AddToWorkList(NewPtr.getNode());
5047 AddToWorkList(NewLD.getNode());
5048 AddToWorkList(NewVal.getNode());
5049 WorkListRemover DeadNodes(*this);
5050 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
5060 SDValue DAGCombiner::visitSTORE(SDNode *N) {
5061 StoreSDNode *ST = cast<StoreSDNode>(N);
5062 SDValue Chain = ST->getChain();
5063 SDValue Value = ST->getValue();
5064 SDValue Ptr = ST->getBasePtr();
5066 // Try to infer better alignment information than the store already has.
5067 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
5068 if (unsigned Align = InferAlignment(Ptr, DAG)) {
5069 if (Align > ST->getAlignment())
5070 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
5071 Ptr, ST->getSrcValue(),
5072 ST->getSrcValueOffset(), ST->getMemoryVT(),
5073 ST->isVolatile(), Align);
5077 // If this is a store of a bit convert, store the input value if the
5078 // resultant store does not need a higher alignment than the original.
5079 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
5080 ST->isUnindexed()) {
5081 unsigned OrigAlign = ST->getAlignment();
5082 EVT SVT = Value.getOperand(0).getValueType();
5083 unsigned Align = TLI.getTargetData()->
5084 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
5085 if (Align <= OrigAlign &&
5086 ((!LegalOperations && !ST->isVolatile()) ||
5087 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
5088 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5089 Ptr, ST->getSrcValue(),
5090 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign);
5093 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
5094 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
5095 // NOTE: If the original store is volatile, this transform must not increase
5096 // the number of stores. For example, on x86-32 an f64 can be stored in one
5097 // processor operation but an i64 (which is not legal) requires two. So the
5098 // transform should not be done in this case.
5099 if (Value.getOpcode() != ISD::TargetConstantFP) {
5101 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
5102 default: llvm_unreachable("Unknown FP type");
5103 case MVT::f80: // We don't do this for these yet.
5108 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations &&
5109 !ST->isVolatile()) ||
5110 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5111 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
5112 bitcastToAPInt().getZExtValue(), MVT::i32);
5113 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5114 Ptr, ST->getSrcValue(),
5115 ST->getSrcValueOffset(), ST->isVolatile(),
5116 ST->getAlignment());
5120 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations &&
5121 !ST->isVolatile()) ||
5122 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
5123 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
5124 getZExtValue(), MVT::i64);
5125 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5126 Ptr, ST->getSrcValue(),
5127 ST->getSrcValueOffset(), ST->isVolatile(),
5128 ST->getAlignment());
5129 } else if (!ST->isVolatile() &&
5130 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5131 // Many FP stores are not made apparent until after legalize, e.g. for
5132 // argument passing. Since this is so common, custom legalize the
5133 // 64-bit integer store into two 32-bit stores.
5134 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
5135 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
5136 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
5137 if (TLI.isBigEndian()) std::swap(Lo, Hi);
5139 int SVOffset = ST->getSrcValueOffset();
5140 unsigned Alignment = ST->getAlignment();
5141 bool isVolatile = ST->isVolatile();
5143 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
5144 Ptr, ST->getSrcValue(),
5145 ST->getSrcValueOffset(),
5146 isVolatile, ST->getAlignment());
5147 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
5148 DAG.getConstant(4, Ptr.getValueType()));
5150 Alignment = MinAlign(Alignment, 4U);
5151 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
5152 Ptr, ST->getSrcValue(),
5153 SVOffset, isVolatile, Alignment);
5154 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
5164 // Walk up chain skipping non-aliasing memory nodes.
5165 SDValue BetterChain = FindBetterChain(N, Chain);
5167 // If there is a better chain.
5168 if (Chain != BetterChain) {
5169 // Replace the chain to avoid dependency.
5171 if (ST->isTruncatingStore()) {
5172 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5173 ST->getSrcValue(),ST->getSrcValueOffset(),
5175 ST->isVolatile(), ST->getAlignment());
5177 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5178 ST->getSrcValue(), ST->getSrcValueOffset(),
5179 ST->isVolatile(), ST->getAlignment());
5182 // Create token to keep both nodes around.
5183 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5184 MVT::Other, Chain, ReplStore);
5186 // Don't add users to work list.
5187 return CombineTo(N, Token, false);
5191 // Try transforming N to an indexed store.
5192 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5193 return SDValue(N, 0);
5195 // FIXME: is there such a thing as a truncating indexed store?
5196 if (ST->isTruncatingStore() && ST->isUnindexed() &&
5197 Value.getValueType().isInteger()) {
5198 // See if we can simplify the input to this truncstore with knowledge that
5199 // only the low bits are being used. For example:
5200 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
5202 GetDemandedBits(Value,
5203 APInt::getLowBitsSet(Value.getValueSizeInBits(),
5204 ST->getMemoryVT().getSizeInBits()));
5205 AddToWorkList(Value.getNode());
5206 if (Shorter.getNode())
5207 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
5208 Ptr, ST->getSrcValue(),
5209 ST->getSrcValueOffset(), ST->getMemoryVT(),
5210 ST->isVolatile(), ST->getAlignment());
5212 // Otherwise, see if we can simplify the operation with
5213 // SimplifyDemandedBits, which only works if the value has a single use.
5214 if (SimplifyDemandedBits(Value,
5215 APInt::getLowBitsSet(
5216 Value.getValueSizeInBits(),
5217 ST->getMemoryVT().getSizeInBits())))
5218 return SDValue(N, 0);
5221 // If this is a load followed by a store to the same location, then the store
5223 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
5224 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
5225 ST->isUnindexed() && !ST->isVolatile() &&
5226 // There can't be any side effects between the load and store, such as
5228 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
5229 // The store is dead, remove it.
5234 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
5235 // truncating store. We can do this even if this is already a truncstore.
5236 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
5237 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
5238 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
5239 ST->getMemoryVT())) {
5240 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5241 Ptr, ST->getSrcValue(),
5242 ST->getSrcValueOffset(), ST->getMemoryVT(),
5243 ST->isVolatile(), ST->getAlignment());
5246 return ReduceLoadOpStoreWidth(N);
5249 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
5250 SDValue InVec = N->getOperand(0);
5251 SDValue InVal = N->getOperand(1);
5252 SDValue EltNo = N->getOperand(2);
5254 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
5255 // vector with the inserted element.
5256 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
5257 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5258 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
5259 InVec.getNode()->op_end());
5260 if (Elt < Ops.size())
5262 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5263 InVec.getValueType(), &Ops[0], Ops.size());
5265 // If the invec is an UNDEF and if EltNo is a constant, create a new
5266 // BUILD_VECTOR with undef elements and the inserted element.
5267 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF &&
5268 isa<ConstantSDNode>(EltNo)) {
5269 EVT VT = InVec.getValueType();
5270 EVT EVT = VT.getVectorElementType();
5271 unsigned NElts = VT.getVectorNumElements();
5272 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT));
5274 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5275 if (Elt < Ops.size())
5277 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5278 InVec.getValueType(), &Ops[0], Ops.size());
5283 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
5284 // (vextract (scalar_to_vector val, 0) -> val
5285 SDValue InVec = N->getOperand(0);
5287 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5288 // If the operand is wider than the vector element type then it is implicitly
5289 // truncated. Make that explicit here.
5290 EVT EltVT = InVec.getValueType().getVectorElementType();
5291 SDValue InOp = InVec.getOperand(0);
5292 if (InOp.getValueType() != EltVT)
5293 return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp);
5297 // Perform only after legalization to ensure build_vector / vector_shuffle
5298 // optimizations have already been done.
5299 if (!LegalOperations) return SDValue();
5301 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
5302 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
5303 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
5304 SDValue EltNo = N->getOperand(1);
5306 if (isa<ConstantSDNode>(EltNo)) {
5307 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5308 bool NewLoad = false;
5309 bool BCNumEltsChanged = false;
5310 EVT VT = InVec.getValueType();
5311 EVT ExtVT = VT.getVectorElementType();
5314 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
5315 EVT BCVT = InVec.getOperand(0).getValueType();
5316 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
5318 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
5319 BCNumEltsChanged = true;
5320 InVec = InVec.getOperand(0);
5321 ExtVT = BCVT.getVectorElementType();
5325 LoadSDNode *LN0 = NULL;
5326 const ShuffleVectorSDNode *SVN = NULL;
5327 if (ISD::isNormalLoad(InVec.getNode())) {
5328 LN0 = cast<LoadSDNode>(InVec);
5329 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5330 InVec.getOperand(0).getValueType() == ExtVT &&
5331 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
5332 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
5333 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
5334 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
5336 // (load $addr+1*size)
5338 // If the bit convert changed the number of elements, it is unsafe
5339 // to examine the mask.
5340 if (BCNumEltsChanged)
5343 // Select the input vector, guarding against out of range extract vector.
5344 unsigned NumElems = VT.getVectorNumElements();
5345 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt);
5346 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
5348 if (InVec.getOpcode() == ISD::BIT_CONVERT)
5349 InVec = InVec.getOperand(0);
5350 if (ISD::isNormalLoad(InVec.getNode())) {
5351 LN0 = cast<LoadSDNode>(InVec);
5352 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems;
5356 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
5359 unsigned Align = LN0->getAlignment();
5361 // Check the resultant load doesn't need a higher alignment than the
5364 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
5366 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
5372 SDValue NewPtr = LN0->getBasePtr();
5374 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
5375 EVT PtrType = NewPtr.getValueType();
5376 if (TLI.isBigEndian())
5377 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
5378 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
5379 DAG.getConstant(PtrOff, PtrType));
5382 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
5383 LN0->getSrcValue(), LN0->getSrcValueOffset(),
5384 LN0->isVolatile(), Align);
5390 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
5391 unsigned NumInScalars = N->getNumOperands();
5392 EVT VT = N->getValueType(0);
5393 EVT EltType = VT.getVectorElementType();
5395 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
5396 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
5397 // at most two distinct vectors, turn this into a shuffle node.
5398 SDValue VecIn1, VecIn2;
5399 for (unsigned i = 0; i != NumInScalars; ++i) {
5400 // Ignore undef inputs.
5401 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5403 // If this input is something other than a EXTRACT_VECTOR_ELT with a
5404 // constant index, bail out.
5405 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5406 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
5407 VecIn1 = VecIn2 = SDValue(0, 0);
5411 // If the input vector type disagrees with the result of the build_vector,
5412 // we can't make a shuffle.
5413 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
5414 if (ExtractedFromVec.getValueType() != VT) {
5415 VecIn1 = VecIn2 = SDValue(0, 0);
5419 // Otherwise, remember this. We allow up to two distinct input vectors.
5420 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
5423 if (VecIn1.getNode() == 0) {
5424 VecIn1 = ExtractedFromVec;
5425 } else if (VecIn2.getNode() == 0) {
5426 VecIn2 = ExtractedFromVec;
5429 VecIn1 = VecIn2 = SDValue(0, 0);
5434 // If everything is good, we can make a shuffle operation.
5435 if (VecIn1.getNode()) {
5436 SmallVector<int, 8> Mask;
5437 for (unsigned i = 0; i != NumInScalars; ++i) {
5438 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
5443 // If extracting from the first vector, just use the index directly.
5444 SDValue Extract = N->getOperand(i);
5445 SDValue ExtVal = Extract.getOperand(1);
5446 if (Extract.getOperand(0) == VecIn1) {
5447 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
5448 if (ExtIndex > VT.getVectorNumElements())
5451 Mask.push_back(ExtIndex);
5455 // Otherwise, use InIdx + VecSize
5456 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
5457 Mask.push_back(Idx+NumInScalars);
5460 // Add count and size info.
5461 if (!TLI.isTypeLegal(VT) && LegalTypes)
5464 // Return the new VECTOR_SHUFFLE node.
5467 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5468 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
5474 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
5475 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
5476 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
5477 // inputs come from at most two distinct vectors, turn this into a shuffle
5480 // If we only have one input vector, we don't need to do any concatenation.
5481 if (N->getNumOperands() == 1)
5482 return N->getOperand(0);
5487 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
5490 EVT VT = N->getValueType(0);
5491 unsigned NumElts = VT.getVectorNumElements();
5493 SDValue N0 = N->getOperand(0);
5494 SDValue N1 = N->getOperand(1);
5496 assert(N0.getValueType().getVectorNumElements() == NumElts &&
5497 "Vector shuffle must be normalized in DAG");
5499 // FIXME: implement canonicalizations from DAG.getVectorShuffle()
5501 // If it is a splat, check if the argument vector is a build_vector with
5502 // all scalar elements the same.
5503 if (cast<ShuffleVectorSDNode>(N)->isSplat()) {
5504 SDNode *V = N0.getNode();
5507 // If this is a bit convert that changes the element type of the vector but
5508 // not the number of vector elements, look through it. Be careful not to
5509 // look though conversions that change things like v4f32 to v2f64.
5510 if (V->getOpcode() == ISD::BIT_CONVERT) {
5511 SDValue ConvInput = V->getOperand(0);
5512 if (ConvInput.getValueType().isVector() &&
5513 ConvInput.getValueType().getVectorNumElements() == NumElts)
5514 V = ConvInput.getNode();
5517 if (V->getOpcode() == ISD::BUILD_VECTOR) {
5518 unsigned NumElems = V->getNumOperands();
5519 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex();
5520 if (NumElems > BaseIdx) {
5522 bool AllSame = true;
5523 for (unsigned i = 0; i != NumElems; ++i) {
5524 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
5525 Base = V->getOperand(i);
5529 // Splat of <u, u, u, u>, return <u, u, u, u>
5530 if (!Base.getNode())
5532 for (unsigned i = 0; i != NumElems; ++i) {
5533 if (V->getOperand(i) != Base) {
5538 // Splat of <x, x, x, x>, return <x, x, x, x>
5547 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
5548 /// an AND to a vector_shuffle with the destination vector and a zero vector.
5549 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
5550 /// vector_shuffle V, Zero, <0, 4, 2, 4>
5551 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
5552 EVT VT = N->getValueType(0);
5553 DebugLoc dl = N->getDebugLoc();
5554 SDValue LHS = N->getOperand(0);
5555 SDValue RHS = N->getOperand(1);
5556 if (N->getOpcode() == ISD::AND) {
5557 if (RHS.getOpcode() == ISD::BIT_CONVERT)
5558 RHS = RHS.getOperand(0);
5559 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
5560 SmallVector<int, 8> Indices;
5561 unsigned NumElts = RHS.getNumOperands();
5562 for (unsigned i = 0; i != NumElts; ++i) {
5563 SDValue Elt = RHS.getOperand(i);
5564 if (!isa<ConstantSDNode>(Elt))
5566 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
5567 Indices.push_back(i);
5568 else if (cast<ConstantSDNode>(Elt)->isNullValue())
5569 Indices.push_back(NumElts);
5574 // Let's see if the target supports this vector_shuffle.
5575 EVT RVT = RHS.getValueType();
5576 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
5579 // Return the new VECTOR_SHUFFLE node.
5580 EVT EVT = RVT.getVectorElementType();
5581 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
5582 DAG.getConstant(0, EVT));
5583 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5584 RVT, &ZeroOps[0], ZeroOps.size());
5585 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS);
5586 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
5587 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf);
5594 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
5595 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
5596 // After legalize, the target may be depending on adds and other
5597 // binary ops to provide legal ways to construct constants or other
5598 // things. Simplifying them may result in a loss of legality.
5599 if (LegalOperations) return SDValue();
5601 EVT VT = N->getValueType(0);
5602 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
5604 EVT EltType = VT.getVectorElementType();
5605 SDValue LHS = N->getOperand(0);
5606 SDValue RHS = N->getOperand(1);
5607 SDValue Shuffle = XformToShuffleWithZero(N);
5608 if (Shuffle.getNode()) return Shuffle;
5610 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
5612 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
5613 RHS.getOpcode() == ISD::BUILD_VECTOR) {
5614 SmallVector<SDValue, 8> Ops;
5615 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
5616 SDValue LHSOp = LHS.getOperand(i);
5617 SDValue RHSOp = RHS.getOperand(i);
5618 // If these two elements can't be folded, bail out.
5619 if ((LHSOp.getOpcode() != ISD::UNDEF &&
5620 LHSOp.getOpcode() != ISD::Constant &&
5621 LHSOp.getOpcode() != ISD::ConstantFP) ||
5622 (RHSOp.getOpcode() != ISD::UNDEF &&
5623 RHSOp.getOpcode() != ISD::Constant &&
5624 RHSOp.getOpcode() != ISD::ConstantFP))
5627 // Can't fold divide by zero.
5628 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
5629 N->getOpcode() == ISD::FDIV) {
5630 if ((RHSOp.getOpcode() == ISD::Constant &&
5631 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
5632 (RHSOp.getOpcode() == ISD::ConstantFP &&
5633 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
5637 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(),
5638 EltType, LHSOp, RHSOp));
5639 AddToWorkList(Ops.back().getNode());
5640 assert((Ops.back().getOpcode() == ISD::UNDEF ||
5641 Ops.back().getOpcode() == ISD::Constant ||
5642 Ops.back().getOpcode() == ISD::ConstantFP) &&
5643 "Scalar binop didn't fold!");
5646 if (Ops.size() == LHS.getNumOperands()) {
5647 EVT VT = LHS.getValueType();
5648 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
5649 &Ops[0], Ops.size());
5656 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
5657 SDValue N1, SDValue N2){
5658 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
5660 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
5661 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5663 // If we got a simplified select_cc node back from SimplifySelectCC, then
5664 // break it down into a new SETCC node, and a new SELECT node, and then return
5665 // the SELECT node, since we were called with a SELECT node.
5666 if (SCC.getNode()) {
5667 // Check to see if we got a select_cc back (to turn into setcc/select).
5668 // Otherwise, just return whatever node we got back, like fabs.
5669 if (SCC.getOpcode() == ISD::SELECT_CC) {
5670 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
5672 SCC.getOperand(0), SCC.getOperand(1),
5674 AddToWorkList(SETCC.getNode());
5675 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
5676 SCC.getOperand(2), SCC.getOperand(3), SETCC);
5684 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
5685 /// are the two values being selected between, see if we can simplify the
5686 /// select. Callers of this should assume that TheSelect is deleted if this
5687 /// returns true. As such, they should return the appropriate thing (e.g. the
5688 /// node) back to the top-level of the DAG combiner loop to avoid it being
5690 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
5693 // If this is a select from two identical things, try to pull the operation
5694 // through the select.
5695 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
5696 // If this is a load and the token chain is identical, replace the select
5697 // of two loads with a load through a select of the address to load from.
5698 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
5699 // constants have been dropped into the constant pool.
5700 if (LHS.getOpcode() == ISD::LOAD &&
5701 // Do not let this transformation reduce the number of volatile loads.
5702 !cast<LoadSDNode>(LHS)->isVolatile() &&
5703 !cast<LoadSDNode>(RHS)->isVolatile() &&
5704 // Token chains must be identical.
5705 LHS.getOperand(0) == RHS.getOperand(0)) {
5706 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
5707 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
5709 // If this is an EXTLOAD, the VT's must match.
5710 if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
5711 // FIXME: this conflates two src values, discarding one. This is not
5712 // the right thing to do, but nothing uses srcvalues now. When they do,
5713 // turn SrcValue into a list of locations.
5715 if (TheSelect->getOpcode() == ISD::SELECT) {
5716 // Check that the condition doesn't reach either load. If so, folding
5717 // this will induce a cycle into the DAG.
5718 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5719 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) {
5720 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
5721 LLD->getBasePtr().getValueType(),
5722 TheSelect->getOperand(0), LLD->getBasePtr(),
5726 // Check that the condition doesn't reach either load. If so, folding
5727 // this will induce a cycle into the DAG.
5728 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5729 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5730 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) &&
5731 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) {
5732 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
5733 LLD->getBasePtr().getValueType(),
5734 TheSelect->getOperand(0),
5735 TheSelect->getOperand(1),
5736 LLD->getBasePtr(), RLD->getBasePtr(),
5737 TheSelect->getOperand(4));
5741 if (Addr.getNode()) {
5743 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
5744 Load = DAG.getLoad(TheSelect->getValueType(0),
5745 TheSelect->getDebugLoc(),
5747 Addr,LLD->getSrcValue(),
5748 LLD->getSrcValueOffset(),
5750 LLD->getAlignment());
5752 Load = DAG.getExtLoad(LLD->getExtensionType(),
5753 TheSelect->getDebugLoc(),
5754 TheSelect->getValueType(0),
5755 LLD->getChain(), Addr, LLD->getSrcValue(),
5756 LLD->getSrcValueOffset(),
5759 LLD->getAlignment());
5762 // Users of the select now use the result of the load.
5763 CombineTo(TheSelect, Load);
5765 // Users of the old loads now use the new load's chain. We know the
5766 // old-load value is dead now.
5767 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
5768 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
5778 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
5779 /// where 'cond' is the comparison specified by CC.
5780 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
5781 SDValue N2, SDValue N3,
5782 ISD::CondCode CC, bool NotExtCompare) {
5783 // (x ? y : y) -> y.
5784 if (N2 == N3) return N2;
5786 EVT VT = N2.getValueType();
5787 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
5788 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
5789 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
5791 // Determine if the condition we're dealing with is constant
5792 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
5793 N0, N1, CC, DL, false);
5794 if (SCC.getNode()) AddToWorkList(SCC.getNode());
5795 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
5797 // fold select_cc true, x, y -> x
5798 if (SCCC && !SCCC->isNullValue())
5800 // fold select_cc false, x, y -> y
5801 if (SCCC && SCCC->isNullValue())
5804 // Check to see if we can simplify the select into an fabs node
5805 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
5806 // Allow either -0.0 or 0.0
5807 if (CFP->getValueAPF().isZero()) {
5808 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
5809 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
5810 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
5811 N2 == N3.getOperand(0))
5812 return DAG.getNode(ISD::FABS, DL, VT, N0);
5814 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
5815 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
5816 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
5817 N2.getOperand(0) == N3)
5818 return DAG.getNode(ISD::FABS, DL, VT, N3);
5822 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
5823 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
5824 // in it. This is a win when the constant is not otherwise available because
5825 // it replaces two constant pool loads with one. We only do this if the FP
5826 // type is known to be legal, because if it isn't, then we are before legalize
5827 // types an we want the other legalization to happen first (e.g. to avoid
5828 // messing with soft float) and if the ConstantFP is not legal, because if
5829 // it is legal, we may not need to store the FP constant in a constant pool.
5830 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
5831 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
5832 if (TLI.isTypeLegal(N2.getValueType()) &&
5833 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
5834 TargetLowering::Legal) &&
5835 // If both constants have multiple uses, then we won't need to do an
5836 // extra load, they are likely around in registers for other users.
5837 (TV->hasOneUse() || FV->hasOneUse())) {
5838 Constant *Elts[] = {
5839 const_cast<ConstantFP*>(FV->getConstantFPValue()),
5840 const_cast<ConstantFP*>(TV->getConstantFPValue())
5842 const Type *FPTy = Elts[0]->getType();
5843 const TargetData &TD = *TLI.getTargetData();
5845 // Create a ConstantArray of the two constants.
5846 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2);
5847 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
5848 TD.getPrefTypeAlignment(FPTy));
5849 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5851 // Get the offsets to the 0 and 1 element of the array so that we can
5852 // select between them.
5853 SDValue Zero = DAG.getIntPtrConstant(0);
5854 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
5855 SDValue One = DAG.getIntPtrConstant(EltSize);
5857 SDValue Cond = DAG.getSetCC(DL,
5858 TLI.getSetCCResultType(N0.getValueType()),
5860 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
5862 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
5864 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
5865 PseudoSourceValue::getConstantPool(), 0, false,
5871 // Check to see if we can perform the "gzip trick", transforming
5872 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
5873 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
5874 N0.getValueType().isInteger() &&
5875 N2.getValueType().isInteger() &&
5876 (N1C->isNullValue() || // (a < 0) ? b : 0
5877 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
5878 EVT XType = N0.getValueType();
5879 EVT AType = N2.getValueType();
5880 if (XType.bitsGE(AType)) {
5881 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
5882 // single-bit constant.
5883 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
5884 unsigned ShCtV = N2C->getAPIntValue().logBase2();
5885 ShCtV = XType.getSizeInBits()-ShCtV-1;
5886 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy());
5887 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
5889 AddToWorkList(Shift.getNode());
5891 if (XType.bitsGT(AType)) {
5892 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
5893 AddToWorkList(Shift.getNode());
5896 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
5899 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
5901 DAG.getConstant(XType.getSizeInBits()-1,
5902 getShiftAmountTy()));
5903 AddToWorkList(Shift.getNode());
5905 if (XType.bitsGT(AType)) {
5906 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
5907 AddToWorkList(Shift.getNode());
5910 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
5914 // fold select C, 16, 0 -> shl C, 4
5915 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
5916 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
5918 // If the caller doesn't want us to simplify this into a zext of a compare,
5920 if (NotExtCompare && N2C->getAPIntValue() == 1)
5923 // Get a SetCC of the condition
5924 // FIXME: Should probably make sure that setcc is legal if we ever have a
5925 // target where it isn't.
5927 // cast from setcc result type to select result type
5929 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
5931 if (N2.getValueType().bitsLT(SCC.getValueType()))
5932 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
5934 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
5935 N2.getValueType(), SCC);
5937 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
5938 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
5939 N2.getValueType(), SCC);
5942 AddToWorkList(SCC.getNode());
5943 AddToWorkList(Temp.getNode());
5945 if (N2C->getAPIntValue() == 1)
5948 // shl setcc result by log2 n2c
5949 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
5950 DAG.getConstant(N2C->getAPIntValue().logBase2(),
5951 getShiftAmountTy()));
5954 // Check to see if this is the equivalent of setcc
5955 // FIXME: Turn all of these into setcc if setcc if setcc is legal
5956 // otherwise, go ahead with the folds.
5957 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
5958 EVT XType = N0.getValueType();
5959 if (!LegalOperations ||
5960 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
5961 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
5962 if (Res.getValueType() != VT)
5963 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
5967 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
5968 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
5969 (!LegalOperations ||
5970 TLI.isOperationLegal(ISD::CTLZ, XType))) {
5971 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
5972 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
5973 DAG.getConstant(Log2_32(XType.getSizeInBits()),
5974 getShiftAmountTy()));
5976 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
5977 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
5978 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
5979 XType, DAG.getConstant(0, XType), N0);
5980 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
5981 return DAG.getNode(ISD::SRL, DL, XType,
5982 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
5983 DAG.getConstant(XType.getSizeInBits()-1,
5984 getShiftAmountTy()));
5986 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
5987 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
5988 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
5989 DAG.getConstant(XType.getSizeInBits()-1,
5990 getShiftAmountTy()));
5991 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
5995 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
5996 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5997 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
5998 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
5999 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
6000 EVT XType = N0.getValueType();
6001 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0,
6002 DAG.getConstant(XType.getSizeInBits()-1,
6003 getShiftAmountTy()));
6004 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType,
6006 AddToWorkList(Shift.getNode());
6007 AddToWorkList(Add.getNode());
6008 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
6010 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
6011 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
6012 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
6013 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
6014 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
6015 EVT XType = N0.getValueType();
6016 if (SubC->isNullValue() && XType.isInteger()) {
6017 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
6019 DAG.getConstant(XType.getSizeInBits()-1,
6020 getShiftAmountTy()));
6021 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
6023 AddToWorkList(Shift.getNode());
6024 AddToWorkList(Add.getNode());
6025 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
6033 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
6034 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
6035 SDValue N1, ISD::CondCode Cond,
6036 DebugLoc DL, bool foldBooleans) {
6037 TargetLowering::DAGCombinerInfo
6038 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
6039 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
6042 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
6043 /// return a DAG expression to select that will generate the same value by
6044 /// multiplying by a magic number. See:
6045 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6046 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
6047 std::vector<SDNode*> Built;
6048 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
6050 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6056 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
6057 /// return a DAG expression to select that will generate the same value by
6058 /// multiplying by a magic number. See:
6059 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6060 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
6061 std::vector<SDNode*> Built;
6062 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
6064 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6070 /// FindBaseOffset - Return true if base is known not to alias with anything
6071 /// but itself. Provides base object and offset as results.
6072 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) {
6073 // Assume it is a primitive operation.
6074 Base = Ptr; Offset = 0;
6076 // If it's an adding a simple constant then integrate the offset.
6077 if (Base.getOpcode() == ISD::ADD) {
6078 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
6079 Base = Base.getOperand(0);
6080 Offset += C->getZExtValue();
6084 // If it's any of the following then it can't alias with anything but itself.
6085 return isa<FrameIndexSDNode>(Base) ||
6086 isa<ConstantPoolSDNode>(Base) ||
6087 isa<GlobalAddressSDNode>(Base);
6090 /// isAlias - Return true if there is any possibility that the two addresses
6092 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
6093 const Value *SrcValue1, int SrcValueOffset1,
6094 SDValue Ptr2, int64_t Size2,
6095 const Value *SrcValue2, int SrcValueOffset2) const {
6096 // If they are the same then they must be aliases.
6097 if (Ptr1 == Ptr2) return true;
6099 // Gather base node and offset information.
6100 SDValue Base1, Base2;
6101 int64_t Offset1, Offset2;
6102 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
6103 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
6105 // If they have a same base address then...
6107 // Check to see if the addresses overlap.
6108 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
6110 // If we know both bases then they can't alias.
6111 if (KnownBase1 && KnownBase2) return false;
6113 if (CombinerGlobalAA) {
6114 // Use alias analysis information.
6115 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
6116 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
6117 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
6118 AliasAnalysis::AliasResult AAResult =
6119 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
6120 if (AAResult == AliasAnalysis::NoAlias)
6124 // Otherwise we have to assume they alias.
6128 /// FindAliasInfo - Extracts the relevant alias information from the memory
6129 /// node. Returns true if the operand was a load.
6130 bool DAGCombiner::FindAliasInfo(SDNode *N,
6131 SDValue &Ptr, int64_t &Size,
6132 const Value *&SrcValue, int &SrcValueOffset) const {
6133 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6134 Ptr = LD->getBasePtr();
6135 Size = LD->getMemoryVT().getSizeInBits() >> 3;
6136 SrcValue = LD->getSrcValue();
6137 SrcValueOffset = LD->getSrcValueOffset();
6139 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6140 Ptr = ST->getBasePtr();
6141 Size = ST->getMemoryVT().getSizeInBits() >> 3;
6142 SrcValue = ST->getSrcValue();
6143 SrcValueOffset = ST->getSrcValueOffset();
6145 llvm_unreachable("FindAliasInfo expected a memory operand");
6151 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
6152 /// looking for aliasing nodes and adding them to the Aliases vector.
6153 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
6154 SmallVector<SDValue, 8> &Aliases) {
6155 SmallVector<SDValue, 8> Chains; // List of chains to visit.
6156 std::set<SDNode *> Visited; // Visited node set.
6158 // Get alias information for node.
6161 const Value *SrcValue = 0;
6162 int SrcValueOffset = 0;
6163 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
6166 Chains.push_back(OriginalChain);
6168 // Look at each chain and determine if it is an alias. If so, add it to the
6169 // aliases list. If not, then continue up the chain looking for the next
6171 while (!Chains.empty()) {
6172 SDValue Chain = Chains.back();
6175 // Don't bother if we've been before.
6176 if (Visited.find(Chain.getNode()) != Visited.end()) continue;
6177 Visited.insert(Chain.getNode());
6179 switch (Chain.getOpcode()) {
6180 case ISD::EntryToken:
6181 // Entry token is ideal chain operand, but handled in FindBetterChain.
6186 // Get alias information for Chain.
6189 const Value *OpSrcValue = 0;
6190 int OpSrcValueOffset = 0;
6191 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
6192 OpSrcValue, OpSrcValueOffset);
6194 // If chain is alias then stop here.
6195 if (!(IsLoad && IsOpLoad) &&
6196 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
6197 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
6198 Aliases.push_back(Chain);
6200 // Look further up the chain.
6201 Chains.push_back(Chain.getOperand(0));
6202 // Clean up old chain.
6203 AddToWorkList(Chain.getNode());
6208 case ISD::TokenFactor:
6209 // We have to check each of the operands of the token factor, so we queue
6210 // then up. Adding the operands to the queue (stack) in reverse order
6211 // maintains the original order and increases the likelihood that getNode
6212 // will find a matching token factor (CSE.)
6213 for (unsigned n = Chain.getNumOperands(); n;)
6214 Chains.push_back(Chain.getOperand(--n));
6215 // Eliminate the token factor if we can.
6216 AddToWorkList(Chain.getNode());
6220 // For all other instructions we will just have to take what we can get.
6221 Aliases.push_back(Chain);
6227 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
6228 /// for a better chain (aliasing node.)
6229 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
6230 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
6232 // Accumulate all the aliases to this node.
6233 GatherAllAliases(N, OldChain, Aliases);
6235 if (Aliases.size() == 0) {
6236 // If no operands then chain to entry token.
6237 return DAG.getEntryNode();
6238 } else if (Aliases.size() == 1) {
6239 // If a single operand then chain to it. We don't need to revisit it.
6243 // Construct a custom tailored token factor.
6244 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6245 &Aliases[0], Aliases.size());
6247 // Make sure the old chain gets cleaned up.
6248 if (NewChain != OldChain) AddToWorkList(OldChain.getNode());
6253 // SelectionDAG::Combine - This is the entry point for the file.
6255 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
6256 CodeGenOpt::Level OptLevel) {
6257 /// run - This is the main entry point to this class.
6259 DAGCombiner(*this, AA, OptLevel).Run(Level);