1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
40 STATISTIC(NodesCombined , "Number of dag nodes combined");
41 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
42 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
43 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
44 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
48 CombinerAA("combiner-alias-analysis", cl::Hidden,
49 cl::desc("Turn on alias analysis during testing"));
52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
53 cl::desc("Include global information in alias analysis"));
55 //------------------------------ DAGCombiner ---------------------------------//
59 const TargetLowering &TLI;
61 CodeGenOpt::Level OptLevel;
65 // Worklist of all of the nodes that need to be simplified.
67 // This has the semantics that when adding to the worklist,
68 // the item added must be next to be processed. It should
69 // also only appear once. The naive approach to this takes
72 // To reduce the insert/remove time to logarithmic, we use
73 // a set and a vector to maintain our worklist.
75 // The set contains the items on the worklist, but does not
76 // maintain the order they should be visited.
78 // The vector maintains the order nodes should be visited, but may
79 // contain duplicate or removed nodes. When choosing a node to
80 // visit, we pop off the order stack until we find an item that is
81 // also in the contents set. All operations are O(log N).
82 SmallPtrSet<SDNode*, 64> WorkListContents;
83 SmallVector<SDNode*, 64> WorkListOrder;
85 // AA - Used for DAG load/store alias analysis.
88 /// AddUsersToWorkList - When an instruction is simplified, add all users of
89 /// the instruction to the work lists because they might get more simplified
92 void AddUsersToWorkList(SDNode *N) {
93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
98 /// visit - call the node-specific routine that knows how to fold each
99 /// particular type of node.
100 SDValue visit(SDNode *N);
103 /// AddToWorkList - Add to the work list making sure its instance is at the
104 /// back (next to be processed.)
105 void AddToWorkList(SDNode *N) {
106 WorkListContents.insert(N);
107 WorkListOrder.push_back(N);
110 /// removeFromWorkList - remove all instances of N from the worklist.
112 void removeFromWorkList(SDNode *N) {
113 WorkListContents.erase(N);
116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
120 return CombineTo(N, &Res, 1, AddTo);
123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
125 SDValue To[] = { Res0, Res1 };
126 return CombineTo(N, To, 2, AddTo);
129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
133 /// SimplifyDemandedBits - Check the specified integer node value to see if
134 /// it can be simplified or if things it uses can be simplified by bit
135 /// propagation. If so, return true.
136 bool SimplifyDemandedBits(SDValue Op) {
137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
138 APInt Demanded = APInt::getAllOnesValue(BitWidth);
139 return SimplifyDemandedBits(Op, Demanded);
142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
144 bool CombineToPreIndexedLoadStore(SDNode *N);
145 bool CombineToPostIndexedLoadStore(SDNode *N);
147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
151 SDValue PromoteIntBinOp(SDValue Op);
152 SDValue PromoteIntShiftOp(SDValue Op);
153 SDValue PromoteExtend(SDValue Op);
154 bool PromoteLoad(SDValue Op);
156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
158 ISD::NodeType ExtType);
160 /// combine - call the node-specific routine that knows how to fold each
161 /// particular type of node. If that doesn't do anything, try the
162 /// target-specific DAG combines.
163 SDValue combine(SDNode *N);
165 // Visitation implementation - Implement dag node combining for different
166 // node types. The semantics are as follows:
168 // SDValue.getNode() == 0 - No change was made
169 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
170 // otherwise - N should be replaced by the returned Operand.
172 SDValue visitTokenFactor(SDNode *N);
173 SDValue visitMERGE_VALUES(SDNode *N);
174 SDValue visitADD(SDNode *N);
175 SDValue visitSUB(SDNode *N);
176 SDValue visitADDC(SDNode *N);
177 SDValue visitSUBC(SDNode *N);
178 SDValue visitADDE(SDNode *N);
179 SDValue visitSUBE(SDNode *N);
180 SDValue visitMUL(SDNode *N);
181 SDValue visitSDIV(SDNode *N);
182 SDValue visitUDIV(SDNode *N);
183 SDValue visitSREM(SDNode *N);
184 SDValue visitUREM(SDNode *N);
185 SDValue visitMULHU(SDNode *N);
186 SDValue visitMULHS(SDNode *N);
187 SDValue visitSMUL_LOHI(SDNode *N);
188 SDValue visitUMUL_LOHI(SDNode *N);
189 SDValue visitSMULO(SDNode *N);
190 SDValue visitUMULO(SDNode *N);
191 SDValue visitSDIVREM(SDNode *N);
192 SDValue visitUDIVREM(SDNode *N);
193 SDValue visitAND(SDNode *N);
194 SDValue visitOR(SDNode *N);
195 SDValue visitXOR(SDNode *N);
196 SDValue SimplifyVBinOp(SDNode *N);
197 SDValue SimplifyVUnaryOp(SDNode *N);
198 SDValue visitSHL(SDNode *N);
199 SDValue visitSRA(SDNode *N);
200 SDValue visitSRL(SDNode *N);
201 SDValue visitCTLZ(SDNode *N);
202 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
203 SDValue visitCTTZ(SDNode *N);
204 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
205 SDValue visitCTPOP(SDNode *N);
206 SDValue visitSELECT(SDNode *N);
207 SDValue visitSELECT_CC(SDNode *N);
208 SDValue visitSETCC(SDNode *N);
209 SDValue visitSIGN_EXTEND(SDNode *N);
210 SDValue visitZERO_EXTEND(SDNode *N);
211 SDValue visitANY_EXTEND(SDNode *N);
212 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
213 SDValue visitTRUNCATE(SDNode *N);
214 SDValue visitBITCAST(SDNode *N);
215 SDValue visitBUILD_PAIR(SDNode *N);
216 SDValue visitFADD(SDNode *N);
217 SDValue visitFSUB(SDNode *N);
218 SDValue visitFMUL(SDNode *N);
219 SDValue visitFMA(SDNode *N);
220 SDValue visitFDIV(SDNode *N);
221 SDValue visitFREM(SDNode *N);
222 SDValue visitFCOPYSIGN(SDNode *N);
223 SDValue visitSINT_TO_FP(SDNode *N);
224 SDValue visitUINT_TO_FP(SDNode *N);
225 SDValue visitFP_TO_SINT(SDNode *N);
226 SDValue visitFP_TO_UINT(SDNode *N);
227 SDValue visitFP_ROUND(SDNode *N);
228 SDValue visitFP_ROUND_INREG(SDNode *N);
229 SDValue visitFP_EXTEND(SDNode *N);
230 SDValue visitFNEG(SDNode *N);
231 SDValue visitFABS(SDNode *N);
232 SDValue visitFCEIL(SDNode *N);
233 SDValue visitFTRUNC(SDNode *N);
234 SDValue visitFFLOOR(SDNode *N);
235 SDValue visitBRCOND(SDNode *N);
236 SDValue visitBR_CC(SDNode *N);
237 SDValue visitLOAD(SDNode *N);
238 SDValue visitSTORE(SDNode *N);
239 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
240 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
241 SDValue visitBUILD_VECTOR(SDNode *N);
242 SDValue visitCONCAT_VECTORS(SDNode *N);
243 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
244 SDValue visitVECTOR_SHUFFLE(SDNode *N);
245 SDValue visitMEMBARRIER(SDNode *N);
247 SDValue XformToShuffleWithZero(SDNode *N);
248 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
250 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
252 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
253 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
254 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
255 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
256 SDValue N3, ISD::CondCode CC,
257 bool NotExtCompare = false);
258 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
259 DebugLoc DL, bool foldBooleans = true);
260 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
262 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
263 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
264 SDValue BuildSDIV(SDNode *N);
265 SDValue BuildUDIV(SDNode *N);
266 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
267 bool DemandHighBits = true);
268 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
269 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
270 SDValue ReduceLoadWidth(SDNode *N);
271 SDValue ReduceLoadOpStoreWidth(SDNode *N);
272 SDValue TransformFPLoadStorePair(SDNode *N);
274 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
276 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
277 /// looking for aliasing nodes and adding them to the Aliases vector.
278 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
279 SmallVector<SDValue, 8> &Aliases);
281 /// isAlias - Return true if there is any possibility that the two addresses
283 bool isAlias(SDValue Ptr1, int64_t Size1,
284 const Value *SrcValue1, int SrcValueOffset1,
285 unsigned SrcValueAlign1,
286 const MDNode *TBAAInfo1,
287 SDValue Ptr2, int64_t Size2,
288 const Value *SrcValue2, int SrcValueOffset2,
289 unsigned SrcValueAlign2,
290 const MDNode *TBAAInfo2) const;
292 /// FindAliasInfo - Extracts the relevant alias information from the memory
293 /// node. Returns true if the operand was a load.
294 bool FindAliasInfo(SDNode *N,
295 SDValue &Ptr, int64_t &Size,
296 const Value *&SrcValue, int &SrcValueOffset,
297 unsigned &SrcValueAlignment,
298 const MDNode *&TBAAInfo) const;
300 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
301 /// looking for a better chain (aliasing node.)
302 SDValue FindBetterChain(SDNode *N, SDValue Chain);
305 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
306 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
307 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
309 /// Run - runs the dag combiner on all nodes in the work list
310 void Run(CombineLevel AtLevel);
312 SelectionDAG &getDAG() const { return DAG; }
314 /// getShiftAmountTy - Returns a type large enough to hold any valid
315 /// shift amount - before type legalization these can be huge.
316 EVT getShiftAmountTy(EVT LHSTy) {
317 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
320 /// isTypeLegal - This method returns true if we are running before type
321 /// legalization or if the specified VT is legal.
322 bool isTypeLegal(const EVT &VT) {
323 if (!LegalTypes) return true;
324 return TLI.isTypeLegal(VT);
331 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
332 /// nodes from the worklist.
333 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
336 explicit WorkListRemover(DAGCombiner &dc)
337 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
339 virtual void NodeDeleted(SDNode *N, SDNode *E) {
340 DC.removeFromWorkList(N);
345 //===----------------------------------------------------------------------===//
346 // TargetLowering::DAGCombinerInfo implementation
347 //===----------------------------------------------------------------------===//
349 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
350 ((DAGCombiner*)DC)->AddToWorkList(N);
353 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
354 ((DAGCombiner*)DC)->removeFromWorkList(N);
357 SDValue TargetLowering::DAGCombinerInfo::
358 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
359 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
362 SDValue TargetLowering::DAGCombinerInfo::
363 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
364 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
368 SDValue TargetLowering::DAGCombinerInfo::
369 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
370 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
373 void TargetLowering::DAGCombinerInfo::
374 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
375 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
378 //===----------------------------------------------------------------------===//
380 //===----------------------------------------------------------------------===//
382 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
383 /// specified expression for the same cost as the expression itself, or 2 if we
384 /// can compute the negated form more cheaply than the expression itself.
385 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
386 const TargetLowering &TLI,
387 const TargetOptions *Options,
388 unsigned Depth = 0) {
389 // No compile time optimizations on this type.
390 if (Op.getValueType() == MVT::ppcf128)
393 // fneg is removable even if it has multiple uses.
394 if (Op.getOpcode() == ISD::FNEG) return 2;
396 // Don't allow anything with multiple uses.
397 if (!Op.hasOneUse()) return 0;
399 // Don't recurse exponentially.
400 if (Depth > 6) return 0;
402 switch (Op.getOpcode()) {
403 default: return false;
404 case ISD::ConstantFP:
405 // Don't invert constant FP values after legalize. The negated constant
406 // isn't necessarily legal.
407 return LegalOperations ? 0 : 1;
409 // FIXME: determine better conditions for this xform.
410 if (!Options->UnsafeFPMath) return 0;
412 // After operation legalization, it might not be legal to create new FSUBs.
413 if (LegalOperations &&
414 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
417 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
418 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
421 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
422 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
425 // We can't turn -(A-B) into B-A when we honor signed zeros.
426 if (!Options->UnsafeFPMath) return 0;
428 // fold (fneg (fsub A, B)) -> (fsub B, A)
433 if (Options->HonorSignDependentRoundingFPMath()) return 0;
435 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
436 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
440 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
446 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
451 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
452 /// returns the newly negated expression.
453 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
454 bool LegalOperations, unsigned Depth = 0) {
455 // fneg is removable even if it has multiple uses.
456 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
458 // Don't allow anything with multiple uses.
459 assert(Op.hasOneUse() && "Unknown reuse!");
461 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
462 switch (Op.getOpcode()) {
463 default: llvm_unreachable("Unknown code");
464 case ISD::ConstantFP: {
465 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
467 return DAG.getConstantFP(V, Op.getValueType());
470 // FIXME: determine better conditions for this xform.
471 assert(DAG.getTarget().Options.UnsafeFPMath);
473 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
474 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
475 DAG.getTargetLoweringInfo(),
476 &DAG.getTarget().Options, Depth+1))
477 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
478 GetNegatedExpression(Op.getOperand(0), DAG,
479 LegalOperations, Depth+1),
481 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
482 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
483 GetNegatedExpression(Op.getOperand(1), DAG,
484 LegalOperations, Depth+1),
487 // We can't turn -(A-B) into B-A when we honor signed zeros.
488 assert(DAG.getTarget().Options.UnsafeFPMath);
490 // fold (fneg (fsub 0, B)) -> B
491 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
492 if (N0CFP->getValueAPF().isZero())
493 return Op.getOperand(1);
495 // fold (fneg (fsub A, B)) -> (fsub B, A)
496 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
497 Op.getOperand(1), Op.getOperand(0));
501 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath());
503 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
504 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
505 DAG.getTargetLoweringInfo(),
506 &DAG.getTarget().Options, Depth+1))
507 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
508 GetNegatedExpression(Op.getOperand(0), DAG,
509 LegalOperations, Depth+1),
512 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
513 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
515 GetNegatedExpression(Op.getOperand(1), DAG,
516 LegalOperations, Depth+1));
520 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
521 GetNegatedExpression(Op.getOperand(0), DAG,
522 LegalOperations, Depth+1));
524 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
525 GetNegatedExpression(Op.getOperand(0), DAG,
526 LegalOperations, Depth+1),
532 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
533 // that selects between the values 1 and 0, making it equivalent to a setcc.
534 // Also, set the incoming LHS, RHS, and CC references to the appropriate
535 // nodes based on the type of node we are checking. This simplifies life a
536 // bit for the callers.
537 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
539 if (N.getOpcode() == ISD::SETCC) {
540 LHS = N.getOperand(0);
541 RHS = N.getOperand(1);
542 CC = N.getOperand(2);
545 if (N.getOpcode() == ISD::SELECT_CC &&
546 N.getOperand(2).getOpcode() == ISD::Constant &&
547 N.getOperand(3).getOpcode() == ISD::Constant &&
548 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
549 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
550 LHS = N.getOperand(0);
551 RHS = N.getOperand(1);
552 CC = N.getOperand(4);
558 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
559 // one use. If this is true, it allows the users to invert the operation for
560 // free when it is profitable to do so.
561 static bool isOneUseSetCC(SDValue N) {
563 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
568 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
569 SDValue N0, SDValue N1) {
570 EVT VT = N0.getValueType();
571 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
572 if (isa<ConstantSDNode>(N1)) {
573 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
575 DAG.FoldConstantArithmetic(Opc, VT,
576 cast<ConstantSDNode>(N0.getOperand(1)),
577 cast<ConstantSDNode>(N1));
578 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
580 if (N0.hasOneUse()) {
581 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
582 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
583 N0.getOperand(0), N1);
584 AddToWorkList(OpNode.getNode());
585 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
589 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
590 if (isa<ConstantSDNode>(N0)) {
591 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
593 DAG.FoldConstantArithmetic(Opc, VT,
594 cast<ConstantSDNode>(N1.getOperand(1)),
595 cast<ConstantSDNode>(N0));
596 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
598 if (N1.hasOneUse()) {
599 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
600 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
601 N1.getOperand(0), N0);
602 AddToWorkList(OpNode.getNode());
603 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
610 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
612 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
614 DEBUG(dbgs() << "\nReplacing.1 ";
616 dbgs() << "\nWith: ";
617 To[0].getNode()->dump(&DAG);
618 dbgs() << " and " << NumTo-1 << " other values\n";
619 for (unsigned i = 0, e = NumTo; i != e; ++i)
620 assert((!To[i].getNode() ||
621 N->getValueType(i) == To[i].getValueType()) &&
622 "Cannot combine value to value of different type!"));
623 WorkListRemover DeadNodes(*this);
624 DAG.ReplaceAllUsesWith(N, To);
626 // Push the new nodes and any users onto the worklist
627 for (unsigned i = 0, e = NumTo; i != e; ++i) {
628 if (To[i].getNode()) {
629 AddToWorkList(To[i].getNode());
630 AddUsersToWorkList(To[i].getNode());
635 // Finally, if the node is now dead, remove it from the graph. The node
636 // may not be dead if the replacement process recursively simplified to
637 // something else needing this node.
638 if (N->use_empty()) {
639 // Nodes can be reintroduced into the worklist. Make sure we do not
640 // process a node that has been replaced.
641 removeFromWorkList(N);
643 // Finally, since the node is now dead, remove it from the graph.
646 return SDValue(N, 0);
650 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
651 // Replace all uses. If any nodes become isomorphic to other nodes and
652 // are deleted, make sure to remove them from our worklist.
653 WorkListRemover DeadNodes(*this);
654 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
656 // Push the new node and any (possibly new) users onto the worklist.
657 AddToWorkList(TLO.New.getNode());
658 AddUsersToWorkList(TLO.New.getNode());
660 // Finally, if the node is now dead, remove it from the graph. The node
661 // may not be dead if the replacement process recursively simplified to
662 // something else needing this node.
663 if (TLO.Old.getNode()->use_empty()) {
664 removeFromWorkList(TLO.Old.getNode());
666 // If the operands of this node are only used by the node, they will now
667 // be dead. Make sure to visit them first to delete dead nodes early.
668 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
669 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
670 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
672 DAG.DeleteNode(TLO.Old.getNode());
676 /// SimplifyDemandedBits - Check the specified integer node value to see if
677 /// it can be simplified or if things it uses can be simplified by bit
678 /// propagation. If so, return true.
679 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
680 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
681 APInt KnownZero, KnownOne;
682 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
686 AddToWorkList(Op.getNode());
688 // Replace the old value with the new one.
690 DEBUG(dbgs() << "\nReplacing.2 ";
691 TLO.Old.getNode()->dump(&DAG);
692 dbgs() << "\nWith: ";
693 TLO.New.getNode()->dump(&DAG);
696 CommitTargetLoweringOpt(TLO);
700 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
701 DebugLoc dl = Load->getDebugLoc();
702 EVT VT = Load->getValueType(0);
703 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
705 DEBUG(dbgs() << "\nReplacing.9 ";
707 dbgs() << "\nWith: ";
708 Trunc.getNode()->dump(&DAG);
710 WorkListRemover DeadNodes(*this);
711 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
712 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
713 removeFromWorkList(Load);
714 DAG.DeleteNode(Load);
715 AddToWorkList(Trunc.getNode());
718 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
720 DebugLoc dl = Op.getDebugLoc();
721 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
722 EVT MemVT = LD->getMemoryVT();
723 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
724 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
726 : LD->getExtensionType();
728 return DAG.getExtLoad(ExtType, dl, PVT,
729 LD->getChain(), LD->getBasePtr(),
730 LD->getPointerInfo(),
731 MemVT, LD->isVolatile(),
732 LD->isNonTemporal(), LD->getAlignment());
735 unsigned Opc = Op.getOpcode();
738 case ISD::AssertSext:
739 return DAG.getNode(ISD::AssertSext, dl, PVT,
740 SExtPromoteOperand(Op.getOperand(0), PVT),
742 case ISD::AssertZext:
743 return DAG.getNode(ISD::AssertZext, dl, PVT,
744 ZExtPromoteOperand(Op.getOperand(0), PVT),
746 case ISD::Constant: {
748 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
749 return DAG.getNode(ExtOpc, dl, PVT, Op);
753 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
755 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
758 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
759 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
761 EVT OldVT = Op.getValueType();
762 DebugLoc dl = Op.getDebugLoc();
763 bool Replace = false;
764 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
765 if (NewOp.getNode() == 0)
767 AddToWorkList(NewOp.getNode());
770 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
771 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
772 DAG.getValueType(OldVT));
775 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
776 EVT OldVT = Op.getValueType();
777 DebugLoc dl = Op.getDebugLoc();
778 bool Replace = false;
779 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
780 if (NewOp.getNode() == 0)
782 AddToWorkList(NewOp.getNode());
785 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
786 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
789 /// PromoteIntBinOp - Promote the specified integer binary operation if the
790 /// target indicates it is beneficial. e.g. On x86, it's usually better to
791 /// promote i16 operations to i32 since i16 instructions are longer.
792 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
793 if (!LegalOperations)
796 EVT VT = Op.getValueType();
797 if (VT.isVector() || !VT.isInteger())
800 // If operation type is 'undesirable', e.g. i16 on x86, consider
802 unsigned Opc = Op.getOpcode();
803 if (TLI.isTypeDesirableForOp(Opc, VT))
807 // Consult target whether it is a good idea to promote this operation and
808 // what's the right type to promote it to.
809 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
810 assert(PVT != VT && "Don't know what type to promote to!");
812 bool Replace0 = false;
813 SDValue N0 = Op.getOperand(0);
814 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
815 if (NN0.getNode() == 0)
818 bool Replace1 = false;
819 SDValue N1 = Op.getOperand(1);
824 NN1 = PromoteOperand(N1, PVT, Replace1);
825 if (NN1.getNode() == 0)
829 AddToWorkList(NN0.getNode());
831 AddToWorkList(NN1.getNode());
834 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
836 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
838 DEBUG(dbgs() << "\nPromoting ";
839 Op.getNode()->dump(&DAG));
840 DebugLoc dl = Op.getDebugLoc();
841 return DAG.getNode(ISD::TRUNCATE, dl, VT,
842 DAG.getNode(Opc, dl, PVT, NN0, NN1));
847 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
848 /// target indicates it is beneficial. e.g. On x86, it's usually better to
849 /// promote i16 operations to i32 since i16 instructions are longer.
850 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
851 if (!LegalOperations)
854 EVT VT = Op.getValueType();
855 if (VT.isVector() || !VT.isInteger())
858 // If operation type is 'undesirable', e.g. i16 on x86, consider
860 unsigned Opc = Op.getOpcode();
861 if (TLI.isTypeDesirableForOp(Opc, VT))
865 // Consult target whether it is a good idea to promote this operation and
866 // what's the right type to promote it to.
867 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
868 assert(PVT != VT && "Don't know what type to promote to!");
870 bool Replace = false;
871 SDValue N0 = Op.getOperand(0);
873 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
874 else if (Opc == ISD::SRL)
875 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
877 N0 = PromoteOperand(N0, PVT, Replace);
878 if (N0.getNode() == 0)
881 AddToWorkList(N0.getNode());
883 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
885 DEBUG(dbgs() << "\nPromoting ";
886 Op.getNode()->dump(&DAG));
887 DebugLoc dl = Op.getDebugLoc();
888 return DAG.getNode(ISD::TRUNCATE, dl, VT,
889 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
894 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
895 if (!LegalOperations)
898 EVT VT = Op.getValueType();
899 if (VT.isVector() || !VT.isInteger())
902 // If operation type is 'undesirable', e.g. i16 on x86, consider
904 unsigned Opc = Op.getOpcode();
905 if (TLI.isTypeDesirableForOp(Opc, VT))
909 // Consult target whether it is a good idea to promote this operation and
910 // what's the right type to promote it to.
911 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
912 assert(PVT != VT && "Don't know what type to promote to!");
913 // fold (aext (aext x)) -> (aext x)
914 // fold (aext (zext x)) -> (zext x)
915 // fold (aext (sext x)) -> (sext x)
916 DEBUG(dbgs() << "\nPromoting ";
917 Op.getNode()->dump(&DAG));
918 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
923 bool DAGCombiner::PromoteLoad(SDValue Op) {
924 if (!LegalOperations)
927 EVT VT = Op.getValueType();
928 if (VT.isVector() || !VT.isInteger())
931 // If operation type is 'undesirable', e.g. i16 on x86, consider
933 unsigned Opc = Op.getOpcode();
934 if (TLI.isTypeDesirableForOp(Opc, VT))
938 // Consult target whether it is a good idea to promote this operation and
939 // what's the right type to promote it to.
940 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
941 assert(PVT != VT && "Don't know what type to promote to!");
943 DebugLoc dl = Op.getDebugLoc();
944 SDNode *N = Op.getNode();
945 LoadSDNode *LD = cast<LoadSDNode>(N);
946 EVT MemVT = LD->getMemoryVT();
947 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
948 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
950 : LD->getExtensionType();
951 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
952 LD->getChain(), LD->getBasePtr(),
953 LD->getPointerInfo(),
954 MemVT, LD->isVolatile(),
955 LD->isNonTemporal(), LD->getAlignment());
956 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
958 DEBUG(dbgs() << "\nPromoting ";
961 Result.getNode()->dump(&DAG);
963 WorkListRemover DeadNodes(*this);
964 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
965 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
966 removeFromWorkList(N);
968 AddToWorkList(Result.getNode());
975 //===----------------------------------------------------------------------===//
976 // Main DAG Combiner implementation
977 //===----------------------------------------------------------------------===//
979 void DAGCombiner::Run(CombineLevel AtLevel) {
980 // set the instance variables, so that the various visit routines may use it.
982 LegalOperations = Level >= AfterLegalizeVectorOps;
983 LegalTypes = Level >= AfterLegalizeTypes;
985 // Add all the dag nodes to the worklist.
986 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
987 E = DAG.allnodes_end(); I != E; ++I)
990 // Create a dummy node (which is not added to allnodes), that adds a reference
991 // to the root node, preventing it from being deleted, and tracking any
992 // changes of the root.
993 HandleSDNode Dummy(DAG.getRoot());
995 // The root of the dag may dangle to deleted nodes until the dag combiner is
996 // done. Set it to null to avoid confusion.
997 DAG.setRoot(SDValue());
999 // while the worklist isn't empty, find a node and
1000 // try and combine it.
1001 while (!WorkListContents.empty()) {
1003 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates.
1004 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the
1005 // worklist *should* contain, and check the node we want to visit is should
1006 // actually be visited.
1008 N = WorkListOrder.pop_back_val();
1009 } while (!WorkListContents.erase(N));
1011 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1012 // N is deleted from the DAG, since they too may now be dead or may have a
1013 // reduced number of uses, allowing other xforms.
1014 if (N->use_empty() && N != &Dummy) {
1015 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1016 AddToWorkList(N->getOperand(i).getNode());
1022 SDValue RV = combine(N);
1024 if (RV.getNode() == 0)
1029 // If we get back the same node we passed in, rather than a new node or
1030 // zero, we know that the node must have defined multiple values and
1031 // CombineTo was used. Since CombineTo takes care of the worklist
1032 // mechanics for us, we have no work to do in this case.
1033 if (RV.getNode() == N)
1036 assert(N->getOpcode() != ISD::DELETED_NODE &&
1037 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1038 "Node was deleted but visit returned new node!");
1040 DEBUG(dbgs() << "\nReplacing.3 ";
1042 dbgs() << "\nWith: ";
1043 RV.getNode()->dump(&DAG);
1046 // Transfer debug value.
1047 DAG.TransferDbgValues(SDValue(N, 0), RV);
1048 WorkListRemover DeadNodes(*this);
1049 if (N->getNumValues() == RV.getNode()->getNumValues())
1050 DAG.ReplaceAllUsesWith(N, RV.getNode());
1052 assert(N->getValueType(0) == RV.getValueType() &&
1053 N->getNumValues() == 1 && "Type mismatch");
1055 DAG.ReplaceAllUsesWith(N, &OpV);
1058 // Push the new node and any users onto the worklist
1059 AddToWorkList(RV.getNode());
1060 AddUsersToWorkList(RV.getNode());
1062 // Add any uses of the old node to the worklist in case this node is the
1063 // last one that uses them. They may become dead after this node is
1065 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1066 AddToWorkList(N->getOperand(i).getNode());
1068 // Finally, if the node is now dead, remove it from the graph. The node
1069 // may not be dead if the replacement process recursively simplified to
1070 // something else needing this node.
1071 if (N->use_empty()) {
1072 // Nodes can be reintroduced into the worklist. Make sure we do not
1073 // process a node that has been replaced.
1074 removeFromWorkList(N);
1076 // Finally, since the node is now dead, remove it from the graph.
1081 // If the root changed (e.g. it was a dead load, update the root).
1082 DAG.setRoot(Dummy.getValue());
1083 DAG.RemoveDeadNodes();
1086 SDValue DAGCombiner::visit(SDNode *N) {
1087 switch (N->getOpcode()) {
1089 case ISD::TokenFactor: return visitTokenFactor(N);
1090 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1091 case ISD::ADD: return visitADD(N);
1092 case ISD::SUB: return visitSUB(N);
1093 case ISD::ADDC: return visitADDC(N);
1094 case ISD::SUBC: return visitSUBC(N);
1095 case ISD::ADDE: return visitADDE(N);
1096 case ISD::SUBE: return visitSUBE(N);
1097 case ISD::MUL: return visitMUL(N);
1098 case ISD::SDIV: return visitSDIV(N);
1099 case ISD::UDIV: return visitUDIV(N);
1100 case ISD::SREM: return visitSREM(N);
1101 case ISD::UREM: return visitUREM(N);
1102 case ISD::MULHU: return visitMULHU(N);
1103 case ISD::MULHS: return visitMULHS(N);
1104 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1105 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1106 case ISD::SMULO: return visitSMULO(N);
1107 case ISD::UMULO: return visitUMULO(N);
1108 case ISD::SDIVREM: return visitSDIVREM(N);
1109 case ISD::UDIVREM: return visitUDIVREM(N);
1110 case ISD::AND: return visitAND(N);
1111 case ISD::OR: return visitOR(N);
1112 case ISD::XOR: return visitXOR(N);
1113 case ISD::SHL: return visitSHL(N);
1114 case ISD::SRA: return visitSRA(N);
1115 case ISD::SRL: return visitSRL(N);
1116 case ISD::CTLZ: return visitCTLZ(N);
1117 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1118 case ISD::CTTZ: return visitCTTZ(N);
1119 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1120 case ISD::CTPOP: return visitCTPOP(N);
1121 case ISD::SELECT: return visitSELECT(N);
1122 case ISD::SELECT_CC: return visitSELECT_CC(N);
1123 case ISD::SETCC: return visitSETCC(N);
1124 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1125 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1126 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1127 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1128 case ISD::TRUNCATE: return visitTRUNCATE(N);
1129 case ISD::BITCAST: return visitBITCAST(N);
1130 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1131 case ISD::FADD: return visitFADD(N);
1132 case ISD::FSUB: return visitFSUB(N);
1133 case ISD::FMUL: return visitFMUL(N);
1134 case ISD::FMA: return visitFMA(N);
1135 case ISD::FDIV: return visitFDIV(N);
1136 case ISD::FREM: return visitFREM(N);
1137 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1138 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1139 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1140 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1141 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1142 case ISD::FP_ROUND: return visitFP_ROUND(N);
1143 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1144 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1145 case ISD::FNEG: return visitFNEG(N);
1146 case ISD::FABS: return visitFABS(N);
1147 case ISD::FFLOOR: return visitFFLOOR(N);
1148 case ISD::FCEIL: return visitFCEIL(N);
1149 case ISD::FTRUNC: return visitFTRUNC(N);
1150 case ISD::BRCOND: return visitBRCOND(N);
1151 case ISD::BR_CC: return visitBR_CC(N);
1152 case ISD::LOAD: return visitLOAD(N);
1153 case ISD::STORE: return visitSTORE(N);
1154 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1155 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1156 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1157 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1158 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1159 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1160 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1165 SDValue DAGCombiner::combine(SDNode *N) {
1166 SDValue RV = visit(N);
1168 // If nothing happened, try a target-specific DAG combine.
1169 if (RV.getNode() == 0) {
1170 assert(N->getOpcode() != ISD::DELETED_NODE &&
1171 "Node was deleted but visit returned NULL!");
1173 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1174 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1176 // Expose the DAG combiner to the target combiner impls.
1177 TargetLowering::DAGCombinerInfo
1178 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1180 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1184 // If nothing happened still, try promoting the operation.
1185 if (RV.getNode() == 0) {
1186 switch (N->getOpcode()) {
1194 RV = PromoteIntBinOp(SDValue(N, 0));
1199 RV = PromoteIntShiftOp(SDValue(N, 0));
1201 case ISD::SIGN_EXTEND:
1202 case ISD::ZERO_EXTEND:
1203 case ISD::ANY_EXTEND:
1204 RV = PromoteExtend(SDValue(N, 0));
1207 if (PromoteLoad(SDValue(N, 0)))
1213 // If N is a commutative binary node, try commuting it to enable more
1215 if (RV.getNode() == 0 &&
1216 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1217 N->getNumValues() == 1) {
1218 SDValue N0 = N->getOperand(0);
1219 SDValue N1 = N->getOperand(1);
1221 // Constant operands are canonicalized to RHS.
1222 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1223 SDValue Ops[] = { N1, N0 };
1224 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1227 return SDValue(CSENode, 0);
1234 /// getInputChainForNode - Given a node, return its input chain if it has one,
1235 /// otherwise return a null sd operand.
1236 static SDValue getInputChainForNode(SDNode *N) {
1237 if (unsigned NumOps = N->getNumOperands()) {
1238 if (N->getOperand(0).getValueType() == MVT::Other)
1239 return N->getOperand(0);
1240 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1241 return N->getOperand(NumOps-1);
1242 for (unsigned i = 1; i < NumOps-1; ++i)
1243 if (N->getOperand(i).getValueType() == MVT::Other)
1244 return N->getOperand(i);
1249 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1250 // If N has two operands, where one has an input chain equal to the other,
1251 // the 'other' chain is redundant.
1252 if (N->getNumOperands() == 2) {
1253 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1254 return N->getOperand(0);
1255 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1256 return N->getOperand(1);
1259 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1260 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1261 SmallPtrSet<SDNode*, 16> SeenOps;
1262 bool Changed = false; // If we should replace this token factor.
1264 // Start out with this token factor.
1267 // Iterate through token factors. The TFs grows when new token factors are
1269 for (unsigned i = 0; i < TFs.size(); ++i) {
1270 SDNode *TF = TFs[i];
1272 // Check each of the operands.
1273 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1274 SDValue Op = TF->getOperand(i);
1276 switch (Op.getOpcode()) {
1277 case ISD::EntryToken:
1278 // Entry tokens don't need to be added to the list. They are
1283 case ISD::TokenFactor:
1284 if (Op.hasOneUse() &&
1285 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1286 // Queue up for processing.
1287 TFs.push_back(Op.getNode());
1288 // Clean up in case the token factor is removed.
1289 AddToWorkList(Op.getNode());
1296 // Only add if it isn't already in the list.
1297 if (SeenOps.insert(Op.getNode()))
1308 // If we've change things around then replace token factor.
1311 // The entry token is the only possible outcome.
1312 Result = DAG.getEntryNode();
1314 // New and improved token factor.
1315 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1316 MVT::Other, &Ops[0], Ops.size());
1319 // Don't add users to work list.
1320 return CombineTo(N, Result, false);
1326 /// MERGE_VALUES can always be eliminated.
1327 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1328 WorkListRemover DeadNodes(*this);
1329 // Replacing results may cause a different MERGE_VALUES to suddenly
1330 // be CSE'd with N, and carry its uses with it. Iterate until no
1331 // uses remain, to ensure that the node can be safely deleted.
1332 // First add the users of this node to the work list so that they
1333 // can be tried again once they have new operands.
1334 AddUsersToWorkList(N);
1336 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1337 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1338 } while (!N->use_empty());
1339 removeFromWorkList(N);
1341 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1345 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1346 SelectionDAG &DAG) {
1347 EVT VT = N0.getValueType();
1348 SDValue N00 = N0.getOperand(0);
1349 SDValue N01 = N0.getOperand(1);
1350 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1352 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1353 isa<ConstantSDNode>(N00.getOperand(1))) {
1354 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1355 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1356 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1357 N00.getOperand(0), N01),
1358 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1359 N00.getOperand(1), N01));
1360 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1366 SDValue DAGCombiner::visitADD(SDNode *N) {
1367 SDValue N0 = N->getOperand(0);
1368 SDValue N1 = N->getOperand(1);
1369 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1370 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1371 EVT VT = N0.getValueType();
1374 if (VT.isVector()) {
1375 SDValue FoldedVOp = SimplifyVBinOp(N);
1376 if (FoldedVOp.getNode()) return FoldedVOp;
1379 // fold (add x, undef) -> undef
1380 if (N0.getOpcode() == ISD::UNDEF)
1382 if (N1.getOpcode() == ISD::UNDEF)
1384 // fold (add c1, c2) -> c1+c2
1386 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1387 // canonicalize constant to RHS
1389 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1390 // fold (add x, 0) -> x
1391 if (N1C && N1C->isNullValue())
1393 // fold (add Sym, c) -> Sym+c
1394 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1395 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1396 GA->getOpcode() == ISD::GlobalAddress)
1397 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1399 (uint64_t)N1C->getSExtValue());
1400 // fold ((c1-A)+c2) -> (c1+c2)-A
1401 if (N1C && N0.getOpcode() == ISD::SUB)
1402 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1403 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1404 DAG.getConstant(N1C->getAPIntValue()+
1405 N0C->getAPIntValue(), VT),
1408 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1409 if (RADD.getNode() != 0)
1411 // fold ((0-A) + B) -> B-A
1412 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1413 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1414 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1415 // fold (A + (0-B)) -> A-B
1416 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1417 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1418 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1419 // fold (A+(B-A)) -> B
1420 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1421 return N1.getOperand(0);
1422 // fold ((B-A)+A) -> B
1423 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1424 return N0.getOperand(0);
1425 // fold (A+(B-(A+C))) to (B-C)
1426 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1427 N0 == N1.getOperand(1).getOperand(0))
1428 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1429 N1.getOperand(1).getOperand(1));
1430 // fold (A+(B-(C+A))) to (B-C)
1431 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1432 N0 == N1.getOperand(1).getOperand(1))
1433 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1434 N1.getOperand(1).getOperand(0));
1435 // fold (A+((B-A)+or-C)) to (B+or-C)
1436 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1437 N1.getOperand(0).getOpcode() == ISD::SUB &&
1438 N0 == N1.getOperand(0).getOperand(1))
1439 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1440 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1442 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1443 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1444 SDValue N00 = N0.getOperand(0);
1445 SDValue N01 = N0.getOperand(1);
1446 SDValue N10 = N1.getOperand(0);
1447 SDValue N11 = N1.getOperand(1);
1449 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1450 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1451 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1452 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1455 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1456 return SDValue(N, 0);
1458 // fold (a+b) -> (a|b) iff a and b share no bits.
1459 if (VT.isInteger() && !VT.isVector()) {
1460 APInt LHSZero, LHSOne;
1461 APInt RHSZero, RHSOne;
1462 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1464 if (LHSZero.getBoolValue()) {
1465 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1467 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1468 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1469 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1470 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1474 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1475 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1476 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1477 if (Result.getNode()) return Result;
1479 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1480 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1481 if (Result.getNode()) return Result;
1484 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1485 if (N1.getOpcode() == ISD::SHL &&
1486 N1.getOperand(0).getOpcode() == ISD::SUB)
1487 if (ConstantSDNode *C =
1488 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1489 if (C->getAPIntValue() == 0)
1490 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1491 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1492 N1.getOperand(0).getOperand(1),
1494 if (N0.getOpcode() == ISD::SHL &&
1495 N0.getOperand(0).getOpcode() == ISD::SUB)
1496 if (ConstantSDNode *C =
1497 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1498 if (C->getAPIntValue() == 0)
1499 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1500 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1501 N0.getOperand(0).getOperand(1),
1504 if (N1.getOpcode() == ISD::AND) {
1505 SDValue AndOp0 = N1.getOperand(0);
1506 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1507 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1508 unsigned DestBits = VT.getScalarType().getSizeInBits();
1510 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1511 // and similar xforms where the inner op is either ~0 or 0.
1512 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1513 DebugLoc DL = N->getDebugLoc();
1514 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1518 // add (sext i1), X -> sub X, (zext i1)
1519 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1520 N0.getOperand(0).getValueType() == MVT::i1 &&
1521 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1522 DebugLoc DL = N->getDebugLoc();
1523 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1524 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1530 SDValue DAGCombiner::visitADDC(SDNode *N) {
1531 SDValue N0 = N->getOperand(0);
1532 SDValue N1 = N->getOperand(1);
1533 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1534 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1535 EVT VT = N0.getValueType();
1537 // If the flag result is dead, turn this into an ADD.
1538 if (!N->hasAnyUseOfValue(1))
1539 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1),
1540 DAG.getNode(ISD::CARRY_FALSE,
1541 N->getDebugLoc(), MVT::Glue));
1543 // canonicalize constant to RHS.
1545 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1547 // fold (addc x, 0) -> x + no carry out
1548 if (N1C && N1C->isNullValue())
1549 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1550 N->getDebugLoc(), MVT::Glue));
1552 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1553 APInt LHSZero, LHSOne;
1554 APInt RHSZero, RHSOne;
1555 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1557 if (LHSZero.getBoolValue()) {
1558 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1560 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1561 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1562 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1563 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1564 DAG.getNode(ISD::CARRY_FALSE,
1565 N->getDebugLoc(), MVT::Glue));
1571 SDValue DAGCombiner::visitADDE(SDNode *N) {
1572 SDValue N0 = N->getOperand(0);
1573 SDValue N1 = N->getOperand(1);
1574 SDValue CarryIn = N->getOperand(2);
1575 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1576 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1578 // canonicalize constant to RHS
1580 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1583 // fold (adde x, y, false) -> (addc x, y)
1584 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1585 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1);
1590 // Since it may not be valid to emit a fold to zero for vector initializers
1591 // check if we can before folding.
1592 static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1593 SelectionDAG &DAG, bool LegalOperations) {
1594 if (!VT.isVector()) {
1595 return DAG.getConstant(0, VT);
1597 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1598 // Produce a vector of zeros.
1599 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1600 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1601 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1602 &Ops[0], Ops.size());
1607 SDValue DAGCombiner::visitSUB(SDNode *N) {
1608 SDValue N0 = N->getOperand(0);
1609 SDValue N1 = N->getOperand(1);
1610 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1611 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1612 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1613 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1614 EVT VT = N0.getValueType();
1617 if (VT.isVector()) {
1618 SDValue FoldedVOp = SimplifyVBinOp(N);
1619 if (FoldedVOp.getNode()) return FoldedVOp;
1622 // fold (sub x, x) -> 0
1623 // FIXME: Refactor this and xor and other similar operations together.
1625 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1626 // fold (sub c1, c2) -> c1-c2
1628 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1629 // fold (sub x, c) -> (add x, -c)
1631 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1632 DAG.getConstant(-N1C->getAPIntValue(), VT));
1633 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1634 if (N0C && N0C->isAllOnesValue())
1635 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1636 // fold A-(A-B) -> B
1637 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1638 return N1.getOperand(1);
1639 // fold (A+B)-A -> B
1640 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1641 return N0.getOperand(1);
1642 // fold (A+B)-B -> A
1643 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1644 return N0.getOperand(0);
1645 // fold C2-(A+C1) -> (C2-C1)-A
1646 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1647 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT);
1648 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
1651 // fold ((A+(B+or-C))-B) -> A+or-C
1652 if (N0.getOpcode() == ISD::ADD &&
1653 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1654 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1655 N0.getOperand(1).getOperand(0) == N1)
1656 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1657 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1658 // fold ((A+(C+B))-B) -> A+C
1659 if (N0.getOpcode() == ISD::ADD &&
1660 N0.getOperand(1).getOpcode() == ISD::ADD &&
1661 N0.getOperand(1).getOperand(1) == N1)
1662 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1663 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1664 // fold ((A-(B-C))-C) -> A-B
1665 if (N0.getOpcode() == ISD::SUB &&
1666 N0.getOperand(1).getOpcode() == ISD::SUB &&
1667 N0.getOperand(1).getOperand(1) == N1)
1668 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1669 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1671 // If either operand of a sub is undef, the result is undef
1672 if (N0.getOpcode() == ISD::UNDEF)
1674 if (N1.getOpcode() == ISD::UNDEF)
1677 // If the relocation model supports it, consider symbol offsets.
1678 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1679 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1680 // fold (sub Sym, c) -> Sym-c
1681 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1682 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1684 (uint64_t)N1C->getSExtValue());
1685 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1686 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1687 if (GA->getGlobal() == GB->getGlobal())
1688 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1695 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1696 SDValue N0 = N->getOperand(0);
1697 SDValue N1 = N->getOperand(1);
1698 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1699 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1700 EVT VT = N0.getValueType();
1702 // If the flag result is dead, turn this into an SUB.
1703 if (!N->hasAnyUseOfValue(1))
1704 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1),
1705 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1708 // fold (subc x, x) -> 0 + no borrow
1710 return CombineTo(N, DAG.getConstant(0, VT),
1711 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1714 // fold (subc x, 0) -> x + no borrow
1715 if (N1C && N1C->isNullValue())
1716 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1719 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1720 if (N0C && N0C->isAllOnesValue())
1721 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0),
1722 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1728 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1729 SDValue N0 = N->getOperand(0);
1730 SDValue N1 = N->getOperand(1);
1731 SDValue CarryIn = N->getOperand(2);
1733 // fold (sube x, y, false) -> (subc x, y)
1734 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1735 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1);
1740 SDValue DAGCombiner::visitMUL(SDNode *N) {
1741 SDValue N0 = N->getOperand(0);
1742 SDValue N1 = N->getOperand(1);
1743 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1744 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1745 EVT VT = N0.getValueType();
1748 if (VT.isVector()) {
1749 SDValue FoldedVOp = SimplifyVBinOp(N);
1750 if (FoldedVOp.getNode()) return FoldedVOp;
1753 // fold (mul x, undef) -> 0
1754 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1755 return DAG.getConstant(0, VT);
1756 // fold (mul c1, c2) -> c1*c2
1758 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1759 // canonicalize constant to RHS
1761 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1762 // fold (mul x, 0) -> 0
1763 if (N1C && N1C->isNullValue())
1765 // fold (mul x, -1) -> 0-x
1766 if (N1C && N1C->isAllOnesValue())
1767 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1768 DAG.getConstant(0, VT), N0);
1769 // fold (mul x, (1 << c)) -> x << c
1770 if (N1C && N1C->getAPIntValue().isPowerOf2())
1771 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1772 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1773 getShiftAmountTy(N0.getValueType())));
1774 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1775 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1776 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1777 // FIXME: If the input is something that is easily negated (e.g. a
1778 // single-use add), we should put the negate there.
1779 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1780 DAG.getConstant(0, VT),
1781 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1782 DAG.getConstant(Log2Val,
1783 getShiftAmountTy(N0.getValueType()))));
1785 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1786 if (N1C && N0.getOpcode() == ISD::SHL &&
1787 isa<ConstantSDNode>(N0.getOperand(1))) {
1788 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1789 N1, N0.getOperand(1));
1790 AddToWorkList(C3.getNode());
1791 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1792 N0.getOperand(0), C3);
1795 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1798 SDValue Sh(0,0), Y(0,0);
1799 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1800 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1801 N0.getNode()->hasOneUse()) {
1803 } else if (N1.getOpcode() == ISD::SHL &&
1804 isa<ConstantSDNode>(N1.getOperand(1)) &&
1805 N1.getNode()->hasOneUse()) {
1810 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1811 Sh.getOperand(0), Y);
1812 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1813 Mul, Sh.getOperand(1));
1817 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1818 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1819 isa<ConstantSDNode>(N0.getOperand(1)))
1820 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1821 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1822 N0.getOperand(0), N1),
1823 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1824 N0.getOperand(1), N1));
1827 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1828 if (RMUL.getNode() != 0)
1834 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1835 SDValue N0 = N->getOperand(0);
1836 SDValue N1 = N->getOperand(1);
1837 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1838 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1839 EVT VT = N->getValueType(0);
1842 if (VT.isVector()) {
1843 SDValue FoldedVOp = SimplifyVBinOp(N);
1844 if (FoldedVOp.getNode()) return FoldedVOp;
1847 // fold (sdiv c1, c2) -> c1/c2
1848 if (N0C && N1C && !N1C->isNullValue())
1849 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1850 // fold (sdiv X, 1) -> X
1851 if (N1C && N1C->getAPIntValue() == 1LL)
1853 // fold (sdiv X, -1) -> 0-X
1854 if (N1C && N1C->isAllOnesValue())
1855 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1856 DAG.getConstant(0, VT), N0);
1857 // If we know the sign bits of both operands are zero, strength reduce to a
1858 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1859 if (!VT.isVector()) {
1860 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1861 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1864 // fold (sdiv X, pow2) -> simple ops after legalize
1865 if (N1C && !N1C->isNullValue() &&
1866 (N1C->getAPIntValue().isPowerOf2() ||
1867 (-N1C->getAPIntValue()).isPowerOf2())) {
1868 // If dividing by powers of two is cheap, then don't perform the following
1870 if (TLI.isPow2DivCheap())
1873 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
1875 // Splat the sign bit into the register
1876 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1877 DAG.getConstant(VT.getSizeInBits()-1,
1878 getShiftAmountTy(N0.getValueType())));
1879 AddToWorkList(SGN.getNode());
1881 // Add (N0 < 0) ? abs2 - 1 : 0;
1882 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1883 DAG.getConstant(VT.getSizeInBits() - lg2,
1884 getShiftAmountTy(SGN.getValueType())));
1885 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1886 AddToWorkList(SRL.getNode());
1887 AddToWorkList(ADD.getNode()); // Divide by pow2
1888 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1889 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1891 // If we're dividing by a positive value, we're done. Otherwise, we must
1892 // negate the result.
1893 if (N1C->getAPIntValue().isNonNegative())
1896 AddToWorkList(SRA.getNode());
1897 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1898 DAG.getConstant(0, VT), SRA);
1901 // if integer divide is expensive and we satisfy the requirements, emit an
1902 // alternate sequence.
1903 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1904 SDValue Op = BuildSDIV(N);
1905 if (Op.getNode()) return Op;
1909 if (N0.getOpcode() == ISD::UNDEF)
1910 return DAG.getConstant(0, VT);
1911 // X / undef -> undef
1912 if (N1.getOpcode() == ISD::UNDEF)
1918 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1919 SDValue N0 = N->getOperand(0);
1920 SDValue N1 = N->getOperand(1);
1921 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1922 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1923 EVT VT = N->getValueType(0);
1926 if (VT.isVector()) {
1927 SDValue FoldedVOp = SimplifyVBinOp(N);
1928 if (FoldedVOp.getNode()) return FoldedVOp;
1931 // fold (udiv c1, c2) -> c1/c2
1932 if (N0C && N1C && !N1C->isNullValue())
1933 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1934 // fold (udiv x, (1 << c)) -> x >>u c
1935 if (N1C && N1C->getAPIntValue().isPowerOf2())
1936 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1937 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1938 getShiftAmountTy(N0.getValueType())));
1939 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1940 if (N1.getOpcode() == ISD::SHL) {
1941 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1942 if (SHC->getAPIntValue().isPowerOf2()) {
1943 EVT ADDVT = N1.getOperand(1).getValueType();
1944 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1946 DAG.getConstant(SHC->getAPIntValue()
1949 AddToWorkList(Add.getNode());
1950 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1954 // fold (udiv x, c) -> alternate
1955 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1956 SDValue Op = BuildUDIV(N);
1957 if (Op.getNode()) return Op;
1961 if (N0.getOpcode() == ISD::UNDEF)
1962 return DAG.getConstant(0, VT);
1963 // X / undef -> undef
1964 if (N1.getOpcode() == ISD::UNDEF)
1970 SDValue DAGCombiner::visitSREM(SDNode *N) {
1971 SDValue N0 = N->getOperand(0);
1972 SDValue N1 = N->getOperand(1);
1973 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1974 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1975 EVT VT = N->getValueType(0);
1977 // fold (srem c1, c2) -> c1%c2
1978 if (N0C && N1C && !N1C->isNullValue())
1979 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1980 // If we know the sign bits of both operands are zero, strength reduce to a
1981 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1982 if (!VT.isVector()) {
1983 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1984 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1987 // If X/C can be simplified by the division-by-constant logic, lower
1988 // X%C to the equivalent of X-X/C*C.
1989 if (N1C && !N1C->isNullValue()) {
1990 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1991 AddToWorkList(Div.getNode());
1992 SDValue OptimizedDiv = combine(Div.getNode());
1993 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1994 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1996 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1997 AddToWorkList(Mul.getNode());
2003 if (N0.getOpcode() == ISD::UNDEF)
2004 return DAG.getConstant(0, VT);
2005 // X % undef -> undef
2006 if (N1.getOpcode() == ISD::UNDEF)
2012 SDValue DAGCombiner::visitUREM(SDNode *N) {
2013 SDValue N0 = N->getOperand(0);
2014 SDValue N1 = N->getOperand(1);
2015 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2016 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2017 EVT VT = N->getValueType(0);
2019 // fold (urem c1, c2) -> c1%c2
2020 if (N0C && N1C && !N1C->isNullValue())
2021 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2022 // fold (urem x, pow2) -> (and x, pow2-1)
2023 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2024 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
2025 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2026 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2027 if (N1.getOpcode() == ISD::SHL) {
2028 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2029 if (SHC->getAPIntValue().isPowerOf2()) {
2031 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
2032 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2034 AddToWorkList(Add.getNode());
2035 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
2040 // If X/C can be simplified by the division-by-constant logic, lower
2041 // X%C to the equivalent of X-X/C*C.
2042 if (N1C && !N1C->isNullValue()) {
2043 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
2044 AddToWorkList(Div.getNode());
2045 SDValue OptimizedDiv = combine(Div.getNode());
2046 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2047 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2049 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2050 AddToWorkList(Mul.getNode());
2056 if (N0.getOpcode() == ISD::UNDEF)
2057 return DAG.getConstant(0, VT);
2058 // X % undef -> undef
2059 if (N1.getOpcode() == ISD::UNDEF)
2065 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2066 SDValue N0 = N->getOperand(0);
2067 SDValue N1 = N->getOperand(1);
2068 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2069 EVT VT = N->getValueType(0);
2070 DebugLoc DL = N->getDebugLoc();
2072 // fold (mulhs x, 0) -> 0
2073 if (N1C && N1C->isNullValue())
2075 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2076 if (N1C && N1C->getAPIntValue() == 1)
2077 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
2078 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2079 getShiftAmountTy(N0.getValueType())));
2080 // fold (mulhs x, undef) -> 0
2081 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2082 return DAG.getConstant(0, VT);
2084 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2086 if (VT.isSimple() && !VT.isVector()) {
2087 MVT Simple = VT.getSimpleVT();
2088 unsigned SimpleSize = Simple.getSizeInBits();
2089 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2090 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2091 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2092 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2093 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2094 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2095 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2096 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2103 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2104 SDValue N0 = N->getOperand(0);
2105 SDValue N1 = N->getOperand(1);
2106 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2107 EVT VT = N->getValueType(0);
2108 DebugLoc DL = N->getDebugLoc();
2110 // fold (mulhu x, 0) -> 0
2111 if (N1C && N1C->isNullValue())
2113 // fold (mulhu x, 1) -> 0
2114 if (N1C && N1C->getAPIntValue() == 1)
2115 return DAG.getConstant(0, N0.getValueType());
2116 // fold (mulhu x, undef) -> 0
2117 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2118 return DAG.getConstant(0, VT);
2120 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2122 if (VT.isSimple() && !VT.isVector()) {
2123 MVT Simple = VT.getSimpleVT();
2124 unsigned SimpleSize = Simple.getSizeInBits();
2125 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2126 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2127 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2128 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2129 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2130 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2131 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2132 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2139 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2140 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2141 /// that are being performed. Return true if a simplification was made.
2143 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2145 // If the high half is not needed, just compute the low half.
2146 bool HiExists = N->hasAnyUseOfValue(1);
2148 (!LegalOperations ||
2149 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2150 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2151 N->op_begin(), N->getNumOperands());
2152 return CombineTo(N, Res, Res);
2155 // If the low half is not needed, just compute the high half.
2156 bool LoExists = N->hasAnyUseOfValue(0);
2158 (!LegalOperations ||
2159 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2160 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2161 N->op_begin(), N->getNumOperands());
2162 return CombineTo(N, Res, Res);
2165 // If both halves are used, return as it is.
2166 if (LoExists && HiExists)
2169 // If the two computed results can be simplified separately, separate them.
2171 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2172 N->op_begin(), N->getNumOperands());
2173 AddToWorkList(Lo.getNode());
2174 SDValue LoOpt = combine(Lo.getNode());
2175 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2176 (!LegalOperations ||
2177 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2178 return CombineTo(N, LoOpt, LoOpt);
2182 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2183 N->op_begin(), N->getNumOperands());
2184 AddToWorkList(Hi.getNode());
2185 SDValue HiOpt = combine(Hi.getNode());
2186 if (HiOpt.getNode() && HiOpt != Hi &&
2187 (!LegalOperations ||
2188 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2189 return CombineTo(N, HiOpt, HiOpt);
2195 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2196 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2197 if (Res.getNode()) return Res;
2199 EVT VT = N->getValueType(0);
2200 DebugLoc DL = N->getDebugLoc();
2202 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2204 if (VT.isSimple() && !VT.isVector()) {
2205 MVT Simple = VT.getSimpleVT();
2206 unsigned SimpleSize = Simple.getSizeInBits();
2207 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2208 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2209 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2210 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2211 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2212 // Compute the high part as N1.
2213 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2214 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2215 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2216 // Compute the low part as N0.
2217 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2218 return CombineTo(N, Lo, Hi);
2225 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2226 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2227 if (Res.getNode()) return Res;
2229 EVT VT = N->getValueType(0);
2230 DebugLoc DL = N->getDebugLoc();
2232 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2234 if (VT.isSimple() && !VT.isVector()) {
2235 MVT Simple = VT.getSimpleVT();
2236 unsigned SimpleSize = Simple.getSizeInBits();
2237 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2238 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2239 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2240 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2241 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2242 // Compute the high part as N1.
2243 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2244 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2245 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2246 // Compute the low part as N0.
2247 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2248 return CombineTo(N, Lo, Hi);
2255 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2256 // (smulo x, 2) -> (saddo x, x)
2257 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2258 if (C2->getAPIntValue() == 2)
2259 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2260 N->getOperand(0), N->getOperand(0));
2265 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2266 // (umulo x, 2) -> (uaddo x, x)
2267 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2268 if (C2->getAPIntValue() == 2)
2269 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2270 N->getOperand(0), N->getOperand(0));
2275 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2276 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2277 if (Res.getNode()) return Res;
2282 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2283 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2284 if (Res.getNode()) return Res;
2289 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2290 /// two operands of the same opcode, try to simplify it.
2291 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2292 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2293 EVT VT = N0.getValueType();
2294 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2296 // Bail early if none of these transforms apply.
2297 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2299 // For each of OP in AND/OR/XOR:
2300 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2301 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2302 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2303 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2305 // do not sink logical op inside of a vector extend, since it may combine
2307 EVT Op0VT = N0.getOperand(0).getValueType();
2308 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2309 N0.getOpcode() == ISD::SIGN_EXTEND ||
2310 // Avoid infinite looping with PromoteIntBinOp.
2311 (N0.getOpcode() == ISD::ANY_EXTEND &&
2312 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2313 (N0.getOpcode() == ISD::TRUNCATE &&
2314 (!TLI.isZExtFree(VT, Op0VT) ||
2315 !TLI.isTruncateFree(Op0VT, VT)) &&
2316 TLI.isTypeLegal(Op0VT))) &&
2318 Op0VT == N1.getOperand(0).getValueType() &&
2319 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2320 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2321 N0.getOperand(0).getValueType(),
2322 N0.getOperand(0), N1.getOperand(0));
2323 AddToWorkList(ORNode.getNode());
2324 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2327 // For each of OP in SHL/SRL/SRA/AND...
2328 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2329 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2330 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2331 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2332 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2333 N0.getOperand(1) == N1.getOperand(1)) {
2334 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2335 N0.getOperand(0).getValueType(),
2336 N0.getOperand(0), N1.getOperand(0));
2337 AddToWorkList(ORNode.getNode());
2338 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2339 ORNode, N0.getOperand(1));
2342 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2343 // Only perform this optimization after type legalization and before
2344 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2345 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2346 // we don't want to undo this promotion.
2347 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2349 if ((N0.getOpcode() == ISD::BITCAST || N0.getOpcode() == ISD::SCALAR_TO_VECTOR)
2350 && Level == AfterLegalizeTypes) {
2351 SDValue In0 = N0.getOperand(0);
2352 SDValue In1 = N1.getOperand(0);
2353 EVT In0Ty = In0.getValueType();
2354 EVT In1Ty = In1.getValueType();
2355 // If both incoming values are integers, and the original types are the same.
2356 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2357 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), In0Ty, In0, In1);
2358 SDValue BC = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, Op);
2359 AddToWorkList(Op.getNode());
2364 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2365 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2366 // If both shuffles use the same mask, and both shuffle within a single
2367 // vector, then it is worthwhile to move the swizzle after the operation.
2368 // The type-legalizer generates this pattern when loading illegal
2369 // vector types from memory. In many cases this allows additional shuffle
2371 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
2372 N0.getOperand(1).getOpcode() == ISD::UNDEF &&
2373 N1.getOperand(1).getOpcode() == ISD::UNDEF) {
2374 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2375 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2377 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() &&
2378 "Inputs to shuffles are not the same type");
2380 unsigned NumElts = VT.getVectorNumElements();
2382 // Check that both shuffles use the same mask. The masks are known to be of
2383 // the same length because the result vector type is the same.
2384 bool SameMask = true;
2385 for (unsigned i = 0; i != NumElts; ++i) {
2386 int Idx0 = SVN0->getMaskElt(i);
2387 int Idx1 = SVN1->getMaskElt(i);
2395 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT,
2396 N0.getOperand(0), N1.getOperand(0));
2397 AddToWorkList(Op.getNode());
2398 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op,
2399 DAG.getUNDEF(VT), &SVN0->getMask()[0]);
2406 SDValue DAGCombiner::visitAND(SDNode *N) {
2407 SDValue N0 = N->getOperand(0);
2408 SDValue N1 = N->getOperand(1);
2409 SDValue LL, LR, RL, RR, CC0, CC1;
2410 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2411 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2412 EVT VT = N1.getValueType();
2413 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2416 if (VT.isVector()) {
2417 SDValue FoldedVOp = SimplifyVBinOp(N);
2418 if (FoldedVOp.getNode()) return FoldedVOp;
2421 // fold (and x, undef) -> 0
2422 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2423 return DAG.getConstant(0, VT);
2424 // fold (and c1, c2) -> c1&c2
2426 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2427 // canonicalize constant to RHS
2429 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2430 // fold (and x, -1) -> x
2431 if (N1C && N1C->isAllOnesValue())
2433 // if (and x, c) is known to be zero, return 0
2434 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2435 APInt::getAllOnesValue(BitWidth)))
2436 return DAG.getConstant(0, VT);
2438 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2439 if (RAND.getNode() != 0)
2441 // fold (and (or x, C), D) -> D if (C & D) == D
2442 if (N1C && N0.getOpcode() == ISD::OR)
2443 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2444 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2446 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2447 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2448 SDValue N0Op0 = N0.getOperand(0);
2449 APInt Mask = ~N1C->getAPIntValue();
2450 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2451 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2452 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2453 N0.getValueType(), N0Op0);
2455 // Replace uses of the AND with uses of the Zero extend node.
2458 // We actually want to replace all uses of the any_extend with the
2459 // zero_extend, to avoid duplicating things. This will later cause this
2460 // AND to be folded.
2461 CombineTo(N0.getNode(), Zext);
2462 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2465 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2466 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2467 // already be zero by virtue of the width of the base type of the load.
2469 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2471 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2472 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2473 N0.getOpcode() == ISD::LOAD) {
2474 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2475 N0 : N0.getOperand(0) );
2477 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2478 // This can be a pure constant or a vector splat, in which case we treat the
2479 // vector as a scalar and use the splat value.
2480 APInt Constant = APInt::getNullValue(1);
2481 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2482 Constant = C->getAPIntValue();
2483 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2484 APInt SplatValue, SplatUndef;
2485 unsigned SplatBitSize;
2487 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2488 SplatBitSize, HasAnyUndefs);
2490 // Undef bits can contribute to a possible optimisation if set, so
2492 SplatValue |= SplatUndef;
2494 // The splat value may be something like "0x00FFFFFF", which means 0 for
2495 // the first vector value and FF for the rest, repeating. We need a mask
2496 // that will apply equally to all members of the vector, so AND all the
2497 // lanes of the constant together.
2498 EVT VT = Vector->getValueType(0);
2499 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2501 // If the splat value has been compressed to a bitlength lower
2502 // than the size of the vector lane, we need to re-expand it to
2504 if (BitWidth > SplatBitSize)
2505 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
2506 SplatBitSize < BitWidth;
2507 SplatBitSize = SplatBitSize * 2)
2508 SplatValue |= SplatValue.shl(SplatBitSize);
2510 Constant = APInt::getAllOnesValue(BitWidth);
2511 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
2512 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2516 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2517 // actually legal and isn't going to get expanded, else this is a false
2519 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2520 Load->getMemoryVT());
2522 // Resize the constant to the same size as the original memory access before
2523 // extension. If it is still the AllOnesValue then this AND is completely
2526 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2529 switch (Load->getExtensionType()) {
2530 default: B = false; break;
2531 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2533 case ISD::NON_EXTLOAD: B = true; break;
2536 if (B && Constant.isAllOnesValue()) {
2537 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2538 // preserve semantics once we get rid of the AND.
2539 SDValue NewLoad(Load, 0);
2540 if (Load->getExtensionType() == ISD::EXTLOAD) {
2541 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2542 Load->getValueType(0), Load->getDebugLoc(),
2543 Load->getChain(), Load->getBasePtr(),
2544 Load->getOffset(), Load->getMemoryVT(),
2545 Load->getMemOperand());
2546 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2547 if (Load->getNumValues() == 3) {
2548 // PRE/POST_INC loads have 3 values.
2549 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
2550 NewLoad.getValue(2) };
2551 CombineTo(Load, To, 3, true);
2553 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2557 // Fold the AND away, taking care not to fold to the old load node if we
2559 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2561 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2564 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2565 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2566 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2567 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2569 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2570 LL.getValueType().isInteger()) {
2571 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2572 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2573 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2574 LR.getValueType(), LL, RL);
2575 AddToWorkList(ORNode.getNode());
2576 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2578 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2579 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2580 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2581 LR.getValueType(), LL, RL);
2582 AddToWorkList(ANDNode.getNode());
2583 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2585 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2586 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2587 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2588 LR.getValueType(), LL, RL);
2589 AddToWorkList(ORNode.getNode());
2590 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2593 // canonicalize equivalent to ll == rl
2594 if (LL == RR && LR == RL) {
2595 Op1 = ISD::getSetCCSwappedOperands(Op1);
2598 if (LL == RL && LR == RR) {
2599 bool isInteger = LL.getValueType().isInteger();
2600 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2601 if (Result != ISD::SETCC_INVALID &&
2602 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2603 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2608 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2609 if (N0.getOpcode() == N1.getOpcode()) {
2610 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2611 if (Tmp.getNode()) return Tmp;
2614 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2615 // fold (and (sra)) -> (and (srl)) when possible.
2616 if (!VT.isVector() &&
2617 SimplifyDemandedBits(SDValue(N, 0)))
2618 return SDValue(N, 0);
2620 // fold (zext_inreg (extload x)) -> (zextload x)
2621 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2622 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2623 EVT MemVT = LN0->getMemoryVT();
2624 // If we zero all the possible extended bits, then we can turn this into
2625 // a zextload if we are running before legalize or the operation is legal.
2626 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2627 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2628 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2629 ((!LegalOperations && !LN0->isVolatile()) ||
2630 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2631 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2632 LN0->getChain(), LN0->getBasePtr(),
2633 LN0->getPointerInfo(), MemVT,
2634 LN0->isVolatile(), LN0->isNonTemporal(),
2635 LN0->getAlignment());
2637 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2638 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2641 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2642 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2644 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2645 EVT MemVT = LN0->getMemoryVT();
2646 // If we zero all the possible extended bits, then we can turn this into
2647 // a zextload if we are running before legalize or the operation is legal.
2648 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2649 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2650 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2651 ((!LegalOperations && !LN0->isVolatile()) ||
2652 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2653 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2655 LN0->getBasePtr(), LN0->getPointerInfo(),
2657 LN0->isVolatile(), LN0->isNonTemporal(),
2658 LN0->getAlignment());
2660 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2661 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2665 // fold (and (load x), 255) -> (zextload x, i8)
2666 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2667 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2668 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2669 (N0.getOpcode() == ISD::ANY_EXTEND &&
2670 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2671 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2672 LoadSDNode *LN0 = HasAnyExt
2673 ? cast<LoadSDNode>(N0.getOperand(0))
2674 : cast<LoadSDNode>(N0);
2675 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2676 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2677 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2678 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2679 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2680 EVT LoadedVT = LN0->getMemoryVT();
2682 if (ExtVT == LoadedVT &&
2683 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2684 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2687 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2688 LN0->getChain(), LN0->getBasePtr(),
2689 LN0->getPointerInfo(),
2690 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2691 LN0->getAlignment());
2693 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2694 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2697 // Do not change the width of a volatile load.
2698 // Do not generate loads of non-round integer types since these can
2699 // be expensive (and would be wrong if the type is not byte sized).
2700 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2701 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2702 EVT PtrType = LN0->getOperand(1).getValueType();
2704 unsigned Alignment = LN0->getAlignment();
2705 SDValue NewPtr = LN0->getBasePtr();
2707 // For big endian targets, we need to add an offset to the pointer
2708 // to load the correct bytes. For little endian systems, we merely
2709 // need to read fewer bytes from the same pointer.
2710 if (TLI.isBigEndian()) {
2711 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2712 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2713 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2714 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2715 NewPtr, DAG.getConstant(PtrOff, PtrType));
2716 Alignment = MinAlign(Alignment, PtrOff);
2719 AddToWorkList(NewPtr.getNode());
2721 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2723 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2724 LN0->getChain(), NewPtr,
2725 LN0->getPointerInfo(),
2726 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2729 CombineTo(LN0, Load, Load.getValue(1));
2730 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2736 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2737 VT.getSizeInBits() <= 64) {
2738 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2739 APInt ADDC = ADDI->getAPIntValue();
2740 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2741 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
2742 // immediate for an add, but it is legal if its top c2 bits are set,
2743 // transform the ADD so the immediate doesn't need to be materialized
2745 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
2746 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
2747 SRLI->getZExtValue());
2748 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
2750 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2752 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
2753 N0.getOperand(0), DAG.getConstant(ADDC, VT));
2754 CombineTo(N0.getNode(), NewAdd);
2755 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2767 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2769 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2770 bool DemandHighBits) {
2771 if (!LegalOperations)
2774 EVT VT = N->getValueType(0);
2775 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2777 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2780 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2781 bool LookPassAnd0 = false;
2782 bool LookPassAnd1 = false;
2783 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2785 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2787 if (N0.getOpcode() == ISD::AND) {
2788 if (!N0.getNode()->hasOneUse())
2790 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2791 if (!N01C || N01C->getZExtValue() != 0xFF00)
2793 N0 = N0.getOperand(0);
2794 LookPassAnd0 = true;
2797 if (N1.getOpcode() == ISD::AND) {
2798 if (!N1.getNode()->hasOneUse())
2800 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2801 if (!N11C || N11C->getZExtValue() != 0xFF)
2803 N1 = N1.getOperand(0);
2804 LookPassAnd1 = true;
2807 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2809 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2811 if (!N0.getNode()->hasOneUse() ||
2812 !N1.getNode()->hasOneUse())
2815 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2816 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2819 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2822 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2823 SDValue N00 = N0->getOperand(0);
2824 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2825 if (!N00.getNode()->hasOneUse())
2827 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2828 if (!N001C || N001C->getZExtValue() != 0xFF)
2830 N00 = N00.getOperand(0);
2831 LookPassAnd0 = true;
2834 SDValue N10 = N1->getOperand(0);
2835 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2836 if (!N10.getNode()->hasOneUse())
2838 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2839 if (!N101C || N101C->getZExtValue() != 0xFF00)
2841 N10 = N10.getOperand(0);
2842 LookPassAnd1 = true;
2848 // Make sure everything beyond the low halfword is zero since the SRL 16
2849 // will clear the top bits.
2850 unsigned OpSizeInBits = VT.getSizeInBits();
2851 if (DemandHighBits && OpSizeInBits > 16 &&
2852 (!LookPassAnd0 || !LookPassAnd1) &&
2853 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
2856 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
2857 if (OpSizeInBits > 16)
2858 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2859 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2863 /// isBSwapHWordElement - Return true if the specified node is an element
2864 /// that makes up a 32-bit packed halfword byteswap. i.e.
2865 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2866 static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
2867 if (!N.getNode()->hasOneUse())
2870 unsigned Opc = N.getOpcode();
2871 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2874 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2879 switch (N1C->getZExtValue()) {
2882 case 0xFF: Num = 0; break;
2883 case 0xFF00: Num = 1; break;
2884 case 0xFF0000: Num = 2; break;
2885 case 0xFF000000: Num = 3; break;
2888 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
2889 SDValue N0 = N.getOperand(0);
2890 if (Opc == ISD::AND) {
2891 if (Num == 0 || Num == 2) {
2893 // (x >> 8) & 0xff0000
2894 if (N0.getOpcode() != ISD::SRL)
2896 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2897 if (!C || C->getZExtValue() != 8)
2900 // (x << 8) & 0xff00
2901 // (x << 8) & 0xff000000
2902 if (N0.getOpcode() != ISD::SHL)
2904 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2905 if (!C || C->getZExtValue() != 8)
2908 } else if (Opc == ISD::SHL) {
2910 // (x & 0xff0000) << 8
2911 if (Num != 0 && Num != 2)
2913 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2914 if (!C || C->getZExtValue() != 8)
2916 } else { // Opc == ISD::SRL
2917 // (x & 0xff00) >> 8
2918 // (x & 0xff000000) >> 8
2919 if (Num != 1 && Num != 3)
2921 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2922 if (!C || C->getZExtValue() != 8)
2929 Parts[Num] = N0.getOperand(0).getNode();
2933 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
2934 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2935 /// => (rotl (bswap x), 16)
2936 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2937 if (!LegalOperations)
2940 EVT VT = N->getValueType(0);
2943 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2946 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
2948 // (or (or (and), (and)), (or (and), (and)))
2949 // (or (or (or (and), (and)), (and)), (and))
2950 if (N0.getOpcode() != ISD::OR)
2952 SDValue N00 = N0.getOperand(0);
2953 SDValue N01 = N0.getOperand(1);
2955 if (N1.getOpcode() == ISD::OR) {
2956 // (or (or (and), (and)), (or (and), (and)))
2957 SDValue N000 = N00.getOperand(0);
2958 if (!isBSwapHWordElement(N000, Parts))
2961 SDValue N001 = N00.getOperand(1);
2962 if (!isBSwapHWordElement(N001, Parts))
2964 SDValue N010 = N01.getOperand(0);
2965 if (!isBSwapHWordElement(N010, Parts))
2967 SDValue N011 = N01.getOperand(1);
2968 if (!isBSwapHWordElement(N011, Parts))
2971 // (or (or (or (and), (and)), (and)), (and))
2972 if (!isBSwapHWordElement(N1, Parts))
2974 if (!isBSwapHWordElement(N01, Parts))
2976 if (N00.getOpcode() != ISD::OR)
2978 SDValue N000 = N00.getOperand(0);
2979 if (!isBSwapHWordElement(N000, Parts))
2981 SDValue N001 = N00.getOperand(1);
2982 if (!isBSwapHWordElement(N001, Parts))
2986 // Make sure the parts are all coming from the same node.
2987 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
2990 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
2991 SDValue(Parts[0],0));
2993 // Result of the bswap should be rotated by 16. If it's not legal, than
2994 // do (x << 16) | (x >> 16).
2995 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
2996 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
2997 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
2998 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
2999 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
3000 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
3001 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
3002 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
3005 SDValue DAGCombiner::visitOR(SDNode *N) {
3006 SDValue N0 = N->getOperand(0);
3007 SDValue N1 = N->getOperand(1);
3008 SDValue LL, LR, RL, RR, CC0, CC1;
3009 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3010 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3011 EVT VT = N1.getValueType();
3014 if (VT.isVector()) {
3015 SDValue FoldedVOp = SimplifyVBinOp(N);
3016 if (FoldedVOp.getNode()) return FoldedVOp;
3019 // fold (or x, undef) -> -1
3020 if (!LegalOperations &&
3021 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3022 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3023 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
3025 // fold (or c1, c2) -> c1|c2
3027 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
3028 // canonicalize constant to RHS
3030 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
3031 // fold (or x, 0) -> x
3032 if (N1C && N1C->isNullValue())
3034 // fold (or x, -1) -> -1
3035 if (N1C && N1C->isAllOnesValue())
3037 // fold (or x, c) -> c iff (x & ~c) == 0
3038 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3041 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3042 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3043 if (BSwap.getNode() != 0)
3045 BSwap = MatchBSwapHWordLow(N, N0, N1);
3046 if (BSwap.getNode() != 0)
3050 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
3051 if (ROR.getNode() != 0)
3053 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3054 // iff (c1 & c2) == 0.
3055 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3056 isa<ConstantSDNode>(N0.getOperand(1))) {
3057 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3058 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
3059 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3060 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3061 N0.getOperand(0), N1),
3062 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
3064 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3065 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3066 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3067 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3069 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3070 LL.getValueType().isInteger()) {
3071 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3072 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3073 if (cast<ConstantSDNode>(LR)->isNullValue() &&
3074 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3075 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
3076 LR.getValueType(), LL, RL);
3077 AddToWorkList(ORNode.getNode());
3078 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
3080 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3081 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3082 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
3083 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3084 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
3085 LR.getValueType(), LL, RL);
3086 AddToWorkList(ANDNode.getNode());
3087 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
3090 // canonicalize equivalent to ll == rl
3091 if (LL == RR && LR == RL) {
3092 Op1 = ISD::getSetCCSwappedOperands(Op1);
3095 if (LL == RL && LR == RR) {
3096 bool isInteger = LL.getValueType().isInteger();
3097 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3098 if (Result != ISD::SETCC_INVALID &&
3099 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
3100 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
3105 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3106 if (N0.getOpcode() == N1.getOpcode()) {
3107 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3108 if (Tmp.getNode()) return Tmp;
3111 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3112 if (N0.getOpcode() == ISD::AND &&
3113 N1.getOpcode() == ISD::AND &&
3114 N0.getOperand(1).getOpcode() == ISD::Constant &&
3115 N1.getOperand(1).getOpcode() == ISD::Constant &&
3116 // Don't increase # computations.
3117 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3118 // We can only do this xform if we know that bits from X that are set in C2
3119 // but not in C1 are already zero. Likewise for Y.
3120 const APInt &LHSMask =
3121 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3122 const APInt &RHSMask =
3123 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3125 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3126 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3127 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3128 N0.getOperand(0), N1.getOperand(0));
3129 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
3130 DAG.getConstant(LHSMask | RHSMask, VT));
3134 // See if this is some rotate idiom.
3135 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
3136 return SDValue(Rot, 0);
3138 // Simplify the operands using demanded-bits information.
3139 if (!VT.isVector() &&
3140 SimplifyDemandedBits(SDValue(N, 0)))
3141 return SDValue(N, 0);
3146 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
3147 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3148 if (Op.getOpcode() == ISD::AND) {
3149 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3150 Mask = Op.getOperand(1);
3151 Op = Op.getOperand(0);
3157 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3165 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3166 // idioms for rotate, and if the target supports rotation instructions, generate
3168 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
3169 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3170 EVT VT = LHS.getValueType();
3171 if (!TLI.isTypeLegal(VT)) return 0;
3173 // The target must have at least one rotate flavor.
3174 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3175 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3176 if (!HasROTL && !HasROTR) return 0;
3178 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3179 SDValue LHSShift; // The shift.
3180 SDValue LHSMask; // AND value if any.
3181 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3182 return 0; // Not part of a rotate.
3184 SDValue RHSShift; // The shift.
3185 SDValue RHSMask; // AND value if any.
3186 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3187 return 0; // Not part of a rotate.
3189 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3190 return 0; // Not shifting the same value.
3192 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3193 return 0; // Shifts must disagree.
3195 // Canonicalize shl to left side in a shl/srl pair.
3196 if (RHSShift.getOpcode() == ISD::SHL) {
3197 std::swap(LHS, RHS);
3198 std::swap(LHSShift, RHSShift);
3199 std::swap(LHSMask , RHSMask );
3202 unsigned OpSizeInBits = VT.getSizeInBits();
3203 SDValue LHSShiftArg = LHSShift.getOperand(0);
3204 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3205 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3207 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3208 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3209 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3210 RHSShiftAmt.getOpcode() == ISD::Constant) {
3211 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3212 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3213 if ((LShVal + RShVal) != OpSizeInBits)
3218 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
3220 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
3222 // If there is an AND of either shifted operand, apply it to the result.
3223 if (LHSMask.getNode() || RHSMask.getNode()) {
3224 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3226 if (LHSMask.getNode()) {
3227 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3228 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3230 if (RHSMask.getNode()) {
3231 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3232 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3235 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3238 return Rot.getNode();
3241 // If there is a mask here, and we have a variable shift, we can't be sure
3242 // that we're masking out the right stuff.
3243 if (LHSMask.getNode() || RHSMask.getNode())
3246 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
3247 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
3248 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
3249 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
3250 if (ConstantSDNode *SUBC =
3251 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
3252 if (SUBC->getAPIntValue() == OpSizeInBits) {
3254 return DAG.getNode(ISD::ROTL, DL, VT,
3255 LHSShiftArg, LHSShiftAmt).getNode();
3257 return DAG.getNode(ISD::ROTR, DL, VT,
3258 LHSShiftArg, RHSShiftAmt).getNode();
3263 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
3264 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
3265 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
3266 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
3267 if (ConstantSDNode *SUBC =
3268 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
3269 if (SUBC->getAPIntValue() == OpSizeInBits) {
3271 return DAG.getNode(ISD::ROTR, DL, VT,
3272 LHSShiftArg, RHSShiftAmt).getNode();
3274 return DAG.getNode(ISD::ROTL, DL, VT,
3275 LHSShiftArg, LHSShiftAmt).getNode();
3280 // Look for sign/zext/any-extended or truncate cases:
3281 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3282 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3283 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3284 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3285 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3286 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3287 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3288 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3289 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
3290 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
3291 if (RExtOp0.getOpcode() == ISD::SUB &&
3292 RExtOp0.getOperand(1) == LExtOp0) {
3293 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3295 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3296 // (rotr x, (sub 32, y))
3297 if (ConstantSDNode *SUBC =
3298 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3299 if (SUBC->getAPIntValue() == OpSizeInBits) {
3300 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3302 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3305 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3306 RExtOp0 == LExtOp0.getOperand(1)) {
3307 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3309 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3310 // (rotl x, (sub 32, y))
3311 if (ConstantSDNode *SUBC =
3312 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3313 if (SUBC->getAPIntValue() == OpSizeInBits) {
3314 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3316 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3325 SDValue DAGCombiner::visitXOR(SDNode *N) {
3326 SDValue N0 = N->getOperand(0);
3327 SDValue N1 = N->getOperand(1);
3328 SDValue LHS, RHS, CC;
3329 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3330 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3331 EVT VT = N0.getValueType();
3334 if (VT.isVector()) {
3335 SDValue FoldedVOp = SimplifyVBinOp(N);
3336 if (FoldedVOp.getNode()) return FoldedVOp;
3339 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3340 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3341 return DAG.getConstant(0, VT);
3342 // fold (xor x, undef) -> undef
3343 if (N0.getOpcode() == ISD::UNDEF)
3345 if (N1.getOpcode() == ISD::UNDEF)
3347 // fold (xor c1, c2) -> c1^c2
3349 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3350 // canonicalize constant to RHS
3352 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3353 // fold (xor x, 0) -> x
3354 if (N1C && N1C->isNullValue())
3357 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3358 if (RXOR.getNode() != 0)
3361 // fold !(x cc y) -> (x !cc y)
3362 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3363 bool isInt = LHS.getValueType().isInteger();
3364 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3367 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
3368 switch (N0.getOpcode()) {
3370 llvm_unreachable("Unhandled SetCC Equivalent!");
3372 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
3373 case ISD::SELECT_CC:
3374 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
3375 N0.getOperand(3), NotCC);
3380 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3381 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3382 N0.getNode()->hasOneUse() &&
3383 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3384 SDValue V = N0.getOperand(0);
3385 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3386 DAG.getConstant(1, V.getValueType()));
3387 AddToWorkList(V.getNode());
3388 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
3391 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3392 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3393 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3394 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3395 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3396 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3397 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3398 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3399 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3400 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3403 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3404 if (N1C && N1C->isAllOnesValue() &&
3405 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3406 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3407 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3408 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3409 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3410 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3411 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3412 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3415 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3416 if (N1C && N0.getOpcode() == ISD::XOR) {
3417 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3418 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3420 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3421 DAG.getConstant(N1C->getAPIntValue() ^
3422 N00C->getAPIntValue(), VT));
3424 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3425 DAG.getConstant(N1C->getAPIntValue() ^
3426 N01C->getAPIntValue(), VT));
3428 // fold (xor x, x) -> 0
3430 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
3432 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3433 if (N0.getOpcode() == N1.getOpcode()) {
3434 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3435 if (Tmp.getNode()) return Tmp;
3438 // Simplify the expression using non-local knowledge.
3439 if (!VT.isVector() &&
3440 SimplifyDemandedBits(SDValue(N, 0)))
3441 return SDValue(N, 0);
3446 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3447 /// the shift amount is a constant.
3448 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3449 SDNode *LHS = N->getOperand(0).getNode();
3450 if (!LHS->hasOneUse()) return SDValue();
3452 // We want to pull some binops through shifts, so that we have (and (shift))
3453 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3454 // thing happens with address calculations, so it's important to canonicalize
3456 bool HighBitSet = false; // Can we transform this if the high bit is set?
3458 switch (LHS->getOpcode()) {
3459 default: return SDValue();
3462 HighBitSet = false; // We can only transform sra if the high bit is clear.
3465 HighBitSet = true; // We can only transform sra if the high bit is set.
3468 if (N->getOpcode() != ISD::SHL)
3469 return SDValue(); // only shl(add) not sr[al](add).
3470 HighBitSet = false; // We can only transform sra if the high bit is clear.
3474 // We require the RHS of the binop to be a constant as well.
3475 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3476 if (!BinOpCst) return SDValue();
3478 // FIXME: disable this unless the input to the binop is a shift by a constant.
3479 // If it is not a shift, it pessimizes some common cases like:
3481 // void foo(int *X, int i) { X[i & 1235] = 1; }
3482 // int bar(int *X, int i) { return X[i & 255]; }
3483 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3484 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3485 BinOpLHSVal->getOpcode() != ISD::SRA &&
3486 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3487 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3490 EVT VT = N->getValueType(0);
3492 // If this is a signed shift right, and the high bit is modified by the
3493 // logical operation, do not perform the transformation. The highBitSet
3494 // boolean indicates the value of the high bit of the constant which would
3495 // cause it to be modified for this operation.
3496 if (N->getOpcode() == ISD::SRA) {
3497 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3498 if (BinOpRHSSignSet != HighBitSet)
3502 // Fold the constants, shifting the binop RHS by the shift amount.
3503 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
3505 LHS->getOperand(1), N->getOperand(1));
3507 // Create the new shift.
3508 SDValue NewShift = DAG.getNode(N->getOpcode(),
3509 LHS->getOperand(0).getDebugLoc(),
3510 VT, LHS->getOperand(0), N->getOperand(1));
3512 // Create the new binop.
3513 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
3516 SDValue DAGCombiner::visitSHL(SDNode *N) {
3517 SDValue N0 = N->getOperand(0);
3518 SDValue N1 = N->getOperand(1);
3519 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3520 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3521 EVT VT = N0.getValueType();
3522 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3524 // fold (shl c1, c2) -> c1<<c2
3526 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3527 // fold (shl 0, x) -> 0
3528 if (N0C && N0C->isNullValue())
3530 // fold (shl x, c >= size(x)) -> undef
3531 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3532 return DAG.getUNDEF(VT);
3533 // fold (shl x, 0) -> x
3534 if (N1C && N1C->isNullValue())
3536 // fold (shl undef, x) -> 0
3537 if (N0.getOpcode() == ISD::UNDEF)
3538 return DAG.getConstant(0, VT);
3539 // if (shl x, c) is known to be zero, return 0
3540 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3541 APInt::getAllOnesValue(OpSizeInBits)))
3542 return DAG.getConstant(0, VT);
3543 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3544 if (N1.getOpcode() == ISD::TRUNCATE &&
3545 N1.getOperand(0).getOpcode() == ISD::AND &&
3546 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3547 SDValue N101 = N1.getOperand(0).getOperand(1);
3548 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3549 EVT TruncVT = N1.getValueType();
3550 SDValue N100 = N1.getOperand(0).getOperand(0);
3551 APInt TruncC = N101C->getAPIntValue();
3552 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3553 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3554 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3555 DAG.getNode(ISD::TRUNCATE,
3558 DAG.getConstant(TruncC, TruncVT)));
3562 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3563 return SDValue(N, 0);
3565 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3566 if (N1C && N0.getOpcode() == ISD::SHL &&
3567 N0.getOperand(1).getOpcode() == ISD::Constant) {
3568 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3569 uint64_t c2 = N1C->getZExtValue();
3570 if (c1 + c2 >= OpSizeInBits)
3571 return DAG.getConstant(0, VT);
3572 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3573 DAG.getConstant(c1 + c2, N1.getValueType()));
3576 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3577 // For this to be valid, the second form must not preserve any of the bits
3578 // that are shifted out by the inner shift in the first form. This means
3579 // the outer shift size must be >= the number of bits added by the ext.
3580 // As a corollary, we don't care what kind of ext it is.
3581 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3582 N0.getOpcode() == ISD::ANY_EXTEND ||
3583 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3584 N0.getOperand(0).getOpcode() == ISD::SHL &&
3585 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3587 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3588 uint64_t c2 = N1C->getZExtValue();
3589 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3590 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3591 if (c2 >= OpSizeInBits - InnerShiftSize) {
3592 if (c1 + c2 >= OpSizeInBits)
3593 return DAG.getConstant(0, VT);
3594 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3595 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3596 N0.getOperand(0)->getOperand(0)),
3597 DAG.getConstant(c1 + c2, N1.getValueType()));
3601 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3602 // (and (srl x, (sub c1, c2), MASK)
3603 // Only fold this if the inner shift has no other uses -- if it does, folding
3604 // this will increase the total number of instructions.
3605 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3606 N0.getOperand(1).getOpcode() == ISD::Constant) {
3607 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3608 if (c1 < VT.getSizeInBits()) {
3609 uint64_t c2 = N1C->getZExtValue();
3610 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3611 VT.getSizeInBits() - c1);
3614 Mask = Mask.shl(c2-c1);
3615 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3616 DAG.getConstant(c2-c1, N1.getValueType()));
3618 Mask = Mask.lshr(c1-c2);
3619 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3620 DAG.getConstant(c1-c2, N1.getValueType()));
3622 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3623 DAG.getConstant(Mask, VT));
3626 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3627 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3628 SDValue HiBitsMask =
3629 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3630 VT.getSizeInBits() -
3631 N1C->getZExtValue()),
3633 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3638 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3639 if (NewSHL.getNode())
3646 SDValue DAGCombiner::visitSRA(SDNode *N) {
3647 SDValue N0 = N->getOperand(0);
3648 SDValue N1 = N->getOperand(1);
3649 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3650 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3651 EVT VT = N0.getValueType();
3652 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3654 // fold (sra c1, c2) -> (sra c1, c2)
3656 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3657 // fold (sra 0, x) -> 0
3658 if (N0C && N0C->isNullValue())
3660 // fold (sra -1, x) -> -1
3661 if (N0C && N0C->isAllOnesValue())
3663 // fold (sra x, (setge c, size(x))) -> undef
3664 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3665 return DAG.getUNDEF(VT);
3666 // fold (sra x, 0) -> x
3667 if (N1C && N1C->isNullValue())
3669 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3671 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3672 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3673 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3675 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3676 ExtVT, VT.getVectorNumElements());
3677 if ((!LegalOperations ||
3678 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3679 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3680 N0.getOperand(0), DAG.getValueType(ExtVT));
3683 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3684 if (N1C && N0.getOpcode() == ISD::SRA) {
3685 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3686 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3687 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3688 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3689 DAG.getConstant(Sum, N1C->getValueType(0)));
3693 // fold (sra (shl X, m), (sub result_size, n))
3694 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3695 // result_size - n != m.
3696 // If truncate is free for the target sext(shl) is likely to result in better
3698 if (N0.getOpcode() == ISD::SHL) {
3699 // Get the two constanst of the shifts, CN0 = m, CN = n.
3700 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3702 // Determine what the truncate's result bitsize and type would be.
3704 EVT::getIntegerVT(*DAG.getContext(),
3705 OpSizeInBits - N1C->getZExtValue());
3706 // Determine the residual right-shift amount.
3707 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3709 // If the shift is not a no-op (in which case this should be just a sign
3710 // extend already), the truncated to type is legal, sign_extend is legal
3711 // on that type, and the truncate to that type is both legal and free,
3712 // perform the transform.
3713 if ((ShiftAmt > 0) &&
3714 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3715 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3716 TLI.isTruncateFree(VT, TruncVT)) {
3718 SDValue Amt = DAG.getConstant(ShiftAmt,
3719 getShiftAmountTy(N0.getOperand(0).getValueType()));
3720 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3721 N0.getOperand(0), Amt);
3722 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3724 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3725 N->getValueType(0), Trunc);
3730 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3731 if (N1.getOpcode() == ISD::TRUNCATE &&
3732 N1.getOperand(0).getOpcode() == ISD::AND &&
3733 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3734 SDValue N101 = N1.getOperand(0).getOperand(1);
3735 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3736 EVT TruncVT = N1.getValueType();
3737 SDValue N100 = N1.getOperand(0).getOperand(0);
3738 APInt TruncC = N101C->getAPIntValue();
3739 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3740 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3741 DAG.getNode(ISD::AND, N->getDebugLoc(),
3743 DAG.getNode(ISD::TRUNCATE,
3746 DAG.getConstant(TruncC, TruncVT)));
3750 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3751 // if c1 is equal to the number of bits the trunc removes
3752 if (N0.getOpcode() == ISD::TRUNCATE &&
3753 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3754 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3755 N0.getOperand(0).hasOneUse() &&
3756 N0.getOperand(0).getOperand(1).hasOneUse() &&
3757 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3758 EVT LargeVT = N0.getOperand(0).getValueType();
3759 ConstantSDNode *LargeShiftAmt =
3760 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3762 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3763 LargeShiftAmt->getZExtValue()) {
3765 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3766 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3767 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3768 N0.getOperand(0).getOperand(0), Amt);
3769 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3773 // Simplify, based on bits shifted out of the LHS.
3774 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3775 return SDValue(N, 0);
3778 // If the sign bit is known to be zero, switch this to a SRL.
3779 if (DAG.SignBitIsZero(N0))
3780 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3783 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3784 if (NewSRA.getNode())
3791 SDValue DAGCombiner::visitSRL(SDNode *N) {
3792 SDValue N0 = N->getOperand(0);
3793 SDValue N1 = N->getOperand(1);
3794 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3795 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3796 EVT VT = N0.getValueType();
3797 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3799 // fold (srl c1, c2) -> c1 >>u c2
3801 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3802 // fold (srl 0, x) -> 0
3803 if (N0C && N0C->isNullValue())
3805 // fold (srl x, c >= size(x)) -> undef
3806 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3807 return DAG.getUNDEF(VT);
3808 // fold (srl x, 0) -> x
3809 if (N1C && N1C->isNullValue())
3811 // if (srl x, c) is known to be zero, return 0
3812 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3813 APInt::getAllOnesValue(OpSizeInBits)))
3814 return DAG.getConstant(0, VT);
3816 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3817 if (N1C && N0.getOpcode() == ISD::SRL &&
3818 N0.getOperand(1).getOpcode() == ISD::Constant) {
3819 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3820 uint64_t c2 = N1C->getZExtValue();
3821 if (c1 + c2 >= OpSizeInBits)
3822 return DAG.getConstant(0, VT);
3823 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3824 DAG.getConstant(c1 + c2, N1.getValueType()));
3827 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3828 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3829 N0.getOperand(0).getOpcode() == ISD::SRL &&
3830 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3832 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3833 uint64_t c2 = N1C->getZExtValue();
3834 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3835 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3836 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3837 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3838 if (c1 + OpSizeInBits == InnerShiftSize) {
3839 if (c1 + c2 >= InnerShiftSize)
3840 return DAG.getConstant(0, VT);
3841 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3842 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3843 N0.getOperand(0)->getOperand(0),
3844 DAG.getConstant(c1 + c2, ShiftCountVT)));
3848 // fold (srl (shl x, c), c) -> (and x, cst2)
3849 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3850 N0.getValueSizeInBits() <= 64) {
3851 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3852 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3853 DAG.getConstant(~0ULL >> ShAmt, VT));
3857 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3858 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3859 // Shifting in all undef bits?
3860 EVT SmallVT = N0.getOperand(0).getValueType();
3861 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3862 return DAG.getUNDEF(VT);
3864 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3865 uint64_t ShiftAmt = N1C->getZExtValue();
3866 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3868 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3869 AddToWorkList(SmallShift.getNode());
3870 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3874 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3875 // bit, which is unmodified by sra.
3876 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3877 if (N0.getOpcode() == ISD::SRA)
3878 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3881 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3882 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3883 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3884 APInt KnownZero, KnownOne;
3885 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne);
3887 // If any of the input bits are KnownOne, then the input couldn't be all
3888 // zeros, thus the result of the srl will always be zero.
3889 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3891 // If all of the bits input the to ctlz node are known to be zero, then
3892 // the result of the ctlz is "32" and the result of the shift is one.
3893 APInt UnknownBits = ~KnownZero;
3894 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3896 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3897 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3898 // Okay, we know that only that the single bit specified by UnknownBits
3899 // could be set on input to the CTLZ node. If this bit is set, the SRL
3900 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3901 // to an SRL/XOR pair, which is likely to simplify more.
3902 unsigned ShAmt = UnknownBits.countTrailingZeros();
3903 SDValue Op = N0.getOperand(0);
3906 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3907 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3908 AddToWorkList(Op.getNode());
3911 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3912 Op, DAG.getConstant(1, VT));
3916 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3917 if (N1.getOpcode() == ISD::TRUNCATE &&
3918 N1.getOperand(0).getOpcode() == ISD::AND &&
3919 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3920 SDValue N101 = N1.getOperand(0).getOperand(1);
3921 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3922 EVT TruncVT = N1.getValueType();
3923 SDValue N100 = N1.getOperand(0).getOperand(0);
3924 APInt TruncC = N101C->getAPIntValue();
3925 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3926 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3927 DAG.getNode(ISD::AND, N->getDebugLoc(),
3929 DAG.getNode(ISD::TRUNCATE,
3932 DAG.getConstant(TruncC, TruncVT)));
3936 // fold operands of srl based on knowledge that the low bits are not
3938 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3939 return SDValue(N, 0);
3942 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3943 if (NewSRL.getNode())
3947 // Attempt to convert a srl of a load into a narrower zero-extending load.
3948 SDValue NarrowLoad = ReduceLoadWidth(N);
3949 if (NarrowLoad.getNode())
3952 // Here is a common situation. We want to optimize:
3955 // %b = and i32 %a, 2
3956 // %c = srl i32 %b, 1
3957 // brcond i32 %c ...
3963 // %c = setcc eq %b, 0
3966 // However when after the source operand of SRL is optimized into AND, the SRL
3967 // itself may not be optimized further. Look for it and add the BRCOND into
3969 if (N->hasOneUse()) {
3970 SDNode *Use = *N->use_begin();
3971 if (Use->getOpcode() == ISD::BRCOND)
3973 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3974 // Also look pass the truncate.
3975 Use = *Use->use_begin();
3976 if (Use->getOpcode() == ISD::BRCOND)
3984 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3985 SDValue N0 = N->getOperand(0);
3986 EVT VT = N->getValueType(0);
3988 // fold (ctlz c1) -> c2
3989 if (isa<ConstantSDNode>(N0))
3990 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3994 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
3995 SDValue N0 = N->getOperand(0);
3996 EVT VT = N->getValueType(0);
3998 // fold (ctlz_zero_undef c1) -> c2
3999 if (isa<ConstantSDNode>(N0))
4000 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
4004 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
4005 SDValue N0 = N->getOperand(0);
4006 EVT VT = N->getValueType(0);
4008 // fold (cttz c1) -> c2
4009 if (isa<ConstantSDNode>(N0))
4010 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
4014 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
4015 SDValue N0 = N->getOperand(0);
4016 EVT VT = N->getValueType(0);
4018 // fold (cttz_zero_undef c1) -> c2
4019 if (isa<ConstantSDNode>(N0))
4020 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
4024 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4025 SDValue N0 = N->getOperand(0);
4026 EVT VT = N->getValueType(0);
4028 // fold (ctpop c1) -> c2
4029 if (isa<ConstantSDNode>(N0))
4030 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
4034 SDValue DAGCombiner::visitSELECT(SDNode *N) {
4035 SDValue N0 = N->getOperand(0);
4036 SDValue N1 = N->getOperand(1);
4037 SDValue N2 = N->getOperand(2);
4038 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4039 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4040 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
4041 EVT VT = N->getValueType(0);
4042 EVT VT0 = N0.getValueType();
4044 // fold (select C, X, X) -> X
4047 // fold (select true, X, Y) -> X
4048 if (N0C && !N0C->isNullValue())
4050 // fold (select false, X, Y) -> Y
4051 if (N0C && N0C->isNullValue())
4053 // fold (select C, 1, X) -> (or C, X)
4054 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
4055 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4056 // fold (select C, 0, 1) -> (xor C, 1)
4057 if (VT.isInteger() &&
4060 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) &&
4061 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
4064 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
4065 N0, DAG.getConstant(1, VT0));
4066 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
4067 N0, DAG.getConstant(1, VT0));
4068 AddToWorkList(XORNode.getNode());
4070 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
4071 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
4073 // fold (select C, 0, X) -> (and (not C), X)
4074 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
4075 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
4076 AddToWorkList(NOTNode.getNode());
4077 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
4079 // fold (select C, X, 1) -> (or (not C), X)
4080 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
4081 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
4082 AddToWorkList(NOTNode.getNode());
4083 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
4085 // fold (select C, X, 0) -> (and C, X)
4086 if (VT == MVT::i1 && N2C && N2C->isNullValue())
4087 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4088 // fold (select X, X, Y) -> (or X, Y)
4089 // fold (select X, 1, Y) -> (or X, Y)
4090 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4091 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4092 // fold (select X, Y, X) -> (and X, Y)
4093 // fold (select X, Y, 0) -> (and X, Y)
4094 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4095 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4097 // If we can fold this based on the true/false value, do so.
4098 if (SimplifySelectOps(N, N1, N2))
4099 return SDValue(N, 0); // Don't revisit N.
4101 // fold selects based on a setcc into other things, such as min/max/abs
4102 if (N0.getOpcode() == ISD::SETCC) {
4104 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
4105 // having to say they don't support SELECT_CC on every type the DAG knows
4106 // about, since there is no way to mark an opcode illegal at all value types
4107 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
4108 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
4109 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
4110 N0.getOperand(0), N0.getOperand(1),
4111 N1, N2, N0.getOperand(2));
4112 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
4118 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
4119 SDValue N0 = N->getOperand(0);
4120 SDValue N1 = N->getOperand(1);
4121 SDValue N2 = N->getOperand(2);
4122 SDValue N3 = N->getOperand(3);
4123 SDValue N4 = N->getOperand(4);
4124 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
4126 // fold select_cc lhs, rhs, x, x, cc -> x
4130 // Determine if the condition we're dealing with is constant
4131 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
4132 N0, N1, CC, N->getDebugLoc(), false);
4133 if (SCC.getNode()) AddToWorkList(SCC.getNode());
4135 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
4136 if (!SCCC->isNullValue())
4137 return N2; // cond always true -> true val
4139 return N3; // cond always false -> false val
4142 // Fold to a simpler select_cc
4143 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
4144 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
4145 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
4148 // If we can fold this based on the true/false value, do so.
4149 if (SimplifySelectOps(N, N2, N3))
4150 return SDValue(N, 0); // Don't revisit N.
4152 // fold select_cc into other things, such as min/max/abs
4153 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
4156 SDValue DAGCombiner::visitSETCC(SDNode *N) {
4157 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
4158 cast<CondCodeSDNode>(N->getOperand(2))->get(),
4162 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
4163 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
4164 // transformation. Returns true if extension are possible and the above
4165 // mentioned transformation is profitable.
4166 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
4168 SmallVector<SDNode*, 4> &ExtendNodes,
4169 const TargetLowering &TLI) {
4170 bool HasCopyToRegUses = false;
4171 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
4172 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4173 UE = N0.getNode()->use_end();
4178 if (UI.getUse().getResNo() != N0.getResNo())
4180 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
4181 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4182 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
4183 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
4184 // Sign bits will be lost after a zext.
4187 for (unsigned i = 0; i != 2; ++i) {
4188 SDValue UseOp = User->getOperand(i);
4191 if (!isa<ConstantSDNode>(UseOp))
4196 ExtendNodes.push_back(User);
4199 // If truncates aren't free and there are users we can't
4200 // extend, it isn't worthwhile.
4203 // Remember if this value is live-out.
4204 if (User->getOpcode() == ISD::CopyToReg)
4205 HasCopyToRegUses = true;
4208 if (HasCopyToRegUses) {
4209 bool BothLiveOut = false;
4210 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4212 SDUse &Use = UI.getUse();
4213 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4219 // Both unextended and extended values are live out. There had better be
4220 // a good reason for the transformation.
4221 return ExtendNodes.size();
4226 void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
4227 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
4228 ISD::NodeType ExtType) {
4229 // Extend SetCC uses if necessary.
4230 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4231 SDNode *SetCC = SetCCs[i];
4232 SmallVector<SDValue, 4> Ops;
4234 for (unsigned j = 0; j != 2; ++j) {
4235 SDValue SOp = SetCC->getOperand(j);
4237 Ops.push_back(ExtLoad);
4239 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
4242 Ops.push_back(SetCC->getOperand(2));
4243 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
4244 &Ops[0], Ops.size()));
4248 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
4249 SDValue N0 = N->getOperand(0);
4250 EVT VT = N->getValueType(0);
4252 // fold (sext c1) -> c1
4253 if (isa<ConstantSDNode>(N0))
4254 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
4256 // fold (sext (sext x)) -> (sext x)
4257 // fold (sext (aext x)) -> (sext x)
4258 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4259 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
4262 if (N0.getOpcode() == ISD::TRUNCATE) {
4263 // fold (sext (truncate (load x))) -> (sext (smaller load x))
4264 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
4265 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4266 if (NarrowLoad.getNode()) {
4267 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4268 if (NarrowLoad.getNode() != N0.getNode()) {
4269 CombineTo(N0.getNode(), NarrowLoad);
4270 // CombineTo deleted the truncate, if needed, but not what's under it.
4273 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4276 // See if the value being truncated is already sign extended. If so, just
4277 // eliminate the trunc/sext pair.
4278 SDValue Op = N0.getOperand(0);
4279 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
4280 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
4281 unsigned DestBits = VT.getScalarType().getSizeInBits();
4282 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
4284 if (OpBits == DestBits) {
4285 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
4286 // bits, it is already ready.
4287 if (NumSignBits > DestBits-MidBits)
4289 } else if (OpBits < DestBits) {
4290 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
4291 // bits, just sext from i32.
4292 if (NumSignBits > OpBits-MidBits)
4293 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
4295 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
4296 // bits, just truncate to i32.
4297 if (NumSignBits > OpBits-MidBits)
4298 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4301 // fold (sext (truncate x)) -> (sextinreg x).
4302 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4303 N0.getValueType())) {
4304 if (OpBits < DestBits)
4305 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4306 else if (OpBits > DestBits)
4307 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4308 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
4309 DAG.getValueType(N0.getValueType()));
4313 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4314 // None of the supported targets knows how to perform load and sign extend
4315 // on vectors in one instruction. We only perform this transformation on
4317 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4318 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4319 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4320 bool DoXform = true;
4321 SmallVector<SDNode*, 4> SetCCs;
4322 if (!N0.hasOneUse())
4323 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4325 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4326 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4328 LN0->getBasePtr(), LN0->getPointerInfo(),
4330 LN0->isVolatile(), LN0->isNonTemporal(),
4331 LN0->getAlignment());
4332 CombineTo(N, ExtLoad);
4333 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4334 N0.getValueType(), ExtLoad);
4335 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4336 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4338 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4342 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4343 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4344 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4345 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4346 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4347 EVT MemVT = LN0->getMemoryVT();
4348 if ((!LegalOperations && !LN0->isVolatile()) ||
4349 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4350 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4352 LN0->getBasePtr(), LN0->getPointerInfo(),
4354 LN0->isVolatile(), LN0->isNonTemporal(),
4355 LN0->getAlignment());
4356 CombineTo(N, ExtLoad);
4357 CombineTo(N0.getNode(),
4358 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4359 N0.getValueType(), ExtLoad),
4360 ExtLoad.getValue(1));
4361 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4365 // fold (sext (and/or/xor (load x), cst)) ->
4366 // (and/or/xor (sextload x), (sext cst))
4367 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4368 N0.getOpcode() == ISD::XOR) &&
4369 isa<LoadSDNode>(N0.getOperand(0)) &&
4370 N0.getOperand(1).getOpcode() == ISD::Constant &&
4371 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4372 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4373 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4374 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4375 bool DoXform = true;
4376 SmallVector<SDNode*, 4> SetCCs;
4377 if (!N0.hasOneUse())
4378 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4381 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4382 LN0->getChain(), LN0->getBasePtr(),
4383 LN0->getPointerInfo(),
4386 LN0->isNonTemporal(),
4387 LN0->getAlignment());
4388 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4389 Mask = Mask.sext(VT.getSizeInBits());
4390 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4391 ExtLoad, DAG.getConstant(Mask, VT));
4392 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4393 N0.getOperand(0).getDebugLoc(),
4394 N0.getOperand(0).getValueType(), ExtLoad);
4396 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4397 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4399 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4404 if (N0.getOpcode() == ISD::SETCC) {
4405 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4406 // Only do this before legalize for now.
4407 if (VT.isVector() && !LegalOperations) {
4408 EVT N0VT = N0.getOperand(0).getValueType();
4409 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
4410 // of the same size as the compared operands. Only optimize sext(setcc())
4411 // if this is the case.
4412 EVT SVT = TLI.getSetCCResultType(N0VT);
4414 // We know that the # elements of the results is the same as the
4415 // # elements of the compare (and the # elements of the compare result
4416 // for that matter). Check to see that they are the same size. If so,
4417 // we know that the element size of the sext'd result matches the
4418 // element size of the compare operands.
4419 if (VT.getSizeInBits() == SVT.getSizeInBits())
4420 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4422 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4423 // If the desired elements are smaller or larger than the source
4424 // elements we can use a matching integer vector type and then
4425 // truncate/sign extend
4427 EVT MatchingElementType =
4428 EVT::getIntegerVT(*DAG.getContext(),
4429 N0VT.getScalarType().getSizeInBits());
4430 EVT MatchingVectorType =
4431 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4432 N0VT.getVectorNumElements());
4434 if (SVT == MatchingVectorType) {
4435 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType,
4436 N0.getOperand(0), N0.getOperand(1),
4437 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4438 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4443 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4444 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4446 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4448 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4449 NegOne, DAG.getConstant(0, VT),
4450 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4451 if (SCC.getNode()) return SCC;
4452 if (!LegalOperations ||
4453 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
4454 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4455 DAG.getSetCC(N->getDebugLoc(),
4456 TLI.getSetCCResultType(VT),
4457 N0.getOperand(0), N0.getOperand(1),
4458 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4459 NegOne, DAG.getConstant(0, VT));
4462 // fold (sext x) -> (zext x) if the sign bit is known zero.
4463 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4464 DAG.SignBitIsZero(N0))
4465 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4470 // isTruncateOf - If N is a truncate of some other value, return true, record
4471 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
4472 // This function computes KnownZero to avoid a duplicated call to
4473 // ComputeMaskedBits in the caller.
4474 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
4477 if (N->getOpcode() == ISD::TRUNCATE) {
4478 Op = N->getOperand(0);
4479 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4483 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
4484 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
4487 SDValue Op0 = N->getOperand(0);
4488 SDValue Op1 = N->getOperand(1);
4489 assert(Op0.getValueType() == Op1.getValueType());
4491 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0);
4492 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
4493 if (COp0 && COp0->isNullValue())
4495 else if (COp1 && COp1->isNullValue())
4500 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4502 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
4508 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4509 SDValue N0 = N->getOperand(0);
4510 EVT VT = N->getValueType(0);
4512 // fold (zext c1) -> c1
4513 if (isa<ConstantSDNode>(N0))
4514 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4515 // fold (zext (zext x)) -> (zext x)
4516 // fold (zext (aext x)) -> (zext x)
4517 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4518 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
4521 // fold (zext (truncate x)) -> (zext x) or
4522 // (zext (truncate x)) -> (truncate x)
4523 // This is valid when the truncated bits of x are already zero.
4524 // FIXME: We should extend this to work for vectors too.
4527 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
4528 APInt TruncatedBits =
4529 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
4530 APInt(Op.getValueSizeInBits(), 0) :
4531 APInt::getBitsSet(Op.getValueSizeInBits(),
4532 N0.getValueSizeInBits(),
4533 std::min(Op.getValueSizeInBits(),
4534 VT.getSizeInBits()));
4535 if (TruncatedBits == (KnownZero & TruncatedBits)) {
4536 if (VT.bitsGT(Op.getValueType()))
4537 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op);
4538 if (VT.bitsLT(Op.getValueType()))
4539 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4545 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4546 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4547 if (N0.getOpcode() == ISD::TRUNCATE) {
4548 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4549 if (NarrowLoad.getNode()) {
4550 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4551 if (NarrowLoad.getNode() != N0.getNode()) {
4552 CombineTo(N0.getNode(), NarrowLoad);
4553 // CombineTo deleted the truncate, if needed, but not what's under it.
4556 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4560 // fold (zext (truncate x)) -> (and x, mask)
4561 if (N0.getOpcode() == ISD::TRUNCATE &&
4562 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4564 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4565 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4566 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4567 if (NarrowLoad.getNode()) {
4568 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4569 if (NarrowLoad.getNode() != N0.getNode()) {
4570 CombineTo(N0.getNode(), NarrowLoad);
4571 // CombineTo deleted the truncate, if needed, but not what's under it.
4574 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4577 SDValue Op = N0.getOperand(0);
4578 if (Op.getValueType().bitsLT(VT)) {
4579 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
4580 AddToWorkList(Op.getNode());
4581 } else if (Op.getValueType().bitsGT(VT)) {
4582 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4583 AddToWorkList(Op.getNode());
4585 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
4586 N0.getValueType().getScalarType());
4589 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4590 // if either of the casts is not free.
4591 if (N0.getOpcode() == ISD::AND &&
4592 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4593 N0.getOperand(1).getOpcode() == ISD::Constant &&
4594 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4595 N0.getValueType()) ||
4596 !TLI.isZExtFree(N0.getValueType(), VT))) {
4597 SDValue X = N0.getOperand(0).getOperand(0);
4598 if (X.getValueType().bitsLT(VT)) {
4599 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
4600 } else if (X.getValueType().bitsGT(VT)) {
4601 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4603 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4604 Mask = Mask.zext(VT.getSizeInBits());
4605 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4606 X, DAG.getConstant(Mask, VT));
4609 // fold (zext (load x)) -> (zext (truncate (zextload x)))
4610 // None of the supported targets knows how to perform load and vector_zext
4611 // on vectors in one instruction. We only perform this transformation on
4613 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4614 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4615 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4616 bool DoXform = true;
4617 SmallVector<SDNode*, 4> SetCCs;
4618 if (!N0.hasOneUse())
4619 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4621 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4622 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4624 LN0->getBasePtr(), LN0->getPointerInfo(),
4626 LN0->isVolatile(), LN0->isNonTemporal(),
4627 LN0->getAlignment());
4628 CombineTo(N, ExtLoad);
4629 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4630 N0.getValueType(), ExtLoad);
4631 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4633 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4635 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4639 // fold (zext (and/or/xor (load x), cst)) ->
4640 // (and/or/xor (zextload x), (zext cst))
4641 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4642 N0.getOpcode() == ISD::XOR) &&
4643 isa<LoadSDNode>(N0.getOperand(0)) &&
4644 N0.getOperand(1).getOpcode() == ISD::Constant &&
4645 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4646 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4647 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4648 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4649 bool DoXform = true;
4650 SmallVector<SDNode*, 4> SetCCs;
4651 if (!N0.hasOneUse())
4652 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4655 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
4656 LN0->getChain(), LN0->getBasePtr(),
4657 LN0->getPointerInfo(),
4660 LN0->isNonTemporal(),
4661 LN0->getAlignment());
4662 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4663 Mask = Mask.zext(VT.getSizeInBits());
4664 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4665 ExtLoad, DAG.getConstant(Mask, VT));
4666 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4667 N0.getOperand(0).getDebugLoc(),
4668 N0.getOperand(0).getValueType(), ExtLoad);
4670 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4671 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4673 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4678 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4679 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4680 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4681 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4682 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4683 EVT MemVT = LN0->getMemoryVT();
4684 if ((!LegalOperations && !LN0->isVolatile()) ||
4685 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4686 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4688 LN0->getBasePtr(), LN0->getPointerInfo(),
4690 LN0->isVolatile(), LN0->isNonTemporal(),
4691 LN0->getAlignment());
4692 CombineTo(N, ExtLoad);
4693 CombineTo(N0.getNode(),
4694 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4696 ExtLoad.getValue(1));
4697 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4701 if (N0.getOpcode() == ISD::SETCC) {
4702 if (!LegalOperations && VT.isVector()) {
4703 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4704 // Only do this before legalize for now.
4705 EVT N0VT = N0.getOperand(0).getValueType();
4706 EVT EltVT = VT.getVectorElementType();
4707 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4708 DAG.getConstant(1, EltVT));
4709 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4710 // We know that the # elements of the results is the same as the
4711 // # elements of the compare (and the # elements of the compare result
4712 // for that matter). Check to see that they are the same size. If so,
4713 // we know that the element size of the sext'd result matches the
4714 // element size of the compare operands.
4715 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4716 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4718 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4719 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4720 &OneOps[0], OneOps.size()));
4722 // If the desired elements are smaller or larger than the source
4723 // elements we can use a matching integer vector type and then
4724 // truncate/sign extend
4725 EVT MatchingElementType =
4726 EVT::getIntegerVT(*DAG.getContext(),
4727 N0VT.getScalarType().getSizeInBits());
4728 EVT MatchingVectorType =
4729 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4730 N0VT.getVectorNumElements());
4732 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4734 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4735 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4736 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4737 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4738 &OneOps[0], OneOps.size()));
4741 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4743 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4744 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4745 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4746 if (SCC.getNode()) return SCC;
4749 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4750 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4751 isa<ConstantSDNode>(N0.getOperand(1)) &&
4752 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4754 SDValue ShAmt = N0.getOperand(1);
4755 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4756 if (N0.getOpcode() == ISD::SHL) {
4757 SDValue InnerZExt = N0.getOperand(0);
4758 // If the original shl may be shifting out bits, do not perform this
4760 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4761 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4762 if (ShAmtVal > KnownZeroBits)
4766 DebugLoc DL = N->getDebugLoc();
4768 // Ensure that the shift amount is wide enough for the shifted value.
4769 if (VT.getSizeInBits() >= 256)
4770 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4772 return DAG.getNode(N0.getOpcode(), DL, VT,
4773 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4780 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4781 SDValue N0 = N->getOperand(0);
4782 EVT VT = N->getValueType(0);
4784 // fold (aext c1) -> c1
4785 if (isa<ConstantSDNode>(N0))
4786 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4787 // fold (aext (aext x)) -> (aext x)
4788 // fold (aext (zext x)) -> (zext x)
4789 // fold (aext (sext x)) -> (sext x)
4790 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4791 N0.getOpcode() == ISD::ZERO_EXTEND ||
4792 N0.getOpcode() == ISD::SIGN_EXTEND)
4793 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4795 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4796 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4797 if (N0.getOpcode() == ISD::TRUNCATE) {
4798 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4799 if (NarrowLoad.getNode()) {
4800 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4801 if (NarrowLoad.getNode() != N0.getNode()) {
4802 CombineTo(N0.getNode(), NarrowLoad);
4803 // CombineTo deleted the truncate, if needed, but not what's under it.
4806 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4810 // fold (aext (truncate x))
4811 if (N0.getOpcode() == ISD::TRUNCATE) {
4812 SDValue TruncOp = N0.getOperand(0);
4813 if (TruncOp.getValueType() == VT)
4814 return TruncOp; // x iff x size == zext size.
4815 if (TruncOp.getValueType().bitsGT(VT))
4816 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4817 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4820 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4821 // if the trunc is not free.
4822 if (N0.getOpcode() == ISD::AND &&
4823 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4824 N0.getOperand(1).getOpcode() == ISD::Constant &&
4825 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4826 N0.getValueType())) {
4827 SDValue X = N0.getOperand(0).getOperand(0);
4828 if (X.getValueType().bitsLT(VT)) {
4829 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4830 } else if (X.getValueType().bitsGT(VT)) {
4831 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4833 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4834 Mask = Mask.zext(VT.getSizeInBits());
4835 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4836 X, DAG.getConstant(Mask, VT));
4839 // fold (aext (load x)) -> (aext (truncate (extload x)))
4840 // None of the supported targets knows how to perform load and any_ext
4841 // on vectors in one instruction. We only perform this transformation on
4843 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4844 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4845 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4846 bool DoXform = true;
4847 SmallVector<SDNode*, 4> SetCCs;
4848 if (!N0.hasOneUse())
4849 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4851 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4852 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4854 LN0->getBasePtr(), LN0->getPointerInfo(),
4856 LN0->isVolatile(), LN0->isNonTemporal(),
4857 LN0->getAlignment());
4858 CombineTo(N, ExtLoad);
4859 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4860 N0.getValueType(), ExtLoad);
4861 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4862 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4864 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4868 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4869 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4870 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4871 if (N0.getOpcode() == ISD::LOAD &&
4872 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4874 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4875 EVT MemVT = LN0->getMemoryVT();
4876 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4877 VT, LN0->getChain(), LN0->getBasePtr(),
4878 LN0->getPointerInfo(), MemVT,
4879 LN0->isVolatile(), LN0->isNonTemporal(),
4880 LN0->getAlignment());
4881 CombineTo(N, ExtLoad);
4882 CombineTo(N0.getNode(),
4883 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4884 N0.getValueType(), ExtLoad),
4885 ExtLoad.getValue(1));
4886 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4889 if (N0.getOpcode() == ISD::SETCC) {
4890 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4891 // Only do this before legalize for now.
4892 if (VT.isVector() && !LegalOperations) {
4893 EVT N0VT = N0.getOperand(0).getValueType();
4894 // We know that the # elements of the results is the same as the
4895 // # elements of the compare (and the # elements of the compare result
4896 // for that matter). Check to see that they are the same size. If so,
4897 // we know that the element size of the sext'd result matches the
4898 // element size of the compare operands.
4899 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4900 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4902 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4903 // If the desired elements are smaller or larger than the source
4904 // elements we can use a matching integer vector type and then
4905 // truncate/sign extend
4907 EVT MatchingElementType =
4908 EVT::getIntegerVT(*DAG.getContext(),
4909 N0VT.getScalarType().getSizeInBits());
4910 EVT MatchingVectorType =
4911 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4912 N0VT.getVectorNumElements());
4914 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4916 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4917 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4921 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4923 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4924 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4925 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4933 /// GetDemandedBits - See if the specified operand can be simplified with the
4934 /// knowledge that only the bits specified by Mask are used. If so, return the
4935 /// simpler operand, otherwise return a null SDValue.
4936 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4937 switch (V.getOpcode()) {
4939 case ISD::Constant: {
4940 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
4941 assert(CV != 0 && "Const value should be ConstSDNode.");
4942 const APInt &CVal = CV->getAPIntValue();
4943 APInt NewVal = CVal & Mask;
4944 if (NewVal != CVal) {
4945 return DAG.getConstant(NewVal, V.getValueType());
4951 // If the LHS or RHS don't contribute bits to the or, drop them.
4952 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4953 return V.getOperand(1);
4954 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4955 return V.getOperand(0);
4958 // Only look at single-use SRLs.
4959 if (!V.getNode()->hasOneUse())
4961 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4962 // See if we can recursively simplify the LHS.
4963 unsigned Amt = RHSC->getZExtValue();
4965 // Watch out for shift count overflow though.
4966 if (Amt >= Mask.getBitWidth()) break;
4967 APInt NewMask = Mask << Amt;
4968 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4969 if (SimplifyLHS.getNode())
4970 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4971 SimplifyLHS, V.getOperand(1));
4977 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4978 /// bits and then truncated to a narrower type and where N is a multiple
4979 /// of number of bits of the narrower type, transform it to a narrower load
4980 /// from address + N / num of bits of new type. If the result is to be
4981 /// extended, also fold the extension to form a extending load.
4982 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4983 unsigned Opc = N->getOpcode();
4985 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4986 SDValue N0 = N->getOperand(0);
4987 EVT VT = N->getValueType(0);
4990 // This transformation isn't valid for vector loads.
4994 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4996 if (Opc == ISD::SIGN_EXTEND_INREG) {
4997 ExtType = ISD::SEXTLOAD;
4998 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4999 } else if (Opc == ISD::SRL) {
5000 // Another special-case: SRL is basically zero-extending a narrower value.
5001 ExtType = ISD::ZEXTLOAD;
5003 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5004 if (!N01) return SDValue();
5005 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
5006 VT.getSizeInBits() - N01->getZExtValue());
5008 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
5011 unsigned EVTBits = ExtVT.getSizeInBits();
5013 // Do not generate loads of non-round integer types since these can
5014 // be expensive (and would be wrong if the type is not byte sized).
5015 if (!ExtVT.isRound())
5019 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5020 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5021 ShAmt = N01->getZExtValue();
5022 // Is the shift amount a multiple of size of VT?
5023 if ((ShAmt & (EVTBits-1)) == 0) {
5024 N0 = N0.getOperand(0);
5025 // Is the load width a multiple of size of VT?
5026 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
5030 // At this point, we must have a load or else we can't do the transform.
5031 if (!isa<LoadSDNode>(N0)) return SDValue();
5033 // If the shift amount is larger than the input type then we're not
5034 // accessing any of the loaded bytes. If the load was a zextload/extload
5035 // then the result of the shift+trunc is zero/undef (handled elsewhere).
5036 // If the load was a sextload then the result is a splat of the sign bit
5037 // of the extended byte. This is not worth optimizing for.
5038 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
5043 // If the load is shifted left (and the result isn't shifted back right),
5044 // we can fold the truncate through the shift.
5045 unsigned ShLeftAmt = 0;
5046 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
5047 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
5048 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5049 ShLeftAmt = N01->getZExtValue();
5050 N0 = N0.getOperand(0);
5054 // If we haven't found a load, we can't narrow it. Don't transform one with
5055 // multiple uses, this would require adding a new load.
5056 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
5057 // Don't change the width of a volatile load.
5058 cast<LoadSDNode>(N0)->isVolatile())
5061 // Verify that we are actually reducing a load width here.
5062 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
5065 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5066 EVT PtrType = N0.getOperand(1).getValueType();
5068 if (PtrType == MVT::Untyped || PtrType.isExtended())
5069 // It's not possible to generate a constant of extended or untyped type.
5072 // For big endian targets, we need to adjust the offset to the pointer to
5073 // load the correct bytes.
5074 if (TLI.isBigEndian()) {
5075 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
5076 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
5077 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
5080 uint64_t PtrOff = ShAmt / 8;
5081 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
5082 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
5083 PtrType, LN0->getBasePtr(),
5084 DAG.getConstant(PtrOff, PtrType));
5085 AddToWorkList(NewPtr.getNode());
5088 if (ExtType == ISD::NON_EXTLOAD)
5089 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
5090 LN0->getPointerInfo().getWithOffset(PtrOff),
5091 LN0->isVolatile(), LN0->isNonTemporal(),
5092 LN0->isInvariant(), NewAlign);
5094 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
5095 LN0->getPointerInfo().getWithOffset(PtrOff),
5096 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
5099 // Replace the old load's chain with the new load's chain.
5100 WorkListRemover DeadNodes(*this);
5101 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
5103 // Shift the result left, if we've swallowed a left shift.
5104 SDValue Result = Load;
5105 if (ShLeftAmt != 0) {
5106 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
5107 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
5109 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
5110 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
5113 // Return the new loaded value.
5117 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
5118 SDValue N0 = N->getOperand(0);
5119 SDValue N1 = N->getOperand(1);
5120 EVT VT = N->getValueType(0);
5121 EVT EVT = cast<VTSDNode>(N1)->getVT();
5122 unsigned VTBits = VT.getScalarType().getSizeInBits();
5123 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
5125 // fold (sext_in_reg c1) -> c1
5126 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
5127 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
5129 // If the input is already sign extended, just drop the extension.
5130 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
5133 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
5134 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5135 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
5136 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5137 N0.getOperand(0), N1);
5140 // fold (sext_in_reg (sext x)) -> (sext x)
5141 // fold (sext_in_reg (aext x)) -> (sext x)
5142 // if x is small enough.
5143 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
5144 SDValue N00 = N0.getOperand(0);
5145 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
5146 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
5147 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
5150 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
5151 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
5152 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
5154 // fold operands of sext_in_reg based on knowledge that the top bits are not
5156 if (SimplifyDemandedBits(SDValue(N, 0)))
5157 return SDValue(N, 0);
5159 // fold (sext_in_reg (load x)) -> (smaller sextload x)
5160 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
5161 SDValue NarrowLoad = ReduceLoadWidth(N);
5162 if (NarrowLoad.getNode())
5165 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
5166 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
5167 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
5168 if (N0.getOpcode() == ISD::SRL) {
5169 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
5170 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
5171 // We can turn this into an SRA iff the input to the SRL is already sign
5173 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
5174 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
5175 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
5176 N0.getOperand(0), N0.getOperand(1));
5180 // fold (sext_inreg (extload x)) -> (sextload x)
5181 if (ISD::isEXTLoad(N0.getNode()) &&
5182 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5183 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5184 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5185 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5186 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5187 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5189 LN0->getBasePtr(), LN0->getPointerInfo(),
5191 LN0->isVolatile(), LN0->isNonTemporal(),
5192 LN0->getAlignment());
5193 CombineTo(N, ExtLoad);
5194 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5195 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5197 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
5198 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5200 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5201 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5202 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5203 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5204 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5206 LN0->getBasePtr(), LN0->getPointerInfo(),
5208 LN0->isVolatile(), LN0->isNonTemporal(),
5209 LN0->getAlignment());
5210 CombineTo(N, ExtLoad);
5211 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5212 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5215 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
5216 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5217 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5218 N0.getOperand(1), false);
5219 if (BSwap.getNode() != 0)
5220 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5227 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
5228 SDValue N0 = N->getOperand(0);
5229 EVT VT = N->getValueType(0);
5230 bool isLE = TLI.isLittleEndian();
5233 if (N0.getValueType() == N->getValueType(0))
5235 // fold (truncate c1) -> c1
5236 if (isa<ConstantSDNode>(N0))
5237 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
5238 // fold (truncate (truncate x)) -> (truncate x)
5239 if (N0.getOpcode() == ISD::TRUNCATE)
5240 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5241 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
5242 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
5243 N0.getOpcode() == ISD::SIGN_EXTEND ||
5244 N0.getOpcode() == ISD::ANY_EXTEND) {
5245 if (N0.getOperand(0).getValueType().bitsLT(VT))
5246 // if the source is smaller than the dest, we still need an extend
5247 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
5249 else if (N0.getOperand(0).getValueType().bitsGT(VT))
5250 // if the source is larger than the dest, than we just need the truncate
5251 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5253 // if the source and dest are the same type, we can drop both the extend
5254 // and the truncate.
5255 return N0.getOperand(0);
5258 // Fold extract-and-trunc into a narrow extract. For example:
5259 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
5260 // i32 y = TRUNCATE(i64 x)
5262 // v16i8 b = BITCAST (v2i64 val)
5263 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
5265 // Note: We only run this optimization after type legalization (which often
5266 // creates this pattern) and before operation legalization after which
5267 // we need to be more careful about the vector instructions that we generate.
5268 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5269 LegalTypes && !LegalOperations && N0->hasOneUse()) {
5271 EVT VecTy = N0.getOperand(0).getValueType();
5272 EVT ExTy = N0.getValueType();
5273 EVT TrTy = N->getValueType(0);
5275 unsigned NumElem = VecTy.getVectorNumElements();
5276 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
5278 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
5279 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
5281 SDValue EltNo = N0->getOperand(1);
5282 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
5283 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5284 EVT IndexTy = N0->getOperand(1).getValueType();
5285 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
5287 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5288 NVT, N0.getOperand(0));
5290 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
5291 N->getDebugLoc(), TrTy, V,
5292 DAG.getConstant(Index, IndexTy));
5296 // See if we can simplify the input to this truncate through knowledge that
5297 // only the low bits are being used.
5298 // For example "trunc (or (shl x, 8), y)" // -> trunc y
5299 // Currently we only perform this optimization on scalars because vectors
5300 // may have different active low bits.
5301 if (!VT.isVector()) {
5303 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
5304 VT.getSizeInBits()));
5305 if (Shorter.getNode())
5306 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
5308 // fold (truncate (load x)) -> (smaller load x)
5309 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
5310 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
5311 SDValue Reduced = ReduceLoadWidth(N);
5312 if (Reduced.getNode())
5316 // Simplify the operands using demanded-bits information.
5317 if (!VT.isVector() &&
5318 SimplifyDemandedBits(SDValue(N, 0)))
5319 return SDValue(N, 0);
5324 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
5325 SDValue Elt = N->getOperand(i);
5326 if (Elt.getOpcode() != ISD::MERGE_VALUES)
5327 return Elt.getNode();
5328 return Elt.getOperand(Elt.getResNo()).getNode();
5331 /// CombineConsecutiveLoads - build_pair (load, load) -> load
5332 /// if load locations are consecutive.
5333 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
5334 assert(N->getOpcode() == ISD::BUILD_PAIR);
5336 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
5337 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
5338 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
5339 LD1->getPointerInfo().getAddrSpace() !=
5340 LD2->getPointerInfo().getAddrSpace())
5342 EVT LD1VT = LD1->getValueType(0);
5344 if (ISD::isNON_EXTLoad(LD2) &&
5346 // If both are volatile this would reduce the number of volatile loads.
5347 // If one is volatile it might be ok, but play conservative and bail out.
5348 !LD1->isVolatile() &&
5349 !LD2->isVolatile() &&
5350 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
5351 unsigned Align = LD1->getAlignment();
5352 unsigned NewAlign = TLI.getTargetData()->
5353 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5355 if (NewAlign <= Align &&
5356 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
5357 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
5358 LD1->getBasePtr(), LD1->getPointerInfo(),
5359 false, false, false, Align);
5365 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
5366 SDValue N0 = N->getOperand(0);
5367 EVT VT = N->getValueType(0);
5369 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
5370 // Only do this before legalize, since afterward the target may be depending
5371 // on the bitconvert.
5372 // First check to see if this is all constant.
5374 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
5376 bool isSimple = true;
5377 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
5378 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
5379 N0.getOperand(i).getOpcode() != ISD::Constant &&
5380 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
5385 EVT DestEltVT = N->getValueType(0).getVectorElementType();
5386 assert(!DestEltVT.isVector() &&
5387 "Element type of vector ValueType must not be vector!");
5389 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
5392 // If the input is a constant, let getNode fold it.
5393 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
5394 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
5395 if (Res.getNode() != N) {
5396 if (!LegalOperations ||
5397 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
5400 // Folding it resulted in an illegal node, and it's too late to
5401 // do that. Clean up the old node and forego the transformation.
5402 // Ideally this won't happen very often, because instcombine
5403 // and the earlier dagcombine runs (where illegal nodes are
5404 // permitted) should have folded most of them already.
5405 DAG.DeleteNode(Res.getNode());
5409 // (conv (conv x, t1), t2) -> (conv x, t2)
5410 if (N0.getOpcode() == ISD::BITCAST)
5411 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
5414 // fold (conv (load x)) -> (load (conv*)x)
5415 // If the resultant load doesn't need a higher alignment than the original!
5416 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5417 // Do not change the width of a volatile load.
5418 !cast<LoadSDNode>(N0)->isVolatile() &&
5419 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
5420 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5421 unsigned Align = TLI.getTargetData()->
5422 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5423 unsigned OrigAlign = LN0->getAlignment();
5425 if (Align <= OrigAlign) {
5426 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
5427 LN0->getBasePtr(), LN0->getPointerInfo(),
5428 LN0->isVolatile(), LN0->isNonTemporal(),
5429 LN0->isInvariant(), OrigAlign);
5431 CombineTo(N0.getNode(),
5432 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5433 N0.getValueType(), Load),
5439 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5440 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5441 // This often reduces constant pool loads.
5442 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) ||
5443 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) &&
5444 N0.getNode()->hasOneUse() && VT.isInteger() &&
5445 !VT.isVector() && !N0.getValueType().isVector()) {
5446 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5448 AddToWorkList(NewConv.getNode());
5450 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5451 if (N0.getOpcode() == ISD::FNEG)
5452 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
5453 NewConv, DAG.getConstant(SignBit, VT));
5454 assert(N0.getOpcode() == ISD::FABS);
5455 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
5456 NewConv, DAG.getConstant(~SignBit, VT));
5459 // fold (bitconvert (fcopysign cst, x)) ->
5460 // (or (and (bitconvert x), sign), (and cst, (not sign)))
5461 // Note that we don't handle (copysign x, cst) because this can always be
5462 // folded to an fneg or fabs.
5463 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5464 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5465 VT.isInteger() && !VT.isVector()) {
5466 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5467 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5468 if (isTypeLegal(IntXVT)) {
5469 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5470 IntXVT, N0.getOperand(1));
5471 AddToWorkList(X.getNode());
5473 // If X has a different width than the result/lhs, sext it or truncate it.
5474 unsigned VTWidth = VT.getSizeInBits();
5475 if (OrigXWidth < VTWidth) {
5476 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
5477 AddToWorkList(X.getNode());
5478 } else if (OrigXWidth > VTWidth) {
5479 // To get the sign bit in the right place, we have to shift it right
5480 // before truncating.
5481 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5482 X.getValueType(), X,
5483 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5484 AddToWorkList(X.getNode());
5485 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
5486 AddToWorkList(X.getNode());
5489 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5490 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
5491 X, DAG.getConstant(SignBit, VT));
5492 AddToWorkList(X.getNode());
5494 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5495 VT, N0.getOperand(0));
5496 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
5497 Cst, DAG.getConstant(~SignBit, VT));
5498 AddToWorkList(Cst.getNode());
5500 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
5504 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5505 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5506 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5507 if (CombineLD.getNode())
5514 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5515 EVT VT = N->getValueType(0);
5516 return CombineConsecutiveLoads(N, VT);
5519 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5520 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
5521 /// destination element value type.
5522 SDValue DAGCombiner::
5523 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5524 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5526 // If this is already the right type, we're done.
5527 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5529 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5530 unsigned DstBitSize = DstEltVT.getSizeInBits();
5532 // If this is a conversion of N elements of one type to N elements of another
5533 // type, convert each element. This handles FP<->INT cases.
5534 if (SrcBitSize == DstBitSize) {
5535 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5536 BV->getValueType(0).getVectorNumElements());
5538 // Due to the FP element handling below calling this routine recursively,
5539 // we can end up with a scalar-to-vector node here.
5540 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5541 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5542 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5543 DstEltVT, BV->getOperand(0)));
5545 SmallVector<SDValue, 8> Ops;
5546 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5547 SDValue Op = BV->getOperand(i);
5548 // If the vector element type is not legal, the BUILD_VECTOR operands
5549 // are promoted and implicitly truncated. Make that explicit here.
5550 if (Op.getValueType() != SrcEltVT)
5551 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
5552 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5554 AddToWorkList(Ops.back().getNode());
5556 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5557 &Ops[0], Ops.size());
5560 // Otherwise, we're growing or shrinking the elements. To avoid having to
5561 // handle annoying details of growing/shrinking FP values, we convert them to
5563 if (SrcEltVT.isFloatingPoint()) {
5564 // Convert the input float vector to a int vector where the elements are the
5566 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5567 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5568 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5572 // Now we know the input is an integer vector. If the output is a FP type,
5573 // convert to integer first, then to FP of the right size.
5574 if (DstEltVT.isFloatingPoint()) {
5575 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5576 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5577 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5579 // Next, convert to FP elements of the same size.
5580 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5583 // Okay, we know the src/dst types are both integers of differing types.
5584 // Handling growing first.
5585 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5586 if (SrcBitSize < DstBitSize) {
5587 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5589 SmallVector<SDValue, 8> Ops;
5590 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5591 i += NumInputsPerOutput) {
5592 bool isLE = TLI.isLittleEndian();
5593 APInt NewBits = APInt(DstBitSize, 0);
5594 bool EltIsUndef = true;
5595 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5596 // Shift the previously computed bits over.
5597 NewBits <<= SrcBitSize;
5598 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
5599 if (Op.getOpcode() == ISD::UNDEF) continue;
5602 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
5603 zextOrTrunc(SrcBitSize).zext(DstBitSize);
5607 Ops.push_back(DAG.getUNDEF(DstEltVT));
5609 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
5612 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
5613 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5614 &Ops[0], Ops.size());
5617 // Finally, this must be the case where we are shrinking elements: each input
5618 // turns into multiple outputs.
5619 bool isS2V = ISD::isScalarToVector(BV);
5620 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
5621 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5622 NumOutputsPerInput*BV->getNumOperands());
5623 SmallVector<SDValue, 8> Ops;
5625 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5626 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5627 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
5628 Ops.push_back(DAG.getUNDEF(DstEltVT));
5632 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
5633 getAPIntValue().zextOrTrunc(SrcBitSize);
5635 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
5636 APInt ThisVal = OpVal.trunc(DstBitSize);
5637 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
5638 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
5639 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
5640 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5642 OpVal = OpVal.lshr(DstBitSize);
5645 // For big endian targets, swap the order of the pieces of each element.
5646 if (TLI.isBigEndian())
5647 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
5650 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5651 &Ops[0], Ops.size());
5654 SDValue DAGCombiner::visitFADD(SDNode *N) {
5655 SDValue N0 = N->getOperand(0);
5656 SDValue N1 = N->getOperand(1);
5657 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5658 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5659 EVT VT = N->getValueType(0);
5662 if (VT.isVector()) {
5663 SDValue FoldedVOp = SimplifyVBinOp(N);
5664 if (FoldedVOp.getNode()) return FoldedVOp;
5667 // fold (fadd c1, c2) -> c1 + c2
5668 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5669 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5670 // canonicalize constant to RHS
5671 if (N0CFP && !N1CFP)
5672 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5673 // fold (fadd A, 0) -> A
5674 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5675 N1CFP->getValueAPF().isZero())
5677 // fold (fadd A, (fneg B)) -> (fsub A, B)
5678 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5679 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5680 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5681 GetNegatedExpression(N1, DAG, LegalOperations));
5682 // fold (fadd (fneg A), B) -> (fsub B, A)
5683 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5684 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5685 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
5686 GetNegatedExpression(N0, DAG, LegalOperations));
5688 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5689 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5690 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
5691 isa<ConstantFPSDNode>(N0.getOperand(1)))
5692 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5693 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5694 N0.getOperand(1), N1));
5696 // In unsafe math mode, we can fold chains of FADD's of the same value
5697 // into multiplications. This transform is not safe in general because
5698 // we are reducing the number of rounding steps.
5699 if (DAG.getTarget().Options.UnsafeFPMath &&
5700 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) &&
5702 if (N0.getOpcode() == ISD::FMUL) {
5703 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
5704 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
5706 // (fadd (fmul c, x), x) -> (fmul c+1, x)
5707 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) {
5708 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5710 DAG.getConstantFP(1.0, VT));
5711 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5715 // (fadd (fmul x, c), x) -> (fmul c+1, x)
5716 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
5717 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5719 DAG.getConstantFP(1.0, VT));
5720 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5724 // (fadd (fadd x, x), x) -> (fmul 3.0, x)
5725 if (!CFP00 && !CFP01 && N0.getOperand(0) == N0.getOperand(1) &&
5726 N0.getOperand(0) == N1) {
5727 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5728 N1, DAG.getConstantFP(3.0, VT));
5731 // (fadd (fmul c, x), (fadd x, x)) -> (fmul c+2, x)
5732 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD &&
5733 N1.getOperand(0) == N1.getOperand(1) &&
5734 N0.getOperand(1) == N1.getOperand(0)) {
5735 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5737 DAG.getConstantFP(2.0, VT));
5738 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5739 N0.getOperand(1), NewCFP);
5742 // (fadd (fmul x, c), (fadd x, x)) -> (fmul c+2, x)
5743 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
5744 N1.getOperand(0) == N1.getOperand(1) &&
5745 N0.getOperand(0) == N1.getOperand(0)) {
5746 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5748 DAG.getConstantFP(2.0, VT));
5749 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5750 N0.getOperand(0), NewCFP);
5754 if (N1.getOpcode() == ISD::FMUL) {
5755 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
5756 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1));
5758 // (fadd x, (fmul c, x)) -> (fmul c+1, x)
5759 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) {
5760 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5762 DAG.getConstantFP(1.0, VT));
5763 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5767 // (fadd x, (fmul x, c)) -> (fmul c+1, x)
5768 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
5769 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5771 DAG.getConstantFP(1.0, VT));
5772 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5776 // (fadd x, (fadd x, x)) -> (fmul 3.0, x)
5777 if (!CFP10 && !CFP11 && N1.getOperand(0) == N1.getOperand(1) &&
5778 N1.getOperand(0) == N0) {
5779 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5780 N0, DAG.getConstantFP(3.0, VT));
5783 // (fadd (fadd x, x), (fmul c, x)) -> (fmul c+2, x)
5784 if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD &&
5785 N1.getOperand(0) == N1.getOperand(1) &&
5786 N0.getOperand(1) == N1.getOperand(0)) {
5787 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5789 DAG.getConstantFP(2.0, VT));
5790 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5791 N0.getOperand(1), NewCFP);
5794 // (fadd (fadd x, x), (fmul x, c)) -> (fmul c+2, x)
5795 if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD &&
5796 N1.getOperand(0) == N1.getOperand(1) &&
5797 N0.getOperand(0) == N1.getOperand(0)) {
5798 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5800 DAG.getConstantFP(2.0, VT));
5801 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5802 N0.getOperand(0), NewCFP);
5806 // (fadd (fadd x, x), (fadd x, x)) -> (fmul 4.0, x)
5807 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
5808 N0.getOperand(0) == N0.getOperand(1) &&
5809 N1.getOperand(0) == N1.getOperand(1) &&
5810 N0.getOperand(0) == N1.getOperand(0)) {
5811 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5813 DAG.getConstantFP(4.0, VT));
5817 // FADD -> FMA combines:
5818 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
5819 DAG.getTarget().Options.UnsafeFPMath) &&
5820 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) &&
5821 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) {
5823 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
5824 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) {
5825 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT,
5826 N0.getOperand(0), N0.getOperand(1), N1);
5829 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
5830 // Note: Commutes FADD operands.
5831 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) {
5832 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT,
5833 N1.getOperand(0), N1.getOperand(1), N0);
5840 SDValue DAGCombiner::visitFSUB(SDNode *N) {
5841 SDValue N0 = N->getOperand(0);
5842 SDValue N1 = N->getOperand(1);
5843 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5844 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5845 EVT VT = N->getValueType(0);
5846 DebugLoc dl = N->getDebugLoc();
5849 if (VT.isVector()) {
5850 SDValue FoldedVOp = SimplifyVBinOp(N);
5851 if (FoldedVOp.getNode()) return FoldedVOp;
5854 // fold (fsub c1, c2) -> c1-c2
5855 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5856 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5857 // fold (fsub A, 0) -> A
5858 if (DAG.getTarget().Options.UnsafeFPMath &&
5859 N1CFP && N1CFP->getValueAPF().isZero())
5861 // fold (fsub 0, B) -> -B
5862 if (DAG.getTarget().Options.UnsafeFPMath &&
5863 N0CFP && N0CFP->getValueAPF().isZero()) {
5864 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
5865 return GetNegatedExpression(N1, DAG, LegalOperations);
5866 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5867 return DAG.getNode(ISD::FNEG, dl, VT, N1);
5869 // fold (fsub A, (fneg B)) -> (fadd A, B)
5870 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
5871 return DAG.getNode(ISD::FADD, dl, VT, N0,
5872 GetNegatedExpression(N1, DAG, LegalOperations));
5874 // If 'unsafe math' is enabled, fold
5875 // (fsub x, x) -> 0.0 &
5876 // (fsub x, (fadd x, y)) -> (fneg y) &
5877 // (fsub x, (fadd y, x)) -> (fneg y)
5878 if (DAG.getTarget().Options.UnsafeFPMath) {
5880 return DAG.getConstantFP(0.0f, VT);
5882 if (N1.getOpcode() == ISD::FADD) {
5883 SDValue N10 = N1->getOperand(0);
5884 SDValue N11 = N1->getOperand(1);
5886 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI,
5887 &DAG.getTarget().Options))
5888 return GetNegatedExpression(N11, DAG, LegalOperations);
5889 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI,
5890 &DAG.getTarget().Options))
5891 return GetNegatedExpression(N10, DAG, LegalOperations);
5895 // FSUB -> FMA combines:
5896 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
5897 DAG.getTarget().Options.UnsafeFPMath) &&
5898 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) &&
5899 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) {
5901 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
5902 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) {
5903 return DAG.getNode(ISD::FMA, dl, VT,
5904 N0.getOperand(0), N0.getOperand(1),
5905 DAG.getNode(ISD::FNEG, dl, VT, N1));
5908 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
5909 // Note: Commutes FSUB operands.
5910 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) {
5911 return DAG.getNode(ISD::FMA, dl, VT,
5912 DAG.getNode(ISD::FNEG, dl, VT,
5914 N1.getOperand(1), N0);
5917 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
5918 if (N0.getOpcode() == ISD::FNEG &&
5919 N0.getOperand(0).getOpcode() == ISD::FMUL &&
5920 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) {
5921 SDValue N00 = N0.getOperand(0).getOperand(0);
5922 SDValue N01 = N0.getOperand(0).getOperand(1);
5923 return DAG.getNode(ISD::FMA, dl, VT,
5924 DAG.getNode(ISD::FNEG, dl, VT, N00), N01,
5925 DAG.getNode(ISD::FNEG, dl, VT, N1));
5932 SDValue DAGCombiner::visitFMUL(SDNode *N) {
5933 SDValue N0 = N->getOperand(0);
5934 SDValue N1 = N->getOperand(1);
5935 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5936 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5937 EVT VT = N->getValueType(0);
5938 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5941 if (VT.isVector()) {
5942 SDValue FoldedVOp = SimplifyVBinOp(N);
5943 if (FoldedVOp.getNode()) return FoldedVOp;
5946 // fold (fmul c1, c2) -> c1*c2
5947 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5948 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
5949 // canonicalize constant to RHS
5950 if (N0CFP && !N1CFP)
5951 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
5952 // fold (fmul A, 0) -> 0
5953 if (DAG.getTarget().Options.UnsafeFPMath &&
5954 N1CFP && N1CFP->getValueAPF().isZero())
5956 // fold (fmul A, 0) -> 0, vector edition.
5957 if (DAG.getTarget().Options.UnsafeFPMath &&
5958 ISD::isBuildVectorAllZeros(N1.getNode()))
5960 // fold (fmul A, 1.0) -> A
5961 if (N1CFP && N1CFP->isExactlyValue(1.0))
5963 // fold (fmul X, 2.0) -> (fadd X, X)
5964 if (N1CFP && N1CFP->isExactlyValue(+2.0))
5965 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
5966 // fold (fmul X, -1.0) -> (fneg X)
5967 if (N1CFP && N1CFP->isExactlyValue(-1.0))
5968 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5969 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
5971 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
5972 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
5973 &DAG.getTarget().Options)) {
5974 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
5975 &DAG.getTarget().Options)) {
5976 // Both can be negated for free, check to see if at least one is cheaper
5978 if (LHSNeg == 2 || RHSNeg == 2)
5979 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5980 GetNegatedExpression(N0, DAG, LegalOperations),
5981 GetNegatedExpression(N1, DAG, LegalOperations));
5985 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
5986 if (DAG.getTarget().Options.UnsafeFPMath &&
5987 N1CFP && N0.getOpcode() == ISD::FMUL &&
5988 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5989 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
5990 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5991 N0.getOperand(1), N1));
5996 SDValue DAGCombiner::visitFMA(SDNode *N) {
5997 SDValue N0 = N->getOperand(0);
5998 SDValue N1 = N->getOperand(1);
5999 SDValue N2 = N->getOperand(2);
6000 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6001 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6002 EVT VT = N->getValueType(0);
6003 DebugLoc dl = N->getDebugLoc();
6005 if (N0CFP && N0CFP->isExactlyValue(1.0))
6006 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2);
6007 if (N1CFP && N1CFP->isExactlyValue(1.0))
6008 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2);
6010 // Canonicalize (fma c, x, y) -> (fma x, c, y)
6011 if (N0CFP && !N1CFP)
6012 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2);
6014 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
6015 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6016 N2.getOpcode() == ISD::FMUL &&
6017 N0 == N2.getOperand(0) &&
6018 N2.getOperand(1).getOpcode() == ISD::ConstantFP) {
6019 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6020 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1)));
6024 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
6025 if (DAG.getTarget().Options.UnsafeFPMath &&
6026 N0.getOpcode() == ISD::FMUL && N1CFP &&
6027 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
6028 return DAG.getNode(ISD::FMA, dl, VT,
6030 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
6034 // (fma x, 1, y) -> (fadd x, y)
6035 // (fma x, -1, y) -> (fadd (fneg x), y)
6037 if (N1CFP->isExactlyValue(1.0))
6038 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
6040 if (N1CFP->isExactlyValue(-1.0) &&
6041 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
6042 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
6043 AddToWorkList(RHSNeg.getNode());
6044 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
6048 // (fma x, c, x) -> (fmul x, (c+1))
6049 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) {
6050 return DAG.getNode(ISD::FMUL, dl, VT,
6052 DAG.getNode(ISD::FADD, dl, VT,
6053 N1, DAG.getConstantFP(1.0, VT)));
6056 // (fma x, c, (fneg x)) -> (fmul x, (c-1))
6057 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6058 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) {
6059 return DAG.getNode(ISD::FMUL, dl, VT,
6061 DAG.getNode(ISD::FADD, dl, VT,
6062 N1, DAG.getConstantFP(-1.0, VT)));
6069 SDValue DAGCombiner::visitFDIV(SDNode *N) {
6070 SDValue N0 = N->getOperand(0);
6071 SDValue N1 = N->getOperand(1);
6072 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6073 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6074 EVT VT = N->getValueType(0);
6075 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6078 if (VT.isVector()) {
6079 SDValue FoldedVOp = SimplifyVBinOp(N);
6080 if (FoldedVOp.getNode()) return FoldedVOp;
6083 // fold (fdiv c1, c2) -> c1/c2
6084 if (N0CFP && N1CFP && VT != MVT::ppcf128)
6085 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
6087 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
6088 if (N1CFP && VT != MVT::ppcf128 && DAG.getTarget().Options.UnsafeFPMath) {
6089 // Compute the reciprocal 1.0 / c2.
6090 APFloat N1APF = N1CFP->getValueAPF();
6091 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
6092 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
6093 // Only do the transform if the reciprocal is a legal fp immediate that
6094 // isn't too nasty (eg NaN, denormal, ...).
6095 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
6096 (!LegalOperations ||
6097 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
6098 // backend)... we should handle this gracefully after Legalize.
6099 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
6100 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
6101 TLI.isFPImmLegal(Recip, VT)))
6102 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0,
6103 DAG.getConstantFP(Recip, VT));
6106 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
6107 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6108 &DAG.getTarget().Options)) {
6109 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
6110 &DAG.getTarget().Options)) {
6111 // Both can be negated for free, check to see if at least one is cheaper
6113 if (LHSNeg == 2 || RHSNeg == 2)
6114 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
6115 GetNegatedExpression(N0, DAG, LegalOperations),
6116 GetNegatedExpression(N1, DAG, LegalOperations));
6123 SDValue DAGCombiner::visitFREM(SDNode *N) {
6124 SDValue N0 = N->getOperand(0);
6125 SDValue N1 = N->getOperand(1);
6126 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6127 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6128 EVT VT = N->getValueType(0);
6130 // fold (frem c1, c2) -> fmod(c1,c2)
6131 if (N0CFP && N1CFP && VT != MVT::ppcf128)
6132 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
6137 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
6138 SDValue N0 = N->getOperand(0);
6139 SDValue N1 = N->getOperand(1);
6140 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6141 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6142 EVT VT = N->getValueType(0);
6144 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
6145 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
6148 const APFloat& V = N1CFP->getValueAPF();
6149 // copysign(x, c1) -> fabs(x) iff ispos(c1)
6150 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
6151 if (!V.isNegative()) {
6152 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
6153 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6155 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6156 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
6157 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
6161 // copysign(fabs(x), y) -> copysign(x, y)
6162 // copysign(fneg(x), y) -> copysign(x, y)
6163 // copysign(copysign(x,z), y) -> copysign(x, y)
6164 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
6165 N0.getOpcode() == ISD::FCOPYSIGN)
6166 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6167 N0.getOperand(0), N1);
6169 // copysign(x, abs(y)) -> abs(x)
6170 if (N1.getOpcode() == ISD::FABS)
6171 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6173 // copysign(x, copysign(y,z)) -> copysign(x, z)
6174 if (N1.getOpcode() == ISD::FCOPYSIGN)
6175 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6176 N0, N1.getOperand(1));
6178 // copysign(x, fp_extend(y)) -> copysign(x, y)
6179 // copysign(x, fp_round(y)) -> copysign(x, y)
6180 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
6181 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6182 N0, N1.getOperand(0));
6187 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
6188 SDValue N0 = N->getOperand(0);
6189 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6190 EVT VT = N->getValueType(0);
6191 EVT OpVT = N0.getValueType();
6193 // fold (sint_to_fp c1) -> c1fp
6194 if (N0C && OpVT != MVT::ppcf128 &&
6195 // ...but only if the target supports immediate floating-point values
6196 (!LegalOperations ||
6197 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6198 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
6200 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
6201 // but UINT_TO_FP is legal on this target, try to convert.
6202 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
6203 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
6204 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
6205 if (DAG.SignBitIsZero(N0))
6206 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
6209 // The next optimizations are desireable only if SELECT_CC can be lowered.
6210 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
6211 // having to say they don't support SELECT_CC on every type the DAG knows
6212 // about, since there is no way to mark an opcode illegal at all value types
6213 // (See also visitSELECT)
6214 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
6215 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6216 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
6218 (!LegalOperations ||
6219 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6221 { N0.getOperand(0), N0.getOperand(1),
6222 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT),
6224 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6227 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
6228 // (select_cc x, y, 1.0, 0.0,, cc)
6229 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
6230 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
6231 (!LegalOperations ||
6232 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6234 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
6235 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT),
6236 N0.getOperand(0).getOperand(2) };
6237 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6244 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
6245 SDValue N0 = N->getOperand(0);
6246 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6247 EVT VT = N->getValueType(0);
6248 EVT OpVT = N0.getValueType();
6250 // fold (uint_to_fp c1) -> c1fp
6251 if (N0C && OpVT != MVT::ppcf128 &&
6252 // ...but only if the target supports immediate floating-point values
6253 (!LegalOperations ||
6254 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6255 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
6257 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
6258 // but SINT_TO_FP is legal on this target, try to convert.
6259 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
6260 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
6261 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
6262 if (DAG.SignBitIsZero(N0))
6263 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
6266 // The next optimizations are desireable only if SELECT_CC can be lowered.
6267 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
6268 // having to say they don't support SELECT_CC on every type the DAG knows
6269 // about, since there is no way to mark an opcode illegal at all value types
6270 // (See also visitSELECT)
6271 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
6272 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6274 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
6275 (!LegalOperations ||
6276 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6278 { N0.getOperand(0), N0.getOperand(1),
6279 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT),
6281 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6288 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
6289 SDValue N0 = N->getOperand(0);
6290 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6291 EVT VT = N->getValueType(0);
6293 // fold (fp_to_sint c1fp) -> c1
6295 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
6300 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
6301 SDValue N0 = N->getOperand(0);
6302 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6303 EVT VT = N->getValueType(0);
6305 // fold (fp_to_uint c1fp) -> c1
6306 if (N0CFP && VT != MVT::ppcf128)
6307 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
6312 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
6313 SDValue N0 = N->getOperand(0);
6314 SDValue N1 = N->getOperand(1);
6315 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6316 EVT VT = N->getValueType(0);
6318 // fold (fp_round c1fp) -> c1fp
6319 if (N0CFP && N0.getValueType() != MVT::ppcf128)
6320 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
6322 // fold (fp_round (fp_extend x)) -> x
6323 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
6324 return N0.getOperand(0);
6326 // fold (fp_round (fp_round x)) -> (fp_round x)
6327 if (N0.getOpcode() == ISD::FP_ROUND) {
6328 // This is a value preserving truncation if both round's are.
6329 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
6330 N0.getNode()->getConstantOperandVal(1) == 1;
6331 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
6332 DAG.getIntPtrConstant(IsTrunc));
6335 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
6336 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
6337 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
6338 N0.getOperand(0), N1);
6339 AddToWorkList(Tmp.getNode());
6340 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6341 Tmp, N0.getOperand(1));
6347 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
6348 SDValue N0 = N->getOperand(0);
6349 EVT VT = N->getValueType(0);
6350 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
6351 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6353 // fold (fp_round_inreg c1fp) -> c1fp
6354 if (N0CFP && isTypeLegal(EVT)) {
6355 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
6356 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
6362 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
6363 SDValue N0 = N->getOperand(0);
6364 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6365 EVT VT = N->getValueType(0);
6367 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
6368 if (N->hasOneUse() &&
6369 N->use_begin()->getOpcode() == ISD::FP_ROUND)
6372 // fold (fp_extend c1fp) -> c1fp
6373 if (N0CFP && VT != MVT::ppcf128)
6374 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
6376 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
6378 if (N0.getOpcode() == ISD::FP_ROUND
6379 && N0.getNode()->getConstantOperandVal(1) == 1) {
6380 SDValue In = N0.getOperand(0);
6381 if (In.getValueType() == VT) return In;
6382 if (VT.bitsLT(In.getValueType()))
6383 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
6384 In, N0.getOperand(1));
6385 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
6388 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
6389 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
6390 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6391 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
6392 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6393 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
6395 LN0->getBasePtr(), LN0->getPointerInfo(),
6397 LN0->isVolatile(), LN0->isNonTemporal(),
6398 LN0->getAlignment());
6399 CombineTo(N, ExtLoad);
6400 CombineTo(N0.getNode(),
6401 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
6402 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
6403 ExtLoad.getValue(1));
6404 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6410 SDValue DAGCombiner::visitFNEG(SDNode *N) {
6411 SDValue N0 = N->getOperand(0);
6412 EVT VT = N->getValueType(0);
6414 if (VT.isVector()) {
6415 SDValue FoldedVOp = SimplifyVUnaryOp(N);
6416 if (FoldedVOp.getNode()) return FoldedVOp;
6419 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
6420 &DAG.getTarget().Options))
6421 return GetNegatedExpression(N0, DAG, LegalOperations);
6423 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
6424 // constant pool values.
6425 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST &&
6427 N0.getNode()->hasOneUse() &&
6428 N0.getOperand(0).getValueType().isInteger()) {
6429 SDValue Int = N0.getOperand(0);
6430 EVT IntVT = Int.getValueType();
6431 if (IntVT.isInteger() && !IntVT.isVector()) {
6432 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
6433 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6434 AddToWorkList(Int.getNode());
6435 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6440 // (fneg (fmul c, x)) -> (fmul -c, x)
6441 if (N0.getOpcode() == ISD::FMUL) {
6442 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
6444 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
6446 DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
6454 SDValue DAGCombiner::visitFCEIL(SDNode *N) {
6455 SDValue N0 = N->getOperand(0);
6456 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6457 EVT VT = N->getValueType(0);
6459 // fold (fceil c1) -> fceil(c1)
6460 if (N0CFP && VT != MVT::ppcf128)
6461 return DAG.getNode(ISD::FCEIL, N->getDebugLoc(), VT, N0);
6466 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
6467 SDValue N0 = N->getOperand(0);
6468 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6469 EVT VT = N->getValueType(0);
6471 // fold (ftrunc c1) -> ftrunc(c1)
6472 if (N0CFP && VT != MVT::ppcf128)
6473 return DAG.getNode(ISD::FTRUNC, N->getDebugLoc(), VT, N0);
6478 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
6479 SDValue N0 = N->getOperand(0);
6480 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6481 EVT VT = N->getValueType(0);
6483 // fold (ffloor c1) -> ffloor(c1)
6484 if (N0CFP && VT != MVT::ppcf128)
6485 return DAG.getNode(ISD::FFLOOR, N->getDebugLoc(), VT, N0);
6490 SDValue DAGCombiner::visitFABS(SDNode *N) {
6491 SDValue N0 = N->getOperand(0);
6492 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6493 EVT VT = N->getValueType(0);
6495 if (VT.isVector()) {
6496 SDValue FoldedVOp = SimplifyVUnaryOp(N);
6497 if (FoldedVOp.getNode()) return FoldedVOp;
6500 // fold (fabs c1) -> fabs(c1)
6501 if (N0CFP && VT != MVT::ppcf128)
6502 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6503 // fold (fabs (fabs x)) -> (fabs x)
6504 if (N0.getOpcode() == ISD::FABS)
6505 return N->getOperand(0);
6506 // fold (fabs (fneg x)) -> (fabs x)
6507 // fold (fabs (fcopysign x, y)) -> (fabs x)
6508 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
6509 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
6511 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
6512 // constant pool values.
6513 if (!TLI.isFAbsFree(VT) &&
6514 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
6515 N0.getOperand(0).getValueType().isInteger() &&
6516 !N0.getOperand(0).getValueType().isVector()) {
6517 SDValue Int = N0.getOperand(0);
6518 EVT IntVT = Int.getValueType();
6519 if (IntVT.isInteger() && !IntVT.isVector()) {
6520 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
6521 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6522 AddToWorkList(Int.getNode());
6523 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6524 N->getValueType(0), Int);
6531 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
6532 SDValue Chain = N->getOperand(0);
6533 SDValue N1 = N->getOperand(1);
6534 SDValue N2 = N->getOperand(2);
6536 // If N is a constant we could fold this into a fallthrough or unconditional
6537 // branch. However that doesn't happen very often in normal code, because
6538 // Instcombine/SimplifyCFG should have handled the available opportunities.
6539 // If we did this folding here, it would be necessary to update the
6540 // MachineBasicBlock CFG, which is awkward.
6542 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
6544 if (N1.getOpcode() == ISD::SETCC &&
6545 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
6546 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6547 Chain, N1.getOperand(2),
6548 N1.getOperand(0), N1.getOperand(1), N2);
6551 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
6552 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
6553 (N1.getOperand(0).hasOneUse() &&
6554 N1.getOperand(0).getOpcode() == ISD::SRL))) {
6556 if (N1.getOpcode() == ISD::TRUNCATE) {
6557 // Look pass the truncate.
6558 Trunc = N1.getNode();
6559 N1 = N1.getOperand(0);
6562 // Match this pattern so that we can generate simpler code:
6565 // %b = and i32 %a, 2
6566 // %c = srl i32 %b, 1
6567 // brcond i32 %c ...
6572 // %b = and i32 %a, 2
6573 // %c = setcc eq %b, 0
6576 // This applies only when the AND constant value has one bit set and the
6577 // SRL constant is equal to the log2 of the AND constant. The back-end is
6578 // smart enough to convert the result into a TEST/JMP sequence.
6579 SDValue Op0 = N1.getOperand(0);
6580 SDValue Op1 = N1.getOperand(1);
6582 if (Op0.getOpcode() == ISD::AND &&
6583 Op1.getOpcode() == ISD::Constant) {
6584 SDValue AndOp1 = Op0.getOperand(1);
6586 if (AndOp1.getOpcode() == ISD::Constant) {
6587 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
6589 if (AndConst.isPowerOf2() &&
6590 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
6592 DAG.getSetCC(N->getDebugLoc(),
6593 TLI.getSetCCResultType(Op0.getValueType()),
6594 Op0, DAG.getConstant(0, Op0.getValueType()),
6597 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6598 MVT::Other, Chain, SetCC, N2);
6599 // Don't add the new BRCond into the worklist or else SimplifySelectCC
6600 // will convert it back to (X & C1) >> C2.
6601 CombineTo(N, NewBRCond, false);
6602 // Truncate is dead.
6604 removeFromWorkList(Trunc);
6605 DAG.DeleteNode(Trunc);
6607 // Replace the uses of SRL with SETCC
6608 WorkListRemover DeadNodes(*this);
6609 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6610 removeFromWorkList(N1.getNode());
6611 DAG.DeleteNode(N1.getNode());
6612 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6618 // Restore N1 if the above transformation doesn't match.
6619 N1 = N->getOperand(1);
6622 // Transform br(xor(x, y)) -> br(x != y)
6623 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
6624 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
6625 SDNode *TheXor = N1.getNode();
6626 SDValue Op0 = TheXor->getOperand(0);
6627 SDValue Op1 = TheXor->getOperand(1);
6628 if (Op0.getOpcode() == Op1.getOpcode()) {
6629 // Avoid missing important xor optimizations.
6630 SDValue Tmp = visitXOR(TheXor);
6631 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
6632 DEBUG(dbgs() << "\nReplacing.8 ";
6634 dbgs() << "\nWith: ";
6635 Tmp.getNode()->dump(&DAG);
6637 WorkListRemover DeadNodes(*this);
6638 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
6639 removeFromWorkList(TheXor);
6640 DAG.DeleteNode(TheXor);
6641 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6642 MVT::Other, Chain, Tmp, N2);
6646 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
6648 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
6649 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
6650 Op0.getOpcode() == ISD::XOR) {
6651 TheXor = Op0.getNode();
6655 EVT SetCCVT = N1.getValueType();
6657 SetCCVT = TLI.getSetCCResultType(SetCCVT);
6658 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
6661 Equal ? ISD::SETEQ : ISD::SETNE);
6662 // Replace the uses of XOR with SETCC
6663 WorkListRemover DeadNodes(*this);
6664 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6665 removeFromWorkList(N1.getNode());
6666 DAG.DeleteNode(N1.getNode());
6667 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6668 MVT::Other, Chain, SetCC, N2);
6675 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
6677 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
6678 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
6679 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
6681 // If N is a constant we could fold this into a fallthrough or unconditional
6682 // branch. However that doesn't happen very often in normal code, because
6683 // Instcombine/SimplifyCFG should have handled the available opportunities.
6684 // If we did this folding here, it would be necessary to update the
6685 // MachineBasicBlock CFG, which is awkward.
6687 // Use SimplifySetCC to simplify SETCC's.
6688 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
6689 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
6691 if (Simp.getNode()) AddToWorkList(Simp.getNode());
6693 // fold to a simpler setcc
6694 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
6695 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6696 N->getOperand(0), Simp.getOperand(2),
6697 Simp.getOperand(0), Simp.getOperand(1),
6703 /// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
6704 /// uses N as its base pointer and that N may be folded in the load / store
6705 /// addressing mode.
6706 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
6708 const TargetLowering &TLI) {
6710 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
6711 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
6713 VT = Use->getValueType(0);
6714 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
6715 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
6717 VT = ST->getValue().getValueType();
6721 TargetLowering::AddrMode AM;
6722 if (N->getOpcode() == ISD::ADD) {
6723 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6726 AM.BaseOffs = Offset->getSExtValue();
6730 } else if (N->getOpcode() == ISD::SUB) {
6731 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6734 AM.BaseOffs = -Offset->getSExtValue();
6741 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
6744 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
6745 /// pre-indexed load / store when the base pointer is an add or subtract
6746 /// and it has other uses besides the load / store. After the
6747 /// transformation, the new indexed load / store has effectively folded
6748 /// the add / subtract in and all of its other uses are redirected to the
6749 /// new load / store.
6750 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
6751 if (Level < AfterLegalizeDAG)
6757 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6758 if (LD->isIndexed())
6760 VT = LD->getMemoryVT();
6761 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
6762 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
6764 Ptr = LD->getBasePtr();
6765 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6766 if (ST->isIndexed())
6768 VT = ST->getMemoryVT();
6769 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
6770 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
6772 Ptr = ST->getBasePtr();
6778 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
6779 // out. There is no reason to make this a preinc/predec.
6780 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
6781 Ptr.getNode()->hasOneUse())
6784 // Ask the target to do addressing mode selection.
6787 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6788 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
6790 // Don't create a indexed load / store with zero offset.
6791 if (isa<ConstantSDNode>(Offset) &&
6792 cast<ConstantSDNode>(Offset)->isNullValue())
6795 // Try turning it into a pre-indexed load / store except when:
6796 // 1) The new base ptr is a frame index.
6797 // 2) If N is a store and the new base ptr is either the same as or is a
6798 // predecessor of the value being stored.
6799 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
6800 // that would create a cycle.
6801 // 4) All uses are load / store ops that use it as old base ptr.
6803 // Check #1. Preinc'ing a frame index would require copying the stack pointer
6804 // (plus the implicit offset) to a register to preinc anyway.
6805 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6810 SDValue Val = cast<StoreSDNode>(N)->getValue();
6811 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
6815 // Now check for #3 and #4.
6816 bool RealUse = false;
6818 // Caches for hasPredecessorHelper
6819 SmallPtrSet<const SDNode *, 32> Visited;
6820 SmallVector<const SDNode *, 16> Worklist;
6822 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6823 E = Ptr.getNode()->use_end(); I != E; ++I) {
6827 if (N->hasPredecessorHelper(Use, Visited, Worklist))
6830 // If Ptr may be folded in addressing mode of other use, then it's
6831 // not profitable to do this transformation.
6832 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
6841 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6842 BasePtr, Offset, AM);
6844 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6845 BasePtr, Offset, AM);
6848 DEBUG(dbgs() << "\nReplacing.4 ";
6850 dbgs() << "\nWith: ";
6851 Result.getNode()->dump(&DAG);
6853 WorkListRemover DeadNodes(*this);
6855 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
6856 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
6858 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
6861 // Finally, since the node is now dead, remove it from the graph.
6864 // Replace the uses of Ptr with uses of the updated base value.
6865 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
6866 removeFromWorkList(Ptr.getNode());
6867 DAG.DeleteNode(Ptr.getNode());
6872 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
6873 /// add / sub of the base pointer node into a post-indexed load / store.
6874 /// The transformation folded the add / subtract into the new indexed
6875 /// load / store effectively and all of its uses are redirected to the
6876 /// new load / store.
6877 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
6878 if (Level < AfterLegalizeDAG)
6884 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6885 if (LD->isIndexed())
6887 VT = LD->getMemoryVT();
6888 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
6889 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
6891 Ptr = LD->getBasePtr();
6892 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6893 if (ST->isIndexed())
6895 VT = ST->getMemoryVT();
6896 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
6897 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
6899 Ptr = ST->getBasePtr();
6905 if (Ptr.getNode()->hasOneUse())
6908 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6909 E = Ptr.getNode()->use_end(); I != E; ++I) {
6912 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
6917 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6918 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
6919 // Don't create a indexed load / store with zero offset.
6920 if (isa<ConstantSDNode>(Offset) &&
6921 cast<ConstantSDNode>(Offset)->isNullValue())
6924 // Try turning it into a post-indexed load / store except when
6925 // 1) All uses are load / store ops that use it as base ptr (and
6926 // it may be folded as addressing mmode).
6927 // 2) Op must be independent of N, i.e. Op is neither a predecessor
6928 // nor a successor of N. Otherwise, if Op is folded that would
6931 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6935 bool TryNext = false;
6936 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
6937 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
6939 if (Use == Ptr.getNode())
6942 // If all the uses are load / store addresses, then don't do the
6944 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
6945 bool RealUse = false;
6946 for (SDNode::use_iterator III = Use->use_begin(),
6947 EEE = Use->use_end(); III != EEE; ++III) {
6948 SDNode *UseUse = *III;
6949 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
6964 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
6965 SDValue Result = isLoad
6966 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6967 BasePtr, Offset, AM)
6968 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6969 BasePtr, Offset, AM);
6972 DEBUG(dbgs() << "\nReplacing.5 ";
6974 dbgs() << "\nWith: ";
6975 Result.getNode()->dump(&DAG);
6977 WorkListRemover DeadNodes(*this);
6979 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
6980 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
6982 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
6985 // Finally, since the node is now dead, remove it from the graph.
6988 // Replace the uses of Use with uses of the updated base value.
6989 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
6990 Result.getValue(isLoad ? 1 : 0));
6991 removeFromWorkList(Op);
7001 SDValue DAGCombiner::visitLOAD(SDNode *N) {
7002 LoadSDNode *LD = cast<LoadSDNode>(N);
7003 SDValue Chain = LD->getChain();
7004 SDValue Ptr = LD->getBasePtr();
7006 // If load is not volatile and there are no uses of the loaded value (and
7007 // the updated indexed value in case of indexed loads), change uses of the
7008 // chain value into uses of the chain input (i.e. delete the dead load).
7009 if (!LD->isVolatile()) {
7010 if (N->getValueType(1) == MVT::Other) {
7012 if (!N->hasAnyUseOfValue(0)) {
7013 // It's not safe to use the two value CombineTo variant here. e.g.
7014 // v1, chain2 = load chain1, loc
7015 // v2, chain3 = load chain2, loc
7017 // Now we replace use of chain2 with chain1. This makes the second load
7018 // isomorphic to the one we are deleting, and thus makes this load live.
7019 DEBUG(dbgs() << "\nReplacing.6 ";
7021 dbgs() << "\nWith chain: ";
7022 Chain.getNode()->dump(&DAG);
7024 WorkListRemover DeadNodes(*this);
7025 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
7027 if (N->use_empty()) {
7028 removeFromWorkList(N);
7032 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7036 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
7037 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) {
7038 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
7039 DEBUG(dbgs() << "\nReplacing.7 ";
7041 dbgs() << "\nWith: ";
7042 Undef.getNode()->dump(&DAG);
7043 dbgs() << " and 2 other values\n");
7044 WorkListRemover DeadNodes(*this);
7045 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
7046 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
7047 DAG.getUNDEF(N->getValueType(1)));
7048 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
7049 removeFromWorkList(N);
7051 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7056 // If this load is directly stored, replace the load value with the stored
7058 // TODO: Handle store large -> read small portion.
7059 // TODO: Handle TRUNCSTORE/LOADEXT
7060 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
7061 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
7062 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
7063 if (PrevST->getBasePtr() == Ptr &&
7064 PrevST->getValue().getValueType() == N->getValueType(0))
7065 return CombineTo(N, Chain.getOperand(1), Chain);
7069 // Try to infer better alignment information than the load already has.
7070 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
7071 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
7072 if (Align > LD->getAlignment())
7073 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
7074 LD->getValueType(0),
7075 Chain, Ptr, LD->getPointerInfo(),
7077 LD->isVolatile(), LD->isNonTemporal(), Align);
7082 // Walk up chain skipping non-aliasing memory nodes.
7083 SDValue BetterChain = FindBetterChain(N, Chain);
7085 // If there is a better chain.
7086 if (Chain != BetterChain) {
7089 // Replace the chain to void dependency.
7090 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
7091 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
7092 BetterChain, Ptr, LD->getPointerInfo(),
7093 LD->isVolatile(), LD->isNonTemporal(),
7094 LD->isInvariant(), LD->getAlignment());
7096 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
7097 LD->getValueType(0),
7098 BetterChain, Ptr, LD->getPointerInfo(),
7101 LD->isNonTemporal(),
7102 LD->getAlignment());
7105 // Create token factor to keep old chain connected.
7106 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
7107 MVT::Other, Chain, ReplLoad.getValue(1));
7109 // Make sure the new and old chains are cleaned up.
7110 AddToWorkList(Token.getNode());
7112 // Replace uses with load result and token factor. Don't add users
7114 return CombineTo(N, ReplLoad.getValue(0), Token, false);
7118 // Try transforming N to an indexed load.
7119 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
7120 return SDValue(N, 0);
7125 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
7126 /// load is having specific bytes cleared out. If so, return the byte size
7127 /// being masked out and the shift amount.
7128 static std::pair<unsigned, unsigned>
7129 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
7130 std::pair<unsigned, unsigned> Result(0, 0);
7132 // Check for the structure we're looking for.
7133 if (V->getOpcode() != ISD::AND ||
7134 !isa<ConstantSDNode>(V->getOperand(1)) ||
7135 !ISD::isNormalLoad(V->getOperand(0).getNode()))
7138 // Check the chain and pointer.
7139 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
7140 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
7142 // The store should be chained directly to the load or be an operand of a
7144 if (LD == Chain.getNode())
7146 else if (Chain->getOpcode() != ISD::TokenFactor)
7147 return Result; // Fail.
7150 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
7151 if (Chain->getOperand(i).getNode() == LD) {
7155 if (!isOk) return Result;
7158 // This only handles simple types.
7159 if (V.getValueType() != MVT::i16 &&
7160 V.getValueType() != MVT::i32 &&
7161 V.getValueType() != MVT::i64)
7164 // Check the constant mask. Invert it so that the bits being masked out are
7165 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
7166 // follow the sign bit for uniformity.
7167 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
7168 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
7169 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
7170 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
7171 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
7172 if (NotMaskLZ == 64) return Result; // All zero mask.
7174 // See if we have a continuous run of bits. If so, we have 0*1+0*
7175 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
7178 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
7179 if (V.getValueType() != MVT::i64 && NotMaskLZ)
7180 NotMaskLZ -= 64-V.getValueSizeInBits();
7182 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
7183 switch (MaskedBytes) {
7187 default: return Result; // All one mask, or 5-byte mask.
7190 // Verify that the first bit starts at a multiple of mask so that the access
7191 // is aligned the same as the access width.
7192 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
7194 Result.first = MaskedBytes;
7195 Result.second = NotMaskTZ/8;
7200 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
7201 /// provides a value as specified by MaskInfo. If so, replace the specified
7202 /// store with a narrower store of truncated IVal.
7204 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
7205 SDValue IVal, StoreSDNode *St,
7207 unsigned NumBytes = MaskInfo.first;
7208 unsigned ByteShift = MaskInfo.second;
7209 SelectionDAG &DAG = DC->getDAG();
7211 // Check to see if IVal is all zeros in the part being masked in by the 'or'
7212 // that uses this. If not, this is not a replacement.
7213 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
7214 ByteShift*8, (ByteShift+NumBytes)*8);
7215 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
7217 // Check that it is legal on the target to do this. It is legal if the new
7218 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
7220 MVT VT = MVT::getIntegerVT(NumBytes*8);
7221 if (!DC->isTypeLegal(VT))
7224 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
7225 // shifted by ByteShift and truncated down to NumBytes.
7227 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
7228 DAG.getConstant(ByteShift*8,
7229 DC->getShiftAmountTy(IVal.getValueType())));
7231 // Figure out the offset for the store and the alignment of the access.
7233 unsigned NewAlign = St->getAlignment();
7235 if (DAG.getTargetLoweringInfo().isLittleEndian())
7236 StOffset = ByteShift;
7238 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
7240 SDValue Ptr = St->getBasePtr();
7242 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
7243 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
7244 NewAlign = MinAlign(NewAlign, StOffset);
7247 // Truncate down to the new size.
7248 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
7251 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
7252 St->getPointerInfo().getWithOffset(StOffset),
7253 false, false, NewAlign).getNode();
7257 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
7258 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
7259 /// of the loaded bits, try narrowing the load and store if it would end up
7260 /// being a win for performance or code size.
7261 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
7262 StoreSDNode *ST = cast<StoreSDNode>(N);
7263 if (ST->isVolatile())
7266 SDValue Chain = ST->getChain();
7267 SDValue Value = ST->getValue();
7268 SDValue Ptr = ST->getBasePtr();
7269 EVT VT = Value.getValueType();
7271 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
7274 unsigned Opc = Value.getOpcode();
7276 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
7277 // is a byte mask indicating a consecutive number of bytes, check to see if
7278 // Y is known to provide just those bytes. If so, we try to replace the
7279 // load + replace + store sequence with a single (narrower) store, which makes
7281 if (Opc == ISD::OR) {
7282 std::pair<unsigned, unsigned> MaskedLoad;
7283 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
7284 if (MaskedLoad.first)
7285 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
7286 Value.getOperand(1), ST,this))
7287 return SDValue(NewST, 0);
7289 // Or is commutative, so try swapping X and Y.
7290 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
7291 if (MaskedLoad.first)
7292 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
7293 Value.getOperand(0), ST,this))
7294 return SDValue(NewST, 0);
7297 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
7298 Value.getOperand(1).getOpcode() != ISD::Constant)
7301 SDValue N0 = Value.getOperand(0);
7302 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7303 Chain == SDValue(N0.getNode(), 1)) {
7304 LoadSDNode *LD = cast<LoadSDNode>(N0);
7305 if (LD->getBasePtr() != Ptr ||
7306 LD->getPointerInfo().getAddrSpace() !=
7307 ST->getPointerInfo().getAddrSpace())
7310 // Find the type to narrow it the load / op / store to.
7311 SDValue N1 = Value.getOperand(1);
7312 unsigned BitWidth = N1.getValueSizeInBits();
7313 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
7314 if (Opc == ISD::AND)
7315 Imm ^= APInt::getAllOnesValue(BitWidth);
7316 if (Imm == 0 || Imm.isAllOnesValue())
7318 unsigned ShAmt = Imm.countTrailingZeros();
7319 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
7320 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
7321 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
7322 while (NewBW < BitWidth &&
7323 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
7324 TLI.isNarrowingProfitable(VT, NewVT))) {
7325 NewBW = NextPowerOf2(NewBW);
7326 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
7328 if (NewBW >= BitWidth)
7331 // If the lsb changed does not start at the type bitwidth boundary,
7332 // start at the previous one.
7334 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
7335 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
7336 if ((Imm & Mask) == Imm) {
7337 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
7338 if (Opc == ISD::AND)
7339 NewImm ^= APInt::getAllOnesValue(NewBW);
7340 uint64_t PtrOff = ShAmt / 8;
7341 // For big endian targets, we need to adjust the offset to the pointer to
7342 // load the correct bytes.
7343 if (TLI.isBigEndian())
7344 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
7346 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
7347 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
7348 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
7351 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
7352 Ptr.getValueType(), Ptr,
7353 DAG.getConstant(PtrOff, Ptr.getValueType()));
7354 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
7355 LD->getChain(), NewPtr,
7356 LD->getPointerInfo().getWithOffset(PtrOff),
7357 LD->isVolatile(), LD->isNonTemporal(),
7358 LD->isInvariant(), NewAlign);
7359 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
7360 DAG.getConstant(NewImm, NewVT));
7361 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
7363 ST->getPointerInfo().getWithOffset(PtrOff),
7364 false, false, NewAlign);
7366 AddToWorkList(NewPtr.getNode());
7367 AddToWorkList(NewLD.getNode());
7368 AddToWorkList(NewVal.getNode());
7369 WorkListRemover DeadNodes(*this);
7370 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
7379 /// TransformFPLoadStorePair - For a given floating point load / store pair,
7380 /// if the load value isn't used by any other operations, then consider
7381 /// transforming the pair to integer load / store operations if the target
7382 /// deems the transformation profitable.
7383 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
7384 StoreSDNode *ST = cast<StoreSDNode>(N);
7385 SDValue Chain = ST->getChain();
7386 SDValue Value = ST->getValue();
7387 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
7388 Value.hasOneUse() &&
7389 Chain == SDValue(Value.getNode(), 1)) {
7390 LoadSDNode *LD = cast<LoadSDNode>(Value);
7391 EVT VT = LD->getMemoryVT();
7392 if (!VT.isFloatingPoint() ||
7393 VT != ST->getMemoryVT() ||
7394 LD->isNonTemporal() ||
7395 ST->isNonTemporal() ||
7396 LD->getPointerInfo().getAddrSpace() != 0 ||
7397 ST->getPointerInfo().getAddrSpace() != 0)
7400 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
7401 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
7402 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
7403 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
7404 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
7407 unsigned LDAlign = LD->getAlignment();
7408 unsigned STAlign = ST->getAlignment();
7409 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
7410 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy);
7411 if (LDAlign < ABIAlign || STAlign < ABIAlign)
7414 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
7415 LD->getChain(), LD->getBasePtr(),
7416 LD->getPointerInfo(),
7417 false, false, false, LDAlign);
7419 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
7420 NewLD, ST->getBasePtr(),
7421 ST->getPointerInfo(),
7422 false, false, STAlign);
7424 AddToWorkList(NewLD.getNode());
7425 AddToWorkList(NewST.getNode());
7426 WorkListRemover DeadNodes(*this);
7427 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
7435 SDValue DAGCombiner::visitSTORE(SDNode *N) {
7436 StoreSDNode *ST = cast<StoreSDNode>(N);
7437 SDValue Chain = ST->getChain();
7438 SDValue Value = ST->getValue();
7439 SDValue Ptr = ST->getBasePtr();
7441 // If this is a store of a bit convert, store the input value if the
7442 // resultant store does not need a higher alignment than the original.
7443 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
7444 ST->isUnindexed()) {
7445 unsigned OrigAlign = ST->getAlignment();
7446 EVT SVT = Value.getOperand(0).getValueType();
7447 unsigned Align = TLI.getTargetData()->
7448 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
7449 if (Align <= OrigAlign &&
7450 ((!LegalOperations && !ST->isVolatile()) ||
7451 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
7452 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
7453 Ptr, ST->getPointerInfo(), ST->isVolatile(),
7454 ST->isNonTemporal(), OrigAlign);
7457 // Turn 'store undef, Ptr' -> nothing.
7458 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
7461 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
7462 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
7463 // NOTE: If the original store is volatile, this transform must not increase
7464 // the number of stores. For example, on x86-32 an f64 can be stored in one
7465 // processor operation but an i64 (which is not legal) requires two. So the
7466 // transform should not be done in this case.
7467 if (Value.getOpcode() != ISD::TargetConstantFP) {
7469 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
7470 default: llvm_unreachable("Unknown FP type");
7471 case MVT::f16: // We don't do this for these yet.
7477 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
7478 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
7479 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
7480 bitcastToAPInt().getZExtValue(), MVT::i32);
7481 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
7482 Ptr, ST->getPointerInfo(), ST->isVolatile(),
7483 ST->isNonTemporal(), ST->getAlignment());
7487 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
7488 !ST->isVolatile()) ||
7489 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
7490 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
7491 getZExtValue(), MVT::i64);
7492 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
7493 Ptr, ST->getPointerInfo(), ST->isVolatile(),
7494 ST->isNonTemporal(), ST->getAlignment());
7497 if (!ST->isVolatile() &&
7498 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
7499 // Many FP stores are not made apparent until after legalize, e.g. for
7500 // argument passing. Since this is so common, custom legalize the
7501 // 64-bit integer store into two 32-bit stores.
7502 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
7503 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
7504 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
7505 if (TLI.isBigEndian()) std::swap(Lo, Hi);
7507 unsigned Alignment = ST->getAlignment();
7508 bool isVolatile = ST->isVolatile();
7509 bool isNonTemporal = ST->isNonTemporal();
7511 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
7512 Ptr, ST->getPointerInfo(),
7513 isVolatile, isNonTemporal,
7514 ST->getAlignment());
7515 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
7516 DAG.getConstant(4, Ptr.getValueType()));
7517 Alignment = MinAlign(Alignment, 4U);
7518 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
7519 Ptr, ST->getPointerInfo().getWithOffset(4),
7520 isVolatile, isNonTemporal,
7522 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
7531 // Try to infer better alignment information than the store already has.
7532 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
7533 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
7534 if (Align > ST->getAlignment())
7535 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
7536 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
7537 ST->isVolatile(), ST->isNonTemporal(), Align);
7541 // Try transforming a pair floating point load / store ops to integer
7542 // load / store ops.
7543 SDValue NewST = TransformFPLoadStorePair(N);
7544 if (NewST.getNode())
7548 // Walk up chain skipping non-aliasing memory nodes.
7549 SDValue BetterChain = FindBetterChain(N, Chain);
7551 // If there is a better chain.
7552 if (Chain != BetterChain) {
7555 // Replace the chain to avoid dependency.
7556 if (ST->isTruncatingStore()) {
7557 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
7558 ST->getPointerInfo(),
7559 ST->getMemoryVT(), ST->isVolatile(),
7560 ST->isNonTemporal(), ST->getAlignment());
7562 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
7563 ST->getPointerInfo(),
7564 ST->isVolatile(), ST->isNonTemporal(),
7565 ST->getAlignment());
7568 // Create token to keep both nodes around.
7569 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
7570 MVT::Other, Chain, ReplStore);
7572 // Make sure the new and old chains are cleaned up.
7573 AddToWorkList(Token.getNode());
7575 // Don't add users to work list.
7576 return CombineTo(N, Token, false);
7580 // Try transforming N to an indexed store.
7581 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
7582 return SDValue(N, 0);
7584 // FIXME: is there such a thing as a truncating indexed store?
7585 if (ST->isTruncatingStore() && ST->isUnindexed() &&
7586 Value.getValueType().isInteger()) {
7587 // See if we can simplify the input to this truncstore with knowledge that
7588 // only the low bits are being used. For example:
7589 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
7591 GetDemandedBits(Value,
7592 APInt::getLowBitsSet(
7593 Value.getValueType().getScalarType().getSizeInBits(),
7594 ST->getMemoryVT().getScalarType().getSizeInBits()));
7595 AddToWorkList(Value.getNode());
7596 if (Shorter.getNode())
7597 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
7598 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
7599 ST->isVolatile(), ST->isNonTemporal(),
7600 ST->getAlignment());
7602 // Otherwise, see if we can simplify the operation with
7603 // SimplifyDemandedBits, which only works if the value has a single use.
7604 if (SimplifyDemandedBits(Value,
7605 APInt::getLowBitsSet(
7606 Value.getValueType().getScalarType().getSizeInBits(),
7607 ST->getMemoryVT().getScalarType().getSizeInBits())))
7608 return SDValue(N, 0);
7611 // If this is a load followed by a store to the same location, then the store
7613 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
7614 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
7615 ST->isUnindexed() && !ST->isVolatile() &&
7616 // There can't be any side effects between the load and store, such as
7618 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
7619 // The store is dead, remove it.
7624 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
7625 // truncating store. We can do this even if this is already a truncstore.
7626 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
7627 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
7628 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
7629 ST->getMemoryVT())) {
7630 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
7631 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
7632 ST->isVolatile(), ST->isNonTemporal(),
7633 ST->getAlignment());
7636 return ReduceLoadOpStoreWidth(N);
7639 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
7640 SDValue InVec = N->getOperand(0);
7641 SDValue InVal = N->getOperand(1);
7642 SDValue EltNo = N->getOperand(2);
7643 DebugLoc dl = N->getDebugLoc();
7645 // If the inserted element is an UNDEF, just use the input vector.
7646 if (InVal.getOpcode() == ISD::UNDEF)
7649 EVT VT = InVec.getValueType();
7651 // If we can't generate a legal BUILD_VECTOR, exit
7652 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
7655 // Check that we know which element is being inserted
7656 if (!isa<ConstantSDNode>(EltNo))
7658 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7660 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
7661 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
7663 SmallVector<SDValue, 8> Ops;
7664 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
7665 Ops.append(InVec.getNode()->op_begin(),
7666 InVec.getNode()->op_end());
7667 } else if (InVec.getOpcode() == ISD::UNDEF) {
7668 unsigned NElts = VT.getVectorNumElements();
7669 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
7674 // Insert the element
7675 if (Elt < Ops.size()) {
7676 // All the operands of BUILD_VECTOR must have the same type;
7677 // we enforce that here.
7678 EVT OpVT = Ops[0].getValueType();
7679 if (InVal.getValueType() != OpVT)
7680 InVal = OpVT.bitsGT(InVal.getValueType()) ?
7681 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
7682 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
7686 // Return the new vector
7687 return DAG.getNode(ISD::BUILD_VECTOR, dl,
7688 VT, &Ops[0], Ops.size());
7691 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
7692 // (vextract (scalar_to_vector val, 0) -> val
7693 SDValue InVec = N->getOperand(0);
7694 EVT VT = InVec.getValueType();
7695 EVT NVT = N->getValueType(0);
7697 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
7698 // Check if the result type doesn't match the inserted element type. A
7699 // SCALAR_TO_VECTOR may truncate the inserted element and the
7700 // EXTRACT_VECTOR_ELT may widen the extracted vector.
7701 SDValue InOp = InVec.getOperand(0);
7702 if (InOp.getValueType() != NVT) {
7703 assert(InOp.getValueType().isInteger() && NVT.isInteger());
7704 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
7709 SDValue EltNo = N->getOperand(1);
7710 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
7712 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
7713 // We only perform this optimization before the op legalization phase because
7714 // we may introduce new vector instructions which are not backed by TD patterns.
7715 // For example on AVX, extracting elements from a wide vector without using
7716 // extract_subvector.
7717 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
7718 && ConstEltNo && !LegalOperations) {
7719 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7720 int NumElem = VT.getVectorNumElements();
7721 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
7722 // Find the new index to extract from.
7723 int OrigElt = SVOp->getMaskElt(Elt);
7725 // Extracting an undef index is undef.
7727 return DAG.getUNDEF(NVT);
7729 // Select the right vector half to extract from.
7730 if (OrigElt < NumElem) {
7731 InVec = InVec->getOperand(0);
7733 InVec = InVec->getOperand(1);
7737 EVT IndexTy = N->getOperand(1).getValueType();
7738 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT,
7739 InVec, DAG.getConstant(OrigElt, IndexTy));
7742 // Perform only after legalization to ensure build_vector / vector_shuffle
7743 // optimizations have already been done.
7744 if (!LegalOperations) return SDValue();
7746 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
7747 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
7748 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
7751 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7752 bool NewLoad = false;
7753 bool BCNumEltsChanged = false;
7754 EVT ExtVT = VT.getVectorElementType();
7757 // If the result of load has to be truncated, then it's not necessarily
7759 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
7762 if (InVec.getOpcode() == ISD::BITCAST) {
7763 // Don't duplicate a load with other uses.
7764 if (!InVec.hasOneUse())
7767 EVT BCVT = InVec.getOperand(0).getValueType();
7768 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
7770 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
7771 BCNumEltsChanged = true;
7772 InVec = InVec.getOperand(0);
7773 ExtVT = BCVT.getVectorElementType();
7777 LoadSDNode *LN0 = NULL;
7778 const ShuffleVectorSDNode *SVN = NULL;
7779 if (ISD::isNormalLoad(InVec.getNode())) {
7780 LN0 = cast<LoadSDNode>(InVec);
7781 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7782 InVec.getOperand(0).getValueType() == ExtVT &&
7783 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
7784 // Don't duplicate a load with other uses.
7785 if (!InVec.hasOneUse())
7788 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
7789 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
7790 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
7792 // (load $addr+1*size)
7794 // Don't duplicate a load with other uses.
7795 if (!InVec.hasOneUse())
7798 // If the bit convert changed the number of elements, it is unsafe
7799 // to examine the mask.
7800 if (BCNumEltsChanged)
7803 // Select the input vector, guarding against out of range extract vector.
7804 unsigned NumElems = VT.getVectorNumElements();
7805 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
7806 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
7808 if (InVec.getOpcode() == ISD::BITCAST) {
7809 // Don't duplicate a load with other uses.
7810 if (!InVec.hasOneUse())
7813 InVec = InVec.getOperand(0);
7815 if (ISD::isNormalLoad(InVec.getNode())) {
7816 LN0 = cast<LoadSDNode>(InVec);
7817 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
7821 // Make sure we found a non-volatile load and the extractelement is
7823 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
7826 // If Idx was -1 above, Elt is going to be -1, so just return undef.
7828 return DAG.getUNDEF(LVT);
7830 unsigned Align = LN0->getAlignment();
7832 // Check the resultant load doesn't need a higher alignment than the
7836 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
7838 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
7844 SDValue NewPtr = LN0->getBasePtr();
7845 unsigned PtrOff = 0;
7848 PtrOff = LVT.getSizeInBits() * Elt / 8;
7849 EVT PtrType = NewPtr.getValueType();
7850 if (TLI.isBigEndian())
7851 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
7852 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
7853 DAG.getConstant(PtrOff, PtrType));
7856 // The replacement we need to do here is a little tricky: we need to
7857 // replace an extractelement of a load with a load.
7858 // Use ReplaceAllUsesOfValuesWith to do the replacement.
7859 // Note that this replacement assumes that the extractvalue is the only
7860 // use of the load; that's okay because we don't want to perform this
7861 // transformation in other cases anyway.
7864 if (NVT.bitsGT(LVT)) {
7865 // If the result type of vextract is wider than the load, then issue an
7866 // extending load instead.
7867 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT)
7868 ? ISD::ZEXTLOAD : ISD::EXTLOAD;
7869 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(),
7870 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff),
7871 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align);
7872 Chain = Load.getValue(1);
7874 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
7875 LN0->getPointerInfo().getWithOffset(PtrOff),
7876 LN0->isVolatile(), LN0->isNonTemporal(),
7877 LN0->isInvariant(), Align);
7878 Chain = Load.getValue(1);
7879 if (NVT.bitsLT(LVT))
7880 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load);
7882 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load);
7884 WorkListRemover DeadNodes(*this);
7885 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) };
7886 SDValue To[] = { Load, Chain };
7887 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7888 // Since we're explcitly calling ReplaceAllUses, add the new node to the
7889 // worklist explicitly as well.
7890 AddToWorkList(Load.getNode());
7891 AddUsersToWorkList(Load.getNode()); // Add users too
7892 // Make sure to revisit this node to clean it up; it will usually be dead.
7894 return SDValue(N, 0);
7900 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
7901 unsigned NumInScalars = N->getNumOperands();
7902 DebugLoc dl = N->getDebugLoc();
7903 EVT VT = N->getValueType(0);
7905 // A vector built entirely of undefs is undef.
7906 if (ISD::allOperandsUndef(N))
7907 return DAG.getUNDEF(VT);
7909 // Check to see if this is a BUILD_VECTOR of a bunch of values
7910 // which come from any_extend or zero_extend nodes. If so, we can create
7911 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
7912 // optimizations. We do not handle sign-extend because we can't fill the sign
7914 EVT SourceType = MVT::Other;
7915 bool AllAnyExt = true;
7917 for (unsigned i = 0; i != NumInScalars; ++i) {
7918 SDValue In = N->getOperand(i);
7919 // Ignore undef inputs.
7920 if (In.getOpcode() == ISD::UNDEF) continue;
7922 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
7923 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
7925 // Abort if the element is not an extension.
7926 if (!ZeroExt && !AnyExt) {
7927 SourceType = MVT::Other;
7931 // The input is a ZeroExt or AnyExt. Check the original type.
7932 EVT InTy = In.getOperand(0).getValueType();
7934 // Check that all of the widened source types are the same.
7935 if (SourceType == MVT::Other)
7938 else if (InTy != SourceType) {
7939 // Multiple income types. Abort.
7940 SourceType = MVT::Other;
7944 // Check if all of the extends are ANY_EXTENDs.
7945 AllAnyExt &= AnyExt;
7948 // In order to have valid types, all of the inputs must be extended from the
7949 // same source type and all of the inputs must be any or zero extend.
7950 // Scalar sizes must be a power of two.
7951 EVT OutScalarTy = N->getValueType(0).getScalarType();
7952 bool ValidTypes = SourceType != MVT::Other &&
7953 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
7954 isPowerOf2_32(SourceType.getSizeInBits());
7956 // We perform this optimization post type-legalization because
7957 // the type-legalizer often scalarizes integer-promoted vectors.
7958 // Performing this optimization before may create bit-casts which
7959 // will be type-legalized to complex code sequences.
7960 // We perform this optimization only before the operation legalizer because we
7961 // may introduce illegal operations.
7962 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
7963 // turn into a single shuffle instruction.
7964 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) &&
7966 bool isLE = TLI.isLittleEndian();
7967 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
7968 assert(ElemRatio > 1 && "Invalid element size ratio");
7969 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
7970 DAG.getConstant(0, SourceType);
7972 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements();
7973 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
7975 // Populate the new build_vector
7976 for (unsigned i=0; i < N->getNumOperands(); ++i) {
7977 SDValue Cast = N->getOperand(i);
7978 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
7979 Cast.getOpcode() == ISD::ZERO_EXTEND ||
7980 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
7982 if (Cast.getOpcode() == ISD::UNDEF)
7983 In = DAG.getUNDEF(SourceType);
7985 In = Cast->getOperand(0);
7986 unsigned Index = isLE ? (i * ElemRatio) :
7987 (i * ElemRatio + (ElemRatio - 1));
7989 assert(Index < Ops.size() && "Invalid index");
7993 // The type of the new BUILD_VECTOR node.
7994 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
7995 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() &&
7996 "Invalid vector size");
7997 // Check if the new vector type is legal.
7998 if (!isTypeLegal(VecVT)) return SDValue();
8000 // Make the new BUILD_VECTOR.
8001 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
8002 VecVT, &Ops[0], Ops.size());
8004 // The new BUILD_VECTOR node has the potential to be further optimized.
8005 AddToWorkList(BV.getNode());
8006 // Bitcast to the desired type.
8007 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV);
8010 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
8011 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
8012 // at most two distinct vectors, turn this into a shuffle node.
8014 // May only combine to shuffle after legalize if shuffle is legal.
8015 if (LegalOperations &&
8016 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))
8019 SDValue VecIn1, VecIn2;
8020 for (unsigned i = 0; i != NumInScalars; ++i) {
8021 // Ignore undef inputs.
8022 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
8024 // If this input is something other than a EXTRACT_VECTOR_ELT with a
8025 // constant index, bail out.
8026 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8027 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
8028 VecIn1 = VecIn2 = SDValue(0, 0);
8032 // We allow up to two distinct input vectors.
8033 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
8034 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
8037 if (VecIn1.getNode() == 0) {
8038 VecIn1 = ExtractedFromVec;
8039 } else if (VecIn2.getNode() == 0) {
8040 VecIn2 = ExtractedFromVec;
8043 VecIn1 = VecIn2 = SDValue(0, 0);
8048 // If everything is good, we can make a shuffle operation.
8049 if (VecIn1.getNode()) {
8050 SmallVector<int, 8> Mask;
8051 for (unsigned i = 0; i != NumInScalars; ++i) {
8052 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
8057 // If extracting from the first vector, just use the index directly.
8058 SDValue Extract = N->getOperand(i);
8059 SDValue ExtVal = Extract.getOperand(1);
8060 if (Extract.getOperand(0) == VecIn1) {
8061 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
8062 if (ExtIndex > VT.getVectorNumElements())
8065 Mask.push_back(ExtIndex);
8069 // Otherwise, use InIdx + VecSize
8070 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
8071 Mask.push_back(Idx+NumInScalars);
8074 // We can't generate a shuffle node with mismatched input and output types.
8075 // Attempt to transform a single input vector to the correct type.
8076 if ((VT != VecIn1.getValueType())) {
8077 // We don't support shuffeling between TWO values of different types.
8078 if (VecIn2.getNode() != 0)
8081 // We only support widening of vectors which are half the size of the
8082 // output registers. For example XMM->YMM widening on X86 with AVX.
8083 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
8086 // If the input vector type has a different base type to the output
8087 // vector type, bail out.
8088 if (VecIn1.getValueType().getVectorElementType() !=
8089 VT.getVectorElementType())
8092 // Widen the input vector by adding undef values.
8093 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
8094 VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
8097 // If VecIn2 is unused then change it to undef.
8098 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
8100 // Check that we were able to transform all incoming values to the same type.
8101 if (VecIn2.getValueType() != VecIn1.getValueType() ||
8102 VecIn1.getValueType() != VT)
8105 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
8106 if (!isTypeLegal(VT))
8109 // Return the new VECTOR_SHUFFLE node.
8113 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
8119 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
8120 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
8121 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
8122 // inputs come from at most two distinct vectors, turn this into a shuffle
8125 // If we only have one input vector, we don't need to do any concatenation.
8126 if (N->getNumOperands() == 1)
8127 return N->getOperand(0);
8129 // Check if all of the operands are undefs.
8130 if (ISD::allOperandsUndef(N))
8131 return DAG.getUNDEF(N->getValueType(0));
8136 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
8137 EVT NVT = N->getValueType(0);
8138 SDValue V = N->getOperand(0);
8140 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
8141 // Handle only simple case where vector being inserted and vector
8142 // being extracted are of same type, and are half size of larger vectors.
8143 EVT BigVT = V->getOperand(0).getValueType();
8144 EVT SmallVT = V->getOperand(1).getValueType();
8145 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
8148 // Only handle cases where both indexes are constants with the same type.
8149 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
8150 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
8152 if (InsIdx && ExtIdx &&
8153 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
8154 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
8156 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
8158 // indices are equal => V1
8159 // otherwise => (extract_subvec V1, ExtIdx)
8160 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue())
8161 return V->getOperand(1);
8162 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT,
8163 V->getOperand(0), N->getOperand(1));
8170 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
8171 EVT VT = N->getValueType(0);
8172 unsigned NumElts = VT.getVectorNumElements();
8174 SDValue N0 = N->getOperand(0);
8175 SDValue N1 = N->getOperand(1);
8177 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
8179 // Canonicalize shuffle undef, undef -> undef
8180 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
8181 return DAG.getUNDEF(VT);
8183 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8185 // Canonicalize shuffle v, v -> v, undef
8187 SmallVector<int, 8> NewMask;
8188 for (unsigned i = 0; i != NumElts; ++i) {
8189 int Idx = SVN->getMaskElt(i);
8190 if (Idx >= (int)NumElts) Idx -= NumElts;
8191 NewMask.push_back(Idx);
8193 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT),
8197 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
8198 if (N0.getOpcode() == ISD::UNDEF) {
8199 SmallVector<int, 8> NewMask;
8200 for (unsigned i = 0; i != NumElts; ++i) {
8201 int Idx = SVN->getMaskElt(i);
8203 if (Idx < (int)NumElts)
8208 NewMask.push_back(Idx);
8210 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT),
8214 // Remove references to rhs if it is undef
8215 if (N1.getOpcode() == ISD::UNDEF) {
8216 bool Changed = false;
8217 SmallVector<int, 8> NewMask;
8218 for (unsigned i = 0; i != NumElts; ++i) {
8219 int Idx = SVN->getMaskElt(i);
8220 if (Idx >= (int)NumElts) {
8224 NewMask.push_back(Idx);
8227 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]);
8230 // If it is a splat, check if the argument vector is another splat or a
8231 // build_vector with all scalar elements the same.
8232 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
8233 SDNode *V = N0.getNode();
8235 // If this is a bit convert that changes the element type of the vector but
8236 // not the number of vector elements, look through it. Be careful not to
8237 // look though conversions that change things like v4f32 to v2f64.
8238 if (V->getOpcode() == ISD::BITCAST) {
8239 SDValue ConvInput = V->getOperand(0);
8240 if (ConvInput.getValueType().isVector() &&
8241 ConvInput.getValueType().getVectorNumElements() == NumElts)
8242 V = ConvInput.getNode();
8245 if (V->getOpcode() == ISD::BUILD_VECTOR) {
8246 assert(V->getNumOperands() == NumElts &&
8247 "BUILD_VECTOR has wrong number of operands");
8249 bool AllSame = true;
8250 for (unsigned i = 0; i != NumElts; ++i) {
8251 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
8252 Base = V->getOperand(i);
8256 // Splat of <u, u, u, u>, return <u, u, u, u>
8257 if (!Base.getNode())
8259 for (unsigned i = 0; i != NumElts; ++i) {
8260 if (V->getOperand(i) != Base) {
8265 // Splat of <x, x, x, x>, return <x, x, x, x>
8271 // If this shuffle node is simply a swizzle of another shuffle node,
8272 // and it reverses the swizzle of the previous shuffle then we can
8273 // optimize shuffle(shuffle(x, undef), undef) -> x.
8274 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
8275 N1.getOpcode() == ISD::UNDEF) {
8277 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
8279 // Shuffle nodes can only reverse shuffles with a single non-undef value.
8280 if (N0.getOperand(1).getOpcode() != ISD::UNDEF)
8283 // The incoming shuffle must be of the same type as the result of the
8285 assert(OtherSV->getOperand(0).getValueType() == VT &&
8286 "Shuffle types don't match");
8288 for (unsigned i = 0; i != NumElts; ++i) {
8289 int Idx = SVN->getMaskElt(i);
8290 assert(Idx < (int)NumElts && "Index references undef operand");
8291 // Next, this index comes from the first value, which is the incoming
8292 // shuffle. Adopt the incoming index.
8294 Idx = OtherSV->getMaskElt(Idx);
8296 // The combined shuffle must map each index to itself.
8297 if (Idx >= 0 && (unsigned)Idx != i)
8301 return OtherSV->getOperand(0);
8307 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
8308 if (!TLI.getShouldFoldAtomicFences())
8311 SDValue atomic = N->getOperand(0);
8312 switch (atomic.getOpcode()) {
8313 case ISD::ATOMIC_CMP_SWAP:
8314 case ISD::ATOMIC_SWAP:
8315 case ISD::ATOMIC_LOAD_ADD:
8316 case ISD::ATOMIC_LOAD_SUB:
8317 case ISD::ATOMIC_LOAD_AND:
8318 case ISD::ATOMIC_LOAD_OR:
8319 case ISD::ATOMIC_LOAD_XOR:
8320 case ISD::ATOMIC_LOAD_NAND:
8321 case ISD::ATOMIC_LOAD_MIN:
8322 case ISD::ATOMIC_LOAD_MAX:
8323 case ISD::ATOMIC_LOAD_UMIN:
8324 case ISD::ATOMIC_LOAD_UMAX:
8330 SDValue fence = atomic.getOperand(0);
8331 if (fence.getOpcode() != ISD::MEMBARRIER)
8334 switch (atomic.getOpcode()) {
8335 case ISD::ATOMIC_CMP_SWAP:
8336 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
8337 fence.getOperand(0),
8338 atomic.getOperand(1), atomic.getOperand(2),
8339 atomic.getOperand(3)), atomic.getResNo());
8340 case ISD::ATOMIC_SWAP:
8341 case ISD::ATOMIC_LOAD_ADD:
8342 case ISD::ATOMIC_LOAD_SUB:
8343 case ISD::ATOMIC_LOAD_AND:
8344 case ISD::ATOMIC_LOAD_OR:
8345 case ISD::ATOMIC_LOAD_XOR:
8346 case ISD::ATOMIC_LOAD_NAND:
8347 case ISD::ATOMIC_LOAD_MIN:
8348 case ISD::ATOMIC_LOAD_MAX:
8349 case ISD::ATOMIC_LOAD_UMIN:
8350 case ISD::ATOMIC_LOAD_UMAX:
8351 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
8352 fence.getOperand(0),
8353 atomic.getOperand(1), atomic.getOperand(2)),
8360 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
8361 /// an AND to a vector_shuffle with the destination vector and a zero vector.
8362 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
8363 /// vector_shuffle V, Zero, <0, 4, 2, 4>
8364 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
8365 EVT VT = N->getValueType(0);
8366 DebugLoc dl = N->getDebugLoc();
8367 SDValue LHS = N->getOperand(0);
8368 SDValue RHS = N->getOperand(1);
8369 if (N->getOpcode() == ISD::AND) {
8370 if (RHS.getOpcode() == ISD::BITCAST)
8371 RHS = RHS.getOperand(0);
8372 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
8373 SmallVector<int, 8> Indices;
8374 unsigned NumElts = RHS.getNumOperands();
8375 for (unsigned i = 0; i != NumElts; ++i) {
8376 SDValue Elt = RHS.getOperand(i);
8377 if (!isa<ConstantSDNode>(Elt))
8380 if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
8381 Indices.push_back(i);
8382 else if (cast<ConstantSDNode>(Elt)->isNullValue())
8383 Indices.push_back(NumElts);
8388 // Let's see if the target supports this vector_shuffle.
8389 EVT RVT = RHS.getValueType();
8390 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
8393 // Return the new VECTOR_SHUFFLE node.
8394 EVT EltVT = RVT.getVectorElementType();
8395 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
8396 DAG.getConstant(0, EltVT));
8397 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
8398 RVT, &ZeroOps[0], ZeroOps.size());
8399 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
8400 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
8401 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
8408 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
8409 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
8410 // After legalize, the target may be depending on adds and other
8411 // binary ops to provide legal ways to construct constants or other
8412 // things. Simplifying them may result in a loss of legality.
8413 if (LegalOperations) return SDValue();
8415 assert(N->getValueType(0).isVector() &&
8416 "SimplifyVBinOp only works on vectors!");
8418 SDValue LHS = N->getOperand(0);
8419 SDValue RHS = N->getOperand(1);
8420 SDValue Shuffle = XformToShuffleWithZero(N);
8421 if (Shuffle.getNode()) return Shuffle;
8423 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
8425 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
8426 RHS.getOpcode() == ISD::BUILD_VECTOR) {
8427 SmallVector<SDValue, 8> Ops;
8428 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
8429 SDValue LHSOp = LHS.getOperand(i);
8430 SDValue RHSOp = RHS.getOperand(i);
8431 // If these two elements can't be folded, bail out.
8432 if ((LHSOp.getOpcode() != ISD::UNDEF &&
8433 LHSOp.getOpcode() != ISD::Constant &&
8434 LHSOp.getOpcode() != ISD::ConstantFP) ||
8435 (RHSOp.getOpcode() != ISD::UNDEF &&
8436 RHSOp.getOpcode() != ISD::Constant &&
8437 RHSOp.getOpcode() != ISD::ConstantFP))
8440 // Can't fold divide by zero.
8441 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
8442 N->getOpcode() == ISD::FDIV) {
8443 if ((RHSOp.getOpcode() == ISD::Constant &&
8444 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
8445 (RHSOp.getOpcode() == ISD::ConstantFP &&
8446 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
8450 EVT VT = LHSOp.getValueType();
8451 EVT RVT = RHSOp.getValueType();
8453 // Integer BUILD_VECTOR operands may have types larger than the element
8454 // size (e.g., when the element type is not legal). Prior to type
8455 // legalization, the types may not match between the two BUILD_VECTORS.
8456 // Truncate one of the operands to make them match.
8457 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
8458 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp);
8460 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp);
8464 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
8466 if (FoldOp.getOpcode() != ISD::UNDEF &&
8467 FoldOp.getOpcode() != ISD::Constant &&
8468 FoldOp.getOpcode() != ISD::ConstantFP)
8470 Ops.push_back(FoldOp);
8471 AddToWorkList(FoldOp.getNode());
8474 if (Ops.size() == LHS.getNumOperands())
8475 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
8476 LHS.getValueType(), &Ops[0], Ops.size());
8482 /// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG.
8483 SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) {
8484 // After legalize, the target may be depending on adds and other
8485 // binary ops to provide legal ways to construct constants or other
8486 // things. Simplifying them may result in a loss of legality.
8487 if (LegalOperations) return SDValue();
8489 assert(N->getValueType(0).isVector() &&
8490 "SimplifyVUnaryOp only works on vectors!");
8492 SDValue N0 = N->getOperand(0);
8494 if (N0.getOpcode() != ISD::BUILD_VECTOR)
8497 // Operand is a BUILD_VECTOR node, see if we can constant fold it.
8498 SmallVector<SDValue, 8> Ops;
8499 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
8500 SDValue Op = N0.getOperand(i);
8501 if (Op.getOpcode() != ISD::UNDEF &&
8502 Op.getOpcode() != ISD::ConstantFP)
8504 EVT EltVT = Op.getValueType();
8505 SDValue FoldOp = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), EltVT, Op);
8506 if (FoldOp.getOpcode() != ISD::UNDEF &&
8507 FoldOp.getOpcode() != ISD::ConstantFP)
8509 Ops.push_back(FoldOp);
8510 AddToWorkList(FoldOp.getNode());
8513 if (Ops.size() != N0.getNumOperands())
8516 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
8517 N0.getValueType(), &Ops[0], Ops.size());
8520 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
8521 SDValue N1, SDValue N2){
8522 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
8524 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
8525 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8527 // If we got a simplified select_cc node back from SimplifySelectCC, then
8528 // break it down into a new SETCC node, and a new SELECT node, and then return
8529 // the SELECT node, since we were called with a SELECT node.
8530 if (SCC.getNode()) {
8531 // Check to see if we got a select_cc back (to turn into setcc/select).
8532 // Otherwise, just return whatever node we got back, like fabs.
8533 if (SCC.getOpcode() == ISD::SELECT_CC) {
8534 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
8536 SCC.getOperand(0), SCC.getOperand(1),
8538 AddToWorkList(SETCC.getNode());
8539 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
8540 SCC.getOperand(2), SCC.getOperand(3), SETCC);
8548 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
8549 /// are the two values being selected between, see if we can simplify the
8550 /// select. Callers of this should assume that TheSelect is deleted if this
8551 /// returns true. As such, they should return the appropriate thing (e.g. the
8552 /// node) back to the top-level of the DAG combiner loop to avoid it being
8554 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
8557 // Cannot simplify select with vector condition
8558 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
8560 // If this is a select from two identical things, try to pull the operation
8561 // through the select.
8562 if (LHS.getOpcode() != RHS.getOpcode() ||
8563 !LHS.hasOneUse() || !RHS.hasOneUse())
8566 // If this is a load and the token chain is identical, replace the select
8567 // of two loads with a load through a select of the address to load from.
8568 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
8569 // constants have been dropped into the constant pool.
8570 if (LHS.getOpcode() == ISD::LOAD) {
8571 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
8572 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
8574 // Token chains must be identical.
8575 if (LHS.getOperand(0) != RHS.getOperand(0) ||
8576 // Do not let this transformation reduce the number of volatile loads.
8577 LLD->isVolatile() || RLD->isVolatile() ||
8578 // If this is an EXTLOAD, the VT's must match.
8579 LLD->getMemoryVT() != RLD->getMemoryVT() ||
8580 // If this is an EXTLOAD, the kind of extension must match.
8581 (LLD->getExtensionType() != RLD->getExtensionType() &&
8582 // The only exception is if one of the extensions is anyext.
8583 LLD->getExtensionType() != ISD::EXTLOAD &&
8584 RLD->getExtensionType() != ISD::EXTLOAD) ||
8585 // FIXME: this discards src value information. This is
8586 // over-conservative. It would be beneficial to be able to remember
8587 // both potential memory locations. Since we are discarding
8588 // src value info, don't do the transformation if the memory
8589 // locations are not in the default address space.
8590 LLD->getPointerInfo().getAddrSpace() != 0 ||
8591 RLD->getPointerInfo().getAddrSpace() != 0)
8594 // Check that the select condition doesn't reach either load. If so,
8595 // folding this will induce a cycle into the DAG. If not, this is safe to
8596 // xform, so create a select of the addresses.
8598 if (TheSelect->getOpcode() == ISD::SELECT) {
8599 SDNode *CondNode = TheSelect->getOperand(0).getNode();
8600 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
8601 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
8603 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
8604 LLD->getBasePtr().getValueType(),
8605 TheSelect->getOperand(0), LLD->getBasePtr(),
8607 } else { // Otherwise SELECT_CC
8608 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
8609 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
8611 if ((LLD->hasAnyUseOfValue(1) &&
8612 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
8613 (RLD->hasAnyUseOfValue(1) &&
8614 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
8617 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
8618 LLD->getBasePtr().getValueType(),
8619 TheSelect->getOperand(0),
8620 TheSelect->getOperand(1),
8621 LLD->getBasePtr(), RLD->getBasePtr(),
8622 TheSelect->getOperand(4));
8626 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
8627 Load = DAG.getLoad(TheSelect->getValueType(0),
8628 TheSelect->getDebugLoc(),
8629 // FIXME: Discards pointer info.
8630 LLD->getChain(), Addr, MachinePointerInfo(),
8631 LLD->isVolatile(), LLD->isNonTemporal(),
8632 LLD->isInvariant(), LLD->getAlignment());
8634 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
8635 RLD->getExtensionType() : LLD->getExtensionType(),
8636 TheSelect->getDebugLoc(),
8637 TheSelect->getValueType(0),
8638 // FIXME: Discards pointer info.
8639 LLD->getChain(), Addr, MachinePointerInfo(),
8640 LLD->getMemoryVT(), LLD->isVolatile(),
8641 LLD->isNonTemporal(), LLD->getAlignment());
8644 // Users of the select now use the result of the load.
8645 CombineTo(TheSelect, Load);
8647 // Users of the old loads now use the new load's chain. We know the
8648 // old-load value is dead now.
8649 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
8650 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
8657 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
8658 /// where 'cond' is the comparison specified by CC.
8659 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
8660 SDValue N2, SDValue N3,
8661 ISD::CondCode CC, bool NotExtCompare) {
8662 // (x ? y : y) -> y.
8663 if (N2 == N3) return N2;
8665 EVT VT = N2.getValueType();
8666 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
8667 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
8668 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
8670 // Determine if the condition we're dealing with is constant
8671 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
8672 N0, N1, CC, DL, false);
8673 if (SCC.getNode()) AddToWorkList(SCC.getNode());
8674 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
8676 // fold select_cc true, x, y -> x
8677 if (SCCC && !SCCC->isNullValue())
8679 // fold select_cc false, x, y -> y
8680 if (SCCC && SCCC->isNullValue())
8683 // Check to see if we can simplify the select into an fabs node
8684 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
8685 // Allow either -0.0 or 0.0
8686 if (CFP->getValueAPF().isZero()) {
8687 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
8688 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
8689 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
8690 N2 == N3.getOperand(0))
8691 return DAG.getNode(ISD::FABS, DL, VT, N0);
8693 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
8694 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
8695 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
8696 N2.getOperand(0) == N3)
8697 return DAG.getNode(ISD::FABS, DL, VT, N3);
8701 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
8702 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
8703 // in it. This is a win when the constant is not otherwise available because
8704 // it replaces two constant pool loads with one. We only do this if the FP
8705 // type is known to be legal, because if it isn't, then we are before legalize
8706 // types an we want the other legalization to happen first (e.g. to avoid
8707 // messing with soft float) and if the ConstantFP is not legal, because if
8708 // it is legal, we may not need to store the FP constant in a constant pool.
8709 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
8710 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
8711 if (TLI.isTypeLegal(N2.getValueType()) &&
8712 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
8713 TargetLowering::Legal) &&
8714 // If both constants have multiple uses, then we won't need to do an
8715 // extra load, they are likely around in registers for other users.
8716 (TV->hasOneUse() || FV->hasOneUse())) {
8717 Constant *Elts[] = {
8718 const_cast<ConstantFP*>(FV->getConstantFPValue()),
8719 const_cast<ConstantFP*>(TV->getConstantFPValue())
8721 Type *FPTy = Elts[0]->getType();
8722 const TargetData &TD = *TLI.getTargetData();
8724 // Create a ConstantArray of the two constants.
8725 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
8726 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
8727 TD.getPrefTypeAlignment(FPTy));
8728 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8730 // Get the offsets to the 0 and 1 element of the array so that we can
8731 // select between them.
8732 SDValue Zero = DAG.getIntPtrConstant(0);
8733 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
8734 SDValue One = DAG.getIntPtrConstant(EltSize);
8736 SDValue Cond = DAG.getSetCC(DL,
8737 TLI.getSetCCResultType(N0.getValueType()),
8739 AddToWorkList(Cond.getNode());
8740 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
8742 AddToWorkList(CstOffset.getNode());
8743 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
8745 AddToWorkList(CPIdx.getNode());
8746 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
8747 MachinePointerInfo::getConstantPool(), false,
8748 false, false, Alignment);
8753 // Check to see if we can perform the "gzip trick", transforming
8754 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
8755 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
8756 (N1C->isNullValue() || // (a < 0) ? b : 0
8757 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
8758 EVT XType = N0.getValueType();
8759 EVT AType = N2.getValueType();
8760 if (XType.bitsGE(AType)) {
8761 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
8762 // single-bit constant.
8763 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
8764 unsigned ShCtV = N2C->getAPIntValue().logBase2();
8765 ShCtV = XType.getSizeInBits()-ShCtV-1;
8766 SDValue ShCt = DAG.getConstant(ShCtV,
8767 getShiftAmountTy(N0.getValueType()));
8768 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
8770 AddToWorkList(Shift.getNode());
8772 if (XType.bitsGT(AType)) {
8773 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
8774 AddToWorkList(Shift.getNode());
8777 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
8780 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
8782 DAG.getConstant(XType.getSizeInBits()-1,
8783 getShiftAmountTy(N0.getValueType())));
8784 AddToWorkList(Shift.getNode());
8786 if (XType.bitsGT(AType)) {
8787 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
8788 AddToWorkList(Shift.getNode());
8791 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
8795 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
8796 // where y is has a single bit set.
8797 // A plaintext description would be, we can turn the SELECT_CC into an AND
8798 // when the condition can be materialized as an all-ones register. Any
8799 // single bit-test can be materialized as an all-ones register with
8800 // shift-left and shift-right-arith.
8801 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
8802 N0->getValueType(0) == VT &&
8803 N1C && N1C->isNullValue() &&
8804 N2C && N2C->isNullValue()) {
8805 SDValue AndLHS = N0->getOperand(0);
8806 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
8807 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
8808 // Shift the tested bit over the sign bit.
8809 APInt AndMask = ConstAndRHS->getAPIntValue();
8811 DAG.getConstant(AndMask.countLeadingZeros(),
8812 getShiftAmountTy(AndLHS.getValueType()));
8813 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
8815 // Now arithmetic right shift it all the way over, so the result is either
8816 // all-ones, or zero.
8818 DAG.getConstant(AndMask.getBitWidth()-1,
8819 getShiftAmountTy(Shl.getValueType()));
8820 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
8822 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
8826 // fold select C, 16, 0 -> shl C, 4
8827 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
8828 TLI.getBooleanContents(N0.getValueType().isVector()) ==
8829 TargetLowering::ZeroOrOneBooleanContent) {
8831 // If the caller doesn't want us to simplify this into a zext of a compare,
8833 if (NotExtCompare && N2C->getAPIntValue() == 1)
8836 // Get a SetCC of the condition
8837 // FIXME: Should probably make sure that setcc is legal if we ever have a
8838 // target where it isn't.
8840 // cast from setcc result type to select result type
8842 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
8844 if (N2.getValueType().bitsLT(SCC.getValueType()))
8845 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
8847 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
8848 N2.getValueType(), SCC);
8850 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
8851 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
8852 N2.getValueType(), SCC);
8855 AddToWorkList(SCC.getNode());
8856 AddToWorkList(Temp.getNode());
8858 if (N2C->getAPIntValue() == 1)
8861 // shl setcc result by log2 n2c
8862 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
8863 DAG.getConstant(N2C->getAPIntValue().logBase2(),
8864 getShiftAmountTy(Temp.getValueType())));
8867 // Check to see if this is the equivalent of setcc
8868 // FIXME: Turn all of these into setcc if setcc if setcc is legal
8869 // otherwise, go ahead with the folds.
8870 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
8871 EVT XType = N0.getValueType();
8872 if (!LegalOperations ||
8873 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
8874 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
8875 if (Res.getValueType() != VT)
8876 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
8880 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
8881 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
8882 (!LegalOperations ||
8883 TLI.isOperationLegal(ISD::CTLZ, XType))) {
8884 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
8885 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
8886 DAG.getConstant(Log2_32(XType.getSizeInBits()),
8887 getShiftAmountTy(Ctlz.getValueType())));
8889 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
8890 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
8891 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
8892 XType, DAG.getConstant(0, XType), N0);
8893 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
8894 return DAG.getNode(ISD::SRL, DL, XType,
8895 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
8896 DAG.getConstant(XType.getSizeInBits()-1,
8897 getShiftAmountTy(XType)));
8899 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
8900 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
8901 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
8902 DAG.getConstant(XType.getSizeInBits()-1,
8903 getShiftAmountTy(N0.getValueType())));
8904 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
8908 // Check to see if this is an integer abs.
8909 // select_cc setg[te] X, 0, X, -X ->
8910 // select_cc setgt X, -1, X, -X ->
8911 // select_cc setl[te] X, 0, -X, X ->
8912 // select_cc setlt X, 1, -X, X ->
8913 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
8915 ConstantSDNode *SubC = NULL;
8916 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
8917 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
8918 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
8919 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
8920 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
8921 (N1C->isOne() && CC == ISD::SETLT)) &&
8922 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
8923 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
8925 EVT XType = N0.getValueType();
8926 if (SubC && SubC->isNullValue() && XType.isInteger()) {
8927 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
8929 DAG.getConstant(XType.getSizeInBits()-1,
8930 getShiftAmountTy(N0.getValueType())));
8931 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
8933 AddToWorkList(Shift.getNode());
8934 AddToWorkList(Add.getNode());
8935 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
8942 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
8943 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
8944 SDValue N1, ISD::CondCode Cond,
8945 DebugLoc DL, bool foldBooleans) {
8946 TargetLowering::DAGCombinerInfo
8947 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
8948 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
8951 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
8952 /// return a DAG expression to select that will generate the same value by
8953 /// multiplying by a magic number. See:
8954 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
8955 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
8956 std::vector<SDNode*> Built;
8957 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built);
8959 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
8965 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
8966 /// return a DAG expression to select that will generate the same value by
8967 /// multiplying by a magic number. See:
8968 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
8969 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
8970 std::vector<SDNode*> Built;
8971 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built);
8973 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
8979 /// FindBaseOffset - Return true if base is a frame index, which is known not
8980 // to alias with anything but itself. Provides base object and offset as
8982 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
8983 const GlobalValue *&GV, const void *&CV) {
8984 // Assume it is a primitive operation.
8985 Base = Ptr; Offset = 0; GV = 0; CV = 0;
8987 // If it's an adding a simple constant then integrate the offset.
8988 if (Base.getOpcode() == ISD::ADD) {
8989 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
8990 Base = Base.getOperand(0);
8991 Offset += C->getZExtValue();
8995 // Return the underlying GlobalValue, and update the Offset. Return false
8996 // for GlobalAddressSDNode since the same GlobalAddress may be represented
8997 // by multiple nodes with different offsets.
8998 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
8999 GV = G->getGlobal();
9000 Offset += G->getOffset();
9004 // Return the underlying Constant value, and update the Offset. Return false
9005 // for ConstantSDNodes since the same constant pool entry may be represented
9006 // by multiple nodes with different offsets.
9007 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
9008 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
9009 : (const void *)C->getConstVal();
9010 Offset += C->getOffset();
9013 // If it's any of the following then it can't alias with anything but itself.
9014 return isa<FrameIndexSDNode>(Base);
9017 /// isAlias - Return true if there is any possibility that the two addresses
9019 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
9020 const Value *SrcValue1, int SrcValueOffset1,
9021 unsigned SrcValueAlign1,
9022 const MDNode *TBAAInfo1,
9023 SDValue Ptr2, int64_t Size2,
9024 const Value *SrcValue2, int SrcValueOffset2,
9025 unsigned SrcValueAlign2,
9026 const MDNode *TBAAInfo2) const {
9027 // If they are the same then they must be aliases.
9028 if (Ptr1 == Ptr2) return true;
9030 // Gather base node and offset information.
9031 SDValue Base1, Base2;
9032 int64_t Offset1, Offset2;
9033 const GlobalValue *GV1, *GV2;
9034 const void *CV1, *CV2;
9035 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
9036 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
9038 // If they have a same base address then check to see if they overlap.
9039 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
9040 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
9042 // It is possible for different frame indices to alias each other, mostly
9043 // when tail call optimization reuses return address slots for arguments.
9044 // To catch this case, look up the actual index of frame indices to compute
9045 // the real alias relationship.
9046 if (isFrameIndex1 && isFrameIndex2) {
9047 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9048 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
9049 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
9050 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
9053 // Otherwise, if we know what the bases are, and they aren't identical, then
9054 // we know they cannot alias.
9055 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
9058 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
9059 // compared to the size and offset of the access, we may be able to prove they
9060 // do not alias. This check is conservative for now to catch cases created by
9061 // splitting vector types.
9062 if ((SrcValueAlign1 == SrcValueAlign2) &&
9063 (SrcValueOffset1 != SrcValueOffset2) &&
9064 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
9065 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
9066 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
9068 // There is no overlap between these relatively aligned accesses of similar
9069 // size, return no alias.
9070 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
9074 if (CombinerGlobalAA) {
9075 // Use alias analysis information.
9076 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
9077 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
9078 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
9079 AliasAnalysis::AliasResult AAResult =
9080 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
9081 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
9082 if (AAResult == AliasAnalysis::NoAlias)
9086 // Otherwise we have to assume they alias.
9090 /// FindAliasInfo - Extracts the relevant alias information from the memory
9091 /// node. Returns true if the operand was a load.
9092 bool DAGCombiner::FindAliasInfo(SDNode *N,
9093 SDValue &Ptr, int64_t &Size,
9094 const Value *&SrcValue,
9095 int &SrcValueOffset,
9096 unsigned &SrcValueAlign,
9097 const MDNode *&TBAAInfo) const {
9098 LSBaseSDNode *LS = cast<LSBaseSDNode>(N);
9100 Ptr = LS->getBasePtr();
9101 Size = LS->getMemoryVT().getSizeInBits() >> 3;
9102 SrcValue = LS->getSrcValue();
9103 SrcValueOffset = LS->getSrcValueOffset();
9104 SrcValueAlign = LS->getOriginalAlignment();
9105 TBAAInfo = LS->getTBAAInfo();
9106 return isa<LoadSDNode>(LS);
9109 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
9110 /// looking for aliasing nodes and adding them to the Aliases vector.
9111 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
9112 SmallVector<SDValue, 8> &Aliases) {
9113 SmallVector<SDValue, 8> Chains; // List of chains to visit.
9114 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
9116 // Get alias information for node.
9119 const Value *SrcValue;
9121 unsigned SrcValueAlign;
9122 const MDNode *SrcTBAAInfo;
9123 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
9124 SrcValueAlign, SrcTBAAInfo);
9127 Chains.push_back(OriginalChain);
9130 // Look at each chain and determine if it is an alias. If so, add it to the
9131 // aliases list. If not, then continue up the chain looking for the next
9133 while (!Chains.empty()) {
9134 SDValue Chain = Chains.back();
9137 // For TokenFactor nodes, look at each operand and only continue up the
9138 // chain until we find two aliases. If we've seen two aliases, assume we'll
9139 // find more and revert to original chain since the xform is unlikely to be
9142 // FIXME: The depth check could be made to return the last non-aliasing
9143 // chain we found before we hit a tokenfactor rather than the original
9145 if (Depth > 6 || Aliases.size() == 2) {
9147 Aliases.push_back(OriginalChain);
9151 // Don't bother if we've been before.
9152 if (!Visited.insert(Chain.getNode()))
9155 switch (Chain.getOpcode()) {
9156 case ISD::EntryToken:
9157 // Entry token is ideal chain operand, but handled in FindBetterChain.
9162 // Get alias information for Chain.
9165 const Value *OpSrcValue;
9166 int OpSrcValueOffset;
9167 unsigned OpSrcValueAlign;
9168 const MDNode *OpSrcTBAAInfo;
9169 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
9170 OpSrcValue, OpSrcValueOffset,
9174 // If chain is alias then stop here.
9175 if (!(IsLoad && IsOpLoad) &&
9176 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
9178 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
9179 OpSrcValueAlign, OpSrcTBAAInfo)) {
9180 Aliases.push_back(Chain);
9182 // Look further up the chain.
9183 Chains.push_back(Chain.getOperand(0));
9189 case ISD::TokenFactor:
9190 // We have to check each of the operands of the token factor for "small"
9191 // token factors, so we queue them up. Adding the operands to the queue
9192 // (stack) in reverse order maintains the original order and increases the
9193 // likelihood that getNode will find a matching token factor (CSE.)
9194 if (Chain.getNumOperands() > 16) {
9195 Aliases.push_back(Chain);
9198 for (unsigned n = Chain.getNumOperands(); n;)
9199 Chains.push_back(Chain.getOperand(--n));
9204 // For all other instructions we will just have to take what we can get.
9205 Aliases.push_back(Chain);
9211 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
9212 /// for a better chain (aliasing node.)
9213 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
9214 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
9216 // Accumulate all the aliases to this node.
9217 GatherAllAliases(N, OldChain, Aliases);
9219 // If no operands then chain to entry token.
9220 if (Aliases.size() == 0)
9221 return DAG.getEntryNode();
9223 // If a single operand then chain to it. We don't need to revisit it.
9224 if (Aliases.size() == 1)
9227 // Construct a custom tailored token factor.
9228 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
9229 &Aliases[0], Aliases.size());
9232 // SelectionDAG::Combine - This is the entry point for the file.
9234 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
9235 CodeGenOpt::Level OptLevel) {
9236 /// run - This is the main entry point to this class.
9238 DAGCombiner(*this, AA, OptLevel).Run(Level);