1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/SetVector.h"
21 #include "llvm/ADT/SmallBitVector.h"
22 #include "llvm/ADT/SmallPtrSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Analysis/AliasAnalysis.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetLowering.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
43 #define DEBUG_TYPE "dagcombine"
45 STATISTIC(NodesCombined , "Number of dag nodes combined");
46 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
47 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
48 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
49 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
50 STATISTIC(SlicedLoads, "Number of load sliced");
54 CombinerAA("combiner-alias-analysis", cl::Hidden,
55 cl::desc("Enable DAG combiner alias-analysis heuristics"));
58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
59 cl::desc("Enable DAG combiner's use of IR alias analysis"));
62 UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
63 cl::desc("Enable DAG combiner's use of TBAA"));
66 static cl::opt<std::string>
67 CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
68 cl::desc("Only use DAG-combiner alias analysis in this"
72 /// Hidden option to stress test load slicing, i.e., when this option
73 /// is enabled, load slicing bypasses most of its profitability guards.
75 StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
76 cl::desc("Bypass the profitability model of load "
81 MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
82 cl::desc("DAG combiner may split indexing from loads"));
84 //------------------------------ DAGCombiner ---------------------------------//
88 const TargetLowering &TLI;
90 CodeGenOpt::Level OptLevel;
95 /// \brief Worklist of all of the nodes that need to be simplified.
97 /// This must behave as a stack -- new nodes to process are pushed onto the
98 /// back and when processing we pop off of the back.
100 /// The worklist will not contain duplicates but may contain null entries
101 /// due to nodes being deleted from the underlying DAG.
102 SmallVector<SDNode *, 64> Worklist;
104 /// \brief Mapping from an SDNode to its position on the worklist.
106 /// This is used to find and remove nodes from the worklist (by nulling
107 /// them) when they are deleted from the underlying DAG. It relies on
108 /// stable indices of nodes within the worklist.
109 DenseMap<SDNode *, unsigned> WorklistMap;
111 /// \brief Set of nodes which have been combined (at least once).
113 /// This is used to allow us to reliably add any operands of a DAG node
114 /// which have not yet been combined to the worklist.
115 SmallPtrSet<SDNode *, 64> CombinedNodes;
117 // AA - Used for DAG load/store alias analysis.
120 /// When an instruction is simplified, add all users of the instruction to
121 /// the work lists because they might get more simplified now.
122 void AddUsersToWorklist(SDNode *N) {
123 for (SDNode *Node : N->uses())
127 /// Call the node-specific routine that folds each particular type of node.
128 SDValue visit(SDNode *N);
131 /// Add to the worklist making sure its instance is at the back (next to be
133 void AddToWorklist(SDNode *N) {
134 // Skip handle nodes as they can't usefully be combined and confuse the
135 // zero-use deletion strategy.
136 if (N->getOpcode() == ISD::HANDLENODE)
139 if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)
140 Worklist.push_back(N);
143 /// Remove all instances of N from the worklist.
144 void removeFromWorklist(SDNode *N) {
145 CombinedNodes.erase(N);
147 auto It = WorklistMap.find(N);
148 if (It == WorklistMap.end())
149 return; // Not in the worklist.
151 // Null out the entry rather than erasing it to avoid a linear operation.
152 Worklist[It->second] = nullptr;
153 WorklistMap.erase(It);
156 void deleteAndRecombine(SDNode *N);
157 bool recursivelyDeleteUnusedNodes(SDNode *N);
159 /// Replaces all uses of the results of one DAG node with new values.
160 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
163 /// Replaces all uses of the results of one DAG node with new values.
164 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
165 return CombineTo(N, &Res, 1, AddTo);
168 /// Replaces all uses of the results of one DAG node with new values.
169 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
171 SDValue To[] = { Res0, Res1 };
172 return CombineTo(N, To, 2, AddTo);
175 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
179 /// Check the specified integer node value to see if it can be simplified or
180 /// if things it uses can be simplified by bit propagation.
181 /// If so, return true.
182 bool SimplifyDemandedBits(SDValue Op) {
183 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
184 APInt Demanded = APInt::getAllOnesValue(BitWidth);
185 return SimplifyDemandedBits(Op, Demanded);
188 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
190 bool CombineToPreIndexedLoadStore(SDNode *N);
191 bool CombineToPostIndexedLoadStore(SDNode *N);
192 SDValue SplitIndexingFromLoad(LoadSDNode *LD);
193 bool SliceUpLoad(SDNode *N);
195 /// \brief Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
198 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
199 /// \param InVecVT type of the input vector to EVE with bitcasts resolved.
200 /// \param EltNo index of the vector element to load.
201 /// \param OriginalLoad load that EVE came from to be replaced.
202 /// \returns EVE on success SDValue() on failure.
203 SDValue ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
204 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad);
205 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
206 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
207 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
208 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
209 SDValue PromoteIntBinOp(SDValue Op);
210 SDValue PromoteIntShiftOp(SDValue Op);
211 SDValue PromoteExtend(SDValue Op);
212 bool PromoteLoad(SDValue Op);
214 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
215 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
216 ISD::NodeType ExtType);
218 /// Call the node-specific routine that knows how to fold each
219 /// particular type of node. If that doesn't do anything, try the
220 /// target-specific DAG combines.
221 SDValue combine(SDNode *N);
223 // Visitation implementation - Implement dag node combining for different
224 // node types. The semantics are as follows:
226 // SDValue.getNode() == 0 - No change was made
227 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
228 // otherwise - N should be replaced by the returned Operand.
230 SDValue visitTokenFactor(SDNode *N);
231 SDValue visitMERGE_VALUES(SDNode *N);
232 SDValue visitADD(SDNode *N);
233 SDValue visitSUB(SDNode *N);
234 SDValue visitADDC(SDNode *N);
235 SDValue visitSUBC(SDNode *N);
236 SDValue visitADDE(SDNode *N);
237 SDValue visitSUBE(SDNode *N);
238 SDValue visitMUL(SDNode *N);
239 SDValue useDivRem(SDNode *N);
240 SDValue visitSDIV(SDNode *N);
241 SDValue visitUDIV(SDNode *N);
242 SDValue visitREM(SDNode *N);
243 SDValue visitMULHU(SDNode *N);
244 SDValue visitMULHS(SDNode *N);
245 SDValue visitSMUL_LOHI(SDNode *N);
246 SDValue visitUMUL_LOHI(SDNode *N);
247 SDValue visitSMULO(SDNode *N);
248 SDValue visitUMULO(SDNode *N);
249 SDValue visitIMINMAX(SDNode *N);
250 SDValue visitAND(SDNode *N);
251 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *LocReference);
252 SDValue visitOR(SDNode *N);
253 SDValue visitORLike(SDValue N0, SDValue N1, SDNode *LocReference);
254 SDValue visitXOR(SDNode *N);
255 SDValue SimplifyVBinOp(SDNode *N);
256 SDValue visitSHL(SDNode *N);
257 SDValue visitSRA(SDNode *N);
258 SDValue visitSRL(SDNode *N);
259 SDValue visitRotate(SDNode *N);
260 SDValue visitBSWAP(SDNode *N);
261 SDValue visitCTLZ(SDNode *N);
262 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
263 SDValue visitCTTZ(SDNode *N);
264 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
265 SDValue visitCTPOP(SDNode *N);
266 SDValue visitSELECT(SDNode *N);
267 SDValue visitVSELECT(SDNode *N);
268 SDValue visitSELECT_CC(SDNode *N);
269 SDValue visitSETCC(SDNode *N);
270 SDValue visitSETCCE(SDNode *N);
271 SDValue visitSIGN_EXTEND(SDNode *N);
272 SDValue visitZERO_EXTEND(SDNode *N);
273 SDValue visitANY_EXTEND(SDNode *N);
274 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
275 SDValue visitSIGN_EXTEND_VECTOR_INREG(SDNode *N);
276 SDValue visitTRUNCATE(SDNode *N);
277 SDValue visitBITCAST(SDNode *N);
278 SDValue visitBUILD_PAIR(SDNode *N);
279 SDValue visitFADD(SDNode *N);
280 SDValue visitFSUB(SDNode *N);
281 SDValue visitFMUL(SDNode *N);
282 SDValue visitFMA(SDNode *N);
283 SDValue visitFDIV(SDNode *N);
284 SDValue visitFREM(SDNode *N);
285 SDValue visitFSQRT(SDNode *N);
286 SDValue visitFCOPYSIGN(SDNode *N);
287 SDValue visitSINT_TO_FP(SDNode *N);
288 SDValue visitUINT_TO_FP(SDNode *N);
289 SDValue visitFP_TO_SINT(SDNode *N);
290 SDValue visitFP_TO_UINT(SDNode *N);
291 SDValue visitFP_ROUND(SDNode *N);
292 SDValue visitFP_ROUND_INREG(SDNode *N);
293 SDValue visitFP_EXTEND(SDNode *N);
294 SDValue visitFNEG(SDNode *N);
295 SDValue visitFABS(SDNode *N);
296 SDValue visitFCEIL(SDNode *N);
297 SDValue visitFTRUNC(SDNode *N);
298 SDValue visitFFLOOR(SDNode *N);
299 SDValue visitFMINNUM(SDNode *N);
300 SDValue visitFMAXNUM(SDNode *N);
301 SDValue visitBRCOND(SDNode *N);
302 SDValue visitBR_CC(SDNode *N);
303 SDValue visitLOAD(SDNode *N);
305 SDValue replaceStoreChain(StoreSDNode *ST, SDValue BetterChain);
306 SDValue replaceStoreOfFPConstant(StoreSDNode *ST);
308 SDValue visitSTORE(SDNode *N);
309 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
310 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
311 SDValue visitBUILD_VECTOR(SDNode *N);
312 SDValue visitCONCAT_VECTORS(SDNode *N);
313 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
314 SDValue visitVECTOR_SHUFFLE(SDNode *N);
315 SDValue visitSCALAR_TO_VECTOR(SDNode *N);
316 SDValue visitINSERT_SUBVECTOR(SDNode *N);
317 SDValue visitMLOAD(SDNode *N);
318 SDValue visitMSTORE(SDNode *N);
319 SDValue visitMGATHER(SDNode *N);
320 SDValue visitMSCATTER(SDNode *N);
321 SDValue visitFP_TO_FP16(SDNode *N);
322 SDValue visitFP16_TO_FP(SDNode *N);
324 SDValue visitFADDForFMACombine(SDNode *N);
325 SDValue visitFSUBForFMACombine(SDNode *N);
326 SDValue visitFMULForFMACombine(SDNode *N);
328 SDValue XformToShuffleWithZero(SDNode *N);
329 SDValue ReassociateOps(unsigned Opc, SDLoc DL, SDValue LHS, SDValue RHS);
331 SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
333 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
334 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
335 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
336 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
337 SDValue N3, ISD::CondCode CC,
338 bool NotExtCompare = false);
339 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
340 SDLoc DL, bool foldBooleans = true);
342 bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
344 bool isOneUseSetCC(SDValue N) const;
346 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
348 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
349 SDValue CombineExtLoad(SDNode *N);
350 SDValue combineRepeatedFPDivisors(SDNode *N);
351 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
352 SDValue BuildSDIV(SDNode *N);
353 SDValue BuildSDIVPow2(SDNode *N);
354 SDValue BuildUDIV(SDNode *N);
355 SDValue BuildReciprocalEstimate(SDValue Op, SDNodeFlags *Flags);
356 SDValue BuildRsqrtEstimate(SDValue Op, SDNodeFlags *Flags);
357 SDValue BuildRsqrtNROneConst(SDValue Op, SDValue Est, unsigned Iterations,
359 SDValue BuildRsqrtNRTwoConst(SDValue Op, SDValue Est, unsigned Iterations,
361 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
362 bool DemandHighBits = true);
363 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
364 SDNode *MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
365 SDValue InnerPos, SDValue InnerNeg,
366 unsigned PosOpcode, unsigned NegOpcode,
368 SDNode *MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL);
369 SDValue ReduceLoadWidth(SDNode *N);
370 SDValue ReduceLoadOpStoreWidth(SDNode *N);
371 SDValue TransformFPLoadStorePair(SDNode *N);
372 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
373 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N);
375 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
377 /// Walk up chain skipping non-aliasing memory nodes,
378 /// looking for aliasing nodes and adding them to the Aliases vector.
379 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
380 SmallVectorImpl<SDValue> &Aliases);
382 /// Return true if there is any possibility that the two addresses overlap.
383 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const;
385 /// Walk up chain skipping non-aliasing memory nodes, looking for a better
386 /// chain (aliasing node.)
387 SDValue FindBetterChain(SDNode *N, SDValue Chain);
389 /// Do FindBetterChain for a store and any possibly adjacent stores on
390 /// consecutive chains.
391 bool findBetterNeighborChains(StoreSDNode *St);
393 /// Holds a pointer to an LSBaseSDNode as well as information on where it
394 /// is located in a sequence of memory operations connected by a chain.
396 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq):
397 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { }
398 // Ptr to the mem node.
399 LSBaseSDNode *MemNode;
400 // Offset from the base ptr.
401 int64_t OffsetFromBase;
402 // What is the sequence number of this mem node.
403 // Lowest mem operand in the DAG starts at zero.
404 unsigned SequenceNum;
407 /// This is a helper function for visitMUL to check the profitability
408 /// of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).
409 /// MulNode is the original multiply, AddNode is (add x, c1),
410 /// and ConstNode is c2.
411 bool isMulAddWithConstProfitable(SDNode *MulNode,
415 /// This is a helper function for MergeStoresOfConstantsOrVecElts. Returns a
416 /// constant build_vector of the stored constant values in Stores.
417 SDValue getMergedConstantVectorStore(SelectionDAG &DAG,
419 ArrayRef<MemOpLink> Stores,
420 SmallVectorImpl<SDValue> &Chains,
423 /// This is a helper function for visitAND and visitZERO_EXTEND. Returns
424 /// true if the (and (load x) c) pattern matches an extload. ExtVT returns
425 /// the type of the loaded value to be extended. LoadedVT returns the type
426 /// of the original loaded value. NarrowLoad returns whether the load would
427 /// need to be narrowed in order to match.
428 bool isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
429 EVT LoadResultTy, EVT &ExtVT, EVT &LoadedVT,
432 /// This is a helper function for MergeConsecutiveStores. When the source
433 /// elements of the consecutive stores are all constants or all extracted
434 /// vector elements, try to merge them into one larger store.
435 /// \return True if a merged store was created.
436 bool MergeStoresOfConstantsOrVecElts(SmallVectorImpl<MemOpLink> &StoreNodes,
437 EVT MemVT, unsigned NumStores,
438 bool IsConstantSrc, bool UseVector);
440 /// This is a helper function for MergeConsecutiveStores.
441 /// Stores that may be merged are placed in StoreNodes.
442 /// Loads that may alias with those stores are placed in AliasLoadNodes.
443 void getStoreMergeAndAliasCandidates(
444 StoreSDNode* St, SmallVectorImpl<MemOpLink> &StoreNodes,
445 SmallVectorImpl<LSBaseSDNode*> &AliasLoadNodes);
447 /// Merge consecutive store operations into a wide store.
448 /// This optimization uses wide integers or vectors when possible.
449 /// \return True if some memory operations were changed.
450 bool MergeConsecutiveStores(StoreSDNode *N);
452 /// \brief Try to transform a truncation where C is a constant:
453 /// (trunc (and X, C)) -> (and (trunc X), (trunc C))
455 /// \p N needs to be a truncation and its first operand an AND. Other
456 /// requirements are checked by the function (e.g. that trunc is
457 /// single-use) and if missed an empty SDValue is returned.
458 SDValue distributeTruncateThroughAnd(SDNode *N);
461 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
462 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
463 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {
464 ForCodeSize = DAG.getMachineFunction().getFunction()->optForSize();
467 /// Runs the dag combiner on all nodes in the work list
468 void Run(CombineLevel AtLevel);
470 SelectionDAG &getDAG() const { return DAG; }
472 /// Returns a type large enough to hold any valid shift amount - before type
473 /// legalization these can be huge.
474 EVT getShiftAmountTy(EVT LHSTy) {
475 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
476 if (LHSTy.isVector())
478 auto &DL = DAG.getDataLayout();
479 return LegalTypes ? TLI.getScalarShiftAmountTy(DL, LHSTy)
480 : TLI.getPointerTy(DL);
483 /// This method returns true if we are running before type legalization or
484 /// if the specified VT is legal.
485 bool isTypeLegal(const EVT &VT) {
486 if (!LegalTypes) return true;
487 return TLI.isTypeLegal(VT);
490 /// Convenience wrapper around TargetLowering::getSetCCResultType
491 EVT getSetCCResultType(EVT VT) const {
492 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
499 /// This class is a DAGUpdateListener that removes any deleted
500 /// nodes from the worklist.
501 class WorklistRemover : public SelectionDAG::DAGUpdateListener {
504 explicit WorklistRemover(DAGCombiner &dc)
505 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
507 void NodeDeleted(SDNode *N, SDNode *E) override {
508 DC.removeFromWorklist(N);
513 //===----------------------------------------------------------------------===//
514 // TargetLowering::DAGCombinerInfo implementation
515 //===----------------------------------------------------------------------===//
517 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
518 ((DAGCombiner*)DC)->AddToWorklist(N);
521 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
522 ((DAGCombiner*)DC)->removeFromWorklist(N);
525 SDValue TargetLowering::DAGCombinerInfo::
526 CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo) {
527 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
530 SDValue TargetLowering::DAGCombinerInfo::
531 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
532 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
536 SDValue TargetLowering::DAGCombinerInfo::
537 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
538 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
541 void TargetLowering::DAGCombinerInfo::
542 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
543 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
546 //===----------------------------------------------------------------------===//
548 //===----------------------------------------------------------------------===//
550 void DAGCombiner::deleteAndRecombine(SDNode *N) {
551 removeFromWorklist(N);
553 // If the operands of this node are only used by the node, they will now be
554 // dead. Make sure to re-visit them and recursively delete dead nodes.
555 for (const SDValue &Op : N->ops())
556 // For an operand generating multiple values, one of the values may
557 // become dead allowing further simplification (e.g. split index
558 // arithmetic from an indexed load).
559 if (Op->hasOneUse() || Op->getNumValues() > 1)
560 AddToWorklist(Op.getNode());
565 /// Return 1 if we can compute the negated form of the specified expression for
566 /// the same cost as the expression itself, or 2 if we can compute the negated
567 /// form more cheaply than the expression itself.
568 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
569 const TargetLowering &TLI,
570 const TargetOptions *Options,
571 unsigned Depth = 0) {
572 // fneg is removable even if it has multiple uses.
573 if (Op.getOpcode() == ISD::FNEG) return 2;
575 // Don't allow anything with multiple uses.
576 if (!Op.hasOneUse()) return 0;
578 // Don't recurse exponentially.
579 if (Depth > 6) return 0;
581 switch (Op.getOpcode()) {
582 default: return false;
583 case ISD::ConstantFP:
584 // Don't invert constant FP values after legalize. The negated constant
585 // isn't necessarily legal.
586 return LegalOperations ? 0 : 1;
588 // FIXME: determine better conditions for this xform.
589 if (!Options->UnsafeFPMath) return 0;
591 // After operation legalization, it might not be legal to create new FSUBs.
592 if (LegalOperations &&
593 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
596 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
597 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
600 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
601 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
604 // We can't turn -(A-B) into B-A when we honor signed zeros.
605 if (!Options->UnsafeFPMath) return 0;
607 // fold (fneg (fsub A, B)) -> (fsub B, A)
612 if (Options->HonorSignDependentRoundingFPMath()) return 0;
614 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
615 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
619 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
625 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
630 /// If isNegatibleForFree returns true, return the newly negated expression.
631 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
632 bool LegalOperations, unsigned Depth = 0) {
633 const TargetOptions &Options = DAG.getTarget().Options;
634 // fneg is removable even if it has multiple uses.
635 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
637 // Don't allow anything with multiple uses.
638 assert(Op.hasOneUse() && "Unknown reuse!");
640 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
642 const SDNodeFlags *Flags = Op.getNode()->getFlags();
644 switch (Op.getOpcode()) {
645 default: llvm_unreachable("Unknown code");
646 case ISD::ConstantFP: {
647 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
649 return DAG.getConstantFP(V, SDLoc(Op), Op.getValueType());
652 // FIXME: determine better conditions for this xform.
653 assert(Options.UnsafeFPMath);
655 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
656 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
657 DAG.getTargetLoweringInfo(), &Options, Depth+1))
658 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
659 GetNegatedExpression(Op.getOperand(0), DAG,
660 LegalOperations, Depth+1),
661 Op.getOperand(1), Flags);
662 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
663 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
664 GetNegatedExpression(Op.getOperand(1), DAG,
665 LegalOperations, Depth+1),
666 Op.getOperand(0), Flags);
668 // We can't turn -(A-B) into B-A when we honor signed zeros.
669 assert(Options.UnsafeFPMath);
671 // fold (fneg (fsub 0, B)) -> B
672 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
674 return Op.getOperand(1);
676 // fold (fneg (fsub A, B)) -> (fsub B, A)
677 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
678 Op.getOperand(1), Op.getOperand(0), Flags);
682 assert(!Options.HonorSignDependentRoundingFPMath());
684 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
685 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
686 DAG.getTargetLoweringInfo(), &Options, Depth+1))
687 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
688 GetNegatedExpression(Op.getOperand(0), DAG,
689 LegalOperations, Depth+1),
690 Op.getOperand(1), Flags);
692 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
693 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
695 GetNegatedExpression(Op.getOperand(1), DAG,
696 LegalOperations, Depth+1), Flags);
700 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
701 GetNegatedExpression(Op.getOperand(0), DAG,
702 LegalOperations, Depth+1));
704 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
705 GetNegatedExpression(Op.getOperand(0), DAG,
706 LegalOperations, Depth+1),
711 // Return true if this node is a setcc, or is a select_cc
712 // that selects between the target values used for true and false, making it
713 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
714 // the appropriate nodes based on the type of node we are checking. This
715 // simplifies life a bit for the callers.
716 bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
718 if (N.getOpcode() == ISD::SETCC) {
719 LHS = N.getOperand(0);
720 RHS = N.getOperand(1);
721 CC = N.getOperand(2);
725 if (N.getOpcode() != ISD::SELECT_CC ||
726 !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
727 !TLI.isConstFalseVal(N.getOperand(3).getNode()))
730 if (TLI.getBooleanContents(N.getValueType()) ==
731 TargetLowering::UndefinedBooleanContent)
734 LHS = N.getOperand(0);
735 RHS = N.getOperand(1);
736 CC = N.getOperand(4);
740 /// Return true if this is a SetCC-equivalent operation with only one use.
741 /// If this is true, it allows the users to invert the operation for free when
742 /// it is profitable to do so.
743 bool DAGCombiner::isOneUseSetCC(SDValue N) const {
745 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
750 /// Returns true if N is a BUILD_VECTOR node whose
751 /// elements are all the same constant or undefined.
752 static bool isConstantSplatVector(SDNode *N, APInt& SplatValue) {
753 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(N);
758 unsigned SplatBitSize;
760 EVT EltVT = N->getValueType(0).getVectorElementType();
761 return (C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
763 EltVT.getSizeInBits() >= SplatBitSize);
766 // \brief Returns the SDNode if it is a constant integer BuildVector
767 // or constant integer.
768 static SDNode *isConstantIntBuildVectorOrConstantInt(SDValue N) {
769 if (isa<ConstantSDNode>(N))
771 if (ISD::isBuildVectorOfConstantSDNodes(N.getNode()))
776 // \brief Returns the SDNode if it is a constant float BuildVector
777 // or constant float.
778 static SDNode *isConstantFPBuildVectorOrConstantFP(SDValue N) {
779 if (isa<ConstantFPSDNode>(N))
781 if (ISD::isBuildVectorOfConstantFPSDNodes(N.getNode()))
786 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
788 static ConstantSDNode *isConstOrConstSplat(SDValue N) {
789 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N))
792 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
793 BitVector UndefElements;
794 ConstantSDNode *CN = BV->getConstantSplatNode(&UndefElements);
796 // BuildVectors can truncate their operands. Ignore that case here.
797 // FIXME: We blindly ignore splats which include undef which is overly
799 if (CN && UndefElements.none() &&
800 CN->getValueType(0) == N.getValueType().getScalarType())
807 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
809 static ConstantFPSDNode *isConstOrConstSplatFP(SDValue N) {
810 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
813 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
814 BitVector UndefElements;
815 ConstantFPSDNode *CN = BV->getConstantFPSplatNode(&UndefElements);
817 if (CN && UndefElements.none())
824 SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDLoc DL,
825 SDValue N0, SDValue N1) {
826 EVT VT = N0.getValueType();
827 if (N0.getOpcode() == Opc) {
828 if (SDNode *L = isConstantIntBuildVectorOrConstantInt(N0.getOperand(1))) {
829 if (SDNode *R = isConstantIntBuildVectorOrConstantInt(N1)) {
830 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
831 if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, L, R))
832 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
835 if (N0.hasOneUse()) {
836 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one
838 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
839 if (!OpNode.getNode())
841 AddToWorklist(OpNode.getNode());
842 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
847 if (N1.getOpcode() == Opc) {
848 if (SDNode *R = isConstantIntBuildVectorOrConstantInt(N1.getOperand(1))) {
849 if (SDNode *L = isConstantIntBuildVectorOrConstantInt(N0)) {
850 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
851 if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, R, L))
852 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
855 if (N1.hasOneUse()) {
856 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one
858 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N1.getOperand(0), N0);
859 if (!OpNode.getNode())
861 AddToWorklist(OpNode.getNode());
862 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
870 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
872 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
874 DEBUG(dbgs() << "\nReplacing.1 ";
876 dbgs() << "\nWith: ";
877 To[0].getNode()->dump(&DAG);
878 dbgs() << " and " << NumTo-1 << " other values\n");
879 for (unsigned i = 0, e = NumTo; i != e; ++i)
880 assert((!To[i].getNode() ||
881 N->getValueType(i) == To[i].getValueType()) &&
882 "Cannot combine value to value of different type!");
884 WorklistRemover DeadNodes(*this);
885 DAG.ReplaceAllUsesWith(N, To);
887 // Push the new nodes and any users onto the worklist
888 for (unsigned i = 0, e = NumTo; i != e; ++i) {
889 if (To[i].getNode()) {
890 AddToWorklist(To[i].getNode());
891 AddUsersToWorklist(To[i].getNode());
896 // Finally, if the node is now dead, remove it from the graph. The node
897 // may not be dead if the replacement process recursively simplified to
898 // something else needing this node.
900 deleteAndRecombine(N);
901 return SDValue(N, 0);
905 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
906 // Replace all uses. If any nodes become isomorphic to other nodes and
907 // are deleted, make sure to remove them from our worklist.
908 WorklistRemover DeadNodes(*this);
909 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
911 // Push the new node and any (possibly new) users onto the worklist.
912 AddToWorklist(TLO.New.getNode());
913 AddUsersToWorklist(TLO.New.getNode());
915 // Finally, if the node is now dead, remove it from the graph. The node
916 // may not be dead if the replacement process recursively simplified to
917 // something else needing this node.
918 if (TLO.Old.getNode()->use_empty())
919 deleteAndRecombine(TLO.Old.getNode());
922 /// Check the specified integer node value to see if it can be simplified or if
923 /// things it uses can be simplified by bit propagation. If so, return true.
924 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
925 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
926 APInt KnownZero, KnownOne;
927 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
931 AddToWorklist(Op.getNode());
933 // Replace the old value with the new one.
935 DEBUG(dbgs() << "\nReplacing.2 ";
936 TLO.Old.getNode()->dump(&DAG);
937 dbgs() << "\nWith: ";
938 TLO.New.getNode()->dump(&DAG);
941 CommitTargetLoweringOpt(TLO);
945 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
947 EVT VT = Load->getValueType(0);
948 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
950 DEBUG(dbgs() << "\nReplacing.9 ";
952 dbgs() << "\nWith: ";
953 Trunc.getNode()->dump(&DAG);
955 WorklistRemover DeadNodes(*this);
956 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
957 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
958 deleteAndRecombine(Load);
959 AddToWorklist(Trunc.getNode());
962 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
965 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
966 EVT MemVT = LD->getMemoryVT();
967 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
968 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD
970 : LD->getExtensionType();
972 return DAG.getExtLoad(ExtType, dl, PVT,
973 LD->getChain(), LD->getBasePtr(),
974 MemVT, LD->getMemOperand());
977 unsigned Opc = Op.getOpcode();
980 case ISD::AssertSext:
981 return DAG.getNode(ISD::AssertSext, dl, PVT,
982 SExtPromoteOperand(Op.getOperand(0), PVT),
984 case ISD::AssertZext:
985 return DAG.getNode(ISD::AssertZext, dl, PVT,
986 ZExtPromoteOperand(Op.getOperand(0), PVT),
988 case ISD::Constant: {
990 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
991 return DAG.getNode(ExtOpc, dl, PVT, Op);
995 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
997 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
1000 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
1001 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
1003 EVT OldVT = Op.getValueType();
1005 bool Replace = false;
1006 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
1007 if (!NewOp.getNode())
1009 AddToWorklist(NewOp.getNode());
1012 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
1013 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
1014 DAG.getValueType(OldVT));
1017 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
1018 EVT OldVT = Op.getValueType();
1020 bool Replace = false;
1021 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
1022 if (!NewOp.getNode())
1024 AddToWorklist(NewOp.getNode());
1027 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
1028 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
1031 /// Promote the specified integer binary operation if the target indicates it is
1032 /// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1033 /// i32 since i16 instructions are longer.
1034 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
1035 if (!LegalOperations)
1038 EVT VT = Op.getValueType();
1039 if (VT.isVector() || !VT.isInteger())
1042 // If operation type is 'undesirable', e.g. i16 on x86, consider
1044 unsigned Opc = Op.getOpcode();
1045 if (TLI.isTypeDesirableForOp(Opc, VT))
1049 // Consult target whether it is a good idea to promote this operation and
1050 // what's the right type to promote it to.
1051 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1052 assert(PVT != VT && "Don't know what type to promote to!");
1054 bool Replace0 = false;
1055 SDValue N0 = Op.getOperand(0);
1056 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
1060 bool Replace1 = false;
1061 SDValue N1 = Op.getOperand(1);
1066 NN1 = PromoteOperand(N1, PVT, Replace1);
1071 AddToWorklist(NN0.getNode());
1073 AddToWorklist(NN1.getNode());
1076 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
1078 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
1080 DEBUG(dbgs() << "\nPromoting ";
1081 Op.getNode()->dump(&DAG));
1083 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1084 DAG.getNode(Opc, dl, PVT, NN0, NN1));
1089 /// Promote the specified integer shift operation if the target indicates it is
1090 /// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1091 /// i32 since i16 instructions are longer.
1092 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
1093 if (!LegalOperations)
1096 EVT VT = Op.getValueType();
1097 if (VT.isVector() || !VT.isInteger())
1100 // If operation type is 'undesirable', e.g. i16 on x86, consider
1102 unsigned Opc = Op.getOpcode();
1103 if (TLI.isTypeDesirableForOp(Opc, VT))
1107 // Consult target whether it is a good idea to promote this operation and
1108 // what's the right type to promote it to.
1109 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1110 assert(PVT != VT && "Don't know what type to promote to!");
1112 bool Replace = false;
1113 SDValue N0 = Op.getOperand(0);
1114 if (Opc == ISD::SRA)
1115 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
1116 else if (Opc == ISD::SRL)
1117 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
1119 N0 = PromoteOperand(N0, PVT, Replace);
1123 AddToWorklist(N0.getNode());
1125 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
1127 DEBUG(dbgs() << "\nPromoting ";
1128 Op.getNode()->dump(&DAG));
1130 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1131 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
1136 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
1137 if (!LegalOperations)
1140 EVT VT = Op.getValueType();
1141 if (VT.isVector() || !VT.isInteger())
1144 // If operation type is 'undesirable', e.g. i16 on x86, consider
1146 unsigned Opc = Op.getOpcode();
1147 if (TLI.isTypeDesirableForOp(Opc, VT))
1151 // Consult target whether it is a good idea to promote this operation and
1152 // what's the right type to promote it to.
1153 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1154 assert(PVT != VT && "Don't know what type to promote to!");
1155 // fold (aext (aext x)) -> (aext x)
1156 // fold (aext (zext x)) -> (zext x)
1157 // fold (aext (sext x)) -> (sext x)
1158 DEBUG(dbgs() << "\nPromoting ";
1159 Op.getNode()->dump(&DAG));
1160 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1165 bool DAGCombiner::PromoteLoad(SDValue Op) {
1166 if (!LegalOperations)
1169 EVT VT = Op.getValueType();
1170 if (VT.isVector() || !VT.isInteger())
1173 // If operation type is 'undesirable', e.g. i16 on x86, consider
1175 unsigned Opc = Op.getOpcode();
1176 if (TLI.isTypeDesirableForOp(Opc, VT))
1180 // Consult target whether it is a good idea to promote this operation and
1181 // what's the right type to promote it to.
1182 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1183 assert(PVT != VT && "Don't know what type to promote to!");
1186 SDNode *N = Op.getNode();
1187 LoadSDNode *LD = cast<LoadSDNode>(N);
1188 EVT MemVT = LD->getMemoryVT();
1189 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
1190 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD
1192 : LD->getExtensionType();
1193 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
1194 LD->getChain(), LD->getBasePtr(),
1195 MemVT, LD->getMemOperand());
1196 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
1198 DEBUG(dbgs() << "\nPromoting ";
1201 Result.getNode()->dump(&DAG);
1203 WorklistRemover DeadNodes(*this);
1204 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
1205 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1206 deleteAndRecombine(N);
1207 AddToWorklist(Result.getNode());
1213 /// \brief Recursively delete a node which has no uses and any operands for
1214 /// which it is the only use.
1216 /// Note that this both deletes the nodes and removes them from the worklist.
1217 /// It also adds any nodes who have had a user deleted to the worklist as they
1218 /// may now have only one use and subject to other combines.
1219 bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
1220 if (!N->use_empty())
1223 SmallSetVector<SDNode *, 16> Nodes;
1226 N = Nodes.pop_back_val();
1230 if (N->use_empty()) {
1231 for (const SDValue &ChildN : N->op_values())
1232 Nodes.insert(ChildN.getNode());
1234 removeFromWorklist(N);
1239 } while (!Nodes.empty());
1243 //===----------------------------------------------------------------------===//
1244 // Main DAG Combiner implementation
1245 //===----------------------------------------------------------------------===//
1247 void DAGCombiner::Run(CombineLevel AtLevel) {
1248 // set the instance variables, so that the various visit routines may use it.
1250 LegalOperations = Level >= AfterLegalizeVectorOps;
1251 LegalTypes = Level >= AfterLegalizeTypes;
1253 // Add all the dag nodes to the worklist.
1254 for (SDNode &Node : DAG.allnodes())
1255 AddToWorklist(&Node);
1257 // Create a dummy node (which is not added to allnodes), that adds a reference
1258 // to the root node, preventing it from being deleted, and tracking any
1259 // changes of the root.
1260 HandleSDNode Dummy(DAG.getRoot());
1262 // while the worklist isn't empty, find a node and
1263 // try and combine it.
1264 while (!WorklistMap.empty()) {
1266 // The Worklist holds the SDNodes in order, but it may contain null entries.
1268 N = Worklist.pop_back_val();
1271 bool GoodWorklistEntry = WorklistMap.erase(N);
1272 (void)GoodWorklistEntry;
1273 assert(GoodWorklistEntry &&
1274 "Found a worklist entry without a corresponding map entry!");
1276 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1277 // N is deleted from the DAG, since they too may now be dead or may have a
1278 // reduced number of uses, allowing other xforms.
1279 if (recursivelyDeleteUnusedNodes(N))
1282 WorklistRemover DeadNodes(*this);
1284 // If this combine is running after legalizing the DAG, re-legalize any
1285 // nodes pulled off the worklist.
1286 if (Level == AfterLegalizeDAG) {
1287 SmallSetVector<SDNode *, 16> UpdatedNodes;
1288 bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);
1290 for (SDNode *LN : UpdatedNodes) {
1292 AddUsersToWorklist(LN);
1298 DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG));
1300 // Add any operands of the new node which have not yet been combined to the
1301 // worklist as well. Because the worklist uniques things already, this
1302 // won't repeatedly process the same operand.
1303 CombinedNodes.insert(N);
1304 for (const SDValue &ChildN : N->op_values())
1305 if (!CombinedNodes.count(ChildN.getNode()))
1306 AddToWorklist(ChildN.getNode());
1308 SDValue RV = combine(N);
1315 // If we get back the same node we passed in, rather than a new node or
1316 // zero, we know that the node must have defined multiple values and
1317 // CombineTo was used. Since CombineTo takes care of the worklist
1318 // mechanics for us, we have no work to do in this case.
1319 if (RV.getNode() == N)
1322 assert(N->getOpcode() != ISD::DELETED_NODE &&
1323 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1324 "Node was deleted but visit returned new node!");
1326 DEBUG(dbgs() << " ... into: ";
1327 RV.getNode()->dump(&DAG));
1329 // Transfer debug value.
1330 DAG.TransferDbgValues(SDValue(N, 0), RV);
1331 if (N->getNumValues() == RV.getNode()->getNumValues())
1332 DAG.ReplaceAllUsesWith(N, RV.getNode());
1334 assert(N->getValueType(0) == RV.getValueType() &&
1335 N->getNumValues() == 1 && "Type mismatch");
1337 DAG.ReplaceAllUsesWith(N, &OpV);
1340 // Push the new node and any users onto the worklist
1341 AddToWorklist(RV.getNode());
1342 AddUsersToWorklist(RV.getNode());
1344 // Finally, if the node is now dead, remove it from the graph. The node
1345 // may not be dead if the replacement process recursively simplified to
1346 // something else needing this node. This will also take care of adding any
1347 // operands which have lost a user to the worklist.
1348 recursivelyDeleteUnusedNodes(N);
1351 // If the root changed (e.g. it was a dead load, update the root).
1352 DAG.setRoot(Dummy.getValue());
1353 DAG.RemoveDeadNodes();
1356 SDValue DAGCombiner::visit(SDNode *N) {
1357 switch (N->getOpcode()) {
1359 case ISD::TokenFactor: return visitTokenFactor(N);
1360 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1361 case ISD::ADD: return visitADD(N);
1362 case ISD::SUB: return visitSUB(N);
1363 case ISD::ADDC: return visitADDC(N);
1364 case ISD::SUBC: return visitSUBC(N);
1365 case ISD::ADDE: return visitADDE(N);
1366 case ISD::SUBE: return visitSUBE(N);
1367 case ISD::MUL: return visitMUL(N);
1368 case ISD::SDIV: return visitSDIV(N);
1369 case ISD::UDIV: return visitUDIV(N);
1371 case ISD::UREM: return visitREM(N);
1372 case ISD::MULHU: return visitMULHU(N);
1373 case ISD::MULHS: return visitMULHS(N);
1374 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1375 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1376 case ISD::SMULO: return visitSMULO(N);
1377 case ISD::UMULO: return visitUMULO(N);
1381 case ISD::UMAX: return visitIMINMAX(N);
1382 case ISD::AND: return visitAND(N);
1383 case ISD::OR: return visitOR(N);
1384 case ISD::XOR: return visitXOR(N);
1385 case ISD::SHL: return visitSHL(N);
1386 case ISD::SRA: return visitSRA(N);
1387 case ISD::SRL: return visitSRL(N);
1389 case ISD::ROTL: return visitRotate(N);
1390 case ISD::BSWAP: return visitBSWAP(N);
1391 case ISD::CTLZ: return visitCTLZ(N);
1392 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1393 case ISD::CTTZ: return visitCTTZ(N);
1394 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1395 case ISD::CTPOP: return visitCTPOP(N);
1396 case ISD::SELECT: return visitSELECT(N);
1397 case ISD::VSELECT: return visitVSELECT(N);
1398 case ISD::SELECT_CC: return visitSELECT_CC(N);
1399 case ISD::SETCC: return visitSETCC(N);
1400 case ISD::SETCCE: return visitSETCCE(N);
1401 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1402 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1403 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1404 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1405 case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N);
1406 case ISD::TRUNCATE: return visitTRUNCATE(N);
1407 case ISD::BITCAST: return visitBITCAST(N);
1408 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1409 case ISD::FADD: return visitFADD(N);
1410 case ISD::FSUB: return visitFSUB(N);
1411 case ISD::FMUL: return visitFMUL(N);
1412 case ISD::FMA: return visitFMA(N);
1413 case ISD::FDIV: return visitFDIV(N);
1414 case ISD::FREM: return visitFREM(N);
1415 case ISD::FSQRT: return visitFSQRT(N);
1416 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1417 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1418 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1419 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1420 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1421 case ISD::FP_ROUND: return visitFP_ROUND(N);
1422 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1423 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1424 case ISD::FNEG: return visitFNEG(N);
1425 case ISD::FABS: return visitFABS(N);
1426 case ISD::FFLOOR: return visitFFLOOR(N);
1427 case ISD::FMINNUM: return visitFMINNUM(N);
1428 case ISD::FMAXNUM: return visitFMAXNUM(N);
1429 case ISD::FCEIL: return visitFCEIL(N);
1430 case ISD::FTRUNC: return visitFTRUNC(N);
1431 case ISD::BRCOND: return visitBRCOND(N);
1432 case ISD::BR_CC: return visitBR_CC(N);
1433 case ISD::LOAD: return visitLOAD(N);
1434 case ISD::STORE: return visitSTORE(N);
1435 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1436 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1437 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1438 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1439 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1440 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1441 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N);
1442 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
1443 case ISD::MGATHER: return visitMGATHER(N);
1444 case ISD::MLOAD: return visitMLOAD(N);
1445 case ISD::MSCATTER: return visitMSCATTER(N);
1446 case ISD::MSTORE: return visitMSTORE(N);
1447 case ISD::FP_TO_FP16: return visitFP_TO_FP16(N);
1448 case ISD::FP16_TO_FP: return visitFP16_TO_FP(N);
1453 SDValue DAGCombiner::combine(SDNode *N) {
1454 SDValue RV = visit(N);
1456 // If nothing happened, try a target-specific DAG combine.
1457 if (!RV.getNode()) {
1458 assert(N->getOpcode() != ISD::DELETED_NODE &&
1459 "Node was deleted but visit returned NULL!");
1461 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1462 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1464 // Expose the DAG combiner to the target combiner impls.
1465 TargetLowering::DAGCombinerInfo
1466 DagCombineInfo(DAG, Level, false, this);
1468 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1472 // If nothing happened still, try promoting the operation.
1473 if (!RV.getNode()) {
1474 switch (N->getOpcode()) {
1482 RV = PromoteIntBinOp(SDValue(N, 0));
1487 RV = PromoteIntShiftOp(SDValue(N, 0));
1489 case ISD::SIGN_EXTEND:
1490 case ISD::ZERO_EXTEND:
1491 case ISD::ANY_EXTEND:
1492 RV = PromoteExtend(SDValue(N, 0));
1495 if (PromoteLoad(SDValue(N, 0)))
1501 // If N is a commutative binary node, try commuting it to enable more
1503 if (!RV.getNode() && SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1504 N->getNumValues() == 1) {
1505 SDValue N0 = N->getOperand(0);
1506 SDValue N1 = N->getOperand(1);
1508 // Constant operands are canonicalized to RHS.
1509 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1510 SDValue Ops[] = {N1, N0};
1511 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
1514 return SDValue(CSENode, 0);
1521 /// Given a node, return its input chain if it has one, otherwise return a null
1523 static SDValue getInputChainForNode(SDNode *N) {
1524 if (unsigned NumOps = N->getNumOperands()) {
1525 if (N->getOperand(0).getValueType() == MVT::Other)
1526 return N->getOperand(0);
1527 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1528 return N->getOperand(NumOps-1);
1529 for (unsigned i = 1; i < NumOps-1; ++i)
1530 if (N->getOperand(i).getValueType() == MVT::Other)
1531 return N->getOperand(i);
1536 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1537 // If N has two operands, where one has an input chain equal to the other,
1538 // the 'other' chain is redundant.
1539 if (N->getNumOperands() == 2) {
1540 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1541 return N->getOperand(0);
1542 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1543 return N->getOperand(1);
1546 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1547 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1548 SmallPtrSet<SDNode*, 16> SeenOps;
1549 bool Changed = false; // If we should replace this token factor.
1551 // Start out with this token factor.
1554 // Iterate through token factors. The TFs grows when new token factors are
1556 for (unsigned i = 0; i < TFs.size(); ++i) {
1557 SDNode *TF = TFs[i];
1559 // Check each of the operands.
1560 for (const SDValue &Op : TF->op_values()) {
1562 switch (Op.getOpcode()) {
1563 case ISD::EntryToken:
1564 // Entry tokens don't need to be added to the list. They are
1569 case ISD::TokenFactor:
1570 if (Op.hasOneUse() &&
1571 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1572 // Queue up for processing.
1573 TFs.push_back(Op.getNode());
1574 // Clean up in case the token factor is removed.
1575 AddToWorklist(Op.getNode());
1582 // Only add if it isn't already in the list.
1583 if (SeenOps.insert(Op.getNode()).second)
1594 // If we've changed things around then replace token factor.
1597 // The entry token is the only possible outcome.
1598 Result = DAG.getEntryNode();
1600 // New and improved token factor.
1601 Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Ops);
1604 // Add users to worklist if AA is enabled, since it may introduce
1605 // a lot of new chained token factors while removing memory deps.
1606 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
1607 : DAG.getSubtarget().useAA();
1608 return CombineTo(N, Result, UseAA /*add to worklist*/);
1614 /// MERGE_VALUES can always be eliminated.
1615 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1616 WorklistRemover DeadNodes(*this);
1617 // Replacing results may cause a different MERGE_VALUES to suddenly
1618 // be CSE'd with N, and carry its uses with it. Iterate until no
1619 // uses remain, to ensure that the node can be safely deleted.
1620 // First add the users of this node to the work list so that they
1621 // can be tried again once they have new operands.
1622 AddUsersToWorklist(N);
1624 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1625 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1626 } while (!N->use_empty());
1627 deleteAndRecombine(N);
1628 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1631 /// If \p N is a ContantSDNode with isOpaque() == false return it casted to a
1632 /// ContantSDNode pointer else nullptr.
1633 static ConstantSDNode *getAsNonOpaqueConstant(SDValue N) {
1634 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N);
1635 return Const != nullptr && !Const->isOpaque() ? Const : nullptr;
1638 SDValue DAGCombiner::visitADD(SDNode *N) {
1639 SDValue N0 = N->getOperand(0);
1640 SDValue N1 = N->getOperand(1);
1641 EVT VT = N0.getValueType();
1644 if (VT.isVector()) {
1645 if (SDValue FoldedVOp = SimplifyVBinOp(N))
1648 // fold (add x, 0) -> x, vector edition
1649 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1651 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1655 // fold (add x, undef) -> undef
1656 if (N0.getOpcode() == ISD::UNDEF)
1658 if (N1.getOpcode() == ISD::UNDEF)
1660 // fold (add c1, c2) -> c1+c2
1661 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
1662 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
1664 return DAG.FoldConstantArithmetic(ISD::ADD, SDLoc(N), VT, N0C, N1C);
1665 // canonicalize constant to RHS
1666 if (isConstantIntBuildVectorOrConstantInt(N0) &&
1667 !isConstantIntBuildVectorOrConstantInt(N1))
1668 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
1669 // fold (add x, 0) -> x
1670 if (isNullConstant(N1))
1672 // fold (add Sym, c) -> Sym+c
1673 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1674 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1675 GA->getOpcode() == ISD::GlobalAddress)
1676 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1678 (uint64_t)N1C->getSExtValue());
1679 // fold ((c1-A)+c2) -> (c1+c2)-A
1680 if (N1C && N0.getOpcode() == ISD::SUB)
1681 if (ConstantSDNode *N0C = getAsNonOpaqueConstant(N0.getOperand(0))) {
1683 return DAG.getNode(ISD::SUB, DL, VT,
1684 DAG.getConstant(N1C->getAPIntValue()+
1685 N0C->getAPIntValue(), DL, VT),
1689 if (SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1))
1691 // fold ((0-A) + B) -> B-A
1692 if (N0.getOpcode() == ISD::SUB && isNullConstant(N0.getOperand(0)))
1693 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1));
1694 // fold (A + (0-B)) -> A-B
1695 if (N1.getOpcode() == ISD::SUB && isNullConstant(N1.getOperand(0)))
1696 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1));
1697 // fold (A+(B-A)) -> B
1698 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1699 return N1.getOperand(0);
1700 // fold ((B-A)+A) -> B
1701 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1702 return N0.getOperand(0);
1703 // fold (A+(B-(A+C))) to (B-C)
1704 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1705 N0 == N1.getOperand(1).getOperand(0))
1706 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1707 N1.getOperand(1).getOperand(1));
1708 // fold (A+(B-(C+A))) to (B-C)
1709 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1710 N0 == N1.getOperand(1).getOperand(1))
1711 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1712 N1.getOperand(1).getOperand(0));
1713 // fold (A+((B-A)+or-C)) to (B+or-C)
1714 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1715 N1.getOperand(0).getOpcode() == ISD::SUB &&
1716 N0 == N1.getOperand(0).getOperand(1))
1717 return DAG.getNode(N1.getOpcode(), SDLoc(N), VT,
1718 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1720 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1721 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1722 SDValue N00 = N0.getOperand(0);
1723 SDValue N01 = N0.getOperand(1);
1724 SDValue N10 = N1.getOperand(0);
1725 SDValue N11 = N1.getOperand(1);
1727 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1728 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1729 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
1730 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
1733 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1734 return SDValue(N, 0);
1736 // fold (a+b) -> (a|b) iff a and b share no bits.
1737 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
1738 VT.isInteger() && !VT.isVector() && DAG.haveNoCommonBitsSet(N0, N1))
1739 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
1741 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1742 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
1743 isNullConstant(N1.getOperand(0).getOperand(0)))
1744 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0,
1745 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1746 N1.getOperand(0).getOperand(1),
1748 if (N0.getOpcode() == ISD::SHL && N0.getOperand(0).getOpcode() == ISD::SUB &&
1749 isNullConstant(N0.getOperand(0).getOperand(0)))
1750 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1,
1751 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1752 N0.getOperand(0).getOperand(1),
1755 if (N1.getOpcode() == ISD::AND) {
1756 SDValue AndOp0 = N1.getOperand(0);
1757 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1758 unsigned DestBits = VT.getScalarType().getSizeInBits();
1760 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1761 // and similar xforms where the inner op is either ~0 or 0.
1762 if (NumSignBits == DestBits && isOneConstant(N1->getOperand(1))) {
1764 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1768 // add (sext i1), X -> sub X, (zext i1)
1769 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1770 N0.getOperand(0).getValueType() == MVT::i1 &&
1771 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1773 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1774 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1777 // add X, (sextinreg Y i1) -> sub X, (and Y 1)
1778 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
1779 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
1780 if (TN->getVT() == MVT::i1) {
1782 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
1783 DAG.getConstant(1, DL, VT));
1784 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
1791 SDValue DAGCombiner::visitADDC(SDNode *N) {
1792 SDValue N0 = N->getOperand(0);
1793 SDValue N1 = N->getOperand(1);
1794 EVT VT = N0.getValueType();
1796 // If the flag result is dead, turn this into an ADD.
1797 if (!N->hasAnyUseOfValue(1))
1798 return CombineTo(N, DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1),
1799 DAG.getNode(ISD::CARRY_FALSE,
1800 SDLoc(N), MVT::Glue));
1802 // canonicalize constant to RHS.
1803 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1804 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1806 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
1808 // fold (addc x, 0) -> x + no carry out
1809 if (isNullConstant(N1))
1810 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1811 SDLoc(N), MVT::Glue));
1813 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1814 APInt LHSZero, LHSOne;
1815 APInt RHSZero, RHSOne;
1816 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1818 if (LHSZero.getBoolValue()) {
1819 DAG.computeKnownBits(N1, RHSZero, RHSOne);
1821 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1822 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1823 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1824 return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1),
1825 DAG.getNode(ISD::CARRY_FALSE,
1826 SDLoc(N), MVT::Glue));
1832 SDValue DAGCombiner::visitADDE(SDNode *N) {
1833 SDValue N0 = N->getOperand(0);
1834 SDValue N1 = N->getOperand(1);
1835 SDValue CarryIn = N->getOperand(2);
1837 // canonicalize constant to RHS
1838 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1839 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1841 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
1844 // fold (adde x, y, false) -> (addc x, y)
1845 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1846 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
1851 // Since it may not be valid to emit a fold to zero for vector initializers
1852 // check if we can before folding.
1853 static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT,
1855 bool LegalOperations, bool LegalTypes) {
1857 return DAG.getConstant(0, DL, VT);
1858 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
1859 return DAG.getConstant(0, DL, VT);
1863 SDValue DAGCombiner::visitSUB(SDNode *N) {
1864 SDValue N0 = N->getOperand(0);
1865 SDValue N1 = N->getOperand(1);
1866 EVT VT = N0.getValueType();
1869 if (VT.isVector()) {
1870 if (SDValue FoldedVOp = SimplifyVBinOp(N))
1873 // fold (sub x, 0) -> x, vector edition
1874 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1878 // fold (sub x, x) -> 0
1879 // FIXME: Refactor this and xor and other similar operations together.
1881 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
1882 // fold (sub c1, c2) -> c1-c2
1883 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
1884 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
1886 return DAG.FoldConstantArithmetic(ISD::SUB, SDLoc(N), VT, N0C, N1C);
1887 // fold (sub x, c) -> (add x, -c)
1890 return DAG.getNode(ISD::ADD, DL, VT, N0,
1891 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
1893 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1894 if (isAllOnesConstant(N0))
1895 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
1896 // fold A-(A-B) -> B
1897 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1898 return N1.getOperand(1);
1899 // fold (A+B)-A -> B
1900 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1901 return N0.getOperand(1);
1902 // fold (A+B)-B -> A
1903 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1904 return N0.getOperand(0);
1905 // fold C2-(A+C1) -> (C2-C1)-A
1906 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? nullptr :
1907 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1908 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1910 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
1912 return DAG.getNode(ISD::SUB, DL, VT, NewC,
1915 // fold ((A+(B+or-C))-B) -> A+or-C
1916 if (N0.getOpcode() == ISD::ADD &&
1917 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1918 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1919 N0.getOperand(1).getOperand(0) == N1)
1920 return DAG.getNode(N0.getOperand(1).getOpcode(), SDLoc(N), VT,
1921 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1922 // fold ((A+(C+B))-B) -> A+C
1923 if (N0.getOpcode() == ISD::ADD &&
1924 N0.getOperand(1).getOpcode() == ISD::ADD &&
1925 N0.getOperand(1).getOperand(1) == N1)
1926 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
1927 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1928 // fold ((A-(B-C))-C) -> A-B
1929 if (N0.getOpcode() == ISD::SUB &&
1930 N0.getOperand(1).getOpcode() == ISD::SUB &&
1931 N0.getOperand(1).getOperand(1) == N1)
1932 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1933 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1935 // If either operand of a sub is undef, the result is undef
1936 if (N0.getOpcode() == ISD::UNDEF)
1938 if (N1.getOpcode() == ISD::UNDEF)
1941 // If the relocation model supports it, consider symbol offsets.
1942 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1943 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1944 // fold (sub Sym, c) -> Sym-c
1945 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1946 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1948 (uint64_t)N1C->getSExtValue());
1949 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1950 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1951 if (GA->getGlobal() == GB->getGlobal())
1952 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1956 // sub X, (sextinreg Y i1) -> add X, (and Y 1)
1957 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
1958 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
1959 if (TN->getVT() == MVT::i1) {
1961 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
1962 DAG.getConstant(1, DL, VT));
1963 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
1970 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1971 SDValue N0 = N->getOperand(0);
1972 SDValue N1 = N->getOperand(1);
1973 EVT VT = N0.getValueType();
1976 // If the flag result is dead, turn this into an SUB.
1977 if (!N->hasAnyUseOfValue(1))
1978 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
1979 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
1981 // fold (subc x, x) -> 0 + no borrow
1983 return CombineTo(N, DAG.getConstant(0, DL, VT),
1984 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
1986 // fold (subc x, 0) -> x + no borrow
1987 if (isNullConstant(N1))
1988 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
1990 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1991 if (isAllOnesConstant(N0))
1992 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
1993 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
1998 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1999 SDValue N0 = N->getOperand(0);
2000 SDValue N1 = N->getOperand(1);
2001 SDValue CarryIn = N->getOperand(2);
2003 // fold (sube x, y, false) -> (subc x, y)
2004 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
2005 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
2010 SDValue DAGCombiner::visitMUL(SDNode *N) {
2011 SDValue N0 = N->getOperand(0);
2012 SDValue N1 = N->getOperand(1);
2013 EVT VT = N0.getValueType();
2015 // fold (mul x, undef) -> 0
2016 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2017 return DAG.getConstant(0, SDLoc(N), VT);
2019 bool N0IsConst = false;
2020 bool N1IsConst = false;
2021 bool N1IsOpaqueConst = false;
2022 bool N0IsOpaqueConst = false;
2023 APInt ConstValue0, ConstValue1;
2025 if (VT.isVector()) {
2026 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2029 N0IsConst = isConstantSplatVector(N0.getNode(), ConstValue0);
2030 N1IsConst = isConstantSplatVector(N1.getNode(), ConstValue1);
2032 N0IsConst = isa<ConstantSDNode>(N0);
2034 ConstValue0 = cast<ConstantSDNode>(N0)->getAPIntValue();
2035 N0IsOpaqueConst = cast<ConstantSDNode>(N0)->isOpaque();
2037 N1IsConst = isa<ConstantSDNode>(N1);
2039 ConstValue1 = cast<ConstantSDNode>(N1)->getAPIntValue();
2040 N1IsOpaqueConst = cast<ConstantSDNode>(N1)->isOpaque();
2044 // fold (mul c1, c2) -> c1*c2
2045 if (N0IsConst && N1IsConst && !N0IsOpaqueConst && !N1IsOpaqueConst)
2046 return DAG.FoldConstantArithmetic(ISD::MUL, SDLoc(N), VT,
2047 N0.getNode(), N1.getNode());
2049 // canonicalize constant to RHS (vector doesn't have to splat)
2050 if (isConstantIntBuildVectorOrConstantInt(N0) &&
2051 !isConstantIntBuildVectorOrConstantInt(N1))
2052 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
2053 // fold (mul x, 0) -> 0
2054 if (N1IsConst && ConstValue1 == 0)
2056 // We require a splat of the entire scalar bit width for non-contiguous
2059 ConstValue1.getBitWidth() == VT.getScalarType().getSizeInBits();
2060 // fold (mul x, 1) -> x
2061 if (N1IsConst && ConstValue1 == 1 && IsFullSplat)
2063 // fold (mul x, -1) -> 0-x
2064 if (N1IsConst && ConstValue1.isAllOnesValue()) {
2066 return DAG.getNode(ISD::SUB, DL, VT,
2067 DAG.getConstant(0, DL, VT), N0);
2069 // fold (mul x, (1 << c)) -> x << c
2070 if (N1IsConst && !N1IsOpaqueConst && ConstValue1.isPowerOf2() &&
2073 return DAG.getNode(ISD::SHL, DL, VT, N0,
2074 DAG.getConstant(ConstValue1.logBase2(), DL,
2075 getShiftAmountTy(N0.getValueType())));
2077 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
2078 if (N1IsConst && !N1IsOpaqueConst && (-ConstValue1).isPowerOf2() &&
2080 unsigned Log2Val = (-ConstValue1).logBase2();
2082 // FIXME: If the input is something that is easily negated (e.g. a
2083 // single-use add), we should put the negate there.
2084 return DAG.getNode(ISD::SUB, DL, VT,
2085 DAG.getConstant(0, DL, VT),
2086 DAG.getNode(ISD::SHL, DL, VT, N0,
2087 DAG.getConstant(Log2Val, DL,
2088 getShiftAmountTy(N0.getValueType()))));
2092 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
2093 if (N1IsConst && N0.getOpcode() == ISD::SHL &&
2094 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2095 isa<ConstantSDNode>(N0.getOperand(1)))) {
2096 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT,
2097 N1, N0.getOperand(1));
2098 AddToWorklist(C3.getNode());
2099 return DAG.getNode(ISD::MUL, SDLoc(N), VT,
2100 N0.getOperand(0), C3);
2103 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
2106 SDValue Sh(nullptr,0), Y(nullptr,0);
2107 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
2108 if (N0.getOpcode() == ISD::SHL &&
2109 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2110 isa<ConstantSDNode>(N0.getOperand(1))) &&
2111 N0.getNode()->hasOneUse()) {
2113 } else if (N1.getOpcode() == ISD::SHL &&
2114 isa<ConstantSDNode>(N1.getOperand(1)) &&
2115 N1.getNode()->hasOneUse()) {
2120 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2121 Sh.getOperand(0), Y);
2122 return DAG.getNode(ISD::SHL, SDLoc(N), VT,
2123 Mul, Sh.getOperand(1));
2127 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
2128 if (isConstantIntBuildVectorOrConstantInt(N1) &&
2129 N0.getOpcode() == ISD::ADD &&
2130 isConstantIntBuildVectorOrConstantInt(N0.getOperand(1)) &&
2131 isMulAddWithConstProfitable(N, N0, N1))
2132 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
2133 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
2134 N0.getOperand(0), N1),
2135 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
2136 N0.getOperand(1), N1));
2139 if (SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1))
2145 /// Return true if divmod libcall is available.
2146 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2147 const TargetLowering &TLI) {
2149 switch (Node->getSimpleValueType(0).SimpleTy) {
2150 default: return false; // No libcall for vector types.
2151 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2152 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2153 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2154 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2155 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2158 return TLI.getLibcallName(LC) != nullptr;
2161 /// Issue divrem if both quotient and remainder are needed.
2162 SDValue DAGCombiner::useDivRem(SDNode *Node) {
2163 if (Node->use_empty())
2164 return SDValue(); // This is a dead node, leave it alone.
2166 EVT VT = Node->getValueType(0);
2167 if (!TLI.isTypeLegal(VT))
2170 unsigned Opcode = Node->getOpcode();
2171 bool isSigned = (Opcode == ISD::SDIV) || (Opcode == ISD::SREM);
2173 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2174 // If DIVREM is going to get expanded into a libcall,
2175 // but there is no libcall available, then don't combine.
2176 if (!TLI.isOperationLegalOrCustom(DivRemOpc, VT) &&
2177 !isDivRemLibcallAvailable(Node, isSigned, TLI))
2180 // If div is legal, it's better to do the normal expansion
2181 unsigned OtherOpcode = 0;
2182 if ((Opcode == ISD::SDIV) || (Opcode == ISD::UDIV)) {
2183 OtherOpcode = isSigned ? ISD::SREM : ISD::UREM;
2184 if (TLI.isOperationLegalOrCustom(Opcode, VT))
2187 OtherOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
2188 if (TLI.isOperationLegalOrCustom(OtherOpcode, VT))
2192 SDValue Op0 = Node->getOperand(0);
2193 SDValue Op1 = Node->getOperand(1);
2195 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2196 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2198 if (User == Node || User->use_empty())
2200 // Convert the other matching node(s), too;
2201 // otherwise, the DIVREM may get target-legalized into something
2202 // target-specific that we won't be able to recognize.
2203 unsigned UserOpc = User->getOpcode();
2204 if ((UserOpc == Opcode || UserOpc == OtherOpcode || UserOpc == DivRemOpc) &&
2205 User->getOperand(0) == Op0 &&
2206 User->getOperand(1) == Op1) {
2208 if (UserOpc == OtherOpcode) {
2209 SDVTList VTs = DAG.getVTList(VT, VT);
2210 combined = DAG.getNode(DivRemOpc, SDLoc(Node), VTs, Op0, Op1);
2211 } else if (UserOpc == DivRemOpc) {
2212 combined = SDValue(User, 0);
2214 assert(UserOpc == Opcode);
2218 if (UserOpc == ISD::SDIV || UserOpc == ISD::UDIV)
2219 CombineTo(User, combined);
2220 else if (UserOpc == ISD::SREM || UserOpc == ISD::UREM)
2221 CombineTo(User, combined.getValue(1));
2227 SDValue DAGCombiner::visitSDIV(SDNode *N) {
2228 SDValue N0 = N->getOperand(0);
2229 SDValue N1 = N->getOperand(1);
2230 EVT VT = N->getValueType(0);
2234 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2239 // fold (sdiv c1, c2) -> c1/c2
2240 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2241 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2242 if (N0C && N1C && !N0C->isOpaque() && !N1C->isOpaque())
2243 return DAG.FoldConstantArithmetic(ISD::SDIV, DL, VT, N0C, N1C);
2244 // fold (sdiv X, 1) -> X
2245 if (N1C && N1C->isOne())
2247 // fold (sdiv X, -1) -> 0-X
2248 if (N1C && N1C->isAllOnesValue())
2249 return DAG.getNode(ISD::SUB, DL, VT,
2250 DAG.getConstant(0, DL, VT), N0);
2252 // If we know the sign bits of both operands are zero, strength reduce to a
2253 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
2254 if (!VT.isVector()) {
2255 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2256 return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);
2259 // fold (sdiv X, pow2) -> simple ops after legalize
2260 // FIXME: We check for the exact bit here because the generic lowering gives
2261 // better results in that case. The target-specific lowering should learn how
2262 // to handle exact sdivs efficiently.
2263 if (N1C && !N1C->isNullValue() && !N1C->isOpaque() &&
2264 !cast<BinaryWithFlagsSDNode>(N)->Flags.hasExact() &&
2265 (N1C->getAPIntValue().isPowerOf2() ||
2266 (-N1C->getAPIntValue()).isPowerOf2())) {
2267 // Target-specific implementation of sdiv x, pow2.
2268 if (SDValue Res = BuildSDIVPow2(N))
2271 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
2273 // Splat the sign bit into the register
2275 DAG.getNode(ISD::SRA, DL, VT, N0,
2276 DAG.getConstant(VT.getScalarSizeInBits() - 1, DL,
2277 getShiftAmountTy(N0.getValueType())));
2278 AddToWorklist(SGN.getNode());
2280 // Add (N0 < 0) ? abs2 - 1 : 0;
2282 DAG.getNode(ISD::SRL, DL, VT, SGN,
2283 DAG.getConstant(VT.getScalarSizeInBits() - lg2, DL,
2284 getShiftAmountTy(SGN.getValueType())));
2285 SDValue ADD = DAG.getNode(ISD::ADD, DL, VT, N0, SRL);
2286 AddToWorklist(SRL.getNode());
2287 AddToWorklist(ADD.getNode()); // Divide by pow2
2288 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, ADD,
2289 DAG.getConstant(lg2, DL,
2290 getShiftAmountTy(ADD.getValueType())));
2292 // If we're dividing by a positive value, we're done. Otherwise, we must
2293 // negate the result.
2294 if (N1C->getAPIntValue().isNonNegative())
2297 AddToWorklist(SRA.getNode());
2298 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
2301 // If integer divide is expensive and we satisfy the requirements, emit an
2302 // alternate sequence. Targets may check function attributes for size/speed
2304 AttributeSet Attr = DAG.getMachineFunction().getFunction()->getAttributes();
2305 if (N1C && !TLI.isIntDivCheap(N->getValueType(0), Attr))
2306 if (SDValue Op = BuildSDIV(N))
2309 // sdiv, srem -> sdivrem
2310 // If the divisor is constant, then return DIVREM only if isIntDivCheap() is true.
2311 // Otherwise, we break the simplification logic in visitREM().
2312 if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
2313 if (SDValue DivRem = useDivRem(N))
2317 if (N0.getOpcode() == ISD::UNDEF)
2318 return DAG.getConstant(0, DL, VT);
2319 // X / undef -> undef
2320 if (N1.getOpcode() == ISD::UNDEF)
2326 SDValue DAGCombiner::visitUDIV(SDNode *N) {
2327 SDValue N0 = N->getOperand(0);
2328 SDValue N1 = N->getOperand(1);
2329 EVT VT = N->getValueType(0);
2333 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2338 // fold (udiv c1, c2) -> c1/c2
2339 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2340 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2342 if (SDValue Folded = DAG.FoldConstantArithmetic(ISD::UDIV, DL, VT,
2345 // fold (udiv x, (1 << c)) -> x >>u c
2346 if (N1C && !N1C->isOpaque() && N1C->getAPIntValue().isPowerOf2())
2347 return DAG.getNode(ISD::SRL, DL, VT, N0,
2348 DAG.getConstant(N1C->getAPIntValue().logBase2(), DL,
2349 getShiftAmountTy(N0.getValueType())));
2351 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
2352 if (N1.getOpcode() == ISD::SHL) {
2353 if (ConstantSDNode *SHC = getAsNonOpaqueConstant(N1.getOperand(0))) {
2354 if (SHC->getAPIntValue().isPowerOf2()) {
2355 EVT ADDVT = N1.getOperand(1).getValueType();
2356 SDValue Add = DAG.getNode(ISD::ADD, DL, ADDVT,
2358 DAG.getConstant(SHC->getAPIntValue()
2361 AddToWorklist(Add.getNode());
2362 return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
2367 // fold (udiv x, c) -> alternate
2368 AttributeSet Attr = DAG.getMachineFunction().getFunction()->getAttributes();
2369 if (N1C && !TLI.isIntDivCheap(N->getValueType(0), Attr))
2370 if (SDValue Op = BuildUDIV(N))
2373 // sdiv, srem -> sdivrem
2374 // If the divisor is constant, then return DIVREM only if isIntDivCheap() is true.
2375 // Otherwise, we break the simplification logic in visitREM().
2376 if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
2377 if (SDValue DivRem = useDivRem(N))
2381 if (N0.getOpcode() == ISD::UNDEF)
2382 return DAG.getConstant(0, DL, VT);
2383 // X / undef -> undef
2384 if (N1.getOpcode() == ISD::UNDEF)
2390 // handles ISD::SREM and ISD::UREM
2391 SDValue DAGCombiner::visitREM(SDNode *N) {
2392 unsigned Opcode = N->getOpcode();
2393 SDValue N0 = N->getOperand(0);
2394 SDValue N1 = N->getOperand(1);
2395 EVT VT = N->getValueType(0);
2396 bool isSigned = (Opcode == ISD::SREM);
2399 // fold (rem c1, c2) -> c1%c2
2400 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2401 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2403 if (SDValue Folded = DAG.FoldConstantArithmetic(Opcode, DL, VT, N0C, N1C))
2407 // If we know the sign bits of both operands are zero, strength reduce to a
2408 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
2409 if (!VT.isVector()) {
2410 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2411 return DAG.getNode(ISD::UREM, DL, VT, N0, N1);
2414 // fold (urem x, pow2) -> (and x, pow2-1)
2415 if (N1C && !N1C->isNullValue() && !N1C->isOpaque() &&
2416 N1C->getAPIntValue().isPowerOf2()) {
2417 return DAG.getNode(ISD::AND, DL, VT, N0,
2418 DAG.getConstant(N1C->getAPIntValue() - 1, DL, VT));
2420 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2421 if (N1.getOpcode() == ISD::SHL) {
2422 if (ConstantSDNode *SHC = getAsNonOpaqueConstant(N1.getOperand(0))) {
2423 if (SHC->getAPIntValue().isPowerOf2()) {
2425 DAG.getNode(ISD::ADD, DL, VT, N1,
2426 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL,
2428 AddToWorklist(Add.getNode());
2429 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
2435 AttributeSet Attr = DAG.getMachineFunction().getFunction()->getAttributes();
2437 // If X/C can be simplified by the division-by-constant logic, lower
2438 // X%C to the equivalent of X-X/C*C.
2439 // To avoid mangling nodes, this simplification requires that the combine()
2440 // call for the speculative DIV must not cause a DIVREM conversion. We guard
2441 // against this by skipping the simplification if isIntDivCheap(). When
2442 // div is not cheap, combine will not return a DIVREM. Regardless,
2443 // checking cheapness here makes sense since the simplification results in
2445 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap(VT, Attr)) {
2446 unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
2447 SDValue Div = DAG.getNode(DivOpcode, DL, VT, N0, N1);
2448 AddToWorklist(Div.getNode());
2449 SDValue OptimizedDiv = combine(Div.getNode());
2450 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2451 assert((OptimizedDiv.getOpcode() != ISD::UDIVREM) &&
2452 (OptimizedDiv.getOpcode() != ISD::SDIVREM));
2453 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, OptimizedDiv, N1);
2454 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
2455 AddToWorklist(Mul.getNode());
2460 // sdiv, srem -> sdivrem
2461 if (SDValue DivRem = useDivRem(N))
2462 return DivRem.getValue(1);
2465 if (N0.getOpcode() == ISD::UNDEF)
2466 return DAG.getConstant(0, DL, VT);
2467 // X % undef -> undef
2468 if (N1.getOpcode() == ISD::UNDEF)
2474 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2475 SDValue N0 = N->getOperand(0);
2476 SDValue N1 = N->getOperand(1);
2477 EVT VT = N->getValueType(0);
2480 // fold (mulhs x, 0) -> 0
2481 if (isNullConstant(N1))
2483 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2484 if (isOneConstant(N1)) {
2486 return DAG.getNode(ISD::SRA, DL, N0.getValueType(), N0,
2487 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2489 getShiftAmountTy(N0.getValueType())));
2491 // fold (mulhs x, undef) -> 0
2492 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2493 return DAG.getConstant(0, SDLoc(N), VT);
2495 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2497 if (VT.isSimple() && !VT.isVector()) {
2498 MVT Simple = VT.getSimpleVT();
2499 unsigned SimpleSize = Simple.getSizeInBits();
2500 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2501 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2502 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2503 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2504 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2505 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2506 DAG.getConstant(SimpleSize, DL,
2507 getShiftAmountTy(N1.getValueType())));
2508 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2515 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2516 SDValue N0 = N->getOperand(0);
2517 SDValue N1 = N->getOperand(1);
2518 EVT VT = N->getValueType(0);
2521 // fold (mulhu x, 0) -> 0
2522 if (isNullConstant(N1))
2524 // fold (mulhu x, 1) -> 0
2525 if (isOneConstant(N1))
2526 return DAG.getConstant(0, DL, N0.getValueType());
2527 // fold (mulhu x, undef) -> 0
2528 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2529 return DAG.getConstant(0, DL, VT);
2531 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2533 if (VT.isSimple() && !VT.isVector()) {
2534 MVT Simple = VT.getSimpleVT();
2535 unsigned SimpleSize = Simple.getSizeInBits();
2536 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2537 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2538 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2539 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2540 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2541 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2542 DAG.getConstant(SimpleSize, DL,
2543 getShiftAmountTy(N1.getValueType())));
2544 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2551 /// Perform optimizations common to nodes that compute two values. LoOp and HiOp
2552 /// give the opcodes for the two computations that are being performed. Return
2553 /// true if a simplification was made.
2554 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2556 // If the high half is not needed, just compute the low half.
2557 bool HiExists = N->hasAnyUseOfValue(1);
2559 (!LegalOperations ||
2560 TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) {
2561 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
2562 return CombineTo(N, Res, Res);
2565 // If the low half is not needed, just compute the high half.
2566 bool LoExists = N->hasAnyUseOfValue(0);
2568 (!LegalOperations ||
2569 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2570 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
2571 return CombineTo(N, Res, Res);
2574 // If both halves are used, return as it is.
2575 if (LoExists && HiExists)
2578 // If the two computed results can be simplified separately, separate them.
2580 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
2581 AddToWorklist(Lo.getNode());
2582 SDValue LoOpt = combine(Lo.getNode());
2583 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2584 (!LegalOperations ||
2585 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2586 return CombineTo(N, LoOpt, LoOpt);
2590 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
2591 AddToWorklist(Hi.getNode());
2592 SDValue HiOpt = combine(Hi.getNode());
2593 if (HiOpt.getNode() && HiOpt != Hi &&
2594 (!LegalOperations ||
2595 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2596 return CombineTo(N, HiOpt, HiOpt);
2602 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2603 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
2606 EVT VT = N->getValueType(0);
2609 // If the type is twice as wide is legal, transform the mulhu to a wider
2610 // multiply plus a shift.
2611 if (VT.isSimple() && !VT.isVector()) {
2612 MVT Simple = VT.getSimpleVT();
2613 unsigned SimpleSize = Simple.getSizeInBits();
2614 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2615 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2616 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2617 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2618 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2619 // Compute the high part as N1.
2620 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2621 DAG.getConstant(SimpleSize, DL,
2622 getShiftAmountTy(Lo.getValueType())));
2623 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2624 // Compute the low part as N0.
2625 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2626 return CombineTo(N, Lo, Hi);
2633 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2634 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
2637 EVT VT = N->getValueType(0);
2640 // If the type is twice as wide is legal, transform the mulhu to a wider
2641 // multiply plus a shift.
2642 if (VT.isSimple() && !VT.isVector()) {
2643 MVT Simple = VT.getSimpleVT();
2644 unsigned SimpleSize = Simple.getSizeInBits();
2645 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2646 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2647 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2648 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2649 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2650 // Compute the high part as N1.
2651 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2652 DAG.getConstant(SimpleSize, DL,
2653 getShiftAmountTy(Lo.getValueType())));
2654 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2655 // Compute the low part as N0.
2656 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2657 return CombineTo(N, Lo, Hi);
2664 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2665 // (smulo x, 2) -> (saddo x, x)
2666 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2667 if (C2->getAPIntValue() == 2)
2668 return DAG.getNode(ISD::SADDO, SDLoc(N), N->getVTList(),
2669 N->getOperand(0), N->getOperand(0));
2674 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2675 // (umulo x, 2) -> (uaddo x, x)
2676 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2677 if (C2->getAPIntValue() == 2)
2678 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(),
2679 N->getOperand(0), N->getOperand(0));
2684 SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
2685 SDValue N0 = N->getOperand(0);
2686 SDValue N1 = N->getOperand(1);
2687 EVT VT = N0.getValueType();
2691 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2694 // fold (add c1, c2) -> c1+c2
2695 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
2696 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
2698 return DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, N0C, N1C);
2700 // canonicalize constant to RHS
2701 if (isConstantIntBuildVectorOrConstantInt(N0) &&
2702 !isConstantIntBuildVectorOrConstantInt(N1))
2703 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
2708 /// If this is a binary operator with two operands of the same opcode, try to
2710 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2711 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2712 EVT VT = N0.getValueType();
2713 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2715 // Bail early if none of these transforms apply.
2716 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2718 // For each of OP in AND/OR/XOR:
2719 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2720 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2721 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2722 // fold (OP (bswap x), (bswap y)) -> (bswap (OP x, y))
2723 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2725 // do not sink logical op inside of a vector extend, since it may combine
2727 EVT Op0VT = N0.getOperand(0).getValueType();
2728 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2729 N0.getOpcode() == ISD::SIGN_EXTEND ||
2730 N0.getOpcode() == ISD::BSWAP ||
2731 // Avoid infinite looping with PromoteIntBinOp.
2732 (N0.getOpcode() == ISD::ANY_EXTEND &&
2733 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2734 (N0.getOpcode() == ISD::TRUNCATE &&
2735 (!TLI.isZExtFree(VT, Op0VT) ||
2736 !TLI.isTruncateFree(Op0VT, VT)) &&
2737 TLI.isTypeLegal(Op0VT))) &&
2739 Op0VT == N1.getOperand(0).getValueType() &&
2740 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2741 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2742 N0.getOperand(0).getValueType(),
2743 N0.getOperand(0), N1.getOperand(0));
2744 AddToWorklist(ORNode.getNode());
2745 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode);
2748 // For each of OP in SHL/SRL/SRA/AND...
2749 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2750 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2751 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2752 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2753 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2754 N0.getOperand(1) == N1.getOperand(1)) {
2755 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2756 N0.getOperand(0).getValueType(),
2757 N0.getOperand(0), N1.getOperand(0));
2758 AddToWorklist(ORNode.getNode());
2759 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
2760 ORNode, N0.getOperand(1));
2763 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2764 // Only perform this optimization after type legalization and before
2765 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2766 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2767 // we don't want to undo this promotion.
2768 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2770 if ((N0.getOpcode() == ISD::BITCAST ||
2771 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2772 Level == AfterLegalizeTypes) {
2773 SDValue In0 = N0.getOperand(0);
2774 SDValue In1 = N1.getOperand(0);
2775 EVT In0Ty = In0.getValueType();
2776 EVT In1Ty = In1.getValueType();
2778 // If both incoming values are integers, and the original types are the
2780 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2781 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2782 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2783 AddToWorklist(Op.getNode());
2788 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2789 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2790 // If both shuffles use the same mask, and both shuffle within a single
2791 // vector, then it is worthwhile to move the swizzle after the operation.
2792 // The type-legalizer generates this pattern when loading illegal
2793 // vector types from memory. In many cases this allows additional shuffle
2795 // There are other cases where moving the shuffle after the xor/and/or
2796 // is profitable even if shuffles don't perform a swizzle.
2797 // If both shuffles use the same mask, and both shuffles have the same first
2798 // or second operand, then it might still be profitable to move the shuffle
2799 // after the xor/and/or operation.
2800 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
2801 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2802 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2804 assert(N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() &&
2805 "Inputs to shuffles are not the same type");
2807 // Check that both shuffles use the same mask. The masks are known to be of
2808 // the same length because the result vector type is the same.
2809 // Check also that shuffles have only one use to avoid introducing extra
2811 if (SVN0->hasOneUse() && SVN1->hasOneUse() &&
2812 SVN0->getMask().equals(SVN1->getMask())) {
2813 SDValue ShOp = N0->getOperand(1);
2815 // Don't try to fold this node if it requires introducing a
2816 // build vector of all zeros that might be illegal at this stage.
2817 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2819 ShOp = DAG.getConstant(0, SDLoc(N), VT);
2824 // (AND (shuf (A, C), shuf (B, C)) -> shuf (AND (A, B), C)
2825 // (OR (shuf (A, C), shuf (B, C)) -> shuf (OR (A, B), C)
2826 // (XOR (shuf (A, C), shuf (B, C)) -> shuf (XOR (A, B), V_0)
2827 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
2828 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2829 N0->getOperand(0), N1->getOperand(0));
2830 AddToWorklist(NewNode.getNode());
2831 return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp,
2832 &SVN0->getMask()[0]);
2835 // Don't try to fold this node if it requires introducing a
2836 // build vector of all zeros that might be illegal at this stage.
2837 ShOp = N0->getOperand(0);
2838 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2840 ShOp = DAG.getConstant(0, SDLoc(N), VT);
2845 // (AND (shuf (C, A), shuf (C, B)) -> shuf (C, AND (A, B))
2846 // (OR (shuf (C, A), shuf (C, B)) -> shuf (C, OR (A, B))
2847 // (XOR (shuf (C, A), shuf (C, B)) -> shuf (V_0, XOR (A, B))
2848 if (N0->getOperand(0) == N1->getOperand(0) && ShOp.getNode()) {
2849 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2850 N0->getOperand(1), N1->getOperand(1));
2851 AddToWorklist(NewNode.getNode());
2852 return DAG.getVectorShuffle(VT, SDLoc(N), ShOp, NewNode,
2853 &SVN0->getMask()[0]);
2861 /// This contains all DAGCombine rules which reduce two values combined by
2862 /// an And operation to a single value. This makes them reusable in the context
2863 /// of visitSELECT(). Rules involving constants are not included as
2864 /// visitSELECT() already handles those cases.
2865 SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1,
2866 SDNode *LocReference) {
2867 EVT VT = N1.getValueType();
2869 // fold (and x, undef) -> 0
2870 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2871 return DAG.getConstant(0, SDLoc(LocReference), VT);
2872 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2873 SDValue LL, LR, RL, RR, CC0, CC1;
2874 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2875 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2876 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2878 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2879 LL.getValueType().isInteger()) {
2880 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2881 if (isNullConstant(LR) && Op1 == ISD::SETEQ) {
2882 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2883 LR.getValueType(), LL, RL);
2884 AddToWorklist(ORNode.getNode());
2885 return DAG.getSetCC(SDLoc(LocReference), VT, ORNode, LR, Op1);
2887 if (isAllOnesConstant(LR)) {
2888 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2889 if (Op1 == ISD::SETEQ) {
2890 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0),
2891 LR.getValueType(), LL, RL);
2892 AddToWorklist(ANDNode.getNode());
2893 return DAG.getSetCC(SDLoc(LocReference), VT, ANDNode, LR, Op1);
2895 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2896 if (Op1 == ISD::SETGT) {
2897 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2898 LR.getValueType(), LL, RL);
2899 AddToWorklist(ORNode.getNode());
2900 return DAG.getSetCC(SDLoc(LocReference), VT, ORNode, LR, Op1);
2904 // Simplify (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
2905 if (LL == RL && isa<ConstantSDNode>(LR) && isa<ConstantSDNode>(RR) &&
2906 Op0 == Op1 && LL.getValueType().isInteger() &&
2907 Op0 == ISD::SETNE && ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
2908 (isAllOnesConstant(LR) && isNullConstant(RR)))) {
2910 SDValue ADDNode = DAG.getNode(ISD::ADD, DL, LL.getValueType(),
2911 LL, DAG.getConstant(1, DL,
2912 LL.getValueType()));
2913 AddToWorklist(ADDNode.getNode());
2914 return DAG.getSetCC(SDLoc(LocReference), VT, ADDNode,
2915 DAG.getConstant(2, DL, LL.getValueType()),
2918 // canonicalize equivalent to ll == rl
2919 if (LL == RR && LR == RL) {
2920 Op1 = ISD::getSetCCSwappedOperands(Op1);
2923 if (LL == RL && LR == RR) {
2924 bool isInteger = LL.getValueType().isInteger();
2925 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2926 if (Result != ISD::SETCC_INVALID &&
2927 (!LegalOperations ||
2928 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
2929 TLI.isOperationLegal(ISD::SETCC, LL.getValueType())))) {
2930 EVT CCVT = getSetCCResultType(LL.getValueType());
2931 if (N0.getValueType() == CCVT ||
2932 (!LegalOperations && N0.getValueType() == MVT::i1))
2933 return DAG.getSetCC(SDLoc(LocReference), N0.getValueType(),
2939 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2940 VT.getSizeInBits() <= 64) {
2941 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2942 APInt ADDC = ADDI->getAPIntValue();
2943 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2944 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
2945 // immediate for an add, but it is legal if its top c2 bits are set,
2946 // transform the ADD so the immediate doesn't need to be materialized
2948 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
2949 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
2950 SRLI->getZExtValue());
2951 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
2953 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2956 DAG.getNode(ISD::ADD, DL, VT,
2957 N0.getOperand(0), DAG.getConstant(ADDC, DL, VT));
2958 CombineTo(N0.getNode(), NewAdd);
2959 // Return N so it doesn't get rechecked!
2960 return SDValue(LocReference, 0);
2971 bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
2972 EVT LoadResultTy, EVT &ExtVT, EVT &LoadedVT,
2974 uint32_t ActiveBits = AndC->getAPIntValue().getActiveBits();
2976 if (ActiveBits == 0 || !APIntOps::isMask(ActiveBits, AndC->getAPIntValue()))
2979 ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2980 LoadedVT = LoadN->getMemoryVT();
2982 if (ExtVT == LoadedVT &&
2983 (!LegalOperations ||
2984 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) {
2985 // ZEXTLOAD will match without needing to change the size of the value being
2991 // Do not change the width of a volatile load.
2992 if (LoadN->isVolatile())
2995 // Do not generate loads of non-round integer types since these can
2996 // be expensive (and would be wrong if the type is not byte sized).
2997 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound())
3000 if (LegalOperations &&
3001 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))
3004 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT))
3011 SDValue DAGCombiner::visitAND(SDNode *N) {
3012 SDValue N0 = N->getOperand(0);
3013 SDValue N1 = N->getOperand(1);
3014 EVT VT = N1.getValueType();
3017 if (VT.isVector()) {
3018 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3021 // fold (and x, 0) -> 0, vector edition
3022 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3023 // do not return N0, because undef node may exist in N0
3024 return DAG.getConstant(
3025 APInt::getNullValue(
3026 N0.getValueType().getScalarType().getSizeInBits()),
3027 SDLoc(N), N0.getValueType());
3028 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3029 // do not return N1, because undef node may exist in N1
3030 return DAG.getConstant(
3031 APInt::getNullValue(
3032 N1.getValueType().getScalarType().getSizeInBits()),
3033 SDLoc(N), N1.getValueType());
3035 // fold (and x, -1) -> x, vector edition
3036 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3038 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3042 // fold (and c1, c2) -> c1&c2
3043 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
3044 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3045 if (N0C && N1C && !N1C->isOpaque())
3046 return DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, N0C, N1C);
3047 // canonicalize constant to RHS
3048 if (isConstantIntBuildVectorOrConstantInt(N0) &&
3049 !isConstantIntBuildVectorOrConstantInt(N1))
3050 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
3051 // fold (and x, -1) -> x
3052 if (isAllOnesConstant(N1))
3054 // if (and x, c) is known to be zero, return 0
3055 unsigned BitWidth = VT.getScalarType().getSizeInBits();
3056 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3057 APInt::getAllOnesValue(BitWidth)))
3058 return DAG.getConstant(0, SDLoc(N), VT);
3060 if (SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1))
3062 // fold (and (or x, C), D) -> D if (C & D) == D
3063 if (N1C && N0.getOpcode() == ISD::OR)
3064 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3065 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
3067 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
3068 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3069 SDValue N0Op0 = N0.getOperand(0);
3070 APInt Mask = ~N1C->getAPIntValue();
3071 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
3072 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
3073 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
3074 N0.getValueType(), N0Op0);
3076 // Replace uses of the AND with uses of the Zero extend node.
3079 // We actually want to replace all uses of the any_extend with the
3080 // zero_extend, to avoid duplicating things. This will later cause this
3081 // AND to be folded.
3082 CombineTo(N0.getNode(), Zext);
3083 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3086 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
3087 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
3088 // already be zero by virtue of the width of the base type of the load.
3090 // the 'X' node here can either be nothing or an extract_vector_elt to catch
3092 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
3093 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
3094 N0.getOpcode() == ISD::LOAD) {
3095 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
3096 N0 : N0.getOperand(0) );
3098 // Get the constant (if applicable) the zero'th operand is being ANDed with.
3099 // This can be a pure constant or a vector splat, in which case we treat the
3100 // vector as a scalar and use the splat value.
3101 APInt Constant = APInt::getNullValue(1);
3102 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
3103 Constant = C->getAPIntValue();
3104 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
3105 APInt SplatValue, SplatUndef;
3106 unsigned SplatBitSize;
3108 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
3109 SplatBitSize, HasAnyUndefs);
3111 // Undef bits can contribute to a possible optimisation if set, so
3113 SplatValue |= SplatUndef;
3115 // The splat value may be something like "0x00FFFFFF", which means 0 for
3116 // the first vector value and FF for the rest, repeating. We need a mask
3117 // that will apply equally to all members of the vector, so AND all the
3118 // lanes of the constant together.
3119 EVT VT = Vector->getValueType(0);
3120 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
3122 // If the splat value has been compressed to a bitlength lower
3123 // than the size of the vector lane, we need to re-expand it to
3125 if (BitWidth > SplatBitSize)
3126 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
3127 SplatBitSize < BitWidth;
3128 SplatBitSize = SplatBitSize * 2)
3129 SplatValue |= SplatValue.shl(SplatBitSize);
3131 // Make sure that variable 'Constant' is only set if 'SplatBitSize' is a
3132 // multiple of 'BitWidth'. Otherwise, we could propagate a wrong value.
3133 if (SplatBitSize % BitWidth == 0) {
3134 Constant = APInt::getAllOnesValue(BitWidth);
3135 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
3136 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
3141 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
3142 // actually legal and isn't going to get expanded, else this is a false
3144 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
3145 Load->getValueType(0),
3146 Load->getMemoryVT());
3148 // Resize the constant to the same size as the original memory access before
3149 // extension. If it is still the AllOnesValue then this AND is completely
3152 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
3155 switch (Load->getExtensionType()) {
3156 default: B = false; break;
3157 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
3159 case ISD::NON_EXTLOAD: B = true; break;
3162 if (B && Constant.isAllOnesValue()) {
3163 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
3164 // preserve semantics once we get rid of the AND.
3165 SDValue NewLoad(Load, 0);
3166 if (Load->getExtensionType() == ISD::EXTLOAD) {
3167 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
3168 Load->getValueType(0), SDLoc(Load),
3169 Load->getChain(), Load->getBasePtr(),
3170 Load->getOffset(), Load->getMemoryVT(),
3171 Load->getMemOperand());
3172 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
3173 if (Load->getNumValues() == 3) {
3174 // PRE/POST_INC loads have 3 values.
3175 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
3176 NewLoad.getValue(2) };
3177 CombineTo(Load, To, 3, true);
3179 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
3183 // Fold the AND away, taking care not to fold to the old load node if we
3185 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
3187 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3191 // fold (and (load x), 255) -> (zextload x, i8)
3192 // fold (and (extload x, i16), 255) -> (zextload x, i8)
3193 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
3194 if (N1C && (N0.getOpcode() == ISD::LOAD ||
3195 (N0.getOpcode() == ISD::ANY_EXTEND &&
3196 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
3197 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
3198 LoadSDNode *LN0 = HasAnyExt
3199 ? cast<LoadSDNode>(N0.getOperand(0))
3200 : cast<LoadSDNode>(N0);
3201 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
3202 LN0->isUnindexed() && N0.hasOneUse() && SDValue(LN0, 0).hasOneUse()) {
3203 auto NarrowLoad = false;
3204 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
3205 EVT ExtVT, LoadedVT;
3206 if (isAndLoadExtLoad(N1C, LN0, LoadResultTy, ExtVT, LoadedVT,
3210 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
3211 LN0->getChain(), LN0->getBasePtr(), ExtVT,
3212 LN0->getMemOperand());
3214 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
3215 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3217 EVT PtrType = LN0->getOperand(1).getValueType();
3219 unsigned Alignment = LN0->getAlignment();
3220 SDValue NewPtr = LN0->getBasePtr();
3222 // For big endian targets, we need to add an offset to the pointer
3223 // to load the correct bytes. For little endian systems, we merely
3224 // need to read fewer bytes from the same pointer.
3225 if (DAG.getDataLayout().isBigEndian()) {
3226 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
3227 unsigned EVTStoreBytes = ExtVT.getStoreSize();
3228 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
3230 NewPtr = DAG.getNode(ISD::ADD, DL, PtrType,
3231 NewPtr, DAG.getConstant(PtrOff, DL, PtrType));
3232 Alignment = MinAlign(Alignment, PtrOff);
3235 AddToWorklist(NewPtr.getNode());
3238 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
3239 LN0->getChain(), NewPtr,
3240 LN0->getPointerInfo(),
3241 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
3242 LN0->isInvariant(), Alignment, LN0->getAAInfo());
3244 CombineTo(LN0, Load, Load.getValue(1));
3245 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3251 if (SDValue Combined = visitANDLike(N0, N1, N))
3254 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
3255 if (N0.getOpcode() == N1.getOpcode())
3256 if (SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N))
3259 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
3260 // fold (and (sra)) -> (and (srl)) when possible.
3261 if (!VT.isVector() &&
3262 SimplifyDemandedBits(SDValue(N, 0)))
3263 return SDValue(N, 0);
3265 // fold (zext_inreg (extload x)) -> (zextload x)
3266 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
3267 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3268 EVT MemVT = LN0->getMemoryVT();
3269 // If we zero all the possible extended bits, then we can turn this into
3270 // a zextload if we are running before legalize or the operation is legal.
3271 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
3272 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
3273 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
3274 ((!LegalOperations && !LN0->isVolatile()) ||
3275 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
3276 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
3277 LN0->getChain(), LN0->getBasePtr(),
3278 MemVT, LN0->getMemOperand());
3280 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3281 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3284 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
3285 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3287 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3288 EVT MemVT = LN0->getMemoryVT();
3289 // If we zero all the possible extended bits, then we can turn this into
3290 // a zextload if we are running before legalize or the operation is legal.
3291 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
3292 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
3293 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
3294 ((!LegalOperations && !LN0->isVolatile()) ||
3295 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
3296 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
3297 LN0->getChain(), LN0->getBasePtr(),
3298 MemVT, LN0->getMemOperand());
3300 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3301 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3304 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
3305 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
3306 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
3307 N0.getOperand(1), false);
3308 if (BSwap.getNode())
3315 /// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
3316 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
3317 bool DemandHighBits) {
3318 if (!LegalOperations)
3321 EVT VT = N->getValueType(0);
3322 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
3324 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3327 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
3328 bool LookPassAnd0 = false;
3329 bool LookPassAnd1 = false;
3330 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
3332 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
3334 if (N0.getOpcode() == ISD::AND) {
3335 if (!N0.getNode()->hasOneUse())
3337 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3338 if (!N01C || N01C->getZExtValue() != 0xFF00)
3340 N0 = N0.getOperand(0);
3341 LookPassAnd0 = true;
3344 if (N1.getOpcode() == ISD::AND) {
3345 if (!N1.getNode()->hasOneUse())
3347 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
3348 if (!N11C || N11C->getZExtValue() != 0xFF)
3350 N1 = N1.getOperand(0);
3351 LookPassAnd1 = true;
3354 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
3356 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
3358 if (!N0.getNode()->hasOneUse() ||
3359 !N1.getNode()->hasOneUse())
3362 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3363 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
3366 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
3369 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
3370 SDValue N00 = N0->getOperand(0);
3371 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
3372 if (!N00.getNode()->hasOneUse())
3374 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
3375 if (!N001C || N001C->getZExtValue() != 0xFF)
3377 N00 = N00.getOperand(0);
3378 LookPassAnd0 = true;
3381 SDValue N10 = N1->getOperand(0);
3382 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
3383 if (!N10.getNode()->hasOneUse())
3385 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
3386 if (!N101C || N101C->getZExtValue() != 0xFF00)
3388 N10 = N10.getOperand(0);
3389 LookPassAnd1 = true;
3395 // Make sure everything beyond the low halfword gets set to zero since the SRL
3396 // 16 will clear the top bits.
3397 unsigned OpSizeInBits = VT.getSizeInBits();
3398 if (DemandHighBits && OpSizeInBits > 16) {
3399 // If the left-shift isn't masked out then the only way this is a bswap is
3400 // if all bits beyond the low 8 are 0. In that case the entire pattern
3401 // reduces to a left shift anyway: leave it for other parts of the combiner.
3405 // However, if the right shift isn't masked out then it might be because
3406 // it's not needed. See if we can spot that too.
3407 if (!LookPassAnd1 &&
3408 !DAG.MaskedValueIsZero(
3409 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
3413 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
3414 if (OpSizeInBits > 16) {
3416 Res = DAG.getNode(ISD::SRL, DL, VT, Res,
3417 DAG.getConstant(OpSizeInBits - 16, DL,
3418 getShiftAmountTy(VT)));
3423 /// Return true if the specified node is an element that makes up a 32-bit
3424 /// packed halfword byteswap.
3425 /// ((x & 0x000000ff) << 8) |
3426 /// ((x & 0x0000ff00) >> 8) |
3427 /// ((x & 0x00ff0000) << 8) |
3428 /// ((x & 0xff000000) >> 8)
3429 static bool isBSwapHWordElement(SDValue N, MutableArrayRef<SDNode *> Parts) {
3430 if (!N.getNode()->hasOneUse())
3433 unsigned Opc = N.getOpcode();
3434 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
3437 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3442 switch (N1C->getZExtValue()) {
3445 case 0xFF: Num = 0; break;
3446 case 0xFF00: Num = 1; break;
3447 case 0xFF0000: Num = 2; break;
3448 case 0xFF000000: Num = 3; break;
3451 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
3452 SDValue N0 = N.getOperand(0);
3453 if (Opc == ISD::AND) {
3454 if (Num == 0 || Num == 2) {
3456 // (x >> 8) & 0xff0000
3457 if (N0.getOpcode() != ISD::SRL)
3459 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3460 if (!C || C->getZExtValue() != 8)
3463 // (x << 8) & 0xff00
3464 // (x << 8) & 0xff000000
3465 if (N0.getOpcode() != ISD::SHL)
3467 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3468 if (!C || C->getZExtValue() != 8)
3471 } else if (Opc == ISD::SHL) {
3473 // (x & 0xff0000) << 8
3474 if (Num != 0 && Num != 2)
3476 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3477 if (!C || C->getZExtValue() != 8)
3479 } else { // Opc == ISD::SRL
3480 // (x & 0xff00) >> 8
3481 // (x & 0xff000000) >> 8
3482 if (Num != 1 && Num != 3)
3484 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3485 if (!C || C->getZExtValue() != 8)
3492 Parts[Num] = N0.getOperand(0).getNode();
3496 /// Match a 32-bit packed halfword bswap. That is
3497 /// ((x & 0x000000ff) << 8) |
3498 /// ((x & 0x0000ff00) >> 8) |
3499 /// ((x & 0x00ff0000) << 8) |
3500 /// ((x & 0xff000000) >> 8)
3501 /// => (rotl (bswap x), 16)
3502 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
3503 if (!LegalOperations)
3506 EVT VT = N->getValueType(0);
3509 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3513 // (or (or (and), (and)), (or (and), (and)))
3514 // (or (or (or (and), (and)), (and)), (and))
3515 if (N0.getOpcode() != ISD::OR)
3517 SDValue N00 = N0.getOperand(0);
3518 SDValue N01 = N0.getOperand(1);
3519 SDNode *Parts[4] = {};
3521 if (N1.getOpcode() == ISD::OR &&
3522 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) {
3523 // (or (or (and), (and)), (or (and), (and)))
3524 SDValue N000 = N00.getOperand(0);
3525 if (!isBSwapHWordElement(N000, Parts))
3528 SDValue N001 = N00.getOperand(1);
3529 if (!isBSwapHWordElement(N001, Parts))
3531 SDValue N010 = N01.getOperand(0);
3532 if (!isBSwapHWordElement(N010, Parts))
3534 SDValue N011 = N01.getOperand(1);
3535 if (!isBSwapHWordElement(N011, Parts))
3538 // (or (or (or (and), (and)), (and)), (and))
3539 if (!isBSwapHWordElement(N1, Parts))
3541 if (!isBSwapHWordElement(N01, Parts))
3543 if (N00.getOpcode() != ISD::OR)
3545 SDValue N000 = N00.getOperand(0);
3546 if (!isBSwapHWordElement(N000, Parts))
3548 SDValue N001 = N00.getOperand(1);
3549 if (!isBSwapHWordElement(N001, Parts))
3553 // Make sure the parts are all coming from the same node.
3554 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
3558 SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT,
3559 SDValue(Parts[0], 0));
3561 // Result of the bswap should be rotated by 16. If it's not legal, then
3562 // do (x << 16) | (x >> 16).
3563 SDValue ShAmt = DAG.getConstant(16, DL, getShiftAmountTy(VT));
3564 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3565 return DAG.getNode(ISD::ROTL, DL, VT, BSwap, ShAmt);
3566 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3567 return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
3568 return DAG.getNode(ISD::OR, DL, VT,
3569 DAG.getNode(ISD::SHL, DL, VT, BSwap, ShAmt),
3570 DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt));
3573 /// This contains all DAGCombine rules which reduce two values combined by
3574 /// an Or operation to a single value \see visitANDLike().
3575 SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, SDNode *LocReference) {
3576 EVT VT = N1.getValueType();
3577 // fold (or x, undef) -> -1
3578 if (!LegalOperations &&
3579 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3580 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3581 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()),
3582 SDLoc(LocReference), VT);
3584 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3585 SDValue LL, LR, RL, RR, CC0, CC1;
3586 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3587 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3588 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3590 if (LR == RR && Op0 == Op1 && LL.getValueType().isInteger()) {
3591 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3592 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3593 if (isNullConstant(LR) && (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3594 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(LR),
3595 LR.getValueType(), LL, RL);
3596 AddToWorklist(ORNode.getNode());
3597 return DAG.getSetCC(SDLoc(LocReference), VT, ORNode, LR, Op1);
3599 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3600 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3601 if (isAllOnesConstant(LR) && (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3602 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(LR),
3603 LR.getValueType(), LL, RL);
3604 AddToWorklist(ANDNode.getNode());
3605 return DAG.getSetCC(SDLoc(LocReference), VT, ANDNode, LR, Op1);
3608 // canonicalize equivalent to ll == rl
3609 if (LL == RR && LR == RL) {
3610 Op1 = ISD::getSetCCSwappedOperands(Op1);
3613 if (LL == RL && LR == RR) {
3614 bool isInteger = LL.getValueType().isInteger();
3615 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3616 if (Result != ISD::SETCC_INVALID &&
3617 (!LegalOperations ||
3618 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
3619 TLI.isOperationLegal(ISD::SETCC, LL.getValueType())))) {
3620 EVT CCVT = getSetCCResultType(LL.getValueType());
3621 if (N0.getValueType() == CCVT ||
3622 (!LegalOperations && N0.getValueType() == MVT::i1))
3623 return DAG.getSetCC(SDLoc(LocReference), N0.getValueType(),
3629 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3630 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
3631 // Don't increase # computations.
3632 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3633 // We can only do this xform if we know that bits from X that are set in C2
3634 // but not in C1 are already zero. Likewise for Y.
3635 if (const ConstantSDNode *N0O1C =
3636 getAsNonOpaqueConstant(N0.getOperand(1))) {
3637 if (const ConstantSDNode *N1O1C =
3638 getAsNonOpaqueConstant(N1.getOperand(1))) {
3639 // We can only do this xform if we know that bits from X that are set in
3640 // C2 but not in C1 are already zero. Likewise for Y.
3641 const APInt &LHSMask = N0O1C->getAPIntValue();
3642 const APInt &RHSMask = N1O1C->getAPIntValue();
3644 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3645 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3646 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3647 N0.getOperand(0), N1.getOperand(0));
3648 SDLoc DL(LocReference);
3649 return DAG.getNode(ISD::AND, DL, VT, X,
3650 DAG.getConstant(LHSMask | RHSMask, DL, VT));
3656 // (or (and X, M), (and X, N)) -> (and X, (or M, N))
3657 if (N0.getOpcode() == ISD::AND &&
3658 N1.getOpcode() == ISD::AND &&
3659 N0.getOperand(0) == N1.getOperand(0) &&
3660 // Don't increase # computations.
3661 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3662 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3663 N0.getOperand(1), N1.getOperand(1));
3664 return DAG.getNode(ISD::AND, SDLoc(LocReference), VT, N0.getOperand(0), X);
3670 SDValue DAGCombiner::visitOR(SDNode *N) {
3671 SDValue N0 = N->getOperand(0);
3672 SDValue N1 = N->getOperand(1);
3673 EVT VT = N1.getValueType();
3676 if (VT.isVector()) {
3677 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3680 // fold (or x, 0) -> x, vector edition
3681 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3683 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3686 // fold (or x, -1) -> -1, vector edition
3687 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3688 // do not return N0, because undef node may exist in N0
3689 return DAG.getConstant(
3690 APInt::getAllOnesValue(
3691 N0.getValueType().getScalarType().getSizeInBits()),
3692 SDLoc(N), N0.getValueType());
3693 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3694 // do not return N1, because undef node may exist in N1
3695 return DAG.getConstant(
3696 APInt::getAllOnesValue(
3697 N1.getValueType().getScalarType().getSizeInBits()),
3698 SDLoc(N), N1.getValueType());
3700 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
3701 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
3702 // Do this only if the resulting shuffle is legal.
3703 if (isa<ShuffleVectorSDNode>(N0) &&
3704 isa<ShuffleVectorSDNode>(N1) &&
3705 // Avoid folding a node with illegal type.
3706 TLI.isTypeLegal(VT) &&
3707 N0->getOperand(1) == N1->getOperand(1) &&
3708 ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode())) {
3709 bool CanFold = true;
3710 unsigned NumElts = VT.getVectorNumElements();
3711 const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
3712 const ShuffleVectorSDNode *SV1 = cast<ShuffleVectorSDNode>(N1);
3713 // We construct two shuffle masks:
3714 // - Mask1 is a shuffle mask for a shuffle with N0 as the first operand
3715 // and N1 as the second operand.
3716 // - Mask2 is a shuffle mask for a shuffle with N1 as the first operand
3717 // and N0 as the second operand.
3718 // We do this because OR is commutable and therefore there might be
3719 // two ways to fold this node into a shuffle.
3720 SmallVector<int,4> Mask1;
3721 SmallVector<int,4> Mask2;
3723 for (unsigned i = 0; i != NumElts && CanFold; ++i) {
3724 int M0 = SV0->getMaskElt(i);
3725 int M1 = SV1->getMaskElt(i);
3727 // Both shuffle indexes are undef. Propagate Undef.
3728 if (M0 < 0 && M1 < 0) {
3729 Mask1.push_back(M0);
3730 Mask2.push_back(M0);
3734 if (M0 < 0 || M1 < 0 ||
3735 (M0 < (int)NumElts && M1 < (int)NumElts) ||
3736 (M0 >= (int)NumElts && M1 >= (int)NumElts)) {
3741 Mask1.push_back(M0 < (int)NumElts ? M0 : M1 + NumElts);
3742 Mask2.push_back(M1 < (int)NumElts ? M1 : M0 + NumElts);
3746 // Fold this sequence only if the resulting shuffle is 'legal'.
3747 if (TLI.isShuffleMaskLegal(Mask1, VT))
3748 return DAG.getVectorShuffle(VT, SDLoc(N), N0->getOperand(0),
3749 N1->getOperand(0), &Mask1[0]);
3750 if (TLI.isShuffleMaskLegal(Mask2, VT))
3751 return DAG.getVectorShuffle(VT, SDLoc(N), N1->getOperand(0),
3752 N0->getOperand(0), &Mask2[0]);
3757 // fold (or c1, c2) -> c1|c2
3758 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
3759 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3760 if (N0C && N1C && !N1C->isOpaque())
3761 return DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N), VT, N0C, N1C);
3762 // canonicalize constant to RHS
3763 if (isConstantIntBuildVectorOrConstantInt(N0) &&
3764 !isConstantIntBuildVectorOrConstantInt(N1))
3765 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
3766 // fold (or x, 0) -> x
3767 if (isNullConstant(N1))
3769 // fold (or x, -1) -> -1
3770 if (isAllOnesConstant(N1))
3772 // fold (or x, c) -> c iff (x & ~c) == 0
3773 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3776 if (SDValue Combined = visitORLike(N0, N1, N))
3779 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3780 if (SDValue BSwap = MatchBSwapHWord(N, N0, N1))
3782 if (SDValue BSwap = MatchBSwapHWordLow(N, N0, N1))
3786 if (SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1))
3788 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3789 // iff (c1 & c2) == 0.
3790 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3791 isa<ConstantSDNode>(N0.getOperand(1))) {
3792 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3793 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) {
3794 if (SDValue COR = DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N1), VT,
3797 ISD::AND, SDLoc(N), VT,
3798 DAG.getNode(ISD::OR, SDLoc(N0), VT, N0.getOperand(0), N1), COR);
3802 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3803 if (N0.getOpcode() == N1.getOpcode())
3804 if (SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N))
3807 // See if this is some rotate idiom.
3808 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
3809 return SDValue(Rot, 0);
3811 // Simplify the operands using demanded-bits information.
3812 if (!VT.isVector() &&
3813 SimplifyDemandedBits(SDValue(N, 0)))
3814 return SDValue(N, 0);
3819 /// Match "(X shl/srl V1) & V2" where V2 may not be present.
3820 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3821 if (Op.getOpcode() == ISD::AND) {
3822 if (isConstantIntBuildVectorOrConstantInt(Op.getOperand(1))) {
3823 Mask = Op.getOperand(1);
3824 Op = Op.getOperand(0);
3830 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3838 // Return true if we can prove that, whenever Neg and Pos are both in the
3839 // range [0, EltSize), Neg == (Pos == 0 ? 0 : EltSize - Pos). This means that
3840 // for two opposing shifts shift1 and shift2 and a value X with OpBits bits:
3842 // (or (shift1 X, Neg), (shift2 X, Pos))
3844 // reduces to a rotate in direction shift2 by Pos or (equivalently) a rotate
3845 // in direction shift1 by Neg. The range [0, EltSize) means that we only need
3846 // to consider shift amounts with defined behavior.
3847 static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned EltSize) {
3848 // If EltSize is a power of 2 then:
3850 // (a) (Pos == 0 ? 0 : EltSize - Pos) == (EltSize - Pos) & (EltSize - 1)
3851 // (b) Neg == Neg & (EltSize - 1) whenever Neg is in [0, EltSize).
3853 // So if EltSize is a power of 2 and Neg is (and Neg', EltSize-1), we check
3854 // for the stronger condition:
3856 // Neg & (EltSize - 1) == (EltSize - Pos) & (EltSize - 1) [A]
3858 // for all Neg and Pos. Since Neg & (EltSize - 1) == Neg' & (EltSize - 1)
3859 // we can just replace Neg with Neg' for the rest of the function.
3861 // In other cases we check for the even stronger condition:
3863 // Neg == EltSize - Pos [B]
3865 // for all Neg and Pos. Note that the (or ...) then invokes undefined
3866 // behavior if Pos == 0 (and consequently Neg == EltSize).
3868 // We could actually use [A] whenever EltSize is a power of 2, but the
3869 // only extra cases that it would match are those uninteresting ones
3870 // where Neg and Pos are never in range at the same time. E.g. for
3871 // EltSize == 32, using [A] would allow a Neg of the form (sub 64, Pos)
3872 // as well as (sub 32, Pos), but:
3874 // (or (shift1 X, (sub 64, Pos)), (shift2 X, Pos))
3876 // always invokes undefined behavior for 32-bit X.
3878 // Below, Mask == EltSize - 1 when using [A] and is all-ones otherwise.
3879 unsigned MaskLoBits = 0;
3880 if (Neg.getOpcode() == ISD::AND && isPowerOf2_64(EltSize)) {
3881 if (ConstantSDNode *NegC = isConstOrConstSplat(Neg.getOperand(1))) {
3882 if (NegC->getAPIntValue() == EltSize - 1) {
3883 Neg = Neg.getOperand(0);
3884 MaskLoBits = Log2_64(EltSize);
3889 // Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1.
3890 if (Neg.getOpcode() != ISD::SUB)
3892 ConstantSDNode *NegC = isConstOrConstSplat(Neg.getOperand(0));
3895 SDValue NegOp1 = Neg.getOperand(1);
3897 // On the RHS of [A], if Pos is Pos' & (EltSize - 1), just replace Pos with
3898 // Pos'. The truncation is redundant for the purpose of the equality.
3899 if (MaskLoBits && Pos.getOpcode() == ISD::AND)
3900 if (ConstantSDNode *PosC = isConstOrConstSplat(Pos.getOperand(1)))
3901 if (PosC->getAPIntValue() == EltSize - 1)
3902 Pos = Pos.getOperand(0);
3904 // The condition we need is now:
3906 // (NegC - NegOp1) & Mask == (EltSize - Pos) & Mask
3908 // If NegOp1 == Pos then we need:
3910 // EltSize & Mask == NegC & Mask
3912 // (because "x & Mask" is a truncation and distributes through subtraction).
3915 Width = NegC->getAPIntValue();
3917 // Check for cases where Pos has the form (add NegOp1, PosC) for some PosC.
3918 // Then the condition we want to prove becomes:
3920 // (NegC - NegOp1) & Mask == (EltSize - (NegOp1 + PosC)) & Mask
3922 // which, again because "x & Mask" is a truncation, becomes:
3924 // NegC & Mask == (EltSize - PosC) & Mask
3925 // EltSize & Mask == (NegC + PosC) & Mask
3926 else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) {
3927 if (ConstantSDNode *PosC = isConstOrConstSplat(Pos.getOperand(1)))
3928 Width = PosC->getAPIntValue() + NegC->getAPIntValue();
3934 // Now we just need to check that EltSize & Mask == Width & Mask.
3936 // EltSize & Mask is 0 since Mask is EltSize - 1.
3937 return Width.getLoBits(MaskLoBits) == 0;
3938 return Width == EltSize;
3941 // A subroutine of MatchRotate used once we have found an OR of two opposite
3942 // shifts of Shifted. If Neg == <operand size> - Pos then the OR reduces
3943 // to both (PosOpcode Shifted, Pos) and (NegOpcode Shifted, Neg), with the
3944 // former being preferred if supported. InnerPos and InnerNeg are Pos and
3945 // Neg with outer conversions stripped away.
3946 SDNode *DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
3947 SDValue Neg, SDValue InnerPos,
3948 SDValue InnerNeg, unsigned PosOpcode,
3949 unsigned NegOpcode, SDLoc DL) {
3950 // fold (or (shl x, (*ext y)),
3951 // (srl x, (*ext (sub 32, y)))) ->
3952 // (rotl x, y) or (rotr x, (sub 32, y))
3954 // fold (or (shl x, (*ext (sub 32, y))),
3955 // (srl x, (*ext y))) ->
3956 // (rotr x, y) or (rotl x, (sub 32, y))
3957 EVT VT = Shifted.getValueType();
3958 if (matchRotateSub(InnerPos, InnerNeg, VT.getScalarSizeInBits())) {
3959 bool HasPos = TLI.isOperationLegalOrCustom(PosOpcode, VT);
3960 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted,
3961 HasPos ? Pos : Neg).getNode();
3967 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3968 // idioms for rotate, and if the target supports rotation instructions, generate
3970 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) {
3971 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3972 EVT VT = LHS.getValueType();
3973 if (!TLI.isTypeLegal(VT)) return nullptr;
3975 // The target must have at least one rotate flavor.
3976 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3977 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3978 if (!HasROTL && !HasROTR) return nullptr;
3980 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3981 SDValue LHSShift; // The shift.
3982 SDValue LHSMask; // AND value if any.
3983 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3984 return nullptr; // Not part of a rotate.
3986 SDValue RHSShift; // The shift.
3987 SDValue RHSMask; // AND value if any.
3988 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3989 return nullptr; // Not part of a rotate.
3991 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3992 return nullptr; // Not shifting the same value.
3994 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3995 return nullptr; // Shifts must disagree.
3997 // Canonicalize shl to left side in a shl/srl pair.
3998 if (RHSShift.getOpcode() == ISD::SHL) {
3999 std::swap(LHS, RHS);
4000 std::swap(LHSShift, RHSShift);
4001 std::swap(LHSMask, RHSMask);
4004 unsigned EltSizeInBits = VT.getScalarSizeInBits();
4005 SDValue LHSShiftArg = LHSShift.getOperand(0);
4006 SDValue LHSShiftAmt = LHSShift.getOperand(1);
4007 SDValue RHSShiftArg = RHSShift.getOperand(0);
4008 SDValue RHSShiftAmt = RHSShift.getOperand(1);
4010 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
4011 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
4012 if (isConstOrConstSplat(LHSShiftAmt) && isConstOrConstSplat(RHSShiftAmt)) {
4013 uint64_t LShVal = isConstOrConstSplat(LHSShiftAmt)->getZExtValue();
4014 uint64_t RShVal = isConstOrConstSplat(RHSShiftAmt)->getZExtValue();
4015 if ((LShVal + RShVal) != EltSizeInBits)
4018 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
4019 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
4021 // If there is an AND of either shifted operand, apply it to the result.
4022 if (LHSMask.getNode() || RHSMask.getNode()) {
4023 APInt AllBits = APInt::getAllOnesValue(EltSizeInBits);
4024 SDValue Mask = DAG.getConstant(AllBits, DL, VT);
4026 if (LHSMask.getNode()) {
4027 APInt RHSBits = APInt::getLowBitsSet(EltSizeInBits, LShVal);
4028 Mask = DAG.getNode(ISD::AND, DL, VT, Mask,
4029 DAG.getNode(ISD::OR, DL, VT, LHSMask,
4030 DAG.getConstant(RHSBits, DL, VT)));
4032 if (RHSMask.getNode()) {
4033 APInt LHSBits = APInt::getHighBitsSet(EltSizeInBits, RShVal);
4034 Mask = DAG.getNode(ISD::AND, DL, VT, Mask,
4035 DAG.getNode(ISD::OR, DL, VT, RHSMask,
4036 DAG.getConstant(LHSBits, DL, VT)));
4039 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, Mask);
4042 return Rot.getNode();
4045 // If there is a mask here, and we have a variable shift, we can't be sure
4046 // that we're masking out the right stuff.
4047 if (LHSMask.getNode() || RHSMask.getNode())
4050 // If the shift amount is sign/zext/any-extended just peel it off.
4051 SDValue LExtOp0 = LHSShiftAmt;
4052 SDValue RExtOp0 = RHSShiftAmt;
4053 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
4054 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
4055 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
4056 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
4057 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
4058 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
4059 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
4060 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
4061 LExtOp0 = LHSShiftAmt.getOperand(0);
4062 RExtOp0 = RHSShiftAmt.getOperand(0);
4065 SDNode *TryL = MatchRotatePosNeg(LHSShiftArg, LHSShiftAmt, RHSShiftAmt,
4066 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
4070 SDNode *TryR = MatchRotatePosNeg(RHSShiftArg, RHSShiftAmt, LHSShiftAmt,
4071 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
4078 SDValue DAGCombiner::visitXOR(SDNode *N) {
4079 SDValue N0 = N->getOperand(0);
4080 SDValue N1 = N->getOperand(1);
4081 EVT VT = N0.getValueType();
4084 if (VT.isVector()) {
4085 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4088 // fold (xor x, 0) -> x, vector edition
4089 if (ISD::isBuildVectorAllZeros(N0.getNode()))
4091 if (ISD::isBuildVectorAllZeros(N1.getNode()))
4095 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
4096 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
4097 return DAG.getConstant(0, SDLoc(N), VT);
4098 // fold (xor x, undef) -> undef
4099 if (N0.getOpcode() == ISD::UNDEF)
4101 if (N1.getOpcode() == ISD::UNDEF)
4103 // fold (xor c1, c2) -> c1^c2
4104 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
4105 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
4107 return DAG.FoldConstantArithmetic(ISD::XOR, SDLoc(N), VT, N0C, N1C);
4108 // canonicalize constant to RHS
4109 if (isConstantIntBuildVectorOrConstantInt(N0) &&
4110 !isConstantIntBuildVectorOrConstantInt(N1))
4111 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
4112 // fold (xor x, 0) -> x
4113 if (isNullConstant(N1))
4116 if (SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1))
4119 // fold !(x cc y) -> (x !cc y)
4120 SDValue LHS, RHS, CC;
4121 if (TLI.isConstTrueVal(N1.getNode()) && isSetCCEquivalent(N0, LHS, RHS, CC)) {
4122 bool isInt = LHS.getValueType().isInteger();
4123 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
4126 if (!LegalOperations ||
4127 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) {
4128 switch (N0.getOpcode()) {
4130 llvm_unreachable("Unhandled SetCC Equivalent!");
4132 return DAG.getSetCC(SDLoc(N), VT, LHS, RHS, NotCC);
4133 case ISD::SELECT_CC:
4134 return DAG.getSelectCC(SDLoc(N), LHS, RHS, N0.getOperand(2),
4135 N0.getOperand(3), NotCC);
4140 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
4141 if (isOneConstant(N1) && N0.getOpcode() == ISD::ZERO_EXTEND &&
4142 N0.getNode()->hasOneUse() &&
4143 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
4144 SDValue V = N0.getOperand(0);
4146 V = DAG.getNode(ISD::XOR, DL, V.getValueType(), V,
4147 DAG.getConstant(1, DL, V.getValueType()));
4148 AddToWorklist(V.getNode());
4149 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, V);
4152 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
4153 if (isOneConstant(N1) && VT == MVT::i1 &&
4154 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
4155 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
4156 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
4157 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
4158 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
4159 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
4160 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
4161 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
4164 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
4165 if (isAllOnesConstant(N1) &&
4166 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
4167 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
4168 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
4169 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
4170 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
4171 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
4172 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
4173 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
4176 // fold (xor (and x, y), y) -> (and (not x), y)
4177 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
4178 N0->getOperand(1) == N1) {
4179 SDValue X = N0->getOperand(0);
4180 SDValue NotX = DAG.getNOT(SDLoc(X), X, VT);
4181 AddToWorklist(NotX.getNode());
4182 return DAG.getNode(ISD::AND, SDLoc(N), VT, NotX, N1);
4184 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
4185 if (N1C && N0.getOpcode() == ISD::XOR) {
4186 if (const ConstantSDNode *N00C = getAsNonOpaqueConstant(N0.getOperand(0))) {
4188 return DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1),
4189 DAG.getConstant(N1C->getAPIntValue() ^
4190 N00C->getAPIntValue(), DL, VT));
4192 if (const ConstantSDNode *N01C = getAsNonOpaqueConstant(N0.getOperand(1))) {
4194 return DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0),
4195 DAG.getConstant(N1C->getAPIntValue() ^
4196 N01C->getAPIntValue(), DL, VT));
4199 // fold (xor x, x) -> 0
4201 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
4203 // fold (xor (shl 1, x), -1) -> (rotl ~1, x)
4204 // Here is a concrete example of this equivalence:
4206 // i16 shl == 1 << 14 == 16384 == 0b0100000000000000
4207 // i16 xor == ~(1 << 14) == 49151 == 0b1011111111111111
4211 // i16 ~1 == 0b1111111111111110
4212 // i16 rol(~1, 14) == 0b1011111111111111
4214 // Some additional tips to help conceptualize this transform:
4215 // - Try to see the operation as placing a single zero in a value of all ones.
4216 // - There exists no value for x which would allow the result to contain zero.
4217 // - Values of x larger than the bitwidth are undefined and do not require a
4218 // consistent result.
4219 // - Pushing the zero left requires shifting one bits in from the right.
4220 // A rotate left of ~1 is a nice way of achieving the desired result.
4221 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT) && N0.getOpcode() == ISD::SHL
4222 && isAllOnesConstant(N1) && isOneConstant(N0.getOperand(0))) {
4224 return DAG.getNode(ISD::ROTL, DL, VT, DAG.getConstant(~1, DL, VT),
4228 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
4229 if (N0.getOpcode() == N1.getOpcode())
4230 if (SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N))
4233 // Simplify the expression using non-local knowledge.
4234 if (!VT.isVector() &&
4235 SimplifyDemandedBits(SDValue(N, 0)))
4236 return SDValue(N, 0);
4241 /// Handle transforms common to the three shifts, when the shift amount is a
4243 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, ConstantSDNode *Amt) {
4244 SDNode *LHS = N->getOperand(0).getNode();
4245 if (!LHS->hasOneUse()) return SDValue();
4247 // We want to pull some binops through shifts, so that we have (and (shift))
4248 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
4249 // thing happens with address calculations, so it's important to canonicalize
4251 bool HighBitSet = false; // Can we transform this if the high bit is set?
4253 switch (LHS->getOpcode()) {
4254 default: return SDValue();
4257 HighBitSet = false; // We can only transform sra if the high bit is clear.
4260 HighBitSet = true; // We can only transform sra if the high bit is set.
4263 if (N->getOpcode() != ISD::SHL)
4264 return SDValue(); // only shl(add) not sr[al](add).
4265 HighBitSet = false; // We can only transform sra if the high bit is clear.
4269 // We require the RHS of the binop to be a constant and not opaque as well.
4270 ConstantSDNode *BinOpCst = getAsNonOpaqueConstant(LHS->getOperand(1));
4271 if (!BinOpCst) return SDValue();
4273 // FIXME: disable this unless the input to the binop is a shift by a constant.
4274 // If it is not a shift, it pessimizes some common cases like:
4276 // void foo(int *X, int i) { X[i & 1235] = 1; }
4277 // int bar(int *X, int i) { return X[i & 255]; }
4278 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
4279 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
4280 BinOpLHSVal->getOpcode() != ISD::SRA &&
4281 BinOpLHSVal->getOpcode() != ISD::SRL) ||
4282 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
4285 EVT VT = N->getValueType(0);
4287 // If this is a signed shift right, and the high bit is modified by the
4288 // logical operation, do not perform the transformation. The highBitSet
4289 // boolean indicates the value of the high bit of the constant which would
4290 // cause it to be modified for this operation.
4291 if (N->getOpcode() == ISD::SRA) {
4292 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
4293 if (BinOpRHSSignSet != HighBitSet)
4297 if (!TLI.isDesirableToCommuteWithShift(LHS))
4300 // Fold the constants, shifting the binop RHS by the shift amount.
4301 SDValue NewRHS = DAG.getNode(N->getOpcode(), SDLoc(LHS->getOperand(1)),
4303 LHS->getOperand(1), N->getOperand(1));
4304 assert(isa<ConstantSDNode>(NewRHS) && "Folding was not successful!");
4306 // Create the new shift.
4307 SDValue NewShift = DAG.getNode(N->getOpcode(),
4308 SDLoc(LHS->getOperand(0)),
4309 VT, LHS->getOperand(0), N->getOperand(1));
4311 // Create the new binop.
4312 return DAG.getNode(LHS->getOpcode(), SDLoc(N), VT, NewShift, NewRHS);
4315 SDValue DAGCombiner::distributeTruncateThroughAnd(SDNode *N) {
4316 assert(N->getOpcode() == ISD::TRUNCATE);
4317 assert(N->getOperand(0).getOpcode() == ISD::AND);
4319 // (truncate:TruncVT (and N00, N01C)) -> (and (truncate:TruncVT N00), TruncC)
4320 if (N->hasOneUse() && N->getOperand(0).hasOneUse()) {
4321 SDValue N01 = N->getOperand(0).getOperand(1);
4323 if (ConstantSDNode *N01C = isConstOrConstSplat(N01)) {
4324 if (!N01C->isOpaque()) {
4325 EVT TruncVT = N->getValueType(0);
4326 SDValue N00 = N->getOperand(0).getOperand(0);
4327 APInt TruncC = N01C->getAPIntValue();
4328 TruncC = TruncC.trunc(TruncVT.getScalarSizeInBits());
4331 return DAG.getNode(ISD::AND, DL, TruncVT,
4332 DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N00),
4333 DAG.getConstant(TruncC, DL, TruncVT));
4341 SDValue DAGCombiner::visitRotate(SDNode *N) {
4342 // fold (rot* x, (trunc (and y, c))) -> (rot* x, (and (trunc y), (trunc c))).
4343 if (N->getOperand(1).getOpcode() == ISD::TRUNCATE &&
4344 N->getOperand(1).getOperand(0).getOpcode() == ISD::AND) {
4345 SDValue NewOp1 = distributeTruncateThroughAnd(N->getOperand(1).getNode());
4346 if (NewOp1.getNode())
4347 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
4348 N->getOperand(0), NewOp1);
4353 SDValue DAGCombiner::visitSHL(SDNode *N) {
4354 SDValue N0 = N->getOperand(0);
4355 SDValue N1 = N->getOperand(1);
4356 EVT VT = N0.getValueType();
4357 unsigned OpSizeInBits = VT.getScalarSizeInBits();
4360 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4361 if (VT.isVector()) {
4362 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4365 BuildVectorSDNode *N1CV = dyn_cast<BuildVectorSDNode>(N1);
4366 // If setcc produces all-one true value then:
4367 // (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV)
4368 if (N1CV && N1CV->isConstant()) {
4369 if (N0.getOpcode() == ISD::AND) {
4370 SDValue N00 = N0->getOperand(0);
4371 SDValue N01 = N0->getOperand(1);
4372 BuildVectorSDNode *N01CV = dyn_cast<BuildVectorSDNode>(N01);
4374 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
4375 TLI.getBooleanContents(N00.getOperand(0).getValueType()) ==
4376 TargetLowering::ZeroOrNegativeOneBooleanContent) {
4377 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT,
4379 return DAG.getNode(ISD::AND, SDLoc(N), VT, N00, C);
4382 N1C = isConstOrConstSplat(N1);
4387 // fold (shl c1, c2) -> c1<<c2
4388 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
4389 if (N0C && N1C && !N1C->isOpaque())
4390 return DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT, N0C, N1C);
4391 // fold (shl 0, x) -> 0
4392 if (isNullConstant(N0))
4394 // fold (shl x, c >= size(x)) -> undef
4395 if (N1C && N1C->getAPIntValue().uge(OpSizeInBits))
4396 return DAG.getUNDEF(VT);
4397 // fold (shl x, 0) -> x
4398 if (N1C && N1C->isNullValue())
4400 // fold (shl undef, x) -> 0
4401 if (N0.getOpcode() == ISD::UNDEF)
4402 return DAG.getConstant(0, SDLoc(N), VT);
4403 // if (shl x, c) is known to be zero, return 0
4404 if (DAG.MaskedValueIsZero(SDValue(N, 0),
4405 APInt::getAllOnesValue(OpSizeInBits)))
4406 return DAG.getConstant(0, SDLoc(N), VT);
4407 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
4408 if (N1.getOpcode() == ISD::TRUNCATE &&
4409 N1.getOperand(0).getOpcode() == ISD::AND) {
4410 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4411 if (NewOp1.getNode())
4412 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, NewOp1);
4415 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4416 return SDValue(N, 0);
4418 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
4419 if (N1C && N0.getOpcode() == ISD::SHL) {
4420 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4421 uint64_t c1 = N0C1->getZExtValue();
4422 uint64_t c2 = N1C->getZExtValue();
4424 if (c1 + c2 >= OpSizeInBits)
4425 return DAG.getConstant(0, DL, VT);
4426 return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
4427 DAG.getConstant(c1 + c2, DL, N1.getValueType()));
4431 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
4432 // For this to be valid, the second form must not preserve any of the bits
4433 // that are shifted out by the inner shift in the first form. This means
4434 // the outer shift size must be >= the number of bits added by the ext.
4435 // As a corollary, we don't care what kind of ext it is.
4436 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
4437 N0.getOpcode() == ISD::ANY_EXTEND ||
4438 N0.getOpcode() == ISD::SIGN_EXTEND) &&
4439 N0.getOperand(0).getOpcode() == ISD::SHL) {
4440 SDValue N0Op0 = N0.getOperand(0);
4441 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
4442 uint64_t c1 = N0Op0C1->getZExtValue();
4443 uint64_t c2 = N1C->getZExtValue();
4444 EVT InnerShiftVT = N0Op0.getValueType();
4445 uint64_t InnerShiftSize = InnerShiftVT.getScalarSizeInBits();
4446 if (c2 >= OpSizeInBits - InnerShiftSize) {
4448 if (c1 + c2 >= OpSizeInBits)
4449 return DAG.getConstant(0, DL, VT);
4450 return DAG.getNode(ISD::SHL, DL, VT,
4451 DAG.getNode(N0.getOpcode(), DL, VT,
4452 N0Op0->getOperand(0)),
4453 DAG.getConstant(c1 + c2, DL, N1.getValueType()));
4458 // fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
4459 // Only fold this if the inner zext has no other uses to avoid increasing
4460 // the total number of instructions.
4461 if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
4462 N0.getOperand(0).getOpcode() == ISD::SRL) {
4463 SDValue N0Op0 = N0.getOperand(0);
4464 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
4465 uint64_t c1 = N0Op0C1->getZExtValue();
4466 if (c1 < VT.getScalarSizeInBits()) {
4467 uint64_t c2 = N1C->getZExtValue();
4469 SDValue NewOp0 = N0.getOperand(0);
4470 EVT CountVT = NewOp0.getOperand(1).getValueType();
4472 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, NewOp0.getValueType(),
4474 DAG.getConstant(c2, DL, CountVT));
4475 AddToWorklist(NewSHL.getNode());
4476 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
4482 // fold (shl (sr[la] exact X, C1), C2) -> (shl X, (C2-C1)) if C1 <= C2
4483 // fold (shl (sr[la] exact X, C1), C2) -> (sr[la] X, (C2-C1)) if C1 > C2
4484 if (N1C && (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) &&
4485 cast<BinaryWithFlagsSDNode>(N0)->Flags.hasExact()) {
4486 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4487 uint64_t C1 = N0C1->getZExtValue();
4488 uint64_t C2 = N1C->getZExtValue();
4491 return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
4492 DAG.getConstant(C2 - C1, DL, N1.getValueType()));
4493 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0),
4494 DAG.getConstant(C1 - C2, DL, N1.getValueType()));
4498 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
4499 // (and (srl x, (sub c1, c2), MASK)
4500 // Only fold this if the inner shift has no other uses -- if it does, folding
4501 // this will increase the total number of instructions.
4502 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4503 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4504 uint64_t c1 = N0C1->getZExtValue();
4505 if (c1 < OpSizeInBits) {
4506 uint64_t c2 = N1C->getZExtValue();
4507 APInt Mask = APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - c1);
4510 Mask = Mask.shl(c2 - c1);
4512 Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
4513 DAG.getConstant(c2 - c1, DL, N1.getValueType()));
4515 Mask = Mask.lshr(c1 - c2);
4517 Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4518 DAG.getConstant(c1 - c2, DL, N1.getValueType()));
4521 return DAG.getNode(ISD::AND, DL, VT, Shift,
4522 DAG.getConstant(Mask, DL, VT));
4526 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
4527 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
4528 unsigned BitSize = VT.getScalarSizeInBits();
4530 SDValue HiBitsMask =
4531 DAG.getConstant(APInt::getHighBitsSet(BitSize,
4532 BitSize - N1C->getZExtValue()),
4534 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0),
4538 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)
4539 // Variant of version done on multiply, except mul by a power of 2 is turned
4542 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
4543 (isa<ConstantSDNode>(N0.getOperand(1)) ||
4544 isConstantSplatVector(N0.getOperand(1).getNode(), Val))) {
4545 SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1);
4546 SDValue Shl1 = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);
4547 return DAG.getNode(ISD::ADD, SDLoc(N), VT, Shl0, Shl1);
4550 // fold (shl (mul x, c1), c2) -> (mul x, c1 << c2)
4551 if (N1C && N0.getOpcode() == ISD::MUL && N0.getNode()->hasOneUse()) {
4552 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4553 if (SDValue Folded =
4554 DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N1), VT, N0C1, N1C))
4555 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), Folded);
4559 if (N1C && !N1C->isOpaque())
4560 if (SDValue NewSHL = visitShiftByConstant(N, N1C))
4566 SDValue DAGCombiner::visitSRA(SDNode *N) {
4567 SDValue N0 = N->getOperand(0);
4568 SDValue N1 = N->getOperand(1);
4569 EVT VT = N0.getValueType();
4570 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
4573 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4574 if (VT.isVector()) {
4575 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4578 N1C = isConstOrConstSplat(N1);
4581 // fold (sra c1, c2) -> (sra c1, c2)
4582 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
4583 if (N0C && N1C && !N1C->isOpaque())
4584 return DAG.FoldConstantArithmetic(ISD::SRA, SDLoc(N), VT, N0C, N1C);
4585 // fold (sra 0, x) -> 0
4586 if (isNullConstant(N0))
4588 // fold (sra -1, x) -> -1
4589 if (isAllOnesConstant(N0))
4591 // fold (sra x, (setge c, size(x))) -> undef
4592 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4593 return DAG.getUNDEF(VT);
4594 // fold (sra x, 0) -> x
4595 if (N1C && N1C->isNullValue())
4597 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
4599 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
4600 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
4601 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
4603 ExtVT = EVT::getVectorVT(*DAG.getContext(),
4604 ExtVT, VT.getVectorNumElements());
4605 if ((!LegalOperations ||
4606 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
4607 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
4608 N0.getOperand(0), DAG.getValueType(ExtVT));
4611 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
4612 if (N1C && N0.getOpcode() == ISD::SRA) {
4613 if (ConstantSDNode *C1 = isConstOrConstSplat(N0.getOperand(1))) {
4614 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
4615 if (Sum >= OpSizeInBits)
4616 Sum = OpSizeInBits - 1;
4618 return DAG.getNode(ISD::SRA, DL, VT, N0.getOperand(0),
4619 DAG.getConstant(Sum, DL, N1.getValueType()));
4623 // fold (sra (shl X, m), (sub result_size, n))
4624 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
4625 // result_size - n != m.
4626 // If truncate is free for the target sext(shl) is likely to result in better
4628 if (N0.getOpcode() == ISD::SHL && N1C) {
4629 // Get the two constanst of the shifts, CN0 = m, CN = n.
4630 const ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1));
4632 LLVMContext &Ctx = *DAG.getContext();
4633 // Determine what the truncate's result bitsize and type would be.
4634 EVT TruncVT = EVT::getIntegerVT(Ctx, OpSizeInBits - N1C->getZExtValue());
4637 TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorNumElements());
4639 // Determine the residual right-shift amount.
4640 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
4642 // If the shift is not a no-op (in which case this should be just a sign
4643 // extend already), the truncated to type is legal, sign_extend is legal
4644 // on that type, and the truncate to that type is both legal and free,
4645 // perform the transform.
4646 if ((ShiftAmt > 0) &&
4647 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
4648 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
4649 TLI.isTruncateFree(VT, TruncVT)) {
4652 SDValue Amt = DAG.getConstant(ShiftAmt, DL,
4653 getShiftAmountTy(N0.getOperand(0).getValueType()));
4654 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT,
4655 N0.getOperand(0), Amt);
4656 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, TruncVT,
4658 return DAG.getNode(ISD::SIGN_EXTEND, DL,
4659 N->getValueType(0), Trunc);
4664 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
4665 if (N1.getOpcode() == ISD::TRUNCATE &&
4666 N1.getOperand(0).getOpcode() == ISD::AND) {
4667 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4668 if (NewOp1.getNode())
4669 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1);
4672 // fold (sra (trunc (srl x, c1)), c2) -> (trunc (sra x, c1 + c2))
4673 // if c1 is equal to the number of bits the trunc removes
4674 if (N0.getOpcode() == ISD::TRUNCATE &&
4675 (N0.getOperand(0).getOpcode() == ISD::SRL ||
4676 N0.getOperand(0).getOpcode() == ISD::SRA) &&
4677 N0.getOperand(0).hasOneUse() &&
4678 N0.getOperand(0).getOperand(1).hasOneUse() &&
4680 SDValue N0Op0 = N0.getOperand(0);
4681 if (ConstantSDNode *LargeShift = isConstOrConstSplat(N0Op0.getOperand(1))) {
4682 unsigned LargeShiftVal = LargeShift->getZExtValue();
4683 EVT LargeVT = N0Op0.getValueType();
4685 if (LargeVT.getScalarSizeInBits() - OpSizeInBits == LargeShiftVal) {
4688 DAG.getConstant(LargeShiftVal + N1C->getZExtValue(), DL,
4689 getShiftAmountTy(N0Op0.getOperand(0).getValueType()));
4690 SDValue SRA = DAG.getNode(ISD::SRA, DL, LargeVT,
4691 N0Op0.getOperand(0), Amt);
4692 return DAG.getNode(ISD::TRUNCATE, DL, VT, SRA);
4697 // Simplify, based on bits shifted out of the LHS.
4698 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4699 return SDValue(N, 0);
4702 // If the sign bit is known to be zero, switch this to a SRL.
4703 if (DAG.SignBitIsZero(N0))
4704 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
4706 if (N1C && !N1C->isOpaque())
4707 if (SDValue NewSRA = visitShiftByConstant(N, N1C))
4713 SDValue DAGCombiner::visitSRL(SDNode *N) {
4714 SDValue N0 = N->getOperand(0);
4715 SDValue N1 = N->getOperand(1);
4716 EVT VT = N0.getValueType();
4717 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
4720 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4721 if (VT.isVector()) {
4722 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4725 N1C = isConstOrConstSplat(N1);
4728 // fold (srl c1, c2) -> c1 >>u c2
4729 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
4730 if (N0C && N1C && !N1C->isOpaque())
4731 return DAG.FoldConstantArithmetic(ISD::SRL, SDLoc(N), VT, N0C, N1C);
4732 // fold (srl 0, x) -> 0
4733 if (isNullConstant(N0))
4735 // fold (srl x, c >= size(x)) -> undef
4736 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4737 return DAG.getUNDEF(VT);
4738 // fold (srl x, 0) -> x
4739 if (N1C && N1C->isNullValue())
4741 // if (srl x, c) is known to be zero, return 0
4742 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
4743 APInt::getAllOnesValue(OpSizeInBits)))
4744 return DAG.getConstant(0, SDLoc(N), VT);
4746 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
4747 if (N1C && N0.getOpcode() == ISD::SRL) {
4748 if (ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1))) {
4749 uint64_t c1 = N01C->getZExtValue();
4750 uint64_t c2 = N1C->getZExtValue();
4752 if (c1 + c2 >= OpSizeInBits)
4753 return DAG.getConstant(0, DL, VT);
4754 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4755 DAG.getConstant(c1 + c2, DL, N1.getValueType()));
4759 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
4760 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
4761 N0.getOperand(0).getOpcode() == ISD::SRL &&
4762 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
4764 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
4765 uint64_t c2 = N1C->getZExtValue();
4766 EVT InnerShiftVT = N0.getOperand(0).getValueType();
4767 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
4768 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
4769 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
4770 if (c1 + OpSizeInBits == InnerShiftSize) {
4772 if (c1 + c2 >= InnerShiftSize)
4773 return DAG.getConstant(0, DL, VT);
4774 return DAG.getNode(ISD::TRUNCATE, DL, VT,
4775 DAG.getNode(ISD::SRL, DL, InnerShiftVT,
4776 N0.getOperand(0)->getOperand(0),
4777 DAG.getConstant(c1 + c2, DL,
4782 // fold (srl (shl x, c), c) -> (and x, cst2)
4783 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1) {
4784 unsigned BitSize = N0.getScalarValueSizeInBits();
4785 if (BitSize <= 64) {
4786 uint64_t ShAmt = N1C->getZExtValue() + 64 - BitSize;
4788 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0),
4789 DAG.getConstant(~0ULL >> ShAmt, DL, VT));
4793 // fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask)
4794 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
4795 // Shifting in all undef bits?
4796 EVT SmallVT = N0.getOperand(0).getValueType();
4797 unsigned BitSize = SmallVT.getScalarSizeInBits();
4798 if (N1C->getZExtValue() >= BitSize)
4799 return DAG.getUNDEF(VT);
4801 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
4802 uint64_t ShiftAmt = N1C->getZExtValue();
4804 SDValue SmallShift = DAG.getNode(ISD::SRL, DL0, SmallVT,
4806 DAG.getConstant(ShiftAmt, DL0,
4807 getShiftAmountTy(SmallVT)));
4808 AddToWorklist(SmallShift.getNode());
4809 APInt Mask = APInt::getAllOnesValue(OpSizeInBits).lshr(ShiftAmt);
4811 return DAG.getNode(ISD::AND, DL, VT,
4812 DAG.getNode(ISD::ANY_EXTEND, DL, VT, SmallShift),
4813 DAG.getConstant(Mask, DL, VT));
4817 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
4818 // bit, which is unmodified by sra.
4819 if (N1C && N1C->getZExtValue() + 1 == OpSizeInBits) {
4820 if (N0.getOpcode() == ISD::SRA)
4821 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
4824 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
4825 if (N1C && N0.getOpcode() == ISD::CTLZ &&
4826 N1C->getAPIntValue() == Log2_32(OpSizeInBits)) {
4827 APInt KnownZero, KnownOne;
4828 DAG.computeKnownBits(N0.getOperand(0), KnownZero, KnownOne);
4830 // If any of the input bits are KnownOne, then the input couldn't be all
4831 // zeros, thus the result of the srl will always be zero.
4832 if (KnownOne.getBoolValue()) return DAG.getConstant(0, SDLoc(N0), VT);
4834 // If all of the bits input the to ctlz node are known to be zero, then
4835 // the result of the ctlz is "32" and the result of the shift is one.
4836 APInt UnknownBits = ~KnownZero;
4837 if (UnknownBits == 0) return DAG.getConstant(1, SDLoc(N0), VT);
4839 // Otherwise, check to see if there is exactly one bit input to the ctlz.
4840 if ((UnknownBits & (UnknownBits - 1)) == 0) {
4841 // Okay, we know that only that the single bit specified by UnknownBits
4842 // could be set on input to the CTLZ node. If this bit is set, the SRL
4843 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
4844 // to an SRL/XOR pair, which is likely to simplify more.
4845 unsigned ShAmt = UnknownBits.countTrailingZeros();
4846 SDValue Op = N0.getOperand(0);
4850 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
4851 DAG.getConstant(ShAmt, DL,
4852 getShiftAmountTy(Op.getValueType())));
4853 AddToWorklist(Op.getNode());
4857 return DAG.getNode(ISD::XOR, DL, VT,
4858 Op, DAG.getConstant(1, DL, VT));
4862 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
4863 if (N1.getOpcode() == ISD::TRUNCATE &&
4864 N1.getOperand(0).getOpcode() == ISD::AND) {
4865 if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode()))
4866 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1);
4869 // fold operands of srl based on knowledge that the low bits are not
4871 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4872 return SDValue(N, 0);
4874 if (N1C && !N1C->isOpaque())
4875 if (SDValue NewSRL = visitShiftByConstant(N, N1C))
4878 // Attempt to convert a srl of a load into a narrower zero-extending load.
4879 if (SDValue NarrowLoad = ReduceLoadWidth(N))
4882 // Here is a common situation. We want to optimize:
4885 // %b = and i32 %a, 2
4886 // %c = srl i32 %b, 1
4887 // brcond i32 %c ...
4893 // %c = setcc eq %b, 0
4896 // However when after the source operand of SRL is optimized into AND, the SRL
4897 // itself may not be optimized further. Look for it and add the BRCOND into
4899 if (N->hasOneUse()) {
4900 SDNode *Use = *N->use_begin();
4901 if (Use->getOpcode() == ISD::BRCOND)
4903 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
4904 // Also look pass the truncate.
4905 Use = *Use->use_begin();
4906 if (Use->getOpcode() == ISD::BRCOND)
4914 SDValue DAGCombiner::visitBSWAP(SDNode *N) {
4915 SDValue N0 = N->getOperand(0);
4916 EVT VT = N->getValueType(0);
4918 // fold (bswap c1) -> c2
4919 if (isConstantIntBuildVectorOrConstantInt(N0))
4920 return DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N0);
4921 // fold (bswap (bswap x)) -> x
4922 if (N0.getOpcode() == ISD::BSWAP)
4923 return N0->getOperand(0);
4927 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
4928 SDValue N0 = N->getOperand(0);
4929 EVT VT = N->getValueType(0);
4931 // fold (ctlz c1) -> c2
4932 if (isConstantIntBuildVectorOrConstantInt(N0))
4933 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
4937 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
4938 SDValue N0 = N->getOperand(0);
4939 EVT VT = N->getValueType(0);
4941 // fold (ctlz_zero_undef c1) -> c2
4942 if (isConstantIntBuildVectorOrConstantInt(N0))
4943 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4947 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
4948 SDValue N0 = N->getOperand(0);
4949 EVT VT = N->getValueType(0);
4951 // fold (cttz c1) -> c2
4952 if (isConstantIntBuildVectorOrConstantInt(N0))
4953 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0);
4957 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
4958 SDValue N0 = N->getOperand(0);
4959 EVT VT = N->getValueType(0);
4961 // fold (cttz_zero_undef c1) -> c2
4962 if (isConstantIntBuildVectorOrConstantInt(N0))
4963 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4967 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4968 SDValue N0 = N->getOperand(0);
4969 EVT VT = N->getValueType(0);
4971 // fold (ctpop c1) -> c2
4972 if (isConstantIntBuildVectorOrConstantInt(N0))
4973 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0);
4978 /// \brief Generate Min/Max node
4979 static SDValue combineMinNumMaxNum(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS,
4980 SDValue True, SDValue False,
4981 ISD::CondCode CC, const TargetLowering &TLI,
4982 SelectionDAG &DAG) {
4983 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
4993 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
4994 if (TLI.isOperationLegal(Opcode, VT))
4995 return DAG.getNode(Opcode, DL, VT, LHS, RHS);
5004 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
5005 if (TLI.isOperationLegal(Opcode, VT))
5006 return DAG.getNode(Opcode, DL, VT, LHS, RHS);
5014 SDValue DAGCombiner::visitSELECT(SDNode *N) {
5015 SDValue N0 = N->getOperand(0);
5016 SDValue N1 = N->getOperand(1);
5017 SDValue N2 = N->getOperand(2);
5018 EVT VT = N->getValueType(0);
5019 EVT VT0 = N0.getValueType();
5021 // fold (select C, X, X) -> X
5024 if (const ConstantSDNode *N0C = dyn_cast<const ConstantSDNode>(N0)) {
5025 // fold (select true, X, Y) -> X
5026 // fold (select false, X, Y) -> Y
5027 return !N0C->isNullValue() ? N1 : N2;
5029 // fold (select C, 1, X) -> (or C, X)
5030 if (VT == MVT::i1 && isOneConstant(N1))
5031 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
5032 // fold (select C, 0, 1) -> (xor C, 1)
5033 // We can't do this reliably if integer based booleans have different contents
5034 // to floating point based booleans. This is because we can't tell whether we
5035 // have an integer-based boolean or a floating-point-based boolean unless we
5036 // can find the SETCC that produced it and inspect its operands. This is
5037 // fairly easy if C is the SETCC node, but it can potentially be
5038 // undiscoverable (or not reasonably discoverable). For example, it could be
5039 // in another basic block or it could require searching a complicated
5041 if (VT.isInteger() &&
5042 (VT0 == MVT::i1 || (VT0.isInteger() &&
5043 TLI.getBooleanContents(false, false) ==
5044 TLI.getBooleanContents(false, true) &&
5045 TLI.getBooleanContents(false, false) ==
5046 TargetLowering::ZeroOrOneBooleanContent)) &&
5047 isNullConstant(N1) && isOneConstant(N2)) {
5051 return DAG.getNode(ISD::XOR, DL, VT0,
5052 N0, DAG.getConstant(1, DL, VT0));
5055 XORNode = DAG.getNode(ISD::XOR, DL0, VT0,
5056 N0, DAG.getConstant(1, DL0, VT0));
5057 AddToWorklist(XORNode.getNode());
5059 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, XORNode);
5060 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, XORNode);
5062 // fold (select C, 0, X) -> (and (not C), X)
5063 if (VT == VT0 && VT == MVT::i1 && isNullConstant(N1)) {
5064 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
5065 AddToWorklist(NOTNode.getNode());
5066 return DAG.getNode(ISD::AND, SDLoc(N), VT, NOTNode, N2);
5068 // fold (select C, X, 1) -> (or (not C), X)
5069 if (VT == VT0 && VT == MVT::i1 && isOneConstant(N2)) {
5070 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
5071 AddToWorklist(NOTNode.getNode());
5072 return DAG.getNode(ISD::OR, SDLoc(N), VT, NOTNode, N1);
5074 // fold (select C, X, 0) -> (and C, X)
5075 if (VT == MVT::i1 && isNullConstant(N2))
5076 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
5077 // fold (select X, X, Y) -> (or X, Y)
5078 // fold (select X, 1, Y) -> (or X, Y)
5079 if (VT == MVT::i1 && (N0 == N1 || isOneConstant(N1)))
5080 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
5081 // fold (select X, Y, X) -> (and X, Y)
5082 // fold (select X, Y, 0) -> (and X, Y)
5083 if (VT == MVT::i1 && (N0 == N2 || isNullConstant(N2)))
5084 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
5086 // If we can fold this based on the true/false value, do so.
5087 if (SimplifySelectOps(N, N1, N2))
5088 return SDValue(N, 0); // Don't revisit N.
5090 if (VT0 == MVT::i1) {
5091 // The code in this block deals with the following 2 equivalences:
5092 // select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y))
5093 // select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y)
5094 // The target can specify its prefered form with the
5095 // shouldNormalizeToSelectSequence() callback. However we always transform
5096 // to the right anyway if we find the inner select exists in the DAG anyway
5097 // and we always transform to the left side if we know that we can further
5098 // optimize the combination of the conditions.
5099 bool normalizeToSequence
5100 = TLI.shouldNormalizeToSelectSequence(*DAG.getContext(), VT);
5101 // select (and Cond0, Cond1), X, Y
5102 // -> select Cond0, (select Cond1, X, Y), Y
5103 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) {
5104 SDValue Cond0 = N0->getOperand(0);
5105 SDValue Cond1 = N0->getOperand(1);
5106 SDValue InnerSelect = DAG.getNode(ISD::SELECT, SDLoc(N),
5107 N1.getValueType(), Cond1, N1, N2);
5108 if (normalizeToSequence || !InnerSelect.use_empty())
5109 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), Cond0,
5112 // select (or Cond0, Cond1), X, Y -> select Cond0, X, (select Cond1, X, Y)
5113 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) {
5114 SDValue Cond0 = N0->getOperand(0);
5115 SDValue Cond1 = N0->getOperand(1);
5116 SDValue InnerSelect = DAG.getNode(ISD::SELECT, SDLoc(N),
5117 N1.getValueType(), Cond1, N1, N2);
5118 if (normalizeToSequence || !InnerSelect.use_empty())
5119 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), Cond0, N1,
5123 // select Cond0, (select Cond1, X, Y), Y -> select (and Cond0, Cond1), X, Y
5124 if (N1->getOpcode() == ISD::SELECT && N1->hasOneUse()) {
5125 SDValue N1_0 = N1->getOperand(0);
5126 SDValue N1_1 = N1->getOperand(1);
5127 SDValue N1_2 = N1->getOperand(2);
5128 if (N1_2 == N2 && N0.getValueType() == N1_0.getValueType()) {
5129 // Create the actual and node if we can generate good code for it.
5130 if (!normalizeToSequence) {
5131 SDValue And = DAG.getNode(ISD::AND, SDLoc(N), N0.getValueType(),
5133 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), And,
5136 // Otherwise see if we can optimize the "and" to a better pattern.
5137 if (SDValue Combined = visitANDLike(N0, N1_0, N))
5138 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), Combined,
5142 // select Cond0, X, (select Cond1, X, Y) -> select (or Cond0, Cond1), X, Y
5143 if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) {
5144 SDValue N2_0 = N2->getOperand(0);
5145 SDValue N2_1 = N2->getOperand(1);
5146 SDValue N2_2 = N2->getOperand(2);
5147 if (N2_1 == N1 && N0.getValueType() == N2_0.getValueType()) {
5148 // Create the actual or node if we can generate good code for it.
5149 if (!normalizeToSequence) {
5150 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N), N0.getValueType(),
5152 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), Or,
5155 // Otherwise see if we can optimize to a better pattern.
5156 if (SDValue Combined = visitORLike(N0, N2_0, N))
5157 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), Combined,
5163 // fold selects based on a setcc into other things, such as min/max/abs
5164 if (N0.getOpcode() == ISD::SETCC) {
5165 // select x, y (fcmp lt x, y) -> fminnum x, y
5166 // select x, y (fcmp gt x, y) -> fmaxnum x, y
5168 // This is OK if we don't care about what happens if either operand is a
5172 // FIXME: Instead of testing for UnsafeFPMath, this should be checking for
5173 // no signed zeros as well as no nans.
5174 const TargetOptions &Options = DAG.getTarget().Options;
5175 if (Options.UnsafeFPMath &&
5176 VT.isFloatingPoint() && N0.hasOneUse() &&
5177 DAG.isKnownNeverNaN(N1) && DAG.isKnownNeverNaN(N2)) {
5178 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
5180 if (SDValue FMinMax = combineMinNumMaxNum(SDLoc(N), VT, N0.getOperand(0),
5181 N0.getOperand(1), N1, N2, CC,
5186 if ((!LegalOperations &&
5187 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) ||
5188 TLI.isOperationLegal(ISD::SELECT_CC, VT))
5189 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT,
5190 N0.getOperand(0), N0.getOperand(1),
5191 N1, N2, N0.getOperand(2));
5192 return SimplifySelect(SDLoc(N), N0, N1, N2);
5199 std::pair<SDValue, SDValue> SplitVSETCC(const SDNode *N, SelectionDAG &DAG) {
5202 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
5204 // Split the inputs.
5205 SDValue Lo, Hi, LL, LH, RL, RH;
5206 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
5207 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
5209 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
5210 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
5212 return std::make_pair(Lo, Hi);
5215 // This function assumes all the vselect's arguments are CONCAT_VECTOR
5216 // nodes and that the condition is a BV of ConstantSDNodes (or undefs).
5217 static SDValue ConvertSelectToConcatVector(SDNode *N, SelectionDAG &DAG) {
5219 SDValue Cond = N->getOperand(0);
5220 SDValue LHS = N->getOperand(1);
5221 SDValue RHS = N->getOperand(2);
5222 EVT VT = N->getValueType(0);
5223 int NumElems = VT.getVectorNumElements();
5224 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS &&
5225 RHS.getOpcode() == ISD::CONCAT_VECTORS &&
5226 Cond.getOpcode() == ISD::BUILD_VECTOR);
5228 // CONCAT_VECTOR can take an arbitrary number of arguments. We only care about
5229 // binary ones here.
5230 if (LHS->getNumOperands() != 2 || RHS->getNumOperands() != 2)
5233 // We're sure we have an even number of elements due to the
5234 // concat_vectors we have as arguments to vselect.
5235 // Skip BV elements until we find one that's not an UNDEF
5236 // After we find an UNDEF element, keep looping until we get to half the
5237 // length of the BV and see if all the non-undef nodes are the same.
5238 ConstantSDNode *BottomHalf = nullptr;
5239 for (int i = 0; i < NumElems / 2; ++i) {
5240 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
5243 if (BottomHalf == nullptr)
5244 BottomHalf = cast<ConstantSDNode>(Cond.getOperand(i));
5245 else if (Cond->getOperand(i).getNode() != BottomHalf)
5249 // Do the same for the second half of the BuildVector
5250 ConstantSDNode *TopHalf = nullptr;
5251 for (int i = NumElems / 2; i < NumElems; ++i) {
5252 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
5255 if (TopHalf == nullptr)
5256 TopHalf = cast<ConstantSDNode>(Cond.getOperand(i));
5257 else if (Cond->getOperand(i).getNode() != TopHalf)
5261 assert(TopHalf && BottomHalf &&
5262 "One half of the selector was all UNDEFs and the other was all the "
5263 "same value. This should have been addressed before this function.");
5265 ISD::CONCAT_VECTORS, dl, VT,
5266 BottomHalf->isNullValue() ? RHS->getOperand(0) : LHS->getOperand(0),
5267 TopHalf->isNullValue() ? RHS->getOperand(1) : LHS->getOperand(1));
5270 SDValue DAGCombiner::visitMSCATTER(SDNode *N) {
5272 if (Level >= AfterLegalizeTypes)
5275 MaskedScatterSDNode *MSC = cast<MaskedScatterSDNode>(N);
5276 SDValue Mask = MSC->getMask();
5277 SDValue Data = MSC->getValue();
5280 // If the MSCATTER data type requires splitting and the mask is provided by a
5281 // SETCC, then split both nodes and its operands before legalization. This
5282 // prevents the type legalizer from unrolling SETCC into scalar comparisons
5283 // and enables future optimizations (e.g. min/max pattern matching on X86).
5284 if (Mask.getOpcode() != ISD::SETCC)
5287 // Check if any splitting is required.
5288 if (TLI.getTypeAction(*DAG.getContext(), Data.getValueType()) !=
5289 TargetLowering::TypeSplitVector)
5291 SDValue MaskLo, MaskHi, Lo, Hi;
5292 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
5295 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MSC->getValueType(0));
5297 SDValue Chain = MSC->getChain();
5299 EVT MemoryVT = MSC->getMemoryVT();
5300 unsigned Alignment = MSC->getOriginalAlignment();
5302 EVT LoMemVT, HiMemVT;
5303 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
5305 SDValue DataLo, DataHi;
5306 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
5308 SDValue BasePtr = MSC->getBasePtr();
5309 SDValue IndexLo, IndexHi;
5310 std::tie(IndexLo, IndexHi) = DAG.SplitVector(MSC->getIndex(), DL);
5312 MachineMemOperand *MMO = DAG.getMachineFunction().
5313 getMachineMemOperand(MSC->getPointerInfo(),
5314 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
5315 Alignment, MSC->getAAInfo(), MSC->getRanges());
5317 SDValue OpsLo[] = { Chain, DataLo, MaskLo, BasePtr, IndexLo };
5318 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
5321 SDValue OpsHi[] = {Chain, DataHi, MaskHi, BasePtr, IndexHi};
5322 Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
5325 AddToWorklist(Lo.getNode());
5326 AddToWorklist(Hi.getNode());
5328 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
5331 SDValue DAGCombiner::visitMSTORE(SDNode *N) {
5333 if (Level >= AfterLegalizeTypes)
5336 MaskedStoreSDNode *MST = dyn_cast<MaskedStoreSDNode>(N);
5337 SDValue Mask = MST->getMask();
5338 SDValue Data = MST->getValue();
5341 // If the MSTORE data type requires splitting and the mask is provided by a
5342 // SETCC, then split both nodes and its operands before legalization. This
5343 // prevents the type legalizer from unrolling SETCC into scalar comparisons
5344 // and enables future optimizations (e.g. min/max pattern matching on X86).
5345 if (Mask.getOpcode() == ISD::SETCC) {
5347 // Check if any splitting is required.
5348 if (TLI.getTypeAction(*DAG.getContext(), Data.getValueType()) !=
5349 TargetLowering::TypeSplitVector)
5352 SDValue MaskLo, MaskHi, Lo, Hi;
5353 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
5356 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MST->getValueType(0));
5358 SDValue Chain = MST->getChain();
5359 SDValue Ptr = MST->getBasePtr();
5361 EVT MemoryVT = MST->getMemoryVT();
5362 unsigned Alignment = MST->getOriginalAlignment();
5364 // if Alignment is equal to the vector size,
5365 // take the half of it for the second part
5366 unsigned SecondHalfAlignment =
5367 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
5368 Alignment/2 : Alignment;
5370 EVT LoMemVT, HiMemVT;
5371 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
5373 SDValue DataLo, DataHi;
5374 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
5376 MachineMemOperand *MMO = DAG.getMachineFunction().
5377 getMachineMemOperand(MST->getPointerInfo(),
5378 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
5379 Alignment, MST->getAAInfo(), MST->getRanges());
5381 Lo = DAG.getMaskedStore(Chain, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
5382 MST->isTruncatingStore());
5384 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
5385 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5386 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
5388 MMO = DAG.getMachineFunction().
5389 getMachineMemOperand(MST->getPointerInfo(),
5390 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
5391 SecondHalfAlignment, MST->getAAInfo(),
5394 Hi = DAG.getMaskedStore(Chain, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
5395 MST->isTruncatingStore());
5397 AddToWorklist(Lo.getNode());
5398 AddToWorklist(Hi.getNode());
5400 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
5405 SDValue DAGCombiner::visitMGATHER(SDNode *N) {
5407 if (Level >= AfterLegalizeTypes)
5410 MaskedGatherSDNode *MGT = dyn_cast<MaskedGatherSDNode>(N);
5411 SDValue Mask = MGT->getMask();
5414 // If the MGATHER result requires splitting and the mask is provided by a
5415 // SETCC, then split both nodes and its operands before legalization. This
5416 // prevents the type legalizer from unrolling SETCC into scalar comparisons
5417 // and enables future optimizations (e.g. min/max pattern matching on X86).
5419 if (Mask.getOpcode() != ISD::SETCC)
5422 EVT VT = N->getValueType(0);
5424 // Check if any splitting is required.
5425 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
5426 TargetLowering::TypeSplitVector)
5429 SDValue MaskLo, MaskHi, Lo, Hi;
5430 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
5432 SDValue Src0 = MGT->getValue();
5433 SDValue Src0Lo, Src0Hi;
5434 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, DL);
5437 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
5439 SDValue Chain = MGT->getChain();
5440 EVT MemoryVT = MGT->getMemoryVT();
5441 unsigned Alignment = MGT->getOriginalAlignment();
5443 EVT LoMemVT, HiMemVT;
5444 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
5446 SDValue BasePtr = MGT->getBasePtr();
5447 SDValue Index = MGT->getIndex();
5448 SDValue IndexLo, IndexHi;
5449 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
5451 MachineMemOperand *MMO = DAG.getMachineFunction().
5452 getMachineMemOperand(MGT->getPointerInfo(),
5453 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
5454 Alignment, MGT->getAAInfo(), MGT->getRanges());
5456 SDValue OpsLo[] = { Chain, Src0Lo, MaskLo, BasePtr, IndexLo };
5457 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, DL, OpsLo,
5460 SDValue OpsHi[] = {Chain, Src0Hi, MaskHi, BasePtr, IndexHi};
5461 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, DL, OpsHi,
5464 AddToWorklist(Lo.getNode());
5465 AddToWorklist(Hi.getNode());
5467 // Build a factor node to remember that this load is independent of the
5469 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo.getValue(1),
5472 // Legalized the chain result - switch anything that used the old chain to
5474 DAG.ReplaceAllUsesOfValueWith(SDValue(MGT, 1), Chain);
5476 SDValue GatherRes = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
5478 SDValue RetOps[] = { GatherRes, Chain };
5479 return DAG.getMergeValues(RetOps, DL);
5482 SDValue DAGCombiner::visitMLOAD(SDNode *N) {
5484 if (Level >= AfterLegalizeTypes)
5487 MaskedLoadSDNode *MLD = dyn_cast<MaskedLoadSDNode>(N);
5488 SDValue Mask = MLD->getMask();
5491 // If the MLOAD result requires splitting and the mask is provided by a
5492 // SETCC, then split both nodes and its operands before legalization. This
5493 // prevents the type legalizer from unrolling SETCC into scalar comparisons
5494 // and enables future optimizations (e.g. min/max pattern matching on X86).
5496 if (Mask.getOpcode() == ISD::SETCC) {
5497 EVT VT = N->getValueType(0);
5499 // Check if any splitting is required.
5500 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
5501 TargetLowering::TypeSplitVector)
5504 SDValue MaskLo, MaskHi, Lo, Hi;
5505 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
5507 SDValue Src0 = MLD->getSrc0();
5508 SDValue Src0Lo, Src0Hi;
5509 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, DL);
5512 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
5514 SDValue Chain = MLD->getChain();
5515 SDValue Ptr = MLD->getBasePtr();
5516 EVT MemoryVT = MLD->getMemoryVT();
5517 unsigned Alignment = MLD->getOriginalAlignment();
5519 // if Alignment is equal to the vector size,
5520 // take the half of it for the second part
5521 unsigned SecondHalfAlignment =
5522 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
5523 Alignment/2 : Alignment;
5525 EVT LoMemVT, HiMemVT;
5526 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
5528 MachineMemOperand *MMO = DAG.getMachineFunction().
5529 getMachineMemOperand(MLD->getPointerInfo(),
5530 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
5531 Alignment, MLD->getAAInfo(), MLD->getRanges());
5533 Lo = DAG.getMaskedLoad(LoVT, DL, Chain, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
5536 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
5537 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5538 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
5540 MMO = DAG.getMachineFunction().
5541 getMachineMemOperand(MLD->getPointerInfo(),
5542 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
5543 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
5545 Hi = DAG.getMaskedLoad(HiVT, DL, Chain, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
5548 AddToWorklist(Lo.getNode());
5549 AddToWorklist(Hi.getNode());
5551 // Build a factor node to remember that this load is independent of the
5553 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo.getValue(1),
5556 // Legalized the chain result - switch anything that used the old chain to
5558 DAG.ReplaceAllUsesOfValueWith(SDValue(MLD, 1), Chain);
5560 SDValue LoadRes = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
5562 SDValue RetOps[] = { LoadRes, Chain };
5563 return DAG.getMergeValues(RetOps, DL);
5568 SDValue DAGCombiner::visitVSELECT(SDNode *N) {
5569 SDValue N0 = N->getOperand(0);
5570 SDValue N1 = N->getOperand(1);
5571 SDValue N2 = N->getOperand(2);
5574 // Canonicalize integer abs.
5575 // vselect (setg[te] X, 0), X, -X ->
5576 // vselect (setgt X, -1), X, -X ->
5577 // vselect (setl[te] X, 0), -X, X ->
5578 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5579 if (N0.getOpcode() == ISD::SETCC) {
5580 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
5581 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
5583 bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
5585 if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
5586 (ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) &&
5587 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
5588 isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode());
5589 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) &&
5590 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
5591 isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
5594 EVT VT = LHS.getValueType();
5595 SDValue Shift = DAG.getNode(
5596 ISD::SRA, DL, VT, LHS,
5597 DAG.getConstant(VT.getScalarType().getSizeInBits() - 1, DL, VT));
5598 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift);
5599 AddToWorklist(Shift.getNode());
5600 AddToWorklist(Add.getNode());
5601 return DAG.getNode(ISD::XOR, DL, VT, Add, Shift);
5605 if (SimplifySelectOps(N, N1, N2))
5606 return SDValue(N, 0); // Don't revisit N.
5608 // If the VSELECT result requires splitting and the mask is provided by a
5609 // SETCC, then split both nodes and its operands before legalization. This
5610 // prevents the type legalizer from unrolling SETCC into scalar comparisons
5611 // and enables future optimizations (e.g. min/max pattern matching on X86).
5612 if (N0.getOpcode() == ISD::SETCC) {
5613 EVT VT = N->getValueType(0);
5615 // Check if any splitting is required.
5616 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
5617 TargetLowering::TypeSplitVector)
5620 SDValue Lo, Hi, CCLo, CCHi, LL, LH, RL, RH;
5621 std::tie(CCLo, CCHi) = SplitVSETCC(N0.getNode(), DAG);
5622 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 1);
5623 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 2);
5625 Lo = DAG.getNode(N->getOpcode(), DL, LL.getValueType(), CCLo, LL, RL);
5626 Hi = DAG.getNode(N->getOpcode(), DL, LH.getValueType(), CCHi, LH, RH);
5628 // Add the new VSELECT nodes to the work list in case they need to be split
5630 AddToWorklist(Lo.getNode());
5631 AddToWorklist(Hi.getNode());
5633 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
5636 // Fold (vselect (build_vector all_ones), N1, N2) -> N1
5637 if (ISD::isBuildVectorAllOnes(N0.getNode()))
5639 // Fold (vselect (build_vector all_zeros), N1, N2) -> N2
5640 if (ISD::isBuildVectorAllZeros(N0.getNode()))
5643 // The ConvertSelectToConcatVector function is assuming both the above
5644 // checks for (vselect (build_vector all{ones,zeros) ...) have been made
5646 if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
5647 N2.getOpcode() == ISD::CONCAT_VECTORS &&
5648 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
5649 if (SDValue CV = ConvertSelectToConcatVector(N, DAG))
5656 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
5657 SDValue N0 = N->getOperand(0);
5658 SDValue N1 = N->getOperand(1);
5659 SDValue N2 = N->getOperand(2);
5660 SDValue N3 = N->getOperand(3);
5661 SDValue N4 = N->getOperand(4);
5662 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
5664 // fold select_cc lhs, rhs, x, x, cc -> x
5668 // Determine if the condition we're dealing with is constant
5669 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
5670 N0, N1, CC, SDLoc(N), false);
5671 if (SCC.getNode()) {
5672 AddToWorklist(SCC.getNode());
5674 if (ConstantSDNode *SCCC = dyn_cast<ConstantSDNode>(SCC.getNode())) {
5675 if (!SCCC->isNullValue())
5676 return N2; // cond always true -> true val
5678 return N3; // cond always false -> false val
5679 } else if (SCC->getOpcode() == ISD::UNDEF) {
5680 // When the condition is UNDEF, just return the first operand. This is
5681 // coherent the DAG creation, no setcc node is created in this case
5683 } else if (SCC.getOpcode() == ISD::SETCC) {
5684 // Fold to a simpler select_cc
5685 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(),
5686 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
5691 // If we can fold this based on the true/false value, do so.
5692 if (SimplifySelectOps(N, N2, N3))
5693 return SDValue(N, 0); // Don't revisit N.
5695 // fold select_cc into other things, such as min/max/abs
5696 return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC);
5699 SDValue DAGCombiner::visitSETCC(SDNode *N) {
5700 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
5701 cast<CondCodeSDNode>(N->getOperand(2))->get(),
5705 SDValue DAGCombiner::visitSETCCE(SDNode *N) {
5706 SDValue LHS = N->getOperand(0);
5707 SDValue RHS = N->getOperand(1);
5708 SDValue Carry = N->getOperand(2);
5709 SDValue Cond = N->getOperand(3);
5711 // If Carry is false, fold to a regular SETCC.
5712 if (Carry.getOpcode() == ISD::CARRY_FALSE)
5713 return DAG.getNode(ISD::SETCC, SDLoc(N), N->getVTList(), LHS, RHS, Cond);
5718 /// Try to fold a sext/zext/aext dag node into a ConstantSDNode or
5719 /// a build_vector of constants.
5720 /// This function is called by the DAGCombiner when visiting sext/zext/aext
5721 /// dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
5722 /// Vector extends are not folded if operations are legal; this is to
5723 /// avoid introducing illegal build_vector dag nodes.
5724 static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
5725 SelectionDAG &DAG, bool LegalTypes,
5726 bool LegalOperations) {
5727 unsigned Opcode = N->getOpcode();
5728 SDValue N0 = N->getOperand(0);
5729 EVT VT = N->getValueType(0);
5731 assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND ||
5732 Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
5733 && "Expected EXTEND dag node in input!");
5735 // fold (sext c1) -> c1
5736 // fold (zext c1) -> c1
5737 // fold (aext c1) -> c1
5738 if (isa<ConstantSDNode>(N0))
5739 return DAG.getNode(Opcode, SDLoc(N), VT, N0).getNode();
5741 // fold (sext (build_vector AllConstants) -> (build_vector AllConstants)
5742 // fold (zext (build_vector AllConstants) -> (build_vector AllConstants)
5743 // fold (aext (build_vector AllConstants) -> (build_vector AllConstants)
5744 EVT SVT = VT.getScalarType();
5745 if (!(VT.isVector() &&
5746 (!LegalTypes || (!LegalOperations && TLI.isTypeLegal(SVT))) &&
5747 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())))
5750 // We can fold this node into a build_vector.
5751 unsigned VTBits = SVT.getSizeInBits();
5752 unsigned EVTBits = N0->getValueType(0).getScalarType().getSizeInBits();
5753 SmallVector<SDValue, 8> Elts;
5754 unsigned NumElts = VT.getVectorNumElements();
5757 for (unsigned i=0; i != NumElts; ++i) {
5758 SDValue Op = N0->getOperand(i);
5759 if (Op->getOpcode() == ISD::UNDEF) {
5760 Elts.push_back(DAG.getUNDEF(SVT));
5765 // Get the constant value and if needed trunc it to the size of the type.
5766 // Nodes like build_vector might have constants wider than the scalar type.
5767 APInt C = cast<ConstantSDNode>(Op)->getAPIntValue().zextOrTrunc(EVTBits);
5768 if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
5769 Elts.push_back(DAG.getConstant(C.sext(VTBits), DL, SVT));
5771 Elts.push_back(DAG.getConstant(C.zext(VTBits), DL, SVT));
5774 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Elts).getNode();
5777 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
5778 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
5779 // transformation. Returns true if extension are possible and the above
5780 // mentioned transformation is profitable.
5781 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
5783 SmallVectorImpl<SDNode *> &ExtendNodes,
5784 const TargetLowering &TLI) {
5785 bool HasCopyToRegUses = false;
5786 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
5787 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
5788 UE = N0.getNode()->use_end();
5793 if (UI.getUse().getResNo() != N0.getResNo())
5795 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
5796 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
5797 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
5798 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
5799 // Sign bits will be lost after a zext.
5802 for (unsigned i = 0; i != 2; ++i) {
5803 SDValue UseOp = User->getOperand(i);
5806 if (!isa<ConstantSDNode>(UseOp))
5811 ExtendNodes.push_back(User);
5814 // If truncates aren't free and there are users we can't
5815 // extend, it isn't worthwhile.
5818 // Remember if this value is live-out.
5819 if (User->getOpcode() == ISD::CopyToReg)
5820 HasCopyToRegUses = true;
5823 if (HasCopyToRegUses) {
5824 bool BothLiveOut = false;
5825 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
5827 SDUse &Use = UI.getUse();
5828 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
5834 // Both unextended and extended values are live out. There had better be
5835 // a good reason for the transformation.
5836 return ExtendNodes.size();
5841 void DAGCombiner::ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
5842 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
5843 ISD::NodeType ExtType) {
5844 // Extend SetCC uses if necessary.
5845 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
5846 SDNode *SetCC = SetCCs[i];
5847 SmallVector<SDValue, 4> Ops;
5849 for (unsigned j = 0; j != 2; ++j) {
5850 SDValue SOp = SetCC->getOperand(j);
5852 Ops.push_back(ExtLoad);
5854 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
5857 Ops.push_back(SetCC->getOperand(2));
5858 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops));
5862 // FIXME: Bring more similar combines here, common to sext/zext (maybe aext?).
5863 SDValue DAGCombiner::CombineExtLoad(SDNode *N) {
5864 SDValue N0 = N->getOperand(0);
5865 EVT DstVT = N->getValueType(0);
5866 EVT SrcVT = N0.getValueType();
5868 assert((N->getOpcode() == ISD::SIGN_EXTEND ||
5869 N->getOpcode() == ISD::ZERO_EXTEND) &&
5870 "Unexpected node type (not an extend)!");
5872 // fold (sext (load x)) to multiple smaller sextloads; same for zext.
5873 // For example, on a target with legal v4i32, but illegal v8i32, turn:
5874 // (v8i32 (sext (v8i16 (load x))))
5876 // (v8i32 (concat_vectors (v4i32 (sextload x)),
5877 // (v4i32 (sextload (x + 16)))))
5878 // Where uses of the original load, i.e.:
5880 // are replaced with:
5882 // (v8i32 (concat_vectors (v4i32 (sextload x)),
5883 // (v4i32 (sextload (x + 16)))))))
5885 // This combine is only applicable to illegal, but splittable, vectors.
5886 // All legal types, and illegal non-vector types, are handled elsewhere.
5887 // This combine is controlled by TargetLowering::isVectorLoadExtDesirable.
5889 if (N0->getOpcode() != ISD::LOAD)
5892 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5894 if (!ISD::isNON_EXTLoad(LN0) || !ISD::isUNINDEXEDLoad(LN0) ||
5895 !N0.hasOneUse() || LN0->isVolatile() || !DstVT.isVector() ||
5896 !DstVT.isPow2VectorType() || !TLI.isVectorLoadExtDesirable(SDValue(N, 0)))
5899 SmallVector<SDNode *, 4> SetCCs;
5900 if (!ExtendUsesToFormExtLoad(N, N0, N->getOpcode(), SetCCs, TLI))
5903 ISD::LoadExtType ExtType =
5904 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
5906 // Try to split the vector types to get down to legal types.
5907 EVT SplitSrcVT = SrcVT;
5908 EVT SplitDstVT = DstVT;
5909 while (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT) &&
5910 SplitSrcVT.getVectorNumElements() > 1) {
5911 SplitDstVT = DAG.GetSplitDestVTs(SplitDstVT).first;
5912 SplitSrcVT = DAG.GetSplitDestVTs(SplitSrcVT).first;
5915 if (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT))
5919 const unsigned NumSplits =
5920 DstVT.getVectorNumElements() / SplitDstVT.getVectorNumElements();
5921 const unsigned Stride = SplitSrcVT.getStoreSize();
5922 SmallVector<SDValue, 4> Loads;
5923 SmallVector<SDValue, 4> Chains;
5925 SDValue BasePtr = LN0->getBasePtr();
5926 for (unsigned Idx = 0; Idx < NumSplits; Idx++) {
5927 const unsigned Offset = Idx * Stride;
5928 const unsigned Align = MinAlign(LN0->getAlignment(), Offset);
5930 SDValue SplitLoad = DAG.getExtLoad(
5931 ExtType, DL, SplitDstVT, LN0->getChain(), BasePtr,
5932 LN0->getPointerInfo().getWithOffset(Offset), SplitSrcVT,
5933 LN0->isVolatile(), LN0->isNonTemporal(), LN0->isInvariant(),
5934 Align, LN0->getAAInfo());
5936 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
5937 DAG.getConstant(Stride, DL, BasePtr.getValueType()));
5939 Loads.push_back(SplitLoad.getValue(0));
5940 Chains.push_back(SplitLoad.getValue(1));
5943 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
5944 SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads);
5946 CombineTo(N, NewValue);
5948 // Replace uses of the original load (before extension)
5949 // with a truncate of the concatenated sextloaded vectors.
5951 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), NewValue);
5952 CombineTo(N0.getNode(), Trunc, NewChain);
5953 ExtendSetCCUses(SetCCs, Trunc, NewValue, DL,
5954 (ISD::NodeType)N->getOpcode());
5955 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5958 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
5959 SDValue N0 = N->getOperand(0);
5960 EVT VT = N->getValueType(0);
5962 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5964 return SDValue(Res, 0);
5966 // fold (sext (sext x)) -> (sext x)
5967 // fold (sext (aext x)) -> (sext x)
5968 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5969 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT,
5972 if (N0.getOpcode() == ISD::TRUNCATE) {
5973 // fold (sext (truncate (load x))) -> (sext (smaller load x))
5974 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
5975 if (SDValue NarrowLoad = ReduceLoadWidth(N0.getNode())) {
5976 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5977 if (NarrowLoad.getNode() != N0.getNode()) {
5978 CombineTo(N0.getNode(), NarrowLoad);
5979 // CombineTo deleted the truncate, if needed, but not what's under it.
5982 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5985 // See if the value being truncated is already sign extended. If so, just
5986 // eliminate the trunc/sext pair.
5987 SDValue Op = N0.getOperand(0);
5988 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
5989 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
5990 unsigned DestBits = VT.getScalarType().getSizeInBits();
5991 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
5993 if (OpBits == DestBits) {
5994 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
5995 // bits, it is already ready.
5996 if (NumSignBits > DestBits-MidBits)
5998 } else if (OpBits < DestBits) {
5999 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
6000 // bits, just sext from i32.
6001 if (NumSignBits > OpBits-MidBits)
6002 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, Op);
6004 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
6005 // bits, just truncate to i32.
6006 if (NumSignBits > OpBits-MidBits)
6007 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
6010 // fold (sext (truncate x)) -> (sextinreg x).
6011 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
6012 N0.getValueType())) {
6013 if (OpBits < DestBits)
6014 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op);
6015 else if (OpBits > DestBits)
6016 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op);
6017 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, Op,
6018 DAG.getValueType(N0.getValueType()));
6022 // fold (sext (load x)) -> (sext (truncate (sextload x)))
6023 // Only generate vector extloads when 1) they're legal, and 2) they are
6024 // deemed desirable by the target.
6025 if (ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
6026 ((!LegalOperations && !VT.isVector() &&
6027 !cast<LoadSDNode>(N0)->isVolatile()) ||
6028 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()))) {
6029 bool DoXform = true;
6030 SmallVector<SDNode*, 4> SetCCs;
6031 if (!N0.hasOneUse())
6032 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
6034 DoXform &= TLI.isVectorLoadExtDesirable(SDValue(N, 0));
6036 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6037 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
6039 LN0->getBasePtr(), N0.getValueType(),
6040 LN0->getMemOperand());
6041 CombineTo(N, ExtLoad);
6042 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
6043 N0.getValueType(), ExtLoad);
6044 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
6045 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
6047 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6051 // fold (sext (load x)) to multiple smaller sextloads.
6052 // Only on illegal but splittable vectors.
6053 if (SDValue ExtLoad = CombineExtLoad(N))
6056 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
6057 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
6058 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
6059 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
6060 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6061 EVT MemVT = LN0->getMemoryVT();
6062 if ((!LegalOperations && !LN0->isVolatile()) ||
6063 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, MemVT)) {
6064 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
6066 LN0->getBasePtr(), MemVT,
6067 LN0->getMemOperand());
6068 CombineTo(N, ExtLoad);
6069 CombineTo(N0.getNode(),
6070 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
6071 N0.getValueType(), ExtLoad),
6072 ExtLoad.getValue(1));
6073 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6077 // fold (sext (and/or/xor (load x), cst)) ->
6078 // (and/or/xor (sextload x), (sext cst))
6079 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
6080 N0.getOpcode() == ISD::XOR) &&
6081 isa<LoadSDNode>(N0.getOperand(0)) &&
6082 N0.getOperand(1).getOpcode() == ISD::Constant &&
6083 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()) &&
6084 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
6085 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
6086 if (LN0->getExtensionType() != ISD::ZEXTLOAD && LN0->isUnindexed()) {
6087 bool DoXform = true;
6088 SmallVector<SDNode*, 4> SetCCs;
6089 if (!N0.hasOneUse())
6090 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
6093 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN0), VT,
6094 LN0->getChain(), LN0->getBasePtr(),
6096 LN0->getMemOperand());
6097 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
6098 Mask = Mask.sext(VT.getSizeInBits());
6100 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
6101 ExtLoad, DAG.getConstant(Mask, DL, VT));
6102 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
6103 SDLoc(N0.getOperand(0)),
6104 N0.getOperand(0).getValueType(), ExtLoad);
6106 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
6107 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL,
6109 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6114 if (N0.getOpcode() == ISD::SETCC) {
6115 EVT N0VT = N0.getOperand(0).getValueType();
6116 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
6117 // Only do this before legalize for now.
6118 if (VT.isVector() && !LegalOperations &&
6119 TLI.getBooleanContents(N0VT) ==
6120 TargetLowering::ZeroOrNegativeOneBooleanContent) {
6121 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
6122 // of the same size as the compared operands. Only optimize sext(setcc())
6123 // if this is the case.
6124 EVT SVT = getSetCCResultType(N0VT);
6126 // We know that the # elements of the results is the same as the
6127 // # elements of the compare (and the # elements of the compare result
6128 // for that matter). Check to see that they are the same size. If so,
6129 // we know that the element size of the sext'd result matches the
6130 // element size of the compare operands.
6131 if (VT.getSizeInBits() == SVT.getSizeInBits())
6132 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
6134 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6136 // If the desired elements are smaller or larger than the source
6137 // elements we can use a matching integer vector type and then
6138 // truncate/sign extend
6139 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
6140 if (SVT == MatchingVectorType) {
6141 SDValue VsetCC = DAG.getSetCC(SDLoc(N), MatchingVectorType,
6142 N0.getOperand(0), N0.getOperand(1),
6143 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6144 return DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT);
6148 // sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)
6149 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
6152 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), DL, VT);
6154 SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1),
6155 NegOne, DAG.getConstant(0, DL, VT),
6156 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
6157 if (SCC.getNode()) return SCC;
6159 if (!VT.isVector()) {
6160 EVT SetCCVT = getSetCCResultType(N0.getOperand(0).getValueType());
6161 if (!LegalOperations ||
6162 TLI.isOperationLegal(ISD::SETCC, N0.getOperand(0).getValueType())) {
6164 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
6165 SDValue SetCC = DAG.getSetCC(DL, SetCCVT,
6166 N0.getOperand(0), N0.getOperand(1), CC);
6167 return DAG.getSelect(DL, VT, SetCC,
6168 NegOne, DAG.getConstant(0, DL, VT));
6173 // fold (sext x) -> (zext x) if the sign bit is known zero.
6174 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
6175 DAG.SignBitIsZero(N0))
6176 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0);
6181 // isTruncateOf - If N is a truncate of some other value, return true, record
6182 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
6183 // This function computes KnownZero to avoid a duplicated call to
6184 // computeKnownBits in the caller.
6185 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
6188 if (N->getOpcode() == ISD::TRUNCATE) {
6189 Op = N->getOperand(0);
6190 DAG.computeKnownBits(Op, KnownZero, KnownOne);
6194 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
6195 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
6198 SDValue Op0 = N->getOperand(0);
6199 SDValue Op1 = N->getOperand(1);
6200 assert(Op0.getValueType() == Op1.getValueType());
6202 if (isNullConstant(Op0))
6204 else if (isNullConstant(Op1))
6209 DAG.computeKnownBits(Op, KnownZero, KnownOne);
6211 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
6217 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
6218 SDValue N0 = N->getOperand(0);
6219 EVT VT = N->getValueType(0);
6221 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
6223 return SDValue(Res, 0);
6225 // fold (zext (zext x)) -> (zext x)
6226 // fold (zext (aext x)) -> (zext x)
6227 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
6228 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT,
6231 // fold (zext (truncate x)) -> (zext x) or
6232 // (zext (truncate x)) -> (truncate x)
6233 // This is valid when the truncated bits of x are already zero.
6234 // FIXME: We should extend this to work for vectors too.
6237 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
6238 APInt TruncatedBits =
6239 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
6240 APInt(Op.getValueSizeInBits(), 0) :
6241 APInt::getBitsSet(Op.getValueSizeInBits(),
6242 N0.getValueSizeInBits(),
6243 std::min(Op.getValueSizeInBits(),
6244 VT.getSizeInBits()));
6245 if (TruncatedBits == (KnownZero & TruncatedBits)) {
6246 if (VT.bitsGT(Op.getValueType()))
6247 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, Op);
6248 if (VT.bitsLT(Op.getValueType()))
6249 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
6255 // fold (zext (truncate (load x))) -> (zext (smaller load x))
6256 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
6257 if (N0.getOpcode() == ISD::TRUNCATE) {
6258 if (SDValue NarrowLoad = ReduceLoadWidth(N0.getNode())) {
6259 SDNode* oye = N0.getNode()->getOperand(0).getNode();
6260 if (NarrowLoad.getNode() != N0.getNode()) {
6261 CombineTo(N0.getNode(), NarrowLoad);
6262 // CombineTo deleted the truncate, if needed, but not what's under it.
6265 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6269 // fold (zext (truncate x)) -> (and x, mask)
6270 if (N0.getOpcode() == ISD::TRUNCATE) {
6271 // fold (zext (truncate (load x))) -> (zext (smaller load x))
6272 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
6273 if (SDValue NarrowLoad = ReduceLoadWidth(N0.getNode())) {
6274 SDNode *oye = N0.getNode()->getOperand(0).getNode();
6275 if (NarrowLoad.getNode() != N0.getNode()) {
6276 CombineTo(N0.getNode(), NarrowLoad);
6277 // CombineTo deleted the truncate, if needed, but not what's under it.
6280 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6283 EVT SrcVT = N0.getOperand(0).getValueType();
6284 EVT MinVT = N0.getValueType();
6286 // Try to mask before the extension to avoid having to generate a larger mask,
6287 // possibly over several sub-vectors.
6288 if (SrcVT.bitsLT(VT)) {
6289 if (!LegalOperations || (TLI.isOperationLegal(ISD::AND, SrcVT) &&
6290 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) {
6291 SDValue Op = N0.getOperand(0);
6292 Op = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT.getScalarType());
6293 AddToWorklist(Op.getNode());
6294 return DAG.getZExtOrTrunc(Op, SDLoc(N), VT);
6298 if (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) {
6299 SDValue Op = N0.getOperand(0);
6300 if (SrcVT.bitsLT(VT)) {
6301 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Op);
6302 AddToWorklist(Op.getNode());
6303 } else if (SrcVT.bitsGT(VT)) {
6304 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
6305 AddToWorklist(Op.getNode());
6307 return DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT.getScalarType());
6311 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
6312 // if either of the casts is not free.
6313 if (N0.getOpcode() == ISD::AND &&
6314 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
6315 N0.getOperand(1).getOpcode() == ISD::Constant &&
6316 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
6317 N0.getValueType()) ||
6318 !TLI.isZExtFree(N0.getValueType(), VT))) {
6319 SDValue X = N0.getOperand(0).getOperand(0);
6320 if (X.getValueType().bitsLT(VT)) {
6321 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(X), VT, X);
6322 } else if (X.getValueType().bitsGT(VT)) {
6323 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
6325 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
6326 Mask = Mask.zext(VT.getSizeInBits());
6328 return DAG.getNode(ISD::AND, DL, VT,
6329 X, DAG.getConstant(Mask, DL, VT));
6332 // fold (zext (load x)) -> (zext (truncate (zextload x)))
6333 // Only generate vector extloads when 1) they're legal, and 2) they are
6334 // deemed desirable by the target.
6335 if (ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
6336 ((!LegalOperations && !VT.isVector() &&
6337 !cast<LoadSDNode>(N0)->isVolatile()) ||
6338 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()))) {
6339 bool DoXform = true;
6340 SmallVector<SDNode*, 4> SetCCs;
6341 if (!N0.hasOneUse())
6342 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
6344 DoXform &= TLI.isVectorLoadExtDesirable(SDValue(N, 0));
6346 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6347 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
6349 LN0->getBasePtr(), N0.getValueType(),
6350 LN0->getMemOperand());
6351 CombineTo(N, ExtLoad);
6352 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
6353 N0.getValueType(), ExtLoad);
6354 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
6356 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
6358 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6362 // fold (zext (load x)) to multiple smaller zextloads.
6363 // Only on illegal but splittable vectors.
6364 if (SDValue ExtLoad = CombineExtLoad(N))
6367 // fold (zext (and/or/xor (load x), cst)) ->
6368 // (and/or/xor (zextload x), (zext cst))
6369 // Unless (and (load x) cst) will match as a zextload already and has
6370 // additional users.
6371 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
6372 N0.getOpcode() == ISD::XOR) &&
6373 isa<LoadSDNode>(N0.getOperand(0)) &&
6374 N0.getOperand(1).getOpcode() == ISD::Constant &&
6375 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()) &&
6376 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
6377 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
6378 if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed()) {
6379 bool DoXform = true;
6380 SmallVector<SDNode*, 4> SetCCs;
6381 if (!N0.hasOneUse()) {
6382 if (N0.getOpcode() == ISD::AND) {
6383 auto *AndC = cast<ConstantSDNode>(N0.getOperand(1));
6384 auto NarrowLoad = false;
6385 EVT LoadResultTy = AndC->getValueType(0);
6386 EVT ExtVT, LoadedVT;
6387 if (isAndLoadExtLoad(AndC, LN0, LoadResultTy, ExtVT, LoadedVT,
6392 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0),
6393 ISD::ZERO_EXTEND, SetCCs, TLI);
6396 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), VT,
6397 LN0->getChain(), LN0->getBasePtr(),
6399 LN0->getMemOperand());
6400 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
6401 Mask = Mask.zext(VT.getSizeInBits());
6403 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
6404 ExtLoad, DAG.getConstant(Mask, DL, VT));
6405 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
6406 SDLoc(N0.getOperand(0)),
6407 N0.getOperand(0).getValueType(), ExtLoad);
6409 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
6410 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL,
6412 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6417 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
6418 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
6419 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
6420 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
6421 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6422 EVT MemVT = LN0->getMemoryVT();
6423 if ((!LegalOperations && !LN0->isVolatile()) ||
6424 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT)) {
6425 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
6427 LN0->getBasePtr(), MemVT,
6428 LN0->getMemOperand());
6429 CombineTo(N, ExtLoad);
6430 CombineTo(N0.getNode(),
6431 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(),
6433 ExtLoad.getValue(1));
6434 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6438 if (N0.getOpcode() == ISD::SETCC) {
6439 if (!LegalOperations && VT.isVector() &&
6440 N0.getValueType().getVectorElementType() == MVT::i1) {
6441 EVT N0VT = N0.getOperand(0).getValueType();
6442 if (getSetCCResultType(N0VT) == N0.getValueType())
6445 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
6446 // Only do this before legalize for now.
6447 EVT EltVT = VT.getVectorElementType();
6449 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
6450 DAG.getConstant(1, DL, EltVT));
6451 if (VT.getSizeInBits() == N0VT.getSizeInBits())
6452 // We know that the # elements of the results is the same as the
6453 // # elements of the compare (and the # elements of the compare result
6454 // for that matter). Check to see that they are the same size. If so,
6455 // we know that the element size of the sext'd result matches the
6456 // element size of the compare operands.
6457 return DAG.getNode(ISD::AND, DL, VT,
6458 DAG.getSetCC(DL, VT, N0.getOperand(0),
6460 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
6461 DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
6464 // If the desired elements are smaller or larger than the source
6465 // elements we can use a matching integer vector type and then
6466 // truncate/sign extend
6467 EVT MatchingElementType =
6468 EVT::getIntegerVT(*DAG.getContext(),
6469 N0VT.getScalarType().getSizeInBits());
6470 EVT MatchingVectorType =
6471 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
6472 N0VT.getVectorNumElements());
6474 DAG.getSetCC(DL, MatchingVectorType, N0.getOperand(0),
6476 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6477 return DAG.getNode(ISD::AND, DL, VT,
6478 DAG.getSExtOrTrunc(VsetCC, DL, VT),
6479 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, OneOps));
6482 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
6485 SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1),
6486 DAG.getConstant(1, DL, VT), DAG.getConstant(0, DL, VT),
6487 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
6488 if (SCC.getNode()) return SCC;
6491 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
6492 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
6493 isa<ConstantSDNode>(N0.getOperand(1)) &&
6494 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
6496 SDValue ShAmt = N0.getOperand(1);
6497 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
6498 if (N0.getOpcode() == ISD::SHL) {
6499 SDValue InnerZExt = N0.getOperand(0);
6500 // If the original shl may be shifting out bits, do not perform this
6502 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
6503 InnerZExt.getOperand(0).getValueType().getSizeInBits();
6504 if (ShAmtVal > KnownZeroBits)
6510 // Ensure that the shift amount is wide enough for the shifted value.
6511 if (VT.getSizeInBits() >= 256)
6512 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
6514 return DAG.getNode(N0.getOpcode(), DL, VT,
6515 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
6522 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
6523 SDValue N0 = N->getOperand(0);
6524 EVT VT = N->getValueType(0);
6526 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
6528 return SDValue(Res, 0);
6530 // fold (aext (aext x)) -> (aext x)
6531 // fold (aext (zext x)) -> (zext x)
6532 // fold (aext (sext x)) -> (sext x)
6533 if (N0.getOpcode() == ISD::ANY_EXTEND ||
6534 N0.getOpcode() == ISD::ZERO_EXTEND ||
6535 N0.getOpcode() == ISD::SIGN_EXTEND)
6536 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0));
6538 // fold (aext (truncate (load x))) -> (aext (smaller load x))
6539 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
6540 if (N0.getOpcode() == ISD::TRUNCATE) {
6541 if (SDValue NarrowLoad = ReduceLoadWidth(N0.getNode())) {
6542 SDNode* oye = N0.getNode()->getOperand(0).getNode();
6543 if (NarrowLoad.getNode() != N0.getNode()) {
6544 CombineTo(N0.getNode(), NarrowLoad);
6545 // CombineTo deleted the truncate, if needed, but not what's under it.
6548 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6552 // fold (aext (truncate x))
6553 if (N0.getOpcode() == ISD::TRUNCATE) {
6554 SDValue TruncOp = N0.getOperand(0);
6555 if (TruncOp.getValueType() == VT)
6556 return TruncOp; // x iff x size == zext size.
6557 if (TruncOp.getValueType().bitsGT(VT))
6558 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, TruncOp);
6559 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, TruncOp);
6562 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
6563 // if the trunc is not free.
6564 if (N0.getOpcode() == ISD::AND &&
6565 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
6566 N0.getOperand(1).getOpcode() == ISD::Constant &&
6567 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
6568 N0.getValueType())) {
6569 SDValue X = N0.getOperand(0).getOperand(0);
6570 if (X.getValueType().bitsLT(VT)) {
6571 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, X);
6572 } else if (X.getValueType().bitsGT(VT)) {
6573 X = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, X);
6575 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
6576 Mask = Mask.zext(VT.getSizeInBits());
6578 return DAG.getNode(ISD::AND, DL, VT,
6579 X, DAG.getConstant(Mask, DL, VT));
6582 // fold (aext (load x)) -> (aext (truncate (extload x)))
6583 // None of the supported targets knows how to perform load and any_ext
6584 // on vectors in one instruction. We only perform this transformation on
6586 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
6587 ISD::isUNINDEXEDLoad(N0.getNode()) &&
6588 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
6589 bool DoXform = true;
6590 SmallVector<SDNode*, 4> SetCCs;
6591 if (!N0.hasOneUse())
6592 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
6594 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6595 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
6597 LN0->getBasePtr(), N0.getValueType(),
6598 LN0->getMemOperand());
6599 CombineTo(N, ExtLoad);
6600 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
6601 N0.getValueType(), ExtLoad);
6602 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
6603 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
6605 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6609 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
6610 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
6611 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
6612 if (N0.getOpcode() == ISD::LOAD &&
6613 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
6615 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6616 ISD::LoadExtType ExtType = LN0->getExtensionType();
6617 EVT MemVT = LN0->getMemoryVT();
6618 if (!LegalOperations || TLI.isLoadExtLegal(ExtType, VT, MemVT)) {
6619 SDValue ExtLoad = DAG.getExtLoad(ExtType, SDLoc(N),
6620 VT, LN0->getChain(), LN0->getBasePtr(),
6621 MemVT, LN0->getMemOperand());
6622 CombineTo(N, ExtLoad);
6623 CombineTo(N0.getNode(),
6624 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
6625 N0.getValueType(), ExtLoad),
6626 ExtLoad.getValue(1));
6627 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6631 if (N0.getOpcode() == ISD::SETCC) {
6633 // aext(setcc) -> vsetcc
6634 // aext(setcc) -> truncate(vsetcc)
6635 // aext(setcc) -> aext(vsetcc)
6636 // Only do this before legalize for now.
6637 if (VT.isVector() && !LegalOperations) {
6638 EVT N0VT = N0.getOperand(0).getValueType();
6639 // We know that the # elements of the results is the same as the
6640 // # elements of the compare (and the # elements of the compare result
6641 // for that matter). Check to see that they are the same size. If so,
6642 // we know that the element size of the sext'd result matches the
6643 // element size of the compare operands.
6644 if (VT.getSizeInBits() == N0VT.getSizeInBits())
6645 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
6647 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6648 // If the desired elements are smaller or larger than the source
6649 // elements we can use a matching integer vector type and then
6650 // truncate/any extend
6652 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
6654 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
6656 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6657 return DAG.getAnyExtOrTrunc(VsetCC, SDLoc(N), VT);
6661 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
6664 SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1),
6665 DAG.getConstant(1, DL, VT), DAG.getConstant(0, DL, VT),
6666 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
6674 /// See if the specified operand can be simplified with the knowledge that only
6675 /// the bits specified by Mask are used. If so, return the simpler operand,
6676 /// otherwise return a null SDValue.
6677 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
6678 switch (V.getOpcode()) {
6680 case ISD::Constant: {
6681 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
6682 assert(CV && "Const value should be ConstSDNode.");
6683 const APInt &CVal = CV->getAPIntValue();
6684 APInt NewVal = CVal & Mask;
6686 return DAG.getConstant(NewVal, SDLoc(V), V.getValueType());
6691 // If the LHS or RHS don't contribute bits to the or, drop them.
6692 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
6693 return V.getOperand(1);
6694 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
6695 return V.getOperand(0);
6698 // Only look at single-use SRLs.
6699 if (!V.getNode()->hasOneUse())
6701 if (ConstantSDNode *RHSC = getAsNonOpaqueConstant(V.getOperand(1))) {
6702 // See if we can recursively simplify the LHS.
6703 unsigned Amt = RHSC->getZExtValue();
6705 // Watch out for shift count overflow though.
6706 if (Amt >= Mask.getBitWidth()) break;
6707 APInt NewMask = Mask << Amt;
6708 if (SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask))
6709 return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(),
6710 SimplifyLHS, V.getOperand(1));
6716 /// If the result of a wider load is shifted to right of N bits and then
6717 /// truncated to a narrower type and where N is a multiple of number of bits of
6718 /// the narrower type, transform it to a narrower load from address + N / num of
6719 /// bits of new type. If the result is to be extended, also fold the extension
6720 /// to form a extending load.
6721 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
6722 unsigned Opc = N->getOpcode();
6724 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
6725 SDValue N0 = N->getOperand(0);
6726 EVT VT = N->getValueType(0);
6729 // This transformation isn't valid for vector loads.
6733 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
6735 if (Opc == ISD::SIGN_EXTEND_INREG) {
6736 ExtType = ISD::SEXTLOAD;
6737 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
6738 } else if (Opc == ISD::SRL) {
6739 // Another special-case: SRL is basically zero-extending a narrower value.
6740 ExtType = ISD::ZEXTLOAD;
6742 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
6743 if (!N01) return SDValue();
6744 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
6745 VT.getSizeInBits() - N01->getZExtValue());
6747 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, VT, ExtVT))
6750 unsigned EVTBits = ExtVT.getSizeInBits();
6752 // Do not generate loads of non-round integer types since these can
6753 // be expensive (and would be wrong if the type is not byte sized).
6754 if (!ExtVT.isRound())
6758 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
6759 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
6760 ShAmt = N01->getZExtValue();
6761 // Is the shift amount a multiple of size of VT?
6762 if ((ShAmt & (EVTBits-1)) == 0) {
6763 N0 = N0.getOperand(0);
6764 // Is the load width a multiple of size of VT?
6765 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
6769 // At this point, we must have a load or else we can't do the transform.
6770 if (!isa<LoadSDNode>(N0)) return SDValue();
6772 // Because a SRL must be assumed to *need* to zero-extend the high bits
6773 // (as opposed to anyext the high bits), we can't combine the zextload
6774 // lowering of SRL and an sextload.
6775 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD)
6778 // If the shift amount is larger than the input type then we're not
6779 // accessing any of the loaded bytes. If the load was a zextload/extload
6780 // then the result of the shift+trunc is zero/undef (handled elsewhere).
6781 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
6786 // If the load is shifted left (and the result isn't shifted back right),
6787 // we can fold the truncate through the shift.
6788 unsigned ShLeftAmt = 0;
6789 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
6790 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
6791 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
6792 ShLeftAmt = N01->getZExtValue();
6793 N0 = N0.getOperand(0);
6797 // If we haven't found a load, we can't narrow it. Don't transform one with
6798 // multiple uses, this would require adding a new load.
6799 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse())
6802 // Don't change the width of a volatile load.
6803 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6804 if (LN0->isVolatile())
6807 // Verify that we are actually reducing a load width here.
6808 if (LN0->getMemoryVT().getSizeInBits() < EVTBits)
6811 // For the transform to be legal, the load must produce only two values
6812 // (the value loaded and the chain). Don't transform a pre-increment
6813 // load, for example, which produces an extra value. Otherwise the
6814 // transformation is not equivalent, and the downstream logic to replace
6815 // uses gets things wrong.
6816 if (LN0->getNumValues() > 2)
6819 // If the load that we're shrinking is an extload and we're not just
6820 // discarding the extension we can't simply shrink the load. Bail.
6821 // TODO: It would be possible to merge the extensions in some cases.
6822 if (LN0->getExtensionType() != ISD::NON_EXTLOAD &&
6823 LN0->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits() + ShAmt)
6826 if (!TLI.shouldReduceLoadWidth(LN0, ExtType, ExtVT))
6829 EVT PtrType = N0.getOperand(1).getValueType();
6831 if (PtrType == MVT::Untyped || PtrType.isExtended())
6832 // It's not possible to generate a constant of extended or untyped type.
6835 // For big endian targets, we need to adjust the offset to the pointer to
6836 // load the correct bytes.
6837 if (DAG.getDataLayout().isBigEndian()) {
6838 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
6839 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
6840 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
6843 uint64_t PtrOff = ShAmt / 8;
6844 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
6846 SDValue NewPtr = DAG.getNode(ISD::ADD, DL,
6847 PtrType, LN0->getBasePtr(),
6848 DAG.getConstant(PtrOff, DL, PtrType));
6849 AddToWorklist(NewPtr.getNode());
6852 if (ExtType == ISD::NON_EXTLOAD)
6853 Load = DAG.getLoad(VT, SDLoc(N0), LN0->getChain(), NewPtr,
6854 LN0->getPointerInfo().getWithOffset(PtrOff),
6855 LN0->isVolatile(), LN0->isNonTemporal(),
6856 LN0->isInvariant(), NewAlign, LN0->getAAInfo());
6858 Load = DAG.getExtLoad(ExtType, SDLoc(N0), VT, LN0->getChain(),NewPtr,
6859 LN0->getPointerInfo().getWithOffset(PtrOff),
6860 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
6861 LN0->isInvariant(), NewAlign, LN0->getAAInfo());
6863 // Replace the old load's chain with the new load's chain.
6864 WorklistRemover DeadNodes(*this);
6865 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
6867 // Shift the result left, if we've swallowed a left shift.
6868 SDValue Result = Load;
6869 if (ShLeftAmt != 0) {
6870 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
6871 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
6873 // If the shift amount is as large as the result size (but, presumably,
6874 // no larger than the source) then the useful bits of the result are
6875 // zero; we can't simply return the shortened shift, because the result
6876 // of that operation is undefined.
6878 if (ShLeftAmt >= VT.getSizeInBits())
6879 Result = DAG.getConstant(0, DL, VT);
6881 Result = DAG.getNode(ISD::SHL, DL, VT,
6882 Result, DAG.getConstant(ShLeftAmt, DL, ShImmTy));
6885 // Return the new loaded value.
6889 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
6890 SDValue N0 = N->getOperand(0);
6891 SDValue N1 = N->getOperand(1);
6892 EVT VT = N->getValueType(0);
6893 EVT EVT = cast<VTSDNode>(N1)->getVT();
6894 unsigned VTBits = VT.getScalarType().getSizeInBits();
6895 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
6898 return DAG.getUNDEF(VT);
6900 // fold (sext_in_reg c1) -> c1
6901 if (isConstantIntBuildVectorOrConstantInt(N0))
6902 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1);
6904 // If the input is already sign extended, just drop the extension.
6905 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
6908 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
6909 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
6910 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT()))
6911 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
6912 N0.getOperand(0), N1);
6914 // fold (sext_in_reg (sext x)) -> (sext x)
6915 // fold (sext_in_reg (aext x)) -> (sext x)
6916 // if x is small enough.
6917 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
6918 SDValue N00 = N0.getOperand(0);
6919 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
6920 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
6921 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1);
6924 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
6925 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
6926 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT);
6928 // fold operands of sext_in_reg based on knowledge that the top bits are not
6930 if (SimplifyDemandedBits(SDValue(N, 0)))
6931 return SDValue(N, 0);
6933 // fold (sext_in_reg (load x)) -> (smaller sextload x)
6934 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
6935 if (SDValue NarrowLoad = ReduceLoadWidth(N))
6938 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
6939 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
6940 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
6941 if (N0.getOpcode() == ISD::SRL) {
6942 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
6943 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
6944 // We can turn this into an SRA iff the input to the SRL is already sign
6946 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
6947 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
6948 return DAG.getNode(ISD::SRA, SDLoc(N), VT,
6949 N0.getOperand(0), N0.getOperand(1));
6953 // fold (sext_inreg (extload x)) -> (sextload x)
6954 if (ISD::isEXTLoad(N0.getNode()) &&
6955 ISD::isUNINDEXEDLoad(N0.getNode()) &&
6956 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
6957 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6958 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, EVT))) {
6959 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6960 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
6962 LN0->getBasePtr(), EVT,
6963 LN0->getMemOperand());
6964 CombineTo(N, ExtLoad);
6965 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
6966 AddToWorklist(ExtLoad.getNode());
6967 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6969 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
6970 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
6972 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
6973 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6974 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, EVT))) {
6975 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6976 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
6978 LN0->getBasePtr(), EVT,
6979 LN0->getMemOperand());
6980 CombineTo(N, ExtLoad);
6981 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
6982 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6985 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
6986 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
6987 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
6988 N0.getOperand(1), false);
6989 if (BSwap.getNode())
6990 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
6997 SDValue DAGCombiner::visitSIGN_EXTEND_VECTOR_INREG(SDNode *N) {
6998 SDValue N0 = N->getOperand(0);
6999 EVT VT = N->getValueType(0);
7001 if (N0.getOpcode() == ISD::UNDEF)
7002 return DAG.getUNDEF(VT);
7004 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
7006 return SDValue(Res, 0);
7011 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
7012 SDValue N0 = N->getOperand(0);
7013 EVT VT = N->getValueType(0);
7014 bool isLE = DAG.getDataLayout().isLittleEndian();
7017 if (N0.getValueType() == N->getValueType(0))
7019 // fold (truncate c1) -> c1
7020 if (isConstantIntBuildVectorOrConstantInt(N0))
7021 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0);
7022 // fold (truncate (truncate x)) -> (truncate x)
7023 if (N0.getOpcode() == ISD::TRUNCATE)
7024 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
7025 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
7026 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
7027 N0.getOpcode() == ISD::SIGN_EXTEND ||
7028 N0.getOpcode() == ISD::ANY_EXTEND) {
7029 if (N0.getOperand(0).getValueType().bitsLT(VT))
7030 // if the source is smaller than the dest, we still need an extend
7031 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
7033 if (N0.getOperand(0).getValueType().bitsGT(VT))
7034 // if the source is larger than the dest, than we just need the truncate
7035 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
7036 // if the source and dest are the same type, we can drop both the extend
7037 // and the truncate.
7038 return N0.getOperand(0);
7041 // Fold extract-and-trunc into a narrow extract. For example:
7042 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
7043 // i32 y = TRUNCATE(i64 x)
7045 // v16i8 b = BITCAST (v2i64 val)
7046 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
7048 // Note: We only run this optimization after type legalization (which often
7049 // creates this pattern) and before operation legalization after which
7050 // we need to be more careful about the vector instructions that we generate.
7051 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7052 LegalTypes && !LegalOperations && N0->hasOneUse() && VT != MVT::i1) {
7054 EVT VecTy = N0.getOperand(0).getValueType();
7055 EVT ExTy = N0.getValueType();
7056 EVT TrTy = N->getValueType(0);
7058 unsigned NumElem = VecTy.getVectorNumElements();
7059 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
7061 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
7062 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
7064 SDValue EltNo = N0->getOperand(1);
7065 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
7066 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7067 EVT IndexTy = TLI.getVectorIdxTy(DAG.getDataLayout());
7068 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
7070 SDValue V = DAG.getNode(ISD::BITCAST, SDLoc(N),
7071 NVT, N0.getOperand(0));
7074 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
7076 DAG.getConstant(Index, DL, IndexTy));
7080 // trunc (select c, a, b) -> select c, (trunc a), (trunc b)
7081 if (N0.getOpcode() == ISD::SELECT) {
7082 EVT SrcVT = N0.getValueType();
7083 if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) &&
7084 TLI.isTruncateFree(SrcVT, VT)) {
7086 SDValue Cond = N0.getOperand(0);
7087 SDValue TruncOp0 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
7088 SDValue TruncOp1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(2));
7089 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, Cond, TruncOp0, TruncOp1);
7093 // Fold a series of buildvector, bitcast, and truncate if possible.
7095 // (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to
7096 // (2xi32 (buildvector x, y)).
7097 if (Level == AfterLegalizeVectorOps && VT.isVector() &&
7098 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
7099 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
7100 N0.getOperand(0).hasOneUse()) {
7102 SDValue BuildVect = N0.getOperand(0);
7103 EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType();
7104 EVT TruncVecEltTy = VT.getVectorElementType();
7106 // Check that the element types match.
7107 if (BuildVectEltTy == TruncVecEltTy) {
7108 // Now we only need to compute the offset of the truncated elements.
7109 unsigned BuildVecNumElts = BuildVect.getNumOperands();
7110 unsigned TruncVecNumElts = VT.getVectorNumElements();
7111 unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts;
7113 assert((BuildVecNumElts % TruncVecNumElts) == 0 &&
7114 "Invalid number of elements");
7116 SmallVector<SDValue, 8> Opnds;
7117 for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset)
7118 Opnds.push_back(BuildVect.getOperand(i));
7120 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
7124 // See if we can simplify the input to this truncate through knowledge that
7125 // only the low bits are being used.
7126 // For example "trunc (or (shl x, 8), y)" // -> trunc y
7127 // Currently we only perform this optimization on scalars because vectors
7128 // may have different active low bits.
7129 if (!VT.isVector()) {
7131 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
7132 VT.getSizeInBits()));
7133 if (Shorter.getNode())
7134 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Shorter);
7136 // fold (truncate (load x)) -> (smaller load x)
7137 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
7138 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
7139 if (SDValue Reduced = ReduceLoadWidth(N))
7142 // Handle the case where the load remains an extending load even
7143 // after truncation.
7144 if (N0.hasOneUse() && ISD::isUNINDEXEDLoad(N0.getNode())) {
7145 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7146 if (!LN0->isVolatile() &&
7147 LN0->getMemoryVT().getStoreSizeInBits() < VT.getSizeInBits()) {
7148 SDValue NewLoad = DAG.getExtLoad(LN0->getExtensionType(), SDLoc(LN0),
7149 VT, LN0->getChain(), LN0->getBasePtr(),
7151 LN0->getMemOperand());
7152 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLoad.getValue(1));
7157 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)),
7158 // where ... are all 'undef'.
7159 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
7160 SmallVector<EVT, 8> VTs;
7163 unsigned NumDefs = 0;
7165 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
7166 SDValue X = N0.getOperand(i);
7167 if (X.getOpcode() != ISD::UNDEF) {
7172 // Stop if more than one members are non-undef.
7175 VTs.push_back(EVT::getVectorVT(*DAG.getContext(),
7176 VT.getVectorElementType(),
7177 X.getValueType().getVectorNumElements()));
7181 return DAG.getUNDEF(VT);
7184 assert(V.getNode() && "The single defined operand is empty!");
7185 SmallVector<SDValue, 8> Opnds;
7186 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
7188 Opnds.push_back(DAG.getUNDEF(VTs[i]));
7191 SDValue NV = DAG.getNode(ISD::TRUNCATE, SDLoc(V), VTs[i], V);
7192 AddToWorklist(NV.getNode());
7193 Opnds.push_back(NV);
7195 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds);
7199 // Simplify the operands using demanded-bits information.
7200 if (!VT.isVector() &&
7201 SimplifyDemandedBits(SDValue(N, 0)))
7202 return SDValue(N, 0);
7207 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
7208 SDValue Elt = N->getOperand(i);
7209 if (Elt.getOpcode() != ISD::MERGE_VALUES)
7210 return Elt.getNode();
7211 return Elt.getOperand(Elt.getResNo()).getNode();
7214 /// build_pair (load, load) -> load
7215 /// if load locations are consecutive.
7216 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
7217 assert(N->getOpcode() == ISD::BUILD_PAIR);
7219 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
7220 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
7221 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
7222 LD1->getAddressSpace() != LD2->getAddressSpace())
7224 EVT LD1VT = LD1->getValueType(0);
7226 if (ISD::isNON_EXTLoad(LD2) &&
7228 // If both are volatile this would reduce the number of volatile loads.
7229 // If one is volatile it might be ok, but play conservative and bail out.
7230 !LD1->isVolatile() &&
7231 !LD2->isVolatile() &&
7232 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
7233 unsigned Align = LD1->getAlignment();
7234 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
7235 VT.getTypeForEVT(*DAG.getContext()));
7237 if (NewAlign <= Align &&
7238 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
7239 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(),
7240 LD1->getBasePtr(), LD1->getPointerInfo(),
7241 false, false, false, Align);
7247 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
7248 SDValue N0 = N->getOperand(0);
7249 EVT VT = N->getValueType(0);
7251 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
7252 // Only do this before legalize, since afterward the target may be depending
7253 // on the bitconvert.
7254 // First check to see if this is all constant.
7256 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
7258 bool isSimple = cast<BuildVectorSDNode>(N0)->isConstant();
7260 EVT DestEltVT = N->getValueType(0).getVectorElementType();
7261 assert(!DestEltVT.isVector() &&
7262 "Element type of vector ValueType must not be vector!");
7264 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
7267 // If the input is a constant, let getNode fold it.
7268 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
7269 // If we can't allow illegal operations, we need to check that this is just
7270 // a fp -> int or int -> conversion and that the resulting operation will
7272 if (!LegalOperations ||
7273 (isa<ConstantSDNode>(N0) && VT.isFloatingPoint() && !VT.isVector() &&
7274 TLI.isOperationLegal(ISD::ConstantFP, VT)) ||
7275 (isa<ConstantFPSDNode>(N0) && VT.isInteger() && !VT.isVector() &&
7276 TLI.isOperationLegal(ISD::Constant, VT)))
7277 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, N0);
7280 // (conv (conv x, t1), t2) -> (conv x, t2)
7281 if (N0.getOpcode() == ISD::BITCAST)
7282 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT,
7285 // fold (conv (load x)) -> (load (conv*)x)
7286 // If the resultant load doesn't need a higher alignment than the original!
7287 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7288 // Do not change the width of a volatile load.
7289 !cast<LoadSDNode>(N0)->isVolatile() &&
7290 // Do not remove the cast if the types differ in endian layout.
7291 TLI.hasBigEndianPartOrdering(N0.getValueType(), DAG.getDataLayout()) ==
7292 TLI.hasBigEndianPartOrdering(VT, DAG.getDataLayout()) &&
7293 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)) &&
7294 TLI.isLoadBitCastBeneficial(N0.getValueType(), VT)) {
7295 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7296 unsigned Align = DAG.getDataLayout().getABITypeAlignment(
7297 VT.getTypeForEVT(*DAG.getContext()));
7298 unsigned OrigAlign = LN0->getAlignment();
7300 if (Align <= OrigAlign) {
7301 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(),
7302 LN0->getBasePtr(), LN0->getPointerInfo(),
7303 LN0->isVolatile(), LN0->isNonTemporal(),
7304 LN0->isInvariant(), OrigAlign,
7306 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
7311 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
7312 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
7313 // This often reduces constant pool loads.
7314 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
7315 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
7316 N0.getNode()->hasOneUse() && VT.isInteger() &&
7317 !VT.isVector() && !N0.getValueType().isVector()) {
7318 SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT,
7320 AddToWorklist(NewConv.getNode());
7323 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
7324 if (N0.getOpcode() == ISD::FNEG)
7325 return DAG.getNode(ISD::XOR, DL, VT,
7326 NewConv, DAG.getConstant(SignBit, DL, VT));
7327 assert(N0.getOpcode() == ISD::FABS);
7328 return DAG.getNode(ISD::AND, DL, VT,
7329 NewConv, DAG.getConstant(~SignBit, DL, VT));
7332 // fold (bitconvert (fcopysign cst, x)) ->
7333 // (or (and (bitconvert x), sign), (and cst, (not sign)))
7334 // Note that we don't handle (copysign x, cst) because this can always be
7335 // folded to an fneg or fabs.
7336 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
7337 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
7338 VT.isInteger() && !VT.isVector()) {
7339 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
7340 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
7341 if (isTypeLegal(IntXVT)) {
7342 SDValue X = DAG.getNode(ISD::BITCAST, SDLoc(N0),
7343 IntXVT, N0.getOperand(1));
7344 AddToWorklist(X.getNode());
7346 // If X has a different width than the result/lhs, sext it or truncate it.
7347 unsigned VTWidth = VT.getSizeInBits();
7348 if (OrigXWidth < VTWidth) {
7349 X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X);
7350 AddToWorklist(X.getNode());
7351 } else if (OrigXWidth > VTWidth) {
7352 // To get the sign bit in the right place, we have to shift it right
7353 // before truncating.
7355 X = DAG.getNode(ISD::SRL, DL,
7356 X.getValueType(), X,
7357 DAG.getConstant(OrigXWidth-VTWidth, DL,
7359 AddToWorklist(X.getNode());
7360 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
7361 AddToWorklist(X.getNode());
7364 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
7365 X = DAG.getNode(ISD::AND, SDLoc(X), VT,
7366 X, DAG.getConstant(SignBit, SDLoc(X), VT));
7367 AddToWorklist(X.getNode());
7369 SDValue Cst = DAG.getNode(ISD::BITCAST, SDLoc(N0),
7370 VT, N0.getOperand(0));
7371 Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT,
7372 Cst, DAG.getConstant(~SignBit, SDLoc(Cst), VT));
7373 AddToWorklist(Cst.getNode());
7375 return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst);
7379 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
7380 if (N0.getOpcode() == ISD::BUILD_PAIR)
7381 if (SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT))
7384 // Remove double bitcasts from shuffles - this is often a legacy of
7385 // XformToShuffleWithZero being used to combine bitmaskings (of
7386 // float vectors bitcast to integer vectors) into shuffles.
7387 // bitcast(shuffle(bitcast(s0),bitcast(s1))) -> shuffle(s0,s1)
7388 if (Level < AfterLegalizeDAG && TLI.isTypeLegal(VT) && VT.isVector() &&
7389 N0->getOpcode() == ISD::VECTOR_SHUFFLE &&
7390 VT.getVectorNumElements() >= N0.getValueType().getVectorNumElements() &&
7391 !(VT.getVectorNumElements() % N0.getValueType().getVectorNumElements())) {
7392 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N0);
7394 // If operands are a bitcast, peek through if it casts the original VT.
7395 // If operands are a constant, just bitcast back to original VT.
7396 auto PeekThroughBitcast = [&](SDValue Op) {
7397 if (Op.getOpcode() == ISD::BITCAST &&
7398 Op.getOperand(0).getValueType() == VT)
7399 return SDValue(Op.getOperand(0));
7400 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) ||
7401 ISD::isBuildVectorOfConstantFPSDNodes(Op.getNode()))
7402 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
7406 SDValue SV0 = PeekThroughBitcast(N0->getOperand(0));
7407 SDValue SV1 = PeekThroughBitcast(N0->getOperand(1));
7412 VT.getVectorNumElements() / N0.getValueType().getVectorNumElements();
7413 SmallVector<int, 8> NewMask;
7414 for (int M : SVN->getMask())
7415 for (int i = 0; i != MaskScale; ++i)
7416 NewMask.push_back(M < 0 ? -1 : M * MaskScale + i);
7418 bool LegalMask = TLI.isShuffleMaskLegal(NewMask, VT);
7420 std::swap(SV0, SV1);
7421 ShuffleVectorSDNode::commuteMask(NewMask);
7422 LegalMask = TLI.isShuffleMaskLegal(NewMask, VT);
7426 return DAG.getVectorShuffle(VT, SDLoc(N), SV0, SV1, NewMask);
7432 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
7433 EVT VT = N->getValueType(0);
7434 return CombineConsecutiveLoads(N, VT);
7437 /// We know that BV is a build_vector node with Constant, ConstantFP or Undef
7438 /// operands. DstEltVT indicates the destination element value type.
7439 SDValue DAGCombiner::
7440 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
7441 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
7443 // If this is already the right type, we're done.
7444 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
7446 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
7447 unsigned DstBitSize = DstEltVT.getSizeInBits();
7449 // If this is a conversion of N elements of one type to N elements of another
7450 // type, convert each element. This handles FP<->INT cases.
7451 if (SrcBitSize == DstBitSize) {
7452 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
7453 BV->getValueType(0).getVectorNumElements());
7455 // Due to the FP element handling below calling this routine recursively,
7456 // we can end up with a scalar-to-vector node here.
7457 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
7458 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
7459 DAG.getNode(ISD::BITCAST, SDLoc(BV),
7460 DstEltVT, BV->getOperand(0)));
7462 SmallVector<SDValue, 8> Ops;
7463 for (SDValue Op : BV->op_values()) {
7464 // If the vector element type is not legal, the BUILD_VECTOR operands
7465 // are promoted and implicitly truncated. Make that explicit here.
7466 if (Op.getValueType() != SrcEltVT)
7467 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(BV), SrcEltVT, Op);
7468 Ops.push_back(DAG.getNode(ISD::BITCAST, SDLoc(BV),
7470 AddToWorklist(Ops.back().getNode());
7472 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
7475 // Otherwise, we're growing or shrinking the elements. To avoid having to
7476 // handle annoying details of growing/shrinking FP values, we convert them to
7478 if (SrcEltVT.isFloatingPoint()) {
7479 // Convert the input float vector to a int vector where the elements are the
7481 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
7482 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
7486 // Now we know the input is an integer vector. If the output is a FP type,
7487 // convert to integer first, then to FP of the right size.
7488 if (DstEltVT.isFloatingPoint()) {
7489 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
7490 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
7492 // Next, convert to FP elements of the same size.
7493 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
7498 // Okay, we know the src/dst types are both integers of differing types.
7499 // Handling growing first.
7500 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
7501 if (SrcBitSize < DstBitSize) {
7502 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
7504 SmallVector<SDValue, 8> Ops;
7505 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
7506 i += NumInputsPerOutput) {
7507 bool isLE = DAG.getDataLayout().isLittleEndian();
7508 APInt NewBits = APInt(DstBitSize, 0);
7509 bool EltIsUndef = true;
7510 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
7511 // Shift the previously computed bits over.
7512 NewBits <<= SrcBitSize;
7513 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
7514 if (Op.getOpcode() == ISD::UNDEF) continue;
7517 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
7518 zextOrTrunc(SrcBitSize).zext(DstBitSize);
7522 Ops.push_back(DAG.getUNDEF(DstEltVT));
7524 Ops.push_back(DAG.getConstant(NewBits, DL, DstEltVT));
7527 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
7528 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
7531 // Finally, this must be the case where we are shrinking elements: each input
7532 // turns into multiple outputs.
7533 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
7534 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
7535 NumOutputsPerInput*BV->getNumOperands());
7536 SmallVector<SDValue, 8> Ops;
7538 for (const SDValue &Op : BV->op_values()) {
7539 if (Op.getOpcode() == ISD::UNDEF) {
7540 Ops.append(NumOutputsPerInput, DAG.getUNDEF(DstEltVT));
7544 APInt OpVal = cast<ConstantSDNode>(Op)->
7545 getAPIntValue().zextOrTrunc(SrcBitSize);
7547 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
7548 APInt ThisVal = OpVal.trunc(DstBitSize);
7549 Ops.push_back(DAG.getConstant(ThisVal, DL, DstEltVT));
7550 OpVal = OpVal.lshr(DstBitSize);
7553 // For big endian targets, swap the order of the pieces of each element.
7554 if (DAG.getDataLayout().isBigEndian())
7555 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
7558 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
7561 /// Try to perform FMA combining on a given FADD node.
7562 SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) {
7563 SDValue N0 = N->getOperand(0);
7564 SDValue N1 = N->getOperand(1);
7565 EVT VT = N->getValueType(0);
7568 const TargetOptions &Options = DAG.getTarget().Options;
7570 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath);
7572 // Floating-point multiply-add with intermediate rounding.
7573 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT));
7575 // Floating-point multiply-add without intermediate rounding.
7577 AllowFusion && TLI.isFMAFasterThanFMulAndFAdd(VT) &&
7578 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT));
7580 // No valid opcode, do not combine.
7581 if (!HasFMAD && !HasFMA)
7584 // Always prefer FMAD to FMA for precision.
7585 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
7586 bool Aggressive = TLI.enableAggressiveFMAFusion(VT);
7587 bool LookThroughFPExt = TLI.isFPExtFree(VT);
7589 // If we have two choices trying to fold (fadd (fmul u, v), (fmul x, y)),
7590 // prefer to fold the multiply with fewer uses.
7591 if (Aggressive && N0.getOpcode() == ISD::FMUL &&
7592 N1.getOpcode() == ISD::FMUL) {
7593 if (N0.getNode()->use_size() > N1.getNode()->use_size())
7597 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
7598 if (N0.getOpcode() == ISD::FMUL &&
7599 (Aggressive || N0->hasOneUse())) {
7600 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7601 N0.getOperand(0), N0.getOperand(1), N1);
7604 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
7605 // Note: Commutes FADD operands.
7606 if (N1.getOpcode() == ISD::FMUL &&
7607 (Aggressive || N1->hasOneUse())) {
7608 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7609 N1.getOperand(0), N1.getOperand(1), N0);
7612 // Look through FP_EXTEND nodes to do more combining.
7613 if (AllowFusion && LookThroughFPExt) {
7614 // fold (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)
7615 if (N0.getOpcode() == ISD::FP_EXTEND) {
7616 SDValue N00 = N0.getOperand(0);
7617 if (N00.getOpcode() == ISD::FMUL)
7618 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7619 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7621 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7622 N00.getOperand(1)), N1);
7625 // fold (fadd x, (fpext (fmul y, z))) -> (fma (fpext y), (fpext z), x)
7626 // Note: Commutes FADD operands.
7627 if (N1.getOpcode() == ISD::FP_EXTEND) {
7628 SDValue N10 = N1.getOperand(0);
7629 if (N10.getOpcode() == ISD::FMUL)
7630 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7631 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7633 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7634 N10.getOperand(1)), N0);
7638 // More folding opportunities when target permits.
7639 if ((AllowFusion || HasFMAD) && Aggressive) {
7640 // fold (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, z))
7641 if (N0.getOpcode() == PreferredFusedOpcode &&
7642 N0.getOperand(2).getOpcode() == ISD::FMUL) {
7643 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7644 N0.getOperand(0), N0.getOperand(1),
7645 DAG.getNode(PreferredFusedOpcode, SL, VT,
7646 N0.getOperand(2).getOperand(0),
7647 N0.getOperand(2).getOperand(1),
7651 // fold (fadd x, (fma y, z, (fmul u, v)) -> (fma y, z (fma u, v, x))
7652 if (N1->getOpcode() == PreferredFusedOpcode &&
7653 N1.getOperand(2).getOpcode() == ISD::FMUL) {
7654 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7655 N1.getOperand(0), N1.getOperand(1),
7656 DAG.getNode(PreferredFusedOpcode, SL, VT,
7657 N1.getOperand(2).getOperand(0),
7658 N1.getOperand(2).getOperand(1),
7662 if (AllowFusion && LookThroughFPExt) {
7663 // fold (fadd (fma x, y, (fpext (fmul u, v))), z)
7664 // -> (fma x, y, (fma (fpext u), (fpext v), z))
7665 auto FoldFAddFMAFPExtFMul = [&] (
7666 SDValue X, SDValue Y, SDValue U, SDValue V, SDValue Z) {
7667 return DAG.getNode(PreferredFusedOpcode, SL, VT, X, Y,
7668 DAG.getNode(PreferredFusedOpcode, SL, VT,
7669 DAG.getNode(ISD::FP_EXTEND, SL, VT, U),
7670 DAG.getNode(ISD::FP_EXTEND, SL, VT, V),
7673 if (N0.getOpcode() == PreferredFusedOpcode) {
7674 SDValue N02 = N0.getOperand(2);
7675 if (N02.getOpcode() == ISD::FP_EXTEND) {
7676 SDValue N020 = N02.getOperand(0);
7677 if (N020.getOpcode() == ISD::FMUL)
7678 return FoldFAddFMAFPExtFMul(N0.getOperand(0), N0.getOperand(1),
7679 N020.getOperand(0), N020.getOperand(1),
7684 // fold (fadd (fpext (fma x, y, (fmul u, v))), z)
7685 // -> (fma (fpext x), (fpext y), (fma (fpext u), (fpext v), z))
7686 // FIXME: This turns two single-precision and one double-precision
7687 // operation into two double-precision operations, which might not be
7688 // interesting for all targets, especially GPUs.
7689 auto FoldFAddFPExtFMAFMul = [&] (
7690 SDValue X, SDValue Y, SDValue U, SDValue V, SDValue Z) {
7691 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7692 DAG.getNode(ISD::FP_EXTEND, SL, VT, X),
7693 DAG.getNode(ISD::FP_EXTEND, SL, VT, Y),
7694 DAG.getNode(PreferredFusedOpcode, SL, VT,
7695 DAG.getNode(ISD::FP_EXTEND, SL, VT, U),
7696 DAG.getNode(ISD::FP_EXTEND, SL, VT, V),
7699 if (N0.getOpcode() == ISD::FP_EXTEND) {
7700 SDValue N00 = N0.getOperand(0);
7701 if (N00.getOpcode() == PreferredFusedOpcode) {
7702 SDValue N002 = N00.getOperand(2);
7703 if (N002.getOpcode() == ISD::FMUL)
7704 return FoldFAddFPExtFMAFMul(N00.getOperand(0), N00.getOperand(1),
7705 N002.getOperand(0), N002.getOperand(1),
7710 // fold (fadd x, (fma y, z, (fpext (fmul u, v)))
7711 // -> (fma y, z, (fma (fpext u), (fpext v), x))
7712 if (N1.getOpcode() == PreferredFusedOpcode) {
7713 SDValue N12 = N1.getOperand(2);
7714 if (N12.getOpcode() == ISD::FP_EXTEND) {
7715 SDValue N120 = N12.getOperand(0);
7716 if (N120.getOpcode() == ISD::FMUL)
7717 return FoldFAddFMAFPExtFMul(N1.getOperand(0), N1.getOperand(1),
7718 N120.getOperand(0), N120.getOperand(1),
7723 // fold (fadd x, (fpext (fma y, z, (fmul u, v)))
7724 // -> (fma (fpext y), (fpext z), (fma (fpext u), (fpext v), x))
7725 // FIXME: This turns two single-precision and one double-precision
7726 // operation into two double-precision operations, which might not be
7727 // interesting for all targets, especially GPUs.
7728 if (N1.getOpcode() == ISD::FP_EXTEND) {
7729 SDValue N10 = N1.getOperand(0);
7730 if (N10.getOpcode() == PreferredFusedOpcode) {
7731 SDValue N102 = N10.getOperand(2);
7732 if (N102.getOpcode() == ISD::FMUL)
7733 return FoldFAddFPExtFMAFMul(N10.getOperand(0), N10.getOperand(1),
7734 N102.getOperand(0), N102.getOperand(1),
7744 /// Try to perform FMA combining on a given FSUB node.
7745 SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) {
7746 SDValue N0 = N->getOperand(0);
7747 SDValue N1 = N->getOperand(1);
7748 EVT VT = N->getValueType(0);
7751 const TargetOptions &Options = DAG.getTarget().Options;
7753 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath);
7755 // Floating-point multiply-add with intermediate rounding.
7756 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT));
7758 // Floating-point multiply-add without intermediate rounding.
7760 AllowFusion && TLI.isFMAFasterThanFMulAndFAdd(VT) &&
7761 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT));
7763 // No valid opcode, do not combine.
7764 if (!HasFMAD && !HasFMA)
7767 // Always prefer FMAD to FMA for precision.
7768 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
7769 bool Aggressive = TLI.enableAggressiveFMAFusion(VT);
7770 bool LookThroughFPExt = TLI.isFPExtFree(VT);
7772 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
7773 if (N0.getOpcode() == ISD::FMUL &&
7774 (Aggressive || N0->hasOneUse())) {
7775 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7776 N0.getOperand(0), N0.getOperand(1),
7777 DAG.getNode(ISD::FNEG, SL, VT, N1));
7780 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
7781 // Note: Commutes FSUB operands.
7782 if (N1.getOpcode() == ISD::FMUL &&
7783 (Aggressive || N1->hasOneUse()))
7784 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7785 DAG.getNode(ISD::FNEG, SL, VT,
7787 N1.getOperand(1), N0);
7789 // fold (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
7790 if (N0.getOpcode() == ISD::FNEG &&
7791 N0.getOperand(0).getOpcode() == ISD::FMUL &&
7792 (Aggressive || (N0->hasOneUse() && N0.getOperand(0).hasOneUse()))) {
7793 SDValue N00 = N0.getOperand(0).getOperand(0);
7794 SDValue N01 = N0.getOperand(0).getOperand(1);
7795 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7796 DAG.getNode(ISD::FNEG, SL, VT, N00), N01,
7797 DAG.getNode(ISD::FNEG, SL, VT, N1));
7800 // Look through FP_EXTEND nodes to do more combining.
7801 if (AllowFusion && LookThroughFPExt) {
7802 // fold (fsub (fpext (fmul x, y)), z)
7803 // -> (fma (fpext x), (fpext y), (fneg z))
7804 if (N0.getOpcode() == ISD::FP_EXTEND) {
7805 SDValue N00 = N0.getOperand(0);
7806 if (N00.getOpcode() == ISD::FMUL)
7807 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7808 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7810 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7812 DAG.getNode(ISD::FNEG, SL, VT, N1));
7815 // fold (fsub x, (fpext (fmul y, z)))
7816 // -> (fma (fneg (fpext y)), (fpext z), x)
7817 // Note: Commutes FSUB operands.
7818 if (N1.getOpcode() == ISD::FP_EXTEND) {
7819 SDValue N10 = N1.getOperand(0);
7820 if (N10.getOpcode() == ISD::FMUL)
7821 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7822 DAG.getNode(ISD::FNEG, SL, VT,
7823 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7824 N10.getOperand(0))),
7825 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7830 // fold (fsub (fpext (fneg (fmul, x, y))), z)
7831 // -> (fneg (fma (fpext x), (fpext y), z))
7832 // Note: This could be removed with appropriate canonicalization of the
7833 // input expression into (fneg (fadd (fpext (fmul, x, y)), z). However, the
7834 // orthogonal flags -fp-contract=fast and -enable-unsafe-fp-math prevent
7835 // from implementing the canonicalization in visitFSUB.
7836 if (N0.getOpcode() == ISD::FP_EXTEND) {
7837 SDValue N00 = N0.getOperand(0);
7838 if (N00.getOpcode() == ISD::FNEG) {
7839 SDValue N000 = N00.getOperand(0);
7840 if (N000.getOpcode() == ISD::FMUL) {
7841 return DAG.getNode(ISD::FNEG, SL, VT,
7842 DAG.getNode(PreferredFusedOpcode, SL, VT,
7843 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7844 N000.getOperand(0)),
7845 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7846 N000.getOperand(1)),
7852 // fold (fsub (fneg (fpext (fmul, x, y))), z)
7853 // -> (fneg (fma (fpext x)), (fpext y), z)
7854 // Note: This could be removed with appropriate canonicalization of the
7855 // input expression into (fneg (fadd (fpext (fmul, x, y)), z). However, the
7856 // orthogonal flags -fp-contract=fast and -enable-unsafe-fp-math prevent
7857 // from implementing the canonicalization in visitFSUB.
7858 if (N0.getOpcode() == ISD::FNEG) {
7859 SDValue N00 = N0.getOperand(0);
7860 if (N00.getOpcode() == ISD::FP_EXTEND) {
7861 SDValue N000 = N00.getOperand(0);
7862 if (N000.getOpcode() == ISD::FMUL) {
7863 return DAG.getNode(ISD::FNEG, SL, VT,
7864 DAG.getNode(PreferredFusedOpcode, SL, VT,
7865 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7866 N000.getOperand(0)),
7867 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7868 N000.getOperand(1)),
7876 // More folding opportunities when target permits.
7877 if ((AllowFusion || HasFMAD) && Aggressive) {
7878 // fold (fsub (fma x, y, (fmul u, v)), z)
7879 // -> (fma x, y (fma u, v, (fneg z)))
7880 if (N0.getOpcode() == PreferredFusedOpcode &&
7881 N0.getOperand(2).getOpcode() == ISD::FMUL) {
7882 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7883 N0.getOperand(0), N0.getOperand(1),
7884 DAG.getNode(PreferredFusedOpcode, SL, VT,
7885 N0.getOperand(2).getOperand(0),
7886 N0.getOperand(2).getOperand(1),
7887 DAG.getNode(ISD::FNEG, SL, VT,
7891 // fold (fsub x, (fma y, z, (fmul u, v)))
7892 // -> (fma (fneg y), z, (fma (fneg u), v, x))
7893 if (N1.getOpcode() == PreferredFusedOpcode &&
7894 N1.getOperand(2).getOpcode() == ISD::FMUL) {
7895 SDValue N20 = N1.getOperand(2).getOperand(0);
7896 SDValue N21 = N1.getOperand(2).getOperand(1);
7897 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7898 DAG.getNode(ISD::FNEG, SL, VT,
7901 DAG.getNode(PreferredFusedOpcode, SL, VT,
7902 DAG.getNode(ISD::FNEG, SL, VT, N20),
7907 if (AllowFusion && LookThroughFPExt) {
7908 // fold (fsub (fma x, y, (fpext (fmul u, v))), z)
7909 // -> (fma x, y (fma (fpext u), (fpext v), (fneg z)))
7910 if (N0.getOpcode() == PreferredFusedOpcode) {
7911 SDValue N02 = N0.getOperand(2);
7912 if (N02.getOpcode() == ISD::FP_EXTEND) {
7913 SDValue N020 = N02.getOperand(0);
7914 if (N020.getOpcode() == ISD::FMUL)
7915 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7916 N0.getOperand(0), N0.getOperand(1),
7917 DAG.getNode(PreferredFusedOpcode, SL, VT,
7918 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7919 N020.getOperand(0)),
7920 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7921 N020.getOperand(1)),
7922 DAG.getNode(ISD::FNEG, SL, VT,
7927 // fold (fsub (fpext (fma x, y, (fmul u, v))), z)
7928 // -> (fma (fpext x), (fpext y),
7929 // (fma (fpext u), (fpext v), (fneg z)))
7930 // FIXME: This turns two single-precision and one double-precision
7931 // operation into two double-precision operations, which might not be
7932 // interesting for all targets, especially GPUs.
7933 if (N0.getOpcode() == ISD::FP_EXTEND) {
7934 SDValue N00 = N0.getOperand(0);
7935 if (N00.getOpcode() == PreferredFusedOpcode) {
7936 SDValue N002 = N00.getOperand(2);
7937 if (N002.getOpcode() == ISD::FMUL)
7938 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7939 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7941 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7943 DAG.getNode(PreferredFusedOpcode, SL, VT,
7944 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7945 N002.getOperand(0)),
7946 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7947 N002.getOperand(1)),
7948 DAG.getNode(ISD::FNEG, SL, VT,
7953 // fold (fsub x, (fma y, z, (fpext (fmul u, v))))
7954 // -> (fma (fneg y), z, (fma (fneg (fpext u)), (fpext v), x))
7955 if (N1.getOpcode() == PreferredFusedOpcode &&
7956 N1.getOperand(2).getOpcode() == ISD::FP_EXTEND) {
7957 SDValue N120 = N1.getOperand(2).getOperand(0);
7958 if (N120.getOpcode() == ISD::FMUL) {
7959 SDValue N1200 = N120.getOperand(0);
7960 SDValue N1201 = N120.getOperand(1);
7961 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7962 DAG.getNode(ISD::FNEG, SL, VT, N1.getOperand(0)),
7964 DAG.getNode(PreferredFusedOpcode, SL, VT,
7965 DAG.getNode(ISD::FNEG, SL, VT,
7966 DAG.getNode(ISD::FP_EXTEND, SL,
7968 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7974 // fold (fsub x, (fpext (fma y, z, (fmul u, v))))
7975 // -> (fma (fneg (fpext y)), (fpext z),
7976 // (fma (fneg (fpext u)), (fpext v), x))
7977 // FIXME: This turns two single-precision and one double-precision
7978 // operation into two double-precision operations, which might not be
7979 // interesting for all targets, especially GPUs.
7980 if (N1.getOpcode() == ISD::FP_EXTEND &&
7981 N1.getOperand(0).getOpcode() == PreferredFusedOpcode) {
7982 SDValue N100 = N1.getOperand(0).getOperand(0);
7983 SDValue N101 = N1.getOperand(0).getOperand(1);
7984 SDValue N102 = N1.getOperand(0).getOperand(2);
7985 if (N102.getOpcode() == ISD::FMUL) {
7986 SDValue N1020 = N102.getOperand(0);
7987 SDValue N1021 = N102.getOperand(1);
7988 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7989 DAG.getNode(ISD::FNEG, SL, VT,
7990 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7992 DAG.getNode(ISD::FP_EXTEND, SL, VT, N101),
7993 DAG.getNode(PreferredFusedOpcode, SL, VT,
7994 DAG.getNode(ISD::FNEG, SL, VT,
7995 DAG.getNode(ISD::FP_EXTEND, SL,
7997 DAG.getNode(ISD::FP_EXTEND, SL, VT,
8008 /// Try to perform FMA combining on a given FMUL node.
8009 SDValue DAGCombiner::visitFMULForFMACombine(SDNode *N) {
8010 SDValue N0 = N->getOperand(0);
8011 SDValue N1 = N->getOperand(1);
8012 EVT VT = N->getValueType(0);
8015 assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation");
8017 const TargetOptions &Options = DAG.getTarget().Options;
8019 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath);
8021 // Floating-point multiply-add with intermediate rounding.
8022 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT));
8024 // Floating-point multiply-add without intermediate rounding.
8026 AllowFusion && TLI.isFMAFasterThanFMulAndFAdd(VT) &&
8027 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT));
8029 // No valid opcode, do not combine.
8030 if (!HasFMAD && !HasFMA)
8033 // Always prefer FMAD to FMA for precision.
8034 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
8035 bool Aggressive = TLI.enableAggressiveFMAFusion(VT);
8037 // fold (fmul (fadd x, +1.0), y) -> (fma x, y, y)
8038 // fold (fmul (fadd x, -1.0), y) -> (fma x, y, (fneg y))
8039 auto FuseFADD = [&](SDValue X, SDValue Y) {
8040 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) {
8041 auto XC1 = isConstOrConstSplatFP(X.getOperand(1));
8042 if (XC1 && XC1->isExactlyValue(+1.0))
8043 return DAG.getNode(PreferredFusedOpcode, SL, VT, X.getOperand(0), Y, Y);
8044 if (XC1 && XC1->isExactlyValue(-1.0))
8045 return DAG.getNode(PreferredFusedOpcode, SL, VT, X.getOperand(0), Y,
8046 DAG.getNode(ISD::FNEG, SL, VT, Y));
8051 if (SDValue FMA = FuseFADD(N0, N1))
8053 if (SDValue FMA = FuseFADD(N1, N0))
8056 // fold (fmul (fsub +1.0, x), y) -> (fma (fneg x), y, y)
8057 // fold (fmul (fsub -1.0, x), y) -> (fma (fneg x), y, (fneg y))
8058 // fold (fmul (fsub x, +1.0), y) -> (fma x, y, (fneg y))
8059 // fold (fmul (fsub x, -1.0), y) -> (fma x, y, y)
8060 auto FuseFSUB = [&](SDValue X, SDValue Y) {
8061 if (X.getOpcode() == ISD::FSUB && (Aggressive || X->hasOneUse())) {
8062 auto XC0 = isConstOrConstSplatFP(X.getOperand(0));
8063 if (XC0 && XC0->isExactlyValue(+1.0))
8064 return DAG.getNode(PreferredFusedOpcode, SL, VT,
8065 DAG.getNode(ISD::FNEG, SL, VT, X.getOperand(1)), Y,
8067 if (XC0 && XC0->isExactlyValue(-1.0))
8068 return DAG.getNode(PreferredFusedOpcode, SL, VT,
8069 DAG.getNode(ISD::FNEG, SL, VT, X.getOperand(1)), Y,
8070 DAG.getNode(ISD::FNEG, SL, VT, Y));
8072 auto XC1 = isConstOrConstSplatFP(X.getOperand(1));
8073 if (XC1 && XC1->isExactlyValue(+1.0))
8074 return DAG.getNode(PreferredFusedOpcode, SL, VT, X.getOperand(0), Y,
8075 DAG.getNode(ISD::FNEG, SL, VT, Y));
8076 if (XC1 && XC1->isExactlyValue(-1.0))
8077 return DAG.getNode(PreferredFusedOpcode, SL, VT, X.getOperand(0), Y, Y);
8082 if (SDValue FMA = FuseFSUB(N0, N1))
8084 if (SDValue FMA = FuseFSUB(N1, N0))
8090 SDValue DAGCombiner::visitFADD(SDNode *N) {
8091 SDValue N0 = N->getOperand(0);
8092 SDValue N1 = N->getOperand(1);
8093 bool N0CFP = isConstantFPBuildVectorOrConstantFP(N0);
8094 bool N1CFP = isConstantFPBuildVectorOrConstantFP(N1);
8095 EVT VT = N->getValueType(0);
8097 const TargetOptions &Options = DAG.getTarget().Options;
8098 const SDNodeFlags *Flags = &cast<BinaryWithFlagsSDNode>(N)->Flags;
8102 if (SDValue FoldedVOp = SimplifyVBinOp(N))
8105 // fold (fadd c1, c2) -> c1 + c2
8107 return DAG.getNode(ISD::FADD, DL, VT, N0, N1, Flags);
8109 // canonicalize constant to RHS
8110 if (N0CFP && !N1CFP)
8111 return DAG.getNode(ISD::FADD, DL, VT, N1, N0, Flags);
8113 // fold (fadd A, (fneg B)) -> (fsub A, B)
8114 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
8115 isNegatibleForFree(N1, LegalOperations, TLI, &Options) == 2)
8116 return DAG.getNode(ISD::FSUB, DL, VT, N0,
8117 GetNegatedExpression(N1, DAG, LegalOperations), Flags);
8119 // fold (fadd (fneg A), B) -> (fsub B, A)
8120 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
8121 isNegatibleForFree(N0, LegalOperations, TLI, &Options) == 2)
8122 return DAG.getNode(ISD::FSUB, DL, VT, N1,
8123 GetNegatedExpression(N0, DAG, LegalOperations), Flags);
8125 // If 'unsafe math' is enabled, fold lots of things.
8126 if (Options.UnsafeFPMath) {
8127 // No FP constant should be created after legalization as Instruction
8128 // Selection pass has a hard time dealing with FP constants.
8129 bool AllowNewConst = (Level < AfterLegalizeDAG);
8131 // fold (fadd A, 0) -> A
8132 if (ConstantFPSDNode *N1C = isConstOrConstSplatFP(N1))
8136 // fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
8137 if (N1CFP && N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
8138 isConstantFPBuildVectorOrConstantFP(N0.getOperand(1)))
8139 return DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(0),
8140 DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), N1,
8144 // If allowed, fold (fadd (fneg x), x) -> 0.0
8145 if (AllowNewConst && N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
8146 return DAG.getConstantFP(0.0, DL, VT);
8148 // If allowed, fold (fadd x, (fneg x)) -> 0.0
8149 if (AllowNewConst && N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
8150 return DAG.getConstantFP(0.0, DL, VT);
8152 // We can fold chains of FADD's of the same value into multiplications.
8153 // This transform is not safe in general because we are reducing the number
8154 // of rounding steps.
8155 if (TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && !N0CFP && !N1CFP) {
8156 if (N0.getOpcode() == ISD::FMUL) {
8157 bool CFP00 = isConstantFPBuildVectorOrConstantFP(N0.getOperand(0));
8158 bool CFP01 = isConstantFPBuildVectorOrConstantFP(N0.getOperand(1));
8160 // (fadd (fmul x, c), x) -> (fmul x, c+1)
8161 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
8162 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1),
8163 DAG.getConstantFP(1.0, DL, VT), Flags);
8164 return DAG.getNode(ISD::FMUL, DL, VT, N1, NewCFP, Flags);
8167 // (fadd (fmul x, c), (fadd x, x)) -> (fmul x, c+2)
8168 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
8169 N1.getOperand(0) == N1.getOperand(1) &&
8170 N0.getOperand(0) == N1.getOperand(0)) {
8171 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1),
8172 DAG.getConstantFP(2.0, DL, VT), Flags);
8173 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), NewCFP, Flags);
8177 if (N1.getOpcode() == ISD::FMUL) {
8178 bool CFP10 = isConstantFPBuildVectorOrConstantFP(N1.getOperand(0));
8179 bool CFP11 = isConstantFPBuildVectorOrConstantFP(N1.getOperand(1));
8181 // (fadd x, (fmul x, c)) -> (fmul x, c+1)
8182 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
8183 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N1.getOperand(1),
8184 DAG.getConstantFP(1.0, DL, VT), Flags);
8185 return DAG.getNode(ISD::FMUL, DL, VT, N0, NewCFP, Flags);
8188 // (fadd (fadd x, x), (fmul x, c)) -> (fmul x, c+2)
8189 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
8190 N0.getOperand(0) == N0.getOperand(1) &&
8191 N1.getOperand(0) == N0.getOperand(0)) {
8192 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N1.getOperand(1),
8193 DAG.getConstantFP(2.0, DL, VT), Flags);
8194 return DAG.getNode(ISD::FMUL, DL, VT, N1.getOperand(0), NewCFP, Flags);
8198 if (N0.getOpcode() == ISD::FADD && AllowNewConst) {
8199 bool CFP00 = isConstantFPBuildVectorOrConstantFP(N0.getOperand(0));
8200 // (fadd (fadd x, x), x) -> (fmul x, 3.0)
8201 if (!CFP00 && N0.getOperand(0) == N0.getOperand(1) &&
8202 (N0.getOperand(0) == N1)) {
8203 return DAG.getNode(ISD::FMUL, DL, VT,
8204 N1, DAG.getConstantFP(3.0, DL, VT), Flags);
8208 if (N1.getOpcode() == ISD::FADD && AllowNewConst) {
8209 bool CFP10 = isConstantFPBuildVectorOrConstantFP(N1.getOperand(0));
8210 // (fadd x, (fadd x, x)) -> (fmul x, 3.0)
8211 if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) &&
8212 N1.getOperand(0) == N0) {
8213 return DAG.getNode(ISD::FMUL, DL, VT,
8214 N0, DAG.getConstantFP(3.0, DL, VT), Flags);
8218 // (fadd (fadd x, x), (fadd x, x)) -> (fmul x, 4.0)
8219 if (AllowNewConst &&
8220 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
8221 N0.getOperand(0) == N0.getOperand(1) &&
8222 N1.getOperand(0) == N1.getOperand(1) &&
8223 N0.getOperand(0) == N1.getOperand(0)) {
8224 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0),
8225 DAG.getConstantFP(4.0, DL, VT), Flags);
8228 } // enable-unsafe-fp-math
8230 // FADD -> FMA combines:
8231 if (SDValue Fused = visitFADDForFMACombine(N)) {
8232 AddToWorklist(Fused.getNode());
8239 SDValue DAGCombiner::visitFSUB(SDNode *N) {
8240 SDValue N0 = N->getOperand(0);
8241 SDValue N1 = N->getOperand(1);
8242 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
8243 ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
8244 EVT VT = N->getValueType(0);
8246 const TargetOptions &Options = DAG.getTarget().Options;
8247 const SDNodeFlags *Flags = &cast<BinaryWithFlagsSDNode>(N)->Flags;
8251 if (SDValue FoldedVOp = SimplifyVBinOp(N))
8254 // fold (fsub c1, c2) -> c1-c2
8256 return DAG.getNode(ISD::FSUB, dl, VT, N0, N1, Flags);
8258 // fold (fsub A, (fneg B)) -> (fadd A, B)
8259 if (isNegatibleForFree(N1, LegalOperations, TLI, &Options))
8260 return DAG.getNode(ISD::FADD, dl, VT, N0,
8261 GetNegatedExpression(N1, DAG, LegalOperations), Flags);
8263 // If 'unsafe math' is enabled, fold lots of things.
8264 if (Options.UnsafeFPMath) {
8266 if (N1CFP && N1CFP->isZero())
8269 // (fsub 0, B) -> -B
8270 if (N0CFP && N0CFP->isZero()) {
8271 if (isNegatibleForFree(N1, LegalOperations, TLI, &Options))
8272 return GetNegatedExpression(N1, DAG, LegalOperations);
8273 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
8274 return DAG.getNode(ISD::FNEG, dl, VT, N1);
8277 // (fsub x, x) -> 0.0
8279 return DAG.getConstantFP(0.0f, dl, VT);
8281 // (fsub x, (fadd x, y)) -> (fneg y)
8282 // (fsub x, (fadd y, x)) -> (fneg y)
8283 if (N1.getOpcode() == ISD::FADD) {
8284 SDValue N10 = N1->getOperand(0);
8285 SDValue N11 = N1->getOperand(1);
8287 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, &Options))
8288 return GetNegatedExpression(N11, DAG, LegalOperations);
8290 if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, &Options))
8291 return GetNegatedExpression(N10, DAG, LegalOperations);
8295 // FSUB -> FMA combines:
8296 if (SDValue Fused = visitFSUBForFMACombine(N)) {
8297 AddToWorklist(Fused.getNode());
8304 SDValue DAGCombiner::visitFMUL(SDNode *N) {
8305 SDValue N0 = N->getOperand(0);
8306 SDValue N1 = N->getOperand(1);
8307 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
8308 ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
8309 EVT VT = N->getValueType(0);
8311 const TargetOptions &Options = DAG.getTarget().Options;
8312 const SDNodeFlags *Flags = &cast<BinaryWithFlagsSDNode>(N)->Flags;
8315 if (VT.isVector()) {
8316 // This just handles C1 * C2 for vectors. Other vector folds are below.
8317 if (SDValue FoldedVOp = SimplifyVBinOp(N))
8321 // fold (fmul c1, c2) -> c1*c2
8323 return DAG.getNode(ISD::FMUL, DL, VT, N0, N1, Flags);
8325 // canonicalize constant to RHS
8326 if (isConstantFPBuildVectorOrConstantFP(N0) &&
8327 !isConstantFPBuildVectorOrConstantFP(N1))
8328 return DAG.getNode(ISD::FMUL, DL, VT, N1, N0, Flags);
8330 // fold (fmul A, 1.0) -> A
8331 if (N1CFP && N1CFP->isExactlyValue(1.0))
8334 if (Options.UnsafeFPMath) {
8335 // fold (fmul A, 0) -> 0
8336 if (N1CFP && N1CFP->isZero())
8339 // fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
8340 if (N0.getOpcode() == ISD::FMUL) {
8341 // Fold scalars or any vector constants (not just splats).
8342 // This fold is done in general by InstCombine, but extra fmul insts
8343 // may have been generated during lowering.
8344 SDValue N00 = N0.getOperand(0);
8345 SDValue N01 = N0.getOperand(1);
8346 auto *BV1 = dyn_cast<BuildVectorSDNode>(N1);
8347 auto *BV00 = dyn_cast<BuildVectorSDNode>(N00);
8348 auto *BV01 = dyn_cast<BuildVectorSDNode>(N01);
8350 // Check 1: Make sure that the first operand of the inner multiply is NOT
8351 // a constant. Otherwise, we may induce infinite looping.
8352 if (!(isConstOrConstSplatFP(N00) || (BV00 && BV00->isConstant()))) {
8353 // Check 2: Make sure that the second operand of the inner multiply and
8354 // the second operand of the outer multiply are constants.
8355 if ((N1CFP && isConstOrConstSplatFP(N01)) ||
8356 (BV1 && BV01 && BV1->isConstant() && BV01->isConstant())) {
8357 SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, N01, N1, Flags);
8358 return DAG.getNode(ISD::FMUL, DL, VT, N00, MulConsts, Flags);
8363 // fold (fmul (fadd x, x), c) -> (fmul x, (fmul 2.0, c))
8364 // Undo the fmul 2.0, x -> fadd x, x transformation, since if it occurs
8365 // during an early run of DAGCombiner can prevent folding with fmuls
8366 // inserted during lowering.
8367 if (N0.getOpcode() == ISD::FADD &&
8368 (N0.getOperand(0) == N0.getOperand(1)) &&
8370 const SDValue Two = DAG.getConstantFP(2.0, DL, VT);
8371 SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, Two, N1, Flags);
8372 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), MulConsts, Flags);
8376 // fold (fmul X, 2.0) -> (fadd X, X)
8377 if (N1CFP && N1CFP->isExactlyValue(+2.0))
8378 return DAG.getNode(ISD::FADD, DL, VT, N0, N0, Flags);
8380 // fold (fmul X, -1.0) -> (fneg X)
8381 if (N1CFP && N1CFP->isExactlyValue(-1.0))
8382 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
8383 return DAG.getNode(ISD::FNEG, DL, VT, N0);
8385 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
8386 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, &Options)) {
8387 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, &Options)) {
8388 // Both can be negated for free, check to see if at least one is cheaper
8390 if (LHSNeg == 2 || RHSNeg == 2)
8391 return DAG.getNode(ISD::FMUL, DL, VT,
8392 GetNegatedExpression(N0, DAG, LegalOperations),
8393 GetNegatedExpression(N1, DAG, LegalOperations),
8398 // FMUL -> FMA combines:
8399 if (SDValue Fused = visitFMULForFMACombine(N)) {
8400 AddToWorklist(Fused.getNode());
8407 SDValue DAGCombiner::visitFMA(SDNode *N) {
8408 SDValue N0 = N->getOperand(0);
8409 SDValue N1 = N->getOperand(1);
8410 SDValue N2 = N->getOperand(2);
8411 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8412 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
8413 EVT VT = N->getValueType(0);
8415 const TargetOptions &Options = DAG.getTarget().Options;
8417 // Constant fold FMA.
8418 if (isa<ConstantFPSDNode>(N0) &&
8419 isa<ConstantFPSDNode>(N1) &&
8420 isa<ConstantFPSDNode>(N2)) {
8421 return DAG.getNode(ISD::FMA, dl, VT, N0, N1, N2);
8424 if (Options.UnsafeFPMath) {
8425 if (N0CFP && N0CFP->isZero())
8427 if (N1CFP && N1CFP->isZero())
8430 // TODO: The FMA node should have flags that propagate to these nodes.
8431 if (N0CFP && N0CFP->isExactlyValue(1.0))
8432 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N2);
8433 if (N1CFP && N1CFP->isExactlyValue(1.0))
8434 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2);
8436 // Canonicalize (fma c, x, y) -> (fma x, c, y)
8437 if (isConstantFPBuildVectorOrConstantFP(N0) &&
8438 !isConstantFPBuildVectorOrConstantFP(N1))
8439 return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2);
8441 // TODO: FMA nodes should have flags that propagate to the created nodes.
8442 // For now, create a Flags object for use with all unsafe math transforms.
8444 Flags.setUnsafeAlgebra(true);
8446 if (Options.UnsafeFPMath) {
8447 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
8448 if (N2.getOpcode() == ISD::FMUL && N0 == N2.getOperand(0) &&
8449 isConstantFPBuildVectorOrConstantFP(N1) &&
8450 isConstantFPBuildVectorOrConstantFP(N2.getOperand(1))) {
8451 return DAG.getNode(ISD::FMUL, dl, VT, N0,
8452 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1),
8456 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
8457 if (N0.getOpcode() == ISD::FMUL &&
8458 isConstantFPBuildVectorOrConstantFP(N1) &&
8459 isConstantFPBuildVectorOrConstantFP(N0.getOperand(1))) {
8460 return DAG.getNode(ISD::FMA, dl, VT,
8462 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1),
8468 // (fma x, 1, y) -> (fadd x, y)
8469 // (fma x, -1, y) -> (fadd (fneg x), y)
8471 if (N1CFP->isExactlyValue(1.0))
8472 // TODO: The FMA node should have flags that propagate to this node.
8473 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
8475 if (N1CFP->isExactlyValue(-1.0) &&
8476 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
8477 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
8478 AddToWorklist(RHSNeg.getNode());
8479 // TODO: The FMA node should have flags that propagate to this node.
8480 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
8484 if (Options.UnsafeFPMath) {
8485 // (fma x, c, x) -> (fmul x, (c+1))
8486 if (N1CFP && N0 == N2) {
8487 return DAG.getNode(ISD::FMUL, dl, VT, N0,
8488 DAG.getNode(ISD::FADD, dl, VT,
8489 N1, DAG.getConstantFP(1.0, dl, VT),
8493 // (fma x, c, (fneg x)) -> (fmul x, (c-1))
8494 if (N1CFP && N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) {
8495 return DAG.getNode(ISD::FMUL, dl, VT, N0,
8496 DAG.getNode(ISD::FADD, dl, VT,
8497 N1, DAG.getConstantFP(-1.0, dl, VT),
8505 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
8507 // E.g., (a / D; b / D;) -> (recip = 1.0 / D; a * recip; b * recip)
8508 // Notice that this is not always beneficial. One reason is different target
8509 // may have different costs for FDIV and FMUL, so sometimes the cost of two
8510 // FDIVs may be lower than the cost of one FDIV and two FMULs. Another reason
8511 // is the critical path is increased from "one FDIV" to "one FDIV + one FMUL".
8512 SDValue DAGCombiner::combineRepeatedFPDivisors(SDNode *N) {
8513 bool UnsafeMath = DAG.getTarget().Options.UnsafeFPMath;
8514 const SDNodeFlags *Flags = N->getFlags();
8515 if (!UnsafeMath && !Flags->hasAllowReciprocal())
8518 // Skip if current node is a reciprocal.
8519 SDValue N0 = N->getOperand(0);
8520 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8521 if (N0CFP && N0CFP->isExactlyValue(1.0))
8524 // Exit early if the target does not want this transform or if there can't
8525 // possibly be enough uses of the divisor to make the transform worthwhile.
8526 SDValue N1 = N->getOperand(1);
8527 unsigned MinUses = TLI.combineRepeatedFPDivisors();
8528 if (!MinUses || N1->use_size() < MinUses)
8531 // Find all FDIV users of the same divisor.
8532 // Use a set because duplicates may be present in the user list.
8533 SetVector<SDNode *> Users;
8534 for (auto *U : N1->uses()) {
8535 if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1) {
8536 // This division is eligible for optimization only if global unsafe math
8537 // is enabled or if this division allows reciprocal formation.
8538 if (UnsafeMath || U->getFlags()->hasAllowReciprocal())
8543 // Now that we have the actual number of divisor uses, make sure it meets
8544 // the minimum threshold specified by the target.
8545 if (Users.size() < MinUses)
8548 EVT VT = N->getValueType(0);
8550 SDValue FPOne = DAG.getConstantFP(1.0, DL, VT);
8551 SDValue Reciprocal = DAG.getNode(ISD::FDIV, DL, VT, FPOne, N1, Flags);
8553 // Dividend / Divisor -> Dividend * Reciprocal
8554 for (auto *U : Users) {
8555 SDValue Dividend = U->getOperand(0);
8556 if (Dividend != FPOne) {
8557 SDValue NewNode = DAG.getNode(ISD::FMUL, SDLoc(U), VT, Dividend,
8559 CombineTo(U, NewNode);
8560 } else if (U != Reciprocal.getNode()) {
8561 // In the absence of fast-math-flags, this user node is always the
8562 // same node as Reciprocal, but with FMF they may be different nodes.
8563 CombineTo(U, Reciprocal);
8566 return SDValue(N, 0); // N was replaced.
8569 SDValue DAGCombiner::visitFDIV(SDNode *N) {
8570 SDValue N0 = N->getOperand(0);
8571 SDValue N1 = N->getOperand(1);
8572 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8573 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
8574 EVT VT = N->getValueType(0);
8576 const TargetOptions &Options = DAG.getTarget().Options;
8577 SDNodeFlags *Flags = &cast<BinaryWithFlagsSDNode>(N)->Flags;
8581 if (SDValue FoldedVOp = SimplifyVBinOp(N))
8584 // fold (fdiv c1, c2) -> c1/c2
8586 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1, Flags);
8588 if (Options.UnsafeFPMath) {
8589 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
8591 // Compute the reciprocal 1.0 / c2.
8592 APFloat N1APF = N1CFP->getValueAPF();
8593 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
8594 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
8595 // Only do the transform if the reciprocal is a legal fp immediate that
8596 // isn't too nasty (eg NaN, denormal, ...).
8597 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
8598 (!LegalOperations ||
8599 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
8600 // backend)... we should handle this gracefully after Legalize.
8601 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
8602 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
8603 TLI.isFPImmLegal(Recip, VT)))
8604 return DAG.getNode(ISD::FMUL, DL, VT, N0,
8605 DAG.getConstantFP(Recip, DL, VT), Flags);
8608 // If this FDIV is part of a reciprocal square root, it may be folded
8609 // into a target-specific square root estimate instruction.
8610 if (N1.getOpcode() == ISD::FSQRT) {
8611 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0), Flags)) {
8612 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags);
8614 } else if (N1.getOpcode() == ISD::FP_EXTEND &&
8615 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
8616 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0).getOperand(0),
8618 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N1), VT, RV);
8619 AddToWorklist(RV.getNode());
8620 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags);
8622 } else if (N1.getOpcode() == ISD::FP_ROUND &&
8623 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
8624 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0).getOperand(0),
8626 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1));
8627 AddToWorklist(RV.getNode());
8628 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags);
8630 } else if (N1.getOpcode() == ISD::FMUL) {
8631 // Look through an FMUL. Even though this won't remove the FDIV directly,
8632 // it's still worthwhile to get rid of the FSQRT if possible.
8635 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) {
8636 SqrtOp = N1.getOperand(0);
8637 OtherOp = N1.getOperand(1);
8638 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) {
8639 SqrtOp = N1.getOperand(1);
8640 OtherOp = N1.getOperand(0);
8642 if (SqrtOp.getNode()) {
8643 // We found a FSQRT, so try to make this fold:
8644 // x / (y * sqrt(z)) -> x * (rsqrt(z) / y)
8645 if (SDValue RV = BuildRsqrtEstimate(SqrtOp.getOperand(0), Flags)) {
8646 RV = DAG.getNode(ISD::FDIV, SDLoc(N1), VT, RV, OtherOp, Flags);
8647 AddToWorklist(RV.getNode());
8648 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags);
8653 // Fold into a reciprocal estimate and multiply instead of a real divide.
8654 if (SDValue RV = BuildReciprocalEstimate(N1, Flags)) {
8655 AddToWorklist(RV.getNode());
8656 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags);
8660 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
8661 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, &Options)) {
8662 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, &Options)) {
8663 // Both can be negated for free, check to see if at least one is cheaper
8665 if (LHSNeg == 2 || RHSNeg == 2)
8666 return DAG.getNode(ISD::FDIV, SDLoc(N), VT,
8667 GetNegatedExpression(N0, DAG, LegalOperations),
8668 GetNegatedExpression(N1, DAG, LegalOperations),
8673 if (SDValue CombineRepeatedDivisors = combineRepeatedFPDivisors(N))
8674 return CombineRepeatedDivisors;
8679 SDValue DAGCombiner::visitFREM(SDNode *N) {
8680 SDValue N0 = N->getOperand(0);
8681 SDValue N1 = N->getOperand(1);
8682 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8683 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
8684 EVT VT = N->getValueType(0);
8686 // fold (frem c1, c2) -> fmod(c1,c2)
8688 return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1,
8689 &cast<BinaryWithFlagsSDNode>(N)->Flags);
8694 SDValue DAGCombiner::visitFSQRT(SDNode *N) {
8695 if (!DAG.getTarget().Options.UnsafeFPMath || TLI.isFsqrtCheap())
8698 // TODO: FSQRT nodes should have flags that propagate to the created nodes.
8699 // For now, create a Flags object for use with all unsafe math transforms.
8701 Flags.setUnsafeAlgebra(true);
8703 // Compute this as X * (1/sqrt(X)) = X * (X ** -0.5)
8704 SDValue RV = BuildRsqrtEstimate(N->getOperand(0), &Flags);
8708 EVT VT = RV.getValueType();
8710 RV = DAG.getNode(ISD::FMUL, DL, VT, N->getOperand(0), RV, &Flags);
8711 AddToWorklist(RV.getNode());
8713 // Unfortunately, RV is now NaN if the input was exactly 0.
8714 // Select out this case and force the answer to 0.
8715 SDValue Zero = DAG.getConstantFP(0.0, DL, VT);
8716 EVT CCVT = getSetCCResultType(VT);
8717 SDValue ZeroCmp = DAG.getSetCC(DL, CCVT, N->getOperand(0), Zero, ISD::SETEQ);
8718 AddToWorklist(ZeroCmp.getNode());
8719 AddToWorklist(RV.getNode());
8721 return DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT,
8725 static inline bool CanCombineFCOPYSIGN_EXTEND_ROUND(SDNode *N) {
8726 // copysign(x, fp_extend(y)) -> copysign(x, y)
8727 // copysign(x, fp_round(y)) -> copysign(x, y)
8728 // Do not optimize out type conversion of f128 type yet.
8729 // For some target like x86_64, configuration is changed
8730 // to keep one f128 value in one SSE register, but
8731 // instruction selection cannot handle FCOPYSIGN on
8732 // SSE registers yet.
8733 SDValue N1 = N->getOperand(1);
8734 EVT N1VT = N1->getValueType(0);
8735 EVT N1Op0VT = N1->getOperand(0)->getValueType(0);
8736 return (N1.getOpcode() == ISD::FP_EXTEND ||
8737 N1.getOpcode() == ISD::FP_ROUND) &&
8738 (N1VT == N1Op0VT || N1Op0VT != MVT::f128);
8741 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
8742 SDValue N0 = N->getOperand(0);
8743 SDValue N1 = N->getOperand(1);
8744 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8745 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
8746 EVT VT = N->getValueType(0);
8748 if (N0CFP && N1CFP) // Constant fold
8749 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1);
8752 const APFloat& V = N1CFP->getValueAPF();
8753 // copysign(x, c1) -> fabs(x) iff ispos(c1)
8754 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
8755 if (!V.isNegative()) {
8756 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
8757 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
8759 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
8760 return DAG.getNode(ISD::FNEG, SDLoc(N), VT,
8761 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0));
8765 // copysign(fabs(x), y) -> copysign(x, y)
8766 // copysign(fneg(x), y) -> copysign(x, y)
8767 // copysign(copysign(x,z), y) -> copysign(x, y)
8768 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
8769 N0.getOpcode() == ISD::FCOPYSIGN)
8770 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
8771 N0.getOperand(0), N1);
8773 // copysign(x, abs(y)) -> abs(x)
8774 if (N1.getOpcode() == ISD::FABS)
8775 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
8777 // copysign(x, copysign(y,z)) -> copysign(x, z)
8778 if (N1.getOpcode() == ISD::FCOPYSIGN)
8779 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
8780 N0, N1.getOperand(1));
8782 // copysign(x, fp_extend(y)) -> copysign(x, y)
8783 // copysign(x, fp_round(y)) -> copysign(x, y)
8784 if (CanCombineFCOPYSIGN_EXTEND_ROUND(N))
8785 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
8786 N0, N1.getOperand(0));
8791 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
8792 SDValue N0 = N->getOperand(0);
8793 EVT VT = N->getValueType(0);
8794 EVT OpVT = N0.getValueType();
8796 // fold (sint_to_fp c1) -> c1fp
8797 if (isConstantIntBuildVectorOrConstantInt(N0) &&
8798 // ...but only if the target supports immediate floating-point values
8799 (!LegalOperations ||
8800 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
8801 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
8803 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
8804 // but UINT_TO_FP is legal on this target, try to convert.
8805 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
8806 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
8807 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
8808 if (DAG.SignBitIsZero(N0))
8809 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
8812 // The next optimizations are desirable only if SELECT_CC can be lowered.
8813 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
8814 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
8815 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
8817 (!LegalOperations ||
8818 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
8821 { N0.getOperand(0), N0.getOperand(1),
8822 DAG.getConstantFP(-1.0, DL, VT), DAG.getConstantFP(0.0, DL, VT),
8824 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops);
8827 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
8828 // (select_cc x, y, 1.0, 0.0,, cc)
8829 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
8830 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
8831 (!LegalOperations ||
8832 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
8835 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
8836 DAG.getConstantFP(1.0, DL, VT), DAG.getConstantFP(0.0, DL, VT),
8837 N0.getOperand(0).getOperand(2) };
8838 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops);
8845 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
8846 SDValue N0 = N->getOperand(0);
8847 EVT VT = N->getValueType(0);
8848 EVT OpVT = N0.getValueType();
8850 // fold (uint_to_fp c1) -> c1fp
8851 if (isConstantIntBuildVectorOrConstantInt(N0) &&
8852 // ...but only if the target supports immediate floating-point values
8853 (!LegalOperations ||
8854 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
8855 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
8857 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
8858 // but SINT_TO_FP is legal on this target, try to convert.
8859 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
8860 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
8861 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
8862 if (DAG.SignBitIsZero(N0))
8863 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
8866 // The next optimizations are desirable only if SELECT_CC can be lowered.
8867 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
8868 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
8870 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
8871 (!LegalOperations ||
8872 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
8875 { N0.getOperand(0), N0.getOperand(1),
8876 DAG.getConstantFP(1.0, DL, VT), DAG.getConstantFP(0.0, DL, VT),
8878 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops);
8885 // Fold (fp_to_{s/u}int ({s/u}int_to_fpx)) -> zext x, sext x, trunc x, or x
8886 static SDValue FoldIntToFPToInt(SDNode *N, SelectionDAG &DAG) {
8887 SDValue N0 = N->getOperand(0);
8888 EVT VT = N->getValueType(0);
8890 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP)
8893 SDValue Src = N0.getOperand(0);
8894 EVT SrcVT = Src.getValueType();
8895 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP;
8896 bool IsOutputSigned = N->getOpcode() == ISD::FP_TO_SINT;
8898 // We can safely assume the conversion won't overflow the output range,
8899 // because (for example) (uint8_t)18293.f is undefined behavior.
8901 // Since we can assume the conversion won't overflow, our decision as to
8902 // whether the input will fit in the float should depend on the minimum
8903 // of the input range and output range.
8905 // This means this is also safe for a signed input and unsigned output, since
8906 // a negative input would lead to undefined behavior.
8907 unsigned InputSize = (int)SrcVT.getScalarSizeInBits() - IsInputSigned;
8908 unsigned OutputSize = (int)VT.getScalarSizeInBits() - IsOutputSigned;
8909 unsigned ActualSize = std::min(InputSize, OutputSize);
8910 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(N0.getValueType());
8912 // We can only fold away the float conversion if the input range can be
8913 // represented exactly in the float range.
8914 if (APFloat::semanticsPrecision(sem) >= ActualSize) {
8915 if (VT.getScalarSizeInBits() > SrcVT.getScalarSizeInBits()) {
8916 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND
8918 return DAG.getNode(ExtOp, SDLoc(N), VT, Src);
8920 if (VT.getScalarSizeInBits() < SrcVT.getScalarSizeInBits())
8921 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Src);
8924 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Src);
8929 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
8930 SDValue N0 = N->getOperand(0);
8931 EVT VT = N->getValueType(0);
8933 // fold (fp_to_sint c1fp) -> c1
8934 if (isConstantFPBuildVectorOrConstantFP(N0))
8935 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0);
8937 return FoldIntToFPToInt(N, DAG);
8940 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
8941 SDValue N0 = N->getOperand(0);
8942 EVT VT = N->getValueType(0);
8944 // fold (fp_to_uint c1fp) -> c1
8945 if (isConstantFPBuildVectorOrConstantFP(N0))
8946 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0);
8948 return FoldIntToFPToInt(N, DAG);
8951 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
8952 SDValue N0 = N->getOperand(0);
8953 SDValue N1 = N->getOperand(1);
8954 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8955 EVT VT = N->getValueType(0);
8957 // fold (fp_round c1fp) -> c1fp
8959 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1);
8961 // fold (fp_round (fp_extend x)) -> x
8962 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
8963 return N0.getOperand(0);
8965 // fold (fp_round (fp_round x)) -> (fp_round x)
8966 if (N0.getOpcode() == ISD::FP_ROUND) {
8967 const bool NIsTrunc = N->getConstantOperandVal(1) == 1;
8968 const bool N0IsTrunc = N0.getNode()->getConstantOperandVal(1) == 1;
8969 // If the first fp_round isn't a value preserving truncation, it might
8970 // introduce a tie in the second fp_round, that wouldn't occur in the
8971 // single-step fp_round we want to fold to.
8972 // In other words, double rounding isn't the same as rounding.
8973 // Also, this is a value preserving truncation iff both fp_round's are.
8974 if (DAG.getTarget().Options.UnsafeFPMath || N0IsTrunc) {
8976 return DAG.getNode(ISD::FP_ROUND, DL, VT, N0.getOperand(0),
8977 DAG.getIntPtrConstant(NIsTrunc && N0IsTrunc, DL));
8981 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
8982 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
8983 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,
8984 N0.getOperand(0), N1);
8985 AddToWorklist(Tmp.getNode());
8986 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
8987 Tmp, N0.getOperand(1));
8993 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
8994 SDValue N0 = N->getOperand(0);
8995 EVT VT = N->getValueType(0);
8996 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
8997 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8999 // fold (fp_round_inreg c1fp) -> c1fp
9000 if (N0CFP && isTypeLegal(EVT)) {
9002 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), DL, EVT);
9003 return DAG.getNode(ISD::FP_EXTEND, DL, VT, Round);
9009 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
9010 SDValue N0 = N->getOperand(0);
9011 EVT VT = N->getValueType(0);
9013 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
9014 if (N->hasOneUse() &&
9015 N->use_begin()->getOpcode() == ISD::FP_ROUND)
9018 // fold (fp_extend c1fp) -> c1fp
9019 if (isConstantFPBuildVectorOrConstantFP(N0))
9020 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);
9022 // fold (fp_extend (fp16_to_fp op)) -> (fp16_to_fp op)
9023 if (N0.getOpcode() == ISD::FP16_TO_FP &&
9024 TLI.getOperationAction(ISD::FP16_TO_FP, VT) == TargetLowering::Legal)
9025 return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), VT, N0.getOperand(0));
9027 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
9029 if (N0.getOpcode() == ISD::FP_ROUND
9030 && N0.getNode()->getConstantOperandVal(1) == 1) {
9031 SDValue In = N0.getOperand(0);
9032 if (In.getValueType() == VT) return In;
9033 if (VT.bitsLT(In.getValueType()))
9034 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT,
9035 In, N0.getOperand(1));
9036 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, In);
9039 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
9040 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
9041 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
9042 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
9043 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
9045 LN0->getBasePtr(), N0.getValueType(),
9046 LN0->getMemOperand());
9047 CombineTo(N, ExtLoad);
9048 CombineTo(N0.getNode(),
9049 DAG.getNode(ISD::FP_ROUND, SDLoc(N0),
9050 N0.getValueType(), ExtLoad,
9051 DAG.getIntPtrConstant(1, SDLoc(N0))),
9052 ExtLoad.getValue(1));
9053 return SDValue(N, 0); // Return N so it doesn't get rechecked!
9059 SDValue DAGCombiner::visitFCEIL(SDNode *N) {
9060 SDValue N0 = N->getOperand(0);
9061 EVT VT = N->getValueType(0);
9063 // fold (fceil c1) -> fceil(c1)
9064 if (isConstantFPBuildVectorOrConstantFP(N0))
9065 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0);
9070 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
9071 SDValue N0 = N->getOperand(0);
9072 EVT VT = N->getValueType(0);
9074 // fold (ftrunc c1) -> ftrunc(c1)
9075 if (isConstantFPBuildVectorOrConstantFP(N0))
9076 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0);
9081 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
9082 SDValue N0 = N->getOperand(0);
9083 EVT VT = N->getValueType(0);
9085 // fold (ffloor c1) -> ffloor(c1)
9086 if (isConstantFPBuildVectorOrConstantFP(N0))
9087 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0);
9092 // FIXME: FNEG and FABS have a lot in common; refactor.
9093 SDValue DAGCombiner::visitFNEG(SDNode *N) {
9094 SDValue N0 = N->getOperand(0);
9095 EVT VT = N->getValueType(0);
9097 // Constant fold FNEG.
9098 if (isConstantFPBuildVectorOrConstantFP(N0))
9099 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
9101 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
9102 &DAG.getTarget().Options))
9103 return GetNegatedExpression(N0, DAG, LegalOperations);
9105 // Transform fneg(bitconvert(x)) -> bitconvert(x ^ sign) to avoid loading
9106 // constant pool values.
9107 if (!TLI.isFNegFree(VT) &&
9108 N0.getOpcode() == ISD::BITCAST &&
9109 N0.getNode()->hasOneUse()) {
9110 SDValue Int = N0.getOperand(0);
9111 EVT IntVT = Int.getValueType();
9112 if (IntVT.isInteger() && !IntVT.isVector()) {
9114 if (N0.getValueType().isVector()) {
9115 // For a vector, get a mask such as 0x80... per scalar element
9117 SignMask = APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
9118 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
9120 // For a scalar, just generate 0x80...
9121 SignMask = APInt::getSignBit(IntVT.getSizeInBits());
9124 Int = DAG.getNode(ISD::XOR, DL0, IntVT, Int,
9125 DAG.getConstant(SignMask, DL0, IntVT));
9126 AddToWorklist(Int.getNode());
9127 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Int);
9131 // (fneg (fmul c, x)) -> (fmul -c, x)
9132 if (N0.getOpcode() == ISD::FMUL &&
9133 (N0.getNode()->hasOneUse() || !TLI.isFNegFree(VT))) {
9134 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
9136 APFloat CVal = CFP1->getValueAPF();
9138 if (Level >= AfterLegalizeDAG &&
9139 (TLI.isFPImmLegal(CVal, VT) ||
9140 TLI.isOperationLegal(ISD::ConstantFP, VT)))
9141 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
9142 DAG.getNode(ISD::FNEG, SDLoc(N), VT,
9144 &cast<BinaryWithFlagsSDNode>(N0)->Flags);
9151 SDValue DAGCombiner::visitFMINNUM(SDNode *N) {
9152 SDValue N0 = N->getOperand(0);
9153 SDValue N1 = N->getOperand(1);
9154 EVT VT = N->getValueType(0);
9155 const ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
9156 const ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
9158 if (N0CFP && N1CFP) {
9159 const APFloat &C0 = N0CFP->getValueAPF();
9160 const APFloat &C1 = N1CFP->getValueAPF();
9161 return DAG.getConstantFP(minnum(C0, C1), SDLoc(N), VT);
9164 // Canonicalize to constant on RHS.
9165 if (isConstantFPBuildVectorOrConstantFP(N0) &&
9166 !isConstantFPBuildVectorOrConstantFP(N1))
9167 return DAG.getNode(ISD::FMINNUM, SDLoc(N), VT, N1, N0);
9172 SDValue DAGCombiner::visitFMAXNUM(SDNode *N) {
9173 SDValue N0 = N->getOperand(0);
9174 SDValue N1 = N->getOperand(1);
9175 EVT VT = N->getValueType(0);
9176 const ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
9177 const ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
9179 if (N0CFP && N1CFP) {
9180 const APFloat &C0 = N0CFP->getValueAPF();
9181 const APFloat &C1 = N1CFP->getValueAPF();
9182 return DAG.getConstantFP(maxnum(C0, C1), SDLoc(N), VT);
9185 // Canonicalize to constant on RHS.
9186 if (isConstantFPBuildVectorOrConstantFP(N0) &&
9187 !isConstantFPBuildVectorOrConstantFP(N1))
9188 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), VT, N1, N0);
9193 SDValue DAGCombiner::visitFABS(SDNode *N) {
9194 SDValue N0 = N->getOperand(0);
9195 EVT VT = N->getValueType(0);
9197 // fold (fabs c1) -> fabs(c1)
9198 if (isConstantFPBuildVectorOrConstantFP(N0))
9199 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
9201 // fold (fabs (fabs x)) -> (fabs x)
9202 if (N0.getOpcode() == ISD::FABS)
9203 return N->getOperand(0);
9205 // fold (fabs (fneg x)) -> (fabs x)
9206 // fold (fabs (fcopysign x, y)) -> (fabs x)
9207 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
9208 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0));
9210 // Transform fabs(bitconvert(x)) -> bitconvert(x & ~sign) to avoid loading
9211 // constant pool values.
9212 if (!TLI.isFAbsFree(VT) &&
9213 N0.getOpcode() == ISD::BITCAST &&
9214 N0.getNode()->hasOneUse()) {
9215 SDValue Int = N0.getOperand(0);
9216 EVT IntVT = Int.getValueType();
9217 if (IntVT.isInteger() && !IntVT.isVector()) {
9219 if (N0.getValueType().isVector()) {
9220 // For a vector, get a mask such as 0x7f... per scalar element
9222 SignMask = ~APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
9223 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
9225 // For a scalar, just generate 0x7f...
9226 SignMask = ~APInt::getSignBit(IntVT.getSizeInBits());
9229 Int = DAG.getNode(ISD::AND, DL, IntVT, Int,
9230 DAG.getConstant(SignMask, DL, IntVT));
9231 AddToWorklist(Int.getNode());
9232 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Int);
9239 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
9240 SDValue Chain = N->getOperand(0);
9241 SDValue N1 = N->getOperand(1);
9242 SDValue N2 = N->getOperand(2);
9244 // If N is a constant we could fold this into a fallthrough or unconditional
9245 // branch. However that doesn't happen very often in normal code, because
9246 // Instcombine/SimplifyCFG should have handled the available opportunities.
9247 // If we did this folding here, it would be necessary to update the
9248 // MachineBasicBlock CFG, which is awkward.
9250 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
9252 if (N1.getOpcode() == ISD::SETCC &&
9253 TLI.isOperationLegalOrCustom(ISD::BR_CC,
9254 N1.getOperand(0).getValueType())) {
9255 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
9256 Chain, N1.getOperand(2),
9257 N1.getOperand(0), N1.getOperand(1), N2);
9260 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
9261 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
9262 (N1.getOperand(0).hasOneUse() &&
9263 N1.getOperand(0).getOpcode() == ISD::SRL))) {
9264 SDNode *Trunc = nullptr;
9265 if (N1.getOpcode() == ISD::TRUNCATE) {
9266 // Look pass the truncate.
9267 Trunc = N1.getNode();
9268 N1 = N1.getOperand(0);
9271 // Match this pattern so that we can generate simpler code:
9274 // %b = and i32 %a, 2
9275 // %c = srl i32 %b, 1
9276 // brcond i32 %c ...
9281 // %b = and i32 %a, 2
9282 // %c = setcc eq %b, 0
9285 // This applies only when the AND constant value has one bit set and the
9286 // SRL constant is equal to the log2 of the AND constant. The back-end is
9287 // smart enough to convert the result into a TEST/JMP sequence.
9288 SDValue Op0 = N1.getOperand(0);
9289 SDValue Op1 = N1.getOperand(1);
9291 if (Op0.getOpcode() == ISD::AND &&
9292 Op1.getOpcode() == ISD::Constant) {
9293 SDValue AndOp1 = Op0.getOperand(1);
9295 if (AndOp1.getOpcode() == ISD::Constant) {
9296 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
9298 if (AndConst.isPowerOf2() &&
9299 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
9303 getSetCCResultType(Op0.getValueType()),
9304 Op0, DAG.getConstant(0, DL, Op0.getValueType()),
9307 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, DL,
9308 MVT::Other, Chain, SetCC, N2);
9309 // Don't add the new BRCond into the worklist or else SimplifySelectCC
9310 // will convert it back to (X & C1) >> C2.
9311 CombineTo(N, NewBRCond, false);
9312 // Truncate is dead.
9314 deleteAndRecombine(Trunc);
9315 // Replace the uses of SRL with SETCC
9316 WorklistRemover DeadNodes(*this);
9317 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
9318 deleteAndRecombine(N1.getNode());
9319 return SDValue(N, 0); // Return N so it doesn't get rechecked!
9325 // Restore N1 if the above transformation doesn't match.
9326 N1 = N->getOperand(1);
9329 // Transform br(xor(x, y)) -> br(x != y)
9330 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
9331 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
9332 SDNode *TheXor = N1.getNode();
9333 SDValue Op0 = TheXor->getOperand(0);
9334 SDValue Op1 = TheXor->getOperand(1);
9335 if (Op0.getOpcode() == Op1.getOpcode()) {
9336 // Avoid missing important xor optimizations.
9337 if (SDValue Tmp = visitXOR(TheXor)) {
9338 if (Tmp.getNode() != TheXor) {
9339 DEBUG(dbgs() << "\nReplacing.8 ";
9341 dbgs() << "\nWith: ";
9342 Tmp.getNode()->dump(&DAG);
9344 WorklistRemover DeadNodes(*this);
9345 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
9346 deleteAndRecombine(TheXor);
9347 return DAG.getNode(ISD::BRCOND, SDLoc(N),
9348 MVT::Other, Chain, Tmp, N2);
9351 // visitXOR has changed XOR's operands or replaced the XOR completely,
9353 return SDValue(N, 0);
9357 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
9359 if (isOneConstant(Op0) && Op0.hasOneUse() &&
9360 Op0.getOpcode() == ISD::XOR) {
9361 TheXor = Op0.getNode();
9365 EVT SetCCVT = N1.getValueType();
9367 SetCCVT = getSetCCResultType(SetCCVT);
9368 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor),
9371 Equal ? ISD::SETEQ : ISD::SETNE);
9372 // Replace the uses of XOR with SETCC
9373 WorklistRemover DeadNodes(*this);
9374 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
9375 deleteAndRecombine(N1.getNode());
9376 return DAG.getNode(ISD::BRCOND, SDLoc(N),
9377 MVT::Other, Chain, SetCC, N2);
9384 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
9386 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
9387 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
9388 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
9390 // If N is a constant we could fold this into a fallthrough or unconditional
9391 // branch. However that doesn't happen very often in normal code, because
9392 // Instcombine/SimplifyCFG should have handled the available opportunities.
9393 // If we did this folding here, it would be necessary to update the
9394 // MachineBasicBlock CFG, which is awkward.
9396 // Use SimplifySetCC to simplify SETCC's.
9397 SDValue Simp = SimplifySetCC(getSetCCResultType(CondLHS.getValueType()),
9398 CondLHS, CondRHS, CC->get(), SDLoc(N),
9400 if (Simp.getNode()) AddToWorklist(Simp.getNode());
9402 // fold to a simpler setcc
9403 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
9404 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
9405 N->getOperand(0), Simp.getOperand(2),
9406 Simp.getOperand(0), Simp.getOperand(1),
9412 /// Return true if 'Use' is a load or a store that uses N as its base pointer
9413 /// and that N may be folded in the load / store addressing mode.
9414 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
9416 const TargetLowering &TLI) {
9420 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
9421 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
9423 VT = LD->getMemoryVT();
9424 AS = LD->getAddressSpace();
9425 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
9426 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
9428 VT = ST->getMemoryVT();
9429 AS = ST->getAddressSpace();
9433 TargetLowering::AddrMode AM;
9434 if (N->getOpcode() == ISD::ADD) {
9435 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
9438 AM.BaseOffs = Offset->getSExtValue();
9442 } else if (N->getOpcode() == ISD::SUB) {
9443 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
9446 AM.BaseOffs = -Offset->getSExtValue();
9453 return TLI.isLegalAddressingMode(DAG.getDataLayout(), AM,
9454 VT.getTypeForEVT(*DAG.getContext()), AS);
9457 /// Try turning a load/store into a pre-indexed load/store when the base
9458 /// pointer is an add or subtract and it has other uses besides the load/store.
9459 /// After the transformation, the new indexed load/store has effectively folded
9460 /// the add/subtract in and all of its other uses are redirected to the
9462 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
9463 if (Level < AfterLegalizeDAG)
9469 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9470 if (LD->isIndexed())
9472 VT = LD->getMemoryVT();
9473 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
9474 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
9476 Ptr = LD->getBasePtr();
9477 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9478 if (ST->isIndexed())
9480 VT = ST->getMemoryVT();
9481 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
9482 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
9484 Ptr = ST->getBasePtr();
9490 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
9491 // out. There is no reason to make this a preinc/predec.
9492 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
9493 Ptr.getNode()->hasOneUse())
9496 // Ask the target to do addressing mode selection.
9499 ISD::MemIndexedMode AM = ISD::UNINDEXED;
9500 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
9503 // Backends without true r+i pre-indexed forms may need to pass a
9504 // constant base with a variable offset so that constant coercion
9505 // will work with the patterns in canonical form.
9506 bool Swapped = false;
9507 if (isa<ConstantSDNode>(BasePtr)) {
9508 std::swap(BasePtr, Offset);
9512 // Don't create a indexed load / store with zero offset.
9513 if (isNullConstant(Offset))
9516 // Try turning it into a pre-indexed load / store except when:
9517 // 1) The new base ptr is a frame index.
9518 // 2) If N is a store and the new base ptr is either the same as or is a
9519 // predecessor of the value being stored.
9520 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
9521 // that would create a cycle.
9522 // 4) All uses are load / store ops that use it as old base ptr.
9524 // Check #1. Preinc'ing a frame index would require copying the stack pointer
9525 // (plus the implicit offset) to a register to preinc anyway.
9526 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
9531 SDValue Val = cast<StoreSDNode>(N)->getValue();
9532 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
9536 // If the offset is a constant, there may be other adds of constants that
9537 // can be folded with this one. We should do this to avoid having to keep
9538 // a copy of the original base pointer.
9539 SmallVector<SDNode *, 16> OtherUses;
9540 if (isa<ConstantSDNode>(Offset))
9541 for (SDNode::use_iterator UI = BasePtr.getNode()->use_begin(),
9542 UE = BasePtr.getNode()->use_end();
9544 SDUse &Use = UI.getUse();
9545 // Skip the use that is Ptr and uses of other results from BasePtr's
9546 // node (important for nodes that return multiple results).
9547 if (Use.getUser() == Ptr.getNode() || Use != BasePtr)
9550 if (Use.getUser()->isPredecessorOf(N))
9553 if (Use.getUser()->getOpcode() != ISD::ADD &&
9554 Use.getUser()->getOpcode() != ISD::SUB) {
9559 SDValue Op1 = Use.getUser()->getOperand((UI.getOperandNo() + 1) & 1);
9560 if (!isa<ConstantSDNode>(Op1)) {
9565 // FIXME: In some cases, we can be smarter about this.
9566 if (Op1.getValueType() != Offset.getValueType()) {
9571 OtherUses.push_back(Use.getUser());
9575 std::swap(BasePtr, Offset);
9577 // Now check for #3 and #4.
9578 bool RealUse = false;
9580 // Caches for hasPredecessorHelper
9581 SmallPtrSet<const SDNode *, 32> Visited;
9582 SmallVector<const SDNode *, 16> Worklist;
9584 for (SDNode *Use : Ptr.getNode()->uses()) {
9587 if (N->hasPredecessorHelper(Use, Visited, Worklist))
9590 // If Ptr may be folded in addressing mode of other use, then it's
9591 // not profitable to do this transformation.
9592 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
9601 Result = DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
9602 BasePtr, Offset, AM);
9604 Result = DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
9605 BasePtr, Offset, AM);
9608 DEBUG(dbgs() << "\nReplacing.4 ";
9610 dbgs() << "\nWith: ";
9611 Result.getNode()->dump(&DAG);
9613 WorklistRemover DeadNodes(*this);
9615 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
9616 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
9618 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
9621 // Finally, since the node is now dead, remove it from the graph.
9622 deleteAndRecombine(N);
9625 std::swap(BasePtr, Offset);
9627 // Replace other uses of BasePtr that can be updated to use Ptr
9628 for (unsigned i = 0, e = OtherUses.size(); i != e; ++i) {
9629 unsigned OffsetIdx = 1;
9630 if (OtherUses[i]->getOperand(OffsetIdx).getNode() == BasePtr.getNode())
9632 assert(OtherUses[i]->getOperand(!OffsetIdx).getNode() ==
9633 BasePtr.getNode() && "Expected BasePtr operand");
9635 // We need to replace ptr0 in the following expression:
9636 // x0 * offset0 + y0 * ptr0 = t0
9638 // x1 * offset1 + y1 * ptr0 = t1 (the indexed load/store)
9640 // where x0, x1, y0 and y1 in {-1, 1} are given by the types of the
9641 // indexed load/store and the expresion that needs to be re-written.
9643 // Therefore, we have:
9644 // t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1
9646 ConstantSDNode *CN =
9647 cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx));
9649 APInt Offset0 = CN->getAPIntValue();
9650 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue();
9652 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
9653 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
9654 X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1;
9655 Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1;
9657 unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD;
9659 APInt CNV = Offset0;
9660 if (X0 < 0) CNV = -CNV;
9661 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1;
9662 else CNV = CNV - Offset1;
9664 SDLoc DL(OtherUses[i]);
9666 // We can now generate the new expression.
9667 SDValue NewOp1 = DAG.getConstant(CNV, DL, CN->getValueType(0));
9668 SDValue NewOp2 = Result.getValue(isLoad ? 1 : 0);
9670 SDValue NewUse = DAG.getNode(Opcode,
9672 OtherUses[i]->getValueType(0), NewOp1, NewOp2);
9673 DAG.ReplaceAllUsesOfValueWith(SDValue(OtherUses[i], 0), NewUse);
9674 deleteAndRecombine(OtherUses[i]);
9677 // Replace the uses of Ptr with uses of the updated base value.
9678 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
9679 deleteAndRecombine(Ptr.getNode());
9684 /// Try to combine a load/store with a add/sub of the base pointer node into a
9685 /// post-indexed load/store. The transformation folded the add/subtract into the
9686 /// new indexed load/store effectively and all of its uses are redirected to the
9688 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
9689 if (Level < AfterLegalizeDAG)
9695 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9696 if (LD->isIndexed())
9698 VT = LD->getMemoryVT();
9699 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
9700 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
9702 Ptr = LD->getBasePtr();
9703 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9704 if (ST->isIndexed())
9706 VT = ST->getMemoryVT();
9707 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
9708 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
9710 Ptr = ST->getBasePtr();
9716 if (Ptr.getNode()->hasOneUse())
9719 for (SDNode *Op : Ptr.getNode()->uses()) {
9721 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
9726 ISD::MemIndexedMode AM = ISD::UNINDEXED;
9727 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
9728 // Don't create a indexed load / store with zero offset.
9729 if (isNullConstant(Offset))
9732 // Try turning it into a post-indexed load / store except when
9733 // 1) All uses are load / store ops that use it as base ptr (and
9734 // it may be folded as addressing mmode).
9735 // 2) Op must be independent of N, i.e. Op is neither a predecessor
9736 // nor a successor of N. Otherwise, if Op is folded that would
9739 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
9743 bool TryNext = false;
9744 for (SDNode *Use : BasePtr.getNode()->uses()) {
9745 if (Use == Ptr.getNode())
9748 // If all the uses are load / store addresses, then don't do the
9750 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
9751 bool RealUse = false;
9752 for (SDNode *UseUse : Use->uses()) {
9753 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
9768 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
9769 SDValue Result = isLoad
9770 ? DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
9771 BasePtr, Offset, AM)
9772 : DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
9773 BasePtr, Offset, AM);
9776 DEBUG(dbgs() << "\nReplacing.5 ";
9778 dbgs() << "\nWith: ";
9779 Result.getNode()->dump(&DAG);
9781 WorklistRemover DeadNodes(*this);
9783 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
9784 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
9786 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
9789 // Finally, since the node is now dead, remove it from the graph.
9790 deleteAndRecombine(N);
9792 // Replace the uses of Use with uses of the updated base value.
9793 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
9794 Result.getValue(isLoad ? 1 : 0));
9795 deleteAndRecombine(Op);
9804 /// \brief Return the base-pointer arithmetic from an indexed \p LD.
9805 SDValue DAGCombiner::SplitIndexingFromLoad(LoadSDNode *LD) {
9806 ISD::MemIndexedMode AM = LD->getAddressingMode();
9807 assert(AM != ISD::UNINDEXED);
9808 SDValue BP = LD->getOperand(1);
9809 SDValue Inc = LD->getOperand(2);
9811 // Some backends use TargetConstants for load offsets, but don't expect
9812 // TargetConstants in general ADD nodes. We can convert these constants into
9813 // regular Constants (if the constant is not opaque).
9814 assert((Inc.getOpcode() != ISD::TargetConstant ||
9815 !cast<ConstantSDNode>(Inc)->isOpaque()) &&
9816 "Cannot split out indexing using opaque target constants");
9817 if (Inc.getOpcode() == ISD::TargetConstant) {
9818 ConstantSDNode *ConstInc = cast<ConstantSDNode>(Inc);
9819 Inc = DAG.getConstant(*ConstInc->getConstantIntValue(), SDLoc(Inc),
9820 ConstInc->getValueType(0));
9824 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB);
9825 return DAG.getNode(Opc, SDLoc(LD), BP.getSimpleValueType(), BP, Inc);
9828 SDValue DAGCombiner::visitLOAD(SDNode *N) {
9829 LoadSDNode *LD = cast<LoadSDNode>(N);
9830 SDValue Chain = LD->getChain();
9831 SDValue Ptr = LD->getBasePtr();
9833 // If load is not volatile and there are no uses of the loaded value (and
9834 // the updated indexed value in case of indexed loads), change uses of the
9835 // chain value into uses of the chain input (i.e. delete the dead load).
9836 if (!LD->isVolatile()) {
9837 if (N->getValueType(1) == MVT::Other) {
9839 if (!N->hasAnyUseOfValue(0)) {
9840 // It's not safe to use the two value CombineTo variant here. e.g.
9841 // v1, chain2 = load chain1, loc
9842 // v2, chain3 = load chain2, loc
9844 // Now we replace use of chain2 with chain1. This makes the second load
9845 // isomorphic to the one we are deleting, and thus makes this load live.
9846 DEBUG(dbgs() << "\nReplacing.6 ";
9848 dbgs() << "\nWith chain: ";
9849 Chain.getNode()->dump(&DAG);
9851 WorklistRemover DeadNodes(*this);
9852 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
9855 deleteAndRecombine(N);
9857 return SDValue(N, 0); // Return N so it doesn't get rechecked!
9861 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
9863 // If this load has an opaque TargetConstant offset, then we cannot split
9864 // the indexing into an add/sub directly (that TargetConstant may not be
9865 // valid for a different type of node, and we cannot convert an opaque
9866 // target constant into a regular constant).
9867 bool HasOTCInc = LD->getOperand(2).getOpcode() == ISD::TargetConstant &&
9868 cast<ConstantSDNode>(LD->getOperand(2))->isOpaque();
9870 if (!N->hasAnyUseOfValue(0) &&
9871 ((MaySplitLoadIndex && !HasOTCInc) || !N->hasAnyUseOfValue(1))) {
9872 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
9874 if (N->hasAnyUseOfValue(1) && MaySplitLoadIndex && !HasOTCInc) {
9875 Index = SplitIndexingFromLoad(LD);
9876 // Try to fold the base pointer arithmetic into subsequent loads and
9878 AddUsersToWorklist(N);
9880 Index = DAG.getUNDEF(N->getValueType(1));
9881 DEBUG(dbgs() << "\nReplacing.7 ";
9883 dbgs() << "\nWith: ";
9884 Undef.getNode()->dump(&DAG);
9885 dbgs() << " and 2 other values\n");
9886 WorklistRemover DeadNodes(*this);
9887 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
9888 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Index);
9889 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
9890 deleteAndRecombine(N);
9891 return SDValue(N, 0); // Return N so it doesn't get rechecked!
9896 // If this load is directly stored, replace the load value with the stored
9898 // TODO: Handle store large -> read small portion.
9899 // TODO: Handle TRUNCSTORE/LOADEXT
9900 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
9901 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
9902 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
9903 if (PrevST->getBasePtr() == Ptr &&
9904 PrevST->getValue().getValueType() == N->getValueType(0))
9905 return CombineTo(N, Chain.getOperand(1), Chain);
9909 // Try to infer better alignment information than the load already has.
9910 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
9911 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
9912 if (Align > LD->getMemOperand()->getBaseAlignment()) {
9914 DAG.getExtLoad(LD->getExtensionType(), SDLoc(N),
9915 LD->getValueType(0),
9916 Chain, Ptr, LD->getPointerInfo(),
9918 LD->isVolatile(), LD->isNonTemporal(),
9919 LD->isInvariant(), Align, LD->getAAInfo());
9920 if (NewLoad.getNode() != N)
9921 return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
9926 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
9927 : DAG.getSubtarget().useAA();
9929 if (CombinerAAOnlyFunc.getNumOccurrences() &&
9930 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
9933 if (UseAA && LD->isUnindexed()) {
9934 // Walk up chain skipping non-aliasing memory nodes.
9935 SDValue BetterChain = FindBetterChain(N, Chain);
9937 // If there is a better chain.
9938 if (Chain != BetterChain) {
9941 // Replace the chain to void dependency.
9942 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
9943 ReplLoad = DAG.getLoad(N->getValueType(0), SDLoc(LD),
9944 BetterChain, Ptr, LD->getMemOperand());
9946 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD),
9947 LD->getValueType(0),
9948 BetterChain, Ptr, LD->getMemoryVT(),
9949 LD->getMemOperand());
9952 // Create token factor to keep old chain connected.
9953 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
9954 MVT::Other, Chain, ReplLoad.getValue(1));
9956 // Make sure the new and old chains are cleaned up.
9957 AddToWorklist(Token.getNode());
9959 // Replace uses with load result and token factor. Don't add users
9961 return CombineTo(N, ReplLoad.getValue(0), Token, false);
9965 // Try transforming N to an indexed load.
9966 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
9967 return SDValue(N, 0);
9969 // Try to slice up N to more direct loads if the slices are mapped to
9970 // different register banks or pairing can take place.
9972 return SDValue(N, 0);
9978 /// \brief Helper structure used to slice a load in smaller loads.
9979 /// Basically a slice is obtained from the following sequence:
9980 /// Origin = load Ty1, Base
9981 /// Shift = srl Ty1 Origin, CstTy Amount
9982 /// Inst = trunc Shift to Ty2
9984 /// Then, it will be rewriten into:
9985 /// Slice = load SliceTy, Base + SliceOffset
9986 /// [Inst = zext Slice to Ty2], only if SliceTy <> Ty2
9988 /// SliceTy is deduced from the number of bits that are actually used to
9990 struct LoadedSlice {
9991 /// \brief Helper structure used to compute the cost of a slice.
9993 /// Are we optimizing for code size.
9998 unsigned CrossRegisterBanksCopies;
10002 Cost(bool ForCodeSize = false)
10003 : ForCodeSize(ForCodeSize), Loads(0), Truncates(0),
10004 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {}
10006 /// \brief Get the cost of one isolated slice.
10007 Cost(const LoadedSlice &LS, bool ForCodeSize = false)
10008 : ForCodeSize(ForCodeSize), Loads(1), Truncates(0),
10009 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {
10010 EVT TruncType = LS.Inst->getValueType(0);
10011 EVT LoadedType = LS.getLoadedType();
10012 if (TruncType != LoadedType &&
10013 !LS.DAG->getTargetLoweringInfo().isZExtFree(LoadedType, TruncType))
10017 /// \brief Account for slicing gain in the current cost.
10018 /// Slicing provide a few gains like removing a shift or a
10019 /// truncate. This method allows to grow the cost of the original
10020 /// load with the gain from this slice.
10021 void addSliceGain(const LoadedSlice &LS) {
10022 // Each slice saves a truncate.
10023 const TargetLowering &TLI = LS.DAG->getTargetLoweringInfo();
10024 if (!TLI.isTruncateFree(LS.Inst->getOperand(0).getValueType(),
10025 LS.Inst->getValueType(0)))
10027 // If there is a shift amount, this slice gets rid of it.
10030 // If this slice can merge a cross register bank copy, account for it.
10031 if (LS.canMergeExpensiveCrossRegisterBankCopy())
10032 ++CrossRegisterBanksCopies;
10035 Cost &operator+=(const Cost &RHS) {
10036 Loads += RHS.Loads;
10037 Truncates += RHS.Truncates;
10038 CrossRegisterBanksCopies += RHS.CrossRegisterBanksCopies;
10039 ZExts += RHS.ZExts;
10040 Shift += RHS.Shift;
10044 bool operator==(const Cost &RHS) const {
10045 return Loads == RHS.Loads && Truncates == RHS.Truncates &&
10046 CrossRegisterBanksCopies == RHS.CrossRegisterBanksCopies &&
10047 ZExts == RHS.ZExts && Shift == RHS.Shift;
10050 bool operator!=(const Cost &RHS) const { return !(*this == RHS); }
10052 bool operator<(const Cost &RHS) const {
10053 // Assume cross register banks copies are as expensive as loads.
10054 // FIXME: Do we want some more target hooks?
10055 unsigned ExpensiveOpsLHS = Loads + CrossRegisterBanksCopies;
10056 unsigned ExpensiveOpsRHS = RHS.Loads + RHS.CrossRegisterBanksCopies;
10057 // Unless we are optimizing for code size, consider the
10058 // expensive operation first.
10059 if (!ForCodeSize && ExpensiveOpsLHS != ExpensiveOpsRHS)
10060 return ExpensiveOpsLHS < ExpensiveOpsRHS;
10061 return (Truncates + ZExts + Shift + ExpensiveOpsLHS) <
10062 (RHS.Truncates + RHS.ZExts + RHS.Shift + ExpensiveOpsRHS);
10065 bool operator>(const Cost &RHS) const { return RHS < *this; }
10067 bool operator<=(const Cost &RHS) const { return !(RHS < *this); }
10069 bool operator>=(const Cost &RHS) const { return !(*this < RHS); }
10071 // The last instruction that represent the slice. This should be a
10072 // truncate instruction.
10074 // The original load instruction.
10075 LoadSDNode *Origin;
10076 // The right shift amount in bits from the original load.
10078 // The DAG from which Origin came from.
10079 // This is used to get some contextual information about legal types, etc.
10082 LoadedSlice(SDNode *Inst = nullptr, LoadSDNode *Origin = nullptr,
10083 unsigned Shift = 0, SelectionDAG *DAG = nullptr)
10084 : Inst(Inst), Origin(Origin), Shift(Shift), DAG(DAG) {}
10086 /// \brief Get the bits used in a chunk of bits \p BitWidth large.
10087 /// \return Result is \p BitWidth and has used bits set to 1 and
10088 /// not used bits set to 0.
10089 APInt getUsedBits() const {
10090 // Reproduce the trunc(lshr) sequence:
10091 // - Start from the truncated value.
10092 // - Zero extend to the desired bit width.
10094 assert(Origin && "No original load to compare against.");
10095 unsigned BitWidth = Origin->getValueSizeInBits(0);
10096 assert(Inst && "This slice is not bound to an instruction");
10097 assert(Inst->getValueSizeInBits(0) <= BitWidth &&
10098 "Extracted slice is bigger than the whole type!");
10099 APInt UsedBits(Inst->getValueSizeInBits(0), 0);
10100 UsedBits.setAllBits();
10101 UsedBits = UsedBits.zext(BitWidth);
10102 UsedBits <<= Shift;
10106 /// \brief Get the size of the slice to be loaded in bytes.
10107 unsigned getLoadedSize() const {
10108 unsigned SliceSize = getUsedBits().countPopulation();
10109 assert(!(SliceSize & 0x7) && "Size is not a multiple of a byte.");
10110 return SliceSize / 8;
10113 /// \brief Get the type that will be loaded for this slice.
10114 /// Note: This may not be the final type for the slice.
10115 EVT getLoadedType() const {
10116 assert(DAG && "Missing context");
10117 LLVMContext &Ctxt = *DAG->getContext();
10118 return EVT::getIntegerVT(Ctxt, getLoadedSize() * 8);
10121 /// \brief Get the alignment of the load used for this slice.
10122 unsigned getAlignment() const {
10123 unsigned Alignment = Origin->getAlignment();
10124 unsigned Offset = getOffsetFromBase();
10126 Alignment = MinAlign(Alignment, Alignment + Offset);
10130 /// \brief Check if this slice can be rewritten with legal operations.
10131 bool isLegal() const {
10132 // An invalid slice is not legal.
10133 if (!Origin || !Inst || !DAG)
10136 // Offsets are for indexed load only, we do not handle that.
10137 if (Origin->getOffset().getOpcode() != ISD::UNDEF)
10140 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
10142 // Check that the type is legal.
10143 EVT SliceType = getLoadedType();
10144 if (!TLI.isTypeLegal(SliceType))
10147 // Check that the load is legal for this type.
10148 if (!TLI.isOperationLegal(ISD::LOAD, SliceType))
10151 // Check that the offset can be computed.
10152 // 1. Check its type.
10153 EVT PtrType = Origin->getBasePtr().getValueType();
10154 if (PtrType == MVT::Untyped || PtrType.isExtended())
10157 // 2. Check that it fits in the immediate.
10158 if (!TLI.isLegalAddImmediate(getOffsetFromBase()))
10161 // 3. Check that the computation is legal.
10162 if (!TLI.isOperationLegal(ISD::ADD, PtrType))
10165 // Check that the zext is legal if it needs one.
10166 EVT TruncateType = Inst->getValueType(0);
10167 if (TruncateType != SliceType &&
10168 !TLI.isOperationLegal(ISD::ZERO_EXTEND, TruncateType))
10174 /// \brief Get the offset in bytes of this slice in the original chunk of
10176 /// \pre DAG != nullptr.
10177 uint64_t getOffsetFromBase() const {
10178 assert(DAG && "Missing context.");
10179 bool IsBigEndian = DAG->getDataLayout().isBigEndian();
10180 assert(!(Shift & 0x7) && "Shifts not aligned on Bytes are not supported.");
10181 uint64_t Offset = Shift / 8;
10182 unsigned TySizeInBytes = Origin->getValueSizeInBits(0) / 8;
10183 assert(!(Origin->getValueSizeInBits(0) & 0x7) &&
10184 "The size of the original loaded type is not a multiple of a"
10186 // If Offset is bigger than TySizeInBytes, it means we are loading all
10187 // zeros. This should have been optimized before in the process.
10188 assert(TySizeInBytes > Offset &&
10189 "Invalid shift amount for given loaded size");
10191 Offset = TySizeInBytes - Offset - getLoadedSize();
10195 /// \brief Generate the sequence of instructions to load the slice
10196 /// represented by this object and redirect the uses of this slice to
10197 /// this new sequence of instructions.
10198 /// \pre this->Inst && this->Origin are valid Instructions and this
10199 /// object passed the legal check: LoadedSlice::isLegal returned true.
10200 /// \return The last instruction of the sequence used to load the slice.
10201 SDValue loadSlice() const {
10202 assert(Inst && Origin && "Unable to replace a non-existing slice.");
10203 const SDValue &OldBaseAddr = Origin->getBasePtr();
10204 SDValue BaseAddr = OldBaseAddr;
10205 // Get the offset in that chunk of bytes w.r.t. the endianess.
10206 int64_t Offset = static_cast<int64_t>(getOffsetFromBase());
10207 assert(Offset >= 0 && "Offset too big to fit in int64_t!");
10209 // BaseAddr = BaseAddr + Offset.
10210 EVT ArithType = BaseAddr.getValueType();
10212 BaseAddr = DAG->getNode(ISD::ADD, DL, ArithType, BaseAddr,
10213 DAG->getConstant(Offset, DL, ArithType));
10216 // Create the type of the loaded slice according to its size.
10217 EVT SliceType = getLoadedType();
10219 // Create the load for the slice.
10220 SDValue LastInst = DAG->getLoad(
10221 SliceType, SDLoc(Origin), Origin->getChain(), BaseAddr,
10222 Origin->getPointerInfo().getWithOffset(Offset), Origin->isVolatile(),
10223 Origin->isNonTemporal(), Origin->isInvariant(), getAlignment());
10224 // If the final type is not the same as the loaded type, this means that
10225 // we have to pad with zero. Create a zero extend for that.
10226 EVT FinalType = Inst->getValueType(0);
10227 if (SliceType != FinalType)
10229 DAG->getNode(ISD::ZERO_EXTEND, SDLoc(LastInst), FinalType, LastInst);
10233 /// \brief Check if this slice can be merged with an expensive cross register
10234 /// bank copy. E.g.,
10236 /// f = bitcast i32 i to float
10237 bool canMergeExpensiveCrossRegisterBankCopy() const {
10238 if (!Inst || !Inst->hasOneUse())
10240 SDNode *Use = *Inst->use_begin();
10241 if (Use->getOpcode() != ISD::BITCAST)
10243 assert(DAG && "Missing context");
10244 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
10245 EVT ResVT = Use->getValueType(0);
10246 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT());
10247 const TargetRegisterClass *ArgRC =
10248 TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT());
10249 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT))
10252 // At this point, we know that we perform a cross-register-bank copy.
10253 // Check if it is expensive.
10254 const TargetRegisterInfo *TRI = DAG->getSubtarget().getRegisterInfo();
10255 // Assume bitcasts are cheap, unless both register classes do not
10256 // explicitly share a common sub class.
10257 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC))
10260 // Check if it will be merged with the load.
10261 // 1. Check the alignment constraint.
10262 unsigned RequiredAlignment = DAG->getDataLayout().getABITypeAlignment(
10263 ResVT.getTypeForEVT(*DAG->getContext()));
10265 if (RequiredAlignment > getAlignment())
10268 // 2. Check that the load is a legal operation for that type.
10269 if (!TLI.isOperationLegal(ISD::LOAD, ResVT))
10272 // 3. Check that we do not have a zext in the way.
10273 if (Inst->getValueType(0) != getLoadedType())
10281 /// \brief Check that all bits set in \p UsedBits form a dense region, i.e.,
10282 /// \p UsedBits looks like 0..0 1..1 0..0.
10283 static bool areUsedBitsDense(const APInt &UsedBits) {
10284 // If all the bits are one, this is dense!
10285 if (UsedBits.isAllOnesValue())
10288 // Get rid of the unused bits on the right.
10289 APInt NarrowedUsedBits = UsedBits.lshr(UsedBits.countTrailingZeros());
10290 // Get rid of the unused bits on the left.
10291 if (NarrowedUsedBits.countLeadingZeros())
10292 NarrowedUsedBits = NarrowedUsedBits.trunc(NarrowedUsedBits.getActiveBits());
10293 // Check that the chunk of bits is completely used.
10294 return NarrowedUsedBits.isAllOnesValue();
10297 /// \brief Check whether or not \p First and \p Second are next to each other
10298 /// in memory. This means that there is no hole between the bits loaded
10299 /// by \p First and the bits loaded by \p Second.
10300 static bool areSlicesNextToEachOther(const LoadedSlice &First,
10301 const LoadedSlice &Second) {
10302 assert(First.Origin == Second.Origin && First.Origin &&
10303 "Unable to match different memory origins.");
10304 APInt UsedBits = First.getUsedBits();
10305 assert((UsedBits & Second.getUsedBits()) == 0 &&
10306 "Slices are not supposed to overlap.");
10307 UsedBits |= Second.getUsedBits();
10308 return areUsedBitsDense(UsedBits);
10311 /// \brief Adjust the \p GlobalLSCost according to the target
10312 /// paring capabilities and the layout of the slices.
10313 /// \pre \p GlobalLSCost should account for at least as many loads as
10314 /// there is in the slices in \p LoadedSlices.
10315 static void adjustCostForPairing(SmallVectorImpl<LoadedSlice> &LoadedSlices,
10316 LoadedSlice::Cost &GlobalLSCost) {
10317 unsigned NumberOfSlices = LoadedSlices.size();
10318 // If there is less than 2 elements, no pairing is possible.
10319 if (NumberOfSlices < 2)
10322 // Sort the slices so that elements that are likely to be next to each
10323 // other in memory are next to each other in the list.
10324 std::sort(LoadedSlices.begin(), LoadedSlices.end(),
10325 [](const LoadedSlice &LHS, const LoadedSlice &RHS) {
10326 assert(LHS.Origin == RHS.Origin && "Different bases not implemented.");
10327 return LHS.getOffsetFromBase() < RHS.getOffsetFromBase();
10329 const TargetLowering &TLI = LoadedSlices[0].DAG->getTargetLoweringInfo();
10330 // First (resp. Second) is the first (resp. Second) potentially candidate
10331 // to be placed in a paired load.
10332 const LoadedSlice *First = nullptr;
10333 const LoadedSlice *Second = nullptr;
10334 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice,
10335 // Set the beginning of the pair.
10338 Second = &LoadedSlices[CurrSlice];
10340 // If First is NULL, it means we start a new pair.
10341 // Get to the next slice.
10345 EVT LoadedType = First->getLoadedType();
10347 // If the types of the slices are different, we cannot pair them.
10348 if (LoadedType != Second->getLoadedType())
10351 // Check if the target supplies paired loads for this type.
10352 unsigned RequiredAlignment = 0;
10353 if (!TLI.hasPairedLoad(LoadedType, RequiredAlignment)) {
10354 // move to the next pair, this type is hopeless.
10358 // Check if we meet the alignment requirement.
10359 if (RequiredAlignment > First->getAlignment())
10362 // Check that both loads are next to each other in memory.
10363 if (!areSlicesNextToEachOther(*First, *Second))
10366 assert(GlobalLSCost.Loads > 0 && "We save more loads than we created!");
10367 --GlobalLSCost.Loads;
10368 // Move to the next pair.
10373 /// \brief Check the profitability of all involved LoadedSlice.
10374 /// Currently, it is considered profitable if there is exactly two
10375 /// involved slices (1) which are (2) next to each other in memory, and
10376 /// whose cost (\see LoadedSlice::Cost) is smaller than the original load (3).
10378 /// Note: The order of the elements in \p LoadedSlices may be modified, but not
10379 /// the elements themselves.
10381 /// FIXME: When the cost model will be mature enough, we can relax
10382 /// constraints (1) and (2).
10383 static bool isSlicingProfitable(SmallVectorImpl<LoadedSlice> &LoadedSlices,
10384 const APInt &UsedBits, bool ForCodeSize) {
10385 unsigned NumberOfSlices = LoadedSlices.size();
10386 if (StressLoadSlicing)
10387 return NumberOfSlices > 1;
10390 if (NumberOfSlices != 2)
10394 if (!areUsedBitsDense(UsedBits))
10398 LoadedSlice::Cost OrigCost(ForCodeSize), GlobalSlicingCost(ForCodeSize);
10399 // The original code has one big load.
10400 OrigCost.Loads = 1;
10401 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice) {
10402 const LoadedSlice &LS = LoadedSlices[CurrSlice];
10403 // Accumulate the cost of all the slices.
10404 LoadedSlice::Cost SliceCost(LS, ForCodeSize);
10405 GlobalSlicingCost += SliceCost;
10407 // Account as cost in the original configuration the gain obtained
10408 // with the current slices.
10409 OrigCost.addSliceGain(LS);
10412 // If the target supports paired load, adjust the cost accordingly.
10413 adjustCostForPairing(LoadedSlices, GlobalSlicingCost);
10414 return OrigCost > GlobalSlicingCost;
10417 /// \brief If the given load, \p LI, is used only by trunc or trunc(lshr)
10418 /// operations, split it in the various pieces being extracted.
10420 /// This sort of thing is introduced by SROA.
10421 /// This slicing takes care not to insert overlapping loads.
10422 /// \pre LI is a simple load (i.e., not an atomic or volatile load).
10423 bool DAGCombiner::SliceUpLoad(SDNode *N) {
10424 if (Level < AfterLegalizeDAG)
10427 LoadSDNode *LD = cast<LoadSDNode>(N);
10428 if (LD->isVolatile() || !ISD::isNormalLoad(LD) ||
10429 !LD->getValueType(0).isInteger())
10432 // Keep track of already used bits to detect overlapping values.
10433 // In that case, we will just abort the transformation.
10434 APInt UsedBits(LD->getValueSizeInBits(0), 0);
10436 SmallVector<LoadedSlice, 4> LoadedSlices;
10438 // Check if this load is used as several smaller chunks of bits.
10439 // Basically, look for uses in trunc or trunc(lshr) and record a new chain
10440 // of computation for each trunc.
10441 for (SDNode::use_iterator UI = LD->use_begin(), UIEnd = LD->use_end();
10442 UI != UIEnd; ++UI) {
10443 // Skip the uses of the chain.
10444 if (UI.getUse().getResNo() != 0)
10447 SDNode *User = *UI;
10448 unsigned Shift = 0;
10450 // Check if this is a trunc(lshr).
10451 if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
10452 isa<ConstantSDNode>(User->getOperand(1))) {
10453 Shift = cast<ConstantSDNode>(User->getOperand(1))->getZExtValue();
10454 User = *User->use_begin();
10457 // At this point, User is a Truncate, iff we encountered, trunc or
10459 if (User->getOpcode() != ISD::TRUNCATE)
10462 // The width of the type must be a power of 2 and greater than 8-bits.
10463 // Otherwise the load cannot be represented in LLVM IR.
10464 // Moreover, if we shifted with a non-8-bits multiple, the slice
10465 // will be across several bytes. We do not support that.
10466 unsigned Width = User->getValueSizeInBits(0);
10467 if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7))
10470 // Build the slice for this chain of computations.
10471 LoadedSlice LS(User, LD, Shift, &DAG);
10472 APInt CurrentUsedBits = LS.getUsedBits();
10474 // Check if this slice overlaps with another.
10475 if ((CurrentUsedBits & UsedBits) != 0)
10477 // Update the bits used globally.
10478 UsedBits |= CurrentUsedBits;
10480 // Check if the new slice would be legal.
10484 // Record the slice.
10485 LoadedSlices.push_back(LS);
10488 // Abort slicing if it does not seem to be profitable.
10489 if (!isSlicingProfitable(LoadedSlices, UsedBits, ForCodeSize))
10494 // Rewrite each chain to use an independent load.
10495 // By construction, each chain can be represented by a unique load.
10497 // Prepare the argument for the new token factor for all the slices.
10498 SmallVector<SDValue, 8> ArgChains;
10499 for (SmallVectorImpl<LoadedSlice>::const_iterator
10500 LSIt = LoadedSlices.begin(),
10501 LSItEnd = LoadedSlices.end();
10502 LSIt != LSItEnd; ++LSIt) {
10503 SDValue SliceInst = LSIt->loadSlice();
10504 CombineTo(LSIt->Inst, SliceInst, true);
10505 if (SliceInst.getNode()->getOpcode() != ISD::LOAD)
10506 SliceInst = SliceInst.getOperand(0);
10507 assert(SliceInst->getOpcode() == ISD::LOAD &&
10508 "It takes more than a zext to get to the loaded slice!!");
10509 ArgChains.push_back(SliceInst.getValue(1));
10512 SDValue Chain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other,
10514 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
10518 /// Check to see if V is (and load (ptr), imm), where the load is having
10519 /// specific bytes cleared out. If so, return the byte size being masked out
10520 /// and the shift amount.
10521 static std::pair<unsigned, unsigned>
10522 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
10523 std::pair<unsigned, unsigned> Result(0, 0);
10525 // Check for the structure we're looking for.
10526 if (V->getOpcode() != ISD::AND ||
10527 !isa<ConstantSDNode>(V->getOperand(1)) ||
10528 !ISD::isNormalLoad(V->getOperand(0).getNode()))
10531 // Check the chain and pointer.
10532 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
10533 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
10535 // The store should be chained directly to the load or be an operand of a
10537 if (LD == Chain.getNode())
10539 else if (Chain->getOpcode() != ISD::TokenFactor)
10540 return Result; // Fail.
10543 for (const SDValue &ChainOp : Chain->op_values())
10544 if (ChainOp.getNode() == LD) {
10548 if (!isOk) return Result;
10551 // This only handles simple types.
10552 if (V.getValueType() != MVT::i16 &&
10553 V.getValueType() != MVT::i32 &&
10554 V.getValueType() != MVT::i64)
10557 // Check the constant mask. Invert it so that the bits being masked out are
10558 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
10559 // follow the sign bit for uniformity.
10560 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
10561 unsigned NotMaskLZ = countLeadingZeros(NotMask);
10562 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
10563 unsigned NotMaskTZ = countTrailingZeros(NotMask);
10564 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
10565 if (NotMaskLZ == 64) return Result; // All zero mask.
10567 // See if we have a continuous run of bits. If so, we have 0*1+0*
10568 if (countTrailingOnes(NotMask >> NotMaskTZ) + NotMaskTZ + NotMaskLZ != 64)
10571 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
10572 if (V.getValueType() != MVT::i64 && NotMaskLZ)
10573 NotMaskLZ -= 64-V.getValueSizeInBits();
10575 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
10576 switch (MaskedBytes) {
10580 default: return Result; // All one mask, or 5-byte mask.
10583 // Verify that the first bit starts at a multiple of mask so that the access
10584 // is aligned the same as the access width.
10585 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
10587 Result.first = MaskedBytes;
10588 Result.second = NotMaskTZ/8;
10593 /// Check to see if IVal is something that provides a value as specified by
10594 /// MaskInfo. If so, replace the specified store with a narrower store of
10595 /// truncated IVal.
10597 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
10598 SDValue IVal, StoreSDNode *St,
10600 unsigned NumBytes = MaskInfo.first;
10601 unsigned ByteShift = MaskInfo.second;
10602 SelectionDAG &DAG = DC->getDAG();
10604 // Check to see if IVal is all zeros in the part being masked in by the 'or'
10605 // that uses this. If not, this is not a replacement.
10606 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
10607 ByteShift*8, (ByteShift+NumBytes)*8);
10608 if (!DAG.MaskedValueIsZero(IVal, Mask)) return nullptr;
10610 // Check that it is legal on the target to do this. It is legal if the new
10611 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
10613 MVT VT = MVT::getIntegerVT(NumBytes*8);
10614 if (!DC->isTypeLegal(VT))
10617 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
10618 // shifted by ByteShift and truncated down to NumBytes.
10621 IVal = DAG.getNode(ISD::SRL, DL, IVal.getValueType(), IVal,
10622 DAG.getConstant(ByteShift*8, DL,
10623 DC->getShiftAmountTy(IVal.getValueType())));
10626 // Figure out the offset for the store and the alignment of the access.
10628 unsigned NewAlign = St->getAlignment();
10630 if (DAG.getDataLayout().isLittleEndian())
10631 StOffset = ByteShift;
10633 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
10635 SDValue Ptr = St->getBasePtr();
10638 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(),
10639 Ptr, DAG.getConstant(StOffset, DL, Ptr.getValueType()));
10640 NewAlign = MinAlign(NewAlign, StOffset);
10643 // Truncate down to the new size.
10644 IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal);
10647 return DAG.getStore(St->getChain(), SDLoc(St), IVal, Ptr,
10648 St->getPointerInfo().getWithOffset(StOffset),
10649 false, false, NewAlign).getNode();
10653 /// Look for sequence of load / op / store where op is one of 'or', 'xor', and
10654 /// 'and' of immediates. If 'op' is only touching some of the loaded bits, try
10655 /// narrowing the load and store if it would end up being a win for performance
10657 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
10658 StoreSDNode *ST = cast<StoreSDNode>(N);
10659 if (ST->isVolatile())
10662 SDValue Chain = ST->getChain();
10663 SDValue Value = ST->getValue();
10664 SDValue Ptr = ST->getBasePtr();
10665 EVT VT = Value.getValueType();
10667 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
10670 unsigned Opc = Value.getOpcode();
10672 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
10673 // is a byte mask indicating a consecutive number of bytes, check to see if
10674 // Y is known to provide just those bytes. If so, we try to replace the
10675 // load + replace + store sequence with a single (narrower) store, which makes
10677 if (Opc == ISD::OR) {
10678 std::pair<unsigned, unsigned> MaskedLoad;
10679 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
10680 if (MaskedLoad.first)
10681 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
10682 Value.getOperand(1), ST,this))
10683 return SDValue(NewST, 0);
10685 // Or is commutative, so try swapping X and Y.
10686 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
10687 if (MaskedLoad.first)
10688 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
10689 Value.getOperand(0), ST,this))
10690 return SDValue(NewST, 0);
10693 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
10694 Value.getOperand(1).getOpcode() != ISD::Constant)
10697 SDValue N0 = Value.getOperand(0);
10698 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
10699 Chain == SDValue(N0.getNode(), 1)) {
10700 LoadSDNode *LD = cast<LoadSDNode>(N0);
10701 if (LD->getBasePtr() != Ptr ||
10702 LD->getPointerInfo().getAddrSpace() !=
10703 ST->getPointerInfo().getAddrSpace())
10706 // Find the type to narrow it the load / op / store to.
10707 SDValue N1 = Value.getOperand(1);
10708 unsigned BitWidth = N1.getValueSizeInBits();
10709 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
10710 if (Opc == ISD::AND)
10711 Imm ^= APInt::getAllOnesValue(BitWidth);
10712 if (Imm == 0 || Imm.isAllOnesValue())
10714 unsigned ShAmt = Imm.countTrailingZeros();
10715 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
10716 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
10717 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
10718 // The narrowing should be profitable, the load/store operation should be
10719 // legal (or custom) and the store size should be equal to the NewVT width.
10720 while (NewBW < BitWidth &&
10721 (NewVT.getStoreSizeInBits() != NewBW ||
10722 !TLI.isOperationLegalOrCustom(Opc, NewVT) ||
10723 !TLI.isNarrowingProfitable(VT, NewVT))) {
10724 NewBW = NextPowerOf2(NewBW);
10725 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
10727 if (NewBW >= BitWidth)
10730 // If the lsb changed does not start at the type bitwidth boundary,
10731 // start at the previous one.
10733 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
10734 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt,
10735 std::min(BitWidth, ShAmt + NewBW));
10736 if ((Imm & Mask) == Imm) {
10737 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
10738 if (Opc == ISD::AND)
10739 NewImm ^= APInt::getAllOnesValue(NewBW);
10740 uint64_t PtrOff = ShAmt / 8;
10741 // For big endian targets, we need to adjust the offset to the pointer to
10742 // load the correct bytes.
10743 if (DAG.getDataLayout().isBigEndian())
10744 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
10746 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
10747 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
10748 if (NewAlign < DAG.getDataLayout().getABITypeAlignment(NewVTTy))
10751 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LD),
10752 Ptr.getValueType(), Ptr,
10753 DAG.getConstant(PtrOff, SDLoc(LD),
10754 Ptr.getValueType()));
10755 SDValue NewLD = DAG.getLoad(NewVT, SDLoc(N0),
10756 LD->getChain(), NewPtr,
10757 LD->getPointerInfo().getWithOffset(PtrOff),
10758 LD->isVolatile(), LD->isNonTemporal(),
10759 LD->isInvariant(), NewAlign,
10761 SDValue NewVal = DAG.getNode(Opc, SDLoc(Value), NewVT, NewLD,
10762 DAG.getConstant(NewImm, SDLoc(Value),
10764 SDValue NewST = DAG.getStore(Chain, SDLoc(N),
10766 ST->getPointerInfo().getWithOffset(PtrOff),
10767 false, false, NewAlign);
10769 AddToWorklist(NewPtr.getNode());
10770 AddToWorklist(NewLD.getNode());
10771 AddToWorklist(NewVal.getNode());
10772 WorklistRemover DeadNodes(*this);
10773 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
10782 /// For a given floating point load / store pair, if the load value isn't used
10783 /// by any other operations, then consider transforming the pair to integer
10784 /// load / store operations if the target deems the transformation profitable.
10785 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
10786 StoreSDNode *ST = cast<StoreSDNode>(N);
10787 SDValue Chain = ST->getChain();
10788 SDValue Value = ST->getValue();
10789 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
10790 Value.hasOneUse() &&
10791 Chain == SDValue(Value.getNode(), 1)) {
10792 LoadSDNode *LD = cast<LoadSDNode>(Value);
10793 EVT VT = LD->getMemoryVT();
10794 if (!VT.isFloatingPoint() ||
10795 VT != ST->getMemoryVT() ||
10796 LD->isNonTemporal() ||
10797 ST->isNonTemporal() ||
10798 LD->getPointerInfo().getAddrSpace() != 0 ||
10799 ST->getPointerInfo().getAddrSpace() != 0)
10802 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
10803 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
10804 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
10805 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
10806 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
10809 unsigned LDAlign = LD->getAlignment();
10810 unsigned STAlign = ST->getAlignment();
10811 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
10812 unsigned ABIAlign = DAG.getDataLayout().getABITypeAlignment(IntVTTy);
10813 if (LDAlign < ABIAlign || STAlign < ABIAlign)
10816 SDValue NewLD = DAG.getLoad(IntVT, SDLoc(Value),
10817 LD->getChain(), LD->getBasePtr(),
10818 LD->getPointerInfo(),
10819 false, false, false, LDAlign);
10821 SDValue NewST = DAG.getStore(NewLD.getValue(1), SDLoc(N),
10822 NewLD, ST->getBasePtr(),
10823 ST->getPointerInfo(),
10824 false, false, STAlign);
10826 AddToWorklist(NewLD.getNode());
10827 AddToWorklist(NewST.getNode());
10828 WorklistRemover DeadNodes(*this);
10829 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
10838 /// Helper struct to parse and store a memory address as base + index + offset.
10839 /// We ignore sign extensions when it is safe to do so.
10840 /// The following two expressions are not equivalent. To differentiate we need
10841 /// to store whether there was a sign extension involved in the index
10843 /// (load (i64 add (i64 copyfromreg %c)
10844 /// (i64 signextend (add (i8 load %index)
10848 /// (load (i64 add (i64 copyfromreg %c)
10849 /// (i64 signextend (i32 add (i32 signextend (i8 load %index))
10851 struct BaseIndexOffset {
10855 bool IsIndexSignExt;
10857 BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {}
10859 BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
10860 bool IsIndexSignExt) :
10861 Base(Base), Index(Index), Offset(Offset), IsIndexSignExt(IsIndexSignExt) {}
10863 bool equalBaseIndex(const BaseIndexOffset &Other) {
10864 return Other.Base == Base && Other.Index == Index &&
10865 Other.IsIndexSignExt == IsIndexSignExt;
10868 /// Parses tree in Ptr for base, index, offset addresses.
10869 static BaseIndexOffset match(SDValue Ptr) {
10870 bool IsIndexSignExt = false;
10872 // We only can pattern match BASE + INDEX + OFFSET. If Ptr is not an ADD
10873 // instruction, then it could be just the BASE or everything else we don't
10874 // know how to handle. Just use Ptr as BASE and give up.
10875 if (Ptr->getOpcode() != ISD::ADD)
10876 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
10878 // We know that we have at least an ADD instruction. Try to pattern match
10879 // the simple case of BASE + OFFSET.
10880 if (isa<ConstantSDNode>(Ptr->getOperand(1))) {
10881 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
10882 return BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset,
10886 // Inside a loop the current BASE pointer is calculated using an ADD and a
10887 // MUL instruction. In this case Ptr is the actual BASE pointer.
10888 // (i64 add (i64 %array_ptr)
10889 // (i64 mul (i64 %induction_var)
10890 // (i64 %element_size)))
10891 if (Ptr->getOperand(1)->getOpcode() == ISD::MUL)
10892 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
10894 // Look at Base + Index + Offset cases.
10895 SDValue Base = Ptr->getOperand(0);
10896 SDValue IndexOffset = Ptr->getOperand(1);
10898 // Skip signextends.
10899 if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) {
10900 IndexOffset = IndexOffset->getOperand(0);
10901 IsIndexSignExt = true;
10904 // Either the case of Base + Index (no offset) or something else.
10905 if (IndexOffset->getOpcode() != ISD::ADD)
10906 return BaseIndexOffset(Base, IndexOffset, 0, IsIndexSignExt);
10908 // Now we have the case of Base + Index + offset.
10909 SDValue Index = IndexOffset->getOperand(0);
10910 SDValue Offset = IndexOffset->getOperand(1);
10912 if (!isa<ConstantSDNode>(Offset))
10913 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
10915 // Ignore signextends.
10916 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
10917 Index = Index->getOperand(0);
10918 IsIndexSignExt = true;
10919 } else IsIndexSignExt = false;
10921 int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue();
10922 return BaseIndexOffset(Base, Index, Off, IsIndexSignExt);
10927 // This is a helper function for visitMUL to check the profitability
10928 // of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).
10929 // MulNode is the original multiply, AddNode is (add x, c1),
10930 // and ConstNode is c2.
10932 // If the (add x, c1) has multiple uses, we could increase
10933 // the number of adds if we make this transformation.
10934 // It would only be worth doing this if we can remove a
10935 // multiply in the process. Check for that here.
10939 // We're checking for cases where we have common "c3 * A" expressions.
10940 bool DAGCombiner::isMulAddWithConstProfitable(SDNode *MulNode,
10942 SDValue &ConstNode) {
10945 // If the add only has one use, this would be OK to do.
10946 if (AddNode.getNode()->hasOneUse())
10949 // Walk all the users of the constant with which we're multiplying.
10950 for (SDNode *Use : ConstNode->uses()) {
10952 if (Use == MulNode) // This use is the one we're on right now. Skip it.
10955 if (Use->getOpcode() == ISD::MUL) { // We have another multiply use.
10957 SDNode *MulVar = AddNode.getOperand(0).getNode();
10959 // OtherOp is what we're multiplying against the constant.
10960 if (Use->getOperand(0) == ConstNode)
10961 OtherOp = Use->getOperand(1).getNode();
10963 OtherOp = Use->getOperand(0).getNode();
10965 // Check to see if multiply is with the same operand of our "add".
10967 // ConstNode = CONST
10968 // Use = ConstNode * A <-- visiting Use. OtherOp is A.
10970 // AddNode = (A + c1) <-- MulVar is A.
10971 // = AddNode * ConstNode <-- current visiting instruction.
10973 // If we make this transformation, we will have a common
10974 // multiply (ConstNode * A) that we can save.
10975 if (OtherOp == MulVar)
10978 // Now check to see if a future expansion will give us a common
10981 // ConstNode = CONST
10982 // AddNode = (A + c1)
10983 // ... = AddNode * ConstNode <-- current visiting instruction.
10985 // OtherOp = (A + c2)
10986 // Use = OtherOp * ConstNode <-- visiting Use.
10988 // If we make this transformation, we will have a common
10989 // multiply (CONST * A) after we also do the same transformation
10990 // to the "t2" instruction.
10991 if (OtherOp->getOpcode() == ISD::ADD &&
10992 isConstantIntBuildVectorOrConstantInt(OtherOp->getOperand(1)) &&
10993 OtherOp->getOperand(0).getNode() == MulVar)
10998 // Didn't find a case where this would be profitable.
11002 SDValue DAGCombiner::getMergedConstantVectorStore(SelectionDAG &DAG,
11004 ArrayRef<MemOpLink> Stores,
11005 SmallVectorImpl<SDValue> &Chains,
11007 SmallVector<SDValue, 8> BuildVector;
11009 for (unsigned I = 0, E = Ty.getVectorNumElements(); I != E; ++I) {
11010 StoreSDNode *St = cast<StoreSDNode>(Stores[I].MemNode);
11011 Chains.push_back(St->getChain());
11012 BuildVector.push_back(St->getValue());
11015 return DAG.getNode(ISD::BUILD_VECTOR, SL, Ty, BuildVector);
11018 bool DAGCombiner::MergeStoresOfConstantsOrVecElts(
11019 SmallVectorImpl<MemOpLink> &StoreNodes, EVT MemVT,
11020 unsigned NumStores, bool IsConstantSrc, bool UseVector) {
11021 // Make sure we have something to merge.
11025 int64_t ElementSizeBytes = MemVT.getSizeInBits() / 8;
11026 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
11027 unsigned LatestNodeUsed = 0;
11029 for (unsigned i=0; i < NumStores; ++i) {
11030 // Find a chain for the new wide-store operand. Notice that some
11031 // of the store nodes that we found may not be selected for inclusion
11032 // in the wide store. The chain we use needs to be the chain of the
11033 // latest store node which is *used* and replaced by the wide store.
11034 if (StoreNodes[i].SequenceNum < StoreNodes[LatestNodeUsed].SequenceNum)
11035 LatestNodeUsed = i;
11038 SmallVector<SDValue, 8> Chains;
11040 // The latest Node in the DAG.
11041 LSBaseSDNode *LatestOp = StoreNodes[LatestNodeUsed].MemNode;
11042 SDLoc DL(StoreNodes[0].MemNode);
11046 bool IsVec = MemVT.isVector();
11047 unsigned Elts = NumStores;
11049 // When merging vector stores, get the total number of elements.
11050 Elts *= MemVT.getVectorNumElements();
11052 // Get the type for the merged vector store.
11053 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), Elts);
11054 assert(TLI.isTypeLegal(Ty) && "Illegal vector store");
11056 if (IsConstantSrc) {
11057 StoredVal = getMergedConstantVectorStore(DAG, DL, StoreNodes, Chains, Ty);
11059 SmallVector<SDValue, 8> Ops;
11060 for (unsigned i = 0; i < NumStores; ++i) {
11061 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
11062 SDValue Val = St->getValue();
11063 // All operands of BUILD_VECTOR / CONCAT_VECTOR must have the same type.
11064 if (Val.getValueType() != MemVT)
11066 Ops.push_back(Val);
11067 Chains.push_back(St->getChain());
11070 // Build the extracted vector elements back into a vector.
11071 StoredVal = DAG.getNode(IsVec ? ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
11074 // We should always use a vector store when merging extracted vector
11075 // elements, so this path implies a store of constants.
11076 assert(IsConstantSrc && "Merged vector elements should use vector store");
11078 unsigned SizeInBits = NumStores * ElementSizeBytes * 8;
11079 APInt StoreInt(SizeInBits, 0);
11081 // Construct a single integer constant which is made of the smaller
11082 // constant inputs.
11083 bool IsLE = DAG.getDataLayout().isLittleEndian();
11084 for (unsigned i = 0; i < NumStores; ++i) {
11085 unsigned Idx = IsLE ? (NumStores - 1 - i) : i;
11086 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode);
11087 Chains.push_back(St->getChain());
11089 SDValue Val = St->getValue();
11090 StoreInt <<= ElementSizeBytes * 8;
11091 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) {
11092 StoreInt |= C->getAPIntValue().zext(SizeInBits);
11093 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
11094 StoreInt |= C->getValueAPF().bitcastToAPInt().zext(SizeInBits);
11096 llvm_unreachable("Invalid constant element type");
11100 // Create the new Load and Store operations.
11101 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), SizeInBits);
11102 StoredVal = DAG.getConstant(StoreInt, DL, StoreTy);
11105 assert(!Chains.empty());
11107 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
11108 SDValue NewStore = DAG.getStore(NewChain, DL, StoredVal,
11109 FirstInChain->getBasePtr(),
11110 FirstInChain->getPointerInfo(),
11112 FirstInChain->getAlignment());
11114 // Replace the last store with the new store
11115 CombineTo(LatestOp, NewStore);
11116 // Erase all other stores.
11117 for (unsigned i = 0; i < NumStores; ++i) {
11118 if (StoreNodes[i].MemNode == LatestOp)
11120 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
11121 // ReplaceAllUsesWith will replace all uses that existed when it was
11122 // called, but graph optimizations may cause new ones to appear. For
11123 // example, the case in pr14333 looks like
11125 // St's chain -> St -> another store -> X
11127 // And the only difference from St to the other store is the chain.
11128 // When we change it's chain to be St's chain they become identical,
11129 // get CSEed and the net result is that X is now a use of St.
11130 // Since we know that St is redundant, just iterate.
11131 while (!St->use_empty())
11132 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain());
11133 deleteAndRecombine(St);
11139 void DAGCombiner::getStoreMergeAndAliasCandidates(
11140 StoreSDNode* St, SmallVectorImpl<MemOpLink> &StoreNodes,
11141 SmallVectorImpl<LSBaseSDNode*> &AliasLoadNodes) {
11142 // This holds the base pointer, index, and the offset in bytes from the base
11144 BaseIndexOffset BasePtr = BaseIndexOffset::match(St->getBasePtr());
11146 // We must have a base and an offset.
11147 if (!BasePtr.Base.getNode())
11150 // Do not handle stores to undef base pointers.
11151 if (BasePtr.Base.getOpcode() == ISD::UNDEF)
11154 // Walk up the chain and look for nodes with offsets from the same
11155 // base pointer. Stop when reaching an instruction with a different kind
11156 // or instruction which has a different base pointer.
11157 EVT MemVT = St->getMemoryVT();
11159 StoreSDNode *Index = St;
11162 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
11163 : DAG.getSubtarget().useAA();
11166 // Look at other users of the same chain. Stores on the same chain do not
11167 // alias. If combiner-aa is enabled, non-aliasing stores are canonicalized
11168 // to be on the same chain, so don't bother looking at adjacent chains.
11170 SDValue Chain = St->getChain();
11171 for (auto I = Chain->use_begin(), E = Chain->use_end(); I != E; ++I) {
11172 if (StoreSDNode *OtherST = dyn_cast<StoreSDNode>(*I)) {
11173 if (I.getOperandNo() != 0)
11176 if (OtherST->isVolatile() || OtherST->isIndexed())
11179 if (OtherST->getMemoryVT() != MemVT)
11182 BaseIndexOffset Ptr = BaseIndexOffset::match(OtherST->getBasePtr());
11184 if (Ptr.equalBaseIndex(BasePtr))
11185 StoreNodes.push_back(MemOpLink(OtherST, Ptr.Offset, Seq++));
11193 // If the chain has more than one use, then we can't reorder the mem ops.
11194 if (Index != St && !SDValue(Index, 0)->hasOneUse())
11197 // Find the base pointer and offset for this memory node.
11198 BaseIndexOffset Ptr = BaseIndexOffset::match(Index->getBasePtr());
11200 // Check that the base pointer is the same as the original one.
11201 if (!Ptr.equalBaseIndex(BasePtr))
11204 // The memory operands must not be volatile.
11205 if (Index->isVolatile() || Index->isIndexed())
11209 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index))
11210 if (St->isTruncatingStore())
11213 // The stored memory type must be the same.
11214 if (Index->getMemoryVT() != MemVT)
11217 // We do not allow under-aligned stores in order to prevent
11218 // overriding stores. NOTE: this is a bad hack. Alignment SHOULD
11219 // be irrelevant here; what MATTERS is that we not move memory
11220 // operations that potentially overlap past each-other.
11221 if (Index->getAlignment() < MemVT.getStoreSize())
11224 // We found a potential memory operand to merge.
11225 StoreNodes.push_back(MemOpLink(Index, Ptr.Offset, Seq++));
11227 // Find the next memory operand in the chain. If the next operand in the
11228 // chain is a store then move up and continue the scan with the next
11229 // memory operand. If the next operand is a load save it and use alias
11230 // information to check if it interferes with anything.
11231 SDNode *NextInChain = Index->getChain().getNode();
11233 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) {
11234 // We found a store node. Use it for the next iteration.
11237 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) {
11238 if (Ldn->isVolatile()) {
11243 // Save the load node for later. Continue the scan.
11244 AliasLoadNodes.push_back(Ldn);
11245 NextInChain = Ldn->getChain().getNode();
11255 bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
11256 if (OptLevel == CodeGenOpt::None)
11259 EVT MemVT = St->getMemoryVT();
11260 int64_t ElementSizeBytes = MemVT.getSizeInBits() / 8;
11261 bool NoVectors = DAG.getMachineFunction().getFunction()->hasFnAttribute(
11262 Attribute::NoImplicitFloat);
11264 // This function cannot currently deal with non-byte-sized memory sizes.
11265 if (ElementSizeBytes * 8 != MemVT.getSizeInBits())
11268 if (!MemVT.isSimple())
11271 // Perform an early exit check. Do not bother looking at stored values that
11272 // are not constants, loads, or extracted vector elements.
11273 SDValue StoredVal = St->getValue();
11274 bool IsLoadSrc = isa<LoadSDNode>(StoredVal);
11275 bool IsConstantSrc = isa<ConstantSDNode>(StoredVal) ||
11276 isa<ConstantFPSDNode>(StoredVal);
11277 bool IsExtractVecSrc = (StoredVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
11278 StoredVal.getOpcode() == ISD::EXTRACT_SUBVECTOR);
11280 if (!IsConstantSrc && !IsLoadSrc && !IsExtractVecSrc)
11283 // Don't merge vectors into wider vectors if the source data comes from loads.
11284 // TODO: This restriction can be lifted by using logic similar to the
11285 // ExtractVecSrc case.
11286 if (MemVT.isVector() && IsLoadSrc)
11289 // Only look at ends of store sequences.
11290 SDValue Chain = SDValue(St, 0);
11291 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
11294 // Save the LoadSDNodes that we find in the chain.
11295 // We need to make sure that these nodes do not interfere with
11296 // any of the store nodes.
11297 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
11299 // Save the StoreSDNodes that we find in the chain.
11300 SmallVector<MemOpLink, 8> StoreNodes;
11302 getStoreMergeAndAliasCandidates(St, StoreNodes, AliasLoadNodes);
11304 // Check if there is anything to merge.
11305 if (StoreNodes.size() < 2)
11308 // Sort the memory operands according to their distance from the
11309 // base pointer. As a secondary criteria: make sure stores coming
11310 // later in the code come first in the list. This is important for
11311 // the non-UseAA case, because we're merging stores into the FINAL
11312 // store along a chain which potentially contains aliasing stores.
11313 // Thus, if there are multiple stores to the same address, the last
11314 // one can be considered for merging but not the others.
11315 std::sort(StoreNodes.begin(), StoreNodes.end(),
11316 [](MemOpLink LHS, MemOpLink RHS) {
11317 return LHS.OffsetFromBase < RHS.OffsetFromBase ||
11318 (LHS.OffsetFromBase == RHS.OffsetFromBase &&
11319 LHS.SequenceNum < RHS.SequenceNum);
11322 // Scan the memory operations on the chain and find the first non-consecutive
11323 // store memory address.
11324 unsigned LastConsecutiveStore = 0;
11325 int64_t StartAddress = StoreNodes[0].OffsetFromBase;
11326 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) {
11328 // Check that the addresses are consecutive starting from the second
11329 // element in the list of stores.
11331 int64_t CurrAddress = StoreNodes[i].OffsetFromBase;
11332 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
11336 // Check if this store interferes with any of the loads that we found.
11337 // If we find a load that alias with this store. Stop the sequence.
11338 if (std::any_of(AliasLoadNodes.begin(), AliasLoadNodes.end(),
11339 [&](LSBaseSDNode* Ldn) {
11340 return isAlias(Ldn, StoreNodes[i].MemNode);
11344 // Mark this node as useful.
11345 LastConsecutiveStore = i;
11348 // The node with the lowest store address.
11349 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
11350 unsigned FirstStoreAS = FirstInChain->getAddressSpace();
11351 unsigned FirstStoreAlign = FirstInChain->getAlignment();
11352 LLVMContext &Context = *DAG.getContext();
11353 const DataLayout &DL = DAG.getDataLayout();
11355 // Store the constants into memory as one consecutive store.
11356 if (IsConstantSrc) {
11357 unsigned LastLegalType = 0;
11358 unsigned LastLegalVectorType = 0;
11359 bool NonZero = false;
11360 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
11361 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
11362 SDValue StoredVal = St->getValue();
11364 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) {
11365 NonZero |= !C->isNullValue();
11366 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
11367 NonZero |= !C->getConstantFPValue()->isNullValue();
11373 // Find a legal type for the constant store.
11374 unsigned SizeInBits = (i+1) * ElementSizeBytes * 8;
11375 EVT StoreTy = EVT::getIntegerVT(Context, SizeInBits);
11377 if (TLI.isTypeLegal(StoreTy) &&
11378 TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstStoreAS,
11379 FirstStoreAlign, &IsFast) && IsFast) {
11380 LastLegalType = i+1;
11381 // Or check whether a truncstore is legal.
11382 } else if (TLI.getTypeAction(Context, StoreTy) ==
11383 TargetLowering::TypePromoteInteger) {
11384 EVT LegalizedStoredValueTy =
11385 TLI.getTypeToTransformTo(Context, StoredVal.getValueType());
11386 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
11387 TLI.allowsMemoryAccess(Context, DL, LegalizedStoredValueTy,
11388 FirstStoreAS, FirstStoreAlign, &IsFast) &&
11390 LastLegalType = i + 1;
11394 // We only use vectors if the constant is known to be zero or the target
11395 // allows it and the function is not marked with the noimplicitfloat
11397 if ((!NonZero || TLI.storeOfVectorConstantIsCheap(MemVT, i+1,
11400 // Find a legal type for the vector store.
11401 EVT Ty = EVT::getVectorVT(Context, MemVT, i+1);
11402 if (TLI.isTypeLegal(Ty) &&
11403 TLI.allowsMemoryAccess(Context, DL, Ty, FirstStoreAS,
11404 FirstStoreAlign, &IsFast) && IsFast)
11405 LastLegalVectorType = i + 1;
11409 // Check if we found a legal integer type to store.
11410 if (LastLegalType == 0 && LastLegalVectorType == 0)
11413 bool UseVector = (LastLegalVectorType > LastLegalType) && !NoVectors;
11414 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType;
11416 return MergeStoresOfConstantsOrVecElts(StoreNodes, MemVT, NumElem,
11420 // When extracting multiple vector elements, try to store them
11421 // in one vector store rather than a sequence of scalar stores.
11422 if (IsExtractVecSrc) {
11423 unsigned NumStoresToMerge = 0;
11424 bool IsVec = MemVT.isVector();
11425 for (unsigned i = 0; i < LastConsecutiveStore + 1; ++i) {
11426 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
11427 unsigned StoreValOpcode = St->getValue().getOpcode();
11428 // This restriction could be loosened.
11429 // Bail out if any stored values are not elements extracted from a vector.
11430 // It should be possible to handle mixed sources, but load sources need
11431 // more careful handling (see the block of code below that handles
11432 // consecutive loads).
11433 if (StoreValOpcode != ISD::EXTRACT_VECTOR_ELT &&
11434 StoreValOpcode != ISD::EXTRACT_SUBVECTOR)
11437 // Find a legal type for the vector store.
11438 unsigned Elts = i + 1;
11440 // When merging vector stores, get the total number of elements.
11441 Elts *= MemVT.getVectorNumElements();
11443 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), Elts);
11445 if (TLI.isTypeLegal(Ty) &&
11446 TLI.allowsMemoryAccess(Context, DL, Ty, FirstStoreAS,
11447 FirstStoreAlign, &IsFast) && IsFast)
11448 NumStoresToMerge = i + 1;
11451 return MergeStoresOfConstantsOrVecElts(StoreNodes, MemVT, NumStoresToMerge,
11455 // Below we handle the case of multiple consecutive stores that
11456 // come from multiple consecutive loads. We merge them into a single
11457 // wide load and a single wide store.
11459 // Look for load nodes which are used by the stored values.
11460 SmallVector<MemOpLink, 8> LoadNodes;
11462 // Find acceptable loads. Loads need to have the same chain (token factor),
11463 // must not be zext, volatile, indexed, and they must be consecutive.
11464 BaseIndexOffset LdBasePtr;
11465 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
11466 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
11467 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
11470 // Loads must only have one use.
11471 if (!Ld->hasNUsesOfValue(1, 0))
11474 // The memory operands must not be volatile.
11475 if (Ld->isVolatile() || Ld->isIndexed())
11478 // We do not accept ext loads.
11479 if (Ld->getExtensionType() != ISD::NON_EXTLOAD)
11482 // The stored memory type must be the same.
11483 if (Ld->getMemoryVT() != MemVT)
11486 BaseIndexOffset LdPtr = BaseIndexOffset::match(Ld->getBasePtr());
11487 // If this is not the first ptr that we check.
11488 if (LdBasePtr.Base.getNode()) {
11489 // The base ptr must be the same.
11490 if (!LdPtr.equalBaseIndex(LdBasePtr))
11493 // Check that all other base pointers are the same as this one.
11497 // We found a potential memory operand to merge.
11498 LoadNodes.push_back(MemOpLink(Ld, LdPtr.Offset, 0));
11501 if (LoadNodes.size() < 2)
11504 // If we have load/store pair instructions and we only have two values,
11506 unsigned RequiredAlignment;
11507 if (LoadNodes.size() == 2 && TLI.hasPairedLoad(MemVT, RequiredAlignment) &&
11508 St->getAlignment() >= RequiredAlignment)
11511 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode);
11512 unsigned FirstLoadAS = FirstLoad->getAddressSpace();
11513 unsigned FirstLoadAlign = FirstLoad->getAlignment();
11515 // Scan the memory operations on the chain and find the first non-consecutive
11516 // load memory address. These variables hold the index in the store node
11518 unsigned LastConsecutiveLoad = 0;
11519 // This variable refers to the size and not index in the array.
11520 unsigned LastLegalVectorType = 0;
11521 unsigned LastLegalIntegerType = 0;
11522 StartAddress = LoadNodes[0].OffsetFromBase;
11523 SDValue FirstChain = FirstLoad->getChain();
11524 for (unsigned i = 1; i < LoadNodes.size(); ++i) {
11525 // All loads must share the same chain.
11526 if (LoadNodes[i].MemNode->getChain() != FirstChain)
11529 int64_t CurrAddress = LoadNodes[i].OffsetFromBase;
11530 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
11532 LastConsecutiveLoad = i;
11533 // Find a legal type for the vector store.
11534 EVT StoreTy = EVT::getVectorVT(Context, MemVT, i+1);
11535 bool IsFastSt, IsFastLd;
11536 if (TLI.isTypeLegal(StoreTy) &&
11537 TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstStoreAS,
11538 FirstStoreAlign, &IsFastSt) && IsFastSt &&
11539 TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstLoadAS,
11540 FirstLoadAlign, &IsFastLd) && IsFastLd) {
11541 LastLegalVectorType = i + 1;
11544 // Find a legal type for the integer store.
11545 unsigned SizeInBits = (i+1) * ElementSizeBytes * 8;
11546 StoreTy = EVT::getIntegerVT(Context, SizeInBits);
11547 if (TLI.isTypeLegal(StoreTy) &&
11548 TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstStoreAS,
11549 FirstStoreAlign, &IsFastSt) && IsFastSt &&
11550 TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstLoadAS,
11551 FirstLoadAlign, &IsFastLd) && IsFastLd)
11552 LastLegalIntegerType = i + 1;
11553 // Or check whether a truncstore and extload is legal.
11554 else if (TLI.getTypeAction(Context, StoreTy) ==
11555 TargetLowering::TypePromoteInteger) {
11556 EVT LegalizedStoredValueTy =
11557 TLI.getTypeToTransformTo(Context, StoreTy);
11558 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
11559 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LegalizedStoredValueTy, StoreTy) &&
11560 TLI.isLoadExtLegal(ISD::SEXTLOAD, LegalizedStoredValueTy, StoreTy) &&
11561 TLI.isLoadExtLegal(ISD::EXTLOAD, LegalizedStoredValueTy, StoreTy) &&
11562 TLI.allowsMemoryAccess(Context, DL, LegalizedStoredValueTy,
11563 FirstStoreAS, FirstStoreAlign, &IsFastSt) &&
11565 TLI.allowsMemoryAccess(Context, DL, LegalizedStoredValueTy,
11566 FirstLoadAS, FirstLoadAlign, &IsFastLd) &&
11568 LastLegalIntegerType = i+1;
11572 // Only use vector types if the vector type is larger than the integer type.
11573 // If they are the same, use integers.
11574 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType && !NoVectors;
11575 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType);
11577 // We add +1 here because the LastXXX variables refer to location while
11578 // the NumElem refers to array/index size.
11579 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1;
11580 NumElem = std::min(LastLegalType, NumElem);
11585 // Collect the chains from all merged stores.
11586 SmallVector<SDValue, 8> MergeStoreChains;
11587 MergeStoreChains.push_back(StoreNodes[0].MemNode->getChain());
11589 // The latest Node in the DAG.
11590 unsigned LatestNodeUsed = 0;
11591 for (unsigned i=1; i<NumElem; ++i) {
11592 // Find a chain for the new wide-store operand. Notice that some
11593 // of the store nodes that we found may not be selected for inclusion
11594 // in the wide store. The chain we use needs to be the chain of the
11595 // latest store node which is *used* and replaced by the wide store.
11596 if (StoreNodes[i].SequenceNum < StoreNodes[LatestNodeUsed].SequenceNum)
11597 LatestNodeUsed = i;
11599 MergeStoreChains.push_back(StoreNodes[i].MemNode->getChain());
11602 LSBaseSDNode *LatestOp = StoreNodes[LatestNodeUsed].MemNode;
11604 // Find if it is better to use vectors or integers to load and store
11608 JointMemOpVT = EVT::getVectorVT(Context, MemVT, NumElem);
11610 unsigned SizeInBits = NumElem * ElementSizeBytes * 8;
11611 JointMemOpVT = EVT::getIntegerVT(Context, SizeInBits);
11614 SDLoc LoadDL(LoadNodes[0].MemNode);
11615 SDLoc StoreDL(StoreNodes[0].MemNode);
11617 // The merged loads are required to have the same incoming chain, so
11618 // using the first's chain is acceptable.
11619 SDValue NewLoad = DAG.getLoad(
11620 JointMemOpVT, LoadDL, FirstLoad->getChain(), FirstLoad->getBasePtr(),
11621 FirstLoad->getPointerInfo(), false, false, false, FirstLoadAlign);
11623 SDValue NewStoreChain =
11624 DAG.getNode(ISD::TokenFactor, StoreDL, MVT::Other, MergeStoreChains);
11626 SDValue NewStore = DAG.getStore(
11627 NewStoreChain, StoreDL, NewLoad, FirstInChain->getBasePtr(),
11628 FirstInChain->getPointerInfo(), false, false, FirstStoreAlign);
11630 // Transfer chain users from old loads to the new load.
11631 for (unsigned i = 0; i < NumElem; ++i) {
11632 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode);
11633 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1),
11634 SDValue(NewLoad.getNode(), 1));
11637 // Replace the last store with the new store.
11638 CombineTo(LatestOp, NewStore);
11639 // Erase all other stores.
11640 for (unsigned i = 0; i < NumElem ; ++i) {
11641 // Remove all Store nodes.
11642 if (StoreNodes[i].MemNode == LatestOp)
11644 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
11645 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
11646 deleteAndRecombine(St);
11652 SDValue DAGCombiner::replaceStoreChain(StoreSDNode *ST, SDValue BetterChain) {
11656 // Replace the chain to avoid dependency.
11657 if (ST->isTruncatingStore()) {
11658 ReplStore = DAG.getTruncStore(BetterChain, SL, ST->getValue(),
11659 ST->getBasePtr(), ST->getMemoryVT(),
11660 ST->getMemOperand());
11662 ReplStore = DAG.getStore(BetterChain, SL, ST->getValue(), ST->getBasePtr(),
11663 ST->getMemOperand());
11666 // Create token to keep both nodes around.
11667 SDValue Token = DAG.getNode(ISD::TokenFactor, SL,
11668 MVT::Other, ST->getChain(), ReplStore);
11670 // Make sure the new and old chains are cleaned up.
11671 AddToWorklist(Token.getNode());
11673 // Don't add users to work list.
11674 return CombineTo(ST, Token, false);
11677 SDValue DAGCombiner::replaceStoreOfFPConstant(StoreSDNode *ST) {
11678 SDValue Value = ST->getValue();
11679 if (Value.getOpcode() == ISD::TargetConstantFP)
11684 SDValue Chain = ST->getChain();
11685 SDValue Ptr = ST->getBasePtr();
11687 const ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Value);
11689 // NOTE: If the original store is volatile, this transform must not increase
11690 // the number of stores. For example, on x86-32 an f64 can be stored in one
11691 // processor operation but an i64 (which is not legal) requires two. So the
11692 // transform should not be done in this case.
11695 switch (CFP->getSimpleValueType(0).SimpleTy) {
11697 llvm_unreachable("Unknown FP type");
11698 case MVT::f16: // We don't do this for these yet.
11704 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
11705 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
11707 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
11708 bitcastToAPInt().getZExtValue(), SDLoc(CFP),
11710 return DAG.getStore(Chain, DL, Tmp, Ptr, ST->getMemOperand());
11715 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
11716 !ST->isVolatile()) ||
11717 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
11719 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
11720 getZExtValue(), SDLoc(CFP), MVT::i64);
11721 return DAG.getStore(Chain, DL, Tmp,
11722 Ptr, ST->getMemOperand());
11725 if (!ST->isVolatile() &&
11726 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
11727 // Many FP stores are not made apparent until after legalize, e.g. for
11728 // argument passing. Since this is so common, custom legalize the
11729 // 64-bit integer store into two 32-bit stores.
11730 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
11731 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, SDLoc(CFP), MVT::i32);
11732 SDValue Hi = DAG.getConstant(Val >> 32, SDLoc(CFP), MVT::i32);
11733 if (DAG.getDataLayout().isBigEndian())
11736 unsigned Alignment = ST->getAlignment();
11737 bool isVolatile = ST->isVolatile();
11738 bool isNonTemporal = ST->isNonTemporal();
11739 AAMDNodes AAInfo = ST->getAAInfo();
11741 SDValue St0 = DAG.getStore(Chain, DL, Lo,
11742 Ptr, ST->getPointerInfo(),
11743 isVolatile, isNonTemporal,
11744 ST->getAlignment(), AAInfo);
11745 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
11746 DAG.getConstant(4, DL, Ptr.getValueType()));
11747 Alignment = MinAlign(Alignment, 4U);
11748 SDValue St1 = DAG.getStore(Chain, DL, Hi,
11749 Ptr, ST->getPointerInfo().getWithOffset(4),
11750 isVolatile, isNonTemporal,
11751 Alignment, AAInfo);
11752 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
11760 SDValue DAGCombiner::visitSTORE(SDNode *N) {
11761 StoreSDNode *ST = cast<StoreSDNode>(N);
11762 SDValue Chain = ST->getChain();
11763 SDValue Value = ST->getValue();
11764 SDValue Ptr = ST->getBasePtr();
11766 // If this is a store of a bit convert, store the input value if the
11767 // resultant store does not need a higher alignment than the original.
11768 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
11769 ST->isUnindexed()) {
11770 unsigned OrigAlign = ST->getAlignment();
11771 EVT SVT = Value.getOperand(0).getValueType();
11772 unsigned Align = DAG.getDataLayout().getABITypeAlignment(
11773 SVT.getTypeForEVT(*DAG.getContext()));
11774 if (Align <= OrigAlign &&
11775 ((!LegalOperations && !ST->isVolatile()) ||
11776 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
11777 return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0),
11778 Ptr, ST->getPointerInfo(), ST->isVolatile(),
11779 ST->isNonTemporal(), OrigAlign,
11783 // Turn 'store undef, Ptr' -> nothing.
11784 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
11787 // Try to infer better alignment information than the store already has.
11788 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
11789 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
11790 if (Align > ST->getAlignment()) {
11792 DAG.getTruncStore(Chain, SDLoc(N), Value,
11793 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
11794 ST->isVolatile(), ST->isNonTemporal(), Align,
11796 if (NewStore.getNode() != N)
11797 return CombineTo(ST, NewStore, true);
11802 // Try transforming a pair floating point load / store ops to integer
11803 // load / store ops.
11804 if (SDValue NewST = TransformFPLoadStorePair(N))
11807 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
11808 : DAG.getSubtarget().useAA();
11810 if (CombinerAAOnlyFunc.getNumOccurrences() &&
11811 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
11814 if (UseAA && ST->isUnindexed()) {
11815 // FIXME: We should do this even without AA enabled. AA will just allow
11816 // FindBetterChain to work in more situations. The problem with this is that
11817 // any combine that expects memory operations to be on consecutive chains
11818 // first needs to be updated to look for users of the same chain.
11820 // Walk up chain skipping non-aliasing memory nodes, on this store and any
11821 // adjacent stores.
11822 if (findBetterNeighborChains(ST)) {
11823 // replaceStoreChain uses CombineTo, which handled all of the worklist
11824 // manipulation. Return the original node to not do anything else.
11825 return SDValue(ST, 0);
11829 // Try transforming N to an indexed store.
11830 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
11831 return SDValue(N, 0);
11833 // FIXME: is there such a thing as a truncating indexed store?
11834 if (ST->isTruncatingStore() && ST->isUnindexed() &&
11835 Value.getValueType().isInteger()) {
11836 // See if we can simplify the input to this truncstore with knowledge that
11837 // only the low bits are being used. For example:
11838 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
11840 GetDemandedBits(Value,
11841 APInt::getLowBitsSet(
11842 Value.getValueType().getScalarType().getSizeInBits(),
11843 ST->getMemoryVT().getScalarType().getSizeInBits()));
11844 AddToWorklist(Value.getNode());
11845 if (Shorter.getNode())
11846 return DAG.getTruncStore(Chain, SDLoc(N), Shorter,
11847 Ptr, ST->getMemoryVT(), ST->getMemOperand());
11849 // Otherwise, see if we can simplify the operation with
11850 // SimplifyDemandedBits, which only works if the value has a single use.
11851 if (SimplifyDemandedBits(Value,
11852 APInt::getLowBitsSet(
11853 Value.getValueType().getScalarType().getSizeInBits(),
11854 ST->getMemoryVT().getScalarType().getSizeInBits())))
11855 return SDValue(N, 0);
11858 // If this is a load followed by a store to the same location, then the store
11860 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
11861 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
11862 ST->isUnindexed() && !ST->isVolatile() &&
11863 // There can't be any side effects between the load and store, such as
11864 // a call or store.
11865 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
11866 // The store is dead, remove it.
11871 // If this is a store followed by a store with the same value to the same
11872 // location, then the store is dead/noop.
11873 if (StoreSDNode *ST1 = dyn_cast<StoreSDNode>(Chain)) {
11874 if (ST1->getBasePtr() == Ptr && ST->getMemoryVT() == ST1->getMemoryVT() &&
11875 ST1->getValue() == Value && ST->isUnindexed() && !ST->isVolatile() &&
11876 ST1->isUnindexed() && !ST1->isVolatile()) {
11877 // The store is dead, remove it.
11882 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
11883 // truncating store. We can do this even if this is already a truncstore.
11884 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
11885 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
11886 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
11887 ST->getMemoryVT())) {
11888 return DAG.getTruncStore(Chain, SDLoc(N), Value.getOperand(0),
11889 Ptr, ST->getMemoryVT(), ST->getMemOperand());
11892 // Only perform this optimization before the types are legal, because we
11893 // don't want to perform this optimization on every DAGCombine invocation.
11895 bool EverChanged = false;
11898 // There can be multiple store sequences on the same chain.
11899 // Keep trying to merge store sequences until we are unable to do so
11900 // or until we merge the last store on the chain.
11901 bool Changed = MergeConsecutiveStores(ST);
11902 EverChanged |= Changed;
11903 if (!Changed) break;
11904 } while (ST->getOpcode() != ISD::DELETED_NODE);
11907 return SDValue(N, 0);
11910 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
11912 // Make sure to do this only after attempting to merge stores in order to
11913 // avoid changing the types of some subset of stores due to visit order,
11914 // preventing their merging.
11915 if (isa<ConstantFPSDNode>(Value)) {
11916 if (SDValue NewSt = replaceStoreOfFPConstant(ST))
11920 return ReduceLoadOpStoreWidth(N);
11923 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
11924 SDValue InVec = N->getOperand(0);
11925 SDValue InVal = N->getOperand(1);
11926 SDValue EltNo = N->getOperand(2);
11929 // If the inserted element is an UNDEF, just use the input vector.
11930 if (InVal.getOpcode() == ISD::UNDEF)
11933 EVT VT = InVec.getValueType();
11935 // If we can't generate a legal BUILD_VECTOR, exit
11936 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
11939 // Check that we know which element is being inserted
11940 if (!isa<ConstantSDNode>(EltNo))
11942 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
11944 // Canonicalize insert_vector_elt dag nodes.
11946 // (insert_vector_elt (insert_vector_elt A, Idx0), Idx1)
11947 // -> (insert_vector_elt (insert_vector_elt A, Idx1), Idx0)
11949 // Do this only if the child insert_vector node has one use; also
11950 // do this only if indices are both constants and Idx1 < Idx0.
11951 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse()
11952 && isa<ConstantSDNode>(InVec.getOperand(2))) {
11953 unsigned OtherElt =
11954 cast<ConstantSDNode>(InVec.getOperand(2))->getZExtValue();
11955 if (Elt < OtherElt) {
11957 SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VT,
11958 InVec.getOperand(0), InVal, EltNo);
11959 AddToWorklist(NewOp.getNode());
11960 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()),
11961 VT, NewOp, InVec.getOperand(1), InVec.getOperand(2));
11965 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
11966 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
11967 // vector elements.
11968 SmallVector<SDValue, 8> Ops;
11969 // Do not combine these two vectors if the output vector will not replace
11970 // the input vector.
11971 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) {
11972 Ops.append(InVec.getNode()->op_begin(),
11973 InVec.getNode()->op_end());
11974 } else if (InVec.getOpcode() == ISD::UNDEF) {
11975 unsigned NElts = VT.getVectorNumElements();
11976 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
11981 // Insert the element
11982 if (Elt < Ops.size()) {
11983 // All the operands of BUILD_VECTOR must have the same type;
11984 // we enforce that here.
11985 EVT OpVT = Ops[0].getValueType();
11986 if (InVal.getValueType() != OpVT)
11987 InVal = OpVT.bitsGT(InVal.getValueType()) ?
11988 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
11989 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
11993 // Return the new vector
11994 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
11997 SDValue DAGCombiner::ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
11998 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad) {
11999 EVT ResultVT = EVE->getValueType(0);
12000 EVT VecEltVT = InVecVT.getVectorElementType();
12001 unsigned Align = OriginalLoad->getAlignment();
12002 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
12003 VecEltVT.getTypeForEVT(*DAG.getContext()));
12005 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VecEltVT))
12010 SDValue NewPtr = OriginalLoad->getBasePtr();
12012 EVT PtrType = NewPtr.getValueType();
12013 MachinePointerInfo MPI;
12015 if (auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo)) {
12016 int Elt = ConstEltNo->getZExtValue();
12017 unsigned PtrOff = VecEltVT.getSizeInBits() * Elt / 8;
12018 Offset = DAG.getConstant(PtrOff, DL, PtrType);
12019 MPI = OriginalLoad->getPointerInfo().getWithOffset(PtrOff);
12021 Offset = DAG.getZExtOrTrunc(EltNo, DL, PtrType);
12022 Offset = DAG.getNode(
12023 ISD::MUL, DL, PtrType, Offset,
12024 DAG.getConstant(VecEltVT.getStoreSize(), DL, PtrType));
12025 MPI = OriginalLoad->getPointerInfo();
12027 NewPtr = DAG.getNode(ISD::ADD, DL, PtrType, NewPtr, Offset);
12029 // The replacement we need to do here is a little tricky: we need to
12030 // replace an extractelement of a load with a load.
12031 // Use ReplaceAllUsesOfValuesWith to do the replacement.
12032 // Note that this replacement assumes that the extractvalue is the only
12033 // use of the load; that's okay because we don't want to perform this
12034 // transformation in other cases anyway.
12037 if (ResultVT.bitsGT(VecEltVT)) {
12038 // If the result type of vextract is wider than the load, then issue an
12039 // extending load instead.
12040 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, ResultVT,
12044 Load = DAG.getExtLoad(
12045 ExtType, SDLoc(EVE), ResultVT, OriginalLoad->getChain(), NewPtr, MPI,
12046 VecEltVT, OriginalLoad->isVolatile(), OriginalLoad->isNonTemporal(),
12047 OriginalLoad->isInvariant(), Align, OriginalLoad->getAAInfo());
12048 Chain = Load.getValue(1);
12050 Load = DAG.getLoad(
12051 VecEltVT, SDLoc(EVE), OriginalLoad->getChain(), NewPtr, MPI,
12052 OriginalLoad->isVolatile(), OriginalLoad->isNonTemporal(),
12053 OriginalLoad->isInvariant(), Align, OriginalLoad->getAAInfo());
12054 Chain = Load.getValue(1);
12055 if (ResultVT.bitsLT(VecEltVT))
12056 Load = DAG.getNode(ISD::TRUNCATE, SDLoc(EVE), ResultVT, Load);
12058 Load = DAG.getNode(ISD::BITCAST, SDLoc(EVE), ResultVT, Load);
12060 WorklistRemover DeadNodes(*this);
12061 SDValue From[] = { SDValue(EVE, 0), SDValue(OriginalLoad, 1) };
12062 SDValue To[] = { Load, Chain };
12063 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
12064 // Since we're explicitly calling ReplaceAllUses, add the new node to the
12065 // worklist explicitly as well.
12066 AddToWorklist(Load.getNode());
12067 AddUsersToWorklist(Load.getNode()); // Add users too
12068 // Make sure to revisit this node to clean it up; it will usually be dead.
12069 AddToWorklist(EVE);
12071 return SDValue(EVE, 0);
12074 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
12075 // (vextract (scalar_to_vector val, 0) -> val
12076 SDValue InVec = N->getOperand(0);
12077 EVT VT = InVec.getValueType();
12078 EVT NVT = N->getValueType(0);
12080 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
12081 // Check if the result type doesn't match the inserted element type. A
12082 // SCALAR_TO_VECTOR may truncate the inserted element and the
12083 // EXTRACT_VECTOR_ELT may widen the extracted vector.
12084 SDValue InOp = InVec.getOperand(0);
12085 if (InOp.getValueType() != NVT) {
12086 assert(InOp.getValueType().isInteger() && NVT.isInteger());
12087 return DAG.getSExtOrTrunc(InOp, SDLoc(InVec), NVT);
12092 SDValue EltNo = N->getOperand(1);
12093 ConstantSDNode *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo);
12095 // extract_vector_elt (build_vector x, y), 1 -> y
12097 InVec.getOpcode() == ISD::BUILD_VECTOR &&
12098 TLI.isTypeLegal(VT) &&
12099 (InVec.hasOneUse() ||
12100 TLI.aggressivelyPreferBuildVectorSources(VT))) {
12101 SDValue Elt = InVec.getOperand(ConstEltNo->getZExtValue());
12102 EVT InEltVT = Elt.getValueType();
12104 // Sometimes build_vector's scalar input types do not match result type.
12105 if (NVT == InEltVT)
12108 // TODO: It may be useful to truncate if free if the build_vector implicitly
12112 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
12113 // We only perform this optimization before the op legalization phase because
12114 // we may introduce new vector instructions which are not backed by TD
12115 // patterns. For example on AVX, extracting elements from a wide vector
12116 // without using extract_subvector. However, if we can find an underlying
12117 // scalar value, then we can always use that.
12118 if (ConstEltNo && InVec.getOpcode() == ISD::VECTOR_SHUFFLE) {
12119 int NumElem = VT.getVectorNumElements();
12120 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
12121 // Find the new index to extract from.
12122 int OrigElt = SVOp->getMaskElt(ConstEltNo->getZExtValue());
12124 // Extracting an undef index is undef.
12126 return DAG.getUNDEF(NVT);
12128 // Select the right vector half to extract from.
12130 if (OrigElt < NumElem) {
12131 SVInVec = InVec->getOperand(0);
12133 SVInVec = InVec->getOperand(1);
12134 OrigElt -= NumElem;
12137 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) {
12138 SDValue InOp = SVInVec.getOperand(OrigElt);
12139 if (InOp.getValueType() != NVT) {
12140 assert(InOp.getValueType().isInteger() && NVT.isInteger());
12141 InOp = DAG.getSExtOrTrunc(InOp, SDLoc(SVInVec), NVT);
12147 // FIXME: We should handle recursing on other vector shuffles and
12148 // scalar_to_vector here as well.
12150 if (!LegalOperations) {
12151 EVT IndexTy = TLI.getVectorIdxTy(DAG.getDataLayout());
12152 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), NVT, SVInVec,
12153 DAG.getConstant(OrigElt, SDLoc(SVOp), IndexTy));
12157 bool BCNumEltsChanged = false;
12158 EVT ExtVT = VT.getVectorElementType();
12161 // If the result of load has to be truncated, then it's not necessarily
12163 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
12166 if (InVec.getOpcode() == ISD::BITCAST) {
12167 // Don't duplicate a load with other uses.
12168 if (!InVec.hasOneUse())
12171 EVT BCVT = InVec.getOperand(0).getValueType();
12172 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
12174 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
12175 BCNumEltsChanged = true;
12176 InVec = InVec.getOperand(0);
12177 ExtVT = BCVT.getVectorElementType();
12180 // (vextract (vN[if]M load $addr), i) -> ([if]M load $addr + i * size)
12181 if (!LegalOperations && !ConstEltNo && InVec.hasOneUse() &&
12182 ISD::isNormalLoad(InVec.getNode()) &&
12183 !N->getOperand(1)->hasPredecessor(InVec.getNode())) {
12184 SDValue Index = N->getOperand(1);
12185 if (LoadSDNode *OrigLoad = dyn_cast<LoadSDNode>(InVec))
12186 return ReplaceExtractVectorEltOfLoadWithNarrowedLoad(N, VT, Index,
12190 // Perform only after legalization to ensure build_vector / vector_shuffle
12191 // optimizations have already been done.
12192 if (!LegalOperations) return SDValue();
12194 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
12195 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
12196 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
12199 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
12201 LoadSDNode *LN0 = nullptr;
12202 const ShuffleVectorSDNode *SVN = nullptr;
12203 if (ISD::isNormalLoad(InVec.getNode())) {
12204 LN0 = cast<LoadSDNode>(InVec);
12205 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
12206 InVec.getOperand(0).getValueType() == ExtVT &&
12207 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
12208 // Don't duplicate a load with other uses.
12209 if (!InVec.hasOneUse())
12212 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
12213 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
12214 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
12216 // (load $addr+1*size)
12218 // Don't duplicate a load with other uses.
12219 if (!InVec.hasOneUse())
12222 // If the bit convert changed the number of elements, it is unsafe
12223 // to examine the mask.
12224 if (BCNumEltsChanged)
12227 // Select the input vector, guarding against out of range extract vector.
12228 unsigned NumElems = VT.getVectorNumElements();
12229 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
12230 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
12232 if (InVec.getOpcode() == ISD::BITCAST) {
12233 // Don't duplicate a load with other uses.
12234 if (!InVec.hasOneUse())
12237 InVec = InVec.getOperand(0);
12239 if (ISD::isNormalLoad(InVec.getNode())) {
12240 LN0 = cast<LoadSDNode>(InVec);
12241 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
12242 EltNo = DAG.getConstant(Elt, SDLoc(EltNo), EltNo.getValueType());
12246 // Make sure we found a non-volatile load and the extractelement is
12248 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
12251 // If Idx was -1 above, Elt is going to be -1, so just return undef.
12253 return DAG.getUNDEF(LVT);
12255 return ReplaceExtractVectorEltOfLoadWithNarrowedLoad(N, VT, EltNo, LN0);
12261 // Simplify (build_vec (ext )) to (bitcast (build_vec ))
12262 SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) {
12263 // We perform this optimization post type-legalization because
12264 // the type-legalizer often scalarizes integer-promoted vectors.
12265 // Performing this optimization before may create bit-casts which
12266 // will be type-legalized to complex code sequences.
12267 // We perform this optimization only before the operation legalizer because we
12268 // may introduce illegal operations.
12269 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes)
12272 unsigned NumInScalars = N->getNumOperands();
12274 EVT VT = N->getValueType(0);
12276 // Check to see if this is a BUILD_VECTOR of a bunch of values
12277 // which come from any_extend or zero_extend nodes. If so, we can create
12278 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
12279 // optimizations. We do not handle sign-extend because we can't fill the sign
12281 EVT SourceType = MVT::Other;
12282 bool AllAnyExt = true;
12284 for (unsigned i = 0; i != NumInScalars; ++i) {
12285 SDValue In = N->getOperand(i);
12286 // Ignore undef inputs.
12287 if (In.getOpcode() == ISD::UNDEF) continue;
12289 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
12290 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
12292 // Abort if the element is not an extension.
12293 if (!ZeroExt && !AnyExt) {
12294 SourceType = MVT::Other;
12298 // The input is a ZeroExt or AnyExt. Check the original type.
12299 EVT InTy = In.getOperand(0).getValueType();
12301 // Check that all of the widened source types are the same.
12302 if (SourceType == MVT::Other)
12305 else if (InTy != SourceType) {
12306 // Multiple income types. Abort.
12307 SourceType = MVT::Other;
12311 // Check if all of the extends are ANY_EXTENDs.
12312 AllAnyExt &= AnyExt;
12315 // In order to have valid types, all of the inputs must be extended from the
12316 // same source type and all of the inputs must be any or zero extend.
12317 // Scalar sizes must be a power of two.
12318 EVT OutScalarTy = VT.getScalarType();
12319 bool ValidTypes = SourceType != MVT::Other &&
12320 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
12321 isPowerOf2_32(SourceType.getSizeInBits());
12323 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
12324 // turn into a single shuffle instruction.
12328 bool isLE = DAG.getDataLayout().isLittleEndian();
12329 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
12330 assert(ElemRatio > 1 && "Invalid element size ratio");
12331 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
12332 DAG.getConstant(0, SDLoc(N), SourceType);
12334 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements();
12335 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
12337 // Populate the new build_vector
12338 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
12339 SDValue Cast = N->getOperand(i);
12340 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
12341 Cast.getOpcode() == ISD::ZERO_EXTEND ||
12342 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
12344 if (Cast.getOpcode() == ISD::UNDEF)
12345 In = DAG.getUNDEF(SourceType);
12347 In = Cast->getOperand(0);
12348 unsigned Index = isLE ? (i * ElemRatio) :
12349 (i * ElemRatio + (ElemRatio - 1));
12351 assert(Index < Ops.size() && "Invalid index");
12355 // The type of the new BUILD_VECTOR node.
12356 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
12357 assert(VecVT.getSizeInBits() == VT.getSizeInBits() &&
12358 "Invalid vector size");
12359 // Check if the new vector type is legal.
12360 if (!isTypeLegal(VecVT)) return SDValue();
12362 // Make the new BUILD_VECTOR.
12363 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
12365 // The new BUILD_VECTOR node has the potential to be further optimized.
12366 AddToWorklist(BV.getNode());
12367 // Bitcast to the desired type.
12368 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
12371 SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
12372 EVT VT = N->getValueType(0);
12374 unsigned NumInScalars = N->getNumOperands();
12377 EVT SrcVT = MVT::Other;
12378 unsigned Opcode = ISD::DELETED_NODE;
12379 unsigned NumDefs = 0;
12381 for (unsigned i = 0; i != NumInScalars; ++i) {
12382 SDValue In = N->getOperand(i);
12383 unsigned Opc = In.getOpcode();
12385 if (Opc == ISD::UNDEF)
12388 // If all scalar values are floats and converted from integers.
12389 if (Opcode == ISD::DELETED_NODE &&
12390 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
12397 EVT InVT = In.getOperand(0).getValueType();
12399 // If all scalar values are typed differently, bail out. It's chosen to
12400 // simplify BUILD_VECTOR of integer types.
12401 if (SrcVT == MVT::Other)
12408 // If the vector has just one element defined, it's not worth to fold it into
12409 // a vectorized one.
12413 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP)
12414 && "Should only handle conversion from integer to float.");
12415 assert(SrcVT != MVT::Other && "Cannot determine source type!");
12417 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
12419 if (!TLI.isOperationLegalOrCustom(Opcode, NVT))
12422 // Just because the floating-point vector type is legal does not necessarily
12423 // mean that the corresponding integer vector type is.
12424 if (!isTypeLegal(NVT))
12427 SmallVector<SDValue, 8> Opnds;
12428 for (unsigned i = 0; i != NumInScalars; ++i) {
12429 SDValue In = N->getOperand(i);
12431 if (In.getOpcode() == ISD::UNDEF)
12432 Opnds.push_back(DAG.getUNDEF(SrcVT));
12434 Opnds.push_back(In.getOperand(0));
12436 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Opnds);
12437 AddToWorklist(BV.getNode());
12439 return DAG.getNode(Opcode, dl, VT, BV);
12442 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
12443 unsigned NumInScalars = N->getNumOperands();
12445 EVT VT = N->getValueType(0);
12447 // A vector built entirely of undefs is undef.
12448 if (ISD::allOperandsUndef(N))
12449 return DAG.getUNDEF(VT);
12451 if (SDValue V = reduceBuildVecExtToExtBuildVec(N))
12454 if (SDValue V = reduceBuildVecConvertToConvertBuildVec(N))
12457 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
12458 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
12459 // at most two distinct vectors, turn this into a shuffle node.
12461 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
12462 if (!isTypeLegal(VT))
12465 // May only combine to shuffle after legalize if shuffle is legal.
12466 if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VT))
12469 SDValue VecIn1, VecIn2;
12470 bool UsesZeroVector = false;
12471 for (unsigned i = 0; i != NumInScalars; ++i) {
12472 SDValue Op = N->getOperand(i);
12473 // Ignore undef inputs.
12474 if (Op.getOpcode() == ISD::UNDEF) continue;
12476 // See if we can combine this build_vector into a blend with a zero vector.
12477 if (!VecIn2.getNode() && (isNullConstant(Op) || isNullFPConstant(Op))) {
12478 UsesZeroVector = true;
12482 // If this input is something other than a EXTRACT_VECTOR_ELT with a
12483 // constant index, bail out.
12484 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
12485 !isa<ConstantSDNode>(Op.getOperand(1))) {
12486 VecIn1 = VecIn2 = SDValue(nullptr, 0);
12490 // We allow up to two distinct input vectors.
12491 SDValue ExtractedFromVec = Op.getOperand(0);
12492 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
12495 if (!VecIn1.getNode()) {
12496 VecIn1 = ExtractedFromVec;
12497 } else if (!VecIn2.getNode() && !UsesZeroVector) {
12498 VecIn2 = ExtractedFromVec;
12500 // Too many inputs.
12501 VecIn1 = VecIn2 = SDValue(nullptr, 0);
12506 // If everything is good, we can make a shuffle operation.
12507 if (VecIn1.getNode()) {
12508 unsigned InNumElements = VecIn1.getValueType().getVectorNumElements();
12509 SmallVector<int, 8> Mask;
12510 for (unsigned i = 0; i != NumInScalars; ++i) {
12511 unsigned Opcode = N->getOperand(i).getOpcode();
12512 if (Opcode == ISD::UNDEF) {
12513 Mask.push_back(-1);
12517 // Operands can also be zero.
12518 if (Opcode != ISD::EXTRACT_VECTOR_ELT) {
12519 assert(UsesZeroVector &&
12520 (Opcode == ISD::Constant || Opcode == ISD::ConstantFP) &&
12521 "Unexpected node found!");
12522 Mask.push_back(NumInScalars+i);
12526 // If extracting from the first vector, just use the index directly.
12527 SDValue Extract = N->getOperand(i);
12528 SDValue ExtVal = Extract.getOperand(1);
12529 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
12530 if (Extract.getOperand(0) == VecIn1) {
12531 Mask.push_back(ExtIndex);
12535 // Otherwise, use InIdx + InputVecSize
12536 Mask.push_back(InNumElements + ExtIndex);
12539 // Avoid introducing illegal shuffles with zero.
12540 if (UsesZeroVector && !TLI.isVectorClearMaskLegal(Mask, VT))
12543 // We can't generate a shuffle node with mismatched input and output types.
12544 // Attempt to transform a single input vector to the correct type.
12545 if ((VT != VecIn1.getValueType())) {
12546 // If the input vector type has a different base type to the output
12547 // vector type, bail out.
12548 EVT VTElemType = VT.getVectorElementType();
12549 if ((VecIn1.getValueType().getVectorElementType() != VTElemType) ||
12550 (VecIn2.getNode() &&
12551 (VecIn2.getValueType().getVectorElementType() != VTElemType)))
12554 // If the input vector is too small, widen it.
12555 // We only support widening of vectors which are half the size of the
12556 // output registers. For example XMM->YMM widening on X86 with AVX.
12557 EVT VecInT = VecIn1.getValueType();
12558 if (VecInT.getSizeInBits() * 2 == VT.getSizeInBits()) {
12559 // If we only have one small input, widen it by adding undef values.
12560 if (!VecIn2.getNode())
12561 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, VecIn1,
12562 DAG.getUNDEF(VecIn1.getValueType()));
12563 else if (VecIn1.getValueType() == VecIn2.getValueType()) {
12564 // If we have two small inputs of the same type, try to concat them.
12565 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, VecIn1, VecIn2);
12566 VecIn2 = SDValue(nullptr, 0);
12569 } else if (VecInT.getSizeInBits() == VT.getSizeInBits() * 2) {
12570 // If the input vector is too large, try to split it.
12571 // We don't support having two input vectors that are too large.
12572 // If the zero vector was used, we can not split the vector,
12573 // since we'd need 3 inputs.
12574 if (UsesZeroVector || VecIn2.getNode())
12577 if (!TLI.isExtractSubvectorCheap(VT, VT.getVectorNumElements()))
12580 // Try to replace VecIn1 with two extract_subvectors
12581 // No need to update the masks, they should still be correct.
12582 VecIn2 = DAG.getNode(
12583 ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1,
12584 DAG.getConstant(VT.getVectorNumElements(), dl,
12585 TLI.getVectorIdxTy(DAG.getDataLayout())));
12586 VecIn1 = DAG.getNode(
12587 ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1,
12588 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
12593 if (UsesZeroVector)
12594 VecIn2 = VT.isInteger() ? DAG.getConstant(0, dl, VT) :
12595 DAG.getConstantFP(0.0, dl, VT);
12597 // If VecIn2 is unused then change it to undef.
12598 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
12600 // Check that we were able to transform all incoming values to the same
12602 if (VecIn2.getValueType() != VecIn1.getValueType() ||
12603 VecIn1.getValueType() != VT)
12606 // Return the new VECTOR_SHUFFLE node.
12610 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]);
12616 static SDValue combineConcatVectorOfScalars(SDNode *N, SelectionDAG &DAG) {
12617 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12618 EVT OpVT = N->getOperand(0).getValueType();
12620 // If the operands are legal vectors, leave them alone.
12621 if (TLI.isTypeLegal(OpVT))
12625 EVT VT = N->getValueType(0);
12626 SmallVector<SDValue, 8> Ops;
12628 EVT SVT = EVT::getIntegerVT(*DAG.getContext(), OpVT.getSizeInBits());
12629 SDValue ScalarUndef = DAG.getNode(ISD::UNDEF, DL, SVT);
12631 // Keep track of what we encounter.
12632 bool AnyInteger = false;
12633 bool AnyFP = false;
12634 for (const SDValue &Op : N->ops()) {
12635 if (ISD::BITCAST == Op.getOpcode() &&
12636 !Op.getOperand(0).getValueType().isVector())
12637 Ops.push_back(Op.getOperand(0));
12638 else if (ISD::UNDEF == Op.getOpcode())
12639 Ops.push_back(ScalarUndef);
12643 // Note whether we encounter an integer or floating point scalar.
12644 // If it's neither, bail out, it could be something weird like x86mmx.
12645 EVT LastOpVT = Ops.back().getValueType();
12646 if (LastOpVT.isFloatingPoint())
12648 else if (LastOpVT.isInteger())
12654 // If any of the operands is a floating point scalar bitcast to a vector,
12655 // use floating point types throughout, and bitcast everything.
12656 // Replace UNDEFs by another scalar UNDEF node, of the final desired type.
12658 SVT = EVT::getFloatingPointVT(OpVT.getSizeInBits());
12659 ScalarUndef = DAG.getNode(ISD::UNDEF, DL, SVT);
12661 for (SDValue &Op : Ops) {
12662 if (Op.getValueType() == SVT)
12664 if (Op.getOpcode() == ISD::UNDEF)
12667 Op = DAG.getNode(ISD::BITCAST, DL, SVT, Op);
12672 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SVT,
12673 VT.getSizeInBits() / SVT.getSizeInBits());
12674 return DAG.getNode(ISD::BITCAST, DL, VT,
12675 DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, Ops));
12678 // Check to see if this is a CONCAT_VECTORS of a bunch of EXTRACT_SUBVECTOR
12679 // operations. If so, and if the EXTRACT_SUBVECTOR vector inputs come from at
12680 // most two distinct vectors the same size as the result, attempt to turn this
12681 // into a legal shuffle.
12682 static SDValue combineConcatVectorOfExtracts(SDNode *N, SelectionDAG &DAG) {
12683 EVT VT = N->getValueType(0);
12684 EVT OpVT = N->getOperand(0).getValueType();
12685 int NumElts = VT.getVectorNumElements();
12686 int NumOpElts = OpVT.getVectorNumElements();
12688 SDValue SV0 = DAG.getUNDEF(VT), SV1 = DAG.getUNDEF(VT);
12689 SmallVector<int, 8> Mask;
12691 for (SDValue Op : N->ops()) {
12692 // Peek through any bitcast.
12693 while (Op.getOpcode() == ISD::BITCAST)
12694 Op = Op.getOperand(0);
12696 // UNDEF nodes convert to UNDEF shuffle mask values.
12697 if (Op.getOpcode() == ISD::UNDEF) {
12698 Mask.append((unsigned)NumOpElts, -1);
12702 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
12705 // What vector are we extracting the subvector from and at what index?
12706 SDValue ExtVec = Op.getOperand(0);
12708 // We want the EVT of the original extraction to correctly scale the
12709 // extraction index.
12710 EVT ExtVT = ExtVec.getValueType();
12712 // Peek through any bitcast.
12713 while (ExtVec.getOpcode() == ISD::BITCAST)
12714 ExtVec = ExtVec.getOperand(0);
12716 // UNDEF nodes convert to UNDEF shuffle mask values.
12717 if (ExtVec.getOpcode() == ISD::UNDEF) {
12718 Mask.append((unsigned)NumOpElts, -1);
12722 if (!isa<ConstantSDNode>(Op.getOperand(1)))
12724 int ExtIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12726 // Ensure that we are extracting a subvector from a vector the same
12727 // size as the result.
12728 if (ExtVT.getSizeInBits() != VT.getSizeInBits())
12731 // Scale the subvector index to account for any bitcast.
12732 int NumExtElts = ExtVT.getVectorNumElements();
12733 if (0 == (NumExtElts % NumElts))
12734 ExtIdx /= (NumExtElts / NumElts);
12735 else if (0 == (NumElts % NumExtElts))
12736 ExtIdx *= (NumElts / NumExtElts);
12740 // At most we can reference 2 inputs in the final shuffle.
12741 if (SV0.getOpcode() == ISD::UNDEF || SV0 == ExtVec) {
12743 for (int i = 0; i != NumOpElts; ++i)
12744 Mask.push_back(i + ExtIdx);
12745 } else if (SV1.getOpcode() == ISD::UNDEF || SV1 == ExtVec) {
12747 for (int i = 0; i != NumOpElts; ++i)
12748 Mask.push_back(i + ExtIdx + NumElts);
12754 if (!DAG.getTargetLoweringInfo().isShuffleMaskLegal(Mask, VT))
12757 return DAG.getVectorShuffle(VT, SDLoc(N), DAG.getBitcast(VT, SV0),
12758 DAG.getBitcast(VT, SV1), Mask);
12761 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
12762 // If we only have one input vector, we don't need to do any concatenation.
12763 if (N->getNumOperands() == 1)
12764 return N->getOperand(0);
12766 // Check if all of the operands are undefs.
12767 EVT VT = N->getValueType(0);
12768 if (ISD::allOperandsUndef(N))
12769 return DAG.getUNDEF(VT);
12771 // Optimize concat_vectors where all but the first of the vectors are undef.
12772 if (std::all_of(std::next(N->op_begin()), N->op_end(), [](const SDValue &Op) {
12773 return Op.getOpcode() == ISD::UNDEF;
12775 SDValue In = N->getOperand(0);
12776 assert(In.getValueType().isVector() && "Must concat vectors");
12778 // Transform: concat_vectors(scalar, undef) -> scalar_to_vector(sclr).
12779 if (In->getOpcode() == ISD::BITCAST &&
12780 !In->getOperand(0)->getValueType(0).isVector()) {
12781 SDValue Scalar = In->getOperand(0);
12783 // If the bitcast type isn't legal, it might be a trunc of a legal type;
12784 // look through the trunc so we can still do the transform:
12785 // concat_vectors(trunc(scalar), undef) -> scalar_to_vector(scalar)
12786 if (Scalar->getOpcode() == ISD::TRUNCATE &&
12787 !TLI.isTypeLegal(Scalar.getValueType()) &&
12788 TLI.isTypeLegal(Scalar->getOperand(0).getValueType()))
12789 Scalar = Scalar->getOperand(0);
12791 EVT SclTy = Scalar->getValueType(0);
12793 if (!SclTy.isFloatingPoint() && !SclTy.isInteger())
12796 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SclTy,
12797 VT.getSizeInBits() / SclTy.getSizeInBits());
12798 if (!TLI.isTypeLegal(NVT) || !TLI.isTypeLegal(Scalar.getValueType()))
12801 SDLoc dl = SDLoc(N);
12802 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NVT, Scalar);
12803 return DAG.getNode(ISD::BITCAST, dl, VT, Res);
12807 // Fold any combination of BUILD_VECTOR or UNDEF nodes into one BUILD_VECTOR.
12808 // We have already tested above for an UNDEF only concatenation.
12809 // fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
12810 // -> (BUILD_VECTOR A, B, ..., C, D, ...)
12811 auto IsBuildVectorOrUndef = [](const SDValue &Op) {
12812 return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode();
12814 bool AllBuildVectorsOrUndefs =
12815 std::all_of(N->op_begin(), N->op_end(), IsBuildVectorOrUndef);
12816 if (AllBuildVectorsOrUndefs) {
12817 SmallVector<SDValue, 8> Opnds;
12818 EVT SVT = VT.getScalarType();
12821 if (!SVT.isFloatingPoint()) {
12822 // If BUILD_VECTOR are from built from integer, they may have different
12823 // operand types. Get the smallest type and truncate all operands to it.
12824 bool FoundMinVT = false;
12825 for (const SDValue &Op : N->ops())
12826 if (ISD::BUILD_VECTOR == Op.getOpcode()) {
12827 EVT OpSVT = Op.getOperand(0)->getValueType(0);
12828 MinVT = (!FoundMinVT || OpSVT.bitsLE(MinVT)) ? OpSVT : MinVT;
12831 assert(FoundMinVT && "Concat vector type mismatch");
12834 for (const SDValue &Op : N->ops()) {
12835 EVT OpVT = Op.getValueType();
12836 unsigned NumElts = OpVT.getVectorNumElements();
12838 if (ISD::UNDEF == Op.getOpcode())
12839 Opnds.append(NumElts, DAG.getUNDEF(MinVT));
12841 if (ISD::BUILD_VECTOR == Op.getOpcode()) {
12842 if (SVT.isFloatingPoint()) {
12843 assert(SVT == OpVT.getScalarType() && "Concat vector type mismatch");
12844 Opnds.append(Op->op_begin(), Op->op_begin() + NumElts);
12846 for (unsigned i = 0; i != NumElts; ++i)
12848 DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinVT, Op.getOperand(i)));
12853 assert(VT.getVectorNumElements() == Opnds.size() &&
12854 "Concat vector type mismatch");
12855 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
12858 // Fold CONCAT_VECTORS of only bitcast scalars (or undef) to BUILD_VECTOR.
12859 if (SDValue V = combineConcatVectorOfScalars(N, DAG))
12862 // Fold CONCAT_VECTORS of EXTRACT_SUBVECTOR (or undef) to VECTOR_SHUFFLE.
12863 if (Level < AfterLegalizeVectorOps && TLI.isTypeLegal(VT))
12864 if (SDValue V = combineConcatVectorOfExtracts(N, DAG))
12867 // Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR
12868 // nodes often generate nop CONCAT_VECTOR nodes.
12869 // Scan the CONCAT_VECTOR operands and look for a CONCAT operations that
12870 // place the incoming vectors at the exact same location.
12871 SDValue SingleSource = SDValue();
12872 unsigned PartNumElem = N->getOperand(0).getValueType().getVectorNumElements();
12874 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
12875 SDValue Op = N->getOperand(i);
12877 if (Op.getOpcode() == ISD::UNDEF)
12880 // Check if this is the identity extract:
12881 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
12884 // Find the single incoming vector for the extract_subvector.
12885 if (SingleSource.getNode()) {
12886 if (Op.getOperand(0) != SingleSource)
12889 SingleSource = Op.getOperand(0);
12891 // Check the source type is the same as the type of the result.
12892 // If not, this concat may extend the vector, so we can not
12893 // optimize it away.
12894 if (SingleSource.getValueType() != N->getValueType(0))
12898 unsigned IdentityIndex = i * PartNumElem;
12899 ConstantSDNode *CS = dyn_cast<ConstantSDNode>(Op.getOperand(1));
12900 // The extract index must be constant.
12904 // Check that we are reading from the identity index.
12905 if (CS->getZExtValue() != IdentityIndex)
12909 if (SingleSource.getNode())
12910 return SingleSource;
12915 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
12916 EVT NVT = N->getValueType(0);
12917 SDValue V = N->getOperand(0);
12919 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
12921 // (extract_subvec (concat V1, V2, ...), i)
12924 // Only operand 0 is checked as 'concat' assumes all inputs of the same
12926 if (V->getOperand(0).getValueType() != NVT)
12928 unsigned Idx = N->getConstantOperandVal(1);
12929 unsigned NumElems = NVT.getVectorNumElements();
12930 assert((Idx % NumElems) == 0 &&
12931 "IDX in concat is not a multiple of the result vector length.");
12932 return V->getOperand(Idx / NumElems);
12936 if (V->getOpcode() == ISD::BITCAST)
12937 V = V.getOperand(0);
12939 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
12941 // Handle only simple case where vector being inserted and vector
12942 // being extracted are of same type, and are half size of larger vectors.
12943 EVT BigVT = V->getOperand(0).getValueType();
12944 EVT SmallVT = V->getOperand(1).getValueType();
12945 if (!NVT.bitsEq(SmallVT) || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
12948 // Only handle cases where both indexes are constants with the same type.
12949 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
12950 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
12952 if (InsIdx && ExtIdx &&
12953 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
12954 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
12956 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
12958 // indices are equal or bit offsets are equal => V1
12959 // otherwise => (extract_subvec V1, ExtIdx)
12960 if (InsIdx->getZExtValue() * SmallVT.getScalarType().getSizeInBits() ==
12961 ExtIdx->getZExtValue() * NVT.getScalarType().getSizeInBits())
12962 return DAG.getNode(ISD::BITCAST, dl, NVT, V->getOperand(1));
12963 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT,
12964 DAG.getNode(ISD::BITCAST, dl,
12965 N->getOperand(0).getValueType(),
12966 V->getOperand(0)), N->getOperand(1));
12973 static SDValue simplifyShuffleOperandRecursively(SmallBitVector &UsedElements,
12974 SDValue V, SelectionDAG &DAG) {
12976 EVT VT = V.getValueType();
12978 switch (V.getOpcode()) {
12982 case ISD::CONCAT_VECTORS: {
12983 EVT OpVT = V->getOperand(0).getValueType();
12984 int OpSize = OpVT.getVectorNumElements();
12985 SmallBitVector OpUsedElements(OpSize, false);
12986 bool FoundSimplification = false;
12987 SmallVector<SDValue, 4> NewOps;
12988 NewOps.reserve(V->getNumOperands());
12989 for (int i = 0, NumOps = V->getNumOperands(); i < NumOps; ++i) {
12990 SDValue Op = V->getOperand(i);
12991 bool OpUsed = false;
12992 for (int j = 0; j < OpSize; ++j)
12993 if (UsedElements[i * OpSize + j]) {
12994 OpUsedElements[j] = true;
12998 OpUsed ? simplifyShuffleOperandRecursively(OpUsedElements, Op, DAG)
12999 : DAG.getUNDEF(OpVT));
13000 FoundSimplification |= Op == NewOps.back();
13001 OpUsedElements.reset();
13003 if (FoundSimplification)
13004 V = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, NewOps);
13008 case ISD::INSERT_SUBVECTOR: {
13009 SDValue BaseV = V->getOperand(0);
13010 SDValue SubV = V->getOperand(1);
13011 auto *IdxN = dyn_cast<ConstantSDNode>(V->getOperand(2));
13015 int SubSize = SubV.getValueType().getVectorNumElements();
13016 int Idx = IdxN->getZExtValue();
13017 bool SubVectorUsed = false;
13018 SmallBitVector SubUsedElements(SubSize, false);
13019 for (int i = 0; i < SubSize; ++i)
13020 if (UsedElements[i + Idx]) {
13021 SubVectorUsed = true;
13022 SubUsedElements[i] = true;
13023 UsedElements[i + Idx] = false;
13026 // Now recurse on both the base and sub vectors.
13027 SDValue SimplifiedSubV =
13029 ? simplifyShuffleOperandRecursively(SubUsedElements, SubV, DAG)
13030 : DAG.getUNDEF(SubV.getValueType());
13031 SDValue SimplifiedBaseV = simplifyShuffleOperandRecursively(UsedElements, BaseV, DAG);
13032 if (SimplifiedSubV != SubV || SimplifiedBaseV != BaseV)
13033 V = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
13034 SimplifiedBaseV, SimplifiedSubV, V->getOperand(2));
13040 static SDValue simplifyShuffleOperands(ShuffleVectorSDNode *SVN, SDValue N0,
13041 SDValue N1, SelectionDAG &DAG) {
13042 EVT VT = SVN->getValueType(0);
13043 int NumElts = VT.getVectorNumElements();
13044 SmallBitVector N0UsedElements(NumElts, false), N1UsedElements(NumElts, false);
13045 for (int M : SVN->getMask())
13046 if (M >= 0 && M < NumElts)
13047 N0UsedElements[M] = true;
13048 else if (M >= NumElts)
13049 N1UsedElements[M - NumElts] = true;
13051 SDValue S0 = simplifyShuffleOperandRecursively(N0UsedElements, N0, DAG);
13052 SDValue S1 = simplifyShuffleOperandRecursively(N1UsedElements, N1, DAG);
13053 if (S0 == N0 && S1 == N1)
13056 return DAG.getVectorShuffle(VT, SDLoc(SVN), S0, S1, SVN->getMask());
13059 // Tries to turn a shuffle of two CONCAT_VECTORS into a single concat,
13060 // or turn a shuffle of a single concat into simpler shuffle then concat.
13061 static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) {
13062 EVT VT = N->getValueType(0);
13063 unsigned NumElts = VT.getVectorNumElements();
13065 SDValue N0 = N->getOperand(0);
13066 SDValue N1 = N->getOperand(1);
13067 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
13069 SmallVector<SDValue, 4> Ops;
13070 EVT ConcatVT = N0.getOperand(0).getValueType();
13071 unsigned NumElemsPerConcat = ConcatVT.getVectorNumElements();
13072 unsigned NumConcats = NumElts / NumElemsPerConcat;
13074 // Special case: shuffle(concat(A,B)) can be more efficiently represented
13075 // as concat(shuffle(A,B),UNDEF) if the shuffle doesn't set any of the high
13076 // half vector elements.
13077 if (NumElemsPerConcat * 2 == NumElts && N1.getOpcode() == ISD::UNDEF &&
13078 std::all_of(SVN->getMask().begin() + NumElemsPerConcat,
13079 SVN->getMask().end(), [](int i) { return i == -1; })) {
13080 N0 = DAG.getVectorShuffle(ConcatVT, SDLoc(N), N0.getOperand(0), N0.getOperand(1),
13081 makeArrayRef(SVN->getMask().begin(), NumElemsPerConcat));
13082 N1 = DAG.getUNDEF(ConcatVT);
13083 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, N0, N1);
13086 // Look at every vector that's inserted. We're looking for exact
13087 // subvector-sized copies from a concatenated vector
13088 for (unsigned I = 0; I != NumConcats; ++I) {
13089 // Make sure we're dealing with a copy.
13090 unsigned Begin = I * NumElemsPerConcat;
13091 bool AllUndef = true, NoUndef = true;
13092 for (unsigned J = Begin; J != Begin + NumElemsPerConcat; ++J) {
13093 if (SVN->getMaskElt(J) >= 0)
13100 if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0)
13103 for (unsigned J = 1; J != NumElemsPerConcat; ++J)
13104 if (SVN->getMaskElt(Begin + J - 1) + 1 != SVN->getMaskElt(Begin + J))
13107 unsigned FirstElt = SVN->getMaskElt(Begin) / NumElemsPerConcat;
13108 if (FirstElt < N0.getNumOperands())
13109 Ops.push_back(N0.getOperand(FirstElt));
13111 Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands()));
13113 } else if (AllUndef) {
13114 Ops.push_back(DAG.getUNDEF(N0.getOperand(0).getValueType()));
13115 } else { // Mixed with general masks and undefs, can't do optimization.
13120 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
13123 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
13124 EVT VT = N->getValueType(0);
13125 unsigned NumElts = VT.getVectorNumElements();
13127 SDValue N0 = N->getOperand(0);
13128 SDValue N1 = N->getOperand(1);
13130 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
13132 // Canonicalize shuffle undef, undef -> undef
13133 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
13134 return DAG.getUNDEF(VT);
13136 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
13138 // Canonicalize shuffle v, v -> v, undef
13140 SmallVector<int, 8> NewMask;
13141 for (unsigned i = 0; i != NumElts; ++i) {
13142 int Idx = SVN->getMaskElt(i);
13143 if (Idx >= (int)NumElts) Idx -= NumElts;
13144 NewMask.push_back(Idx);
13146 return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT),
13150 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
13151 if (N0.getOpcode() == ISD::UNDEF) {
13152 SmallVector<int, 8> NewMask;
13153 for (unsigned i = 0; i != NumElts; ++i) {
13154 int Idx = SVN->getMaskElt(i);
13156 if (Idx >= (int)NumElts)
13159 Idx = -1; // remove reference to lhs
13161 NewMask.push_back(Idx);
13163 return DAG.getVectorShuffle(VT, SDLoc(N), N1, DAG.getUNDEF(VT),
13167 // Remove references to rhs if it is undef
13168 if (N1.getOpcode() == ISD::UNDEF) {
13169 bool Changed = false;
13170 SmallVector<int, 8> NewMask;
13171 for (unsigned i = 0; i != NumElts; ++i) {
13172 int Idx = SVN->getMaskElt(i);
13173 if (Idx >= (int)NumElts) {
13177 NewMask.push_back(Idx);
13180 return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, &NewMask[0]);
13183 // If it is a splat, check if the argument vector is another splat or a
13185 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
13186 SDNode *V = N0.getNode();
13188 // If this is a bit convert that changes the element type of the vector but
13189 // not the number of vector elements, look through it. Be careful not to
13190 // look though conversions that change things like v4f32 to v2f64.
13191 if (V->getOpcode() == ISD::BITCAST) {
13192 SDValue ConvInput = V->getOperand(0);
13193 if (ConvInput.getValueType().isVector() &&
13194 ConvInput.getValueType().getVectorNumElements() == NumElts)
13195 V = ConvInput.getNode();
13198 if (V->getOpcode() == ISD::BUILD_VECTOR) {
13199 assert(V->getNumOperands() == NumElts &&
13200 "BUILD_VECTOR has wrong number of operands");
13202 bool AllSame = true;
13203 for (unsigned i = 0; i != NumElts; ++i) {
13204 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
13205 Base = V->getOperand(i);
13209 // Splat of <u, u, u, u>, return <u, u, u, u>
13210 if (!Base.getNode())
13212 for (unsigned i = 0; i != NumElts; ++i) {
13213 if (V->getOperand(i) != Base) {
13218 // Splat of <x, x, x, x>, return <x, x, x, x>
13222 // Canonicalize any other splat as a build_vector.
13223 const SDValue &Splatted = V->getOperand(SVN->getSplatIndex());
13224 SmallVector<SDValue, 8> Ops(NumElts, Splatted);
13225 SDValue NewBV = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
13226 V->getValueType(0), Ops);
13228 // We may have jumped through bitcasts, so the type of the
13229 // BUILD_VECTOR may not match the type of the shuffle.
13230 if (V->getValueType(0) != VT)
13231 NewBV = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, NewBV);
13236 // There are various patterns used to build up a vector from smaller vectors,
13237 // subvectors, or elements. Scan chains of these and replace unused insertions
13238 // or components with undef.
13239 if (SDValue S = simplifyShuffleOperands(SVN, N0, N1, DAG))
13242 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
13243 Level < AfterLegalizeVectorOps &&
13244 (N1.getOpcode() == ISD::UNDEF ||
13245 (N1.getOpcode() == ISD::CONCAT_VECTORS &&
13246 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) {
13247 SDValue V = partitionShuffleOfConcats(N, DAG);
13253 // Attempt to combine a shuffle of 2 inputs of 'scalar sources' -
13254 // BUILD_VECTOR or SCALAR_TO_VECTOR into a single BUILD_VECTOR.
13255 if (Level < AfterLegalizeVectorOps && TLI.isTypeLegal(VT)) {
13256 SmallVector<SDValue, 8> Ops;
13257 for (int M : SVN->getMask()) {
13258 SDValue Op = DAG.getUNDEF(VT.getScalarType());
13260 int Idx = M % NumElts;
13261 SDValue &S = (M < (int)NumElts ? N0 : N1);
13262 if (S.getOpcode() == ISD::BUILD_VECTOR && S.hasOneUse()) {
13263 Op = S.getOperand(Idx);
13264 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR && S.hasOneUse()) {
13266 Op = S.getOperand(0);
13268 // Operand can't be combined - bail out.
13274 if (Ops.size() == VT.getVectorNumElements()) {
13275 // BUILD_VECTOR requires all inputs to be of the same type, find the
13276 // maximum type and extend them all.
13277 EVT SVT = VT.getScalarType();
13278 if (SVT.isInteger())
13279 for (SDValue &Op : Ops)
13280 SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT);
13281 if (SVT != VT.getScalarType())
13282 for (SDValue &Op : Ops)
13283 Op = TLI.isZExtFree(Op.getValueType(), SVT)
13284 ? DAG.getZExtOrTrunc(Op, SDLoc(N), SVT)
13285 : DAG.getSExtOrTrunc(Op, SDLoc(N), SVT);
13286 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Ops);
13290 // If this shuffle only has a single input that is a bitcasted shuffle,
13291 // attempt to merge the 2 shuffles and suitably bitcast the inputs/output
13292 // back to their original types.
13293 if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
13294 N1.getOpcode() == ISD::UNDEF && Level < AfterLegalizeVectorOps &&
13295 TLI.isTypeLegal(VT)) {
13297 // Peek through the bitcast only if there is one user.
13299 while (BC0.getOpcode() == ISD::BITCAST) {
13300 if (!BC0.hasOneUse())
13302 BC0 = BC0.getOperand(0);
13305 auto ScaleShuffleMask = [](ArrayRef<int> Mask, int Scale) {
13307 return SmallVector<int, 8>(Mask.begin(), Mask.end());
13309 SmallVector<int, 8> NewMask;
13311 for (int s = 0; s != Scale; ++s)
13312 NewMask.push_back(M < 0 ? -1 : Scale * M + s);
13316 if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) {
13317 EVT SVT = VT.getScalarType();
13318 EVT InnerVT = BC0->getValueType(0);
13319 EVT InnerSVT = InnerVT.getScalarType();
13321 // Determine which shuffle works with the smaller scalar type.
13322 EVT ScaleVT = SVT.bitsLT(InnerSVT) ? VT : InnerVT;
13323 EVT ScaleSVT = ScaleVT.getScalarType();
13325 if (TLI.isTypeLegal(ScaleVT) &&
13326 0 == (InnerSVT.getSizeInBits() % ScaleSVT.getSizeInBits()) &&
13327 0 == (SVT.getSizeInBits() % ScaleSVT.getSizeInBits())) {
13329 int InnerScale = InnerSVT.getSizeInBits() / ScaleSVT.getSizeInBits();
13330 int OuterScale = SVT.getSizeInBits() / ScaleSVT.getSizeInBits();
13332 // Scale the shuffle masks to the smaller scalar type.
13333 ShuffleVectorSDNode *InnerSVN = cast<ShuffleVectorSDNode>(BC0);
13334 SmallVector<int, 8> InnerMask =
13335 ScaleShuffleMask(InnerSVN->getMask(), InnerScale);
13336 SmallVector<int, 8> OuterMask =
13337 ScaleShuffleMask(SVN->getMask(), OuterScale);
13339 // Merge the shuffle masks.
13340 SmallVector<int, 8> NewMask;
13341 for (int M : OuterMask)
13342 NewMask.push_back(M < 0 ? -1 : InnerMask[M]);
13344 // Test for shuffle mask legality over both commutations.
13345 SDValue SV0 = BC0->getOperand(0);
13346 SDValue SV1 = BC0->getOperand(1);
13347 bool LegalMask = TLI.isShuffleMaskLegal(NewMask, ScaleVT);
13349 std::swap(SV0, SV1);
13350 ShuffleVectorSDNode::commuteMask(NewMask);
13351 LegalMask = TLI.isShuffleMaskLegal(NewMask, ScaleVT);
13355 SV0 = DAG.getNode(ISD::BITCAST, SDLoc(N), ScaleVT, SV0);
13356 SV1 = DAG.getNode(ISD::BITCAST, SDLoc(N), ScaleVT, SV1);
13357 return DAG.getNode(
13358 ISD::BITCAST, SDLoc(N), VT,
13359 DAG.getVectorShuffle(ScaleVT, SDLoc(N), SV0, SV1, NewMask));
13365 // Canonicalize shuffles according to rules:
13366 // shuffle(A, shuffle(A, B)) -> shuffle(shuffle(A,B), A)
13367 // shuffle(B, shuffle(A, B)) -> shuffle(shuffle(A,B), B)
13368 // shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
13369 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
13370 N0.getOpcode() != ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
13371 TLI.isTypeLegal(VT)) {
13372 // The incoming shuffle must be of the same type as the result of the
13373 // current shuffle.
13374 assert(N1->getOperand(0).getValueType() == VT &&
13375 "Shuffle types don't match");
13377 SDValue SV0 = N1->getOperand(0);
13378 SDValue SV1 = N1->getOperand(1);
13379 bool HasSameOp0 = N0 == SV0;
13380 bool IsSV1Undef = SV1.getOpcode() == ISD::UNDEF;
13381 if (HasSameOp0 || IsSV1Undef || N0 == SV1)
13382 // Commute the operands of this shuffle so that next rule
13384 return DAG.getCommutedVectorShuffle(*SVN);
13387 // Try to fold according to rules:
13388 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, B, M2)
13389 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, C, M2)
13390 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, C, M2)
13391 // Don't try to fold shuffles with illegal type.
13392 // Only fold if this shuffle is the only user of the other shuffle.
13393 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && N->isOnlyUserOf(N0.getNode()) &&
13394 Level < AfterLegalizeDAG && TLI.isTypeLegal(VT)) {
13395 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
13397 // The incoming shuffle must be of the same type as the result of the
13398 // current shuffle.
13399 assert(OtherSV->getOperand(0).getValueType() == VT &&
13400 "Shuffle types don't match");
13403 SmallVector<int, 4> Mask;
13404 // Compute the combined shuffle mask for a shuffle with SV0 as the first
13405 // operand, and SV1 as the second operand.
13406 for (unsigned i = 0; i != NumElts; ++i) {
13407 int Idx = SVN->getMaskElt(i);
13409 // Propagate Undef.
13410 Mask.push_back(Idx);
13414 SDValue CurrentVec;
13415 if (Idx < (int)NumElts) {
13416 // This shuffle index refers to the inner shuffle N0. Lookup the inner
13417 // shuffle mask to identify which vector is actually referenced.
13418 Idx = OtherSV->getMaskElt(Idx);
13420 // Propagate Undef.
13421 Mask.push_back(Idx);
13425 CurrentVec = (Idx < (int) NumElts) ? OtherSV->getOperand(0)
13426 : OtherSV->getOperand(1);
13428 // This shuffle index references an element within N1.
13432 // Simple case where 'CurrentVec' is UNDEF.
13433 if (CurrentVec.getOpcode() == ISD::UNDEF) {
13434 Mask.push_back(-1);
13438 // Canonicalize the shuffle index. We don't know yet if CurrentVec
13439 // will be the first or second operand of the combined shuffle.
13440 Idx = Idx % NumElts;
13441 if (!SV0.getNode() || SV0 == CurrentVec) {
13442 // Ok. CurrentVec is the left hand side.
13443 // Update the mask accordingly.
13445 Mask.push_back(Idx);
13449 // Bail out if we cannot convert the shuffle pair into a single shuffle.
13450 if (SV1.getNode() && SV1 != CurrentVec)
13453 // Ok. CurrentVec is the right hand side.
13454 // Update the mask accordingly.
13456 Mask.push_back(Idx + NumElts);
13459 // Check if all indices in Mask are Undef. In case, propagate Undef.
13460 bool isUndefMask = true;
13461 for (unsigned i = 0; i != NumElts && isUndefMask; ++i)
13462 isUndefMask &= Mask[i] < 0;
13465 return DAG.getUNDEF(VT);
13467 if (!SV0.getNode())
13468 SV0 = DAG.getUNDEF(VT);
13469 if (!SV1.getNode())
13470 SV1 = DAG.getUNDEF(VT);
13472 // Avoid introducing shuffles with illegal mask.
13473 if (!TLI.isShuffleMaskLegal(Mask, VT)) {
13474 ShuffleVectorSDNode::commuteMask(Mask);
13476 if (!TLI.isShuffleMaskLegal(Mask, VT))
13479 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, A, M2)
13480 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(C, A, M2)
13481 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(C, B, M2)
13482 std::swap(SV0, SV1);
13485 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, B, M2)
13486 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, C, M2)
13487 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, C, M2)
13488 return DAG.getVectorShuffle(VT, SDLoc(N), SV0, SV1, &Mask[0]);
13494 SDValue DAGCombiner::visitSCALAR_TO_VECTOR(SDNode *N) {
13495 SDValue InVal = N->getOperand(0);
13496 EVT VT = N->getValueType(0);
13498 // Replace a SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT(V,C0)) pattern
13499 // with a VECTOR_SHUFFLE.
13500 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
13501 SDValue InVec = InVal->getOperand(0);
13502 SDValue EltNo = InVal->getOperand(1);
13504 // FIXME: We could support implicit truncation if the shuffle can be
13505 // scaled to a smaller vector scalar type.
13506 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(EltNo);
13507 if (C0 && VT == InVec.getValueType() &&
13508 VT.getScalarType() == InVal.getValueType()) {
13509 SmallVector<int, 8> NewMask(VT.getVectorNumElements(), -1);
13510 int Elt = C0->getZExtValue();
13513 if (TLI.isShuffleMaskLegal(NewMask, VT))
13514 return DAG.getVectorShuffle(VT, SDLoc(N), InVec, DAG.getUNDEF(VT),
13522 SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) {
13523 SDValue N0 = N->getOperand(0);
13524 SDValue N2 = N->getOperand(2);
13526 // If the input vector is a concatenation, and the insert replaces
13527 // one of the halves, we can optimize into a single concat_vectors.
13528 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
13529 N0->getNumOperands() == 2 && N2.getOpcode() == ISD::Constant) {
13530 APInt InsIdx = cast<ConstantSDNode>(N2)->getAPIntValue();
13531 EVT VT = N->getValueType(0);
13533 // Lower half: fold (insert_subvector (concat_vectors X, Y), Z) ->
13534 // (concat_vectors Z, Y)
13536 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
13537 N->getOperand(1), N0.getOperand(1));
13539 // Upper half: fold (insert_subvector (concat_vectors X, Y), Z) ->
13540 // (concat_vectors X, Z)
13541 if (InsIdx == VT.getVectorNumElements()/2)
13542 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
13543 N0.getOperand(0), N->getOperand(1));
13549 SDValue DAGCombiner::visitFP_TO_FP16(SDNode *N) {
13550 SDValue N0 = N->getOperand(0);
13552 // fold (fp_to_fp16 (fp16_to_fp op)) -> op
13553 if (N0->getOpcode() == ISD::FP16_TO_FP)
13554 return N0->getOperand(0);
13559 SDValue DAGCombiner::visitFP16_TO_FP(SDNode *N) {
13560 SDValue N0 = N->getOperand(0);
13562 // fold fp16_to_fp(op & 0xffff) -> fp16_to_fp(op)
13563 if (N0->getOpcode() == ISD::AND) {
13564 ConstantSDNode *AndConst = getAsNonOpaqueConstant(N0.getOperand(1));
13565 if (AndConst && AndConst->getAPIntValue() == 0xffff) {
13566 return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), N->getValueType(0),
13574 /// Returns a vector_shuffle if it able to transform an AND to a vector_shuffle
13575 /// with the destination vector and a zero vector.
13576 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
13577 /// vector_shuffle V, Zero, <0, 4, 2, 4>
13578 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
13579 EVT VT = N->getValueType(0);
13580 SDValue LHS = N->getOperand(0);
13581 SDValue RHS = N->getOperand(1);
13584 // Make sure we're not running after operation legalization where it
13585 // may have custom lowered the vector shuffles.
13586 if (LegalOperations)
13589 if (N->getOpcode() != ISD::AND)
13592 if (RHS.getOpcode() == ISD::BITCAST)
13593 RHS = RHS.getOperand(0);
13595 if (RHS.getOpcode() != ISD::BUILD_VECTOR)
13598 EVT RVT = RHS.getValueType();
13599 unsigned NumElts = RHS.getNumOperands();
13601 // Attempt to create a valid clear mask, splitting the mask into
13602 // sub elements and checking to see if each is
13603 // all zeros or all ones - suitable for shuffle masking.
13604 auto BuildClearMask = [&](int Split) {
13605 int NumSubElts = NumElts * Split;
13606 int NumSubBits = RVT.getScalarSizeInBits() / Split;
13608 SmallVector<int, 8> Indices;
13609 for (int i = 0; i != NumSubElts; ++i) {
13610 int EltIdx = i / Split;
13611 int SubIdx = i % Split;
13612 SDValue Elt = RHS.getOperand(EltIdx);
13613 if (Elt.getOpcode() == ISD::UNDEF) {
13614 Indices.push_back(-1);
13619 if (isa<ConstantSDNode>(Elt))
13620 Bits = cast<ConstantSDNode>(Elt)->getAPIntValue();
13621 else if (isa<ConstantFPSDNode>(Elt))
13622 Bits = cast<ConstantFPSDNode>(Elt)->getValueAPF().bitcastToAPInt();
13626 // Extract the sub element from the constant bit mask.
13627 if (DAG.getDataLayout().isBigEndian()) {
13628 Bits = Bits.lshr((Split - SubIdx - 1) * NumSubBits);
13630 Bits = Bits.lshr(SubIdx * NumSubBits);
13634 Bits = Bits.trunc(NumSubBits);
13636 if (Bits.isAllOnesValue())
13637 Indices.push_back(i);
13638 else if (Bits == 0)
13639 Indices.push_back(i + NumSubElts);
13644 // Let's see if the target supports this vector_shuffle.
13645 EVT ClearSVT = EVT::getIntegerVT(*DAG.getContext(), NumSubBits);
13646 EVT ClearVT = EVT::getVectorVT(*DAG.getContext(), ClearSVT, NumSubElts);
13647 if (!TLI.isVectorClearMaskLegal(Indices, ClearVT))
13650 SDValue Zero = DAG.getConstant(0, dl, ClearVT);
13651 return DAG.getBitcast(VT, DAG.getVectorShuffle(ClearVT, dl,
13652 DAG.getBitcast(ClearVT, LHS),
13653 Zero, &Indices[0]));
13656 // Determine maximum split level (byte level masking).
13658 if (RVT.getScalarSizeInBits() % 8 == 0)
13659 MaxSplit = RVT.getScalarSizeInBits() / 8;
13661 for (int Split = 1; Split <= MaxSplit; ++Split)
13662 if (RVT.getScalarSizeInBits() % Split == 0)
13663 if (SDValue S = BuildClearMask(Split))
13669 /// Visit a binary vector operation, like ADD.
13670 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
13671 assert(N->getValueType(0).isVector() &&
13672 "SimplifyVBinOp only works on vectors!");
13674 SDValue LHS = N->getOperand(0);
13675 SDValue RHS = N->getOperand(1);
13676 SDValue Ops[] = {LHS, RHS};
13678 // See if we can constant fold the vector operation.
13679 if (SDValue Fold = DAG.FoldConstantVectorArithmetic(
13680 N->getOpcode(), SDLoc(LHS), LHS.getValueType(), Ops, N->getFlags()))
13683 // Try to convert a constant mask AND into a shuffle clear mask.
13684 if (SDValue Shuffle = XformToShuffleWithZero(N))
13687 // Type legalization might introduce new shuffles in the DAG.
13688 // Fold (VBinOp (shuffle (A, Undef, Mask)), (shuffle (B, Undef, Mask)))
13689 // -> (shuffle (VBinOp (A, B)), Undef, Mask).
13690 if (LegalTypes && isa<ShuffleVectorSDNode>(LHS) &&
13691 isa<ShuffleVectorSDNode>(RHS) && LHS.hasOneUse() && RHS.hasOneUse() &&
13692 LHS.getOperand(1).getOpcode() == ISD::UNDEF &&
13693 RHS.getOperand(1).getOpcode() == ISD::UNDEF) {
13694 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(LHS);
13695 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(RHS);
13697 if (SVN0->getMask().equals(SVN1->getMask())) {
13698 EVT VT = N->getValueType(0);
13699 SDValue UndefVector = LHS.getOperand(1);
13700 SDValue NewBinOp = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
13701 LHS.getOperand(0), RHS.getOperand(0),
13703 AddUsersToWorklist(N);
13704 return DAG.getVectorShuffle(VT, SDLoc(N), NewBinOp, UndefVector,
13705 &SVN0->getMask()[0]);
13712 SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0,
13713 SDValue N1, SDValue N2){
13714 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
13716 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
13717 cast<CondCodeSDNode>(N0.getOperand(2))->get());
13719 // If we got a simplified select_cc node back from SimplifySelectCC, then
13720 // break it down into a new SETCC node, and a new SELECT node, and then return
13721 // the SELECT node, since we were called with a SELECT node.
13722 if (SCC.getNode()) {
13723 // Check to see if we got a select_cc back (to turn into setcc/select).
13724 // Otherwise, just return whatever node we got back, like fabs.
13725 if (SCC.getOpcode() == ISD::SELECT_CC) {
13726 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
13728 SCC.getOperand(0), SCC.getOperand(1),
13729 SCC.getOperand(4));
13730 AddToWorklist(SETCC.getNode());
13731 return DAG.getSelect(SDLoc(SCC), SCC.getValueType(), SETCC,
13732 SCC.getOperand(2), SCC.getOperand(3));
13740 /// Given a SELECT or a SELECT_CC node, where LHS and RHS are the two values
13741 /// being selected between, see if we can simplify the select. Callers of this
13742 /// should assume that TheSelect is deleted if this returns true. As such, they
13743 /// should return the appropriate thing (e.g. the node) back to the top-level of
13744 /// the DAG combiner loop to avoid it being looked at.
13745 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
13748 // fold (select (setcc x, -0.0, *lt), NaN, (fsqrt x))
13749 // The select + setcc is redundant, because fsqrt returns NaN for X < -0.
13750 if (const ConstantFPSDNode *NaN = isConstOrConstSplatFP(LHS)) {
13751 if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) {
13752 // We have: (select (setcc ?, ?, ?), NaN, (fsqrt ?))
13753 SDValue Sqrt = RHS;
13756 const ConstantFPSDNode *NegZero = nullptr;
13758 if (TheSelect->getOpcode() == ISD::SELECT_CC) {
13759 CC = dyn_cast<CondCodeSDNode>(TheSelect->getOperand(4))->get();
13760 CmpLHS = TheSelect->getOperand(0);
13761 NegZero = isConstOrConstSplatFP(TheSelect->getOperand(1));
13763 // SELECT or VSELECT
13764 SDValue Cmp = TheSelect->getOperand(0);
13765 if (Cmp.getOpcode() == ISD::SETCC) {
13766 CC = dyn_cast<CondCodeSDNode>(Cmp.getOperand(2))->get();
13767 CmpLHS = Cmp.getOperand(0);
13768 NegZero = isConstOrConstSplatFP(Cmp.getOperand(1));
13771 if (NegZero && NegZero->isNegative() && NegZero->isZero() &&
13772 Sqrt.getOperand(0) == CmpLHS && (CC == ISD::SETOLT ||
13773 CC == ISD::SETULT || CC == ISD::SETLT)) {
13774 // We have: (select (setcc x, -0.0, *lt), NaN, (fsqrt x))
13775 CombineTo(TheSelect, Sqrt);
13780 // Cannot simplify select with vector condition
13781 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
13783 // If this is a select from two identical things, try to pull the operation
13784 // through the select.
13785 if (LHS.getOpcode() != RHS.getOpcode() ||
13786 !LHS.hasOneUse() || !RHS.hasOneUse())
13789 // If this is a load and the token chain is identical, replace the select
13790 // of two loads with a load through a select of the address to load from.
13791 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
13792 // constants have been dropped into the constant pool.
13793 if (LHS.getOpcode() == ISD::LOAD) {
13794 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
13795 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
13797 // Token chains must be identical.
13798 if (LHS.getOperand(0) != RHS.getOperand(0) ||
13799 // Do not let this transformation reduce the number of volatile loads.
13800 LLD->isVolatile() || RLD->isVolatile() ||
13801 // FIXME: If either is a pre/post inc/dec load,
13802 // we'd need to split out the address adjustment.
13803 LLD->isIndexed() || RLD->isIndexed() ||
13804 // If this is an EXTLOAD, the VT's must match.
13805 LLD->getMemoryVT() != RLD->getMemoryVT() ||
13806 // If this is an EXTLOAD, the kind of extension must match.
13807 (LLD->getExtensionType() != RLD->getExtensionType() &&
13808 // The only exception is if one of the extensions is anyext.
13809 LLD->getExtensionType() != ISD::EXTLOAD &&
13810 RLD->getExtensionType() != ISD::EXTLOAD) ||
13811 // FIXME: this discards src value information. This is
13812 // over-conservative. It would be beneficial to be able to remember
13813 // both potential memory locations. Since we are discarding
13814 // src value info, don't do the transformation if the memory
13815 // locations are not in the default address space.
13816 LLD->getPointerInfo().getAddrSpace() != 0 ||
13817 RLD->getPointerInfo().getAddrSpace() != 0 ||
13818 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(),
13819 LLD->getBasePtr().getValueType()))
13822 // Check that the select condition doesn't reach either load. If so,
13823 // folding this will induce a cycle into the DAG. If not, this is safe to
13824 // xform, so create a select of the addresses.
13826 if (TheSelect->getOpcode() == ISD::SELECT) {
13827 SDNode *CondNode = TheSelect->getOperand(0).getNode();
13828 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
13829 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
13831 // The loads must not depend on one another.
13832 if (LLD->isPredecessorOf(RLD) ||
13833 RLD->isPredecessorOf(LLD))
13835 Addr = DAG.getSelect(SDLoc(TheSelect),
13836 LLD->getBasePtr().getValueType(),
13837 TheSelect->getOperand(0), LLD->getBasePtr(),
13838 RLD->getBasePtr());
13839 } else { // Otherwise SELECT_CC
13840 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
13841 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
13843 if ((LLD->hasAnyUseOfValue(1) &&
13844 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
13845 (RLD->hasAnyUseOfValue(1) &&
13846 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
13849 Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect),
13850 LLD->getBasePtr().getValueType(),
13851 TheSelect->getOperand(0),
13852 TheSelect->getOperand(1),
13853 LLD->getBasePtr(), RLD->getBasePtr(),
13854 TheSelect->getOperand(4));
13858 // It is safe to replace the two loads if they have different alignments,
13859 // but the new load must be the minimum (most restrictive) alignment of the
13861 bool isInvariant = LLD->isInvariant() & RLD->isInvariant();
13862 unsigned Alignment = std::min(LLD->getAlignment(), RLD->getAlignment());
13863 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
13864 Load = DAG.getLoad(TheSelect->getValueType(0),
13866 // FIXME: Discards pointer and AA info.
13867 LLD->getChain(), Addr, MachinePointerInfo(),
13868 LLD->isVolatile(), LLD->isNonTemporal(),
13869 isInvariant, Alignment);
13871 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
13872 RLD->getExtensionType() : LLD->getExtensionType(),
13874 TheSelect->getValueType(0),
13875 // FIXME: Discards pointer and AA info.
13876 LLD->getChain(), Addr, MachinePointerInfo(),
13877 LLD->getMemoryVT(), LLD->isVolatile(),
13878 LLD->isNonTemporal(), isInvariant, Alignment);
13881 // Users of the select now use the result of the load.
13882 CombineTo(TheSelect, Load);
13884 // Users of the old loads now use the new load's chain. We know the
13885 // old-load value is dead now.
13886 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
13887 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
13894 /// Simplify an expression of the form (N0 cond N1) ? N2 : N3
13895 /// where 'cond' is the comparison specified by CC.
13896 SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
13897 SDValue N2, SDValue N3,
13898 ISD::CondCode CC, bool NotExtCompare) {
13899 // (x ? y : y) -> y.
13900 if (N2 == N3) return N2;
13902 EVT VT = N2.getValueType();
13903 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
13904 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
13906 // Determine if the condition we're dealing with is constant
13907 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
13908 N0, N1, CC, DL, false);
13909 if (SCC.getNode()) AddToWorklist(SCC.getNode());
13911 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
13912 // fold select_cc true, x, y -> x
13913 // fold select_cc false, x, y -> y
13914 return !SCCC->isNullValue() ? N2 : N3;
13917 // Check to see if we can simplify the select into an fabs node
13918 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
13919 // Allow either -0.0 or 0.0
13920 if (CFP->isZero()) {
13921 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
13922 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
13923 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
13924 N2 == N3.getOperand(0))
13925 return DAG.getNode(ISD::FABS, DL, VT, N0);
13927 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
13928 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
13929 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
13930 N2.getOperand(0) == N3)
13931 return DAG.getNode(ISD::FABS, DL, VT, N3);
13935 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
13936 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
13937 // in it. This is a win when the constant is not otherwise available because
13938 // it replaces two constant pool loads with one. We only do this if the FP
13939 // type is known to be legal, because if it isn't, then we are before legalize
13940 // types an we want the other legalization to happen first (e.g. to avoid
13941 // messing with soft float) and if the ConstantFP is not legal, because if
13942 // it is legal, we may not need to store the FP constant in a constant pool.
13943 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
13944 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
13945 if (TLI.isTypeLegal(N2.getValueType()) &&
13946 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
13947 TargetLowering::Legal &&
13948 !TLI.isFPImmLegal(TV->getValueAPF(), TV->getValueType(0)) &&
13949 !TLI.isFPImmLegal(FV->getValueAPF(), FV->getValueType(0))) &&
13950 // If both constants have multiple uses, then we won't need to do an
13951 // extra load, they are likely around in registers for other users.
13952 (TV->hasOneUse() || FV->hasOneUse())) {
13953 Constant *Elts[] = {
13954 const_cast<ConstantFP*>(FV->getConstantFPValue()),
13955 const_cast<ConstantFP*>(TV->getConstantFPValue())
13957 Type *FPTy = Elts[0]->getType();
13958 const DataLayout &TD = DAG.getDataLayout();
13960 // Create a ConstantArray of the two constants.
13961 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
13963 DAG.getConstantPool(CA, TLI.getPointerTy(DAG.getDataLayout()),
13964 TD.getPrefTypeAlignment(FPTy));
13965 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13967 // Get the offsets to the 0 and 1 element of the array so that we can
13968 // select between them.
13969 SDValue Zero = DAG.getIntPtrConstant(0, DL);
13970 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
13971 SDValue One = DAG.getIntPtrConstant(EltSize, SDLoc(FV));
13973 SDValue Cond = DAG.getSetCC(DL,
13974 getSetCCResultType(N0.getValueType()),
13976 AddToWorklist(Cond.getNode());
13977 SDValue CstOffset = DAG.getSelect(DL, Zero.getValueType(),
13979 AddToWorklist(CstOffset.getNode());
13980 CPIdx = DAG.getNode(ISD::ADD, DL, CPIdx.getValueType(), CPIdx,
13982 AddToWorklist(CPIdx.getNode());
13983 return DAG.getLoad(
13984 TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
13985 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13986 false, false, false, Alignment);
13990 // Check to see if we can perform the "gzip trick", transforming
13991 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
13992 if (isNullConstant(N3) && CC == ISD::SETLT &&
13993 (isNullConstant(N1) || // (a < 0) ? b : 0
13994 (isOneConstant(N1) && N0 == N2))) { // (a < 1) ? a : 0
13995 EVT XType = N0.getValueType();
13996 EVT AType = N2.getValueType();
13997 if (XType.bitsGE(AType)) {
13998 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
13999 // single-bit constant.
14000 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue() - 1)) == 0)) {
14001 unsigned ShCtV = N2C->getAPIntValue().logBase2();
14002 ShCtV = XType.getSizeInBits() - ShCtV - 1;
14003 SDValue ShCt = DAG.getConstant(ShCtV, SDLoc(N0),
14004 getShiftAmountTy(N0.getValueType()));
14005 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0),
14007 AddToWorklist(Shift.getNode());
14009 if (XType.bitsGT(AType)) {
14010 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
14011 AddToWorklist(Shift.getNode());
14014 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
14017 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0),
14019 DAG.getConstant(XType.getSizeInBits() - 1,
14021 getShiftAmountTy(N0.getValueType())));
14022 AddToWorklist(Shift.getNode());
14024 if (XType.bitsGT(AType)) {
14025 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
14026 AddToWorklist(Shift.getNode());
14029 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
14033 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
14034 // where y is has a single bit set.
14035 // A plaintext description would be, we can turn the SELECT_CC into an AND
14036 // when the condition can be materialized as an all-ones register. Any
14037 // single bit-test can be materialized as an all-ones register with
14038 // shift-left and shift-right-arith.
14039 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
14040 N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2)) {
14041 SDValue AndLHS = N0->getOperand(0);
14042 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
14043 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
14044 // Shift the tested bit over the sign bit.
14045 APInt AndMask = ConstAndRHS->getAPIntValue();
14047 DAG.getConstant(AndMask.countLeadingZeros(), SDLoc(AndLHS),
14048 getShiftAmountTy(AndLHS.getValueType()));
14049 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
14051 // Now arithmetic right shift it all the way over, so the result is either
14052 // all-ones, or zero.
14054 DAG.getConstant(AndMask.getBitWidth() - 1, SDLoc(Shl),
14055 getShiftAmountTy(Shl.getValueType()));
14056 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
14058 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
14062 // fold select C, 16, 0 -> shl C, 4
14063 if (N2C && isNullConstant(N3) && N2C->getAPIntValue().isPowerOf2() &&
14064 TLI.getBooleanContents(N0.getValueType()) ==
14065 TargetLowering::ZeroOrOneBooleanContent) {
14067 // If the caller doesn't want us to simplify this into a zext of a compare,
14069 if (NotExtCompare && N2C->isOne())
14072 // Get a SetCC of the condition
14073 // NOTE: Don't create a SETCC if it's not legal on this target.
14074 if (!LegalOperations ||
14075 TLI.isOperationLegal(ISD::SETCC, N0.getValueType())) {
14077 // cast from setcc result type to select result type
14079 SCC = DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()),
14081 if (N2.getValueType().bitsLT(SCC.getValueType()))
14082 Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2),
14083 N2.getValueType());
14085 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
14086 N2.getValueType(), SCC);
14088 SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
14089 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
14090 N2.getValueType(), SCC);
14093 AddToWorklist(SCC.getNode());
14094 AddToWorklist(Temp.getNode());
14099 // shl setcc result by log2 n2c
14100 return DAG.getNode(
14101 ISD::SHL, DL, N2.getValueType(), Temp,
14102 DAG.getConstant(N2C->getAPIntValue().logBase2(), SDLoc(Temp),
14103 getShiftAmountTy(Temp.getValueType())));
14107 // Check to see if this is an integer abs.
14108 // select_cc setg[te] X, 0, X, -X ->
14109 // select_cc setgt X, -1, X, -X ->
14110 // select_cc setl[te] X, 0, -X, X ->
14111 // select_cc setlt X, 1, -X, X ->
14112 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
14114 ConstantSDNode *SubC = nullptr;
14115 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
14116 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
14117 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
14118 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
14119 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
14120 (N1C->isOne() && CC == ISD::SETLT)) &&
14121 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
14122 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
14124 EVT XType = N0.getValueType();
14125 if (SubC && SubC->isNullValue() && XType.isInteger()) {
14127 SDValue Shift = DAG.getNode(ISD::SRA, DL, XType,
14129 DAG.getConstant(XType.getSizeInBits() - 1, DL,
14130 getShiftAmountTy(N0.getValueType())));
14131 SDValue Add = DAG.getNode(ISD::ADD, DL,
14133 AddToWorklist(Shift.getNode());
14134 AddToWorklist(Add.getNode());
14135 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
14142 /// This is a stub for TargetLowering::SimplifySetCC.
14143 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
14144 SDValue N1, ISD::CondCode Cond,
14145 SDLoc DL, bool foldBooleans) {
14146 TargetLowering::DAGCombinerInfo
14147 DagCombineInfo(DAG, Level, false, this);
14148 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
14151 /// Given an ISD::SDIV node expressing a divide by constant, return
14152 /// a DAG expression to select that will generate the same value by multiplying
14153 /// by a magic number.
14154 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
14155 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
14156 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
14160 // Avoid division by zero.
14161 if (C->isNullValue())
14164 std::vector<SDNode*> Built;
14166 TLI.BuildSDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
14168 for (SDNode *N : Built)
14173 /// Given an ISD::SDIV node expressing a divide by constant power of 2, return a
14174 /// DAG expression that will generate the same value by right shifting.
14175 SDValue DAGCombiner::BuildSDIVPow2(SDNode *N) {
14176 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
14180 // Avoid division by zero.
14181 if (C->isNullValue())
14184 std::vector<SDNode *> Built;
14185 SDValue S = TLI.BuildSDIVPow2(N, C->getAPIntValue(), DAG, &Built);
14187 for (SDNode *N : Built)
14192 /// Given an ISD::UDIV node expressing a divide by constant, return a DAG
14193 /// expression that will generate the same value by multiplying by a magic
14195 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
14196 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
14197 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
14201 // Avoid division by zero.
14202 if (C->isNullValue())
14205 std::vector<SDNode*> Built;
14207 TLI.BuildUDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
14209 for (SDNode *N : Built)
14214 SDValue DAGCombiner::BuildReciprocalEstimate(SDValue Op, SDNodeFlags *Flags) {
14215 if (Level >= AfterLegalizeDAG)
14218 // Expose the DAG combiner to the target combiner implementations.
14219 TargetLowering::DAGCombinerInfo DCI(DAG, Level, false, this);
14221 unsigned Iterations = 0;
14222 if (SDValue Est = TLI.getRecipEstimate(Op, DCI, Iterations)) {
14224 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
14225 // For the reciprocal, we need to find the zero of the function:
14226 // F(X) = A X - 1 [which has a zero at X = 1/A]
14228 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
14229 // does not require additional intermediate precision]
14230 EVT VT = Op.getValueType();
14232 SDValue FPOne = DAG.getConstantFP(1.0, DL, VT);
14234 AddToWorklist(Est.getNode());
14236 // Newton iterations: Est = Est + Est (1 - Arg * Est)
14237 for (unsigned i = 0; i < Iterations; ++i) {
14238 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Op, Est, Flags);
14239 AddToWorklist(NewEst.getNode());
14241 NewEst = DAG.getNode(ISD::FSUB, DL, VT, FPOne, NewEst, Flags);
14242 AddToWorklist(NewEst.getNode());
14244 NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst, Flags);
14245 AddToWorklist(NewEst.getNode());
14247 Est = DAG.getNode(ISD::FADD, DL, VT, Est, NewEst, Flags);
14248 AddToWorklist(Est.getNode());
14257 /// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
14258 /// For the reciprocal sqrt, we need to find the zero of the function:
14259 /// F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
14261 /// X_{i+1} = X_i (1.5 - A X_i^2 / 2)
14262 /// As a result, we precompute A/2 prior to the iteration loop.
14263 SDValue DAGCombiner::BuildRsqrtNROneConst(SDValue Arg, SDValue Est,
14264 unsigned Iterations,
14265 SDNodeFlags *Flags) {
14266 EVT VT = Arg.getValueType();
14268 SDValue ThreeHalves = DAG.getConstantFP(1.5, DL, VT);
14270 // We now need 0.5 * Arg which we can write as (1.5 * Arg - Arg) so that
14271 // this entire sequence requires only one FP constant.
14272 SDValue HalfArg = DAG.getNode(ISD::FMUL, DL, VT, ThreeHalves, Arg, Flags);
14273 AddToWorklist(HalfArg.getNode());
14275 HalfArg = DAG.getNode(ISD::FSUB, DL, VT, HalfArg, Arg, Flags);
14276 AddToWorklist(HalfArg.getNode());
14278 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
14279 for (unsigned i = 0; i < Iterations; ++i) {
14280 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, Est, Flags);
14281 AddToWorklist(NewEst.getNode());
14283 NewEst = DAG.getNode(ISD::FMUL, DL, VT, HalfArg, NewEst, Flags);
14284 AddToWorklist(NewEst.getNode());
14286 NewEst = DAG.getNode(ISD::FSUB, DL, VT, ThreeHalves, NewEst, Flags);
14287 AddToWorklist(NewEst.getNode());
14289 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst, Flags);
14290 AddToWorklist(Est.getNode());
14295 /// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
14296 /// For the reciprocal sqrt, we need to find the zero of the function:
14297 /// F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
14299 /// X_{i+1} = (-0.5 * X_i) * (A * X_i * X_i + (-3.0))
14300 SDValue DAGCombiner::BuildRsqrtNRTwoConst(SDValue Arg, SDValue Est,
14301 unsigned Iterations,
14302 SDNodeFlags *Flags) {
14303 EVT VT = Arg.getValueType();
14305 SDValue MinusThree = DAG.getConstantFP(-3.0, DL, VT);
14306 SDValue MinusHalf = DAG.getConstantFP(-0.5, DL, VT);
14308 // Newton iterations: Est = -0.5 * Est * (-3.0 + Arg * Est * Est)
14309 for (unsigned i = 0; i < Iterations; ++i) {
14310 SDValue HalfEst = DAG.getNode(ISD::FMUL, DL, VT, Est, MinusHalf, Flags);
14311 AddToWorklist(HalfEst.getNode());
14313 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Est, Flags);
14314 AddToWorklist(Est.getNode());
14316 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Arg, Flags);
14317 AddToWorklist(Est.getNode());
14319 Est = DAG.getNode(ISD::FADD, DL, VT, Est, MinusThree, Flags);
14320 AddToWorklist(Est.getNode());
14322 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, HalfEst, Flags);
14323 AddToWorklist(Est.getNode());
14328 SDValue DAGCombiner::BuildRsqrtEstimate(SDValue Op, SDNodeFlags *Flags) {
14329 if (Level >= AfterLegalizeDAG)
14332 // Expose the DAG combiner to the target combiner implementations.
14333 TargetLowering::DAGCombinerInfo DCI(DAG, Level, false, this);
14334 unsigned Iterations = 0;
14335 bool UseOneConstNR = false;
14336 if (SDValue Est = TLI.getRsqrtEstimate(Op, DCI, Iterations, UseOneConstNR)) {
14337 AddToWorklist(Est.getNode());
14339 Est = UseOneConstNR ?
14340 BuildRsqrtNROneConst(Op, Est, Iterations, Flags) :
14341 BuildRsqrtNRTwoConst(Op, Est, Iterations, Flags);
14349 /// Return true if base is a frame index, which is known not to alias with
14350 /// anything but itself. Provides base object and offset as results.
14351 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
14352 const GlobalValue *&GV, const void *&CV) {
14353 // Assume it is a primitive operation.
14354 Base = Ptr; Offset = 0; GV = nullptr; CV = nullptr;
14356 // If it's an adding a simple constant then integrate the offset.
14357 if (Base.getOpcode() == ISD::ADD) {
14358 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
14359 Base = Base.getOperand(0);
14360 Offset += C->getZExtValue();
14364 // Return the underlying GlobalValue, and update the Offset. Return false
14365 // for GlobalAddressSDNode since the same GlobalAddress may be represented
14366 // by multiple nodes with different offsets.
14367 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
14368 GV = G->getGlobal();
14369 Offset += G->getOffset();
14373 // Return the underlying Constant value, and update the Offset. Return false
14374 // for ConstantSDNodes since the same constant pool entry may be represented
14375 // by multiple nodes with different offsets.
14376 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
14377 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
14378 : (const void *)C->getConstVal();
14379 Offset += C->getOffset();
14382 // If it's any of the following then it can't alias with anything but itself.
14383 return isa<FrameIndexSDNode>(Base);
14386 /// Return true if there is any possibility that the two addresses overlap.
14387 bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const {
14388 // If they are the same then they must be aliases.
14389 if (Op0->getBasePtr() == Op1->getBasePtr()) return true;
14391 // If they are both volatile then they cannot be reordered.
14392 if (Op0->isVolatile() && Op1->isVolatile()) return true;
14394 // If one operation reads from invariant memory, and the other may store, they
14395 // cannot alias. These should really be checking the equivalent of mayWrite,
14396 // but it only matters for memory nodes other than load /store.
14397 if (Op0->isInvariant() && Op1->writeMem())
14400 if (Op1->isInvariant() && Op0->writeMem())
14403 // Gather base node and offset information.
14404 SDValue Base1, Base2;
14405 int64_t Offset1, Offset2;
14406 const GlobalValue *GV1, *GV2;
14407 const void *CV1, *CV2;
14408 bool isFrameIndex1 = FindBaseOffset(Op0->getBasePtr(),
14409 Base1, Offset1, GV1, CV1);
14410 bool isFrameIndex2 = FindBaseOffset(Op1->getBasePtr(),
14411 Base2, Offset2, GV2, CV2);
14413 // If they have a same base address then check to see if they overlap.
14414 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
14415 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
14416 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
14418 // It is possible for different frame indices to alias each other, mostly
14419 // when tail call optimization reuses return address slots for arguments.
14420 // To catch this case, look up the actual index of frame indices to compute
14421 // the real alias relationship.
14422 if (isFrameIndex1 && isFrameIndex2) {
14423 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
14424 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
14425 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
14426 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
14427 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
14430 // Otherwise, if we know what the bases are, and they aren't identical, then
14431 // we know they cannot alias.
14432 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
14435 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
14436 // compared to the size and offset of the access, we may be able to prove they
14437 // do not alias. This check is conservative for now to catch cases created by
14438 // splitting vector types.
14439 if ((Op0->getOriginalAlignment() == Op1->getOriginalAlignment()) &&
14440 (Op0->getSrcValueOffset() != Op1->getSrcValueOffset()) &&
14441 (Op0->getMemoryVT().getSizeInBits() >> 3 ==
14442 Op1->getMemoryVT().getSizeInBits() >> 3) &&
14443 (Op0->getOriginalAlignment() > Op0->getMemoryVT().getSizeInBits()) >> 3) {
14444 int64_t OffAlign1 = Op0->getSrcValueOffset() % Op0->getOriginalAlignment();
14445 int64_t OffAlign2 = Op1->getSrcValueOffset() % Op1->getOriginalAlignment();
14447 // There is no overlap between these relatively aligned accesses of similar
14448 // size, return no alias.
14449 if ((OffAlign1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign2 ||
14450 (OffAlign2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign1)
14454 bool UseAA = CombinerGlobalAA.getNumOccurrences() > 0
14456 : DAG.getSubtarget().useAA();
14458 if (CombinerAAOnlyFunc.getNumOccurrences() &&
14459 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
14463 Op0->getMemOperand()->getValue() && Op1->getMemOperand()->getValue()) {
14464 // Use alias analysis information.
14465 int64_t MinOffset = std::min(Op0->getSrcValueOffset(),
14466 Op1->getSrcValueOffset());
14467 int64_t Overlap1 = (Op0->getMemoryVT().getSizeInBits() >> 3) +
14468 Op0->getSrcValueOffset() - MinOffset;
14469 int64_t Overlap2 = (Op1->getMemoryVT().getSizeInBits() >> 3) +
14470 Op1->getSrcValueOffset() - MinOffset;
14471 AliasResult AAResult =
14472 AA.alias(MemoryLocation(Op0->getMemOperand()->getValue(), Overlap1,
14473 UseTBAA ? Op0->getAAInfo() : AAMDNodes()),
14474 MemoryLocation(Op1->getMemOperand()->getValue(), Overlap2,
14475 UseTBAA ? Op1->getAAInfo() : AAMDNodes()));
14476 if (AAResult == NoAlias)
14480 // Otherwise we have to assume they alias.
14484 /// Walk up chain skipping non-aliasing memory nodes,
14485 /// looking for aliasing nodes and adding them to the Aliases vector.
14486 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
14487 SmallVectorImpl<SDValue> &Aliases) {
14488 SmallVector<SDValue, 8> Chains; // List of chains to visit.
14489 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
14491 // Get alias information for node.
14492 bool IsLoad = isa<LoadSDNode>(N) && !cast<LSBaseSDNode>(N)->isVolatile();
14495 Chains.push_back(OriginalChain);
14496 unsigned Depth = 0;
14498 // Look at each chain and determine if it is an alias. If so, add it to the
14499 // aliases list. If not, then continue up the chain looking for the next
14501 while (!Chains.empty()) {
14502 SDValue Chain = Chains.pop_back_val();
14504 // For TokenFactor nodes, look at each operand and only continue up the
14505 // chain until we reach the depth limit.
14507 // FIXME: The depth check could be made to return the last non-aliasing
14508 // chain we found before we hit a tokenfactor rather than the original
14510 if (Depth > TLI.getGatherAllAliasesMaxDepth()) {
14512 Aliases.push_back(OriginalChain);
14516 // Don't bother if we've been before.
14517 if (!Visited.insert(Chain.getNode()).second)
14520 switch (Chain.getOpcode()) {
14521 case ISD::EntryToken:
14522 // Entry token is ideal chain operand, but handled in FindBetterChain.
14527 // Get alias information for Chain.
14528 bool IsOpLoad = isa<LoadSDNode>(Chain.getNode()) &&
14529 !cast<LSBaseSDNode>(Chain.getNode())->isVolatile();
14531 // If chain is alias then stop here.
14532 if (!(IsLoad && IsOpLoad) &&
14533 isAlias(cast<LSBaseSDNode>(N), cast<LSBaseSDNode>(Chain.getNode()))) {
14534 Aliases.push_back(Chain);
14536 // Look further up the chain.
14537 Chains.push_back(Chain.getOperand(0));
14543 case ISD::TokenFactor:
14544 // We have to check each of the operands of the token factor for "small"
14545 // token factors, so we queue them up. Adding the operands to the queue
14546 // (stack) in reverse order maintains the original order and increases the
14547 // likelihood that getNode will find a matching token factor (CSE.)
14548 if (Chain.getNumOperands() > 16) {
14549 Aliases.push_back(Chain);
14552 for (unsigned n = Chain.getNumOperands(); n;)
14553 Chains.push_back(Chain.getOperand(--n));
14558 // For all other instructions we will just have to take what we can get.
14559 Aliases.push_back(Chain);
14564 // We need to be careful here to also search for aliases through the
14565 // value operand of a store, etc. Consider the following situation:
14567 // L1 = load Token1, %52
14568 // S1 = store Token1, L1, %51
14569 // L2 = load Token1, %52+8
14570 // S2 = store Token1, L2, %51+8
14571 // Token2 = Token(S1, S2)
14572 // L3 = load Token2, %53
14573 // S3 = store Token2, L3, %52
14574 // L4 = load Token2, %53+8
14575 // S4 = store Token2, L4, %52+8
14576 // If we search for aliases of S3 (which loads address %52), and we look
14577 // only through the chain, then we'll miss the trivial dependence on L1
14578 // (which also loads from %52). We then might change all loads and
14579 // stores to use Token1 as their chain operand, which could result in
14580 // copying %53 into %52 before copying %52 into %51 (which should
14583 // The problem is, however, that searching for such data dependencies
14584 // can become expensive, and the cost is not directly related to the
14585 // chain depth. Instead, we'll rule out such configurations here by
14586 // insisting that we've visited all chain users (except for users
14587 // of the original chain, which is not necessary). When doing this,
14588 // we need to look through nodes we don't care about (otherwise, things
14589 // like register copies will interfere with trivial cases).
14591 SmallVector<const SDNode *, 16> Worklist;
14592 for (const SDNode *N : Visited)
14593 if (N != OriginalChain.getNode())
14594 Worklist.push_back(N);
14596 while (!Worklist.empty()) {
14597 const SDNode *M = Worklist.pop_back_val();
14599 // We have already visited M, and want to make sure we've visited any uses
14600 // of M that we care about. For uses that we've not visisted, and don't
14601 // care about, queue them to the worklist.
14603 for (SDNode::use_iterator UI = M->use_begin(),
14604 UIE = M->use_end(); UI != UIE; ++UI)
14605 if (UI.getUse().getValueType() == MVT::Other &&
14606 Visited.insert(*UI).second) {
14607 if (isa<MemSDNode>(*UI)) {
14608 // We've not visited this use, and we care about it (it could have an
14609 // ordering dependency with the original node).
14611 Aliases.push_back(OriginalChain);
14615 // We've not visited this use, but we don't care about it. Mark it as
14616 // visited and enqueue it to the worklist.
14617 Worklist.push_back(*UI);
14622 /// Walk up chain skipping non-aliasing memory nodes, looking for a better chain
14623 /// (aliasing node.)
14624 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
14625 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
14627 // Accumulate all the aliases to this node.
14628 GatherAllAliases(N, OldChain, Aliases);
14630 // If no operands then chain to entry token.
14631 if (Aliases.size() == 0)
14632 return DAG.getEntryNode();
14634 // If a single operand then chain to it. We don't need to revisit it.
14635 if (Aliases.size() == 1)
14638 // Construct a custom tailored token factor.
14639 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Aliases);
14642 bool DAGCombiner::findBetterNeighborChains(StoreSDNode* St) {
14643 // This holds the base pointer, index, and the offset in bytes from the base
14645 BaseIndexOffset BasePtr = BaseIndexOffset::match(St->getBasePtr());
14647 // We must have a base and an offset.
14648 if (!BasePtr.Base.getNode())
14651 // Do not handle stores to undef base pointers.
14652 if (BasePtr.Base.getOpcode() == ISD::UNDEF)
14655 SmallVector<StoreSDNode *, 8> ChainedStores;
14656 ChainedStores.push_back(St);
14658 // Walk up the chain and look for nodes with offsets from the same
14659 // base pointer. Stop when reaching an instruction with a different kind
14660 // or instruction which has a different base pointer.
14661 StoreSDNode *Index = St;
14663 // If the chain has more than one use, then we can't reorder the mem ops.
14664 if (Index != St && !SDValue(Index, 0)->hasOneUse())
14667 if (Index->isVolatile() || Index->isIndexed())
14670 // Find the base pointer and offset for this memory node.
14671 BaseIndexOffset Ptr = BaseIndexOffset::match(Index->getBasePtr());
14673 // Check that the base pointer is the same as the original one.
14674 if (!Ptr.equalBaseIndex(BasePtr))
14677 // Find the next memory operand in the chain. If the next operand in the
14678 // chain is a store then move up and continue the scan with the next
14679 // memory operand. If the next operand is a load save it and use alias
14680 // information to check if it interferes with anything.
14681 SDNode *NextInChain = Index->getChain().getNode();
14683 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) {
14684 // We found a store node. Use it for the next iteration.
14685 ChainedStores.push_back(STn);
14688 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) {
14689 NextInChain = Ldn->getChain().getNode();
14698 bool MadeChange = false;
14699 SmallVector<std::pair<StoreSDNode *, SDValue>, 8> BetterChains;
14701 for (StoreSDNode *ChainedStore : ChainedStores) {
14702 SDValue Chain = ChainedStore->getChain();
14703 SDValue BetterChain = FindBetterChain(ChainedStore, Chain);
14705 if (Chain != BetterChain) {
14707 BetterChains.push_back(std::make_pair(ChainedStore, BetterChain));
14711 // Do all replacements after finding the replacements to make to avoid making
14712 // the chains more complicated by introducing new TokenFactors.
14713 for (auto Replacement : BetterChains)
14714 replaceStoreChain(Replacement.first, Replacement.second);
14719 /// This is the entry point for the file.
14720 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
14721 CodeGenOpt::Level OptLevel) {
14722 /// This is the main entry point to this class.
14723 DAGCombiner(*this, AA, OptLevel).Run(Level);