1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
40 STATISTIC(NodesCombined , "Number of dag nodes combined");
41 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
42 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
43 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
44 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
48 CombinerAA("combiner-alias-analysis", cl::Hidden,
49 cl::desc("Turn on alias analysis during testing"));
52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
53 cl::desc("Include global information in alias analysis"));
55 //------------------------------ DAGCombiner ---------------------------------//
59 const TargetLowering &TLI;
61 CodeGenOpt::Level OptLevel;
65 // Worklist of all of the nodes that need to be simplified.
67 // This has the semantics that when adding to the worklist,
68 // the item added must be next to be processed. It should
69 // also only appear once. The naive approach to this takes
72 // To reduce the insert/remove time to logarithmic, we use
73 // a set and a vector to maintain our worklist.
75 // The set contains the items on the worklist, but does not
76 // maintain the order they should be visited.
78 // The vector maintains the order nodes should be visited, but may
79 // contain duplicate or removed nodes. When choosing a node to
80 // visit, we pop off the order stack until we find an item that is
81 // also in the contents set. All operations are O(log N).
82 SmallPtrSet<SDNode*, 64> WorkListContents;
83 SmallVector<SDNode*, 64> WorkListOrder;
85 // AA - Used for DAG load/store alias analysis.
88 /// AddUsersToWorkList - When an instruction is simplified, add all users of
89 /// the instruction to the work lists because they might get more simplified
92 void AddUsersToWorkList(SDNode *N) {
93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
98 /// visit - call the node-specific routine that knows how to fold each
99 /// particular type of node.
100 SDValue visit(SDNode *N);
103 /// AddToWorkList - Add to the work list making sure its instance is at the
104 /// back (next to be processed.)
105 void AddToWorkList(SDNode *N) {
106 WorkListContents.insert(N);
107 WorkListOrder.push_back(N);
110 /// removeFromWorkList - remove all instances of N from the worklist.
112 void removeFromWorkList(SDNode *N) {
113 WorkListContents.erase(N);
116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
120 return CombineTo(N, &Res, 1, AddTo);
123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
125 SDValue To[] = { Res0, Res1 };
126 return CombineTo(N, To, 2, AddTo);
129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
133 /// SimplifyDemandedBits - Check the specified integer node value to see if
134 /// it can be simplified or if things it uses can be simplified by bit
135 /// propagation. If so, return true.
136 bool SimplifyDemandedBits(SDValue Op) {
137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
138 APInt Demanded = APInt::getAllOnesValue(BitWidth);
139 return SimplifyDemandedBits(Op, Demanded);
142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
144 bool CombineToPreIndexedLoadStore(SDNode *N);
145 bool CombineToPostIndexedLoadStore(SDNode *N);
147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
151 SDValue PromoteIntBinOp(SDValue Op);
152 SDValue PromoteIntShiftOp(SDValue Op);
153 SDValue PromoteExtend(SDValue Op);
154 bool PromoteLoad(SDValue Op);
156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
158 ISD::NodeType ExtType);
160 /// combine - call the node-specific routine that knows how to fold each
161 /// particular type of node. If that doesn't do anything, try the
162 /// target-specific DAG combines.
163 SDValue combine(SDNode *N);
165 // Visitation implementation - Implement dag node combining for different
166 // node types. The semantics are as follows:
168 // SDValue.getNode() == 0 - No change was made
169 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
170 // otherwise - N should be replaced by the returned Operand.
172 SDValue visitTokenFactor(SDNode *N);
173 SDValue visitMERGE_VALUES(SDNode *N);
174 SDValue visitADD(SDNode *N);
175 SDValue visitSUB(SDNode *N);
176 SDValue visitADDC(SDNode *N);
177 SDValue visitSUBC(SDNode *N);
178 SDValue visitADDE(SDNode *N);
179 SDValue visitSUBE(SDNode *N);
180 SDValue visitMUL(SDNode *N);
181 SDValue visitSDIV(SDNode *N);
182 SDValue visitUDIV(SDNode *N);
183 SDValue visitSREM(SDNode *N);
184 SDValue visitUREM(SDNode *N);
185 SDValue visitMULHU(SDNode *N);
186 SDValue visitMULHS(SDNode *N);
187 SDValue visitSMUL_LOHI(SDNode *N);
188 SDValue visitUMUL_LOHI(SDNode *N);
189 SDValue visitSMULO(SDNode *N);
190 SDValue visitUMULO(SDNode *N);
191 SDValue visitSDIVREM(SDNode *N);
192 SDValue visitUDIVREM(SDNode *N);
193 SDValue visitAND(SDNode *N);
194 SDValue visitOR(SDNode *N);
195 SDValue visitXOR(SDNode *N);
196 SDValue SimplifyVBinOp(SDNode *N);
197 SDValue visitSHL(SDNode *N);
198 SDValue visitSRA(SDNode *N);
199 SDValue visitSRL(SDNode *N);
200 SDValue visitCTLZ(SDNode *N);
201 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
202 SDValue visitCTTZ(SDNode *N);
203 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
204 SDValue visitCTPOP(SDNode *N);
205 SDValue visitSELECT(SDNode *N);
206 SDValue visitSELECT_CC(SDNode *N);
207 SDValue visitSETCC(SDNode *N);
208 SDValue visitSIGN_EXTEND(SDNode *N);
209 SDValue visitZERO_EXTEND(SDNode *N);
210 SDValue visitANY_EXTEND(SDNode *N);
211 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
212 SDValue visitTRUNCATE(SDNode *N);
213 SDValue visitBITCAST(SDNode *N);
214 SDValue visitBUILD_PAIR(SDNode *N);
215 SDValue visitFADD(SDNode *N);
216 SDValue visitFSUB(SDNode *N);
217 SDValue visitFMUL(SDNode *N);
218 SDValue visitFMA(SDNode *N);
219 SDValue visitFDIV(SDNode *N);
220 SDValue visitFREM(SDNode *N);
221 SDValue visitFCOPYSIGN(SDNode *N);
222 SDValue visitSINT_TO_FP(SDNode *N);
223 SDValue visitUINT_TO_FP(SDNode *N);
224 SDValue visitFP_TO_SINT(SDNode *N);
225 SDValue visitFP_TO_UINT(SDNode *N);
226 SDValue visitFP_ROUND(SDNode *N);
227 SDValue visitFP_ROUND_INREG(SDNode *N);
228 SDValue visitFP_EXTEND(SDNode *N);
229 SDValue visitFNEG(SDNode *N);
230 SDValue visitFABS(SDNode *N);
231 SDValue visitBRCOND(SDNode *N);
232 SDValue visitBR_CC(SDNode *N);
233 SDValue visitLOAD(SDNode *N);
234 SDValue visitSTORE(SDNode *N);
235 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
236 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
237 SDValue visitBUILD_VECTOR(SDNode *N);
238 SDValue visitCONCAT_VECTORS(SDNode *N);
239 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
240 SDValue visitVECTOR_SHUFFLE(SDNode *N);
241 SDValue visitMEMBARRIER(SDNode *N);
243 SDValue XformToShuffleWithZero(SDNode *N);
244 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
246 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
248 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
249 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
250 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
251 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
252 SDValue N3, ISD::CondCode CC,
253 bool NotExtCompare = false);
254 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
255 DebugLoc DL, bool foldBooleans = true);
256 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
258 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
259 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
260 SDValue BuildSDIV(SDNode *N);
261 SDValue BuildUDIV(SDNode *N);
262 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
263 bool DemandHighBits = true);
264 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
265 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
266 SDValue ReduceLoadWidth(SDNode *N);
267 SDValue ReduceLoadOpStoreWidth(SDNode *N);
268 SDValue TransformFPLoadStorePair(SDNode *N);
270 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
272 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
273 /// looking for aliasing nodes and adding them to the Aliases vector.
274 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
275 SmallVector<SDValue, 8> &Aliases);
277 /// isAlias - Return true if there is any possibility that the two addresses
279 bool isAlias(SDValue Ptr1, int64_t Size1,
280 const Value *SrcValue1, int SrcValueOffset1,
281 unsigned SrcValueAlign1,
282 const MDNode *TBAAInfo1,
283 SDValue Ptr2, int64_t Size2,
284 const Value *SrcValue2, int SrcValueOffset2,
285 unsigned SrcValueAlign2,
286 const MDNode *TBAAInfo2) const;
288 /// FindAliasInfo - Extracts the relevant alias information from the memory
289 /// node. Returns true if the operand was a load.
290 bool FindAliasInfo(SDNode *N,
291 SDValue &Ptr, int64_t &Size,
292 const Value *&SrcValue, int &SrcValueOffset,
293 unsigned &SrcValueAlignment,
294 const MDNode *&TBAAInfo) const;
296 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
297 /// looking for a better chain (aliasing node.)
298 SDValue FindBetterChain(SDNode *N, SDValue Chain);
301 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
302 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
303 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
305 /// Run - runs the dag combiner on all nodes in the work list
306 void Run(CombineLevel AtLevel);
308 SelectionDAG &getDAG() const { return DAG; }
310 /// getShiftAmountTy - Returns a type large enough to hold any valid
311 /// shift amount - before type legalization these can be huge.
312 EVT getShiftAmountTy(EVT LHSTy) {
313 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
316 /// isTypeLegal - This method returns true if we are running before type
317 /// legalization or if the specified VT is legal.
318 bool isTypeLegal(const EVT &VT) {
319 if (!LegalTypes) return true;
320 return TLI.isTypeLegal(VT);
327 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
328 /// nodes from the worklist.
329 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
332 explicit WorkListRemover(DAGCombiner &dc)
333 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
335 virtual void NodeDeleted(SDNode *N, SDNode *E) {
336 DC.removeFromWorkList(N);
341 //===----------------------------------------------------------------------===//
342 // TargetLowering::DAGCombinerInfo implementation
343 //===----------------------------------------------------------------------===//
345 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
346 ((DAGCombiner*)DC)->AddToWorkList(N);
349 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
350 ((DAGCombiner*)DC)->removeFromWorkList(N);
353 SDValue TargetLowering::DAGCombinerInfo::
354 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
355 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
358 SDValue TargetLowering::DAGCombinerInfo::
359 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
360 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
364 SDValue TargetLowering::DAGCombinerInfo::
365 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
366 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
369 void TargetLowering::DAGCombinerInfo::
370 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
371 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
374 //===----------------------------------------------------------------------===//
376 //===----------------------------------------------------------------------===//
378 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
379 /// specified expression for the same cost as the expression itself, or 2 if we
380 /// can compute the negated form more cheaply than the expression itself.
381 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
382 const TargetLowering &TLI,
383 const TargetOptions *Options,
384 unsigned Depth = 0) {
385 // No compile time optimizations on this type.
386 if (Op.getValueType() == MVT::ppcf128)
389 // fneg is removable even if it has multiple uses.
390 if (Op.getOpcode() == ISD::FNEG) return 2;
392 // Don't allow anything with multiple uses.
393 if (!Op.hasOneUse()) return 0;
395 // Don't recurse exponentially.
396 if (Depth > 6) return 0;
398 switch (Op.getOpcode()) {
399 default: return false;
400 case ISD::ConstantFP:
401 // Don't invert constant FP values after legalize. The negated constant
402 // isn't necessarily legal.
403 return LegalOperations ? 0 : 1;
405 // FIXME: determine better conditions for this xform.
406 if (!Options->UnsafeFPMath) return 0;
408 // After operation legalization, it might not be legal to create new FSUBs.
409 if (LegalOperations &&
410 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
413 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
414 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
417 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
418 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
421 // We can't turn -(A-B) into B-A when we honor signed zeros.
422 if (!Options->UnsafeFPMath) return 0;
424 // fold (fneg (fsub A, B)) -> (fsub B, A)
429 if (Options->HonorSignDependentRoundingFPMath()) return 0;
431 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
432 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
436 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
442 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
447 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
448 /// returns the newly negated expression.
449 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
450 bool LegalOperations, unsigned Depth = 0) {
451 // fneg is removable even if it has multiple uses.
452 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
454 // Don't allow anything with multiple uses.
455 assert(Op.hasOneUse() && "Unknown reuse!");
457 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
458 switch (Op.getOpcode()) {
459 default: llvm_unreachable("Unknown code");
460 case ISD::ConstantFP: {
461 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
463 return DAG.getConstantFP(V, Op.getValueType());
466 // FIXME: determine better conditions for this xform.
467 assert(DAG.getTarget().Options.UnsafeFPMath);
469 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
470 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
471 DAG.getTargetLoweringInfo(),
472 &DAG.getTarget().Options, Depth+1))
473 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
474 GetNegatedExpression(Op.getOperand(0), DAG,
475 LegalOperations, Depth+1),
477 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
478 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
479 GetNegatedExpression(Op.getOperand(1), DAG,
480 LegalOperations, Depth+1),
483 // We can't turn -(A-B) into B-A when we honor signed zeros.
484 assert(DAG.getTarget().Options.UnsafeFPMath);
486 // fold (fneg (fsub 0, B)) -> B
487 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
488 if (N0CFP->getValueAPF().isZero())
489 return Op.getOperand(1);
491 // fold (fneg (fsub A, B)) -> (fsub B, A)
492 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
493 Op.getOperand(1), Op.getOperand(0));
497 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath());
499 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
500 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
501 DAG.getTargetLoweringInfo(),
502 &DAG.getTarget().Options, Depth+1))
503 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
504 GetNegatedExpression(Op.getOperand(0), DAG,
505 LegalOperations, Depth+1),
508 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
509 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
511 GetNegatedExpression(Op.getOperand(1), DAG,
512 LegalOperations, Depth+1));
516 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
517 GetNegatedExpression(Op.getOperand(0), DAG,
518 LegalOperations, Depth+1));
520 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
521 GetNegatedExpression(Op.getOperand(0), DAG,
522 LegalOperations, Depth+1),
528 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
529 // that selects between the values 1 and 0, making it equivalent to a setcc.
530 // Also, set the incoming LHS, RHS, and CC references to the appropriate
531 // nodes based on the type of node we are checking. This simplifies life a
532 // bit for the callers.
533 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
535 if (N.getOpcode() == ISD::SETCC) {
536 LHS = N.getOperand(0);
537 RHS = N.getOperand(1);
538 CC = N.getOperand(2);
541 if (N.getOpcode() == ISD::SELECT_CC &&
542 N.getOperand(2).getOpcode() == ISD::Constant &&
543 N.getOperand(3).getOpcode() == ISD::Constant &&
544 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
545 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
546 LHS = N.getOperand(0);
547 RHS = N.getOperand(1);
548 CC = N.getOperand(4);
554 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
555 // one use. If this is true, it allows the users to invert the operation for
556 // free when it is profitable to do so.
557 static bool isOneUseSetCC(SDValue N) {
559 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
564 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
565 SDValue N0, SDValue N1) {
566 EVT VT = N0.getValueType();
567 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
568 if (isa<ConstantSDNode>(N1)) {
569 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
571 DAG.FoldConstantArithmetic(Opc, VT,
572 cast<ConstantSDNode>(N0.getOperand(1)),
573 cast<ConstantSDNode>(N1));
574 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
576 if (N0.hasOneUse()) {
577 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
578 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
579 N0.getOperand(0), N1);
580 AddToWorkList(OpNode.getNode());
581 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
585 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
586 if (isa<ConstantSDNode>(N0)) {
587 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
589 DAG.FoldConstantArithmetic(Opc, VT,
590 cast<ConstantSDNode>(N1.getOperand(1)),
591 cast<ConstantSDNode>(N0));
592 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
594 if (N1.hasOneUse()) {
595 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
596 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
597 N1.getOperand(0), N0);
598 AddToWorkList(OpNode.getNode());
599 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
606 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
608 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
610 DEBUG(dbgs() << "\nReplacing.1 ";
612 dbgs() << "\nWith: ";
613 To[0].getNode()->dump(&DAG);
614 dbgs() << " and " << NumTo-1 << " other values\n";
615 for (unsigned i = 0, e = NumTo; i != e; ++i)
616 assert((!To[i].getNode() ||
617 N->getValueType(i) == To[i].getValueType()) &&
618 "Cannot combine value to value of different type!"));
619 WorkListRemover DeadNodes(*this);
620 DAG.ReplaceAllUsesWith(N, To);
622 // Push the new nodes and any users onto the worklist
623 for (unsigned i = 0, e = NumTo; i != e; ++i) {
624 if (To[i].getNode()) {
625 AddToWorkList(To[i].getNode());
626 AddUsersToWorkList(To[i].getNode());
631 // Finally, if the node is now dead, remove it from the graph. The node
632 // may not be dead if the replacement process recursively simplified to
633 // something else needing this node.
634 if (N->use_empty()) {
635 // Nodes can be reintroduced into the worklist. Make sure we do not
636 // process a node that has been replaced.
637 removeFromWorkList(N);
639 // Finally, since the node is now dead, remove it from the graph.
642 return SDValue(N, 0);
646 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
647 // Replace all uses. If any nodes become isomorphic to other nodes and
648 // are deleted, make sure to remove them from our worklist.
649 WorkListRemover DeadNodes(*this);
650 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
652 // Push the new node and any (possibly new) users onto the worklist.
653 AddToWorkList(TLO.New.getNode());
654 AddUsersToWorkList(TLO.New.getNode());
656 // Finally, if the node is now dead, remove it from the graph. The node
657 // may not be dead if the replacement process recursively simplified to
658 // something else needing this node.
659 if (TLO.Old.getNode()->use_empty()) {
660 removeFromWorkList(TLO.Old.getNode());
662 // If the operands of this node are only used by the node, they will now
663 // be dead. Make sure to visit them first to delete dead nodes early.
664 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
665 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
666 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
668 DAG.DeleteNode(TLO.Old.getNode());
672 /// SimplifyDemandedBits - Check the specified integer node value to see if
673 /// it can be simplified or if things it uses can be simplified by bit
674 /// propagation. If so, return true.
675 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
676 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
677 APInt KnownZero, KnownOne;
678 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
682 AddToWorkList(Op.getNode());
684 // Replace the old value with the new one.
686 DEBUG(dbgs() << "\nReplacing.2 ";
687 TLO.Old.getNode()->dump(&DAG);
688 dbgs() << "\nWith: ";
689 TLO.New.getNode()->dump(&DAG);
692 CommitTargetLoweringOpt(TLO);
696 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
697 DebugLoc dl = Load->getDebugLoc();
698 EVT VT = Load->getValueType(0);
699 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
701 DEBUG(dbgs() << "\nReplacing.9 ";
703 dbgs() << "\nWith: ";
704 Trunc.getNode()->dump(&DAG);
706 WorkListRemover DeadNodes(*this);
707 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
708 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
709 removeFromWorkList(Load);
710 DAG.DeleteNode(Load);
711 AddToWorkList(Trunc.getNode());
714 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
716 DebugLoc dl = Op.getDebugLoc();
717 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
718 EVT MemVT = LD->getMemoryVT();
719 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
720 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
722 : LD->getExtensionType();
724 return DAG.getExtLoad(ExtType, dl, PVT,
725 LD->getChain(), LD->getBasePtr(),
726 LD->getPointerInfo(),
727 MemVT, LD->isVolatile(),
728 LD->isNonTemporal(), LD->getAlignment());
731 unsigned Opc = Op.getOpcode();
734 case ISD::AssertSext:
735 return DAG.getNode(ISD::AssertSext, dl, PVT,
736 SExtPromoteOperand(Op.getOperand(0), PVT),
738 case ISD::AssertZext:
739 return DAG.getNode(ISD::AssertZext, dl, PVT,
740 ZExtPromoteOperand(Op.getOperand(0), PVT),
742 case ISD::Constant: {
744 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
745 return DAG.getNode(ExtOpc, dl, PVT, Op);
749 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
751 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
754 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
755 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
757 EVT OldVT = Op.getValueType();
758 DebugLoc dl = Op.getDebugLoc();
759 bool Replace = false;
760 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
761 if (NewOp.getNode() == 0)
763 AddToWorkList(NewOp.getNode());
766 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
767 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
768 DAG.getValueType(OldVT));
771 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
772 EVT OldVT = Op.getValueType();
773 DebugLoc dl = Op.getDebugLoc();
774 bool Replace = false;
775 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
776 if (NewOp.getNode() == 0)
778 AddToWorkList(NewOp.getNode());
781 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
782 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
785 /// PromoteIntBinOp - Promote the specified integer binary operation if the
786 /// target indicates it is beneficial. e.g. On x86, it's usually better to
787 /// promote i16 operations to i32 since i16 instructions are longer.
788 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
789 if (!LegalOperations)
792 EVT VT = Op.getValueType();
793 if (VT.isVector() || !VT.isInteger())
796 // If operation type is 'undesirable', e.g. i16 on x86, consider
798 unsigned Opc = Op.getOpcode();
799 if (TLI.isTypeDesirableForOp(Opc, VT))
803 // Consult target whether it is a good idea to promote this operation and
804 // what's the right type to promote it to.
805 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
806 assert(PVT != VT && "Don't know what type to promote to!");
808 bool Replace0 = false;
809 SDValue N0 = Op.getOperand(0);
810 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
811 if (NN0.getNode() == 0)
814 bool Replace1 = false;
815 SDValue N1 = Op.getOperand(1);
820 NN1 = PromoteOperand(N1, PVT, Replace1);
821 if (NN1.getNode() == 0)
825 AddToWorkList(NN0.getNode());
827 AddToWorkList(NN1.getNode());
830 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
832 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
834 DEBUG(dbgs() << "\nPromoting ";
835 Op.getNode()->dump(&DAG));
836 DebugLoc dl = Op.getDebugLoc();
837 return DAG.getNode(ISD::TRUNCATE, dl, VT,
838 DAG.getNode(Opc, dl, PVT, NN0, NN1));
843 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
844 /// target indicates it is beneficial. e.g. On x86, it's usually better to
845 /// promote i16 operations to i32 since i16 instructions are longer.
846 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
847 if (!LegalOperations)
850 EVT VT = Op.getValueType();
851 if (VT.isVector() || !VT.isInteger())
854 // If operation type is 'undesirable', e.g. i16 on x86, consider
856 unsigned Opc = Op.getOpcode();
857 if (TLI.isTypeDesirableForOp(Opc, VT))
861 // Consult target whether it is a good idea to promote this operation and
862 // what's the right type to promote it to.
863 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
864 assert(PVT != VT && "Don't know what type to promote to!");
866 bool Replace = false;
867 SDValue N0 = Op.getOperand(0);
869 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
870 else if (Opc == ISD::SRL)
871 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
873 N0 = PromoteOperand(N0, PVT, Replace);
874 if (N0.getNode() == 0)
877 AddToWorkList(N0.getNode());
879 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
881 DEBUG(dbgs() << "\nPromoting ";
882 Op.getNode()->dump(&DAG));
883 DebugLoc dl = Op.getDebugLoc();
884 return DAG.getNode(ISD::TRUNCATE, dl, VT,
885 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
890 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
891 if (!LegalOperations)
894 EVT VT = Op.getValueType();
895 if (VT.isVector() || !VT.isInteger())
898 // If operation type is 'undesirable', e.g. i16 on x86, consider
900 unsigned Opc = Op.getOpcode();
901 if (TLI.isTypeDesirableForOp(Opc, VT))
905 // Consult target whether it is a good idea to promote this operation and
906 // what's the right type to promote it to.
907 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
908 assert(PVT != VT && "Don't know what type to promote to!");
909 // fold (aext (aext x)) -> (aext x)
910 // fold (aext (zext x)) -> (zext x)
911 // fold (aext (sext x)) -> (sext x)
912 DEBUG(dbgs() << "\nPromoting ";
913 Op.getNode()->dump(&DAG));
914 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
919 bool DAGCombiner::PromoteLoad(SDValue Op) {
920 if (!LegalOperations)
923 EVT VT = Op.getValueType();
924 if (VT.isVector() || !VT.isInteger())
927 // If operation type is 'undesirable', e.g. i16 on x86, consider
929 unsigned Opc = Op.getOpcode();
930 if (TLI.isTypeDesirableForOp(Opc, VT))
934 // Consult target whether it is a good idea to promote this operation and
935 // what's the right type to promote it to.
936 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
937 assert(PVT != VT && "Don't know what type to promote to!");
939 DebugLoc dl = Op.getDebugLoc();
940 SDNode *N = Op.getNode();
941 LoadSDNode *LD = cast<LoadSDNode>(N);
942 EVT MemVT = LD->getMemoryVT();
943 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
944 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
946 : LD->getExtensionType();
947 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
948 LD->getChain(), LD->getBasePtr(),
949 LD->getPointerInfo(),
950 MemVT, LD->isVolatile(),
951 LD->isNonTemporal(), LD->getAlignment());
952 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
954 DEBUG(dbgs() << "\nPromoting ";
957 Result.getNode()->dump(&DAG);
959 WorkListRemover DeadNodes(*this);
960 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
961 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
962 removeFromWorkList(N);
964 AddToWorkList(Result.getNode());
971 //===----------------------------------------------------------------------===//
972 // Main DAG Combiner implementation
973 //===----------------------------------------------------------------------===//
975 void DAGCombiner::Run(CombineLevel AtLevel) {
976 // set the instance variables, so that the various visit routines may use it.
978 LegalOperations = Level >= AfterLegalizeVectorOps;
979 LegalTypes = Level >= AfterLegalizeTypes;
981 // Add all the dag nodes to the worklist.
982 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
983 E = DAG.allnodes_end(); I != E; ++I)
986 // Create a dummy node (which is not added to allnodes), that adds a reference
987 // to the root node, preventing it from being deleted, and tracking any
988 // changes of the root.
989 HandleSDNode Dummy(DAG.getRoot());
991 // The root of the dag may dangle to deleted nodes until the dag combiner is
992 // done. Set it to null to avoid confusion.
993 DAG.setRoot(SDValue());
995 // while the worklist isn't empty, find a node and
996 // try and combine it.
997 while (!WorkListContents.empty()) {
999 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates.
1000 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the
1001 // worklist *should* contain, and check the node we want to visit is should
1002 // actually be visited.
1004 N = WorkListOrder.pop_back_val();
1005 } while (!WorkListContents.erase(N));
1007 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1008 // N is deleted from the DAG, since they too may now be dead or may have a
1009 // reduced number of uses, allowing other xforms.
1010 if (N->use_empty() && N != &Dummy) {
1011 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1012 AddToWorkList(N->getOperand(i).getNode());
1018 SDValue RV = combine(N);
1020 if (RV.getNode() == 0)
1025 // If we get back the same node we passed in, rather than a new node or
1026 // zero, we know that the node must have defined multiple values and
1027 // CombineTo was used. Since CombineTo takes care of the worklist
1028 // mechanics for us, we have no work to do in this case.
1029 if (RV.getNode() == N)
1032 assert(N->getOpcode() != ISD::DELETED_NODE &&
1033 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1034 "Node was deleted but visit returned new node!");
1036 DEBUG(dbgs() << "\nReplacing.3 ";
1038 dbgs() << "\nWith: ";
1039 RV.getNode()->dump(&DAG);
1042 // Transfer debug value.
1043 DAG.TransferDbgValues(SDValue(N, 0), RV);
1044 WorkListRemover DeadNodes(*this);
1045 if (N->getNumValues() == RV.getNode()->getNumValues())
1046 DAG.ReplaceAllUsesWith(N, RV.getNode());
1048 assert(N->getValueType(0) == RV.getValueType() &&
1049 N->getNumValues() == 1 && "Type mismatch");
1051 DAG.ReplaceAllUsesWith(N, &OpV);
1054 // Push the new node and any users onto the worklist
1055 AddToWorkList(RV.getNode());
1056 AddUsersToWorkList(RV.getNode());
1058 // Add any uses of the old node to the worklist in case this node is the
1059 // last one that uses them. They may become dead after this node is
1061 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1062 AddToWorkList(N->getOperand(i).getNode());
1064 // Finally, if the node is now dead, remove it from the graph. The node
1065 // may not be dead if the replacement process recursively simplified to
1066 // something else needing this node.
1067 if (N->use_empty()) {
1068 // Nodes can be reintroduced into the worklist. Make sure we do not
1069 // process a node that has been replaced.
1070 removeFromWorkList(N);
1072 // Finally, since the node is now dead, remove it from the graph.
1077 // If the root changed (e.g. it was a dead load, update the root).
1078 DAG.setRoot(Dummy.getValue());
1079 DAG.RemoveDeadNodes();
1082 SDValue DAGCombiner::visit(SDNode *N) {
1083 switch (N->getOpcode()) {
1085 case ISD::TokenFactor: return visitTokenFactor(N);
1086 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1087 case ISD::ADD: return visitADD(N);
1088 case ISD::SUB: return visitSUB(N);
1089 case ISD::ADDC: return visitADDC(N);
1090 case ISD::SUBC: return visitSUBC(N);
1091 case ISD::ADDE: return visitADDE(N);
1092 case ISD::SUBE: return visitSUBE(N);
1093 case ISD::MUL: return visitMUL(N);
1094 case ISD::SDIV: return visitSDIV(N);
1095 case ISD::UDIV: return visitUDIV(N);
1096 case ISD::SREM: return visitSREM(N);
1097 case ISD::UREM: return visitUREM(N);
1098 case ISD::MULHU: return visitMULHU(N);
1099 case ISD::MULHS: return visitMULHS(N);
1100 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1101 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1102 case ISD::SMULO: return visitSMULO(N);
1103 case ISD::UMULO: return visitUMULO(N);
1104 case ISD::SDIVREM: return visitSDIVREM(N);
1105 case ISD::UDIVREM: return visitUDIVREM(N);
1106 case ISD::AND: return visitAND(N);
1107 case ISD::OR: return visitOR(N);
1108 case ISD::XOR: return visitXOR(N);
1109 case ISD::SHL: return visitSHL(N);
1110 case ISD::SRA: return visitSRA(N);
1111 case ISD::SRL: return visitSRL(N);
1112 case ISD::CTLZ: return visitCTLZ(N);
1113 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1114 case ISD::CTTZ: return visitCTTZ(N);
1115 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1116 case ISD::CTPOP: return visitCTPOP(N);
1117 case ISD::SELECT: return visitSELECT(N);
1118 case ISD::SELECT_CC: return visitSELECT_CC(N);
1119 case ISD::SETCC: return visitSETCC(N);
1120 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1121 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1122 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1123 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1124 case ISD::TRUNCATE: return visitTRUNCATE(N);
1125 case ISD::BITCAST: return visitBITCAST(N);
1126 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1127 case ISD::FADD: return visitFADD(N);
1128 case ISD::FSUB: return visitFSUB(N);
1129 case ISD::FMUL: return visitFMUL(N);
1130 case ISD::FMA: return visitFMA(N);
1131 case ISD::FDIV: return visitFDIV(N);
1132 case ISD::FREM: return visitFREM(N);
1133 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1134 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1135 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1136 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1137 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1138 case ISD::FP_ROUND: return visitFP_ROUND(N);
1139 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1140 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1141 case ISD::FNEG: return visitFNEG(N);
1142 case ISD::FABS: return visitFABS(N);
1143 case ISD::BRCOND: return visitBRCOND(N);
1144 case ISD::BR_CC: return visitBR_CC(N);
1145 case ISD::LOAD: return visitLOAD(N);
1146 case ISD::STORE: return visitSTORE(N);
1147 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1148 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1149 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1150 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1151 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1152 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1153 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1158 SDValue DAGCombiner::combine(SDNode *N) {
1159 SDValue RV = visit(N);
1161 // If nothing happened, try a target-specific DAG combine.
1162 if (RV.getNode() == 0) {
1163 assert(N->getOpcode() != ISD::DELETED_NODE &&
1164 "Node was deleted but visit returned NULL!");
1166 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1167 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1169 // Expose the DAG combiner to the target combiner impls.
1170 TargetLowering::DAGCombinerInfo
1171 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1173 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1177 // If nothing happened still, try promoting the operation.
1178 if (RV.getNode() == 0) {
1179 switch (N->getOpcode()) {
1187 RV = PromoteIntBinOp(SDValue(N, 0));
1192 RV = PromoteIntShiftOp(SDValue(N, 0));
1194 case ISD::SIGN_EXTEND:
1195 case ISD::ZERO_EXTEND:
1196 case ISD::ANY_EXTEND:
1197 RV = PromoteExtend(SDValue(N, 0));
1200 if (PromoteLoad(SDValue(N, 0)))
1206 // If N is a commutative binary node, try commuting it to enable more
1208 if (RV.getNode() == 0 &&
1209 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1210 N->getNumValues() == 1) {
1211 SDValue N0 = N->getOperand(0);
1212 SDValue N1 = N->getOperand(1);
1214 // Constant operands are canonicalized to RHS.
1215 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1216 SDValue Ops[] = { N1, N0 };
1217 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1220 return SDValue(CSENode, 0);
1227 /// getInputChainForNode - Given a node, return its input chain if it has one,
1228 /// otherwise return a null sd operand.
1229 static SDValue getInputChainForNode(SDNode *N) {
1230 if (unsigned NumOps = N->getNumOperands()) {
1231 if (N->getOperand(0).getValueType() == MVT::Other)
1232 return N->getOperand(0);
1233 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1234 return N->getOperand(NumOps-1);
1235 for (unsigned i = 1; i < NumOps-1; ++i)
1236 if (N->getOperand(i).getValueType() == MVT::Other)
1237 return N->getOperand(i);
1242 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1243 // If N has two operands, where one has an input chain equal to the other,
1244 // the 'other' chain is redundant.
1245 if (N->getNumOperands() == 2) {
1246 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1247 return N->getOperand(0);
1248 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1249 return N->getOperand(1);
1252 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1253 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1254 SmallPtrSet<SDNode*, 16> SeenOps;
1255 bool Changed = false; // If we should replace this token factor.
1257 // Start out with this token factor.
1260 // Iterate through token factors. The TFs grows when new token factors are
1262 for (unsigned i = 0; i < TFs.size(); ++i) {
1263 SDNode *TF = TFs[i];
1265 // Check each of the operands.
1266 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1267 SDValue Op = TF->getOperand(i);
1269 switch (Op.getOpcode()) {
1270 case ISD::EntryToken:
1271 // Entry tokens don't need to be added to the list. They are
1276 case ISD::TokenFactor:
1277 if (Op.hasOneUse() &&
1278 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1279 // Queue up for processing.
1280 TFs.push_back(Op.getNode());
1281 // Clean up in case the token factor is removed.
1282 AddToWorkList(Op.getNode());
1289 // Only add if it isn't already in the list.
1290 if (SeenOps.insert(Op.getNode()))
1301 // If we've change things around then replace token factor.
1304 // The entry token is the only possible outcome.
1305 Result = DAG.getEntryNode();
1307 // New and improved token factor.
1308 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1309 MVT::Other, &Ops[0], Ops.size());
1312 // Don't add users to work list.
1313 return CombineTo(N, Result, false);
1319 /// MERGE_VALUES can always be eliminated.
1320 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1321 WorkListRemover DeadNodes(*this);
1322 // Replacing results may cause a different MERGE_VALUES to suddenly
1323 // be CSE'd with N, and carry its uses with it. Iterate until no
1324 // uses remain, to ensure that the node can be safely deleted.
1325 // First add the users of this node to the work list so that they
1326 // can be tried again once they have new operands.
1327 AddUsersToWorkList(N);
1329 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1330 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1331 } while (!N->use_empty());
1332 removeFromWorkList(N);
1334 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1338 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1339 SelectionDAG &DAG) {
1340 EVT VT = N0.getValueType();
1341 SDValue N00 = N0.getOperand(0);
1342 SDValue N01 = N0.getOperand(1);
1343 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1345 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1346 isa<ConstantSDNode>(N00.getOperand(1))) {
1347 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1348 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1349 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1350 N00.getOperand(0), N01),
1351 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1352 N00.getOperand(1), N01));
1353 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1359 SDValue DAGCombiner::visitADD(SDNode *N) {
1360 SDValue N0 = N->getOperand(0);
1361 SDValue N1 = N->getOperand(1);
1362 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1363 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1364 EVT VT = N0.getValueType();
1367 if (VT.isVector()) {
1368 SDValue FoldedVOp = SimplifyVBinOp(N);
1369 if (FoldedVOp.getNode()) return FoldedVOp;
1372 // fold (add x, undef) -> undef
1373 if (N0.getOpcode() == ISD::UNDEF)
1375 if (N1.getOpcode() == ISD::UNDEF)
1377 // fold (add c1, c2) -> c1+c2
1379 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1380 // canonicalize constant to RHS
1382 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1383 // fold (add x, 0) -> x
1384 if (N1C && N1C->isNullValue())
1386 // fold (add Sym, c) -> Sym+c
1387 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1388 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1389 GA->getOpcode() == ISD::GlobalAddress)
1390 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1392 (uint64_t)N1C->getSExtValue());
1393 // fold ((c1-A)+c2) -> (c1+c2)-A
1394 if (N1C && N0.getOpcode() == ISD::SUB)
1395 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1396 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1397 DAG.getConstant(N1C->getAPIntValue()+
1398 N0C->getAPIntValue(), VT),
1401 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1402 if (RADD.getNode() != 0)
1404 // fold ((0-A) + B) -> B-A
1405 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1406 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1407 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1408 // fold (A + (0-B)) -> A-B
1409 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1410 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1411 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1412 // fold (A+(B-A)) -> B
1413 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1414 return N1.getOperand(0);
1415 // fold ((B-A)+A) -> B
1416 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1417 return N0.getOperand(0);
1418 // fold (A+(B-(A+C))) to (B-C)
1419 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1420 N0 == N1.getOperand(1).getOperand(0))
1421 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1422 N1.getOperand(1).getOperand(1));
1423 // fold (A+(B-(C+A))) to (B-C)
1424 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1425 N0 == N1.getOperand(1).getOperand(1))
1426 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1427 N1.getOperand(1).getOperand(0));
1428 // fold (A+((B-A)+or-C)) to (B+or-C)
1429 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1430 N1.getOperand(0).getOpcode() == ISD::SUB &&
1431 N0 == N1.getOperand(0).getOperand(1))
1432 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1433 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1435 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1436 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1437 SDValue N00 = N0.getOperand(0);
1438 SDValue N01 = N0.getOperand(1);
1439 SDValue N10 = N1.getOperand(0);
1440 SDValue N11 = N1.getOperand(1);
1442 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1443 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1444 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1445 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1448 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1449 return SDValue(N, 0);
1451 // fold (a+b) -> (a|b) iff a and b share no bits.
1452 if (VT.isInteger() && !VT.isVector()) {
1453 APInt LHSZero, LHSOne;
1454 APInt RHSZero, RHSOne;
1455 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1457 if (LHSZero.getBoolValue()) {
1458 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1460 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1461 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1462 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1463 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1467 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1468 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1469 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1470 if (Result.getNode()) return Result;
1472 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1473 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1474 if (Result.getNode()) return Result;
1477 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1478 if (N1.getOpcode() == ISD::SHL &&
1479 N1.getOperand(0).getOpcode() == ISD::SUB)
1480 if (ConstantSDNode *C =
1481 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1482 if (C->getAPIntValue() == 0)
1483 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1484 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1485 N1.getOperand(0).getOperand(1),
1487 if (N0.getOpcode() == ISD::SHL &&
1488 N0.getOperand(0).getOpcode() == ISD::SUB)
1489 if (ConstantSDNode *C =
1490 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1491 if (C->getAPIntValue() == 0)
1492 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1493 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1494 N0.getOperand(0).getOperand(1),
1497 if (N1.getOpcode() == ISD::AND) {
1498 SDValue AndOp0 = N1.getOperand(0);
1499 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1500 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1501 unsigned DestBits = VT.getScalarType().getSizeInBits();
1503 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1504 // and similar xforms where the inner op is either ~0 or 0.
1505 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1506 DebugLoc DL = N->getDebugLoc();
1507 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1511 // add (sext i1), X -> sub X, (zext i1)
1512 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1513 N0.getOperand(0).getValueType() == MVT::i1 &&
1514 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1515 DebugLoc DL = N->getDebugLoc();
1516 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1517 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1523 SDValue DAGCombiner::visitADDC(SDNode *N) {
1524 SDValue N0 = N->getOperand(0);
1525 SDValue N1 = N->getOperand(1);
1526 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1527 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1528 EVT VT = N0.getValueType();
1530 // If the flag result is dead, turn this into an ADD.
1531 if (!N->hasAnyUseOfValue(1))
1532 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1),
1533 DAG.getNode(ISD::CARRY_FALSE,
1534 N->getDebugLoc(), MVT::Glue));
1536 // canonicalize constant to RHS.
1538 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1540 // fold (addc x, 0) -> x + no carry out
1541 if (N1C && N1C->isNullValue())
1542 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1543 N->getDebugLoc(), MVT::Glue));
1545 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1546 APInt LHSZero, LHSOne;
1547 APInt RHSZero, RHSOne;
1548 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1550 if (LHSZero.getBoolValue()) {
1551 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1553 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1554 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1555 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1556 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1557 DAG.getNode(ISD::CARRY_FALSE,
1558 N->getDebugLoc(), MVT::Glue));
1564 SDValue DAGCombiner::visitADDE(SDNode *N) {
1565 SDValue N0 = N->getOperand(0);
1566 SDValue N1 = N->getOperand(1);
1567 SDValue CarryIn = N->getOperand(2);
1568 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1569 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1571 // canonicalize constant to RHS
1573 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1576 // fold (adde x, y, false) -> (addc x, y)
1577 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1578 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1);
1583 // Since it may not be valid to emit a fold to zero for vector initializers
1584 // check if we can before folding.
1585 static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1586 SelectionDAG &DAG, bool LegalOperations) {
1587 if (!VT.isVector()) {
1588 return DAG.getConstant(0, VT);
1590 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1591 // Produce a vector of zeros.
1592 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1593 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1594 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1595 &Ops[0], Ops.size());
1600 SDValue DAGCombiner::visitSUB(SDNode *N) {
1601 SDValue N0 = N->getOperand(0);
1602 SDValue N1 = N->getOperand(1);
1603 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1604 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1605 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1606 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1607 EVT VT = N0.getValueType();
1610 if (VT.isVector()) {
1611 SDValue FoldedVOp = SimplifyVBinOp(N);
1612 if (FoldedVOp.getNode()) return FoldedVOp;
1615 // fold (sub x, x) -> 0
1616 // FIXME: Refactor this and xor and other similar operations together.
1618 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1619 // fold (sub c1, c2) -> c1-c2
1621 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1622 // fold (sub x, c) -> (add x, -c)
1624 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1625 DAG.getConstant(-N1C->getAPIntValue(), VT));
1626 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1627 if (N0C && N0C->isAllOnesValue())
1628 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1629 // fold A-(A-B) -> B
1630 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1631 return N1.getOperand(1);
1632 // fold (A+B)-A -> B
1633 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1634 return N0.getOperand(1);
1635 // fold (A+B)-B -> A
1636 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1637 return N0.getOperand(0);
1638 // fold C2-(A+C1) -> (C2-C1)-A
1639 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1640 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT);
1641 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
1644 // fold ((A+(B+or-C))-B) -> A+or-C
1645 if (N0.getOpcode() == ISD::ADD &&
1646 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1647 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1648 N0.getOperand(1).getOperand(0) == N1)
1649 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1650 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1651 // fold ((A+(C+B))-B) -> A+C
1652 if (N0.getOpcode() == ISD::ADD &&
1653 N0.getOperand(1).getOpcode() == ISD::ADD &&
1654 N0.getOperand(1).getOperand(1) == N1)
1655 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1656 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1657 // fold ((A-(B-C))-C) -> A-B
1658 if (N0.getOpcode() == ISD::SUB &&
1659 N0.getOperand(1).getOpcode() == ISD::SUB &&
1660 N0.getOperand(1).getOperand(1) == N1)
1661 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1662 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1664 // If either operand of a sub is undef, the result is undef
1665 if (N0.getOpcode() == ISD::UNDEF)
1667 if (N1.getOpcode() == ISD::UNDEF)
1670 // If the relocation model supports it, consider symbol offsets.
1671 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1672 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1673 // fold (sub Sym, c) -> Sym-c
1674 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1675 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1677 (uint64_t)N1C->getSExtValue());
1678 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1679 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1680 if (GA->getGlobal() == GB->getGlobal())
1681 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1688 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1689 SDValue N0 = N->getOperand(0);
1690 SDValue N1 = N->getOperand(1);
1691 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1692 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1693 EVT VT = N0.getValueType();
1695 // If the flag result is dead, turn this into an SUB.
1696 if (!N->hasAnyUseOfValue(1))
1697 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1),
1698 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1701 // fold (subc x, x) -> 0 + no borrow
1703 return CombineTo(N, DAG.getConstant(0, VT),
1704 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1707 // fold (subc x, 0) -> x + no borrow
1708 if (N1C && N1C->isNullValue())
1709 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1712 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1713 if (N0C && N0C->isAllOnesValue())
1714 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0),
1715 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1721 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1722 SDValue N0 = N->getOperand(0);
1723 SDValue N1 = N->getOperand(1);
1724 SDValue CarryIn = N->getOperand(2);
1726 // fold (sube x, y, false) -> (subc x, y)
1727 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1728 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1);
1733 SDValue DAGCombiner::visitMUL(SDNode *N) {
1734 SDValue N0 = N->getOperand(0);
1735 SDValue N1 = N->getOperand(1);
1736 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1737 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1738 EVT VT = N0.getValueType();
1741 if (VT.isVector()) {
1742 SDValue FoldedVOp = SimplifyVBinOp(N);
1743 if (FoldedVOp.getNode()) return FoldedVOp;
1746 // fold (mul x, undef) -> 0
1747 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1748 return DAG.getConstant(0, VT);
1749 // fold (mul c1, c2) -> c1*c2
1751 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1752 // canonicalize constant to RHS
1754 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1755 // fold (mul x, 0) -> 0
1756 if (N1C && N1C->isNullValue())
1758 // fold (mul x, -1) -> 0-x
1759 if (N1C && N1C->isAllOnesValue())
1760 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1761 DAG.getConstant(0, VT), N0);
1762 // fold (mul x, (1 << c)) -> x << c
1763 if (N1C && N1C->getAPIntValue().isPowerOf2())
1764 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1765 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1766 getShiftAmountTy(N0.getValueType())));
1767 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1768 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1769 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1770 // FIXME: If the input is something that is easily negated (e.g. a
1771 // single-use add), we should put the negate there.
1772 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1773 DAG.getConstant(0, VT),
1774 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1775 DAG.getConstant(Log2Val,
1776 getShiftAmountTy(N0.getValueType()))));
1778 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1779 if (N1C && N0.getOpcode() == ISD::SHL &&
1780 isa<ConstantSDNode>(N0.getOperand(1))) {
1781 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1782 N1, N0.getOperand(1));
1783 AddToWorkList(C3.getNode());
1784 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1785 N0.getOperand(0), C3);
1788 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1791 SDValue Sh(0,0), Y(0,0);
1792 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1793 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1794 N0.getNode()->hasOneUse()) {
1796 } else if (N1.getOpcode() == ISD::SHL &&
1797 isa<ConstantSDNode>(N1.getOperand(1)) &&
1798 N1.getNode()->hasOneUse()) {
1803 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1804 Sh.getOperand(0), Y);
1805 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1806 Mul, Sh.getOperand(1));
1810 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1811 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1812 isa<ConstantSDNode>(N0.getOperand(1)))
1813 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1814 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1815 N0.getOperand(0), N1),
1816 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1817 N0.getOperand(1), N1));
1820 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1821 if (RMUL.getNode() != 0)
1827 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1828 SDValue N0 = N->getOperand(0);
1829 SDValue N1 = N->getOperand(1);
1830 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1831 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1832 EVT VT = N->getValueType(0);
1835 if (VT.isVector()) {
1836 SDValue FoldedVOp = SimplifyVBinOp(N);
1837 if (FoldedVOp.getNode()) return FoldedVOp;
1840 // fold (sdiv c1, c2) -> c1/c2
1841 if (N0C && N1C && !N1C->isNullValue())
1842 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1843 // fold (sdiv X, 1) -> X
1844 if (N1C && N1C->getAPIntValue() == 1LL)
1846 // fold (sdiv X, -1) -> 0-X
1847 if (N1C && N1C->isAllOnesValue())
1848 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1849 DAG.getConstant(0, VT), N0);
1850 // If we know the sign bits of both operands are zero, strength reduce to a
1851 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1852 if (!VT.isVector()) {
1853 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1854 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1857 // fold (sdiv X, pow2) -> simple ops after legalize
1858 if (N1C && !N1C->isNullValue() &&
1859 (N1C->getAPIntValue().isPowerOf2() ||
1860 (-N1C->getAPIntValue()).isPowerOf2())) {
1861 // If dividing by powers of two is cheap, then don't perform the following
1863 if (TLI.isPow2DivCheap())
1866 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
1868 // Splat the sign bit into the register
1869 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1870 DAG.getConstant(VT.getSizeInBits()-1,
1871 getShiftAmountTy(N0.getValueType())));
1872 AddToWorkList(SGN.getNode());
1874 // Add (N0 < 0) ? abs2 - 1 : 0;
1875 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1876 DAG.getConstant(VT.getSizeInBits() - lg2,
1877 getShiftAmountTy(SGN.getValueType())));
1878 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1879 AddToWorkList(SRL.getNode());
1880 AddToWorkList(ADD.getNode()); // Divide by pow2
1881 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1882 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1884 // If we're dividing by a positive value, we're done. Otherwise, we must
1885 // negate the result.
1886 if (N1C->getAPIntValue().isNonNegative())
1889 AddToWorkList(SRA.getNode());
1890 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1891 DAG.getConstant(0, VT), SRA);
1894 // if integer divide is expensive and we satisfy the requirements, emit an
1895 // alternate sequence.
1896 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1897 SDValue Op = BuildSDIV(N);
1898 if (Op.getNode()) return Op;
1902 if (N0.getOpcode() == ISD::UNDEF)
1903 return DAG.getConstant(0, VT);
1904 // X / undef -> undef
1905 if (N1.getOpcode() == ISD::UNDEF)
1911 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1912 SDValue N0 = N->getOperand(0);
1913 SDValue N1 = N->getOperand(1);
1914 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1915 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1916 EVT VT = N->getValueType(0);
1919 if (VT.isVector()) {
1920 SDValue FoldedVOp = SimplifyVBinOp(N);
1921 if (FoldedVOp.getNode()) return FoldedVOp;
1924 // fold (udiv c1, c2) -> c1/c2
1925 if (N0C && N1C && !N1C->isNullValue())
1926 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1927 // fold (udiv x, (1 << c)) -> x >>u c
1928 if (N1C && N1C->getAPIntValue().isPowerOf2())
1929 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1930 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1931 getShiftAmountTy(N0.getValueType())));
1932 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1933 if (N1.getOpcode() == ISD::SHL) {
1934 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1935 if (SHC->getAPIntValue().isPowerOf2()) {
1936 EVT ADDVT = N1.getOperand(1).getValueType();
1937 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1939 DAG.getConstant(SHC->getAPIntValue()
1942 AddToWorkList(Add.getNode());
1943 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1947 // fold (udiv x, c) -> alternate
1948 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1949 SDValue Op = BuildUDIV(N);
1950 if (Op.getNode()) return Op;
1954 if (N0.getOpcode() == ISD::UNDEF)
1955 return DAG.getConstant(0, VT);
1956 // X / undef -> undef
1957 if (N1.getOpcode() == ISD::UNDEF)
1963 SDValue DAGCombiner::visitSREM(SDNode *N) {
1964 SDValue N0 = N->getOperand(0);
1965 SDValue N1 = N->getOperand(1);
1966 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1967 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1968 EVT VT = N->getValueType(0);
1970 // fold (srem c1, c2) -> c1%c2
1971 if (N0C && N1C && !N1C->isNullValue())
1972 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1973 // If we know the sign bits of both operands are zero, strength reduce to a
1974 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1975 if (!VT.isVector()) {
1976 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1977 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1980 // If X/C can be simplified by the division-by-constant logic, lower
1981 // X%C to the equivalent of X-X/C*C.
1982 if (N1C && !N1C->isNullValue()) {
1983 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1984 AddToWorkList(Div.getNode());
1985 SDValue OptimizedDiv = combine(Div.getNode());
1986 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1987 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1989 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1990 AddToWorkList(Mul.getNode());
1996 if (N0.getOpcode() == ISD::UNDEF)
1997 return DAG.getConstant(0, VT);
1998 // X % undef -> undef
1999 if (N1.getOpcode() == ISD::UNDEF)
2005 SDValue DAGCombiner::visitUREM(SDNode *N) {
2006 SDValue N0 = N->getOperand(0);
2007 SDValue N1 = N->getOperand(1);
2008 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2009 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2010 EVT VT = N->getValueType(0);
2012 // fold (urem c1, c2) -> c1%c2
2013 if (N0C && N1C && !N1C->isNullValue())
2014 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2015 // fold (urem x, pow2) -> (and x, pow2-1)
2016 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2017 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
2018 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2019 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2020 if (N1.getOpcode() == ISD::SHL) {
2021 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2022 if (SHC->getAPIntValue().isPowerOf2()) {
2024 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
2025 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2027 AddToWorkList(Add.getNode());
2028 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
2033 // If X/C can be simplified by the division-by-constant logic, lower
2034 // X%C to the equivalent of X-X/C*C.
2035 if (N1C && !N1C->isNullValue()) {
2036 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
2037 AddToWorkList(Div.getNode());
2038 SDValue OptimizedDiv = combine(Div.getNode());
2039 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2040 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2042 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2043 AddToWorkList(Mul.getNode());
2049 if (N0.getOpcode() == ISD::UNDEF)
2050 return DAG.getConstant(0, VT);
2051 // X % undef -> undef
2052 if (N1.getOpcode() == ISD::UNDEF)
2058 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2059 SDValue N0 = N->getOperand(0);
2060 SDValue N1 = N->getOperand(1);
2061 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2062 EVT VT = N->getValueType(0);
2063 DebugLoc DL = N->getDebugLoc();
2065 // fold (mulhs x, 0) -> 0
2066 if (N1C && N1C->isNullValue())
2068 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2069 if (N1C && N1C->getAPIntValue() == 1)
2070 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
2071 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2072 getShiftAmountTy(N0.getValueType())));
2073 // fold (mulhs x, undef) -> 0
2074 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2075 return DAG.getConstant(0, VT);
2077 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2079 if (VT.isSimple() && !VT.isVector()) {
2080 MVT Simple = VT.getSimpleVT();
2081 unsigned SimpleSize = Simple.getSizeInBits();
2082 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2083 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2084 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2085 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2086 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2087 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2088 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2089 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2096 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2097 SDValue N0 = N->getOperand(0);
2098 SDValue N1 = N->getOperand(1);
2099 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2100 EVT VT = N->getValueType(0);
2101 DebugLoc DL = N->getDebugLoc();
2103 // fold (mulhu x, 0) -> 0
2104 if (N1C && N1C->isNullValue())
2106 // fold (mulhu x, 1) -> 0
2107 if (N1C && N1C->getAPIntValue() == 1)
2108 return DAG.getConstant(0, N0.getValueType());
2109 // fold (mulhu x, undef) -> 0
2110 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2111 return DAG.getConstant(0, VT);
2113 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2115 if (VT.isSimple() && !VT.isVector()) {
2116 MVT Simple = VT.getSimpleVT();
2117 unsigned SimpleSize = Simple.getSizeInBits();
2118 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2119 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2120 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2121 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2122 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2123 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2124 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2125 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2132 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2133 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2134 /// that are being performed. Return true if a simplification was made.
2136 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2138 // If the high half is not needed, just compute the low half.
2139 bool HiExists = N->hasAnyUseOfValue(1);
2141 (!LegalOperations ||
2142 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2143 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2144 N->op_begin(), N->getNumOperands());
2145 return CombineTo(N, Res, Res);
2148 // If the low half is not needed, just compute the high half.
2149 bool LoExists = N->hasAnyUseOfValue(0);
2151 (!LegalOperations ||
2152 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2153 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2154 N->op_begin(), N->getNumOperands());
2155 return CombineTo(N, Res, Res);
2158 // If both halves are used, return as it is.
2159 if (LoExists && HiExists)
2162 // If the two computed results can be simplified separately, separate them.
2164 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2165 N->op_begin(), N->getNumOperands());
2166 AddToWorkList(Lo.getNode());
2167 SDValue LoOpt = combine(Lo.getNode());
2168 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2169 (!LegalOperations ||
2170 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2171 return CombineTo(N, LoOpt, LoOpt);
2175 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2176 N->op_begin(), N->getNumOperands());
2177 AddToWorkList(Hi.getNode());
2178 SDValue HiOpt = combine(Hi.getNode());
2179 if (HiOpt.getNode() && HiOpt != Hi &&
2180 (!LegalOperations ||
2181 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2182 return CombineTo(N, HiOpt, HiOpt);
2188 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2189 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2190 if (Res.getNode()) return Res;
2192 EVT VT = N->getValueType(0);
2193 DebugLoc DL = N->getDebugLoc();
2195 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2197 if (VT.isSimple() && !VT.isVector()) {
2198 MVT Simple = VT.getSimpleVT();
2199 unsigned SimpleSize = Simple.getSizeInBits();
2200 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2201 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2202 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2203 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2204 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2205 // Compute the high part as N1.
2206 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2207 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2208 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2209 // Compute the low part as N0.
2210 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2211 return CombineTo(N, Lo, Hi);
2218 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2219 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2220 if (Res.getNode()) return Res;
2222 EVT VT = N->getValueType(0);
2223 DebugLoc DL = N->getDebugLoc();
2225 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2227 if (VT.isSimple() && !VT.isVector()) {
2228 MVT Simple = VT.getSimpleVT();
2229 unsigned SimpleSize = Simple.getSizeInBits();
2230 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2231 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2232 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2233 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2234 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2235 // Compute the high part as N1.
2236 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2237 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2238 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2239 // Compute the low part as N0.
2240 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2241 return CombineTo(N, Lo, Hi);
2248 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2249 // (smulo x, 2) -> (saddo x, x)
2250 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2251 if (C2->getAPIntValue() == 2)
2252 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2253 N->getOperand(0), N->getOperand(0));
2258 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2259 // (umulo x, 2) -> (uaddo x, x)
2260 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2261 if (C2->getAPIntValue() == 2)
2262 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2263 N->getOperand(0), N->getOperand(0));
2268 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2269 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2270 if (Res.getNode()) return Res;
2275 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2276 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2277 if (Res.getNode()) return Res;
2282 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2283 /// two operands of the same opcode, try to simplify it.
2284 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2285 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2286 EVT VT = N0.getValueType();
2287 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2289 // Bail early if none of these transforms apply.
2290 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2292 // For each of OP in AND/OR/XOR:
2293 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2294 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2295 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2296 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2298 // do not sink logical op inside of a vector extend, since it may combine
2300 EVT Op0VT = N0.getOperand(0).getValueType();
2301 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2302 N0.getOpcode() == ISD::SIGN_EXTEND ||
2303 // Avoid infinite looping with PromoteIntBinOp.
2304 (N0.getOpcode() == ISD::ANY_EXTEND &&
2305 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2306 (N0.getOpcode() == ISD::TRUNCATE &&
2307 (!TLI.isZExtFree(VT, Op0VT) ||
2308 !TLI.isTruncateFree(Op0VT, VT)) &&
2309 TLI.isTypeLegal(Op0VT))) &&
2311 Op0VT == N1.getOperand(0).getValueType() &&
2312 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2313 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2314 N0.getOperand(0).getValueType(),
2315 N0.getOperand(0), N1.getOperand(0));
2316 AddToWorkList(ORNode.getNode());
2317 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2320 // For each of OP in SHL/SRL/SRA/AND...
2321 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2322 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2323 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2324 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2325 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2326 N0.getOperand(1) == N1.getOperand(1)) {
2327 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2328 N0.getOperand(0).getValueType(),
2329 N0.getOperand(0), N1.getOperand(0));
2330 AddToWorkList(ORNode.getNode());
2331 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2332 ORNode, N0.getOperand(1));
2335 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2336 // Only perform this optimization after type legalization and before
2337 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2338 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2339 // we don't want to undo this promotion.
2340 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2342 if ((N0.getOpcode() == ISD::BITCAST || N0.getOpcode() == ISD::SCALAR_TO_VECTOR)
2343 && Level == AfterLegalizeTypes) {
2344 SDValue In0 = N0.getOperand(0);
2345 SDValue In1 = N1.getOperand(0);
2346 EVT In0Ty = In0.getValueType();
2347 EVT In1Ty = In1.getValueType();
2348 // If both incoming values are integers, and the original types are the same.
2349 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2350 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), In0Ty, In0, In1);
2351 SDValue BC = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, Op);
2352 AddToWorkList(Op.getNode());
2357 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2358 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2359 // If both shuffles use the same mask, and both shuffle within a single
2360 // vector, then it is worthwhile to move the swizzle after the operation.
2361 // The type-legalizer generates this pattern when loading illegal
2362 // vector types from memory. In many cases this allows additional shuffle
2364 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
2365 N0.getOperand(1).getOpcode() == ISD::UNDEF &&
2366 N1.getOperand(1).getOpcode() == ISD::UNDEF) {
2367 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2368 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2370 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() &&
2371 "Inputs to shuffles are not the same type");
2373 unsigned NumElts = VT.getVectorNumElements();
2375 // Check that both shuffles use the same mask. The masks are known to be of
2376 // the same length because the result vector type is the same.
2377 bool SameMask = true;
2378 for (unsigned i = 0; i != NumElts; ++i) {
2379 int Idx0 = SVN0->getMaskElt(i);
2380 int Idx1 = SVN1->getMaskElt(i);
2388 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT,
2389 N0.getOperand(0), N1.getOperand(0));
2390 AddToWorkList(Op.getNode());
2391 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op,
2392 DAG.getUNDEF(VT), &SVN0->getMask()[0]);
2399 SDValue DAGCombiner::visitAND(SDNode *N) {
2400 SDValue N0 = N->getOperand(0);
2401 SDValue N1 = N->getOperand(1);
2402 SDValue LL, LR, RL, RR, CC0, CC1;
2403 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2404 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2405 EVT VT = N1.getValueType();
2406 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2409 if (VT.isVector()) {
2410 SDValue FoldedVOp = SimplifyVBinOp(N);
2411 if (FoldedVOp.getNode()) return FoldedVOp;
2414 // fold (and x, undef) -> 0
2415 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2416 return DAG.getConstant(0, VT);
2417 // fold (and c1, c2) -> c1&c2
2419 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2420 // canonicalize constant to RHS
2422 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2423 // fold (and x, -1) -> x
2424 if (N1C && N1C->isAllOnesValue())
2426 // if (and x, c) is known to be zero, return 0
2427 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2428 APInt::getAllOnesValue(BitWidth)))
2429 return DAG.getConstant(0, VT);
2431 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2432 if (RAND.getNode() != 0)
2434 // fold (and (or x, C), D) -> D if (C & D) == D
2435 if (N1C && N0.getOpcode() == ISD::OR)
2436 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2437 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2439 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2440 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2441 SDValue N0Op0 = N0.getOperand(0);
2442 APInt Mask = ~N1C->getAPIntValue();
2443 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2444 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2445 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2446 N0.getValueType(), N0Op0);
2448 // Replace uses of the AND with uses of the Zero extend node.
2451 // We actually want to replace all uses of the any_extend with the
2452 // zero_extend, to avoid duplicating things. This will later cause this
2453 // AND to be folded.
2454 CombineTo(N0.getNode(), Zext);
2455 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2458 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2459 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2460 // already be zero by virtue of the width of the base type of the load.
2462 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2464 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2465 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2466 N0.getOpcode() == ISD::LOAD) {
2467 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2468 N0 : N0.getOperand(0) );
2470 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2471 // This can be a pure constant or a vector splat, in which case we treat the
2472 // vector as a scalar and use the splat value.
2473 APInt Constant = APInt::getNullValue(1);
2474 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2475 Constant = C->getAPIntValue();
2476 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2477 APInt SplatValue, SplatUndef;
2478 unsigned SplatBitSize;
2480 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2481 SplatBitSize, HasAnyUndefs);
2483 // Undef bits can contribute to a possible optimisation if set, so
2485 SplatValue |= SplatUndef;
2487 // The splat value may be something like "0x00FFFFFF", which means 0 for
2488 // the first vector value and FF for the rest, repeating. We need a mask
2489 // that will apply equally to all members of the vector, so AND all the
2490 // lanes of the constant together.
2491 EVT VT = Vector->getValueType(0);
2492 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2493 Constant = APInt::getAllOnesValue(BitWidth);
2494 for (unsigned i = 0, n = VT.getVectorNumElements(); i < n; ++i)
2495 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2499 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2500 // actually legal and isn't going to get expanded, else this is a false
2502 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2503 Load->getMemoryVT());
2505 // Resize the constant to the same size as the original memory access before
2506 // extension. If it is still the AllOnesValue then this AND is completely
2509 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2512 switch (Load->getExtensionType()) {
2513 default: B = false; break;
2514 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2516 case ISD::NON_EXTLOAD: B = true; break;
2519 if (B && Constant.isAllOnesValue()) {
2520 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2521 // preserve semantics once we get rid of the AND.
2522 SDValue NewLoad(Load, 0);
2523 if (Load->getExtensionType() == ISD::EXTLOAD) {
2524 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2525 Load->getValueType(0), Load->getDebugLoc(),
2526 Load->getChain(), Load->getBasePtr(),
2527 Load->getOffset(), Load->getMemoryVT(),
2528 Load->getMemOperand());
2529 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2530 if (Load->getNumValues() == 3) {
2531 // PRE/POST_INC loads have 3 values.
2532 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
2533 NewLoad.getValue(2) };
2534 CombineTo(Load, To, 3, true);
2536 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2540 // Fold the AND away, taking care not to fold to the old load node if we
2542 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2544 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2547 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2548 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2549 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2550 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2552 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2553 LL.getValueType().isInteger()) {
2554 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2555 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2556 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2557 LR.getValueType(), LL, RL);
2558 AddToWorkList(ORNode.getNode());
2559 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2561 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2562 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2563 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2564 LR.getValueType(), LL, RL);
2565 AddToWorkList(ANDNode.getNode());
2566 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2568 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2569 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2570 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2571 LR.getValueType(), LL, RL);
2572 AddToWorkList(ORNode.getNode());
2573 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2576 // canonicalize equivalent to ll == rl
2577 if (LL == RR && LR == RL) {
2578 Op1 = ISD::getSetCCSwappedOperands(Op1);
2581 if (LL == RL && LR == RR) {
2582 bool isInteger = LL.getValueType().isInteger();
2583 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2584 if (Result != ISD::SETCC_INVALID &&
2585 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2586 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2591 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2592 if (N0.getOpcode() == N1.getOpcode()) {
2593 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2594 if (Tmp.getNode()) return Tmp;
2597 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2598 // fold (and (sra)) -> (and (srl)) when possible.
2599 if (!VT.isVector() &&
2600 SimplifyDemandedBits(SDValue(N, 0)))
2601 return SDValue(N, 0);
2603 // fold (zext_inreg (extload x)) -> (zextload x)
2604 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2605 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2606 EVT MemVT = LN0->getMemoryVT();
2607 // If we zero all the possible extended bits, then we can turn this into
2608 // a zextload if we are running before legalize or the operation is legal.
2609 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2610 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2611 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2612 ((!LegalOperations && !LN0->isVolatile()) ||
2613 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2614 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2615 LN0->getChain(), LN0->getBasePtr(),
2616 LN0->getPointerInfo(), MemVT,
2617 LN0->isVolatile(), LN0->isNonTemporal(),
2618 LN0->getAlignment());
2620 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2621 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2624 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2625 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2627 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2628 EVT MemVT = LN0->getMemoryVT();
2629 // If we zero all the possible extended bits, then we can turn this into
2630 // a zextload if we are running before legalize or the operation is legal.
2631 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2632 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2633 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2634 ((!LegalOperations && !LN0->isVolatile()) ||
2635 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2636 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2638 LN0->getBasePtr(), LN0->getPointerInfo(),
2640 LN0->isVolatile(), LN0->isNonTemporal(),
2641 LN0->getAlignment());
2643 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2644 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2648 // fold (and (load x), 255) -> (zextload x, i8)
2649 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2650 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2651 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2652 (N0.getOpcode() == ISD::ANY_EXTEND &&
2653 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2654 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2655 LoadSDNode *LN0 = HasAnyExt
2656 ? cast<LoadSDNode>(N0.getOperand(0))
2657 : cast<LoadSDNode>(N0);
2658 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2659 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2660 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2661 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2662 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2663 EVT LoadedVT = LN0->getMemoryVT();
2665 if (ExtVT == LoadedVT &&
2666 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2667 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2670 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2671 LN0->getChain(), LN0->getBasePtr(),
2672 LN0->getPointerInfo(),
2673 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2674 LN0->getAlignment());
2676 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2677 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2680 // Do not change the width of a volatile load.
2681 // Do not generate loads of non-round integer types since these can
2682 // be expensive (and would be wrong if the type is not byte sized).
2683 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2684 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2685 EVT PtrType = LN0->getOperand(1).getValueType();
2687 unsigned Alignment = LN0->getAlignment();
2688 SDValue NewPtr = LN0->getBasePtr();
2690 // For big endian targets, we need to add an offset to the pointer
2691 // to load the correct bytes. For little endian systems, we merely
2692 // need to read fewer bytes from the same pointer.
2693 if (TLI.isBigEndian()) {
2694 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2695 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2696 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2697 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2698 NewPtr, DAG.getConstant(PtrOff, PtrType));
2699 Alignment = MinAlign(Alignment, PtrOff);
2702 AddToWorkList(NewPtr.getNode());
2704 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2706 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2707 LN0->getChain(), NewPtr,
2708 LN0->getPointerInfo(),
2709 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2712 CombineTo(LN0, Load, Load.getValue(1));
2713 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2719 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2720 VT.getSizeInBits() <= 64) {
2721 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2722 APInt ADDC = ADDI->getAPIntValue();
2723 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2724 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
2725 // immediate for an add, but it is legal if its top c2 bits are set,
2726 // transform the ADD so the immediate doesn't need to be materialized
2728 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
2729 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
2730 SRLI->getZExtValue());
2731 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
2733 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2735 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
2736 N0.getOperand(0), DAG.getConstant(ADDC, VT));
2737 CombineTo(N0.getNode(), NewAdd);
2738 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2750 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2752 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2753 bool DemandHighBits) {
2754 if (!LegalOperations)
2757 EVT VT = N->getValueType(0);
2758 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2760 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2763 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2764 bool LookPassAnd0 = false;
2765 bool LookPassAnd1 = false;
2766 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2768 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2770 if (N0.getOpcode() == ISD::AND) {
2771 if (!N0.getNode()->hasOneUse())
2773 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2774 if (!N01C || N01C->getZExtValue() != 0xFF00)
2776 N0 = N0.getOperand(0);
2777 LookPassAnd0 = true;
2780 if (N1.getOpcode() == ISD::AND) {
2781 if (!N1.getNode()->hasOneUse())
2783 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2784 if (!N11C || N11C->getZExtValue() != 0xFF)
2786 N1 = N1.getOperand(0);
2787 LookPassAnd1 = true;
2790 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2792 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2794 if (!N0.getNode()->hasOneUse() ||
2795 !N1.getNode()->hasOneUse())
2798 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2799 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2802 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2805 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2806 SDValue N00 = N0->getOperand(0);
2807 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2808 if (!N00.getNode()->hasOneUse())
2810 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2811 if (!N001C || N001C->getZExtValue() != 0xFF)
2813 N00 = N00.getOperand(0);
2814 LookPassAnd0 = true;
2817 SDValue N10 = N1->getOperand(0);
2818 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2819 if (!N10.getNode()->hasOneUse())
2821 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2822 if (!N101C || N101C->getZExtValue() != 0xFF00)
2824 N10 = N10.getOperand(0);
2825 LookPassAnd1 = true;
2831 // Make sure everything beyond the low halfword is zero since the SRL 16
2832 // will clear the top bits.
2833 unsigned OpSizeInBits = VT.getSizeInBits();
2834 if (DemandHighBits && OpSizeInBits > 16 &&
2835 (!LookPassAnd0 || !LookPassAnd1) &&
2836 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
2839 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
2840 if (OpSizeInBits > 16)
2841 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2842 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2846 /// isBSwapHWordElement - Return true if the specified node is an element
2847 /// that makes up a 32-bit packed halfword byteswap. i.e.
2848 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2849 static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
2850 if (!N.getNode()->hasOneUse())
2853 unsigned Opc = N.getOpcode();
2854 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2857 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2862 switch (N1C->getZExtValue()) {
2865 case 0xFF: Num = 0; break;
2866 case 0xFF00: Num = 1; break;
2867 case 0xFF0000: Num = 2; break;
2868 case 0xFF000000: Num = 3; break;
2871 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
2872 SDValue N0 = N.getOperand(0);
2873 if (Opc == ISD::AND) {
2874 if (Num == 0 || Num == 2) {
2876 // (x >> 8) & 0xff0000
2877 if (N0.getOpcode() != ISD::SRL)
2879 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2880 if (!C || C->getZExtValue() != 8)
2883 // (x << 8) & 0xff00
2884 // (x << 8) & 0xff000000
2885 if (N0.getOpcode() != ISD::SHL)
2887 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2888 if (!C || C->getZExtValue() != 8)
2891 } else if (Opc == ISD::SHL) {
2893 // (x & 0xff0000) << 8
2894 if (Num != 0 && Num != 2)
2896 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2897 if (!C || C->getZExtValue() != 8)
2899 } else { // Opc == ISD::SRL
2900 // (x & 0xff00) >> 8
2901 // (x & 0xff000000) >> 8
2902 if (Num != 1 && Num != 3)
2904 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2905 if (!C || C->getZExtValue() != 8)
2912 Parts[Num] = N0.getOperand(0).getNode();
2916 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
2917 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2918 /// => (rotl (bswap x), 16)
2919 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2920 if (!LegalOperations)
2923 EVT VT = N->getValueType(0);
2926 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2929 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
2931 // (or (or (and), (and)), (or (and), (and)))
2932 // (or (or (or (and), (and)), (and)), (and))
2933 if (N0.getOpcode() != ISD::OR)
2935 SDValue N00 = N0.getOperand(0);
2936 SDValue N01 = N0.getOperand(1);
2938 if (N1.getOpcode() == ISD::OR) {
2939 // (or (or (and), (and)), (or (and), (and)))
2940 SDValue N000 = N00.getOperand(0);
2941 if (!isBSwapHWordElement(N000, Parts))
2944 SDValue N001 = N00.getOperand(1);
2945 if (!isBSwapHWordElement(N001, Parts))
2947 SDValue N010 = N01.getOperand(0);
2948 if (!isBSwapHWordElement(N010, Parts))
2950 SDValue N011 = N01.getOperand(1);
2951 if (!isBSwapHWordElement(N011, Parts))
2954 // (or (or (or (and), (and)), (and)), (and))
2955 if (!isBSwapHWordElement(N1, Parts))
2957 if (!isBSwapHWordElement(N01, Parts))
2959 if (N00.getOpcode() != ISD::OR)
2961 SDValue N000 = N00.getOperand(0);
2962 if (!isBSwapHWordElement(N000, Parts))
2964 SDValue N001 = N00.getOperand(1);
2965 if (!isBSwapHWordElement(N001, Parts))
2969 // Make sure the parts are all coming from the same node.
2970 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
2973 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
2974 SDValue(Parts[0],0));
2976 // Result of the bswap should be rotated by 16. If it's not legal, than
2977 // do (x << 16) | (x >> 16).
2978 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
2979 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
2980 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
2981 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
2982 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
2983 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
2984 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
2985 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
2988 SDValue DAGCombiner::visitOR(SDNode *N) {
2989 SDValue N0 = N->getOperand(0);
2990 SDValue N1 = N->getOperand(1);
2991 SDValue LL, LR, RL, RR, CC0, CC1;
2992 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2993 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2994 EVT VT = N1.getValueType();
2997 if (VT.isVector()) {
2998 SDValue FoldedVOp = SimplifyVBinOp(N);
2999 if (FoldedVOp.getNode()) return FoldedVOp;
3002 // fold (or x, undef) -> -1
3003 if (!LegalOperations &&
3004 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3005 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3006 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
3008 // fold (or c1, c2) -> c1|c2
3010 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
3011 // canonicalize constant to RHS
3013 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
3014 // fold (or x, 0) -> x
3015 if (N1C && N1C->isNullValue())
3017 // fold (or x, -1) -> -1
3018 if (N1C && N1C->isAllOnesValue())
3020 // fold (or x, c) -> c iff (x & ~c) == 0
3021 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3024 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3025 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3026 if (BSwap.getNode() != 0)
3028 BSwap = MatchBSwapHWordLow(N, N0, N1);
3029 if (BSwap.getNode() != 0)
3033 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
3034 if (ROR.getNode() != 0)
3036 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3037 // iff (c1 & c2) == 0.
3038 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3039 isa<ConstantSDNode>(N0.getOperand(1))) {
3040 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3041 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
3042 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3043 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3044 N0.getOperand(0), N1),
3045 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
3047 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3048 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3049 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3050 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3052 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3053 LL.getValueType().isInteger()) {
3054 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3055 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3056 if (cast<ConstantSDNode>(LR)->isNullValue() &&
3057 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3058 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
3059 LR.getValueType(), LL, RL);
3060 AddToWorkList(ORNode.getNode());
3061 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
3063 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3064 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3065 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
3066 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3067 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
3068 LR.getValueType(), LL, RL);
3069 AddToWorkList(ANDNode.getNode());
3070 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
3073 // canonicalize equivalent to ll == rl
3074 if (LL == RR && LR == RL) {
3075 Op1 = ISD::getSetCCSwappedOperands(Op1);
3078 if (LL == RL && LR == RR) {
3079 bool isInteger = LL.getValueType().isInteger();
3080 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3081 if (Result != ISD::SETCC_INVALID &&
3082 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
3083 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
3088 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3089 if (N0.getOpcode() == N1.getOpcode()) {
3090 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3091 if (Tmp.getNode()) return Tmp;
3094 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3095 if (N0.getOpcode() == ISD::AND &&
3096 N1.getOpcode() == ISD::AND &&
3097 N0.getOperand(1).getOpcode() == ISD::Constant &&
3098 N1.getOperand(1).getOpcode() == ISD::Constant &&
3099 // Don't increase # computations.
3100 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3101 // We can only do this xform if we know that bits from X that are set in C2
3102 // but not in C1 are already zero. Likewise for Y.
3103 const APInt &LHSMask =
3104 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3105 const APInt &RHSMask =
3106 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3108 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3109 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3110 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3111 N0.getOperand(0), N1.getOperand(0));
3112 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
3113 DAG.getConstant(LHSMask | RHSMask, VT));
3117 // See if this is some rotate idiom.
3118 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
3119 return SDValue(Rot, 0);
3121 // Simplify the operands using demanded-bits information.
3122 if (!VT.isVector() &&
3123 SimplifyDemandedBits(SDValue(N, 0)))
3124 return SDValue(N, 0);
3129 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
3130 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3131 if (Op.getOpcode() == ISD::AND) {
3132 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3133 Mask = Op.getOperand(1);
3134 Op = Op.getOperand(0);
3140 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3148 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3149 // idioms for rotate, and if the target supports rotation instructions, generate
3151 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
3152 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3153 EVT VT = LHS.getValueType();
3154 if (!TLI.isTypeLegal(VT)) return 0;
3156 // The target must have at least one rotate flavor.
3157 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3158 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3159 if (!HasROTL && !HasROTR) return 0;
3161 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3162 SDValue LHSShift; // The shift.
3163 SDValue LHSMask; // AND value if any.
3164 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3165 return 0; // Not part of a rotate.
3167 SDValue RHSShift; // The shift.
3168 SDValue RHSMask; // AND value if any.
3169 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3170 return 0; // Not part of a rotate.
3172 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3173 return 0; // Not shifting the same value.
3175 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3176 return 0; // Shifts must disagree.
3178 // Canonicalize shl to left side in a shl/srl pair.
3179 if (RHSShift.getOpcode() == ISD::SHL) {
3180 std::swap(LHS, RHS);
3181 std::swap(LHSShift, RHSShift);
3182 std::swap(LHSMask , RHSMask );
3185 unsigned OpSizeInBits = VT.getSizeInBits();
3186 SDValue LHSShiftArg = LHSShift.getOperand(0);
3187 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3188 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3190 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3191 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3192 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3193 RHSShiftAmt.getOpcode() == ISD::Constant) {
3194 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3195 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3196 if ((LShVal + RShVal) != OpSizeInBits)
3201 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
3203 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
3205 // If there is an AND of either shifted operand, apply it to the result.
3206 if (LHSMask.getNode() || RHSMask.getNode()) {
3207 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3209 if (LHSMask.getNode()) {
3210 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3211 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3213 if (RHSMask.getNode()) {
3214 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3215 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3218 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3221 return Rot.getNode();
3224 // If there is a mask here, and we have a variable shift, we can't be sure
3225 // that we're masking out the right stuff.
3226 if (LHSMask.getNode() || RHSMask.getNode())
3229 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
3230 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
3231 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
3232 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
3233 if (ConstantSDNode *SUBC =
3234 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
3235 if (SUBC->getAPIntValue() == OpSizeInBits) {
3237 return DAG.getNode(ISD::ROTL, DL, VT,
3238 LHSShiftArg, LHSShiftAmt).getNode();
3240 return DAG.getNode(ISD::ROTR, DL, VT,
3241 LHSShiftArg, RHSShiftAmt).getNode();
3246 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
3247 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
3248 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
3249 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
3250 if (ConstantSDNode *SUBC =
3251 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
3252 if (SUBC->getAPIntValue() == OpSizeInBits) {
3254 return DAG.getNode(ISD::ROTR, DL, VT,
3255 LHSShiftArg, RHSShiftAmt).getNode();
3257 return DAG.getNode(ISD::ROTL, DL, VT,
3258 LHSShiftArg, LHSShiftAmt).getNode();
3263 // Look for sign/zext/any-extended or truncate cases:
3264 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3265 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3266 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3267 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3268 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3269 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3270 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3271 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3272 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
3273 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
3274 if (RExtOp0.getOpcode() == ISD::SUB &&
3275 RExtOp0.getOperand(1) == LExtOp0) {
3276 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3278 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3279 // (rotr x, (sub 32, y))
3280 if (ConstantSDNode *SUBC =
3281 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3282 if (SUBC->getAPIntValue() == OpSizeInBits) {
3283 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3285 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3288 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3289 RExtOp0 == LExtOp0.getOperand(1)) {
3290 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3292 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3293 // (rotl x, (sub 32, y))
3294 if (ConstantSDNode *SUBC =
3295 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3296 if (SUBC->getAPIntValue() == OpSizeInBits) {
3297 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3299 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3308 SDValue DAGCombiner::visitXOR(SDNode *N) {
3309 SDValue N0 = N->getOperand(0);
3310 SDValue N1 = N->getOperand(1);
3311 SDValue LHS, RHS, CC;
3312 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3313 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3314 EVT VT = N0.getValueType();
3317 if (VT.isVector()) {
3318 SDValue FoldedVOp = SimplifyVBinOp(N);
3319 if (FoldedVOp.getNode()) return FoldedVOp;
3322 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3323 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3324 return DAG.getConstant(0, VT);
3325 // fold (xor x, undef) -> undef
3326 if (N0.getOpcode() == ISD::UNDEF)
3328 if (N1.getOpcode() == ISD::UNDEF)
3330 // fold (xor c1, c2) -> c1^c2
3332 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3333 // canonicalize constant to RHS
3335 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3336 // fold (xor x, 0) -> x
3337 if (N1C && N1C->isNullValue())
3340 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3341 if (RXOR.getNode() != 0)
3344 // fold !(x cc y) -> (x !cc y)
3345 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3346 bool isInt = LHS.getValueType().isInteger();
3347 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3350 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
3351 switch (N0.getOpcode()) {
3353 llvm_unreachable("Unhandled SetCC Equivalent!");
3355 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
3356 case ISD::SELECT_CC:
3357 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
3358 N0.getOperand(3), NotCC);
3363 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3364 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3365 N0.getNode()->hasOneUse() &&
3366 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3367 SDValue V = N0.getOperand(0);
3368 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3369 DAG.getConstant(1, V.getValueType()));
3370 AddToWorkList(V.getNode());
3371 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
3374 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3375 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3376 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3377 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3378 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3379 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3380 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3381 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3382 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3383 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3386 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3387 if (N1C && N1C->isAllOnesValue() &&
3388 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3389 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3390 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3391 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3392 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3393 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3394 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3395 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3398 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3399 if (N1C && N0.getOpcode() == ISD::XOR) {
3400 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3401 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3403 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3404 DAG.getConstant(N1C->getAPIntValue() ^
3405 N00C->getAPIntValue(), VT));
3407 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3408 DAG.getConstant(N1C->getAPIntValue() ^
3409 N01C->getAPIntValue(), VT));
3411 // fold (xor x, x) -> 0
3413 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
3415 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3416 if (N0.getOpcode() == N1.getOpcode()) {
3417 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3418 if (Tmp.getNode()) return Tmp;
3421 // Simplify the expression using non-local knowledge.
3422 if (!VT.isVector() &&
3423 SimplifyDemandedBits(SDValue(N, 0)))
3424 return SDValue(N, 0);
3429 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3430 /// the shift amount is a constant.
3431 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3432 SDNode *LHS = N->getOperand(0).getNode();
3433 if (!LHS->hasOneUse()) return SDValue();
3435 // We want to pull some binops through shifts, so that we have (and (shift))
3436 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3437 // thing happens with address calculations, so it's important to canonicalize
3439 bool HighBitSet = false; // Can we transform this if the high bit is set?
3441 switch (LHS->getOpcode()) {
3442 default: return SDValue();
3445 HighBitSet = false; // We can only transform sra if the high bit is clear.
3448 HighBitSet = true; // We can only transform sra if the high bit is set.
3451 if (N->getOpcode() != ISD::SHL)
3452 return SDValue(); // only shl(add) not sr[al](add).
3453 HighBitSet = false; // We can only transform sra if the high bit is clear.
3457 // We require the RHS of the binop to be a constant as well.
3458 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3459 if (!BinOpCst) return SDValue();
3461 // FIXME: disable this unless the input to the binop is a shift by a constant.
3462 // If it is not a shift, it pessimizes some common cases like:
3464 // void foo(int *X, int i) { X[i & 1235] = 1; }
3465 // int bar(int *X, int i) { return X[i & 255]; }
3466 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3467 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3468 BinOpLHSVal->getOpcode() != ISD::SRA &&
3469 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3470 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3473 EVT VT = N->getValueType(0);
3475 // If this is a signed shift right, and the high bit is modified by the
3476 // logical operation, do not perform the transformation. The highBitSet
3477 // boolean indicates the value of the high bit of the constant which would
3478 // cause it to be modified for this operation.
3479 if (N->getOpcode() == ISD::SRA) {
3480 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3481 if (BinOpRHSSignSet != HighBitSet)
3485 // Fold the constants, shifting the binop RHS by the shift amount.
3486 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
3488 LHS->getOperand(1), N->getOperand(1));
3490 // Create the new shift.
3491 SDValue NewShift = DAG.getNode(N->getOpcode(),
3492 LHS->getOperand(0).getDebugLoc(),
3493 VT, LHS->getOperand(0), N->getOperand(1));
3495 // Create the new binop.
3496 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
3499 SDValue DAGCombiner::visitSHL(SDNode *N) {
3500 SDValue N0 = N->getOperand(0);
3501 SDValue N1 = N->getOperand(1);
3502 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3503 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3504 EVT VT = N0.getValueType();
3505 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3507 // fold (shl c1, c2) -> c1<<c2
3509 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3510 // fold (shl 0, x) -> 0
3511 if (N0C && N0C->isNullValue())
3513 // fold (shl x, c >= size(x)) -> undef
3514 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3515 return DAG.getUNDEF(VT);
3516 // fold (shl x, 0) -> x
3517 if (N1C && N1C->isNullValue())
3519 // fold (shl undef, x) -> 0
3520 if (N0.getOpcode() == ISD::UNDEF)
3521 return DAG.getConstant(0, VT);
3522 // if (shl x, c) is known to be zero, return 0
3523 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3524 APInt::getAllOnesValue(OpSizeInBits)))
3525 return DAG.getConstant(0, VT);
3526 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3527 if (N1.getOpcode() == ISD::TRUNCATE &&
3528 N1.getOperand(0).getOpcode() == ISD::AND &&
3529 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3530 SDValue N101 = N1.getOperand(0).getOperand(1);
3531 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3532 EVT TruncVT = N1.getValueType();
3533 SDValue N100 = N1.getOperand(0).getOperand(0);
3534 APInt TruncC = N101C->getAPIntValue();
3535 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3536 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3537 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3538 DAG.getNode(ISD::TRUNCATE,
3541 DAG.getConstant(TruncC, TruncVT)));
3545 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3546 return SDValue(N, 0);
3548 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3549 if (N1C && N0.getOpcode() == ISD::SHL &&
3550 N0.getOperand(1).getOpcode() == ISD::Constant) {
3551 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3552 uint64_t c2 = N1C->getZExtValue();
3553 if (c1 + c2 >= OpSizeInBits)
3554 return DAG.getConstant(0, VT);
3555 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3556 DAG.getConstant(c1 + c2, N1.getValueType()));
3559 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3560 // For this to be valid, the second form must not preserve any of the bits
3561 // that are shifted out by the inner shift in the first form. This means
3562 // the outer shift size must be >= the number of bits added by the ext.
3563 // As a corollary, we don't care what kind of ext it is.
3564 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3565 N0.getOpcode() == ISD::ANY_EXTEND ||
3566 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3567 N0.getOperand(0).getOpcode() == ISD::SHL &&
3568 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3570 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3571 uint64_t c2 = N1C->getZExtValue();
3572 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3573 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3574 if (c2 >= OpSizeInBits - InnerShiftSize) {
3575 if (c1 + c2 >= OpSizeInBits)
3576 return DAG.getConstant(0, VT);
3577 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3578 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3579 N0.getOperand(0)->getOperand(0)),
3580 DAG.getConstant(c1 + c2, N1.getValueType()));
3584 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3585 // (and (srl x, (sub c1, c2), MASK)
3586 // Only fold this if the inner shift has no other uses -- if it does, folding
3587 // this will increase the total number of instructions.
3588 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3589 N0.getOperand(1).getOpcode() == ISD::Constant) {
3590 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3591 if (c1 < VT.getSizeInBits()) {
3592 uint64_t c2 = N1C->getZExtValue();
3593 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3594 VT.getSizeInBits() - c1);
3597 Mask = Mask.shl(c2-c1);
3598 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3599 DAG.getConstant(c2-c1, N1.getValueType()));
3601 Mask = Mask.lshr(c1-c2);
3602 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3603 DAG.getConstant(c1-c2, N1.getValueType()));
3605 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3606 DAG.getConstant(Mask, VT));
3609 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3610 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3611 SDValue HiBitsMask =
3612 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3613 VT.getSizeInBits() -
3614 N1C->getZExtValue()),
3616 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3621 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3622 if (NewSHL.getNode())
3629 SDValue DAGCombiner::visitSRA(SDNode *N) {
3630 SDValue N0 = N->getOperand(0);
3631 SDValue N1 = N->getOperand(1);
3632 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3633 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3634 EVT VT = N0.getValueType();
3635 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3637 // fold (sra c1, c2) -> (sra c1, c2)
3639 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3640 // fold (sra 0, x) -> 0
3641 if (N0C && N0C->isNullValue())
3643 // fold (sra -1, x) -> -1
3644 if (N0C && N0C->isAllOnesValue())
3646 // fold (sra x, (setge c, size(x))) -> undef
3647 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3648 return DAG.getUNDEF(VT);
3649 // fold (sra x, 0) -> x
3650 if (N1C && N1C->isNullValue())
3652 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3654 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3655 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3656 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3658 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3659 ExtVT, VT.getVectorNumElements());
3660 if ((!LegalOperations ||
3661 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3662 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3663 N0.getOperand(0), DAG.getValueType(ExtVT));
3666 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3667 if (N1C && N0.getOpcode() == ISD::SRA) {
3668 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3669 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3670 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3671 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3672 DAG.getConstant(Sum, N1C->getValueType(0)));
3676 // fold (sra (shl X, m), (sub result_size, n))
3677 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3678 // result_size - n != m.
3679 // If truncate is free for the target sext(shl) is likely to result in better
3681 if (N0.getOpcode() == ISD::SHL) {
3682 // Get the two constanst of the shifts, CN0 = m, CN = n.
3683 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3685 // Determine what the truncate's result bitsize and type would be.
3687 EVT::getIntegerVT(*DAG.getContext(),
3688 OpSizeInBits - N1C->getZExtValue());
3689 // Determine the residual right-shift amount.
3690 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3692 // If the shift is not a no-op (in which case this should be just a sign
3693 // extend already), the truncated to type is legal, sign_extend is legal
3694 // on that type, and the truncate to that type is both legal and free,
3695 // perform the transform.
3696 if ((ShiftAmt > 0) &&
3697 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3698 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3699 TLI.isTruncateFree(VT, TruncVT)) {
3701 SDValue Amt = DAG.getConstant(ShiftAmt,
3702 getShiftAmountTy(N0.getOperand(0).getValueType()));
3703 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3704 N0.getOperand(0), Amt);
3705 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3707 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3708 N->getValueType(0), Trunc);
3713 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3714 if (N1.getOpcode() == ISD::TRUNCATE &&
3715 N1.getOperand(0).getOpcode() == ISD::AND &&
3716 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3717 SDValue N101 = N1.getOperand(0).getOperand(1);
3718 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3719 EVT TruncVT = N1.getValueType();
3720 SDValue N100 = N1.getOperand(0).getOperand(0);
3721 APInt TruncC = N101C->getAPIntValue();
3722 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3723 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3724 DAG.getNode(ISD::AND, N->getDebugLoc(),
3726 DAG.getNode(ISD::TRUNCATE,
3729 DAG.getConstant(TruncC, TruncVT)));
3733 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3734 // if c1 is equal to the number of bits the trunc removes
3735 if (N0.getOpcode() == ISD::TRUNCATE &&
3736 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3737 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3738 N0.getOperand(0).hasOneUse() &&
3739 N0.getOperand(0).getOperand(1).hasOneUse() &&
3740 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3741 EVT LargeVT = N0.getOperand(0).getValueType();
3742 ConstantSDNode *LargeShiftAmt =
3743 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3745 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3746 LargeShiftAmt->getZExtValue()) {
3748 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3749 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3750 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3751 N0.getOperand(0).getOperand(0), Amt);
3752 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3756 // Simplify, based on bits shifted out of the LHS.
3757 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3758 return SDValue(N, 0);
3761 // If the sign bit is known to be zero, switch this to a SRL.
3762 if (DAG.SignBitIsZero(N0))
3763 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3766 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3767 if (NewSRA.getNode())
3774 SDValue DAGCombiner::visitSRL(SDNode *N) {
3775 SDValue N0 = N->getOperand(0);
3776 SDValue N1 = N->getOperand(1);
3777 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3778 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3779 EVT VT = N0.getValueType();
3780 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3782 // fold (srl c1, c2) -> c1 >>u c2
3784 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3785 // fold (srl 0, x) -> 0
3786 if (N0C && N0C->isNullValue())
3788 // fold (srl x, c >= size(x)) -> undef
3789 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3790 return DAG.getUNDEF(VT);
3791 // fold (srl x, 0) -> x
3792 if (N1C && N1C->isNullValue())
3794 // if (srl x, c) is known to be zero, return 0
3795 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3796 APInt::getAllOnesValue(OpSizeInBits)))
3797 return DAG.getConstant(0, VT);
3799 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3800 if (N1C && N0.getOpcode() == ISD::SRL &&
3801 N0.getOperand(1).getOpcode() == ISD::Constant) {
3802 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3803 uint64_t c2 = N1C->getZExtValue();
3804 if (c1 + c2 >= OpSizeInBits)
3805 return DAG.getConstant(0, VT);
3806 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3807 DAG.getConstant(c1 + c2, N1.getValueType()));
3810 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3811 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3812 N0.getOperand(0).getOpcode() == ISD::SRL &&
3813 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3815 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3816 uint64_t c2 = N1C->getZExtValue();
3817 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3818 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3819 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3820 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3821 if (c1 + OpSizeInBits == InnerShiftSize) {
3822 if (c1 + c2 >= InnerShiftSize)
3823 return DAG.getConstant(0, VT);
3824 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3825 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3826 N0.getOperand(0)->getOperand(0),
3827 DAG.getConstant(c1 + c2, ShiftCountVT)));
3831 // fold (srl (shl x, c), c) -> (and x, cst2)
3832 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3833 N0.getValueSizeInBits() <= 64) {
3834 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3835 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3836 DAG.getConstant(~0ULL >> ShAmt, VT));
3840 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3841 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3842 // Shifting in all undef bits?
3843 EVT SmallVT = N0.getOperand(0).getValueType();
3844 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3845 return DAG.getUNDEF(VT);
3847 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3848 uint64_t ShiftAmt = N1C->getZExtValue();
3849 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3851 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3852 AddToWorkList(SmallShift.getNode());
3853 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3857 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3858 // bit, which is unmodified by sra.
3859 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3860 if (N0.getOpcode() == ISD::SRA)
3861 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3864 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3865 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3866 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3867 APInt KnownZero, KnownOne;
3868 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne);
3870 // If any of the input bits are KnownOne, then the input couldn't be all
3871 // zeros, thus the result of the srl will always be zero.
3872 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3874 // If all of the bits input the to ctlz node are known to be zero, then
3875 // the result of the ctlz is "32" and the result of the shift is one.
3876 APInt UnknownBits = ~KnownZero;
3877 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3879 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3880 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3881 // Okay, we know that only that the single bit specified by UnknownBits
3882 // could be set on input to the CTLZ node. If this bit is set, the SRL
3883 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3884 // to an SRL/XOR pair, which is likely to simplify more.
3885 unsigned ShAmt = UnknownBits.countTrailingZeros();
3886 SDValue Op = N0.getOperand(0);
3889 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3890 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3891 AddToWorkList(Op.getNode());
3894 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3895 Op, DAG.getConstant(1, VT));
3899 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3900 if (N1.getOpcode() == ISD::TRUNCATE &&
3901 N1.getOperand(0).getOpcode() == ISD::AND &&
3902 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3903 SDValue N101 = N1.getOperand(0).getOperand(1);
3904 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3905 EVT TruncVT = N1.getValueType();
3906 SDValue N100 = N1.getOperand(0).getOperand(0);
3907 APInt TruncC = N101C->getAPIntValue();
3908 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3909 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3910 DAG.getNode(ISD::AND, N->getDebugLoc(),
3912 DAG.getNode(ISD::TRUNCATE,
3915 DAG.getConstant(TruncC, TruncVT)));
3919 // fold operands of srl based on knowledge that the low bits are not
3921 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3922 return SDValue(N, 0);
3925 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3926 if (NewSRL.getNode())
3930 // Attempt to convert a srl of a load into a narrower zero-extending load.
3931 SDValue NarrowLoad = ReduceLoadWidth(N);
3932 if (NarrowLoad.getNode())
3935 // Here is a common situation. We want to optimize:
3938 // %b = and i32 %a, 2
3939 // %c = srl i32 %b, 1
3940 // brcond i32 %c ...
3946 // %c = setcc eq %b, 0
3949 // However when after the source operand of SRL is optimized into AND, the SRL
3950 // itself may not be optimized further. Look for it and add the BRCOND into
3952 if (N->hasOneUse()) {
3953 SDNode *Use = *N->use_begin();
3954 if (Use->getOpcode() == ISD::BRCOND)
3956 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3957 // Also look pass the truncate.
3958 Use = *Use->use_begin();
3959 if (Use->getOpcode() == ISD::BRCOND)
3967 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3968 SDValue N0 = N->getOperand(0);
3969 EVT VT = N->getValueType(0);
3971 // fold (ctlz c1) -> c2
3972 if (isa<ConstantSDNode>(N0))
3973 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3977 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
3978 SDValue N0 = N->getOperand(0);
3979 EVT VT = N->getValueType(0);
3981 // fold (ctlz_zero_undef c1) -> c2
3982 if (isa<ConstantSDNode>(N0))
3983 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
3987 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
3988 SDValue N0 = N->getOperand(0);
3989 EVT VT = N->getValueType(0);
3991 // fold (cttz c1) -> c2
3992 if (isa<ConstantSDNode>(N0))
3993 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3997 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
3998 SDValue N0 = N->getOperand(0);
3999 EVT VT = N->getValueType(0);
4001 // fold (cttz_zero_undef c1) -> c2
4002 if (isa<ConstantSDNode>(N0))
4003 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
4007 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4008 SDValue N0 = N->getOperand(0);
4009 EVT VT = N->getValueType(0);
4011 // fold (ctpop c1) -> c2
4012 if (isa<ConstantSDNode>(N0))
4013 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
4017 SDValue DAGCombiner::visitSELECT(SDNode *N) {
4018 SDValue N0 = N->getOperand(0);
4019 SDValue N1 = N->getOperand(1);
4020 SDValue N2 = N->getOperand(2);
4021 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4022 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4023 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
4024 EVT VT = N->getValueType(0);
4025 EVT VT0 = N0.getValueType();
4027 // fold (select C, X, X) -> X
4030 // fold (select true, X, Y) -> X
4031 if (N0C && !N0C->isNullValue())
4033 // fold (select false, X, Y) -> Y
4034 if (N0C && N0C->isNullValue())
4036 // fold (select C, 1, X) -> (or C, X)
4037 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
4038 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4039 // fold (select C, 0, 1) -> (xor C, 1)
4040 if (VT.isInteger() &&
4043 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) &&
4044 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
4047 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
4048 N0, DAG.getConstant(1, VT0));
4049 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
4050 N0, DAG.getConstant(1, VT0));
4051 AddToWorkList(XORNode.getNode());
4053 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
4054 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
4056 // fold (select C, 0, X) -> (and (not C), X)
4057 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
4058 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
4059 AddToWorkList(NOTNode.getNode());
4060 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
4062 // fold (select C, X, 1) -> (or (not C), X)
4063 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
4064 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
4065 AddToWorkList(NOTNode.getNode());
4066 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
4068 // fold (select C, X, 0) -> (and C, X)
4069 if (VT == MVT::i1 && N2C && N2C->isNullValue())
4070 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4071 // fold (select X, X, Y) -> (or X, Y)
4072 // fold (select X, 1, Y) -> (or X, Y)
4073 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4074 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4075 // fold (select X, Y, X) -> (and X, Y)
4076 // fold (select X, Y, 0) -> (and X, Y)
4077 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4078 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4080 // If we can fold this based on the true/false value, do so.
4081 if (SimplifySelectOps(N, N1, N2))
4082 return SDValue(N, 0); // Don't revisit N.
4084 // fold selects based on a setcc into other things, such as min/max/abs
4085 if (N0.getOpcode() == ISD::SETCC) {
4087 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
4088 // having to say they don't support SELECT_CC on every type the DAG knows
4089 // about, since there is no way to mark an opcode illegal at all value types
4090 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
4091 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
4092 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
4093 N0.getOperand(0), N0.getOperand(1),
4094 N1, N2, N0.getOperand(2));
4095 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
4101 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
4102 SDValue N0 = N->getOperand(0);
4103 SDValue N1 = N->getOperand(1);
4104 SDValue N2 = N->getOperand(2);
4105 SDValue N3 = N->getOperand(3);
4106 SDValue N4 = N->getOperand(4);
4107 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
4109 // fold select_cc lhs, rhs, x, x, cc -> x
4113 // Determine if the condition we're dealing with is constant
4114 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
4115 N0, N1, CC, N->getDebugLoc(), false);
4116 if (SCC.getNode()) AddToWorkList(SCC.getNode());
4118 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
4119 if (!SCCC->isNullValue())
4120 return N2; // cond always true -> true val
4122 return N3; // cond always false -> false val
4125 // Fold to a simpler select_cc
4126 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
4127 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
4128 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
4131 // If we can fold this based on the true/false value, do so.
4132 if (SimplifySelectOps(N, N2, N3))
4133 return SDValue(N, 0); // Don't revisit N.
4135 // fold select_cc into other things, such as min/max/abs
4136 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
4139 SDValue DAGCombiner::visitSETCC(SDNode *N) {
4140 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
4141 cast<CondCodeSDNode>(N->getOperand(2))->get(),
4145 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
4146 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
4147 // transformation. Returns true if extension are possible and the above
4148 // mentioned transformation is profitable.
4149 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
4151 SmallVector<SDNode*, 4> &ExtendNodes,
4152 const TargetLowering &TLI) {
4153 bool HasCopyToRegUses = false;
4154 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
4155 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4156 UE = N0.getNode()->use_end();
4161 if (UI.getUse().getResNo() != N0.getResNo())
4163 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
4164 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4165 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
4166 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
4167 // Sign bits will be lost after a zext.
4170 for (unsigned i = 0; i != 2; ++i) {
4171 SDValue UseOp = User->getOperand(i);
4174 if (!isa<ConstantSDNode>(UseOp))
4179 ExtendNodes.push_back(User);
4182 // If truncates aren't free and there are users we can't
4183 // extend, it isn't worthwhile.
4186 // Remember if this value is live-out.
4187 if (User->getOpcode() == ISD::CopyToReg)
4188 HasCopyToRegUses = true;
4191 if (HasCopyToRegUses) {
4192 bool BothLiveOut = false;
4193 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4195 SDUse &Use = UI.getUse();
4196 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4202 // Both unextended and extended values are live out. There had better be
4203 // a good reason for the transformation.
4204 return ExtendNodes.size();
4209 void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
4210 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
4211 ISD::NodeType ExtType) {
4212 // Extend SetCC uses if necessary.
4213 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4214 SDNode *SetCC = SetCCs[i];
4215 SmallVector<SDValue, 4> Ops;
4217 for (unsigned j = 0; j != 2; ++j) {
4218 SDValue SOp = SetCC->getOperand(j);
4220 Ops.push_back(ExtLoad);
4222 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
4225 Ops.push_back(SetCC->getOperand(2));
4226 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
4227 &Ops[0], Ops.size()));
4231 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
4232 SDValue N0 = N->getOperand(0);
4233 EVT VT = N->getValueType(0);
4235 // fold (sext c1) -> c1
4236 if (isa<ConstantSDNode>(N0))
4237 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
4239 // fold (sext (sext x)) -> (sext x)
4240 // fold (sext (aext x)) -> (sext x)
4241 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4242 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
4245 if (N0.getOpcode() == ISD::TRUNCATE) {
4246 // fold (sext (truncate (load x))) -> (sext (smaller load x))
4247 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
4248 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4249 if (NarrowLoad.getNode()) {
4250 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4251 if (NarrowLoad.getNode() != N0.getNode()) {
4252 CombineTo(N0.getNode(), NarrowLoad);
4253 // CombineTo deleted the truncate, if needed, but not what's under it.
4256 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4259 // See if the value being truncated is already sign extended. If so, just
4260 // eliminate the trunc/sext pair.
4261 SDValue Op = N0.getOperand(0);
4262 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
4263 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
4264 unsigned DestBits = VT.getScalarType().getSizeInBits();
4265 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
4267 if (OpBits == DestBits) {
4268 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
4269 // bits, it is already ready.
4270 if (NumSignBits > DestBits-MidBits)
4272 } else if (OpBits < DestBits) {
4273 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
4274 // bits, just sext from i32.
4275 if (NumSignBits > OpBits-MidBits)
4276 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
4278 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
4279 // bits, just truncate to i32.
4280 if (NumSignBits > OpBits-MidBits)
4281 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4284 // fold (sext (truncate x)) -> (sextinreg x).
4285 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4286 N0.getValueType())) {
4287 if (OpBits < DestBits)
4288 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4289 else if (OpBits > DestBits)
4290 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4291 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
4292 DAG.getValueType(N0.getValueType()));
4296 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4297 // None of the supported targets knows how to perform load and sign extend
4298 // on vectors in one instruction. We only perform this transformation on
4300 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4301 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4302 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4303 bool DoXform = true;
4304 SmallVector<SDNode*, 4> SetCCs;
4305 if (!N0.hasOneUse())
4306 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4308 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4309 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4311 LN0->getBasePtr(), LN0->getPointerInfo(),
4313 LN0->isVolatile(), LN0->isNonTemporal(),
4314 LN0->getAlignment());
4315 CombineTo(N, ExtLoad);
4316 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4317 N0.getValueType(), ExtLoad);
4318 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4319 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4321 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4325 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4326 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4327 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4328 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4329 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4330 EVT MemVT = LN0->getMemoryVT();
4331 if ((!LegalOperations && !LN0->isVolatile()) ||
4332 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4333 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4335 LN0->getBasePtr(), LN0->getPointerInfo(),
4337 LN0->isVolatile(), LN0->isNonTemporal(),
4338 LN0->getAlignment());
4339 CombineTo(N, ExtLoad);
4340 CombineTo(N0.getNode(),
4341 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4342 N0.getValueType(), ExtLoad),
4343 ExtLoad.getValue(1));
4344 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4348 // fold (sext (and/or/xor (load x), cst)) ->
4349 // (and/or/xor (sextload x), (sext cst))
4350 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4351 N0.getOpcode() == ISD::XOR) &&
4352 isa<LoadSDNode>(N0.getOperand(0)) &&
4353 N0.getOperand(1).getOpcode() == ISD::Constant &&
4354 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4355 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4356 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4357 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4358 bool DoXform = true;
4359 SmallVector<SDNode*, 4> SetCCs;
4360 if (!N0.hasOneUse())
4361 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4364 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4365 LN0->getChain(), LN0->getBasePtr(),
4366 LN0->getPointerInfo(),
4369 LN0->isNonTemporal(),
4370 LN0->getAlignment());
4371 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4372 Mask = Mask.sext(VT.getSizeInBits());
4373 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4374 ExtLoad, DAG.getConstant(Mask, VT));
4375 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4376 N0.getOperand(0).getDebugLoc(),
4377 N0.getOperand(0).getValueType(), ExtLoad);
4379 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4380 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4382 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4387 if (N0.getOpcode() == ISD::SETCC) {
4388 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4389 // Only do this before legalize for now.
4390 if (VT.isVector() && !LegalOperations) {
4391 EVT N0VT = N0.getOperand(0).getValueType();
4392 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
4393 // of the same size as the compared operands. Only optimize sext(setcc())
4394 // if this is the case.
4395 EVT SVT = TLI.getSetCCResultType(N0VT);
4397 // We know that the # elements of the results is the same as the
4398 // # elements of the compare (and the # elements of the compare result
4399 // for that matter). Check to see that they are the same size. If so,
4400 // we know that the element size of the sext'd result matches the
4401 // element size of the compare operands.
4402 if (VT.getSizeInBits() == SVT.getSizeInBits())
4403 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4405 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4406 // If the desired elements are smaller or larger than the source
4407 // elements we can use a matching integer vector type and then
4408 // truncate/sign extend
4410 EVT MatchingElementType =
4411 EVT::getIntegerVT(*DAG.getContext(),
4412 N0VT.getScalarType().getSizeInBits());
4413 EVT MatchingVectorType =
4414 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4415 N0VT.getVectorNumElements());
4417 if (SVT == MatchingVectorType) {
4418 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType,
4419 N0.getOperand(0), N0.getOperand(1),
4420 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4421 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4426 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4427 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4429 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4431 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4432 NegOne, DAG.getConstant(0, VT),
4433 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4434 if (SCC.getNode()) return SCC;
4435 if (!LegalOperations ||
4436 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
4437 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4438 DAG.getSetCC(N->getDebugLoc(),
4439 TLI.getSetCCResultType(VT),
4440 N0.getOperand(0), N0.getOperand(1),
4441 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4442 NegOne, DAG.getConstant(0, VT));
4445 // fold (sext x) -> (zext x) if the sign bit is known zero.
4446 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4447 DAG.SignBitIsZero(N0))
4448 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4453 // isTruncateOf - If N is a truncate of some other value, return true, record
4454 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
4455 // This function computes KnownZero to avoid a duplicated call to
4456 // ComputeMaskedBits in the caller.
4457 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
4460 if (N->getOpcode() == ISD::TRUNCATE) {
4461 Op = N->getOperand(0);
4462 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4466 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
4467 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
4470 SDValue Op0 = N->getOperand(0);
4471 SDValue Op1 = N->getOperand(1);
4472 assert(Op0.getValueType() == Op1.getValueType());
4474 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0);
4475 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
4476 if (COp0 && COp0->isNullValue())
4478 else if (COp1 && COp1->isNullValue())
4483 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4485 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
4491 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4492 SDValue N0 = N->getOperand(0);
4493 EVT VT = N->getValueType(0);
4495 // fold (zext c1) -> c1
4496 if (isa<ConstantSDNode>(N0))
4497 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4498 // fold (zext (zext x)) -> (zext x)
4499 // fold (zext (aext x)) -> (zext x)
4500 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4501 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
4504 // fold (zext (truncate x)) -> (zext x) or
4505 // (zext (truncate x)) -> (truncate x)
4506 // This is valid when the truncated bits of x are already zero.
4507 // FIXME: We should extend this to work for vectors too.
4510 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
4511 APInt TruncatedBits =
4512 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
4513 APInt(Op.getValueSizeInBits(), 0) :
4514 APInt::getBitsSet(Op.getValueSizeInBits(),
4515 N0.getValueSizeInBits(),
4516 std::min(Op.getValueSizeInBits(),
4517 VT.getSizeInBits()));
4518 if (TruncatedBits == (KnownZero & TruncatedBits)) {
4519 if (VT.bitsGT(Op.getValueType()))
4520 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op);
4521 if (VT.bitsLT(Op.getValueType()))
4522 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4528 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4529 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4530 if (N0.getOpcode() == ISD::TRUNCATE) {
4531 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4532 if (NarrowLoad.getNode()) {
4533 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4534 if (NarrowLoad.getNode() != N0.getNode()) {
4535 CombineTo(N0.getNode(), NarrowLoad);
4536 // CombineTo deleted the truncate, if needed, but not what's under it.
4539 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4543 // fold (zext (truncate x)) -> (and x, mask)
4544 if (N0.getOpcode() == ISD::TRUNCATE &&
4545 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4547 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4548 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4549 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4550 if (NarrowLoad.getNode()) {
4551 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4552 if (NarrowLoad.getNode() != N0.getNode()) {
4553 CombineTo(N0.getNode(), NarrowLoad);
4554 // CombineTo deleted the truncate, if needed, but not what's under it.
4557 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4560 SDValue Op = N0.getOperand(0);
4561 if (Op.getValueType().bitsLT(VT)) {
4562 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
4563 AddToWorkList(Op.getNode());
4564 } else if (Op.getValueType().bitsGT(VT)) {
4565 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4566 AddToWorkList(Op.getNode());
4568 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
4569 N0.getValueType().getScalarType());
4572 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4573 // if either of the casts is not free.
4574 if (N0.getOpcode() == ISD::AND &&
4575 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4576 N0.getOperand(1).getOpcode() == ISD::Constant &&
4577 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4578 N0.getValueType()) ||
4579 !TLI.isZExtFree(N0.getValueType(), VT))) {
4580 SDValue X = N0.getOperand(0).getOperand(0);
4581 if (X.getValueType().bitsLT(VT)) {
4582 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
4583 } else if (X.getValueType().bitsGT(VT)) {
4584 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4586 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4587 Mask = Mask.zext(VT.getSizeInBits());
4588 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4589 X, DAG.getConstant(Mask, VT));
4592 // fold (zext (load x)) -> (zext (truncate (zextload x)))
4593 // None of the supported targets knows how to perform load and vector_zext
4594 // on vectors in one instruction. We only perform this transformation on
4596 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4597 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4598 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4599 bool DoXform = true;
4600 SmallVector<SDNode*, 4> SetCCs;
4601 if (!N0.hasOneUse())
4602 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4604 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4605 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4607 LN0->getBasePtr(), LN0->getPointerInfo(),
4609 LN0->isVolatile(), LN0->isNonTemporal(),
4610 LN0->getAlignment());
4611 CombineTo(N, ExtLoad);
4612 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4613 N0.getValueType(), ExtLoad);
4614 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4616 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4618 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4622 // fold (zext (and/or/xor (load x), cst)) ->
4623 // (and/or/xor (zextload x), (zext cst))
4624 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4625 N0.getOpcode() == ISD::XOR) &&
4626 isa<LoadSDNode>(N0.getOperand(0)) &&
4627 N0.getOperand(1).getOpcode() == ISD::Constant &&
4628 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4629 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4630 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4631 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4632 bool DoXform = true;
4633 SmallVector<SDNode*, 4> SetCCs;
4634 if (!N0.hasOneUse())
4635 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4638 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
4639 LN0->getChain(), LN0->getBasePtr(),
4640 LN0->getPointerInfo(),
4643 LN0->isNonTemporal(),
4644 LN0->getAlignment());
4645 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4646 Mask = Mask.zext(VT.getSizeInBits());
4647 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4648 ExtLoad, DAG.getConstant(Mask, VT));
4649 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4650 N0.getOperand(0).getDebugLoc(),
4651 N0.getOperand(0).getValueType(), ExtLoad);
4653 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4654 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4656 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4661 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4662 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4663 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4664 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4665 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4666 EVT MemVT = LN0->getMemoryVT();
4667 if ((!LegalOperations && !LN0->isVolatile()) ||
4668 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4669 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4671 LN0->getBasePtr(), LN0->getPointerInfo(),
4673 LN0->isVolatile(), LN0->isNonTemporal(),
4674 LN0->getAlignment());
4675 CombineTo(N, ExtLoad);
4676 CombineTo(N0.getNode(),
4677 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4679 ExtLoad.getValue(1));
4680 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4684 if (N0.getOpcode() == ISD::SETCC) {
4685 if (!LegalOperations && VT.isVector()) {
4686 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4687 // Only do this before legalize for now.
4688 EVT N0VT = N0.getOperand(0).getValueType();
4689 EVT EltVT = VT.getVectorElementType();
4690 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4691 DAG.getConstant(1, EltVT));
4692 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4693 // We know that the # elements of the results is the same as the
4694 // # elements of the compare (and the # elements of the compare result
4695 // for that matter). Check to see that they are the same size. If so,
4696 // we know that the element size of the sext'd result matches the
4697 // element size of the compare operands.
4698 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4699 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4701 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4702 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4703 &OneOps[0], OneOps.size()));
4705 // If the desired elements are smaller or larger than the source
4706 // elements we can use a matching integer vector type and then
4707 // truncate/sign extend
4708 EVT MatchingElementType =
4709 EVT::getIntegerVT(*DAG.getContext(),
4710 N0VT.getScalarType().getSizeInBits());
4711 EVT MatchingVectorType =
4712 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4713 N0VT.getVectorNumElements());
4715 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4717 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4718 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4719 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4720 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4721 &OneOps[0], OneOps.size()));
4724 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4726 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4727 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4728 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4729 if (SCC.getNode()) return SCC;
4732 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4733 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4734 isa<ConstantSDNode>(N0.getOperand(1)) &&
4735 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4737 SDValue ShAmt = N0.getOperand(1);
4738 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4739 if (N0.getOpcode() == ISD::SHL) {
4740 SDValue InnerZExt = N0.getOperand(0);
4741 // If the original shl may be shifting out bits, do not perform this
4743 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4744 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4745 if (ShAmtVal > KnownZeroBits)
4749 DebugLoc DL = N->getDebugLoc();
4751 // Ensure that the shift amount is wide enough for the shifted value.
4752 if (VT.getSizeInBits() >= 256)
4753 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4755 return DAG.getNode(N0.getOpcode(), DL, VT,
4756 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4763 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4764 SDValue N0 = N->getOperand(0);
4765 EVT VT = N->getValueType(0);
4767 // fold (aext c1) -> c1
4768 if (isa<ConstantSDNode>(N0))
4769 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4770 // fold (aext (aext x)) -> (aext x)
4771 // fold (aext (zext x)) -> (zext x)
4772 // fold (aext (sext x)) -> (sext x)
4773 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4774 N0.getOpcode() == ISD::ZERO_EXTEND ||
4775 N0.getOpcode() == ISD::SIGN_EXTEND)
4776 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4778 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4779 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4780 if (N0.getOpcode() == ISD::TRUNCATE) {
4781 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4782 if (NarrowLoad.getNode()) {
4783 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4784 if (NarrowLoad.getNode() != N0.getNode()) {
4785 CombineTo(N0.getNode(), NarrowLoad);
4786 // CombineTo deleted the truncate, if needed, but not what's under it.
4789 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4793 // fold (aext (truncate x))
4794 if (N0.getOpcode() == ISD::TRUNCATE) {
4795 SDValue TruncOp = N0.getOperand(0);
4796 if (TruncOp.getValueType() == VT)
4797 return TruncOp; // x iff x size == zext size.
4798 if (TruncOp.getValueType().bitsGT(VT))
4799 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4800 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4803 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4804 // if the trunc is not free.
4805 if (N0.getOpcode() == ISD::AND &&
4806 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4807 N0.getOperand(1).getOpcode() == ISD::Constant &&
4808 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4809 N0.getValueType())) {
4810 SDValue X = N0.getOperand(0).getOperand(0);
4811 if (X.getValueType().bitsLT(VT)) {
4812 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4813 } else if (X.getValueType().bitsGT(VT)) {
4814 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4816 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4817 Mask = Mask.zext(VT.getSizeInBits());
4818 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4819 X, DAG.getConstant(Mask, VT));
4822 // fold (aext (load x)) -> (aext (truncate (extload x)))
4823 // None of the supported targets knows how to perform load and any_ext
4824 // on vectors in one instruction. We only perform this transformation on
4826 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4827 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4828 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4829 bool DoXform = true;
4830 SmallVector<SDNode*, 4> SetCCs;
4831 if (!N0.hasOneUse())
4832 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4834 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4835 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4837 LN0->getBasePtr(), LN0->getPointerInfo(),
4839 LN0->isVolatile(), LN0->isNonTemporal(),
4840 LN0->getAlignment());
4841 CombineTo(N, ExtLoad);
4842 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4843 N0.getValueType(), ExtLoad);
4844 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4845 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4847 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4851 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4852 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4853 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4854 if (N0.getOpcode() == ISD::LOAD &&
4855 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4857 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4858 EVT MemVT = LN0->getMemoryVT();
4859 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4860 VT, LN0->getChain(), LN0->getBasePtr(),
4861 LN0->getPointerInfo(), MemVT,
4862 LN0->isVolatile(), LN0->isNonTemporal(),
4863 LN0->getAlignment());
4864 CombineTo(N, ExtLoad);
4865 CombineTo(N0.getNode(),
4866 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4867 N0.getValueType(), ExtLoad),
4868 ExtLoad.getValue(1));
4869 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4872 if (N0.getOpcode() == ISD::SETCC) {
4873 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4874 // Only do this before legalize for now.
4875 if (VT.isVector() && !LegalOperations) {
4876 EVT N0VT = N0.getOperand(0).getValueType();
4877 // We know that the # elements of the results is the same as the
4878 // # elements of the compare (and the # elements of the compare result
4879 // for that matter). Check to see that they are the same size. If so,
4880 // we know that the element size of the sext'd result matches the
4881 // element size of the compare operands.
4882 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4883 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4885 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4886 // If the desired elements are smaller or larger than the source
4887 // elements we can use a matching integer vector type and then
4888 // truncate/sign extend
4890 EVT MatchingElementType =
4891 EVT::getIntegerVT(*DAG.getContext(),
4892 N0VT.getScalarType().getSizeInBits());
4893 EVT MatchingVectorType =
4894 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4895 N0VT.getVectorNumElements());
4897 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4899 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4900 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4904 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4906 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4907 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4908 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4916 /// GetDemandedBits - See if the specified operand can be simplified with the
4917 /// knowledge that only the bits specified by Mask are used. If so, return the
4918 /// simpler operand, otherwise return a null SDValue.
4919 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4920 switch (V.getOpcode()) {
4922 case ISD::Constant: {
4923 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
4924 assert(CV != 0 && "Const value should be ConstSDNode.");
4925 const APInt &CVal = CV->getAPIntValue();
4926 APInt NewVal = CVal & Mask;
4927 if (NewVal != CVal) {
4928 return DAG.getConstant(NewVal, V.getValueType());
4934 // If the LHS or RHS don't contribute bits to the or, drop them.
4935 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4936 return V.getOperand(1);
4937 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4938 return V.getOperand(0);
4941 // Only look at single-use SRLs.
4942 if (!V.getNode()->hasOneUse())
4944 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4945 // See if we can recursively simplify the LHS.
4946 unsigned Amt = RHSC->getZExtValue();
4948 // Watch out for shift count overflow though.
4949 if (Amt >= Mask.getBitWidth()) break;
4950 APInt NewMask = Mask << Amt;
4951 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4952 if (SimplifyLHS.getNode())
4953 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4954 SimplifyLHS, V.getOperand(1));
4960 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4961 /// bits and then truncated to a narrower type and where N is a multiple
4962 /// of number of bits of the narrower type, transform it to a narrower load
4963 /// from address + N / num of bits of new type. If the result is to be
4964 /// extended, also fold the extension to form a extending load.
4965 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4966 unsigned Opc = N->getOpcode();
4968 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4969 SDValue N0 = N->getOperand(0);
4970 EVT VT = N->getValueType(0);
4973 // This transformation isn't valid for vector loads.
4977 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4979 if (Opc == ISD::SIGN_EXTEND_INREG) {
4980 ExtType = ISD::SEXTLOAD;
4981 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4982 } else if (Opc == ISD::SRL) {
4983 // Another special-case: SRL is basically zero-extending a narrower value.
4984 ExtType = ISD::ZEXTLOAD;
4986 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4987 if (!N01) return SDValue();
4988 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
4989 VT.getSizeInBits() - N01->getZExtValue());
4991 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
4994 unsigned EVTBits = ExtVT.getSizeInBits();
4996 // Do not generate loads of non-round integer types since these can
4997 // be expensive (and would be wrong if the type is not byte sized).
4998 if (!ExtVT.isRound())
5002 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5003 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5004 ShAmt = N01->getZExtValue();
5005 // Is the shift amount a multiple of size of VT?
5006 if ((ShAmt & (EVTBits-1)) == 0) {
5007 N0 = N0.getOperand(0);
5008 // Is the load width a multiple of size of VT?
5009 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
5013 // At this point, we must have a load or else we can't do the transform.
5014 if (!isa<LoadSDNode>(N0)) return SDValue();
5016 // If the shift amount is larger than the input type then we're not
5017 // accessing any of the loaded bytes. If the load was a zextload/extload
5018 // then the result of the shift+trunc is zero/undef (handled elsewhere).
5019 // If the load was a sextload then the result is a splat of the sign bit
5020 // of the extended byte. This is not worth optimizing for.
5021 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
5026 // If the load is shifted left (and the result isn't shifted back right),
5027 // we can fold the truncate through the shift.
5028 unsigned ShLeftAmt = 0;
5029 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
5030 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
5031 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5032 ShLeftAmt = N01->getZExtValue();
5033 N0 = N0.getOperand(0);
5037 // If we haven't found a load, we can't narrow it. Don't transform one with
5038 // multiple uses, this would require adding a new load.
5039 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
5040 // Don't change the width of a volatile load.
5041 cast<LoadSDNode>(N0)->isVolatile())
5044 // Verify that we are actually reducing a load width here.
5045 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
5048 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5049 EVT PtrType = N0.getOperand(1).getValueType();
5051 if (PtrType == MVT::Untyped || PtrType.isExtended())
5052 // It's not possible to generate a constant of extended or untyped type.
5055 // For big endian targets, we need to adjust the offset to the pointer to
5056 // load the correct bytes.
5057 if (TLI.isBigEndian()) {
5058 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
5059 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
5060 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
5063 uint64_t PtrOff = ShAmt / 8;
5064 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
5065 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
5066 PtrType, LN0->getBasePtr(),
5067 DAG.getConstant(PtrOff, PtrType));
5068 AddToWorkList(NewPtr.getNode());
5071 if (ExtType == ISD::NON_EXTLOAD)
5072 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
5073 LN0->getPointerInfo().getWithOffset(PtrOff),
5074 LN0->isVolatile(), LN0->isNonTemporal(),
5075 LN0->isInvariant(), NewAlign);
5077 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
5078 LN0->getPointerInfo().getWithOffset(PtrOff),
5079 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
5082 // Replace the old load's chain with the new load's chain.
5083 WorkListRemover DeadNodes(*this);
5084 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
5086 // Shift the result left, if we've swallowed a left shift.
5087 SDValue Result = Load;
5088 if (ShLeftAmt != 0) {
5089 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
5090 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
5092 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
5093 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
5096 // Return the new loaded value.
5100 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
5101 SDValue N0 = N->getOperand(0);
5102 SDValue N1 = N->getOperand(1);
5103 EVT VT = N->getValueType(0);
5104 EVT EVT = cast<VTSDNode>(N1)->getVT();
5105 unsigned VTBits = VT.getScalarType().getSizeInBits();
5106 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
5108 // fold (sext_in_reg c1) -> c1
5109 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
5110 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
5112 // If the input is already sign extended, just drop the extension.
5113 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
5116 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
5117 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5118 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
5119 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5120 N0.getOperand(0), N1);
5123 // fold (sext_in_reg (sext x)) -> (sext x)
5124 // fold (sext_in_reg (aext x)) -> (sext x)
5125 // if x is small enough.
5126 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
5127 SDValue N00 = N0.getOperand(0);
5128 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
5129 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
5130 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
5133 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
5134 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
5135 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
5137 // fold operands of sext_in_reg based on knowledge that the top bits are not
5139 if (SimplifyDemandedBits(SDValue(N, 0)))
5140 return SDValue(N, 0);
5142 // fold (sext_in_reg (load x)) -> (smaller sextload x)
5143 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
5144 SDValue NarrowLoad = ReduceLoadWidth(N);
5145 if (NarrowLoad.getNode())
5148 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
5149 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
5150 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
5151 if (N0.getOpcode() == ISD::SRL) {
5152 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
5153 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
5154 // We can turn this into an SRA iff the input to the SRL is already sign
5156 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
5157 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
5158 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
5159 N0.getOperand(0), N0.getOperand(1));
5163 // fold (sext_inreg (extload x)) -> (sextload x)
5164 if (ISD::isEXTLoad(N0.getNode()) &&
5165 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5166 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5167 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5168 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5169 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5170 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5172 LN0->getBasePtr(), LN0->getPointerInfo(),
5174 LN0->isVolatile(), LN0->isNonTemporal(),
5175 LN0->getAlignment());
5176 CombineTo(N, ExtLoad);
5177 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5178 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5180 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
5181 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5183 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5184 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5185 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5186 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5187 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5189 LN0->getBasePtr(), LN0->getPointerInfo(),
5191 LN0->isVolatile(), LN0->isNonTemporal(),
5192 LN0->getAlignment());
5193 CombineTo(N, ExtLoad);
5194 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5195 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5198 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
5199 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5200 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5201 N0.getOperand(1), false);
5202 if (BSwap.getNode() != 0)
5203 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5210 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
5211 SDValue N0 = N->getOperand(0);
5212 EVT VT = N->getValueType(0);
5213 bool isLE = TLI.isLittleEndian();
5216 if (N0.getValueType() == N->getValueType(0))
5218 // fold (truncate c1) -> c1
5219 if (isa<ConstantSDNode>(N0))
5220 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
5221 // fold (truncate (truncate x)) -> (truncate x)
5222 if (N0.getOpcode() == ISD::TRUNCATE)
5223 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5224 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
5225 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
5226 N0.getOpcode() == ISD::SIGN_EXTEND ||
5227 N0.getOpcode() == ISD::ANY_EXTEND) {
5228 if (N0.getOperand(0).getValueType().bitsLT(VT))
5229 // if the source is smaller than the dest, we still need an extend
5230 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
5232 else if (N0.getOperand(0).getValueType().bitsGT(VT))
5233 // if the source is larger than the dest, than we just need the truncate
5234 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5236 // if the source and dest are the same type, we can drop both the extend
5237 // and the truncate.
5238 return N0.getOperand(0);
5241 // Fold extract-and-trunc into a narrow extract. For example:
5242 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
5243 // i32 y = TRUNCATE(i64 x)
5245 // v16i8 b = BITCAST (v2i64 val)
5246 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
5248 // Note: We only run this optimization after type legalization (which often
5249 // creates this pattern) and before operation legalization after which
5250 // we need to be more careful about the vector instructions that we generate.
5251 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5252 LegalTypes && !LegalOperations && N0->hasOneUse()) {
5254 EVT VecTy = N0.getOperand(0).getValueType();
5255 EVT ExTy = N0.getValueType();
5256 EVT TrTy = N->getValueType(0);
5258 unsigned NumElem = VecTy.getVectorNumElements();
5259 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
5261 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
5262 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
5264 SDValue EltNo = N0->getOperand(1);
5265 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
5266 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5267 EVT IndexTy = N0->getOperand(1).getValueType();
5268 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
5270 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5271 NVT, N0.getOperand(0));
5273 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
5274 N->getDebugLoc(), TrTy, V,
5275 DAG.getConstant(Index, IndexTy));
5279 // See if we can simplify the input to this truncate through knowledge that
5280 // only the low bits are being used.
5281 // For example "trunc (or (shl x, 8), y)" // -> trunc y
5282 // Currently we only perform this optimization on scalars because vectors
5283 // may have different active low bits.
5284 if (!VT.isVector()) {
5286 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
5287 VT.getSizeInBits()));
5288 if (Shorter.getNode())
5289 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
5291 // fold (truncate (load x)) -> (smaller load x)
5292 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
5293 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
5294 SDValue Reduced = ReduceLoadWidth(N);
5295 if (Reduced.getNode())
5299 // Simplify the operands using demanded-bits information.
5300 if (!VT.isVector() &&
5301 SimplifyDemandedBits(SDValue(N, 0)))
5302 return SDValue(N, 0);
5307 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
5308 SDValue Elt = N->getOperand(i);
5309 if (Elt.getOpcode() != ISD::MERGE_VALUES)
5310 return Elt.getNode();
5311 return Elt.getOperand(Elt.getResNo()).getNode();
5314 /// CombineConsecutiveLoads - build_pair (load, load) -> load
5315 /// if load locations are consecutive.
5316 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
5317 assert(N->getOpcode() == ISD::BUILD_PAIR);
5319 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
5320 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
5321 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
5322 LD1->getPointerInfo().getAddrSpace() !=
5323 LD2->getPointerInfo().getAddrSpace())
5325 EVT LD1VT = LD1->getValueType(0);
5327 if (ISD::isNON_EXTLoad(LD2) &&
5329 // If both are volatile this would reduce the number of volatile loads.
5330 // If one is volatile it might be ok, but play conservative and bail out.
5331 !LD1->isVolatile() &&
5332 !LD2->isVolatile() &&
5333 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
5334 unsigned Align = LD1->getAlignment();
5335 unsigned NewAlign = TLI.getTargetData()->
5336 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5338 if (NewAlign <= Align &&
5339 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
5340 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
5341 LD1->getBasePtr(), LD1->getPointerInfo(),
5342 false, false, false, Align);
5348 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
5349 SDValue N0 = N->getOperand(0);
5350 EVT VT = N->getValueType(0);
5352 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
5353 // Only do this before legalize, since afterward the target may be depending
5354 // on the bitconvert.
5355 // First check to see if this is all constant.
5357 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
5359 bool isSimple = true;
5360 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
5361 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
5362 N0.getOperand(i).getOpcode() != ISD::Constant &&
5363 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
5368 EVT DestEltVT = N->getValueType(0).getVectorElementType();
5369 assert(!DestEltVT.isVector() &&
5370 "Element type of vector ValueType must not be vector!");
5372 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
5375 // If the input is a constant, let getNode fold it.
5376 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
5377 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
5378 if (Res.getNode() != N) {
5379 if (!LegalOperations ||
5380 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
5383 // Folding it resulted in an illegal node, and it's too late to
5384 // do that. Clean up the old node and forego the transformation.
5385 // Ideally this won't happen very often, because instcombine
5386 // and the earlier dagcombine runs (where illegal nodes are
5387 // permitted) should have folded most of them already.
5388 DAG.DeleteNode(Res.getNode());
5392 // (conv (conv x, t1), t2) -> (conv x, t2)
5393 if (N0.getOpcode() == ISD::BITCAST)
5394 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
5397 // fold (conv (load x)) -> (load (conv*)x)
5398 // If the resultant load doesn't need a higher alignment than the original!
5399 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5400 // Do not change the width of a volatile load.
5401 !cast<LoadSDNode>(N0)->isVolatile() &&
5402 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
5403 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5404 unsigned Align = TLI.getTargetData()->
5405 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5406 unsigned OrigAlign = LN0->getAlignment();
5408 if (Align <= OrigAlign) {
5409 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
5410 LN0->getBasePtr(), LN0->getPointerInfo(),
5411 LN0->isVolatile(), LN0->isNonTemporal(),
5412 LN0->isInvariant(), OrigAlign);
5414 CombineTo(N0.getNode(),
5415 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5416 N0.getValueType(), Load),
5422 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5423 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5424 // This often reduces constant pool loads.
5425 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) ||
5426 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) &&
5427 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
5428 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5430 AddToWorkList(NewConv.getNode());
5432 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5433 if (N0.getOpcode() == ISD::FNEG)
5434 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
5435 NewConv, DAG.getConstant(SignBit, VT));
5436 assert(N0.getOpcode() == ISD::FABS);
5437 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
5438 NewConv, DAG.getConstant(~SignBit, VT));
5441 // fold (bitconvert (fcopysign cst, x)) ->
5442 // (or (and (bitconvert x), sign), (and cst, (not sign)))
5443 // Note that we don't handle (copysign x, cst) because this can always be
5444 // folded to an fneg or fabs.
5445 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5446 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5447 VT.isInteger() && !VT.isVector()) {
5448 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5449 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5450 if (isTypeLegal(IntXVT)) {
5451 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5452 IntXVT, N0.getOperand(1));
5453 AddToWorkList(X.getNode());
5455 // If X has a different width than the result/lhs, sext it or truncate it.
5456 unsigned VTWidth = VT.getSizeInBits();
5457 if (OrigXWidth < VTWidth) {
5458 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
5459 AddToWorkList(X.getNode());
5460 } else if (OrigXWidth > VTWidth) {
5461 // To get the sign bit in the right place, we have to shift it right
5462 // before truncating.
5463 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5464 X.getValueType(), X,
5465 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5466 AddToWorkList(X.getNode());
5467 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
5468 AddToWorkList(X.getNode());
5471 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5472 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
5473 X, DAG.getConstant(SignBit, VT));
5474 AddToWorkList(X.getNode());
5476 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5477 VT, N0.getOperand(0));
5478 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
5479 Cst, DAG.getConstant(~SignBit, VT));
5480 AddToWorkList(Cst.getNode());
5482 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
5486 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5487 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5488 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5489 if (CombineLD.getNode())
5496 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5497 EVT VT = N->getValueType(0);
5498 return CombineConsecutiveLoads(N, VT);
5501 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5502 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
5503 /// destination element value type.
5504 SDValue DAGCombiner::
5505 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5506 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5508 // If this is already the right type, we're done.
5509 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5511 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5512 unsigned DstBitSize = DstEltVT.getSizeInBits();
5514 // If this is a conversion of N elements of one type to N elements of another
5515 // type, convert each element. This handles FP<->INT cases.
5516 if (SrcBitSize == DstBitSize) {
5517 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5518 BV->getValueType(0).getVectorNumElements());
5520 // Due to the FP element handling below calling this routine recursively,
5521 // we can end up with a scalar-to-vector node here.
5522 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5523 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5524 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5525 DstEltVT, BV->getOperand(0)));
5527 SmallVector<SDValue, 8> Ops;
5528 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5529 SDValue Op = BV->getOperand(i);
5530 // If the vector element type is not legal, the BUILD_VECTOR operands
5531 // are promoted and implicitly truncated. Make that explicit here.
5532 if (Op.getValueType() != SrcEltVT)
5533 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
5534 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5536 AddToWorkList(Ops.back().getNode());
5538 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5539 &Ops[0], Ops.size());
5542 // Otherwise, we're growing or shrinking the elements. To avoid having to
5543 // handle annoying details of growing/shrinking FP values, we convert them to
5545 if (SrcEltVT.isFloatingPoint()) {
5546 // Convert the input float vector to a int vector where the elements are the
5548 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5549 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5550 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5554 // Now we know the input is an integer vector. If the output is a FP type,
5555 // convert to integer first, then to FP of the right size.
5556 if (DstEltVT.isFloatingPoint()) {
5557 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5558 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5559 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5561 // Next, convert to FP elements of the same size.
5562 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5565 // Okay, we know the src/dst types are both integers of differing types.
5566 // Handling growing first.
5567 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5568 if (SrcBitSize < DstBitSize) {
5569 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5571 SmallVector<SDValue, 8> Ops;
5572 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5573 i += NumInputsPerOutput) {
5574 bool isLE = TLI.isLittleEndian();
5575 APInt NewBits = APInt(DstBitSize, 0);
5576 bool EltIsUndef = true;
5577 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5578 // Shift the previously computed bits over.
5579 NewBits <<= SrcBitSize;
5580 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
5581 if (Op.getOpcode() == ISD::UNDEF) continue;
5584 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
5585 zextOrTrunc(SrcBitSize).zext(DstBitSize);
5589 Ops.push_back(DAG.getUNDEF(DstEltVT));
5591 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
5594 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
5595 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5596 &Ops[0], Ops.size());
5599 // Finally, this must be the case where we are shrinking elements: each input
5600 // turns into multiple outputs.
5601 bool isS2V = ISD::isScalarToVector(BV);
5602 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
5603 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5604 NumOutputsPerInput*BV->getNumOperands());
5605 SmallVector<SDValue, 8> Ops;
5607 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5608 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5609 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
5610 Ops.push_back(DAG.getUNDEF(DstEltVT));
5614 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
5615 getAPIntValue().zextOrTrunc(SrcBitSize);
5617 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
5618 APInt ThisVal = OpVal.trunc(DstBitSize);
5619 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
5620 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
5621 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
5622 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5624 OpVal = OpVal.lshr(DstBitSize);
5627 // For big endian targets, swap the order of the pieces of each element.
5628 if (TLI.isBigEndian())
5629 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
5632 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5633 &Ops[0], Ops.size());
5636 SDValue DAGCombiner::visitFADD(SDNode *N) {
5637 SDValue N0 = N->getOperand(0);
5638 SDValue N1 = N->getOperand(1);
5639 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5640 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5641 EVT VT = N->getValueType(0);
5644 if (VT.isVector()) {
5645 SDValue FoldedVOp = SimplifyVBinOp(N);
5646 if (FoldedVOp.getNode()) return FoldedVOp;
5649 // fold (fadd c1, c2) -> c1 + c2
5650 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5651 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5652 // canonicalize constant to RHS
5653 if (N0CFP && !N1CFP)
5654 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5655 // fold (fadd A, 0) -> A
5656 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5657 N1CFP->getValueAPF().isZero())
5659 // fold (fadd A, (fneg B)) -> (fsub A, B)
5660 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5661 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5662 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5663 GetNegatedExpression(N1, DAG, LegalOperations));
5664 // fold (fadd (fneg A), B) -> (fsub B, A)
5665 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5666 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5667 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
5668 GetNegatedExpression(N0, DAG, LegalOperations));
5670 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5671 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5672 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
5673 isa<ConstantFPSDNode>(N0.getOperand(1)))
5674 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5675 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5676 N0.getOperand(1), N1));
5678 // FADD -> FMA combines:
5679 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
5680 DAG.getTarget().Options.UnsafeFPMath) &&
5681 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) &&
5682 TLI.isOperationLegal(ISD::FMA, VT)) {
5684 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
5685 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) {
5686 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT,
5687 N0.getOperand(0), N0.getOperand(1), N1);
5690 // fold (fadd x, (fmul y, z)) -> (fma x, y, z)
5691 // Note: Commutes FADD operands.
5692 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) {
5693 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT,
5694 N1.getOperand(0), N1.getOperand(1), N0);
5701 SDValue DAGCombiner::visitFSUB(SDNode *N) {
5702 SDValue N0 = N->getOperand(0);
5703 SDValue N1 = N->getOperand(1);
5704 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5705 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5706 EVT VT = N->getValueType(0);
5709 if (VT.isVector()) {
5710 SDValue FoldedVOp = SimplifyVBinOp(N);
5711 if (FoldedVOp.getNode()) return FoldedVOp;
5714 // fold (fsub c1, c2) -> c1-c2
5715 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5716 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5717 // fold (fsub A, 0) -> A
5718 if (DAG.getTarget().Options.UnsafeFPMath &&
5719 N1CFP && N1CFP->getValueAPF().isZero())
5721 // fold (fsub 0, B) -> -B
5722 if (DAG.getTarget().Options.UnsafeFPMath &&
5723 N0CFP && N0CFP->getValueAPF().isZero()) {
5724 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
5725 return GetNegatedExpression(N1, DAG, LegalOperations);
5726 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5727 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
5729 // fold (fsub A, (fneg B)) -> (fadd A, B)
5730 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
5731 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
5732 GetNegatedExpression(N1, DAG, LegalOperations));
5734 // If 'unsafe math' is enabled, fold
5735 // (fsub x, x) -> 0.0 &
5736 // (fsub x, (fadd x, y)) -> (fneg y) &
5737 // (fsub x, (fadd y, x)) -> (fneg y)
5738 if (DAG.getTarget().Options.UnsafeFPMath) {
5740 return DAG.getConstantFP(0.0f, VT);
5742 if (N1.getOpcode() == ISD::FADD) {
5743 SDValue N10 = N1->getOperand(0);
5744 SDValue N11 = N1->getOperand(1);
5746 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI,
5747 &DAG.getTarget().Options))
5748 return GetNegatedExpression(N11, DAG, LegalOperations);
5749 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI,
5750 &DAG.getTarget().Options))
5751 return GetNegatedExpression(N10, DAG, LegalOperations);
5755 // FSUB -> FMA combines:
5756 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
5757 DAG.getTarget().Options.UnsafeFPMath) &&
5758 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) &&
5759 TLI.isOperationLegal(ISD::FMA, VT)) {
5761 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
5762 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) {
5763 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT,
5764 N0.getOperand(0), N0.getOperand(1),
5765 DAG.getNode(ISD::FNEG, N1->getDebugLoc(), VT, N1));
5768 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
5769 // Note: Commutes FSUB operands.
5770 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) {
5771 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT,
5772 DAG.getNode(ISD::FNEG, N1->getDebugLoc(), VT,
5774 N1.getOperand(1), N0);
5781 SDValue DAGCombiner::visitFMUL(SDNode *N) {
5782 SDValue N0 = N->getOperand(0);
5783 SDValue N1 = N->getOperand(1);
5784 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5785 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5786 EVT VT = N->getValueType(0);
5787 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5790 if (VT.isVector()) {
5791 SDValue FoldedVOp = SimplifyVBinOp(N);
5792 if (FoldedVOp.getNode()) return FoldedVOp;
5795 // fold (fmul c1, c2) -> c1*c2
5796 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5797 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
5798 // canonicalize constant to RHS
5799 if (N0CFP && !N1CFP)
5800 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
5801 // fold (fmul A, 0) -> 0
5802 if (DAG.getTarget().Options.UnsafeFPMath &&
5803 N1CFP && N1CFP->getValueAPF().isZero())
5805 // fold (fmul A, 0) -> 0, vector edition.
5806 if (DAG.getTarget().Options.UnsafeFPMath &&
5807 ISD::isBuildVectorAllZeros(N1.getNode()))
5809 // fold (fmul A, 1.0) -> A
5810 if (N1CFP && N1CFP->isExactlyValue(1.0))
5812 // fold (fmul X, 2.0) -> (fadd X, X)
5813 if (N1CFP && N1CFP->isExactlyValue(+2.0))
5814 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
5815 // fold (fmul X, -1.0) -> (fneg X)
5816 if (N1CFP && N1CFP->isExactlyValue(-1.0))
5817 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5818 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
5820 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
5821 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
5822 &DAG.getTarget().Options)) {
5823 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
5824 &DAG.getTarget().Options)) {
5825 // Both can be negated for free, check to see if at least one is cheaper
5827 if (LHSNeg == 2 || RHSNeg == 2)
5828 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5829 GetNegatedExpression(N0, DAG, LegalOperations),
5830 GetNegatedExpression(N1, DAG, LegalOperations));
5834 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
5835 if (DAG.getTarget().Options.UnsafeFPMath &&
5836 N1CFP && N0.getOpcode() == ISD::FMUL &&
5837 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5838 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
5839 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5840 N0.getOperand(1), N1));
5845 SDValue DAGCombiner::visitFMA(SDNode *N) {
5846 SDValue N0 = N->getOperand(0);
5847 SDValue N1 = N->getOperand(1);
5848 SDValue N2 = N->getOperand(2);
5849 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5850 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5851 EVT VT = N->getValueType(0);
5853 if (N0CFP && N0CFP->isExactlyValue(1.0))
5854 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2);
5855 if (N1CFP && N1CFP->isExactlyValue(1.0))
5856 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2);
5858 // Canonicalize (fma c, x, y) -> (fma x, c, y)
5859 if (N0CFP && !N1CFP)
5860 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2);
5865 SDValue DAGCombiner::visitFDIV(SDNode *N) {
5866 SDValue N0 = N->getOperand(0);
5867 SDValue N1 = N->getOperand(1);
5868 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5869 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5870 EVT VT = N->getValueType(0);
5871 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5874 if (VT.isVector()) {
5875 SDValue FoldedVOp = SimplifyVBinOp(N);
5876 if (FoldedVOp.getNode()) return FoldedVOp;
5879 // fold (fdiv c1, c2) -> c1/c2
5880 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5881 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
5883 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
5884 if (N1CFP && VT != MVT::ppcf128 && DAG.getTarget().Options.UnsafeFPMath) {
5885 // Compute the reciprocal 1.0 / c2.
5886 APFloat N1APF = N1CFP->getValueAPF();
5887 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
5888 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
5889 // Only do the transform if the reciprocal is a legal fp immediate that
5890 // isn't too nasty (eg NaN, denormal, ...).
5891 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
5892 (!LegalOperations ||
5893 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
5894 // backend)... we should handle this gracefully after Legalize.
5895 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
5896 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
5897 TLI.isFPImmLegal(Recip, VT)))
5898 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0,
5899 DAG.getConstantFP(Recip, VT));
5902 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
5903 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
5904 &DAG.getTarget().Options)) {
5905 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
5906 &DAG.getTarget().Options)) {
5907 // Both can be negated for free, check to see if at least one is cheaper
5909 if (LHSNeg == 2 || RHSNeg == 2)
5910 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
5911 GetNegatedExpression(N0, DAG, LegalOperations),
5912 GetNegatedExpression(N1, DAG, LegalOperations));
5919 SDValue DAGCombiner::visitFREM(SDNode *N) {
5920 SDValue N0 = N->getOperand(0);
5921 SDValue N1 = N->getOperand(1);
5922 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5923 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5924 EVT VT = N->getValueType(0);
5926 // fold (frem c1, c2) -> fmod(c1,c2)
5927 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5928 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
5933 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
5934 SDValue N0 = N->getOperand(0);
5935 SDValue N1 = N->getOperand(1);
5936 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5937 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5938 EVT VT = N->getValueType(0);
5940 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
5941 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
5944 const APFloat& V = N1CFP->getValueAPF();
5945 // copysign(x, c1) -> fabs(x) iff ispos(c1)
5946 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
5947 if (!V.isNegative()) {
5948 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
5949 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5951 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5952 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
5953 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
5957 // copysign(fabs(x), y) -> copysign(x, y)
5958 // copysign(fneg(x), y) -> copysign(x, y)
5959 // copysign(copysign(x,z), y) -> copysign(x, y)
5960 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
5961 N0.getOpcode() == ISD::FCOPYSIGN)
5962 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5963 N0.getOperand(0), N1);
5965 // copysign(x, abs(y)) -> abs(x)
5966 if (N1.getOpcode() == ISD::FABS)
5967 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5969 // copysign(x, copysign(y,z)) -> copysign(x, z)
5970 if (N1.getOpcode() == ISD::FCOPYSIGN)
5971 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5972 N0, N1.getOperand(1));
5974 // copysign(x, fp_extend(y)) -> copysign(x, y)
5975 // copysign(x, fp_round(y)) -> copysign(x, y)
5976 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
5977 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5978 N0, N1.getOperand(0));
5983 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
5984 SDValue N0 = N->getOperand(0);
5985 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5986 EVT VT = N->getValueType(0);
5987 EVT OpVT = N0.getValueType();
5989 // fold (sint_to_fp c1) -> c1fp
5990 if (N0C && OpVT != MVT::ppcf128 &&
5991 // ...but only if the target supports immediate floating-point values
5992 (!LegalOperations ||
5993 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5994 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5996 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
5997 // but UINT_TO_FP is legal on this target, try to convert.
5998 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
5999 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
6000 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
6001 if (DAG.SignBitIsZero(N0))
6002 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
6005 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6006 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
6008 (!LegalOperations ||
6009 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6011 { N0.getOperand(0), N0.getOperand(1),
6012 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT),
6014 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6017 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
6018 // (select_cc x, y, 1.0, 0.0,, cc)
6019 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
6020 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
6021 (!LegalOperations ||
6022 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6024 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
6025 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT),
6026 N0.getOperand(0).getOperand(2) };
6027 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6033 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
6034 SDValue N0 = N->getOperand(0);
6035 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6036 EVT VT = N->getValueType(0);
6037 EVT OpVT = N0.getValueType();
6039 // fold (uint_to_fp c1) -> c1fp
6040 if (N0C && OpVT != MVT::ppcf128 &&
6041 // ...but only if the target supports immediate floating-point values
6042 (!LegalOperations ||
6043 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6044 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
6046 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
6047 // but SINT_TO_FP is legal on this target, try to convert.
6048 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
6049 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
6050 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
6051 if (DAG.SignBitIsZero(N0))
6052 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
6055 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6056 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
6057 (!LegalOperations ||
6058 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6060 { N0.getOperand(0), N0.getOperand(1),
6061 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT),
6063 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6070 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
6071 SDValue N0 = N->getOperand(0);
6072 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6073 EVT VT = N->getValueType(0);
6075 // fold (fp_to_sint c1fp) -> c1
6077 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
6082 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
6083 SDValue N0 = N->getOperand(0);
6084 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6085 EVT VT = N->getValueType(0);
6087 // fold (fp_to_uint c1fp) -> c1
6088 if (N0CFP && VT != MVT::ppcf128)
6089 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
6094 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
6095 SDValue N0 = N->getOperand(0);
6096 SDValue N1 = N->getOperand(1);
6097 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6098 EVT VT = N->getValueType(0);
6100 // fold (fp_round c1fp) -> c1fp
6101 if (N0CFP && N0.getValueType() != MVT::ppcf128)
6102 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
6104 // fold (fp_round (fp_extend x)) -> x
6105 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
6106 return N0.getOperand(0);
6108 // fold (fp_round (fp_round x)) -> (fp_round x)
6109 if (N0.getOpcode() == ISD::FP_ROUND) {
6110 // This is a value preserving truncation if both round's are.
6111 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
6112 N0.getNode()->getConstantOperandVal(1) == 1;
6113 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
6114 DAG.getIntPtrConstant(IsTrunc));
6117 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
6118 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
6119 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
6120 N0.getOperand(0), N1);
6121 AddToWorkList(Tmp.getNode());
6122 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6123 Tmp, N0.getOperand(1));
6129 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
6130 SDValue N0 = N->getOperand(0);
6131 EVT VT = N->getValueType(0);
6132 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
6133 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6135 // fold (fp_round_inreg c1fp) -> c1fp
6136 if (N0CFP && isTypeLegal(EVT)) {
6137 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
6138 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
6144 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
6145 SDValue N0 = N->getOperand(0);
6146 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6147 EVT VT = N->getValueType(0);
6149 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
6150 if (N->hasOneUse() &&
6151 N->use_begin()->getOpcode() == ISD::FP_ROUND)
6154 // fold (fp_extend c1fp) -> c1fp
6155 if (N0CFP && VT != MVT::ppcf128)
6156 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
6158 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
6160 if (N0.getOpcode() == ISD::FP_ROUND
6161 && N0.getNode()->getConstantOperandVal(1) == 1) {
6162 SDValue In = N0.getOperand(0);
6163 if (In.getValueType() == VT) return In;
6164 if (VT.bitsLT(In.getValueType()))
6165 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
6166 In, N0.getOperand(1));
6167 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
6170 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
6171 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
6172 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6173 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
6174 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6175 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
6177 LN0->getBasePtr(), LN0->getPointerInfo(),
6179 LN0->isVolatile(), LN0->isNonTemporal(),
6180 LN0->getAlignment());
6181 CombineTo(N, ExtLoad);
6182 CombineTo(N0.getNode(),
6183 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
6184 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
6185 ExtLoad.getValue(1));
6186 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6192 SDValue DAGCombiner::visitFNEG(SDNode *N) {
6193 SDValue N0 = N->getOperand(0);
6194 EVT VT = N->getValueType(0);
6196 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
6197 &DAG.getTarget().Options))
6198 return GetNegatedExpression(N0, DAG, LegalOperations);
6200 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
6201 // constant pool values.
6202 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST &&
6204 N0.getNode()->hasOneUse() &&
6205 N0.getOperand(0).getValueType().isInteger()) {
6206 SDValue Int = N0.getOperand(0);
6207 EVT IntVT = Int.getValueType();
6208 if (IntVT.isInteger() && !IntVT.isVector()) {
6209 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
6210 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6211 AddToWorkList(Int.getNode());
6212 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6220 SDValue DAGCombiner::visitFABS(SDNode *N) {
6221 SDValue N0 = N->getOperand(0);
6222 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6223 EVT VT = N->getValueType(0);
6225 // fold (fabs c1) -> fabs(c1)
6226 if (N0CFP && VT != MVT::ppcf128)
6227 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6228 // fold (fabs (fabs x)) -> (fabs x)
6229 if (N0.getOpcode() == ISD::FABS)
6230 return N->getOperand(0);
6231 // fold (fabs (fneg x)) -> (fabs x)
6232 // fold (fabs (fcopysign x, y)) -> (fabs x)
6233 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
6234 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
6236 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
6237 // constant pool values.
6238 if (!TLI.isFAbsFree(VT) &&
6239 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
6240 N0.getOperand(0).getValueType().isInteger() &&
6241 !N0.getOperand(0).getValueType().isVector()) {
6242 SDValue Int = N0.getOperand(0);
6243 EVT IntVT = Int.getValueType();
6244 if (IntVT.isInteger() && !IntVT.isVector()) {
6245 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
6246 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6247 AddToWorkList(Int.getNode());
6248 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6249 N->getValueType(0), Int);
6256 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
6257 SDValue Chain = N->getOperand(0);
6258 SDValue N1 = N->getOperand(1);
6259 SDValue N2 = N->getOperand(2);
6261 // If N is a constant we could fold this into a fallthrough or unconditional
6262 // branch. However that doesn't happen very often in normal code, because
6263 // Instcombine/SimplifyCFG should have handled the available opportunities.
6264 // If we did this folding here, it would be necessary to update the
6265 // MachineBasicBlock CFG, which is awkward.
6267 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
6269 if (N1.getOpcode() == ISD::SETCC &&
6270 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
6271 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6272 Chain, N1.getOperand(2),
6273 N1.getOperand(0), N1.getOperand(1), N2);
6276 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
6277 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
6278 (N1.getOperand(0).hasOneUse() &&
6279 N1.getOperand(0).getOpcode() == ISD::SRL))) {
6281 if (N1.getOpcode() == ISD::TRUNCATE) {
6282 // Look pass the truncate.
6283 Trunc = N1.getNode();
6284 N1 = N1.getOperand(0);
6287 // Match this pattern so that we can generate simpler code:
6290 // %b = and i32 %a, 2
6291 // %c = srl i32 %b, 1
6292 // brcond i32 %c ...
6297 // %b = and i32 %a, 2
6298 // %c = setcc eq %b, 0
6301 // This applies only when the AND constant value has one bit set and the
6302 // SRL constant is equal to the log2 of the AND constant. The back-end is
6303 // smart enough to convert the result into a TEST/JMP sequence.
6304 SDValue Op0 = N1.getOperand(0);
6305 SDValue Op1 = N1.getOperand(1);
6307 if (Op0.getOpcode() == ISD::AND &&
6308 Op1.getOpcode() == ISD::Constant) {
6309 SDValue AndOp1 = Op0.getOperand(1);
6311 if (AndOp1.getOpcode() == ISD::Constant) {
6312 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
6314 if (AndConst.isPowerOf2() &&
6315 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
6317 DAG.getSetCC(N->getDebugLoc(),
6318 TLI.getSetCCResultType(Op0.getValueType()),
6319 Op0, DAG.getConstant(0, Op0.getValueType()),
6322 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6323 MVT::Other, Chain, SetCC, N2);
6324 // Don't add the new BRCond into the worklist or else SimplifySelectCC
6325 // will convert it back to (X & C1) >> C2.
6326 CombineTo(N, NewBRCond, false);
6327 // Truncate is dead.
6329 removeFromWorkList(Trunc);
6330 DAG.DeleteNode(Trunc);
6332 // Replace the uses of SRL with SETCC
6333 WorkListRemover DeadNodes(*this);
6334 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6335 removeFromWorkList(N1.getNode());
6336 DAG.DeleteNode(N1.getNode());
6337 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6343 // Restore N1 if the above transformation doesn't match.
6344 N1 = N->getOperand(1);
6347 // Transform br(xor(x, y)) -> br(x != y)
6348 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
6349 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
6350 SDNode *TheXor = N1.getNode();
6351 SDValue Op0 = TheXor->getOperand(0);
6352 SDValue Op1 = TheXor->getOperand(1);
6353 if (Op0.getOpcode() == Op1.getOpcode()) {
6354 // Avoid missing important xor optimizations.
6355 SDValue Tmp = visitXOR(TheXor);
6356 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
6357 DEBUG(dbgs() << "\nReplacing.8 ";
6359 dbgs() << "\nWith: ";
6360 Tmp.getNode()->dump(&DAG);
6362 WorkListRemover DeadNodes(*this);
6363 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
6364 removeFromWorkList(TheXor);
6365 DAG.DeleteNode(TheXor);
6366 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6367 MVT::Other, Chain, Tmp, N2);
6371 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
6373 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
6374 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
6375 Op0.getOpcode() == ISD::XOR) {
6376 TheXor = Op0.getNode();
6380 EVT SetCCVT = N1.getValueType();
6382 SetCCVT = TLI.getSetCCResultType(SetCCVT);
6383 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
6386 Equal ? ISD::SETEQ : ISD::SETNE);
6387 // Replace the uses of XOR with SETCC
6388 WorkListRemover DeadNodes(*this);
6389 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6390 removeFromWorkList(N1.getNode());
6391 DAG.DeleteNode(N1.getNode());
6392 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6393 MVT::Other, Chain, SetCC, N2);
6400 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
6402 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
6403 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
6404 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
6406 // If N is a constant we could fold this into a fallthrough or unconditional
6407 // branch. However that doesn't happen very often in normal code, because
6408 // Instcombine/SimplifyCFG should have handled the available opportunities.
6409 // If we did this folding here, it would be necessary to update the
6410 // MachineBasicBlock CFG, which is awkward.
6412 // Use SimplifySetCC to simplify SETCC's.
6413 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
6414 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
6416 if (Simp.getNode()) AddToWorkList(Simp.getNode());
6418 // fold to a simpler setcc
6419 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
6420 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6421 N->getOperand(0), Simp.getOperand(2),
6422 Simp.getOperand(0), Simp.getOperand(1),
6428 /// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
6429 /// uses N as its base pointer and that N may be folded in the load / store
6430 /// addressing mode.
6431 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
6433 const TargetLowering &TLI) {
6435 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
6436 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
6438 VT = Use->getValueType(0);
6439 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
6440 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
6442 VT = ST->getValue().getValueType();
6446 TargetLowering::AddrMode AM;
6447 if (N->getOpcode() == ISD::ADD) {
6448 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6451 AM.BaseOffs = Offset->getSExtValue();
6455 } else if (N->getOpcode() == ISD::SUB) {
6456 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6459 AM.BaseOffs = -Offset->getSExtValue();
6466 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
6469 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
6470 /// pre-indexed load / store when the base pointer is an add or subtract
6471 /// and it has other uses besides the load / store. After the
6472 /// transformation, the new indexed load / store has effectively folded
6473 /// the add / subtract in and all of its other uses are redirected to the
6474 /// new load / store.
6475 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
6476 if (Level < AfterLegalizeDAG)
6482 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6483 if (LD->isIndexed())
6485 VT = LD->getMemoryVT();
6486 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
6487 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
6489 Ptr = LD->getBasePtr();
6490 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6491 if (ST->isIndexed())
6493 VT = ST->getMemoryVT();
6494 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
6495 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
6497 Ptr = ST->getBasePtr();
6503 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
6504 // out. There is no reason to make this a preinc/predec.
6505 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
6506 Ptr.getNode()->hasOneUse())
6509 // Ask the target to do addressing mode selection.
6512 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6513 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
6515 // Don't create a indexed load / store with zero offset.
6516 if (isa<ConstantSDNode>(Offset) &&
6517 cast<ConstantSDNode>(Offset)->isNullValue())
6520 // Try turning it into a pre-indexed load / store except when:
6521 // 1) The new base ptr is a frame index.
6522 // 2) If N is a store and the new base ptr is either the same as or is a
6523 // predecessor of the value being stored.
6524 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
6525 // that would create a cycle.
6526 // 4) All uses are load / store ops that use it as old base ptr.
6528 // Check #1. Preinc'ing a frame index would require copying the stack pointer
6529 // (plus the implicit offset) to a register to preinc anyway.
6530 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6535 SDValue Val = cast<StoreSDNode>(N)->getValue();
6536 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
6540 // Now check for #3 and #4.
6541 bool RealUse = false;
6543 // Caches for hasPredecessorHelper
6544 SmallPtrSet<const SDNode *, 32> Visited;
6545 SmallVector<const SDNode *, 16> Worklist;
6547 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6548 E = Ptr.getNode()->use_end(); I != E; ++I) {
6552 if (N->hasPredecessorHelper(Use, Visited, Worklist))
6555 // If Ptr may be folded in addressing mode of other use, then it's
6556 // not profitable to do this transformation.
6557 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
6566 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6567 BasePtr, Offset, AM);
6569 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6570 BasePtr, Offset, AM);
6573 DEBUG(dbgs() << "\nReplacing.4 ";
6575 dbgs() << "\nWith: ";
6576 Result.getNode()->dump(&DAG);
6578 WorkListRemover DeadNodes(*this);
6580 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
6581 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
6583 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
6586 // Finally, since the node is now dead, remove it from the graph.
6589 // Replace the uses of Ptr with uses of the updated base value.
6590 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
6591 removeFromWorkList(Ptr.getNode());
6592 DAG.DeleteNode(Ptr.getNode());
6597 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
6598 /// add / sub of the base pointer node into a post-indexed load / store.
6599 /// The transformation folded the add / subtract into the new indexed
6600 /// load / store effectively and all of its uses are redirected to the
6601 /// new load / store.
6602 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
6603 if (Level < AfterLegalizeDAG)
6609 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6610 if (LD->isIndexed())
6612 VT = LD->getMemoryVT();
6613 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
6614 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
6616 Ptr = LD->getBasePtr();
6617 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6618 if (ST->isIndexed())
6620 VT = ST->getMemoryVT();
6621 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
6622 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
6624 Ptr = ST->getBasePtr();
6630 if (Ptr.getNode()->hasOneUse())
6633 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6634 E = Ptr.getNode()->use_end(); I != E; ++I) {
6637 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
6642 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6643 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
6644 // Don't create a indexed load / store with zero offset.
6645 if (isa<ConstantSDNode>(Offset) &&
6646 cast<ConstantSDNode>(Offset)->isNullValue())
6649 // Try turning it into a post-indexed load / store except when
6650 // 1) All uses are load / store ops that use it as base ptr (and
6651 // it may be folded as addressing mmode).
6652 // 2) Op must be independent of N, i.e. Op is neither a predecessor
6653 // nor a successor of N. Otherwise, if Op is folded that would
6656 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6660 bool TryNext = false;
6661 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
6662 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
6664 if (Use == Ptr.getNode())
6667 // If all the uses are load / store addresses, then don't do the
6669 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
6670 bool RealUse = false;
6671 for (SDNode::use_iterator III = Use->use_begin(),
6672 EEE = Use->use_end(); III != EEE; ++III) {
6673 SDNode *UseUse = *III;
6674 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
6689 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
6690 SDValue Result = isLoad
6691 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6692 BasePtr, Offset, AM)
6693 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6694 BasePtr, Offset, AM);
6697 DEBUG(dbgs() << "\nReplacing.5 ";
6699 dbgs() << "\nWith: ";
6700 Result.getNode()->dump(&DAG);
6702 WorkListRemover DeadNodes(*this);
6704 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
6705 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
6707 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
6710 // Finally, since the node is now dead, remove it from the graph.
6713 // Replace the uses of Use with uses of the updated base value.
6714 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
6715 Result.getValue(isLoad ? 1 : 0));
6716 removeFromWorkList(Op);
6726 SDValue DAGCombiner::visitLOAD(SDNode *N) {
6727 LoadSDNode *LD = cast<LoadSDNode>(N);
6728 SDValue Chain = LD->getChain();
6729 SDValue Ptr = LD->getBasePtr();
6731 // If load is not volatile and there are no uses of the loaded value (and
6732 // the updated indexed value in case of indexed loads), change uses of the
6733 // chain value into uses of the chain input (i.e. delete the dead load).
6734 if (!LD->isVolatile()) {
6735 if (N->getValueType(1) == MVT::Other) {
6737 if (!N->hasAnyUseOfValue(0)) {
6738 // It's not safe to use the two value CombineTo variant here. e.g.
6739 // v1, chain2 = load chain1, loc
6740 // v2, chain3 = load chain2, loc
6742 // Now we replace use of chain2 with chain1. This makes the second load
6743 // isomorphic to the one we are deleting, and thus makes this load live.
6744 DEBUG(dbgs() << "\nReplacing.6 ";
6746 dbgs() << "\nWith chain: ";
6747 Chain.getNode()->dump(&DAG);
6749 WorkListRemover DeadNodes(*this);
6750 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
6752 if (N->use_empty()) {
6753 removeFromWorkList(N);
6757 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6761 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
6762 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) {
6763 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
6764 DEBUG(dbgs() << "\nReplacing.7 ";
6766 dbgs() << "\nWith: ";
6767 Undef.getNode()->dump(&DAG);
6768 dbgs() << " and 2 other values\n");
6769 WorkListRemover DeadNodes(*this);
6770 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
6771 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
6772 DAG.getUNDEF(N->getValueType(1)));
6773 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
6774 removeFromWorkList(N);
6776 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6781 // If this load is directly stored, replace the load value with the stored
6783 // TODO: Handle store large -> read small portion.
6784 // TODO: Handle TRUNCSTORE/LOADEXT
6785 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
6786 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
6787 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
6788 if (PrevST->getBasePtr() == Ptr &&
6789 PrevST->getValue().getValueType() == N->getValueType(0))
6790 return CombineTo(N, Chain.getOperand(1), Chain);
6794 // Try to infer better alignment information than the load already has.
6795 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
6796 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6797 if (Align > LD->getAlignment())
6798 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
6799 LD->getValueType(0),
6800 Chain, Ptr, LD->getPointerInfo(),
6802 LD->isVolatile(), LD->isNonTemporal(), Align);
6807 // Walk up chain skipping non-aliasing memory nodes.
6808 SDValue BetterChain = FindBetterChain(N, Chain);
6810 // If there is a better chain.
6811 if (Chain != BetterChain) {
6814 // Replace the chain to void dependency.
6815 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
6816 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
6817 BetterChain, Ptr, LD->getPointerInfo(),
6818 LD->isVolatile(), LD->isNonTemporal(),
6819 LD->isInvariant(), LD->getAlignment());
6821 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
6822 LD->getValueType(0),
6823 BetterChain, Ptr, LD->getPointerInfo(),
6826 LD->isNonTemporal(),
6827 LD->getAlignment());
6830 // Create token factor to keep old chain connected.
6831 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6832 MVT::Other, Chain, ReplLoad.getValue(1));
6834 // Make sure the new and old chains are cleaned up.
6835 AddToWorkList(Token.getNode());
6837 // Replace uses with load result and token factor. Don't add users
6839 return CombineTo(N, ReplLoad.getValue(0), Token, false);
6843 // Try transforming N to an indexed load.
6844 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6845 return SDValue(N, 0);
6850 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
6851 /// load is having specific bytes cleared out. If so, return the byte size
6852 /// being masked out and the shift amount.
6853 static std::pair<unsigned, unsigned>
6854 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
6855 std::pair<unsigned, unsigned> Result(0, 0);
6857 // Check for the structure we're looking for.
6858 if (V->getOpcode() != ISD::AND ||
6859 !isa<ConstantSDNode>(V->getOperand(1)) ||
6860 !ISD::isNormalLoad(V->getOperand(0).getNode()))
6863 // Check the chain and pointer.
6864 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
6865 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
6867 // The store should be chained directly to the load or be an operand of a
6869 if (LD == Chain.getNode())
6871 else if (Chain->getOpcode() != ISD::TokenFactor)
6872 return Result; // Fail.
6875 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
6876 if (Chain->getOperand(i).getNode() == LD) {
6880 if (!isOk) return Result;
6883 // This only handles simple types.
6884 if (V.getValueType() != MVT::i16 &&
6885 V.getValueType() != MVT::i32 &&
6886 V.getValueType() != MVT::i64)
6889 // Check the constant mask. Invert it so that the bits being masked out are
6890 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
6891 // follow the sign bit for uniformity.
6892 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
6893 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
6894 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
6895 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
6896 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
6897 if (NotMaskLZ == 64) return Result; // All zero mask.
6899 // See if we have a continuous run of bits. If so, we have 0*1+0*
6900 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
6903 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
6904 if (V.getValueType() != MVT::i64 && NotMaskLZ)
6905 NotMaskLZ -= 64-V.getValueSizeInBits();
6907 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
6908 switch (MaskedBytes) {
6912 default: return Result; // All one mask, or 5-byte mask.
6915 // Verify that the first bit starts at a multiple of mask so that the access
6916 // is aligned the same as the access width.
6917 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
6919 Result.first = MaskedBytes;
6920 Result.second = NotMaskTZ/8;
6925 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
6926 /// provides a value as specified by MaskInfo. If so, replace the specified
6927 /// store with a narrower store of truncated IVal.
6929 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
6930 SDValue IVal, StoreSDNode *St,
6932 unsigned NumBytes = MaskInfo.first;
6933 unsigned ByteShift = MaskInfo.second;
6934 SelectionDAG &DAG = DC->getDAG();
6936 // Check to see if IVal is all zeros in the part being masked in by the 'or'
6937 // that uses this. If not, this is not a replacement.
6938 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
6939 ByteShift*8, (ByteShift+NumBytes)*8);
6940 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
6942 // Check that it is legal on the target to do this. It is legal if the new
6943 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
6945 MVT VT = MVT::getIntegerVT(NumBytes*8);
6946 if (!DC->isTypeLegal(VT))
6949 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
6950 // shifted by ByteShift and truncated down to NumBytes.
6952 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
6953 DAG.getConstant(ByteShift*8,
6954 DC->getShiftAmountTy(IVal.getValueType())));
6956 // Figure out the offset for the store and the alignment of the access.
6958 unsigned NewAlign = St->getAlignment();
6960 if (DAG.getTargetLoweringInfo().isLittleEndian())
6961 StOffset = ByteShift;
6963 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
6965 SDValue Ptr = St->getBasePtr();
6967 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
6968 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
6969 NewAlign = MinAlign(NewAlign, StOffset);
6972 // Truncate down to the new size.
6973 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
6976 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
6977 St->getPointerInfo().getWithOffset(StOffset),
6978 false, false, NewAlign).getNode();
6982 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
6983 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
6984 /// of the loaded bits, try narrowing the load and store if it would end up
6985 /// being a win for performance or code size.
6986 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
6987 StoreSDNode *ST = cast<StoreSDNode>(N);
6988 if (ST->isVolatile())
6991 SDValue Chain = ST->getChain();
6992 SDValue Value = ST->getValue();
6993 SDValue Ptr = ST->getBasePtr();
6994 EVT VT = Value.getValueType();
6996 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
6999 unsigned Opc = Value.getOpcode();
7001 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
7002 // is a byte mask indicating a consecutive number of bytes, check to see if
7003 // Y is known to provide just those bytes. If so, we try to replace the
7004 // load + replace + store sequence with a single (narrower) store, which makes
7006 if (Opc == ISD::OR) {
7007 std::pair<unsigned, unsigned> MaskedLoad;
7008 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
7009 if (MaskedLoad.first)
7010 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
7011 Value.getOperand(1), ST,this))
7012 return SDValue(NewST, 0);
7014 // Or is commutative, so try swapping X and Y.
7015 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
7016 if (MaskedLoad.first)
7017 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
7018 Value.getOperand(0), ST,this))
7019 return SDValue(NewST, 0);
7022 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
7023 Value.getOperand(1).getOpcode() != ISD::Constant)
7026 SDValue N0 = Value.getOperand(0);
7027 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7028 Chain == SDValue(N0.getNode(), 1)) {
7029 LoadSDNode *LD = cast<LoadSDNode>(N0);
7030 if (LD->getBasePtr() != Ptr ||
7031 LD->getPointerInfo().getAddrSpace() !=
7032 ST->getPointerInfo().getAddrSpace())
7035 // Find the type to narrow it the load / op / store to.
7036 SDValue N1 = Value.getOperand(1);
7037 unsigned BitWidth = N1.getValueSizeInBits();
7038 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
7039 if (Opc == ISD::AND)
7040 Imm ^= APInt::getAllOnesValue(BitWidth);
7041 if (Imm == 0 || Imm.isAllOnesValue())
7043 unsigned ShAmt = Imm.countTrailingZeros();
7044 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
7045 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
7046 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
7047 while (NewBW < BitWidth &&
7048 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
7049 TLI.isNarrowingProfitable(VT, NewVT))) {
7050 NewBW = NextPowerOf2(NewBW);
7051 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
7053 if (NewBW >= BitWidth)
7056 // If the lsb changed does not start at the type bitwidth boundary,
7057 // start at the previous one.
7059 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
7060 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
7061 if ((Imm & Mask) == Imm) {
7062 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
7063 if (Opc == ISD::AND)
7064 NewImm ^= APInt::getAllOnesValue(NewBW);
7065 uint64_t PtrOff = ShAmt / 8;
7066 // For big endian targets, we need to adjust the offset to the pointer to
7067 // load the correct bytes.
7068 if (TLI.isBigEndian())
7069 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
7071 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
7072 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
7073 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
7076 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
7077 Ptr.getValueType(), Ptr,
7078 DAG.getConstant(PtrOff, Ptr.getValueType()));
7079 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
7080 LD->getChain(), NewPtr,
7081 LD->getPointerInfo().getWithOffset(PtrOff),
7082 LD->isVolatile(), LD->isNonTemporal(),
7083 LD->isInvariant(), NewAlign);
7084 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
7085 DAG.getConstant(NewImm, NewVT));
7086 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
7088 ST->getPointerInfo().getWithOffset(PtrOff),
7089 false, false, NewAlign);
7091 AddToWorkList(NewPtr.getNode());
7092 AddToWorkList(NewLD.getNode());
7093 AddToWorkList(NewVal.getNode());
7094 WorkListRemover DeadNodes(*this);
7095 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
7104 /// TransformFPLoadStorePair - For a given floating point load / store pair,
7105 /// if the load value isn't used by any other operations, then consider
7106 /// transforming the pair to integer load / store operations if the target
7107 /// deems the transformation profitable.
7108 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
7109 StoreSDNode *ST = cast<StoreSDNode>(N);
7110 SDValue Chain = ST->getChain();
7111 SDValue Value = ST->getValue();
7112 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
7113 Value.hasOneUse() &&
7114 Chain == SDValue(Value.getNode(), 1)) {
7115 LoadSDNode *LD = cast<LoadSDNode>(Value);
7116 EVT VT = LD->getMemoryVT();
7117 if (!VT.isFloatingPoint() ||
7118 VT != ST->getMemoryVT() ||
7119 LD->isNonTemporal() ||
7120 ST->isNonTemporal() ||
7121 LD->getPointerInfo().getAddrSpace() != 0 ||
7122 ST->getPointerInfo().getAddrSpace() != 0)
7125 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
7126 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
7127 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
7128 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
7129 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
7132 unsigned LDAlign = LD->getAlignment();
7133 unsigned STAlign = ST->getAlignment();
7134 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
7135 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy);
7136 if (LDAlign < ABIAlign || STAlign < ABIAlign)
7139 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
7140 LD->getChain(), LD->getBasePtr(),
7141 LD->getPointerInfo(),
7142 false, false, false, LDAlign);
7144 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
7145 NewLD, ST->getBasePtr(),
7146 ST->getPointerInfo(),
7147 false, false, STAlign);
7149 AddToWorkList(NewLD.getNode());
7150 AddToWorkList(NewST.getNode());
7151 WorkListRemover DeadNodes(*this);
7152 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
7160 SDValue DAGCombiner::visitSTORE(SDNode *N) {
7161 StoreSDNode *ST = cast<StoreSDNode>(N);
7162 SDValue Chain = ST->getChain();
7163 SDValue Value = ST->getValue();
7164 SDValue Ptr = ST->getBasePtr();
7166 // If this is a store of a bit convert, store the input value if the
7167 // resultant store does not need a higher alignment than the original.
7168 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
7169 ST->isUnindexed()) {
7170 unsigned OrigAlign = ST->getAlignment();
7171 EVT SVT = Value.getOperand(0).getValueType();
7172 unsigned Align = TLI.getTargetData()->
7173 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
7174 if (Align <= OrigAlign &&
7175 ((!LegalOperations && !ST->isVolatile()) ||
7176 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
7177 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
7178 Ptr, ST->getPointerInfo(), ST->isVolatile(),
7179 ST->isNonTemporal(), OrigAlign);
7182 // Turn 'store undef, Ptr' -> nothing.
7183 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
7186 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
7187 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
7188 // NOTE: If the original store is volatile, this transform must not increase
7189 // the number of stores. For example, on x86-32 an f64 can be stored in one
7190 // processor operation but an i64 (which is not legal) requires two. So the
7191 // transform should not be done in this case.
7192 if (Value.getOpcode() != ISD::TargetConstantFP) {
7194 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
7195 default: llvm_unreachable("Unknown FP type");
7196 case MVT::f16: // We don't do this for these yet.
7202 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
7203 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
7204 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
7205 bitcastToAPInt().getZExtValue(), MVT::i32);
7206 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
7207 Ptr, ST->getPointerInfo(), ST->isVolatile(),
7208 ST->isNonTemporal(), ST->getAlignment());
7212 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
7213 !ST->isVolatile()) ||
7214 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
7215 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
7216 getZExtValue(), MVT::i64);
7217 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
7218 Ptr, ST->getPointerInfo(), ST->isVolatile(),
7219 ST->isNonTemporal(), ST->getAlignment());
7222 if (!ST->isVolatile() &&
7223 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
7224 // Many FP stores are not made apparent until after legalize, e.g. for
7225 // argument passing. Since this is so common, custom legalize the
7226 // 64-bit integer store into two 32-bit stores.
7227 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
7228 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
7229 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
7230 if (TLI.isBigEndian()) std::swap(Lo, Hi);
7232 unsigned Alignment = ST->getAlignment();
7233 bool isVolatile = ST->isVolatile();
7234 bool isNonTemporal = ST->isNonTemporal();
7236 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
7237 Ptr, ST->getPointerInfo(),
7238 isVolatile, isNonTemporal,
7239 ST->getAlignment());
7240 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
7241 DAG.getConstant(4, Ptr.getValueType()));
7242 Alignment = MinAlign(Alignment, 4U);
7243 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
7244 Ptr, ST->getPointerInfo().getWithOffset(4),
7245 isVolatile, isNonTemporal,
7247 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
7256 // Try to infer better alignment information than the store already has.
7257 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
7258 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
7259 if (Align > ST->getAlignment())
7260 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
7261 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
7262 ST->isVolatile(), ST->isNonTemporal(), Align);
7266 // Try transforming a pair floating point load / store ops to integer
7267 // load / store ops.
7268 SDValue NewST = TransformFPLoadStorePair(N);
7269 if (NewST.getNode())
7273 // Walk up chain skipping non-aliasing memory nodes.
7274 SDValue BetterChain = FindBetterChain(N, Chain);
7276 // If there is a better chain.
7277 if (Chain != BetterChain) {
7280 // Replace the chain to avoid dependency.
7281 if (ST->isTruncatingStore()) {
7282 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
7283 ST->getPointerInfo(),
7284 ST->getMemoryVT(), ST->isVolatile(),
7285 ST->isNonTemporal(), ST->getAlignment());
7287 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
7288 ST->getPointerInfo(),
7289 ST->isVolatile(), ST->isNonTemporal(),
7290 ST->getAlignment());
7293 // Create token to keep both nodes around.
7294 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
7295 MVT::Other, Chain, ReplStore);
7297 // Make sure the new and old chains are cleaned up.
7298 AddToWorkList(Token.getNode());
7300 // Don't add users to work list.
7301 return CombineTo(N, Token, false);
7305 // Try transforming N to an indexed store.
7306 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
7307 return SDValue(N, 0);
7309 // FIXME: is there such a thing as a truncating indexed store?
7310 if (ST->isTruncatingStore() && ST->isUnindexed() &&
7311 Value.getValueType().isInteger()) {
7312 // See if we can simplify the input to this truncstore with knowledge that
7313 // only the low bits are being used. For example:
7314 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
7316 GetDemandedBits(Value,
7317 APInt::getLowBitsSet(
7318 Value.getValueType().getScalarType().getSizeInBits(),
7319 ST->getMemoryVT().getScalarType().getSizeInBits()));
7320 AddToWorkList(Value.getNode());
7321 if (Shorter.getNode())
7322 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
7323 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
7324 ST->isVolatile(), ST->isNonTemporal(),
7325 ST->getAlignment());
7327 // Otherwise, see if we can simplify the operation with
7328 // SimplifyDemandedBits, which only works if the value has a single use.
7329 if (SimplifyDemandedBits(Value,
7330 APInt::getLowBitsSet(
7331 Value.getValueType().getScalarType().getSizeInBits(),
7332 ST->getMemoryVT().getScalarType().getSizeInBits())))
7333 return SDValue(N, 0);
7336 // If this is a load followed by a store to the same location, then the store
7338 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
7339 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
7340 ST->isUnindexed() && !ST->isVolatile() &&
7341 // There can't be any side effects between the load and store, such as
7343 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
7344 // The store is dead, remove it.
7349 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
7350 // truncating store. We can do this even if this is already a truncstore.
7351 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
7352 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
7353 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
7354 ST->getMemoryVT())) {
7355 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
7356 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
7357 ST->isVolatile(), ST->isNonTemporal(),
7358 ST->getAlignment());
7361 return ReduceLoadOpStoreWidth(N);
7364 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
7365 SDValue InVec = N->getOperand(0);
7366 SDValue InVal = N->getOperand(1);
7367 SDValue EltNo = N->getOperand(2);
7368 DebugLoc dl = N->getDebugLoc();
7370 // If the inserted element is an UNDEF, just use the input vector.
7371 if (InVal.getOpcode() == ISD::UNDEF)
7374 EVT VT = InVec.getValueType();
7376 // If we can't generate a legal BUILD_VECTOR, exit
7377 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
7380 // Check that we know which element is being inserted
7381 if (!isa<ConstantSDNode>(EltNo))
7383 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7385 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
7386 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
7388 SmallVector<SDValue, 8> Ops;
7389 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
7390 Ops.append(InVec.getNode()->op_begin(),
7391 InVec.getNode()->op_end());
7392 } else if (InVec.getOpcode() == ISD::UNDEF) {
7393 unsigned NElts = VT.getVectorNumElements();
7394 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
7399 // Insert the element
7400 if (Elt < Ops.size()) {
7401 // All the operands of BUILD_VECTOR must have the same type;
7402 // we enforce that here.
7403 EVT OpVT = Ops[0].getValueType();
7404 if (InVal.getValueType() != OpVT)
7405 InVal = OpVT.bitsGT(InVal.getValueType()) ?
7406 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
7407 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
7411 // Return the new vector
7412 return DAG.getNode(ISD::BUILD_VECTOR, dl,
7413 VT, &Ops[0], Ops.size());
7416 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
7417 // (vextract (scalar_to_vector val, 0) -> val
7418 SDValue InVec = N->getOperand(0);
7419 EVT VT = InVec.getValueType();
7420 EVT NVT = N->getValueType(0);
7422 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
7423 // Check if the result type doesn't match the inserted element type. A
7424 // SCALAR_TO_VECTOR may truncate the inserted element and the
7425 // EXTRACT_VECTOR_ELT may widen the extracted vector.
7426 SDValue InOp = InVec.getOperand(0);
7427 if (InOp.getValueType() != NVT) {
7428 assert(InOp.getValueType().isInteger() && NVT.isInteger());
7429 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
7434 SDValue EltNo = N->getOperand(1);
7435 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
7437 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
7438 // We only perform this optimization before the op legalization phase because
7439 // we may introduce new vector instructions which are not backed by TD patterns.
7440 // For example on AVX, extracting elements from a wide vector without using
7441 // extract_subvector.
7442 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
7443 && ConstEltNo && !LegalOperations) {
7444 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7445 int NumElem = VT.getVectorNumElements();
7446 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
7447 // Find the new index to extract from.
7448 int OrigElt = SVOp->getMaskElt(Elt);
7450 // Extracting an undef index is undef.
7452 return DAG.getUNDEF(NVT);
7454 // Select the right vector half to extract from.
7455 if (OrigElt < NumElem) {
7456 InVec = InVec->getOperand(0);
7458 InVec = InVec->getOperand(1);
7462 EVT IndexTy = N->getOperand(1).getValueType();
7463 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT,
7464 InVec, DAG.getConstant(OrigElt, IndexTy));
7467 // Perform only after legalization to ensure build_vector / vector_shuffle
7468 // optimizations have already been done.
7469 if (!LegalOperations) return SDValue();
7471 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
7472 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
7473 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
7476 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7477 bool NewLoad = false;
7478 bool BCNumEltsChanged = false;
7479 EVT ExtVT = VT.getVectorElementType();
7482 // If the result of load has to be truncated, then it's not necessarily
7484 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
7487 if (InVec.getOpcode() == ISD::BITCAST) {
7488 // Don't duplicate a load with other uses.
7489 if (!InVec.hasOneUse())
7492 EVT BCVT = InVec.getOperand(0).getValueType();
7493 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
7495 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
7496 BCNumEltsChanged = true;
7497 InVec = InVec.getOperand(0);
7498 ExtVT = BCVT.getVectorElementType();
7502 LoadSDNode *LN0 = NULL;
7503 const ShuffleVectorSDNode *SVN = NULL;
7504 if (ISD::isNormalLoad(InVec.getNode())) {
7505 LN0 = cast<LoadSDNode>(InVec);
7506 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7507 InVec.getOperand(0).getValueType() == ExtVT &&
7508 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
7509 // Don't duplicate a load with other uses.
7510 if (!InVec.hasOneUse())
7513 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
7514 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
7515 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
7517 // (load $addr+1*size)
7519 // Don't duplicate a load with other uses.
7520 if (!InVec.hasOneUse())
7523 // If the bit convert changed the number of elements, it is unsafe
7524 // to examine the mask.
7525 if (BCNumEltsChanged)
7528 // Select the input vector, guarding against out of range extract vector.
7529 unsigned NumElems = VT.getVectorNumElements();
7530 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
7531 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
7533 if (InVec.getOpcode() == ISD::BITCAST) {
7534 // Don't duplicate a load with other uses.
7535 if (!InVec.hasOneUse())
7538 InVec = InVec.getOperand(0);
7540 if (ISD::isNormalLoad(InVec.getNode())) {
7541 LN0 = cast<LoadSDNode>(InVec);
7542 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
7546 // Make sure we found a non-volatile load and the extractelement is
7548 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
7551 // If Idx was -1 above, Elt is going to be -1, so just return undef.
7553 return DAG.getUNDEF(LVT);
7555 unsigned Align = LN0->getAlignment();
7557 // Check the resultant load doesn't need a higher alignment than the
7561 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
7563 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
7569 SDValue NewPtr = LN0->getBasePtr();
7570 unsigned PtrOff = 0;
7573 PtrOff = LVT.getSizeInBits() * Elt / 8;
7574 EVT PtrType = NewPtr.getValueType();
7575 if (TLI.isBigEndian())
7576 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
7577 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
7578 DAG.getConstant(PtrOff, PtrType));
7581 // The replacement we need to do here is a little tricky: we need to
7582 // replace an extractelement of a load with a load.
7583 // Use ReplaceAllUsesOfValuesWith to do the replacement.
7584 // Note that this replacement assumes that the extractvalue is the only
7585 // use of the load; that's okay because we don't want to perform this
7586 // transformation in other cases anyway.
7589 if (NVT.bitsGT(LVT)) {
7590 // If the result type of vextract is wider than the load, then issue an
7591 // extending load instead.
7592 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT)
7593 ? ISD::ZEXTLOAD : ISD::EXTLOAD;
7594 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(),
7595 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff),
7596 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align);
7597 Chain = Load.getValue(1);
7599 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
7600 LN0->getPointerInfo().getWithOffset(PtrOff),
7601 LN0->isVolatile(), LN0->isNonTemporal(),
7602 LN0->isInvariant(), Align);
7603 Chain = Load.getValue(1);
7604 if (NVT.bitsLT(LVT))
7605 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load);
7607 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load);
7609 WorkListRemover DeadNodes(*this);
7610 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) };
7611 SDValue To[] = { Load, Chain };
7612 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7613 // Since we're explcitly calling ReplaceAllUses, add the new node to the
7614 // worklist explicitly as well.
7615 AddToWorkList(Load.getNode());
7616 AddUsersToWorkList(Load.getNode()); // Add users too
7617 // Make sure to revisit this node to clean it up; it will usually be dead.
7619 return SDValue(N, 0);
7625 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
7626 unsigned NumInScalars = N->getNumOperands();
7627 DebugLoc dl = N->getDebugLoc();
7628 EVT VT = N->getValueType(0);
7630 // A vector built entirely of undefs is undef.
7631 if (ISD::allOperandsUndef(N))
7632 return DAG.getUNDEF(VT);
7634 // Check to see if this is a BUILD_VECTOR of a bunch of values
7635 // which come from any_extend or zero_extend nodes. If so, we can create
7636 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
7637 // optimizations. We do not handle sign-extend because we can't fill the sign
7639 EVT SourceType = MVT::Other;
7640 bool AllAnyExt = true;
7642 for (unsigned i = 0; i != NumInScalars; ++i) {
7643 SDValue In = N->getOperand(i);
7644 // Ignore undef inputs.
7645 if (In.getOpcode() == ISD::UNDEF) continue;
7647 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
7648 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
7650 // Abort if the element is not an extension.
7651 if (!ZeroExt && !AnyExt) {
7652 SourceType = MVT::Other;
7656 // The input is a ZeroExt or AnyExt. Check the original type.
7657 EVT InTy = In.getOperand(0).getValueType();
7659 // Check that all of the widened source types are the same.
7660 if (SourceType == MVT::Other)
7663 else if (InTy != SourceType) {
7664 // Multiple income types. Abort.
7665 SourceType = MVT::Other;
7669 // Check if all of the extends are ANY_EXTENDs.
7670 AllAnyExt &= AnyExt;
7673 // In order to have valid types, all of the inputs must be extended from the
7674 // same source type and all of the inputs must be any or zero extend.
7675 // Scalar sizes must be a power of two.
7676 EVT OutScalarTy = N->getValueType(0).getScalarType();
7677 bool ValidTypes = SourceType != MVT::Other &&
7678 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
7679 isPowerOf2_32(SourceType.getSizeInBits());
7681 // We perform this optimization post type-legalization because
7682 // the type-legalizer often scalarizes integer-promoted vectors.
7683 // Performing this optimization before may create bit-casts which
7684 // will be type-legalized to complex code sequences.
7685 // We perform this optimization only before the operation legalizer because we
7686 // may introduce illegal operations.
7687 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
7688 // turn into a single shuffle instruction.
7689 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) &&
7691 bool isLE = TLI.isLittleEndian();
7692 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
7693 assert(ElemRatio > 1 && "Invalid element size ratio");
7694 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
7695 DAG.getConstant(0, SourceType);
7697 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements();
7698 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
7700 // Populate the new build_vector
7701 for (unsigned i=0; i < N->getNumOperands(); ++i) {
7702 SDValue Cast = N->getOperand(i);
7703 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
7704 Cast.getOpcode() == ISD::ZERO_EXTEND ||
7705 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
7707 if (Cast.getOpcode() == ISD::UNDEF)
7708 In = DAG.getUNDEF(SourceType);
7710 In = Cast->getOperand(0);
7711 unsigned Index = isLE ? (i * ElemRatio) :
7712 (i * ElemRatio + (ElemRatio - 1));
7714 assert(Index < Ops.size() && "Invalid index");
7718 // The type of the new BUILD_VECTOR node.
7719 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
7720 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() &&
7721 "Invalid vector size");
7722 // Check if the new vector type is legal.
7723 if (!isTypeLegal(VecVT)) return SDValue();
7725 // Make the new BUILD_VECTOR.
7726 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7727 VecVT, &Ops[0], Ops.size());
7729 // The new BUILD_VECTOR node has the potential to be further optimized.
7730 AddToWorkList(BV.getNode());
7731 // Bitcast to the desired type.
7732 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV);
7735 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
7736 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
7737 // at most two distinct vectors, turn this into a shuffle node.
7739 // May only combine to shuffle after legalize if shuffle is legal.
7740 if (LegalOperations &&
7741 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))
7744 SDValue VecIn1, VecIn2;
7745 for (unsigned i = 0; i != NumInScalars; ++i) {
7746 // Ignore undef inputs.
7747 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
7749 // If this input is something other than a EXTRACT_VECTOR_ELT with a
7750 // constant index, bail out.
7751 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
7752 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
7753 VecIn1 = VecIn2 = SDValue(0, 0);
7757 // We allow up to two distinct input vectors.
7758 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
7759 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
7762 if (VecIn1.getNode() == 0) {
7763 VecIn1 = ExtractedFromVec;
7764 } else if (VecIn2.getNode() == 0) {
7765 VecIn2 = ExtractedFromVec;
7768 VecIn1 = VecIn2 = SDValue(0, 0);
7773 // If everything is good, we can make a shuffle operation.
7774 if (VecIn1.getNode()) {
7775 SmallVector<int, 8> Mask;
7776 for (unsigned i = 0; i != NumInScalars; ++i) {
7777 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
7782 // If extracting from the first vector, just use the index directly.
7783 SDValue Extract = N->getOperand(i);
7784 SDValue ExtVal = Extract.getOperand(1);
7785 if (Extract.getOperand(0) == VecIn1) {
7786 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
7787 if (ExtIndex > VT.getVectorNumElements())
7790 Mask.push_back(ExtIndex);
7794 // Otherwise, use InIdx + VecSize
7795 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
7796 Mask.push_back(Idx+NumInScalars);
7799 // We can't generate a shuffle node with mismatched input and output types.
7800 // Attempt to transform a single input vector to the correct type.
7801 if ((VT != VecIn1.getValueType())) {
7802 // We don't support shuffeling between TWO values of different types.
7803 if (VecIn2.getNode() != 0)
7806 // We only support widening of vectors which are half the size of the
7807 // output registers. For example XMM->YMM widening on X86 with AVX.
7808 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
7811 // Widen the input vector by adding undef values.
7812 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
7813 VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
7816 // If VecIn2 is unused then change it to undef.
7817 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
7819 // Check that we were able to transform all incoming values to the same type.
7820 if (VecIn2.getValueType() != VecIn1.getValueType() ||
7821 VecIn1.getValueType() != VT)
7824 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
7825 if (!isTypeLegal(VT))
7828 // Return the new VECTOR_SHUFFLE node.
7832 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
7838 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
7839 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
7840 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
7841 // inputs come from at most two distinct vectors, turn this into a shuffle
7844 // If we only have one input vector, we don't need to do any concatenation.
7845 if (N->getNumOperands() == 1)
7846 return N->getOperand(0);
7848 // Check if all of the operands are undefs.
7849 if (ISD::allOperandsUndef(N))
7850 return DAG.getUNDEF(N->getValueType(0));
7855 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
7856 EVT NVT = N->getValueType(0);
7857 SDValue V = N->getOperand(0);
7859 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
7860 // Handle only simple case where vector being inserted and vector
7861 // being extracted are of same type, and are half size of larger vectors.
7862 EVT BigVT = V->getOperand(0).getValueType();
7863 EVT SmallVT = V->getOperand(1).getValueType();
7864 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
7867 // Only handle cases where both indexes are constants with the same type.
7868 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
7869 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
7871 if (InsIdx && ExtIdx &&
7872 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
7873 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
7875 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
7877 // indices are equal => V1
7878 // otherwise => (extract_subvec V1, ExtIdx)
7879 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue())
7880 return V->getOperand(1);
7881 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT,
7882 V->getOperand(0), N->getOperand(1));
7889 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
7890 EVT VT = N->getValueType(0);
7891 unsigned NumElts = VT.getVectorNumElements();
7893 SDValue N0 = N->getOperand(0);
7894 SDValue N1 = N->getOperand(1);
7896 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
7898 // Canonicalize shuffle undef, undef -> undef
7899 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
7900 return DAG.getUNDEF(VT);
7902 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7904 // Canonicalize shuffle v, v -> v, undef
7906 SmallVector<int, 8> NewMask;
7907 for (unsigned i = 0; i != NumElts; ++i) {
7908 int Idx = SVN->getMaskElt(i);
7909 if (Idx >= (int)NumElts) Idx -= NumElts;
7910 NewMask.push_back(Idx);
7912 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT),
7916 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
7917 if (N0.getOpcode() == ISD::UNDEF) {
7918 SmallVector<int, 8> NewMask;
7919 for (unsigned i = 0; i != NumElts; ++i) {
7920 int Idx = SVN->getMaskElt(i);
7922 if (Idx < (int)NumElts)
7927 NewMask.push_back(Idx);
7929 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT),
7933 // Remove references to rhs if it is undef
7934 if (N1.getOpcode() == ISD::UNDEF) {
7935 bool Changed = false;
7936 SmallVector<int, 8> NewMask;
7937 for (unsigned i = 0; i != NumElts; ++i) {
7938 int Idx = SVN->getMaskElt(i);
7939 if (Idx >= (int)NumElts) {
7943 NewMask.push_back(Idx);
7946 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]);
7949 // If it is a splat, check if the argument vector is another splat or a
7950 // build_vector with all scalar elements the same.
7951 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
7952 SDNode *V = N0.getNode();
7954 // If this is a bit convert that changes the element type of the vector but
7955 // not the number of vector elements, look through it. Be careful not to
7956 // look though conversions that change things like v4f32 to v2f64.
7957 if (V->getOpcode() == ISD::BITCAST) {
7958 SDValue ConvInput = V->getOperand(0);
7959 if (ConvInput.getValueType().isVector() &&
7960 ConvInput.getValueType().getVectorNumElements() == NumElts)
7961 V = ConvInput.getNode();
7964 if (V->getOpcode() == ISD::BUILD_VECTOR) {
7965 assert(V->getNumOperands() == NumElts &&
7966 "BUILD_VECTOR has wrong number of operands");
7968 bool AllSame = true;
7969 for (unsigned i = 0; i != NumElts; ++i) {
7970 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
7971 Base = V->getOperand(i);
7975 // Splat of <u, u, u, u>, return <u, u, u, u>
7976 if (!Base.getNode())
7978 for (unsigned i = 0; i != NumElts; ++i) {
7979 if (V->getOperand(i) != Base) {
7984 // Splat of <x, x, x, x>, return <x, x, x, x>
7990 // If this shuffle node is simply a swizzle of another shuffle node,
7991 // and it reverses the swizzle of the previous shuffle then we can
7992 // optimize shuffle(shuffle(x, undef), undef) -> x.
7993 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
7994 N1.getOpcode() == ISD::UNDEF) {
7996 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
7998 // Shuffle nodes can only reverse shuffles with a single non-undef value.
7999 if (N0.getOperand(1).getOpcode() != ISD::UNDEF)
8002 // The incoming shuffle must be of the same type as the result of the
8004 assert(OtherSV->getOperand(0).getValueType() == VT &&
8005 "Shuffle types don't match");
8007 for (unsigned i = 0; i != NumElts; ++i) {
8008 int Idx = SVN->getMaskElt(i);
8009 assert(Idx < (int)NumElts && "Index references undef operand");
8010 // Next, this index comes from the first value, which is the incoming
8011 // shuffle. Adopt the incoming index.
8013 Idx = OtherSV->getMaskElt(Idx);
8015 // The combined shuffle must map each index to itself.
8016 if (Idx >= 0 && (unsigned)Idx != i)
8020 return OtherSV->getOperand(0);
8026 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
8027 if (!TLI.getShouldFoldAtomicFences())
8030 SDValue atomic = N->getOperand(0);
8031 switch (atomic.getOpcode()) {
8032 case ISD::ATOMIC_CMP_SWAP:
8033 case ISD::ATOMIC_SWAP:
8034 case ISD::ATOMIC_LOAD_ADD:
8035 case ISD::ATOMIC_LOAD_SUB:
8036 case ISD::ATOMIC_LOAD_AND:
8037 case ISD::ATOMIC_LOAD_OR:
8038 case ISD::ATOMIC_LOAD_XOR:
8039 case ISD::ATOMIC_LOAD_NAND:
8040 case ISD::ATOMIC_LOAD_MIN:
8041 case ISD::ATOMIC_LOAD_MAX:
8042 case ISD::ATOMIC_LOAD_UMIN:
8043 case ISD::ATOMIC_LOAD_UMAX:
8049 SDValue fence = atomic.getOperand(0);
8050 if (fence.getOpcode() != ISD::MEMBARRIER)
8053 switch (atomic.getOpcode()) {
8054 case ISD::ATOMIC_CMP_SWAP:
8055 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
8056 fence.getOperand(0),
8057 atomic.getOperand(1), atomic.getOperand(2),
8058 atomic.getOperand(3)), atomic.getResNo());
8059 case ISD::ATOMIC_SWAP:
8060 case ISD::ATOMIC_LOAD_ADD:
8061 case ISD::ATOMIC_LOAD_SUB:
8062 case ISD::ATOMIC_LOAD_AND:
8063 case ISD::ATOMIC_LOAD_OR:
8064 case ISD::ATOMIC_LOAD_XOR:
8065 case ISD::ATOMIC_LOAD_NAND:
8066 case ISD::ATOMIC_LOAD_MIN:
8067 case ISD::ATOMIC_LOAD_MAX:
8068 case ISD::ATOMIC_LOAD_UMIN:
8069 case ISD::ATOMIC_LOAD_UMAX:
8070 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
8071 fence.getOperand(0),
8072 atomic.getOperand(1), atomic.getOperand(2)),
8079 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
8080 /// an AND to a vector_shuffle with the destination vector and a zero vector.
8081 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
8082 /// vector_shuffle V, Zero, <0, 4, 2, 4>
8083 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
8084 EVT VT = N->getValueType(0);
8085 DebugLoc dl = N->getDebugLoc();
8086 SDValue LHS = N->getOperand(0);
8087 SDValue RHS = N->getOperand(1);
8088 if (N->getOpcode() == ISD::AND) {
8089 if (RHS.getOpcode() == ISD::BITCAST)
8090 RHS = RHS.getOperand(0);
8091 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
8092 SmallVector<int, 8> Indices;
8093 unsigned NumElts = RHS.getNumOperands();
8094 for (unsigned i = 0; i != NumElts; ++i) {
8095 SDValue Elt = RHS.getOperand(i);
8096 if (!isa<ConstantSDNode>(Elt))
8099 if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
8100 Indices.push_back(i);
8101 else if (cast<ConstantSDNode>(Elt)->isNullValue())
8102 Indices.push_back(NumElts);
8107 // Let's see if the target supports this vector_shuffle.
8108 EVT RVT = RHS.getValueType();
8109 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
8112 // Return the new VECTOR_SHUFFLE node.
8113 EVT EltVT = RVT.getVectorElementType();
8114 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
8115 DAG.getConstant(0, EltVT));
8116 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
8117 RVT, &ZeroOps[0], ZeroOps.size());
8118 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
8119 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
8120 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
8127 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
8128 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
8129 // After legalize, the target may be depending on adds and other
8130 // binary ops to provide legal ways to construct constants or other
8131 // things. Simplifying them may result in a loss of legality.
8132 if (LegalOperations) return SDValue();
8134 assert(N->getValueType(0).isVector() &&
8135 "SimplifyVBinOp only works on vectors!");
8137 SDValue LHS = N->getOperand(0);
8138 SDValue RHS = N->getOperand(1);
8139 SDValue Shuffle = XformToShuffleWithZero(N);
8140 if (Shuffle.getNode()) return Shuffle;
8142 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
8144 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
8145 RHS.getOpcode() == ISD::BUILD_VECTOR) {
8146 SmallVector<SDValue, 8> Ops;
8147 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
8148 SDValue LHSOp = LHS.getOperand(i);
8149 SDValue RHSOp = RHS.getOperand(i);
8150 // If these two elements can't be folded, bail out.
8151 if ((LHSOp.getOpcode() != ISD::UNDEF &&
8152 LHSOp.getOpcode() != ISD::Constant &&
8153 LHSOp.getOpcode() != ISD::ConstantFP) ||
8154 (RHSOp.getOpcode() != ISD::UNDEF &&
8155 RHSOp.getOpcode() != ISD::Constant &&
8156 RHSOp.getOpcode() != ISD::ConstantFP))
8159 // Can't fold divide by zero.
8160 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
8161 N->getOpcode() == ISD::FDIV) {
8162 if ((RHSOp.getOpcode() == ISD::Constant &&
8163 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
8164 (RHSOp.getOpcode() == ISD::ConstantFP &&
8165 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
8169 EVT VT = LHSOp.getValueType();
8170 EVT RVT = RHSOp.getValueType();
8172 // Integer BUILD_VECTOR operands may have types larger than the element
8173 // size (e.g., when the element type is not legal). Prior to type
8174 // legalization, the types may not match between the two BUILD_VECTORS.
8175 // Truncate one of the operands to make them match.
8176 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
8177 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp);
8179 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp);
8183 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
8185 if (FoldOp.getOpcode() != ISD::UNDEF &&
8186 FoldOp.getOpcode() != ISD::Constant &&
8187 FoldOp.getOpcode() != ISD::ConstantFP)
8189 Ops.push_back(FoldOp);
8190 AddToWorkList(FoldOp.getNode());
8193 if (Ops.size() == LHS.getNumOperands())
8194 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
8195 LHS.getValueType(), &Ops[0], Ops.size());
8201 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
8202 SDValue N1, SDValue N2){
8203 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
8205 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
8206 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8208 // If we got a simplified select_cc node back from SimplifySelectCC, then
8209 // break it down into a new SETCC node, and a new SELECT node, and then return
8210 // the SELECT node, since we were called with a SELECT node.
8211 if (SCC.getNode()) {
8212 // Check to see if we got a select_cc back (to turn into setcc/select).
8213 // Otherwise, just return whatever node we got back, like fabs.
8214 if (SCC.getOpcode() == ISD::SELECT_CC) {
8215 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
8217 SCC.getOperand(0), SCC.getOperand(1),
8219 AddToWorkList(SETCC.getNode());
8220 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
8221 SCC.getOperand(2), SCC.getOperand(3), SETCC);
8229 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
8230 /// are the two values being selected between, see if we can simplify the
8231 /// select. Callers of this should assume that TheSelect is deleted if this
8232 /// returns true. As such, they should return the appropriate thing (e.g. the
8233 /// node) back to the top-level of the DAG combiner loop to avoid it being
8235 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
8238 // Cannot simplify select with vector condition
8239 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
8241 // If this is a select from two identical things, try to pull the operation
8242 // through the select.
8243 if (LHS.getOpcode() != RHS.getOpcode() ||
8244 !LHS.hasOneUse() || !RHS.hasOneUse())
8247 // If this is a load and the token chain is identical, replace the select
8248 // of two loads with a load through a select of the address to load from.
8249 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
8250 // constants have been dropped into the constant pool.
8251 if (LHS.getOpcode() == ISD::LOAD) {
8252 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
8253 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
8255 // Token chains must be identical.
8256 if (LHS.getOperand(0) != RHS.getOperand(0) ||
8257 // Do not let this transformation reduce the number of volatile loads.
8258 LLD->isVolatile() || RLD->isVolatile() ||
8259 // If this is an EXTLOAD, the VT's must match.
8260 LLD->getMemoryVT() != RLD->getMemoryVT() ||
8261 // If this is an EXTLOAD, the kind of extension must match.
8262 (LLD->getExtensionType() != RLD->getExtensionType() &&
8263 // The only exception is if one of the extensions is anyext.
8264 LLD->getExtensionType() != ISD::EXTLOAD &&
8265 RLD->getExtensionType() != ISD::EXTLOAD) ||
8266 // FIXME: this discards src value information. This is
8267 // over-conservative. It would be beneficial to be able to remember
8268 // both potential memory locations. Since we are discarding
8269 // src value info, don't do the transformation if the memory
8270 // locations are not in the default address space.
8271 LLD->getPointerInfo().getAddrSpace() != 0 ||
8272 RLD->getPointerInfo().getAddrSpace() != 0)
8275 // Check that the select condition doesn't reach either load. If so,
8276 // folding this will induce a cycle into the DAG. If not, this is safe to
8277 // xform, so create a select of the addresses.
8279 if (TheSelect->getOpcode() == ISD::SELECT) {
8280 SDNode *CondNode = TheSelect->getOperand(0).getNode();
8281 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
8282 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
8284 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
8285 LLD->getBasePtr().getValueType(),
8286 TheSelect->getOperand(0), LLD->getBasePtr(),
8288 } else { // Otherwise SELECT_CC
8289 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
8290 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
8292 if ((LLD->hasAnyUseOfValue(1) &&
8293 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
8294 (RLD->hasAnyUseOfValue(1) &&
8295 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
8298 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
8299 LLD->getBasePtr().getValueType(),
8300 TheSelect->getOperand(0),
8301 TheSelect->getOperand(1),
8302 LLD->getBasePtr(), RLD->getBasePtr(),
8303 TheSelect->getOperand(4));
8307 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
8308 Load = DAG.getLoad(TheSelect->getValueType(0),
8309 TheSelect->getDebugLoc(),
8310 // FIXME: Discards pointer info.
8311 LLD->getChain(), Addr, MachinePointerInfo(),
8312 LLD->isVolatile(), LLD->isNonTemporal(),
8313 LLD->isInvariant(), LLD->getAlignment());
8315 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
8316 RLD->getExtensionType() : LLD->getExtensionType(),
8317 TheSelect->getDebugLoc(),
8318 TheSelect->getValueType(0),
8319 // FIXME: Discards pointer info.
8320 LLD->getChain(), Addr, MachinePointerInfo(),
8321 LLD->getMemoryVT(), LLD->isVolatile(),
8322 LLD->isNonTemporal(), LLD->getAlignment());
8325 // Users of the select now use the result of the load.
8326 CombineTo(TheSelect, Load);
8328 // Users of the old loads now use the new load's chain. We know the
8329 // old-load value is dead now.
8330 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
8331 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
8338 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
8339 /// where 'cond' is the comparison specified by CC.
8340 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
8341 SDValue N2, SDValue N3,
8342 ISD::CondCode CC, bool NotExtCompare) {
8343 // (x ? y : y) -> y.
8344 if (N2 == N3) return N2;
8346 EVT VT = N2.getValueType();
8347 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
8348 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
8349 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
8351 // Determine if the condition we're dealing with is constant
8352 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
8353 N0, N1, CC, DL, false);
8354 if (SCC.getNode()) AddToWorkList(SCC.getNode());
8355 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
8357 // fold select_cc true, x, y -> x
8358 if (SCCC && !SCCC->isNullValue())
8360 // fold select_cc false, x, y -> y
8361 if (SCCC && SCCC->isNullValue())
8364 // Check to see if we can simplify the select into an fabs node
8365 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
8366 // Allow either -0.0 or 0.0
8367 if (CFP->getValueAPF().isZero()) {
8368 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
8369 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
8370 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
8371 N2 == N3.getOperand(0))
8372 return DAG.getNode(ISD::FABS, DL, VT, N0);
8374 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
8375 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
8376 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
8377 N2.getOperand(0) == N3)
8378 return DAG.getNode(ISD::FABS, DL, VT, N3);
8382 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
8383 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
8384 // in it. This is a win when the constant is not otherwise available because
8385 // it replaces two constant pool loads with one. We only do this if the FP
8386 // type is known to be legal, because if it isn't, then we are before legalize
8387 // types an we want the other legalization to happen first (e.g. to avoid
8388 // messing with soft float) and if the ConstantFP is not legal, because if
8389 // it is legal, we may not need to store the FP constant in a constant pool.
8390 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
8391 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
8392 if (TLI.isTypeLegal(N2.getValueType()) &&
8393 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
8394 TargetLowering::Legal) &&
8395 // If both constants have multiple uses, then we won't need to do an
8396 // extra load, they are likely around in registers for other users.
8397 (TV->hasOneUse() || FV->hasOneUse())) {
8398 Constant *Elts[] = {
8399 const_cast<ConstantFP*>(FV->getConstantFPValue()),
8400 const_cast<ConstantFP*>(TV->getConstantFPValue())
8402 Type *FPTy = Elts[0]->getType();
8403 const TargetData &TD = *TLI.getTargetData();
8405 // Create a ConstantArray of the two constants.
8406 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
8407 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
8408 TD.getPrefTypeAlignment(FPTy));
8409 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8411 // Get the offsets to the 0 and 1 element of the array so that we can
8412 // select between them.
8413 SDValue Zero = DAG.getIntPtrConstant(0);
8414 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
8415 SDValue One = DAG.getIntPtrConstant(EltSize);
8417 SDValue Cond = DAG.getSetCC(DL,
8418 TLI.getSetCCResultType(N0.getValueType()),
8420 AddToWorkList(Cond.getNode());
8421 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
8423 AddToWorkList(CstOffset.getNode());
8424 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
8426 AddToWorkList(CPIdx.getNode());
8427 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
8428 MachinePointerInfo::getConstantPool(), false,
8429 false, false, Alignment);
8434 // Check to see if we can perform the "gzip trick", transforming
8435 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
8436 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
8437 (N1C->isNullValue() || // (a < 0) ? b : 0
8438 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
8439 EVT XType = N0.getValueType();
8440 EVT AType = N2.getValueType();
8441 if (XType.bitsGE(AType)) {
8442 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
8443 // single-bit constant.
8444 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
8445 unsigned ShCtV = N2C->getAPIntValue().logBase2();
8446 ShCtV = XType.getSizeInBits()-ShCtV-1;
8447 SDValue ShCt = DAG.getConstant(ShCtV,
8448 getShiftAmountTy(N0.getValueType()));
8449 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
8451 AddToWorkList(Shift.getNode());
8453 if (XType.bitsGT(AType)) {
8454 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
8455 AddToWorkList(Shift.getNode());
8458 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
8461 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
8463 DAG.getConstant(XType.getSizeInBits()-1,
8464 getShiftAmountTy(N0.getValueType())));
8465 AddToWorkList(Shift.getNode());
8467 if (XType.bitsGT(AType)) {
8468 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
8469 AddToWorkList(Shift.getNode());
8472 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
8476 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
8477 // where y is has a single bit set.
8478 // A plaintext description would be, we can turn the SELECT_CC into an AND
8479 // when the condition can be materialized as an all-ones register. Any
8480 // single bit-test can be materialized as an all-ones register with
8481 // shift-left and shift-right-arith.
8482 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
8483 N0->getValueType(0) == VT &&
8484 N1C && N1C->isNullValue() &&
8485 N2C && N2C->isNullValue()) {
8486 SDValue AndLHS = N0->getOperand(0);
8487 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
8488 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
8489 // Shift the tested bit over the sign bit.
8490 APInt AndMask = ConstAndRHS->getAPIntValue();
8492 DAG.getConstant(AndMask.countLeadingZeros(),
8493 getShiftAmountTy(AndLHS.getValueType()));
8494 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
8496 // Now arithmetic right shift it all the way over, so the result is either
8497 // all-ones, or zero.
8499 DAG.getConstant(AndMask.getBitWidth()-1,
8500 getShiftAmountTy(Shl.getValueType()));
8501 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
8503 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
8507 // fold select C, 16, 0 -> shl C, 4
8508 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
8509 TLI.getBooleanContents(N0.getValueType().isVector()) ==
8510 TargetLowering::ZeroOrOneBooleanContent) {
8512 // If the caller doesn't want us to simplify this into a zext of a compare,
8514 if (NotExtCompare && N2C->getAPIntValue() == 1)
8517 // Get a SetCC of the condition
8518 // FIXME: Should probably make sure that setcc is legal if we ever have a
8519 // target where it isn't.
8521 // cast from setcc result type to select result type
8523 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
8525 if (N2.getValueType().bitsLT(SCC.getValueType()))
8526 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
8528 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
8529 N2.getValueType(), SCC);
8531 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
8532 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
8533 N2.getValueType(), SCC);
8536 AddToWorkList(SCC.getNode());
8537 AddToWorkList(Temp.getNode());
8539 if (N2C->getAPIntValue() == 1)
8542 // shl setcc result by log2 n2c
8543 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
8544 DAG.getConstant(N2C->getAPIntValue().logBase2(),
8545 getShiftAmountTy(Temp.getValueType())));
8548 // Check to see if this is the equivalent of setcc
8549 // FIXME: Turn all of these into setcc if setcc if setcc is legal
8550 // otherwise, go ahead with the folds.
8551 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
8552 EVT XType = N0.getValueType();
8553 if (!LegalOperations ||
8554 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
8555 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
8556 if (Res.getValueType() != VT)
8557 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
8561 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
8562 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
8563 (!LegalOperations ||
8564 TLI.isOperationLegal(ISD::CTLZ, XType))) {
8565 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
8566 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
8567 DAG.getConstant(Log2_32(XType.getSizeInBits()),
8568 getShiftAmountTy(Ctlz.getValueType())));
8570 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
8571 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
8572 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
8573 XType, DAG.getConstant(0, XType), N0);
8574 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
8575 return DAG.getNode(ISD::SRL, DL, XType,
8576 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
8577 DAG.getConstant(XType.getSizeInBits()-1,
8578 getShiftAmountTy(XType)));
8580 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
8581 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
8582 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
8583 DAG.getConstant(XType.getSizeInBits()-1,
8584 getShiftAmountTy(N0.getValueType())));
8585 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
8589 // Check to see if this is an integer abs.
8590 // select_cc setg[te] X, 0, X, -X ->
8591 // select_cc setgt X, -1, X, -X ->
8592 // select_cc setl[te] X, 0, -X, X ->
8593 // select_cc setlt X, 1, -X, X ->
8594 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
8596 ConstantSDNode *SubC = NULL;
8597 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
8598 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
8599 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
8600 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
8601 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
8602 (N1C->isOne() && CC == ISD::SETLT)) &&
8603 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
8604 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
8606 EVT XType = N0.getValueType();
8607 if (SubC && SubC->isNullValue() && XType.isInteger()) {
8608 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
8610 DAG.getConstant(XType.getSizeInBits()-1,
8611 getShiftAmountTy(N0.getValueType())));
8612 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
8614 AddToWorkList(Shift.getNode());
8615 AddToWorkList(Add.getNode());
8616 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
8623 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
8624 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
8625 SDValue N1, ISD::CondCode Cond,
8626 DebugLoc DL, bool foldBooleans) {
8627 TargetLowering::DAGCombinerInfo
8628 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
8629 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
8632 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
8633 /// return a DAG expression to select that will generate the same value by
8634 /// multiplying by a magic number. See:
8635 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
8636 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
8637 std::vector<SDNode*> Built;
8638 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built);
8640 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
8646 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
8647 /// return a DAG expression to select that will generate the same value by
8648 /// multiplying by a magic number. See:
8649 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
8650 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
8651 std::vector<SDNode*> Built;
8652 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built);
8654 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
8660 /// FindBaseOffset - Return true if base is a frame index, which is known not
8661 // to alias with anything but itself. Provides base object and offset as
8663 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
8664 const GlobalValue *&GV, void *&CV) {
8665 // Assume it is a primitive operation.
8666 Base = Ptr; Offset = 0; GV = 0; CV = 0;
8668 // If it's an adding a simple constant then integrate the offset.
8669 if (Base.getOpcode() == ISD::ADD) {
8670 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
8671 Base = Base.getOperand(0);
8672 Offset += C->getZExtValue();
8676 // Return the underlying GlobalValue, and update the Offset. Return false
8677 // for GlobalAddressSDNode since the same GlobalAddress may be represented
8678 // by multiple nodes with different offsets.
8679 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
8680 GV = G->getGlobal();
8681 Offset += G->getOffset();
8685 // Return the underlying Constant value, and update the Offset. Return false
8686 // for ConstantSDNodes since the same constant pool entry may be represented
8687 // by multiple nodes with different offsets.
8688 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
8689 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
8690 : (void *)C->getConstVal();
8691 Offset += C->getOffset();
8694 // If it's any of the following then it can't alias with anything but itself.
8695 return isa<FrameIndexSDNode>(Base);
8698 /// isAlias - Return true if there is any possibility that the two addresses
8700 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
8701 const Value *SrcValue1, int SrcValueOffset1,
8702 unsigned SrcValueAlign1,
8703 const MDNode *TBAAInfo1,
8704 SDValue Ptr2, int64_t Size2,
8705 const Value *SrcValue2, int SrcValueOffset2,
8706 unsigned SrcValueAlign2,
8707 const MDNode *TBAAInfo2) const {
8708 // If they are the same then they must be aliases.
8709 if (Ptr1 == Ptr2) return true;
8711 // Gather base node and offset information.
8712 SDValue Base1, Base2;
8713 int64_t Offset1, Offset2;
8714 const GlobalValue *GV1, *GV2;
8716 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
8717 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
8719 // If they have a same base address then check to see if they overlap.
8720 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
8721 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
8723 // It is possible for different frame indices to alias each other, mostly
8724 // when tail call optimization reuses return address slots for arguments.
8725 // To catch this case, look up the actual index of frame indices to compute
8726 // the real alias relationship.
8727 if (isFrameIndex1 && isFrameIndex2) {
8728 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8729 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
8730 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
8731 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
8734 // Otherwise, if we know what the bases are, and they aren't identical, then
8735 // we know they cannot alias.
8736 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
8739 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
8740 // compared to the size and offset of the access, we may be able to prove they
8741 // do not alias. This check is conservative for now to catch cases created by
8742 // splitting vector types.
8743 if ((SrcValueAlign1 == SrcValueAlign2) &&
8744 (SrcValueOffset1 != SrcValueOffset2) &&
8745 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
8746 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
8747 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
8749 // There is no overlap between these relatively aligned accesses of similar
8750 // size, return no alias.
8751 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
8755 if (CombinerGlobalAA) {
8756 // Use alias analysis information.
8757 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
8758 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
8759 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
8760 AliasAnalysis::AliasResult AAResult =
8761 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
8762 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
8763 if (AAResult == AliasAnalysis::NoAlias)
8767 // Otherwise we have to assume they alias.
8771 /// FindAliasInfo - Extracts the relevant alias information from the memory
8772 /// node. Returns true if the operand was a load.
8773 bool DAGCombiner::FindAliasInfo(SDNode *N,
8774 SDValue &Ptr, int64_t &Size,
8775 const Value *&SrcValue,
8776 int &SrcValueOffset,
8777 unsigned &SrcValueAlign,
8778 const MDNode *&TBAAInfo) const {
8779 LSBaseSDNode *LS = cast<LSBaseSDNode>(N);
8781 Ptr = LS->getBasePtr();
8782 Size = LS->getMemoryVT().getSizeInBits() >> 3;
8783 SrcValue = LS->getSrcValue();
8784 SrcValueOffset = LS->getSrcValueOffset();
8785 SrcValueAlign = LS->getOriginalAlignment();
8786 TBAAInfo = LS->getTBAAInfo();
8787 return isa<LoadSDNode>(LS);
8790 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
8791 /// looking for aliasing nodes and adding them to the Aliases vector.
8792 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
8793 SmallVector<SDValue, 8> &Aliases) {
8794 SmallVector<SDValue, 8> Chains; // List of chains to visit.
8795 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
8797 // Get alias information for node.
8800 const Value *SrcValue;
8802 unsigned SrcValueAlign;
8803 const MDNode *SrcTBAAInfo;
8804 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
8805 SrcValueAlign, SrcTBAAInfo);
8808 Chains.push_back(OriginalChain);
8811 // Look at each chain and determine if it is an alias. If so, add it to the
8812 // aliases list. If not, then continue up the chain looking for the next
8814 while (!Chains.empty()) {
8815 SDValue Chain = Chains.back();
8818 // For TokenFactor nodes, look at each operand and only continue up the
8819 // chain until we find two aliases. If we've seen two aliases, assume we'll
8820 // find more and revert to original chain since the xform is unlikely to be
8823 // FIXME: The depth check could be made to return the last non-aliasing
8824 // chain we found before we hit a tokenfactor rather than the original
8826 if (Depth > 6 || Aliases.size() == 2) {
8828 Aliases.push_back(OriginalChain);
8832 // Don't bother if we've been before.
8833 if (!Visited.insert(Chain.getNode()))
8836 switch (Chain.getOpcode()) {
8837 case ISD::EntryToken:
8838 // Entry token is ideal chain operand, but handled in FindBetterChain.
8843 // Get alias information for Chain.
8846 const Value *OpSrcValue;
8847 int OpSrcValueOffset;
8848 unsigned OpSrcValueAlign;
8849 const MDNode *OpSrcTBAAInfo;
8850 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
8851 OpSrcValue, OpSrcValueOffset,
8855 // If chain is alias then stop here.
8856 if (!(IsLoad && IsOpLoad) &&
8857 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
8859 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
8860 OpSrcValueAlign, OpSrcTBAAInfo)) {
8861 Aliases.push_back(Chain);
8863 // Look further up the chain.
8864 Chains.push_back(Chain.getOperand(0));
8870 case ISD::TokenFactor:
8871 // We have to check each of the operands of the token factor for "small"
8872 // token factors, so we queue them up. Adding the operands to the queue
8873 // (stack) in reverse order maintains the original order and increases the
8874 // likelihood that getNode will find a matching token factor (CSE.)
8875 if (Chain.getNumOperands() > 16) {
8876 Aliases.push_back(Chain);
8879 for (unsigned n = Chain.getNumOperands(); n;)
8880 Chains.push_back(Chain.getOperand(--n));
8885 // For all other instructions we will just have to take what we can get.
8886 Aliases.push_back(Chain);
8892 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
8893 /// for a better chain (aliasing node.)
8894 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
8895 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
8897 // Accumulate all the aliases to this node.
8898 GatherAllAliases(N, OldChain, Aliases);
8900 // If no operands then chain to entry token.
8901 if (Aliases.size() == 0)
8902 return DAG.getEntryNode();
8904 // If a single operand then chain to it. We don't need to revisit it.
8905 if (Aliases.size() == 1)
8908 // Construct a custom tailored token factor.
8909 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
8910 &Aliases[0], Aliases.size());
8913 // SelectionDAG::Combine - This is the entry point for the file.
8915 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
8916 CodeGenOpt::Level OptLevel) {
8917 /// run - This is the main entry point to this class.
8919 DAGCombiner(*this, AA, OptLevel).Run(Level);