1 //==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAGInstrs class, which implements
11 // scheduling for a MachineInstr-based dependency graph.
13 //===----------------------------------------------------------------------===//
15 #ifndef SCHEDULEDAGINSTRS_H
16 #define SCHEDULEDAGINSTRS_H
18 #include "llvm/CodeGen/MachineDominators.h"
19 #include "llvm/CodeGen/MachineLoopInfo.h"
20 #include "llvm/CodeGen/ScheduleDAG.h"
21 #include "llvm/Support/Compiler.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include "llvm/ADT/SmallSet.h"
27 class MachineLoopInfo;
28 class MachineDominatorTree;
30 /// LoopDependencies - This class analyzes loop-oriented register
31 /// dependencies, which are used to guide scheduling decisions.
32 /// For example, loop induction variable increments should be
33 /// scheduled as soon as possible after the variable's last use.
35 class LLVM_LIBRARY_VISIBILITY LoopDependencies {
36 const MachineLoopInfo &MLI;
37 const MachineDominatorTree &MDT;
40 typedef std::map<unsigned, std::pair<const MachineOperand *, unsigned> >
44 LoopDependencies(const MachineLoopInfo &mli,
45 const MachineDominatorTree &mdt) :
48 /// VisitLoop - Clear out any previous state and analyze the given loop.
50 void VisitLoop(const MachineLoop *Loop) {
51 assert(Deps.empty() && "stale loop dependencies");
53 MachineBasicBlock *Header = Loop->getHeader();
54 SmallSet<unsigned, 8> LoopLiveIns;
55 for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(),
56 LE = Header->livein_end(); LI != LE; ++LI)
57 LoopLiveIns.insert(*LI);
59 const MachineDomTreeNode *Node = MDT.getNode(Header);
60 const MachineBasicBlock *MBB = Node->getBlock();
61 assert(Loop->contains(MBB) &&
62 "Loop does not contain header!");
63 VisitRegion(Node, MBB, Loop, LoopLiveIns);
67 void VisitRegion(const MachineDomTreeNode *Node,
68 const MachineBasicBlock *MBB,
69 const MachineLoop *Loop,
70 const SmallSet<unsigned, 8> &LoopLiveIns) {
72 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
74 const MachineInstr *MI = I;
75 if (MI->isDebugValue())
77 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
78 const MachineOperand &MO = MI->getOperand(i);
79 if (!MO.isReg() || !MO.isUse())
81 unsigned MOReg = MO.getReg();
82 if (LoopLiveIns.count(MOReg))
83 Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count)));
85 ++Count; // Not every iteration due to dbg_value above.
88 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
89 for (std::vector<MachineDomTreeNode*>::const_iterator I =
90 Children.begin(), E = Children.end(); I != E; ++I) {
91 const MachineDomTreeNode *ChildNode = *I;
92 MachineBasicBlock *ChildBlock = ChildNode->getBlock();
93 if (Loop->contains(ChildBlock))
94 VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns);
99 /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
101 class LLVM_LIBRARY_VISIBILITY ScheduleDAGInstrs : public ScheduleDAG {
102 const MachineLoopInfo &MLI;
103 const MachineDominatorTree &MDT;
104 const MachineFrameInfo *MFI;
105 const InstrItineraryData *InstrItins;
107 /// isPostRA flag indicates vregs cannot be present.
110 /// Defs, Uses - Remember where defs and uses of each register are as we
111 /// iterate upward through the instructions. This is allocated here instead
112 /// of inside BuildSchedGraph to avoid the need for it to be initialized and
113 /// destructed for each block.
114 std::vector<std::vector<SUnit *> > Defs;
115 std::vector<std::vector<SUnit *> > Uses;
117 /// PendingLoads - Remember where unknown loads are after the most recent
118 /// unknown store, as we iterate. As with Defs and Uses, this is here
119 /// to minimize construction/destruction.
120 std::vector<SUnit *> PendingLoads;
122 /// LoopRegs - Track which registers are used for loop-carried dependencies.
124 LoopDependencies LoopRegs;
128 /// DbgValues - Remember instruction that preceeds DBG_VALUE.
129 typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
131 DbgValueVector DbgValues;
132 MachineInstr *FirstDbgValue;
135 MachineBasicBlock::iterator Begin; // The beginning of the range to
136 // be scheduled. The range extends
138 unsigned InsertPosIndex; // The index in BB of InsertPos.
140 explicit ScheduleDAGInstrs(MachineFunction &mf,
141 const MachineLoopInfo &mli,
142 const MachineDominatorTree &mdt,
145 virtual ~ScheduleDAGInstrs() {}
147 /// NewSUnit - Creates a new SUnit and return a ptr to it.
149 SUnit *NewSUnit(MachineInstr *MI) {
151 const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
153 SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
154 assert((Addr == 0 || Addr == &SUnits[0]) &&
155 "SUnits std::vector reallocated on the fly!");
156 SUnits.back().OrigNode = &SUnits.back();
157 return &SUnits.back();
160 /// Run - perform scheduling.
162 void Run(MachineBasicBlock *bb,
163 MachineBasicBlock::iterator begin,
164 MachineBasicBlock::iterator end,
167 /// BuildSchedGraph - Build SUnits from the MachineBasicBlock that we are
169 virtual void BuildSchedGraph(AliasAnalysis *AA);
171 /// AddSchedBarrierDeps - Add dependencies from instructions in the current
172 /// list of instructions being scheduled to scheduling barrier. We want to
173 /// make sure instructions which define registers that are either used by
174 /// the terminator or are live-out are properly scheduled. This is
175 /// especially important when the definition latency of the return value(s)
176 /// are too high to be hidden by the branch or when the liveout registers
177 /// used by instructions in the fallthrough block.
178 void AddSchedBarrierDeps();
180 /// ComputeLatency - Compute node latency.
182 virtual void ComputeLatency(SUnit *SU);
184 /// ComputeOperandLatency - Override dependence edge latency using
185 /// operand use/def information
187 virtual void ComputeOperandLatency(SUnit *Def, SUnit *Use,
190 virtual MachineBasicBlock *EmitSchedule();
192 /// StartBlock - Prepare to perform scheduling in the given block.
194 virtual void StartBlock(MachineBasicBlock *BB);
196 /// Schedule - Order nodes according to selected style, filling
197 /// in the Sequence member.
199 virtual void Schedule() = 0;
201 /// FinishBlock - Clean up after scheduling in the given block.
203 virtual void FinishBlock();
205 virtual void dumpNode(const SUnit *SU) const;
207 virtual std::string getGraphNodeLabel(const SUnit *SU) const;