1 //==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAGInstrs class, which implements
11 // scheduling for a MachineInstr-based dependency graph.
13 //===----------------------------------------------------------------------===//
15 #ifndef SCHEDULEDAGINSTRS_H
16 #define SCHEDULEDAGINSTRS_H
18 #include "llvm/CodeGen/MachineDominators.h"
19 #include "llvm/CodeGen/MachineLoopInfo.h"
20 #include "llvm/CodeGen/ScheduleDAG.h"
21 #include "llvm/Support/Compiler.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include "llvm/ADT/SmallSet.h"
27 class MachineLoopInfo;
28 class MachineDominatorTree;
30 /// LoopDependencies - This class analyzes loop-oriented register
31 /// dependencies, which are used to guide scheduling decisions.
32 /// For example, loop induction variable increments should be
33 /// scheduled as soon as possible after the variable's last use.
35 class LLVM_LIBRARY_VISIBILITY LoopDependencies {
36 const MachineLoopInfo &MLI;
37 const MachineDominatorTree &MDT;
40 typedef std::map<unsigned, std::pair<const MachineOperand *, unsigned> >
44 LoopDependencies(const MachineLoopInfo &mli,
45 const MachineDominatorTree &mdt) :
48 /// VisitLoop - Clear out any previous state and analyze the given loop.
50 void VisitLoop(const MachineLoop *Loop) {
52 MachineBasicBlock *Header = Loop->getHeader();
53 SmallSet<unsigned, 8> LoopLiveIns;
54 for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(),
55 LE = Header->livein_end(); LI != LE; ++LI)
56 LoopLiveIns.insert(*LI);
58 const MachineDomTreeNode *Node = MDT.getNode(Header);
59 const MachineBasicBlock *MBB = Node->getBlock();
60 assert(Loop->contains(MBB) &&
61 "Loop does not contain header!");
62 VisitRegion(Node, MBB, Loop, LoopLiveIns);
66 void VisitRegion(const MachineDomTreeNode *Node,
67 const MachineBasicBlock *MBB,
68 const MachineLoop *Loop,
69 const SmallSet<unsigned, 8> &LoopLiveIns) {
71 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
73 const MachineInstr *MI = I;
74 if (MI->isDebugValue())
76 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
77 const MachineOperand &MO = MI->getOperand(i);
78 if (!MO.isReg() || !MO.isUse())
80 unsigned MOReg = MO.getReg();
81 if (LoopLiveIns.count(MOReg))
82 Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count)));
84 ++Count; // Not every iteration due to dbg_value above.
87 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
88 for (std::vector<MachineDomTreeNode*>::const_iterator I =
89 Children.begin(), E = Children.end(); I != E; ++I) {
90 const MachineDomTreeNode *ChildNode = *I;
91 MachineBasicBlock *ChildBlock = ChildNode->getBlock();
92 if (Loop->contains(ChildBlock))
93 VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns);
98 /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
100 class LLVM_LIBRARY_VISIBILITY ScheduleDAGInstrs : public ScheduleDAG {
101 const MachineLoopInfo &MLI;
102 const MachineDominatorTree &MDT;
103 const MachineFrameInfo *MFI;
105 /// Defs, Uses - Remember where defs and uses of each physical register
106 /// are as we iterate upward through the instructions. This is allocated
107 /// here instead of inside BuildSchedGraph to avoid the need for it to be
108 /// initialized and destructed for each block.
109 std::vector<SUnit *> Defs[TargetRegisterInfo::FirstVirtualRegister];
110 std::vector<SUnit *> Uses[TargetRegisterInfo::FirstVirtualRegister];
112 /// DbgValueVec - Remember DBG_VALUEs that refer to a particular
114 std::vector<MachineInstr *>DbgValueVec;
116 /// PendingLoads - Remember where unknown loads are after the most recent
117 /// unknown store, as we iterate. As with Defs and Uses, this is here
118 /// to minimize construction/destruction.
119 std::vector<SUnit *> PendingLoads;
121 /// LoopRegs - Track which registers are used for loop-carried dependencies.
123 LoopDependencies LoopRegs;
125 /// LoopLiveInRegs - Track which regs are live into a loop, to help guide
126 /// back-edge-aware scheduling.
128 SmallSet<unsigned, 8> LoopLiveInRegs;
131 MachineBasicBlock::iterator Begin; // The beginning of the range to
132 // be scheduled. The range extends
134 unsigned InsertPosIndex; // The index in BB of InsertPos.
136 explicit ScheduleDAGInstrs(MachineFunction &mf,
137 const MachineLoopInfo &mli,
138 const MachineDominatorTree &mdt);
140 virtual ~ScheduleDAGInstrs() {}
142 /// NewSUnit - Creates a new SUnit and return a ptr to it.
144 SUnit *NewSUnit(MachineInstr *MI) {
146 const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
148 SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
149 assert((Addr == 0 || Addr == &SUnits[0]) &&
150 "SUnits std::vector reallocated on the fly!");
151 SUnits.back().OrigNode = &SUnits.back();
152 return &SUnits.back();
155 /// Run - perform scheduling.
157 void Run(MachineBasicBlock *bb,
158 MachineBasicBlock::iterator begin,
159 MachineBasicBlock::iterator end,
162 /// BuildSchedGraph - Build SUnits from the MachineBasicBlock that we are
164 virtual void BuildSchedGraph(AliasAnalysis *AA);
166 /// ComputeLatency - Compute node latency.
168 virtual void ComputeLatency(SUnit *SU);
170 /// ComputeOperandLatency - Override dependence edge latency using
171 /// operand use/def information
173 virtual void ComputeOperandLatency(SUnit *Def, SUnit *Use,
176 virtual MachineBasicBlock *EmitSchedule();
178 /// StartBlock - Prepare to perform scheduling in the given block.
180 virtual void StartBlock(MachineBasicBlock *BB);
182 /// Schedule - Order nodes according to selected style, filling
183 /// in the Sequence member.
185 virtual void Schedule() = 0;
187 /// FinishBlock - Clean up after scheduling in the given block.
189 virtual void FinishBlock();
191 virtual void dumpNode(const SUnit *SU) const;
193 virtual std::string getGraphNodeLabel(const SUnit *SU) const;