1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAGInstrs class, which implements re-scheduling
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "misched"
16 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
17 #include "llvm/ADT/MapVector.h"
18 #include "llvm/ADT/SmallPtrSet.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ValueTracking.h"
22 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineMemOperand.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/RegisterPressure.h"
29 #include "llvm/CodeGen/ScheduleDFS.h"
30 #include "llvm/IR/Operator.h"
31 #include "llvm/MC/MCInstrItineraries.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/Format.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
44 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
45 cl::ZeroOrMore, cl::init(false),
46 cl::desc("Enable use of AA during MI GAD construction"));
48 // FIXME: Enable the use of TBAA. There are two known issues preventing this:
49 // 1. Stack coloring does not update TBAA when merging allocas
50 // 2. CGP inserts ptrtoint/inttoptr pairs when sinking address computations.
51 // Because BasicAA does not handle inttoptr, we'll often miss basic type
52 // punning idioms that we need to catch so we don't miscompile real-world
54 static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
55 cl::init(false), cl::desc("Enable use of TBAA during MI GAD construction"));
57 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
58 const MachineLoopInfo &mli,
59 const MachineDominatorTree &mdt,
63 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), LIS(lis),
64 IsPostRA(IsPostRAFlag), RemoveKillFlags(RemoveKillFlags),
65 CanHandleTerminators(false), FirstDbgValue(0) {
66 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
68 assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
69 "Virtual registers must be removed prior to PostRA scheduling");
71 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
72 SchedModel.init(*ST.getSchedModel(), &ST, TII);
75 /// getUnderlyingObjectFromInt - This is the function that does the work of
76 /// looking through basic ptrtoint+arithmetic+inttoptr sequences.
77 static const Value *getUnderlyingObjectFromInt(const Value *V) {
79 if (const Operator *U = dyn_cast<Operator>(V)) {
80 // If we find a ptrtoint, we can transfer control back to the
81 // regular getUnderlyingObjectFromInt.
82 if (U->getOpcode() == Instruction::PtrToInt)
83 return U->getOperand(0);
84 // If we find an add of a constant, a multiplied value, or a phi, it's
85 // likely that the other operand will lead us to the base
86 // object. We don't have to worry about the case where the
87 // object address is somehow being computed by the multiply,
88 // because our callers only care when the result is an
89 // identifiable object.
90 if (U->getOpcode() != Instruction::Add ||
91 (!isa<ConstantInt>(U->getOperand(1)) &&
92 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul &&
93 !isa<PHINode>(U->getOperand(1))))
99 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
103 /// getUnderlyingObjects - This is a wrapper around GetUnderlyingObjects
104 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
105 static void getUnderlyingObjects(const Value *V,
106 SmallVectorImpl<Value *> &Objects) {
107 SmallPtrSet<const Value*, 16> Visited;
108 SmallVector<const Value *, 4> Working(1, V);
110 V = Working.pop_back_val();
112 SmallVector<Value *, 4> Objs;
113 GetUnderlyingObjects(const_cast<Value *>(V), Objs);
115 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), IE = Objs.end();
118 if (!Visited.insert(V))
120 if (Operator::getOpcode(V) == Instruction::IntToPtr) {
122 getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
123 if (O->getType()->isPointerTy()) {
124 Working.push_back(O);
128 Objects.push_back(const_cast<Value *>(V));
130 } while (!Working.empty());
133 typedef SmallVector<PointerIntPair<const Value *, 1, bool>, 4>
134 UnderlyingObjectsVector;
136 /// getUnderlyingObjectsForInstr - If this machine instr has memory reference
137 /// information and it can be tracked to a normal reference to a known
138 /// object, return the Value for that object.
139 static void getUnderlyingObjectsForInstr(const MachineInstr *MI,
140 const MachineFrameInfo *MFI,
141 UnderlyingObjectsVector &Objects) {
142 if (!MI->hasOneMemOperand() ||
143 !(*MI->memoperands_begin())->getValue() ||
144 (*MI->memoperands_begin())->isVolatile())
147 const Value *V = (*MI->memoperands_begin())->getValue();
151 SmallVector<Value *, 4> Objs;
152 getUnderlyingObjects(V, Objs);
154 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), IE = Objs.end();
156 bool MayAlias = true;
159 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
160 // For now, ignore PseudoSourceValues which may alias LLVM IR values
161 // because the code that uses this function has no way to cope with
164 if (PSV->isAliased(MFI)) {
169 MayAlias = PSV->mayAlias(MFI);
170 } else if (!isIdentifiedObject(V)) {
175 Objects.push_back(UnderlyingObjectsVector::value_type(V, MayAlias));
179 void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
183 void ScheduleDAGInstrs::finishBlock() {
184 // Subclasses should no longer refer to the old block.
188 /// Initialize the DAG and common scheduler state for the current scheduling
189 /// region. This does not actually create the DAG, only clears it. The
190 /// scheduling driver may call BuildSchedGraph multiple times per scheduling
192 void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
193 MachineBasicBlock::iterator begin,
194 MachineBasicBlock::iterator end,
195 unsigned regioninstrs) {
196 assert(bb == BB && "startBlock should set BB");
199 NumRegionInstrs = regioninstrs;
202 /// Close the current scheduling region. Don't clear any state in case the
203 /// driver wants to refer to the previous scheduling region.
204 void ScheduleDAGInstrs::exitRegion() {
208 /// addSchedBarrierDeps - Add dependencies from instructions in the current
209 /// list of instructions being scheduled to scheduling barrier by adding
210 /// the exit SU to the register defs and use list. This is because we want to
211 /// make sure instructions which define registers that are either used by
212 /// the terminator or are live-out are properly scheduled. This is
213 /// especially important when the definition latency of the return value(s)
214 /// are too high to be hidden by the branch or when the liveout registers
215 /// used by instructions in the fallthrough block.
216 void ScheduleDAGInstrs::addSchedBarrierDeps() {
217 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : 0;
218 ExitSU.setInstr(ExitMI);
219 bool AllDepKnown = ExitMI &&
220 (ExitMI->isCall() || ExitMI->isBarrier());
221 if (ExitMI && AllDepKnown) {
222 // If it's a call or a barrier, add dependencies on the defs and uses of
224 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
225 const MachineOperand &MO = ExitMI->getOperand(i);
226 if (!MO.isReg() || MO.isDef()) continue;
227 unsigned Reg = MO.getReg();
228 if (Reg == 0) continue;
230 if (TRI->isPhysicalRegister(Reg))
231 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
233 assert(!IsPostRA && "Virtual register encountered after regalloc.");
234 if (MO.readsReg()) // ignore undef operands
235 addVRegUseDeps(&ExitSU, i);
239 // For others, e.g. fallthrough, conditional branch, assume the exit
240 // uses all the registers that are livein to the successor blocks.
241 assert(Uses.empty() && "Uses in set before adding deps?");
242 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
243 SE = BB->succ_end(); SI != SE; ++SI)
244 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
245 E = (*SI)->livein_end(); I != E; ++I) {
247 if (!Uses.contains(Reg))
248 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
253 /// MO is an operand of SU's instruction that defines a physical register. Add
254 /// data dependencies from SU to any uses of the physical register.
255 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
256 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
257 assert(MO.isDef() && "expect physreg def");
259 // Ask the target if address-backscheduling is desirable, and if so how much.
260 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
262 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
263 Alias.isValid(); ++Alias) {
264 if (!Uses.contains(*Alias))
266 for (Reg2SUnitsMap::iterator I = Uses.find(*Alias); I != Uses.end(); ++I) {
267 SUnit *UseSU = I->SU;
271 // Adjust the dependence latency using operand def/use information,
272 // then allow the target to perform its own adjustments.
273 int UseOp = I->OpIdx;
274 MachineInstr *RegUse = 0;
277 Dep = SDep(SU, SDep::Artificial);
279 // Set the hasPhysRegDefs only for physreg defs that have a use within
280 // the scheduling region.
281 SU->hasPhysRegDefs = true;
282 Dep = SDep(SU, SDep::Data, *Alias);
283 RegUse = UseSU->getInstr();
286 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,
289 ST.adjustSchedDependency(SU, UseSU, Dep);
295 /// addPhysRegDeps - Add register dependencies (data, anti, and output) from
296 /// this SUnit to following instructions in the same scheduling region that
297 /// depend the physical register referenced at OperIdx.
298 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
299 MachineInstr *MI = SU->getInstr();
300 MachineOperand &MO = MI->getOperand(OperIdx);
302 // Optionally add output and anti dependencies. For anti
303 // dependencies we use a latency of 0 because for a multi-issue
304 // target we want to allow the defining instruction to issue
305 // in the same cycle as the using instruction.
306 // TODO: Using a latency of 1 here for output dependencies assumes
307 // there's no cost for reusing registers.
308 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
309 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
310 Alias.isValid(); ++Alias) {
311 if (!Defs.contains(*Alias))
313 for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) {
314 SUnit *DefSU = I->SU;
315 if (DefSU == &ExitSU)
318 (Kind != SDep::Output || !MO.isDead() ||
319 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
320 if (Kind == SDep::Anti)
321 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
323 SDep Dep(SU, Kind, /*Reg=*/*Alias);
325 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
333 SU->hasPhysRegUses = true;
334 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
335 // retrieve the existing SUnits list for this register's uses.
336 // Push this SUnit on the use list.
337 Uses.insert(PhysRegSUOper(SU, OperIdx, MO.getReg()));
342 addPhysRegDataDeps(SU, OperIdx);
343 unsigned Reg = MO.getReg();
345 // clear this register's use list
346 if (Uses.contains(Reg))
351 } else if (SU->isCall) {
352 // Calls will not be reordered because of chain dependencies (see
353 // below). Since call operands are dead, calls may continue to be added
354 // to the DefList making dependence checking quadratic in the size of
355 // the block. Instead, we leave only one call at the back of the
357 Reg2SUnitsMap::RangePair P = Defs.equal_range(Reg);
358 Reg2SUnitsMap::iterator B = P.first;
359 Reg2SUnitsMap::iterator I = P.second;
360 for (bool isBegin = I == B; !isBegin; /* empty */) {
361 isBegin = (--I) == B;
368 // Defs are pushed in the order they are visited and never reordered.
369 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));
373 /// addVRegDefDeps - Add register output and data dependencies from this SUnit
374 /// to instructions that occur later in the same scheduling region if they read
375 /// from or write to the virtual register defined at OperIdx.
377 /// TODO: Hoist loop induction variable increments. This has to be
378 /// reevaluated. Generally, IV scheduling should be done before coalescing.
379 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
380 const MachineInstr *MI = SU->getInstr();
381 unsigned Reg = MI->getOperand(OperIdx).getReg();
383 // Singly defined vregs do not have output/anti dependencies.
384 // The current operand is a def, so we have at least one.
385 // Check here if there are any others...
386 if (MRI.hasOneDef(Reg))
389 // Add output dependence to the next nearest def of this vreg.
391 // Unless this definition is dead, the output dependence should be
392 // transitively redundant with antidependencies from this definition's
393 // uses. We're conservative for now until we have a way to guarantee the uses
394 // are not eliminated sometime during scheduling. The output dependence edge
395 // is also useful if output latency exceeds def-use latency.
396 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
397 if (DefI == VRegDefs.end())
398 VRegDefs.insert(VReg2SUnit(Reg, SU));
400 SUnit *DefSU = DefI->SU;
401 if (DefSU != SU && DefSU != &ExitSU) {
402 SDep Dep(SU, SDep::Output, Reg);
404 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
411 /// addVRegUseDeps - Add a register data dependency if the instruction that
412 /// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
413 /// register antidependency from this SUnit to instructions that occur later in
414 /// the same scheduling region if they write the virtual register.
416 /// TODO: Handle ExitSU "uses" properly.
417 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
418 MachineInstr *MI = SU->getInstr();
419 unsigned Reg = MI->getOperand(OperIdx).getReg();
421 // Record this local VReg use.
422 VReg2UseMap::iterator UI = VRegUses.find(Reg);
423 for (; UI != VRegUses.end(); ++UI) {
427 if (UI == VRegUses.end())
428 VRegUses.insert(VReg2SUnit(Reg, SU));
430 // Lookup this operand's reaching definition.
431 assert(LIS && "vreg dependencies requires LiveIntervals");
433 = LIS->getInterval(Reg).Query(LIS->getInstructionIndex(MI));
434 VNInfo *VNI = LRQ.valueIn();
436 // VNI will be valid because MachineOperand::readsReg() is checked by caller.
437 assert(VNI && "No value to read by operand");
438 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
439 // Phis and other noninstructions (after coalescing) have a NULL Def.
441 SUnit *DefSU = getSUnit(Def);
443 // The reaching Def lives within this scheduling region.
444 // Create a data dependence.
445 SDep dep(DefSU, SDep::Data, Reg);
446 // Adjust the dependence latency using operand def/use information, then
447 // allow the target to perform its own adjustments.
448 int DefOp = Def->findRegisterDefOperandIdx(Reg);
449 dep.setLatency(SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx));
451 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
452 ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
457 // Add antidependence to the following def of the vreg it uses.
458 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
459 if (DefI != VRegDefs.end() && DefI->SU != SU)
460 DefI->SU->addPred(SDep(SU, SDep::Anti, Reg));
463 /// Return true if MI is an instruction we are unable to reason about
464 /// (like a call or something with unmodeled side effects).
465 static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
466 if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
467 (MI->hasOrderedMemoryRef() &&
468 (!MI->mayLoad() || !MI->isInvariantLoad(AA))))
473 // This MI might have either incomplete info, or known to be unsafe
474 // to deal with (i.e. volatile object).
475 static inline bool isUnsafeMemoryObject(MachineInstr *MI,
476 const MachineFrameInfo *MFI) {
477 if (!MI || MI->memoperands_empty())
479 // We purposefully do no check for hasOneMemOperand() here
480 // in hope to trigger an assert downstream in order to
481 // finish implementation.
482 if ((*MI->memoperands_begin())->isVolatile() ||
483 MI->hasUnmodeledSideEffects())
485 const Value *V = (*MI->memoperands_begin())->getValue();
489 SmallVector<Value *, 4> Objs;
490 getUnderlyingObjects(V, Objs);
491 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(),
492 IE = Objs.end(); I != IE; ++I) {
495 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
496 // Similarly to getUnderlyingObjectForInstr:
497 // For now, ignore PseudoSourceValues which may alias LLVM IR values
498 // because the code that uses this function has no way to cope with
500 if (PSV->isAliased(MFI))
504 // Does this pointer refer to a distinct and identifiable object?
505 if (!isIdentifiedObject(V))
512 /// This returns true if the two MIs need a chain edge betwee them.
513 /// If these are not even memory operations, we still may need
514 /// chain deps between them. The question really is - could
515 /// these two MIs be reordered during scheduling from memory dependency
517 static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI,
520 // Cover a trivial case - no edge is need to itself.
524 // FIXME: Need to handle multiple memory operands to support all targets.
525 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())
528 if (isUnsafeMemoryObject(MIa, MFI) || isUnsafeMemoryObject(MIb, MFI))
531 // If we are dealing with two "normal" loads, we do not need an edge
532 // between them - they could be reordered.
533 if (!MIa->mayStore() && !MIb->mayStore())
536 // To this point analysis is generic. From here on we do need AA.
540 MachineMemOperand *MMOa = *MIa->memoperands_begin();
541 MachineMemOperand *MMOb = *MIb->memoperands_begin();
543 // The following interface to AA is fashioned after DAGCombiner::isAlias
544 // and operates with MachineMemOperand offset with some important
546 // - LLVM fundamentally assumes flat address spaces.
547 // - MachineOperand offset can *only* result from legalization and
548 // cannot affect queries other than the trivial case of overlap
550 // - These offsets never wrap and never step outside
551 // of allocated objects.
552 // - There should never be any negative offsets here.
554 // FIXME: Modify API to hide this math from "user"
555 // FIXME: Even before we go to AA we can reason locally about some
556 // memory objects. It can save compile time, and possibly catch some
557 // corner cases not currently covered.
559 assert ((MMOa->getOffset() >= 0) && "Negative MachineMemOperand offset");
560 assert ((MMOb->getOffset() >= 0) && "Negative MachineMemOperand offset");
562 int64_t MinOffset = std::min(MMOa->getOffset(), MMOb->getOffset());
563 int64_t Overlapa = MMOa->getSize() + MMOa->getOffset() - MinOffset;
564 int64_t Overlapb = MMOb->getSize() + MMOb->getOffset() - MinOffset;
566 AliasAnalysis::AliasResult AAResult = AA->alias(
567 AliasAnalysis::Location(MMOa->getValue(), Overlapa,
568 UseTBAA ? MMOa->getTBAAInfo() : 0),
569 AliasAnalysis::Location(MMOb->getValue(), Overlapb,
570 UseTBAA ? MMOb->getTBAAInfo() : 0));
572 return (AAResult != AliasAnalysis::NoAlias);
575 /// This recursive function iterates over chain deps of SUb looking for
576 /// "latest" node that needs a chain edge to SUa.
578 iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI,
579 SUnit *SUa, SUnit *SUb, SUnit *ExitSU, unsigned *Depth,
580 SmallPtrSet<const SUnit*, 16> &Visited) {
581 if (!SUa || !SUb || SUb == ExitSU)
584 // Remember visited nodes.
585 if (!Visited.insert(SUb))
587 // If there is _some_ dependency already in place, do not
588 // descend any further.
589 // TODO: Need to make sure that if that dependency got eliminated or ignored
590 // for any reason in the future, we would not violate DAG topology.
591 // Currently it does not happen, but makes an implicit assumption about
592 // future implementation.
594 // Independently, if we encounter node that is some sort of global
595 // object (like a call) we already have full set of dependencies to it
596 // and we can stop descending.
597 if (SUa->isSucc(SUb) ||
598 isGlobalMemoryObject(AA, SUb->getInstr()))
601 // If we do need an edge, or we have exceeded depth budget,
602 // add that edge to the predecessors chain of SUb,
603 // and stop descending.
605 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
606 SUb->addPred(SDep(SUa, SDep::MayAliasMem));
609 // Track current depth.
611 // Iterate over chain dependencies only.
612 for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end();
615 iterateChainSucc (AA, MFI, SUa, I->getSUnit(), ExitSU, Depth, Visited);
619 /// This function assumes that "downward" from SU there exist
620 /// tail/leaf of already constructed DAG. It iterates downward and
621 /// checks whether SU can be aliasing any node dominated
623 static void adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI,
624 SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList,
625 unsigned LatencyToLoad) {
629 SmallPtrSet<const SUnit*, 16> Visited;
632 for (std::set<SUnit *>::iterator I = CheckList.begin(), IE = CheckList.end();
636 if (MIsNeedChainEdge(AA, MFI, SU->getInstr(), (*I)->getInstr())) {
637 SDep Dep(SU, SDep::MayAliasMem);
638 Dep.setLatency(((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0);
641 // Now go through all the chain successors and iterate from them.
642 // Keep track of visited nodes.
643 for (SUnit::const_succ_iterator J = (*I)->Succs.begin(),
644 JE = (*I)->Succs.end(); J != JE; ++J)
646 iterateChainSucc (AA, MFI, SU, J->getSUnit(),
647 ExitSU, &Depth, Visited);
651 /// Check whether two objects need a chain edge, if so, add it
652 /// otherwise remember the rejected SU.
654 void addChainDependency (AliasAnalysis *AA, const MachineFrameInfo *MFI,
655 SUnit *SUa, SUnit *SUb,
656 std::set<SUnit *> &RejectList,
657 unsigned TrueMemOrderLatency = 0,
658 bool isNormalMemory = false) {
659 // If this is a false dependency,
660 // do not add the edge, but rememeber the rejected node.
661 if (!AA || MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
662 SDep Dep(SUa, isNormalMemory ? SDep::MayAliasMem : SDep::Barrier);
663 Dep.setLatency(TrueMemOrderLatency);
667 // Duplicate entries should be ignored.
668 RejectList.insert(SUb);
669 DEBUG(dbgs() << "\tReject chain dep between SU("
670 << SUa->NodeNum << ") and SU("
671 << SUb->NodeNum << ")\n");
675 /// Create an SUnit for each real instruction, numbered in top-down toplological
676 /// order. The instruction order A < B, implies that no edge exists from B to A.
678 /// Map each real instruction to its SUnit.
680 /// After initSUnits, the SUnits vector cannot be resized and the scheduler may
681 /// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
682 /// instead of pointers.
684 /// MachineScheduler relies on initSUnits numbering the nodes by their order in
685 /// the original instruction list.
686 void ScheduleDAGInstrs::initSUnits() {
687 // We'll be allocating one SUnit for each real instruction in the region,
688 // which is contained within a basic block.
689 SUnits.reserve(NumRegionInstrs);
691 for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) {
692 MachineInstr *MI = I;
693 if (MI->isDebugValue())
696 SUnit *SU = newSUnit(MI);
699 SU->isCall = MI->isCall();
700 SU->isCommutable = MI->isCommutable();
702 // Assign the Latency field of SU using target-provided information.
703 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
705 // If this SUnit uses an unbuffered resource, mark it as such.
706 // These resources are used for in-order execution pipelines within an
707 // out-of-order core and are identified by BufferSize=1. BufferSize=0 is
708 // used for dispatch/issue groups and is not considered here.
709 if (SchedModel.hasInstrSchedModel()) {
710 const MCSchedClassDesc *SC = getSchedClass(SU);
711 for (TargetSchedModel::ProcResIter
712 PI = SchedModel.getWriteProcResBegin(SC),
713 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
714 switch (SchedModel.getProcResource(PI->ProcResourceIdx)->BufferSize) {
716 SU->hasReservedResource = true;
719 SU->isUnbuffered = true;
729 /// If RegPressure is non-null, compute register pressure as a side effect. The
730 /// DAG builder is an efficient place to do it because it already visits
732 void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
733 RegPressureTracker *RPTracker,
734 PressureDiffs *PDiffs) {
735 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
736 bool UseAA = EnableAASchedMI.getNumOccurrences() > 0 ? EnableAASchedMI
738 AliasAnalysis *AAForDep = UseAA ? AA : 0;
741 ScheduleDAG::clearDAG();
743 // Create an SUnit for each real instruction.
747 PDiffs->init(SUnits.size());
749 // We build scheduling units by walking a block's instruction list from bottom
752 // Remember where a generic side-effecting instruction is as we procede.
753 SUnit *BarrierChain = 0, *AliasChain = 0;
755 // Memory references to specific known memory locations are tracked
756 // so that they can be given more precise dependencies. We track
757 // separately the known memory locations that may alias and those
758 // that are known not to alias
759 MapVector<const Value *, std::vector<SUnit *> > AliasMemDefs, NonAliasMemDefs;
760 MapVector<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
761 std::set<SUnit*> RejectMemNodes;
763 // Remove any stale debug info; sometimes BuildSchedGraph is called again
764 // without emitting the info from the previous call.
766 FirstDbgValue = NULL;
768 assert(Defs.empty() && Uses.empty() &&
769 "Only BuildGraph should update Defs/Uses");
770 Defs.setUniverse(TRI->getNumRegs());
771 Uses.setUniverse(TRI->getNumRegs());
773 assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs");
775 VRegDefs.setUniverse(MRI.getNumVirtRegs());
776 VRegUses.setUniverse(MRI.getNumVirtRegs());
778 // Model data dependencies between instructions being scheduled and the
780 addSchedBarrierDeps();
782 // Walk the list of instructions, from bottom moving up.
783 MachineInstr *DbgMI = NULL;
784 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
786 MachineInstr *MI = prior(MII);
788 DbgValues.push_back(std::make_pair(DbgMI, MI));
792 if (MI->isDebugValue()) {
796 SUnit *SU = MISUnitMap[MI];
797 assert(SU && "No SUnit mapped to this MI");
800 PressureDiff *PDiff = PDiffs ? &(*PDiffs)[SU->NodeNum] : 0;
801 RPTracker->recede(/*LiveUses=*/0, PDiff);
802 assert(RPTracker->getPos() == prior(MII) && "RPTracker can't find MI");
805 assert((CanHandleTerminators || (!MI->isTerminator() && !MI->isLabel())) &&
806 "Cannot schedule terminators or labels!");
808 // Add register-based dependencies (data, anti, and output).
809 bool HasVRegDef = false;
810 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
811 const MachineOperand &MO = MI->getOperand(j);
812 if (!MO.isReg()) continue;
813 unsigned Reg = MO.getReg();
814 if (Reg == 0) continue;
816 if (TRI->isPhysicalRegister(Reg))
817 addPhysRegDeps(SU, j);
819 assert(!IsPostRA && "Virtual register encountered!");
822 addVRegDefDeps(SU, j);
824 else if (MO.readsReg()) // ignore undef operands
825 addVRegUseDeps(SU, j);
828 // If we haven't seen any uses in this scheduling region, create a
829 // dependence edge to ExitSU to model the live-out latency. This is required
830 // for vreg defs with no in-region use, and prefetches with no vreg def.
832 // FIXME: NumDataSuccs would be more precise than NumSuccs here. This
833 // check currently relies on being called before adding chain deps.
834 if (SU->NumSuccs == 0 && SU->Latency > 1
835 && (HasVRegDef || MI->mayLoad())) {
836 SDep Dep(SU, SDep::Artificial);
837 Dep.setLatency(SU->Latency - 1);
841 // Add chain dependencies.
842 // Chain dependencies used to enforce memory order should have
843 // latency of 0 (except for true dependency of Store followed by
844 // aliased Load... we estimate that with a single cycle of latency
845 // assuming the hardware will bypass)
846 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
847 // after stack slots are lowered to actual addresses.
848 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and
849 // produce more precise dependence information.
850 unsigned TrueMemOrderLatency = MI->mayStore() ? 1 : 0;
851 if (isGlobalMemoryObject(AA, MI)) {
852 // Be conservative with these and add dependencies on all memory
853 // references, even those that are known to not alias.
854 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
855 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
856 for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
857 I->second[i]->addPred(SDep(SU, SDep::Barrier));
860 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
861 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
862 for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
863 SDep Dep(SU, SDep::Barrier);
864 Dep.setLatency(TrueMemOrderLatency);
865 I->second[i]->addPred(Dep);
868 // Add SU to the barrier chain.
870 BarrierChain->addPred(SDep(SU, SDep::Barrier));
872 // This is a barrier event that acts as a pivotal node in the DAG,
873 // so it is safe to clear list of exposed nodes.
874 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
875 TrueMemOrderLatency);
876 RejectMemNodes.clear();
877 NonAliasMemDefs.clear();
878 NonAliasMemUses.clear();
882 // Chain all possibly aliasing memory references though SU.
884 unsigned ChainLatency = 0;
885 if (AliasChain->getInstr()->mayLoad())
886 ChainLatency = TrueMemOrderLatency;
887 addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes,
891 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
892 addChainDependency(AAForDep, MFI, SU, PendingLoads[k], RejectMemNodes,
893 TrueMemOrderLatency);
894 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
895 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I) {
896 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
897 addChainDependency(AAForDep, MFI, SU, I->second[i], RejectMemNodes);
899 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
900 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
901 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
902 addChainDependency(AAForDep, MFI, SU, I->second[i], RejectMemNodes,
903 TrueMemOrderLatency);
905 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
906 TrueMemOrderLatency);
907 PendingLoads.clear();
908 AliasMemDefs.clear();
909 AliasMemUses.clear();
910 } else if (MI->mayStore()) {
911 UnderlyingObjectsVector Objs;
912 getUnderlyingObjectsForInstr(MI, MFI, Objs);
915 // Treat all other stores conservatively.
916 goto new_alias_chain;
919 bool MayAlias = false;
920 for (UnderlyingObjectsVector::iterator K = Objs.begin(), KE = Objs.end();
922 const Value *V = K->getPointer();
923 bool ThisMayAlias = K->getInt();
927 // A store to a specific PseudoSourceValue. Add precise dependencies.
928 // Record the def in MemDefs, first adding a dep if there is
930 MapVector<const Value *, std::vector<SUnit *> >::iterator I =
931 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
932 MapVector<const Value *, std::vector<SUnit *> >::iterator IE =
933 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
935 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
936 addChainDependency(AAForDep, MFI, SU, I->second[i], RejectMemNodes,
939 // If we're not using AA, then we only need one store per object.
942 I->second.push_back(SU);
946 AliasMemDefs[V].clear();
947 AliasMemDefs[V].push_back(SU);
950 NonAliasMemDefs[V].clear();
951 NonAliasMemDefs[V].push_back(SU);
954 // Handle the uses in MemUses, if there are any.
955 MapVector<const Value *, std::vector<SUnit *> >::iterator J =
956 ((ThisMayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
957 MapVector<const Value *, std::vector<SUnit *> >::iterator JE =
958 ((ThisMayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
960 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
961 addChainDependency(AAForDep, MFI, SU, J->second[i], RejectMemNodes,
962 TrueMemOrderLatency, true);
967 // Add dependencies from all the PendingLoads, i.e. loads
968 // with no underlying object.
969 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
970 addChainDependency(AAForDep, MFI, SU, PendingLoads[k], RejectMemNodes,
971 TrueMemOrderLatency);
972 // Add dependence on alias chain, if needed.
974 addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes);
975 // But we also should check dependent instructions for the
977 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
978 TrueMemOrderLatency);
980 // Add dependence on barrier chain, if needed.
981 // There is no point to check aliasing on barrier event. Even if
982 // SU and barrier _could_ be reordered, they should not. In addition,
983 // we have lost all RejectMemNodes below barrier.
985 BarrierChain->addPred(SDep(SU, SDep::Barrier));
987 if (!ExitSU.isPred(SU))
988 // Push store's up a bit to avoid them getting in between cmp
990 ExitSU.addPred(SDep(SU, SDep::Artificial));
991 } else if (MI->mayLoad()) {
992 bool MayAlias = true;
993 if (MI->isInvariantLoad(AA)) {
994 // Invariant load, no chain dependencies needed!
996 UnderlyingObjectsVector Objs;
997 getUnderlyingObjectsForInstr(MI, MFI, Objs);
1000 // A load with no underlying object. Depend on all
1001 // potentially aliasing stores.
1002 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
1003 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
1004 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1005 addChainDependency(AAForDep, MFI, SU, I->second[i],
1008 PendingLoads.push_back(SU);
1014 for (UnderlyingObjectsVector::iterator
1015 J = Objs.begin(), JE = Objs.end(); J != JE; ++J) {
1016 const Value *V = J->getPointer();
1017 bool ThisMayAlias = J->getInt();
1022 // A load from a specific PseudoSourceValue. Add precise dependencies.
1023 MapVector<const Value *, std::vector<SUnit *> >::iterator I =
1024 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
1025 MapVector<const Value *, std::vector<SUnit *> >::iterator IE =
1026 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
1028 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1029 addChainDependency(AAForDep, MFI, SU, I->second[i],
1030 RejectMemNodes, 0, true);
1032 AliasMemUses[V].push_back(SU);
1034 NonAliasMemUses[V].push_back(SU);
1037 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, /*Latency=*/0);
1038 // Add dependencies on alias and barrier chains, if needed.
1039 if (MayAlias && AliasChain)
1040 addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes);
1042 BarrierChain->addPred(SDep(SU, SDep::Barrier));
1047 FirstDbgValue = DbgMI;
1052 PendingLoads.clear();
1055 /// \brief Initialize register live-range state for updating kills.
1056 void ScheduleDAGInstrs::startBlockForKills(MachineBasicBlock *BB) {
1057 // Start with no live registers.
1060 // Examine the live-in regs of all successors.
1061 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
1062 SE = BB->succ_end(); SI != SE; ++SI) {
1063 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
1064 E = (*SI)->livein_end(); I != E; ++I) {
1066 // Repeat, for reg and all subregs.
1067 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1068 SubRegs.isValid(); ++SubRegs)
1069 LiveRegs.set(*SubRegs);
1074 bool ScheduleDAGInstrs::toggleKillFlag(MachineInstr *MI, MachineOperand &MO) {
1075 // Setting kill flag...
1081 // If MO itself is live, clear the kill flag...
1082 if (LiveRegs.test(MO.getReg())) {
1083 MO.setIsKill(false);
1087 // If any subreg of MO is live, then create an imp-def for that
1088 // subreg and keep MO marked as killed.
1089 MO.setIsKill(false);
1090 bool AllDead = true;
1091 const unsigned SuperReg = MO.getReg();
1092 MachineInstrBuilder MIB(MF, MI);
1093 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
1094 if (LiveRegs.test(*SubRegs)) {
1095 MIB.addReg(*SubRegs, RegState::ImplicitDefine);
1105 // FIXME: Reuse the LivePhysRegs utility for this.
1106 void ScheduleDAGInstrs::fixupKills(MachineBasicBlock *MBB) {
1107 DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
1109 LiveRegs.resize(TRI->getNumRegs());
1110 BitVector killedRegs(TRI->getNumRegs());
1112 startBlockForKills(MBB);
1114 // Examine block from end to start...
1115 unsigned Count = MBB->size();
1116 for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
1118 MachineInstr *MI = --I;
1119 if (MI->isDebugValue())
1122 // Update liveness. Registers that are defed but not used in this
1123 // instruction are now dead. Mark register and all subregs as they
1124 // are completely defined.
1125 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1126 MachineOperand &MO = MI->getOperand(i);
1128 LiveRegs.clearBitsNotInMask(MO.getRegMask());
1129 if (!MO.isReg()) continue;
1130 unsigned Reg = MO.getReg();
1131 if (Reg == 0) continue;
1132 if (!MO.isDef()) continue;
1133 // Ignore two-addr defs.
1134 if (MI->isRegTiedToUseOperand(i)) continue;
1136 // Repeat for reg and all subregs.
1137 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1138 SubRegs.isValid(); ++SubRegs)
1139 LiveRegs.reset(*SubRegs);
1142 // Examine all used registers and set/clear kill flag. When a
1143 // register is used multiple times we only set the kill flag on
1144 // the first use. Don't set kill flags on undef operands.
1146 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1147 MachineOperand &MO = MI->getOperand(i);
1148 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
1149 unsigned Reg = MO.getReg();
1150 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1153 if (!killedRegs.test(Reg)) {
1155 // A register is not killed if any subregs are live...
1156 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
1157 if (LiveRegs.test(*SubRegs)) {
1163 // If subreg is not live, then register is killed if it became
1164 // live in this instruction
1166 kill = !LiveRegs.test(Reg);
1169 if (MO.isKill() != kill) {
1170 DEBUG(dbgs() << "Fixing " << MO << " in ");
1171 // Warning: toggleKillFlag may invalidate MO.
1172 toggleKillFlag(MI, MO);
1176 killedRegs.set(Reg);
1179 // Mark any used register (that is not using undef) and subregs as
1181 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1182 MachineOperand &MO = MI->getOperand(i);
1183 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
1184 unsigned Reg = MO.getReg();
1185 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1187 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1188 SubRegs.isValid(); ++SubRegs)
1189 LiveRegs.set(*SubRegs);
1194 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
1195 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1196 SU->getInstr()->dump();
1200 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1202 raw_string_ostream oss(s);
1205 else if (SU == &ExitSU)
1208 SU->getInstr()->print(oss, &TM, /*SkipOpers=*/true);
1212 /// Return the basic block label. It is not necessarilly unique because a block
1213 /// contains multiple scheduling regions. But it is fine for visualization.
1214 std::string ScheduleDAGInstrs::getDAGName() const {
1215 return "dag." + BB->getFullName();
1218 //===----------------------------------------------------------------------===//
1219 // SchedDFSResult Implementation
1220 //===----------------------------------------------------------------------===//
1223 /// \brief Internal state used to compute SchedDFSResult.
1224 class SchedDFSImpl {
1227 /// Join DAG nodes into equivalence classes by their subtree.
1228 IntEqClasses SubtreeClasses;
1229 /// List PredSU, SuccSU pairs that represent data edges between subtrees.
1230 std::vector<std::pair<const SUnit*, const SUnit*> > ConnectionPairs;
1234 unsigned ParentNodeID; // Parent node (member of the parent subtree).
1235 unsigned SubInstrCount; // Instr count in this tree only, not children.
1237 RootData(unsigned id): NodeID(id),
1238 ParentNodeID(SchedDFSResult::InvalidSubtreeID),
1241 unsigned getSparseSetIndex() const { return NodeID; }
1244 SparseSet<RootData> RootSet;
1247 SchedDFSImpl(SchedDFSResult &r): R(r), SubtreeClasses(R.DFSNodeData.size()) {
1248 RootSet.setUniverse(R.DFSNodeData.size());
1251 /// Return true if this node been visited by the DFS traversal.
1253 /// During visitPostorderNode the Node's SubtreeID is assigned to the Node
1254 /// ID. Later, SubtreeID is updated but remains valid.
1255 bool isVisited(const SUnit *SU) const {
1256 return R.DFSNodeData[SU->NodeNum].SubtreeID
1257 != SchedDFSResult::InvalidSubtreeID;
1260 /// Initialize this node's instruction count. We don't need to flag the node
1261 /// visited until visitPostorder because the DAG cannot have cycles.
1262 void visitPreorder(const SUnit *SU) {
1263 R.DFSNodeData[SU->NodeNum].InstrCount =
1264 SU->getInstr()->isTransient() ? 0 : 1;
1267 /// Called once for each node after all predecessors are visited. Revisit this
1268 /// node's predecessors and potentially join them now that we know the ILP of
1269 /// the other predecessors.
1270 void visitPostorderNode(const SUnit *SU) {
1271 // Mark this node as the root of a subtree. It may be joined with its
1272 // successors later.
1273 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
1274 RootData RData(SU->NodeNum);
1275 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
1277 // If any predecessors are still in their own subtree, they either cannot be
1278 // joined or are large enough to remain separate. If this parent node's
1279 // total instruction count is not greater than a child subtree by at least
1280 // the subtree limit, then try to join it now since splitting subtrees is
1281 // only useful if multiple high-pressure paths are possible.
1282 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
1283 for (SUnit::const_pred_iterator
1284 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1285 if (PI->getKind() != SDep::Data)
1287 unsigned PredNum = PI->getSUnit()->NodeNum;
1288 if ((InstrCount - R.DFSNodeData[PredNum].InstrCount) < R.SubtreeLimit)
1289 joinPredSubtree(*PI, SU, /*CheckLimit=*/false);
1291 // Either link or merge the TreeData entry from the child to the parent.
1292 if (R.DFSNodeData[PredNum].SubtreeID == PredNum) {
1293 // If the predecessor's parent is invalid, this is a tree edge and the
1294 // current node is the parent.
1295 if (RootSet[PredNum].ParentNodeID == SchedDFSResult::InvalidSubtreeID)
1296 RootSet[PredNum].ParentNodeID = SU->NodeNum;
1298 else if (RootSet.count(PredNum)) {
1299 // The predecessor is not a root, but is still in the root set. This
1300 // must be the new parent that it was just joined to. Note that
1301 // RootSet[PredNum].ParentNodeID may either be invalid or may still be
1302 // set to the original parent.
1303 RData.SubInstrCount += RootSet[PredNum].SubInstrCount;
1304 RootSet.erase(PredNum);
1307 RootSet[SU->NodeNum] = RData;
1310 /// Called once for each tree edge after calling visitPostOrderNode on the
1311 /// predecessor. Increment the parent node's instruction count and
1312 /// preemptively join this subtree to its parent's if it is small enough.
1313 void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ) {
1314 R.DFSNodeData[Succ->NodeNum].InstrCount
1315 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount;
1316 joinPredSubtree(PredDep, Succ);
1319 /// Add a connection for cross edges.
1320 void visitCrossEdge(const SDep &PredDep, const SUnit *Succ) {
1321 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ));
1324 /// Set each node's subtree ID to the representative ID and record connections
1327 SubtreeClasses.compress();
1328 R.DFSTreeData.resize(SubtreeClasses.getNumClasses());
1329 assert(SubtreeClasses.getNumClasses() == RootSet.size()
1330 && "number of roots should match trees");
1331 for (SparseSet<RootData>::const_iterator
1332 RI = RootSet.begin(), RE = RootSet.end(); RI != RE; ++RI) {
1333 unsigned TreeID = SubtreeClasses[RI->NodeID];
1334 if (RI->ParentNodeID != SchedDFSResult::InvalidSubtreeID)
1335 R.DFSTreeData[TreeID].ParentTreeID = SubtreeClasses[RI->ParentNodeID];
1336 R.DFSTreeData[TreeID].SubInstrCount = RI->SubInstrCount;
1337 // Note that SubInstrCount may be greater than InstrCount if we joined
1338 // subtrees across a cross edge. InstrCount will be attributed to the
1339 // original parent, while SubInstrCount will be attributed to the joined
1342 R.SubtreeConnections.resize(SubtreeClasses.getNumClasses());
1343 R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses());
1344 DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n");
1345 for (unsigned Idx = 0, End = R.DFSNodeData.size(); Idx != End; ++Idx) {
1346 R.DFSNodeData[Idx].SubtreeID = SubtreeClasses[Idx];
1347 DEBUG(dbgs() << " SU(" << Idx << ") in tree "
1348 << R.DFSNodeData[Idx].SubtreeID << '\n');
1350 for (std::vector<std::pair<const SUnit*, const SUnit*> >::const_iterator
1351 I = ConnectionPairs.begin(), E = ConnectionPairs.end();
1353 unsigned PredTree = SubtreeClasses[I->first->NodeNum];
1354 unsigned SuccTree = SubtreeClasses[I->second->NodeNum];
1355 if (PredTree == SuccTree)
1357 unsigned Depth = I->first->getDepth();
1358 addConnection(PredTree, SuccTree, Depth);
1359 addConnection(SuccTree, PredTree, Depth);
1364 /// Join the predecessor subtree with the successor that is its DFS
1365 /// parent. Apply some heuristics before joining.
1366 bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ,
1367 bool CheckLimit = true) {
1368 assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges");
1370 // Check if the predecessor is already joined.
1371 const SUnit *PredSU = PredDep.getSUnit();
1372 unsigned PredNum = PredSU->NodeNum;
1373 if (R.DFSNodeData[PredNum].SubtreeID != PredNum)
1376 // Four is the magic number of successors before a node is considered a
1378 unsigned NumDataSucs = 0;
1379 for (SUnit::const_succ_iterator SI = PredSU->Succs.begin(),
1380 SE = PredSU->Succs.end(); SI != SE; ++SI) {
1381 if (SI->getKind() == SDep::Data) {
1382 if (++NumDataSucs >= 4)
1386 if (CheckLimit && R.DFSNodeData[PredNum].InstrCount > R.SubtreeLimit)
1388 R.DFSNodeData[PredNum].SubtreeID = Succ->NodeNum;
1389 SubtreeClasses.join(Succ->NodeNum, PredNum);
1393 /// Called by finalize() to record a connection between trees.
1394 void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth) {
1399 SmallVectorImpl<SchedDFSResult::Connection> &Connections =
1400 R.SubtreeConnections[FromTree];
1401 for (SmallVectorImpl<SchedDFSResult::Connection>::iterator
1402 I = Connections.begin(), E = Connections.end(); I != E; ++I) {
1403 if (I->TreeID == ToTree) {
1404 I->Level = std::max(I->Level, Depth);
1408 Connections.push_back(SchedDFSResult::Connection(ToTree, Depth));
1409 FromTree = R.DFSTreeData[FromTree].ParentTreeID;
1410 } while (FromTree != SchedDFSResult::InvalidSubtreeID);
1416 /// \brief Manage the stack used by a reverse depth-first search over the DAG.
1417 class SchedDAGReverseDFS {
1418 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack;
1420 bool isComplete() const { return DFSStack.empty(); }
1422 void follow(const SUnit *SU) {
1423 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
1425 void advance() { ++DFSStack.back().second; }
1427 const SDep *backtrack() {
1428 DFSStack.pop_back();
1429 return DFSStack.empty() ? 0 : llvm::prior(DFSStack.back().second);
1432 const SUnit *getCurr() const { return DFSStack.back().first; }
1434 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; }
1436 SUnit::const_pred_iterator getPredEnd() const {
1437 return getCurr()->Preds.end();
1442 static bool hasDataSucc(const SUnit *SU) {
1443 for (SUnit::const_succ_iterator
1444 SI = SU->Succs.begin(), SE = SU->Succs.end(); SI != SE; ++SI) {
1445 if (SI->getKind() == SDep::Data && !SI->getSUnit()->isBoundaryNode())
1451 /// Compute an ILP metric for all nodes in the subDAG reachable via depth-first
1452 /// search from this root.
1453 void SchedDFSResult::compute(ArrayRef<SUnit> SUnits) {
1455 llvm_unreachable("Top-down ILP metric is unimplemnted");
1457 SchedDFSImpl Impl(*this);
1458 for (ArrayRef<SUnit>::const_iterator
1459 SI = SUnits.begin(), SE = SUnits.end(); SI != SE; ++SI) {
1460 const SUnit *SU = &*SI;
1461 if (Impl.isVisited(SU) || hasDataSucc(SU))
1464 SchedDAGReverseDFS DFS;
1465 Impl.visitPreorder(SU);
1468 // Traverse the leftmost path as far as possible.
1469 while (DFS.getPred() != DFS.getPredEnd()) {
1470 const SDep &PredDep = *DFS.getPred();
1472 // Ignore non-data edges.
1473 if (PredDep.getKind() != SDep::Data
1474 || PredDep.getSUnit()->isBoundaryNode()) {
1477 // An already visited edge is a cross edge, assuming an acyclic DAG.
1478 if (Impl.isVisited(PredDep.getSUnit())) {
1479 Impl.visitCrossEdge(PredDep, DFS.getCurr());
1482 Impl.visitPreorder(PredDep.getSUnit());
1483 DFS.follow(PredDep.getSUnit());
1485 // Visit the top of the stack in postorder and backtrack.
1486 const SUnit *Child = DFS.getCurr();
1487 const SDep *PredDep = DFS.backtrack();
1488 Impl.visitPostorderNode(Child);
1490 Impl.visitPostorderEdge(*PredDep, DFS.getCurr());
1491 if (DFS.isComplete())
1498 /// The root of the given SubtreeID was just scheduled. For all subtrees
1499 /// connected to this tree, record the depth of the connection so that the
1500 /// nearest connected subtrees can be prioritized.
1501 void SchedDFSResult::scheduleTree(unsigned SubtreeID) {
1502 for (SmallVectorImpl<Connection>::const_iterator
1503 I = SubtreeConnections[SubtreeID].begin(),
1504 E = SubtreeConnections[SubtreeID].end(); I != E; ++I) {
1505 SubtreeConnectLevels[I->TreeID] =
1506 std::max(SubtreeConnectLevels[I->TreeID], I->Level);
1507 DEBUG(dbgs() << " Tree: " << I->TreeID
1508 << " @" << SubtreeConnectLevels[I->TreeID] << '\n');
1512 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1513 void ILPValue::print(raw_ostream &OS) const {
1514 OS << InstrCount << " / " << Length << " = ";
1518 OS << format("%g", ((double)InstrCount / Length));
1521 void ILPValue::dump() const {
1522 dbgs() << *this << '\n';
1527 raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) {
1533 #endif // !NDEBUG || LLVM_ENABLE_DUMP