1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAGInstrs class, which implements re-scheduling
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
16 #include "llvm/ADT/MapVector.h"
17 #include "llvm/ADT/SmallPtrSet.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/ValueTracking.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/RegisterPressure.h"
28 #include "llvm/CodeGen/ScheduleDFS.h"
29 #include "llvm/IR/Operator.h"
30 #include "llvm/MC/MCInstrItineraries.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/Format.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetRegisterInfo.h"
38 #include "llvm/Target/TargetSubtargetInfo.h"
43 #define DEBUG_TYPE "misched"
45 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
46 cl::ZeroOrMore, cl::init(false),
47 cl::desc("Enable use of AA during MI GAD construction"));
49 static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
50 cl::init(true), cl::desc("Enable use of TBAA during MI GAD construction"));
52 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
53 const MachineLoopInfo *mli,
57 : ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()), LIS(lis),
58 IsPostRA(IsPostRAFlag), RemoveKillFlags(RemoveKillFlags),
59 CanHandleTerminators(false), FirstDbgValue(nullptr) {
60 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
62 assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
63 "Virtual registers must be removed prior to PostRA scheduling");
65 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
66 SchedModel.init(ST.getSchedModel(), &ST, TII);
69 /// getUnderlyingObjectFromInt - This is the function that does the work of
70 /// looking through basic ptrtoint+arithmetic+inttoptr sequences.
71 static const Value *getUnderlyingObjectFromInt(const Value *V) {
73 if (const Operator *U = dyn_cast<Operator>(V)) {
74 // If we find a ptrtoint, we can transfer control back to the
75 // regular getUnderlyingObjectFromInt.
76 if (U->getOpcode() == Instruction::PtrToInt)
77 return U->getOperand(0);
78 // If we find an add of a constant, a multiplied value, or a phi, it's
79 // likely that the other operand will lead us to the base
80 // object. We don't have to worry about the case where the
81 // object address is somehow being computed by the multiply,
82 // because our callers only care when the result is an
83 // identifiable object.
84 if (U->getOpcode() != Instruction::Add ||
85 (!isa<ConstantInt>(U->getOperand(1)) &&
86 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul &&
87 !isa<PHINode>(U->getOperand(1))))
93 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
97 /// getUnderlyingObjects - This is a wrapper around GetUnderlyingObjects
98 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
99 static void getUnderlyingObjects(const Value *V,
100 SmallVectorImpl<Value *> &Objects) {
101 SmallPtrSet<const Value *, 16> Visited;
102 SmallVector<const Value *, 4> Working(1, V);
104 V = Working.pop_back_val();
106 SmallVector<Value *, 4> Objs;
107 GetUnderlyingObjects(const_cast<Value *>(V), Objs);
109 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), IE = Objs.end();
112 if (!Visited.insert(V).second)
114 if (Operator::getOpcode(V) == Instruction::IntToPtr) {
116 getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
117 if (O->getType()->isPointerTy()) {
118 Working.push_back(O);
122 Objects.push_back(const_cast<Value *>(V));
124 } while (!Working.empty());
127 typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType;
128 typedef SmallVector<PointerIntPair<ValueType, 1, bool>, 4>
129 UnderlyingObjectsVector;
131 /// getUnderlyingObjectsForInstr - If this machine instr has memory reference
132 /// information and it can be tracked to a normal reference to a known
133 /// object, return the Value for that object.
134 static void getUnderlyingObjectsForInstr(const MachineInstr *MI,
135 const MachineFrameInfo *MFI,
136 UnderlyingObjectsVector &Objects) {
137 if (!MI->hasOneMemOperand() ||
138 (!(*MI->memoperands_begin())->getValue() &&
139 !(*MI->memoperands_begin())->getPseudoValue()) ||
140 (*MI->memoperands_begin())->isVolatile())
143 if (const PseudoSourceValue *PSV =
144 (*MI->memoperands_begin())->getPseudoValue()) {
145 // For now, ignore PseudoSourceValues which may alias LLVM IR values
146 // because the code that uses this function has no way to cope with
148 if (!PSV->isAliased(MFI)) {
149 bool MayAlias = PSV->mayAlias(MFI);
150 Objects.push_back(UnderlyingObjectsVector::value_type(PSV, MayAlias));
155 const Value *V = (*MI->memoperands_begin())->getValue();
159 SmallVector<Value *, 4> Objs;
160 getUnderlyingObjects(V, Objs);
162 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), IE = Objs.end();
166 if (!isIdentifiedObject(V)) {
171 Objects.push_back(UnderlyingObjectsVector::value_type(V, true));
175 void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
179 void ScheduleDAGInstrs::finishBlock() {
180 // Subclasses should no longer refer to the old block.
184 /// Initialize the DAG and common scheduler state for the current scheduling
185 /// region. This does not actually create the DAG, only clears it. The
186 /// scheduling driver may call BuildSchedGraph multiple times per scheduling
188 void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
189 MachineBasicBlock::iterator begin,
190 MachineBasicBlock::iterator end,
191 unsigned regioninstrs) {
192 assert(bb == BB && "startBlock should set BB");
195 NumRegionInstrs = regioninstrs;
198 /// Close the current scheduling region. Don't clear any state in case the
199 /// driver wants to refer to the previous scheduling region.
200 void ScheduleDAGInstrs::exitRegion() {
204 /// addSchedBarrierDeps - Add dependencies from instructions in the current
205 /// list of instructions being scheduled to scheduling barrier by adding
206 /// the exit SU to the register defs and use list. This is because we want to
207 /// make sure instructions which define registers that are either used by
208 /// the terminator or are live-out are properly scheduled. This is
209 /// especially important when the definition latency of the return value(s)
210 /// are too high to be hidden by the branch or when the liveout registers
211 /// used by instructions in the fallthrough block.
212 void ScheduleDAGInstrs::addSchedBarrierDeps() {
213 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : nullptr;
214 ExitSU.setInstr(ExitMI);
215 bool AllDepKnown = ExitMI &&
216 (ExitMI->isCall() || ExitMI->isBarrier());
217 if (ExitMI && AllDepKnown) {
218 // If it's a call or a barrier, add dependencies on the defs and uses of
220 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
221 const MachineOperand &MO = ExitMI->getOperand(i);
222 if (!MO.isReg() || MO.isDef()) continue;
223 unsigned Reg = MO.getReg();
224 if (Reg == 0) continue;
226 if (TRI->isPhysicalRegister(Reg))
227 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
229 assert(!IsPostRA && "Virtual register encountered after regalloc.");
230 if (MO.readsReg()) // ignore undef operands
231 addVRegUseDeps(&ExitSU, i);
235 // For others, e.g. fallthrough, conditional branch, assume the exit
236 // uses all the registers that are livein to the successor blocks.
237 assert(Uses.empty() && "Uses in set before adding deps?");
238 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
239 SE = BB->succ_end(); SI != SE; ++SI)
240 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
241 E = (*SI)->livein_end(); I != E; ++I) {
243 if (!Uses.contains(Reg))
244 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
249 /// MO is an operand of SU's instruction that defines a physical register. Add
250 /// data dependencies from SU to any uses of the physical register.
251 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
252 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
253 assert(MO.isDef() && "expect physreg def");
255 // Ask the target if address-backscheduling is desirable, and if so how much.
256 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
258 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
259 Alias.isValid(); ++Alias) {
260 if (!Uses.contains(*Alias))
262 for (Reg2SUnitsMap::iterator I = Uses.find(*Alias); I != Uses.end(); ++I) {
263 SUnit *UseSU = I->SU;
267 // Adjust the dependence latency using operand def/use information,
268 // then allow the target to perform its own adjustments.
269 int UseOp = I->OpIdx;
270 MachineInstr *RegUse = nullptr;
273 Dep = SDep(SU, SDep::Artificial);
275 // Set the hasPhysRegDefs only for physreg defs that have a use within
276 // the scheduling region.
277 SU->hasPhysRegDefs = true;
278 Dep = SDep(SU, SDep::Data, *Alias);
279 RegUse = UseSU->getInstr();
282 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,
285 ST.adjustSchedDependency(SU, UseSU, Dep);
291 /// addPhysRegDeps - Add register dependencies (data, anti, and output) from
292 /// this SUnit to following instructions in the same scheduling region that
293 /// depend the physical register referenced at OperIdx.
294 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
295 MachineInstr *MI = SU->getInstr();
296 MachineOperand &MO = MI->getOperand(OperIdx);
298 // Optionally add output and anti dependencies. For anti
299 // dependencies we use a latency of 0 because for a multi-issue
300 // target we want to allow the defining instruction to issue
301 // in the same cycle as the using instruction.
302 // TODO: Using a latency of 1 here for output dependencies assumes
303 // there's no cost for reusing registers.
304 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
305 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
306 Alias.isValid(); ++Alias) {
307 if (!Defs.contains(*Alias))
309 for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) {
310 SUnit *DefSU = I->SU;
311 if (DefSU == &ExitSU)
313 auto IsDefDead = [this](SUnit *DefSU, unsigned Reg) {
314 for (MCSubRegIterator SR(Reg, TRI, true); SR.isValid(); ++SR)
315 if (!DefSU->getInstr()->registerDefIsDead(*SR))
320 (Kind != SDep::Output || !MO.isDead() ||
321 !IsDefDead(DefSU, *Alias))) {
322 if (Kind == SDep::Anti)
323 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
325 SDep Dep(SU, Kind, /*Reg=*/*Alias);
327 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
335 SU->hasPhysRegUses = true;
336 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
337 // retrieve the existing SUnits list for this register's uses.
338 // Push this SUnit on the use list.
339 Uses.insert(PhysRegSUOper(SU, OperIdx, MO.getReg()));
344 addPhysRegDataDeps(SU, OperIdx);
345 unsigned Reg = MO.getReg();
347 // clear this register's use list
348 if (Uses.contains(Reg))
353 } else if (SU->isCall) {
354 // Calls will not be reordered because of chain dependencies (see
355 // below). Since call operands are dead, calls may continue to be added
356 // to the DefList making dependence checking quadratic in the size of
357 // the block. Instead, we leave only one call at the back of the
359 Reg2SUnitsMap::RangePair P = Defs.equal_range(Reg);
360 Reg2SUnitsMap::iterator B = P.first;
361 Reg2SUnitsMap::iterator I = P.second;
362 for (bool isBegin = I == B; !isBegin; /* empty */) {
363 isBegin = (--I) == B;
370 // Defs are pushed in the order they are visited and never reordered.
371 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));
375 /// addVRegDefDeps - Add register output and data dependencies from this SUnit
376 /// to instructions that occur later in the same scheduling region if they read
377 /// from or write to the virtual register defined at OperIdx.
379 /// TODO: Hoist loop induction variable increments. This has to be
380 /// reevaluated. Generally, IV scheduling should be done before coalescing.
381 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
382 const MachineInstr *MI = SU->getInstr();
383 unsigned Reg = MI->getOperand(OperIdx).getReg();
385 // Singly defined vregs do not have output/anti dependencies.
386 // The current operand is a def, so we have at least one.
387 // Check here if there are any others...
388 if (MRI.hasOneDef(Reg))
391 // Add output dependence to the next nearest def of this vreg.
393 // Unless this definition is dead, the output dependence should be
394 // transitively redundant with antidependencies from this definition's
395 // uses. We're conservative for now until we have a way to guarantee the uses
396 // are not eliminated sometime during scheduling. The output dependence edge
397 // is also useful if output latency exceeds def-use latency.
398 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
399 if (DefI == VRegDefs.end())
400 VRegDefs.insert(VReg2SUnit(Reg, SU));
402 SUnit *DefSU = DefI->SU;
403 if (DefSU != SU && DefSU != &ExitSU) {
404 SDep Dep(SU, SDep::Output, Reg);
406 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
413 /// addVRegUseDeps - Add a register data dependency if the instruction that
414 /// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
415 /// register antidependency from this SUnit to instructions that occur later in
416 /// the same scheduling region if they write the virtual register.
418 /// TODO: Handle ExitSU "uses" properly.
419 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
420 MachineInstr *MI = SU->getInstr();
421 unsigned Reg = MI->getOperand(OperIdx).getReg();
423 // Record this local VReg use.
424 VReg2UseMap::iterator UI = VRegUses.find(Reg);
425 for (; UI != VRegUses.end(); ++UI) {
429 if (UI == VRegUses.end())
430 VRegUses.insert(VReg2SUnit(Reg, SU));
432 // Lookup this operand's reaching definition.
433 assert(LIS && "vreg dependencies requires LiveIntervals");
435 = LIS->getInterval(Reg).Query(LIS->getInstructionIndex(MI));
436 VNInfo *VNI = LRQ.valueIn();
438 // VNI will be valid because MachineOperand::readsReg() is checked by caller.
439 assert(VNI && "No value to read by operand");
440 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
441 // Phis and other noninstructions (after coalescing) have a NULL Def.
443 SUnit *DefSU = getSUnit(Def);
445 // The reaching Def lives within this scheduling region.
446 // Create a data dependence.
447 SDep dep(DefSU, SDep::Data, Reg);
448 // Adjust the dependence latency using operand def/use information, then
449 // allow the target to perform its own adjustments.
450 int DefOp = Def->findRegisterDefOperandIdx(Reg);
451 dep.setLatency(SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx));
453 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
454 ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
459 // Add antidependence to the following def of the vreg it uses.
460 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
461 if (DefI != VRegDefs.end() && DefI->SU != SU)
462 DefI->SU->addPred(SDep(SU, SDep::Anti, Reg));
465 /// Return true if MI is an instruction we are unable to reason about
466 /// (like a call or something with unmodeled side effects).
467 static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
468 if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
469 (MI->hasOrderedMemoryRef() &&
470 (!MI->mayLoad() || !MI->isInvariantLoad(AA))))
475 // This MI might have either incomplete info, or known to be unsafe
476 // to deal with (i.e. volatile object).
477 static inline bool isUnsafeMemoryObject(MachineInstr *MI,
478 const MachineFrameInfo *MFI) {
479 if (!MI || MI->memoperands_empty())
481 // We purposefully do no check for hasOneMemOperand() here
482 // in hope to trigger an assert downstream in order to
483 // finish implementation.
484 if ((*MI->memoperands_begin())->isVolatile() ||
485 MI->hasUnmodeledSideEffects())
488 if ((*MI->memoperands_begin())->getPseudoValue()) {
489 // Similarly to getUnderlyingObjectForInstr:
490 // For now, ignore PseudoSourceValues which may alias LLVM IR values
491 // because the code that uses this function has no way to cope with
496 const Value *V = (*MI->memoperands_begin())->getValue();
500 SmallVector<Value *, 4> Objs;
501 getUnderlyingObjects(V, Objs);
502 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(),
503 IE = Objs.end(); I != IE; ++I) {
504 // Does this pointer refer to a distinct and identifiable object?
505 if (!isIdentifiedObject(*I))
512 /// This returns true if the two MIs need a chain edge betwee them.
513 /// If these are not even memory operations, we still may need
514 /// chain deps between them. The question really is - could
515 /// these two MIs be reordered during scheduling from memory dependency
517 static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI,
520 const MachineFunction *MF = MIa->getParent()->getParent();
521 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
523 // Cover a trivial case - no edge is need to itself.
527 // Let the target decide if memory accesses cannot possibly overlap.
528 if ((MIa->mayLoad() || MIa->mayStore()) &&
529 (MIb->mayLoad() || MIb->mayStore()))
530 if (TII->areMemAccessesTriviallyDisjoint(MIa, MIb, AA))
533 // FIXME: Need to handle multiple memory operands to support all targets.
534 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())
537 if (isUnsafeMemoryObject(MIa, MFI) || isUnsafeMemoryObject(MIb, MFI))
540 // If we are dealing with two "normal" loads, we do not need an edge
541 // between them - they could be reordered.
542 if (!MIa->mayStore() && !MIb->mayStore())
545 // To this point analysis is generic. From here on we do need AA.
549 MachineMemOperand *MMOa = *MIa->memoperands_begin();
550 MachineMemOperand *MMOb = *MIb->memoperands_begin();
552 if (!MMOa->getValue() || !MMOb->getValue())
555 // The following interface to AA is fashioned after DAGCombiner::isAlias
556 // and operates with MachineMemOperand offset with some important
558 // - LLVM fundamentally assumes flat address spaces.
559 // - MachineOperand offset can *only* result from legalization and
560 // cannot affect queries other than the trivial case of overlap
562 // - These offsets never wrap and never step outside
563 // of allocated objects.
564 // - There should never be any negative offsets here.
566 // FIXME: Modify API to hide this math from "user"
567 // FIXME: Even before we go to AA we can reason locally about some
568 // memory objects. It can save compile time, and possibly catch some
569 // corner cases not currently covered.
571 assert ((MMOa->getOffset() >= 0) && "Negative MachineMemOperand offset");
572 assert ((MMOb->getOffset() >= 0) && "Negative MachineMemOperand offset");
574 int64_t MinOffset = std::min(MMOa->getOffset(), MMOb->getOffset());
575 int64_t Overlapa = MMOa->getSize() + MMOa->getOffset() - MinOffset;
576 int64_t Overlapb = MMOb->getSize() + MMOb->getOffset() - MinOffset;
578 AliasAnalysis::AliasResult AAResult = AA->alias(
579 AliasAnalysis::Location(MMOa->getValue(), Overlapa,
580 UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
581 AliasAnalysis::Location(MMOb->getValue(), Overlapb,
582 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
584 return (AAResult != AliasAnalysis::NoAlias);
587 /// This recursive function iterates over chain deps of SUb looking for
588 /// "latest" node that needs a chain edge to SUa.
590 iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI,
591 SUnit *SUa, SUnit *SUb, SUnit *ExitSU, unsigned *Depth,
592 SmallPtrSetImpl<const SUnit*> &Visited) {
593 if (!SUa || !SUb || SUb == ExitSU)
596 // Remember visited nodes.
597 if (!Visited.insert(SUb).second)
599 // If there is _some_ dependency already in place, do not
600 // descend any further.
601 // TODO: Need to make sure that if that dependency got eliminated or ignored
602 // for any reason in the future, we would not violate DAG topology.
603 // Currently it does not happen, but makes an implicit assumption about
604 // future implementation.
606 // Independently, if we encounter node that is some sort of global
607 // object (like a call) we already have full set of dependencies to it
608 // and we can stop descending.
609 if (SUa->isSucc(SUb) ||
610 isGlobalMemoryObject(AA, SUb->getInstr()))
613 // If we do need an edge, or we have exceeded depth budget,
614 // add that edge to the predecessors chain of SUb,
615 // and stop descending.
617 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
618 SUb->addPred(SDep(SUa, SDep::MayAliasMem));
621 // Track current depth.
623 // Iterate over chain dependencies only.
624 for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end();
627 iterateChainSucc (AA, MFI, SUa, I->getSUnit(), ExitSU, Depth, Visited);
631 /// This function assumes that "downward" from SU there exist
632 /// tail/leaf of already constructed DAG. It iterates downward and
633 /// checks whether SU can be aliasing any node dominated
635 static void adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI,
636 SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList,
637 unsigned LatencyToLoad) {
641 SmallPtrSet<const SUnit*, 16> Visited;
644 for (std::set<SUnit *>::iterator I = CheckList.begin(), IE = CheckList.end();
648 if (MIsNeedChainEdge(AA, MFI, SU->getInstr(), (*I)->getInstr())) {
649 SDep Dep(SU, SDep::MayAliasMem);
650 Dep.setLatency(((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0);
653 // Now go through all the chain successors and iterate from them.
654 // Keep track of visited nodes.
655 for (SUnit::const_succ_iterator J = (*I)->Succs.begin(),
656 JE = (*I)->Succs.end(); J != JE; ++J)
658 iterateChainSucc (AA, MFI, SU, J->getSUnit(),
659 ExitSU, &Depth, Visited);
663 /// Check whether two objects need a chain edge, if so, add it
664 /// otherwise remember the rejected SU.
666 void addChainDependency (AliasAnalysis *AA, const MachineFrameInfo *MFI,
667 SUnit *SUa, SUnit *SUb,
668 std::set<SUnit *> &RejectList,
669 unsigned TrueMemOrderLatency = 0,
670 bool isNormalMemory = false) {
671 // If this is a false dependency,
672 // do not add the edge, but rememeber the rejected node.
673 if (MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
674 SDep Dep(SUa, isNormalMemory ? SDep::MayAliasMem : SDep::Barrier);
675 Dep.setLatency(TrueMemOrderLatency);
679 // Duplicate entries should be ignored.
680 RejectList.insert(SUb);
681 DEBUG(dbgs() << "\tReject chain dep between SU("
682 << SUa->NodeNum << ") and SU("
683 << SUb->NodeNum << ")\n");
687 /// Create an SUnit for each real instruction, numbered in top-down toplological
688 /// order. The instruction order A < B, implies that no edge exists from B to A.
690 /// Map each real instruction to its SUnit.
692 /// After initSUnits, the SUnits vector cannot be resized and the scheduler may
693 /// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
694 /// instead of pointers.
696 /// MachineScheduler relies on initSUnits numbering the nodes by their order in
697 /// the original instruction list.
698 void ScheduleDAGInstrs::initSUnits() {
699 // We'll be allocating one SUnit for each real instruction in the region,
700 // which is contained within a basic block.
701 SUnits.reserve(NumRegionInstrs);
703 for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) {
704 MachineInstr *MI = I;
705 if (MI->isDebugValue())
708 SUnit *SU = newSUnit(MI);
711 SU->isCall = MI->isCall();
712 SU->isCommutable = MI->isCommutable();
714 // Assign the Latency field of SU using target-provided information.
715 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
717 // If this SUnit uses a reserved or unbuffered resource, mark it as such.
719 // Reserved resources block an instruction from issuing and stall the
720 // entire pipeline. These are identified by BufferSize=0.
722 // Unbuffered resources prevent execution of subsequent instructions that
723 // require the same resources. This is used for in-order execution pipelines
724 // within an out-of-order core. These are identified by BufferSize=1.
725 if (SchedModel.hasInstrSchedModel()) {
726 const MCSchedClassDesc *SC = getSchedClass(SU);
727 for (TargetSchedModel::ProcResIter
728 PI = SchedModel.getWriteProcResBegin(SC),
729 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
730 switch (SchedModel.getProcResource(PI->ProcResourceIdx)->BufferSize) {
732 SU->hasReservedResource = true;
735 SU->isUnbuffered = true;
745 /// If RegPressure is non-null, compute register pressure as a side effect. The
746 /// DAG builder is an efficient place to do it because it already visits
748 void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
749 RegPressureTracker *RPTracker,
750 PressureDiffs *PDiffs) {
751 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
752 bool UseAA = EnableAASchedMI.getNumOccurrences() > 0 ? EnableAASchedMI
754 AliasAnalysis *AAForDep = UseAA ? AA : nullptr;
757 ScheduleDAG::clearDAG();
759 // Create an SUnit for each real instruction.
763 PDiffs->init(SUnits.size());
765 // We build scheduling units by walking a block's instruction list from bottom
768 // Remember where a generic side-effecting instruction is as we procede.
769 SUnit *BarrierChain = nullptr, *AliasChain = nullptr;
771 // Memory references to specific known memory locations are tracked
772 // so that they can be given more precise dependencies. We track
773 // separately the known memory locations that may alias and those
774 // that are known not to alias
775 MapVector<ValueType, std::vector<SUnit *> > AliasMemDefs, NonAliasMemDefs;
776 MapVector<ValueType, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
777 std::set<SUnit*> RejectMemNodes;
779 // Remove any stale debug info; sometimes BuildSchedGraph is called again
780 // without emitting the info from the previous call.
782 FirstDbgValue = nullptr;
784 assert(Defs.empty() && Uses.empty() &&
785 "Only BuildGraph should update Defs/Uses");
786 Defs.setUniverse(TRI->getNumRegs());
787 Uses.setUniverse(TRI->getNumRegs());
789 assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs");
791 VRegDefs.setUniverse(MRI.getNumVirtRegs());
792 VRegUses.setUniverse(MRI.getNumVirtRegs());
794 // Model data dependencies between instructions being scheduled and the
796 addSchedBarrierDeps();
798 // Walk the list of instructions, from bottom moving up.
799 MachineInstr *DbgMI = nullptr;
800 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
802 MachineInstr *MI = std::prev(MII);
804 DbgValues.push_back(std::make_pair(DbgMI, MI));
808 if (MI->isDebugValue()) {
812 SUnit *SU = MISUnitMap[MI];
813 assert(SU && "No SUnit mapped to this MI");
816 PressureDiff *PDiff = PDiffs ? &(*PDiffs)[SU->NodeNum] : nullptr;
817 RPTracker->recede(/*LiveUses=*/nullptr, PDiff);
818 assert(RPTracker->getPos() == std::prev(MII) &&
819 "RPTracker can't find MI");
823 (CanHandleTerminators || (!MI->isTerminator() && !MI->isPosition())) &&
824 "Cannot schedule terminators or labels!");
826 // Add register-based dependencies (data, anti, and output).
827 bool HasVRegDef = false;
828 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
829 const MachineOperand &MO = MI->getOperand(j);
830 if (!MO.isReg()) continue;
831 unsigned Reg = MO.getReg();
832 if (Reg == 0) continue;
834 if (TRI->isPhysicalRegister(Reg))
835 addPhysRegDeps(SU, j);
837 assert(!IsPostRA && "Virtual register encountered!");
840 addVRegDefDeps(SU, j);
842 else if (MO.readsReg()) // ignore undef operands
843 addVRegUseDeps(SU, j);
846 // If we haven't seen any uses in this scheduling region, create a
847 // dependence edge to ExitSU to model the live-out latency. This is required
848 // for vreg defs with no in-region use, and prefetches with no vreg def.
850 // FIXME: NumDataSuccs would be more precise than NumSuccs here. This
851 // check currently relies on being called before adding chain deps.
852 if (SU->NumSuccs == 0 && SU->Latency > 1
853 && (HasVRegDef || MI->mayLoad())) {
854 SDep Dep(SU, SDep::Artificial);
855 Dep.setLatency(SU->Latency - 1);
859 // Add chain dependencies.
860 // Chain dependencies used to enforce memory order should have
861 // latency of 0 (except for true dependency of Store followed by
862 // aliased Load... we estimate that with a single cycle of latency
863 // assuming the hardware will bypass)
864 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
865 // after stack slots are lowered to actual addresses.
866 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and
867 // produce more precise dependence information.
868 unsigned TrueMemOrderLatency = MI->mayStore() ? 1 : 0;
869 if (isGlobalMemoryObject(AA, MI)) {
870 // Be conservative with these and add dependencies on all memory
871 // references, even those that are known to not alias.
872 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
873 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
874 for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
875 I->second[i]->addPred(SDep(SU, SDep::Barrier));
878 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
879 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
880 for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
881 SDep Dep(SU, SDep::Barrier);
882 Dep.setLatency(TrueMemOrderLatency);
883 I->second[i]->addPred(Dep);
886 // Add SU to the barrier chain.
888 BarrierChain->addPred(SDep(SU, SDep::Barrier));
890 // This is a barrier event that acts as a pivotal node in the DAG,
891 // so it is safe to clear list of exposed nodes.
892 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
893 TrueMemOrderLatency);
894 RejectMemNodes.clear();
895 NonAliasMemDefs.clear();
896 NonAliasMemUses.clear();
900 // Chain all possibly aliasing memory references though SU.
902 unsigned ChainLatency = 0;
903 if (AliasChain->getInstr()->mayLoad())
904 ChainLatency = TrueMemOrderLatency;
905 addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes,
909 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
910 addChainDependency(AAForDep, MFI, SU, PendingLoads[k], RejectMemNodes,
911 TrueMemOrderLatency);
912 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
913 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I) {
914 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
915 addChainDependency(AAForDep, MFI, SU, I->second[i], RejectMemNodes);
917 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
918 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
919 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
920 addChainDependency(AAForDep, MFI, SU, I->second[i], RejectMemNodes,
921 TrueMemOrderLatency);
923 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
924 TrueMemOrderLatency);
925 PendingLoads.clear();
926 AliasMemDefs.clear();
927 AliasMemUses.clear();
928 } else if (MI->mayStore()) {
929 UnderlyingObjectsVector Objs;
930 getUnderlyingObjectsForInstr(MI, MFI, Objs);
933 // Treat all other stores conservatively.
934 goto new_alias_chain;
937 bool MayAlias = false;
938 for (UnderlyingObjectsVector::iterator K = Objs.begin(), KE = Objs.end();
940 ValueType V = K->getPointer();
941 bool ThisMayAlias = K->getInt();
945 // A store to a specific PseudoSourceValue. Add precise dependencies.
946 // Record the def in MemDefs, first adding a dep if there is
948 MapVector<ValueType, std::vector<SUnit *> >::iterator I =
949 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
950 MapVector<ValueType, std::vector<SUnit *> >::iterator IE =
951 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
953 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
954 addChainDependency(AAForDep, MFI, SU, I->second[i], RejectMemNodes,
957 // If we're not using AA, then we only need one store per object.
960 I->second.push_back(SU);
964 AliasMemDefs[V].clear();
965 AliasMemDefs[V].push_back(SU);
968 NonAliasMemDefs[V].clear();
969 NonAliasMemDefs[V].push_back(SU);
972 // Handle the uses in MemUses, if there are any.
973 MapVector<ValueType, std::vector<SUnit *> >::iterator J =
974 ((ThisMayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
975 MapVector<ValueType, std::vector<SUnit *> >::iterator JE =
976 ((ThisMayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
978 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
979 addChainDependency(AAForDep, MFI, SU, J->second[i], RejectMemNodes,
980 TrueMemOrderLatency, true);
985 // Add dependencies from all the PendingLoads, i.e. loads
986 // with no underlying object.
987 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
988 addChainDependency(AAForDep, MFI, SU, PendingLoads[k], RejectMemNodes,
989 TrueMemOrderLatency);
990 // Add dependence on alias chain, if needed.
992 addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes);
993 // But we also should check dependent instructions for the
995 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
996 TrueMemOrderLatency);
998 // Add dependence on barrier chain, if needed.
999 // There is no point to check aliasing on barrier event. Even if
1000 // SU and barrier _could_ be reordered, they should not. In addition,
1001 // we have lost all RejectMemNodes below barrier.
1003 BarrierChain->addPred(SDep(SU, SDep::Barrier));
1004 } else if (MI->mayLoad()) {
1005 bool MayAlias = true;
1006 if (MI->isInvariantLoad(AA)) {
1007 // Invariant load, no chain dependencies needed!
1009 UnderlyingObjectsVector Objs;
1010 getUnderlyingObjectsForInstr(MI, MFI, Objs);
1013 // A load with no underlying object. Depend on all
1014 // potentially aliasing stores.
1015 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
1016 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
1017 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1018 addChainDependency(AAForDep, MFI, SU, I->second[i],
1021 PendingLoads.push_back(SU);
1027 for (UnderlyingObjectsVector::iterator
1028 J = Objs.begin(), JE = Objs.end(); J != JE; ++J) {
1029 ValueType V = J->getPointer();
1030 bool ThisMayAlias = J->getInt();
1035 // A load from a specific PseudoSourceValue. Add precise dependencies.
1036 MapVector<ValueType, std::vector<SUnit *> >::iterator I =
1037 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
1038 MapVector<ValueType, std::vector<SUnit *> >::iterator IE =
1039 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
1041 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1042 addChainDependency(AAForDep, MFI, SU, I->second[i],
1043 RejectMemNodes, 0, true);
1045 AliasMemUses[V].push_back(SU);
1047 NonAliasMemUses[V].push_back(SU);
1050 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, /*Latency=*/0);
1051 // Add dependencies on alias and barrier chains, if needed.
1052 if (MayAlias && AliasChain)
1053 addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes);
1055 BarrierChain->addPred(SDep(SU, SDep::Barrier));
1060 FirstDbgValue = DbgMI;
1065 PendingLoads.clear();
1068 /// \brief Initialize register live-range state for updating kills.
1069 void ScheduleDAGInstrs::startBlockForKills(MachineBasicBlock *BB) {
1070 // Start with no live registers.
1073 // Examine the live-in regs of all successors.
1074 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
1075 SE = BB->succ_end(); SI != SE; ++SI) {
1076 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
1077 E = (*SI)->livein_end(); I != E; ++I) {
1079 // Repeat, for reg and all subregs.
1080 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1081 SubRegs.isValid(); ++SubRegs)
1082 LiveRegs.set(*SubRegs);
1087 bool ScheduleDAGInstrs::toggleKillFlag(MachineInstr *MI, MachineOperand &MO) {
1088 // Setting kill flag...
1094 // If MO itself is live, clear the kill flag...
1095 if (LiveRegs.test(MO.getReg())) {
1096 MO.setIsKill(false);
1100 // If any subreg of MO is live, then create an imp-def for that
1101 // subreg and keep MO marked as killed.
1102 MO.setIsKill(false);
1103 bool AllDead = true;
1104 const unsigned SuperReg = MO.getReg();
1105 MachineInstrBuilder MIB(MF, MI);
1106 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
1107 if (LiveRegs.test(*SubRegs)) {
1108 MIB.addReg(*SubRegs, RegState::ImplicitDefine);
1118 // FIXME: Reuse the LivePhysRegs utility for this.
1119 void ScheduleDAGInstrs::fixupKills(MachineBasicBlock *MBB) {
1120 DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
1122 LiveRegs.resize(TRI->getNumRegs());
1123 BitVector killedRegs(TRI->getNumRegs());
1125 startBlockForKills(MBB);
1127 // Examine block from end to start...
1128 unsigned Count = MBB->size();
1129 for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
1131 MachineInstr *MI = --I;
1132 if (MI->isDebugValue())
1135 // Update liveness. Registers that are defed but not used in this
1136 // instruction are now dead. Mark register and all subregs as they
1137 // are completely defined.
1138 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1139 MachineOperand &MO = MI->getOperand(i);
1141 LiveRegs.clearBitsNotInMask(MO.getRegMask());
1142 if (!MO.isReg()) continue;
1143 unsigned Reg = MO.getReg();
1144 if (Reg == 0) continue;
1145 if (!MO.isDef()) continue;
1146 // Ignore two-addr defs.
1147 if (MI->isRegTiedToUseOperand(i)) continue;
1149 // Repeat for reg and all subregs.
1150 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1151 SubRegs.isValid(); ++SubRegs)
1152 LiveRegs.reset(*SubRegs);
1155 // Examine all used registers and set/clear kill flag. When a
1156 // register is used multiple times we only set the kill flag on
1157 // the first use. Don't set kill flags on undef operands.
1159 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1160 MachineOperand &MO = MI->getOperand(i);
1161 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
1162 unsigned Reg = MO.getReg();
1163 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1166 if (!killedRegs.test(Reg)) {
1168 // A register is not killed if any subregs are live...
1169 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
1170 if (LiveRegs.test(*SubRegs)) {
1176 // If subreg is not live, then register is killed if it became
1177 // live in this instruction
1179 kill = !LiveRegs.test(Reg);
1182 if (MO.isKill() != kill) {
1183 DEBUG(dbgs() << "Fixing " << MO << " in ");
1184 // Warning: toggleKillFlag may invalidate MO.
1185 toggleKillFlag(MI, MO);
1189 killedRegs.set(Reg);
1192 // Mark any used register (that is not using undef) and subregs as
1194 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1195 MachineOperand &MO = MI->getOperand(i);
1196 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
1197 unsigned Reg = MO.getReg();
1198 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1200 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1201 SubRegs.isValid(); ++SubRegs)
1202 LiveRegs.set(*SubRegs);
1207 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
1208 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1209 SU->getInstr()->dump();
1213 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1215 raw_string_ostream oss(s);
1218 else if (SU == &ExitSU)
1221 SU->getInstr()->print(oss, &TM, /*SkipOpers=*/true);
1225 /// Return the basic block label. It is not necessarilly unique because a block
1226 /// contains multiple scheduling regions. But it is fine for visualization.
1227 std::string ScheduleDAGInstrs::getDAGName() const {
1228 return "dag." + BB->getFullName();
1231 //===----------------------------------------------------------------------===//
1232 // SchedDFSResult Implementation
1233 //===----------------------------------------------------------------------===//
1236 /// \brief Internal state used to compute SchedDFSResult.
1237 class SchedDFSImpl {
1240 /// Join DAG nodes into equivalence classes by their subtree.
1241 IntEqClasses SubtreeClasses;
1242 /// List PredSU, SuccSU pairs that represent data edges between subtrees.
1243 std::vector<std::pair<const SUnit*, const SUnit*> > ConnectionPairs;
1247 unsigned ParentNodeID; // Parent node (member of the parent subtree).
1248 unsigned SubInstrCount; // Instr count in this tree only, not children.
1250 RootData(unsigned id): NodeID(id),
1251 ParentNodeID(SchedDFSResult::InvalidSubtreeID),
1254 unsigned getSparseSetIndex() const { return NodeID; }
1257 SparseSet<RootData> RootSet;
1260 SchedDFSImpl(SchedDFSResult &r): R(r), SubtreeClasses(R.DFSNodeData.size()) {
1261 RootSet.setUniverse(R.DFSNodeData.size());
1264 /// Return true if this node been visited by the DFS traversal.
1266 /// During visitPostorderNode the Node's SubtreeID is assigned to the Node
1267 /// ID. Later, SubtreeID is updated but remains valid.
1268 bool isVisited(const SUnit *SU) const {
1269 return R.DFSNodeData[SU->NodeNum].SubtreeID
1270 != SchedDFSResult::InvalidSubtreeID;
1273 /// Initialize this node's instruction count. We don't need to flag the node
1274 /// visited until visitPostorder because the DAG cannot have cycles.
1275 void visitPreorder(const SUnit *SU) {
1276 R.DFSNodeData[SU->NodeNum].InstrCount =
1277 SU->getInstr()->isTransient() ? 0 : 1;
1280 /// Called once for each node after all predecessors are visited. Revisit this
1281 /// node's predecessors and potentially join them now that we know the ILP of
1282 /// the other predecessors.
1283 void visitPostorderNode(const SUnit *SU) {
1284 // Mark this node as the root of a subtree. It may be joined with its
1285 // successors later.
1286 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
1287 RootData RData(SU->NodeNum);
1288 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
1290 // If any predecessors are still in their own subtree, they either cannot be
1291 // joined or are large enough to remain separate. If this parent node's
1292 // total instruction count is not greater than a child subtree by at least
1293 // the subtree limit, then try to join it now since splitting subtrees is
1294 // only useful if multiple high-pressure paths are possible.
1295 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
1296 for (SUnit::const_pred_iterator
1297 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1298 if (PI->getKind() != SDep::Data)
1300 unsigned PredNum = PI->getSUnit()->NodeNum;
1301 if ((InstrCount - R.DFSNodeData[PredNum].InstrCount) < R.SubtreeLimit)
1302 joinPredSubtree(*PI, SU, /*CheckLimit=*/false);
1304 // Either link or merge the TreeData entry from the child to the parent.
1305 if (R.DFSNodeData[PredNum].SubtreeID == PredNum) {
1306 // If the predecessor's parent is invalid, this is a tree edge and the
1307 // current node is the parent.
1308 if (RootSet[PredNum].ParentNodeID == SchedDFSResult::InvalidSubtreeID)
1309 RootSet[PredNum].ParentNodeID = SU->NodeNum;
1311 else if (RootSet.count(PredNum)) {
1312 // The predecessor is not a root, but is still in the root set. This
1313 // must be the new parent that it was just joined to. Note that
1314 // RootSet[PredNum].ParentNodeID may either be invalid or may still be
1315 // set to the original parent.
1316 RData.SubInstrCount += RootSet[PredNum].SubInstrCount;
1317 RootSet.erase(PredNum);
1320 RootSet[SU->NodeNum] = RData;
1323 /// Called once for each tree edge after calling visitPostOrderNode on the
1324 /// predecessor. Increment the parent node's instruction count and
1325 /// preemptively join this subtree to its parent's if it is small enough.
1326 void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ) {
1327 R.DFSNodeData[Succ->NodeNum].InstrCount
1328 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount;
1329 joinPredSubtree(PredDep, Succ);
1332 /// Add a connection for cross edges.
1333 void visitCrossEdge(const SDep &PredDep, const SUnit *Succ) {
1334 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ));
1337 /// Set each node's subtree ID to the representative ID and record connections
1340 SubtreeClasses.compress();
1341 R.DFSTreeData.resize(SubtreeClasses.getNumClasses());
1342 assert(SubtreeClasses.getNumClasses() == RootSet.size()
1343 && "number of roots should match trees");
1344 for (SparseSet<RootData>::const_iterator
1345 RI = RootSet.begin(), RE = RootSet.end(); RI != RE; ++RI) {
1346 unsigned TreeID = SubtreeClasses[RI->NodeID];
1347 if (RI->ParentNodeID != SchedDFSResult::InvalidSubtreeID)
1348 R.DFSTreeData[TreeID].ParentTreeID = SubtreeClasses[RI->ParentNodeID];
1349 R.DFSTreeData[TreeID].SubInstrCount = RI->SubInstrCount;
1350 // Note that SubInstrCount may be greater than InstrCount if we joined
1351 // subtrees across a cross edge. InstrCount will be attributed to the
1352 // original parent, while SubInstrCount will be attributed to the joined
1355 R.SubtreeConnections.resize(SubtreeClasses.getNumClasses());
1356 R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses());
1357 DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n");
1358 for (unsigned Idx = 0, End = R.DFSNodeData.size(); Idx != End; ++Idx) {
1359 R.DFSNodeData[Idx].SubtreeID = SubtreeClasses[Idx];
1360 DEBUG(dbgs() << " SU(" << Idx << ") in tree "
1361 << R.DFSNodeData[Idx].SubtreeID << '\n');
1363 for (std::vector<std::pair<const SUnit*, const SUnit*> >::const_iterator
1364 I = ConnectionPairs.begin(), E = ConnectionPairs.end();
1366 unsigned PredTree = SubtreeClasses[I->first->NodeNum];
1367 unsigned SuccTree = SubtreeClasses[I->second->NodeNum];
1368 if (PredTree == SuccTree)
1370 unsigned Depth = I->first->getDepth();
1371 addConnection(PredTree, SuccTree, Depth);
1372 addConnection(SuccTree, PredTree, Depth);
1377 /// Join the predecessor subtree with the successor that is its DFS
1378 /// parent. Apply some heuristics before joining.
1379 bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ,
1380 bool CheckLimit = true) {
1381 assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges");
1383 // Check if the predecessor is already joined.
1384 const SUnit *PredSU = PredDep.getSUnit();
1385 unsigned PredNum = PredSU->NodeNum;
1386 if (R.DFSNodeData[PredNum].SubtreeID != PredNum)
1389 // Four is the magic number of successors before a node is considered a
1391 unsigned NumDataSucs = 0;
1392 for (SUnit::const_succ_iterator SI = PredSU->Succs.begin(),
1393 SE = PredSU->Succs.end(); SI != SE; ++SI) {
1394 if (SI->getKind() == SDep::Data) {
1395 if (++NumDataSucs >= 4)
1399 if (CheckLimit && R.DFSNodeData[PredNum].InstrCount > R.SubtreeLimit)
1401 R.DFSNodeData[PredNum].SubtreeID = Succ->NodeNum;
1402 SubtreeClasses.join(Succ->NodeNum, PredNum);
1406 /// Called by finalize() to record a connection between trees.
1407 void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth) {
1412 SmallVectorImpl<SchedDFSResult::Connection> &Connections =
1413 R.SubtreeConnections[FromTree];
1414 for (SmallVectorImpl<SchedDFSResult::Connection>::iterator
1415 I = Connections.begin(), E = Connections.end(); I != E; ++I) {
1416 if (I->TreeID == ToTree) {
1417 I->Level = std::max(I->Level, Depth);
1421 Connections.push_back(SchedDFSResult::Connection(ToTree, Depth));
1422 FromTree = R.DFSTreeData[FromTree].ParentTreeID;
1423 } while (FromTree != SchedDFSResult::InvalidSubtreeID);
1429 /// \brief Manage the stack used by a reverse depth-first search over the DAG.
1430 class SchedDAGReverseDFS {
1431 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack;
1433 bool isComplete() const { return DFSStack.empty(); }
1435 void follow(const SUnit *SU) {
1436 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
1438 void advance() { ++DFSStack.back().second; }
1440 const SDep *backtrack() {
1441 DFSStack.pop_back();
1442 return DFSStack.empty() ? nullptr : std::prev(DFSStack.back().second);
1445 const SUnit *getCurr() const { return DFSStack.back().first; }
1447 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; }
1449 SUnit::const_pred_iterator getPredEnd() const {
1450 return getCurr()->Preds.end();
1455 static bool hasDataSucc(const SUnit *SU) {
1456 for (SUnit::const_succ_iterator
1457 SI = SU->Succs.begin(), SE = SU->Succs.end(); SI != SE; ++SI) {
1458 if (SI->getKind() == SDep::Data && !SI->getSUnit()->isBoundaryNode())
1464 /// Compute an ILP metric for all nodes in the subDAG reachable via depth-first
1465 /// search from this root.
1466 void SchedDFSResult::compute(ArrayRef<SUnit> SUnits) {
1468 llvm_unreachable("Top-down ILP metric is unimplemnted");
1470 SchedDFSImpl Impl(*this);
1471 for (ArrayRef<SUnit>::const_iterator
1472 SI = SUnits.begin(), SE = SUnits.end(); SI != SE; ++SI) {
1473 const SUnit *SU = &*SI;
1474 if (Impl.isVisited(SU) || hasDataSucc(SU))
1477 SchedDAGReverseDFS DFS;
1478 Impl.visitPreorder(SU);
1481 // Traverse the leftmost path as far as possible.
1482 while (DFS.getPred() != DFS.getPredEnd()) {
1483 const SDep &PredDep = *DFS.getPred();
1485 // Ignore non-data edges.
1486 if (PredDep.getKind() != SDep::Data
1487 || PredDep.getSUnit()->isBoundaryNode()) {
1490 // An already visited edge is a cross edge, assuming an acyclic DAG.
1491 if (Impl.isVisited(PredDep.getSUnit())) {
1492 Impl.visitCrossEdge(PredDep, DFS.getCurr());
1495 Impl.visitPreorder(PredDep.getSUnit());
1496 DFS.follow(PredDep.getSUnit());
1498 // Visit the top of the stack in postorder and backtrack.
1499 const SUnit *Child = DFS.getCurr();
1500 const SDep *PredDep = DFS.backtrack();
1501 Impl.visitPostorderNode(Child);
1503 Impl.visitPostorderEdge(*PredDep, DFS.getCurr());
1504 if (DFS.isComplete())
1511 /// The root of the given SubtreeID was just scheduled. For all subtrees
1512 /// connected to this tree, record the depth of the connection so that the
1513 /// nearest connected subtrees can be prioritized.
1514 void SchedDFSResult::scheduleTree(unsigned SubtreeID) {
1515 for (SmallVectorImpl<Connection>::const_iterator
1516 I = SubtreeConnections[SubtreeID].begin(),
1517 E = SubtreeConnections[SubtreeID].end(); I != E; ++I) {
1518 SubtreeConnectLevels[I->TreeID] =
1519 std::max(SubtreeConnectLevels[I->TreeID], I->Level);
1520 DEBUG(dbgs() << " Tree: " << I->TreeID
1521 << " @" << SubtreeConnectLevels[I->TreeID] << '\n');
1526 void ILPValue::print(raw_ostream &OS) const {
1527 OS << InstrCount << " / " << Length << " = ";
1531 OS << format("%g", ((double)InstrCount / Length));
1535 void ILPValue::dump() const {
1536 dbgs() << *this << '\n';
1542 raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) {