1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAGInstrs class, which implements re-scheduling
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
16 #include "llvm/ADT/IntEqClasses.h"
17 #include "llvm/ADT/MapVector.h"
18 #include "llvm/ADT/SmallPtrSet.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ValueTracking.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineMemOperand.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/RegisterPressure.h"
29 #include "llvm/CodeGen/ScheduleDFS.h"
30 #include "llvm/IR/Operator.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/Format.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetRegisterInfo.h"
38 #include "llvm/Target/TargetSubtargetInfo.h"
43 #define DEBUG_TYPE "misched"
45 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
46 cl::ZeroOrMore, cl::init(false),
47 cl::desc("Enable use of AA during MI DAG construction"));
49 static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
50 cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"));
52 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
53 const MachineLoopInfo *mli,
56 : ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()), LIS(LIS),
57 RemoveKillFlags(RemoveKillFlags), CanHandleTerminators(false),
58 TrackLaneMasks(false), FirstDbgValue(nullptr) {
61 const TargetSubtargetInfo &ST = mf.getSubtarget();
62 SchedModel.init(ST.getSchedModel(), &ST, TII);
65 /// getUnderlyingObjectFromInt - This is the function that does the work of
66 /// looking through basic ptrtoint+arithmetic+inttoptr sequences.
67 static const Value *getUnderlyingObjectFromInt(const Value *V) {
69 if (const Operator *U = dyn_cast<Operator>(V)) {
70 // If we find a ptrtoint, we can transfer control back to the
71 // regular getUnderlyingObjectFromInt.
72 if (U->getOpcode() == Instruction::PtrToInt)
73 return U->getOperand(0);
74 // If we find an add of a constant, a multiplied value, or a phi, it's
75 // likely that the other operand will lead us to the base
76 // object. We don't have to worry about the case where the
77 // object address is somehow being computed by the multiply,
78 // because our callers only care when the result is an
79 // identifiable object.
80 if (U->getOpcode() != Instruction::Add ||
81 (!isa<ConstantInt>(U->getOperand(1)) &&
82 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul &&
83 !isa<PHINode>(U->getOperand(1))))
89 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
93 /// getUnderlyingObjects - This is a wrapper around GetUnderlyingObjects
94 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
95 static void getUnderlyingObjects(const Value *V,
96 SmallVectorImpl<Value *> &Objects,
97 const DataLayout &DL) {
98 SmallPtrSet<const Value *, 16> Visited;
99 SmallVector<const Value *, 4> Working(1, V);
101 V = Working.pop_back_val();
103 SmallVector<Value *, 4> Objs;
104 GetUnderlyingObjects(const_cast<Value *>(V), Objs, DL);
106 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), IE = Objs.end();
109 if (!Visited.insert(V).second)
111 if (Operator::getOpcode(V) == Instruction::IntToPtr) {
113 getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
114 if (O->getType()->isPointerTy()) {
115 Working.push_back(O);
119 Objects.push_back(const_cast<Value *>(V));
121 } while (!Working.empty());
124 typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType;
125 typedef SmallVector<PointerIntPair<ValueType, 1, bool>, 4>
126 UnderlyingObjectsVector;
128 /// getUnderlyingObjectsForInstr - If this machine instr has memory reference
129 /// information and it can be tracked to a normal reference to a known
130 /// object, return the Value for that object.
131 static void getUnderlyingObjectsForInstr(const MachineInstr *MI,
132 const MachineFrameInfo *MFI,
133 UnderlyingObjectsVector &Objects,
134 const DataLayout &DL) {
135 if (!MI->hasOneMemOperand() ||
136 (!(*MI->memoperands_begin())->getValue() &&
137 !(*MI->memoperands_begin())->getPseudoValue()) ||
138 (*MI->memoperands_begin())->isVolatile())
141 if (const PseudoSourceValue *PSV =
142 (*MI->memoperands_begin())->getPseudoValue()) {
143 // Function that contain tail calls don't have unique PseudoSourceValue
144 // objects. Two PseudoSourceValues might refer to the same or overlapping
145 // locations. The client code calling this function assumes this is not the
146 // case. So return a conservative answer of no known object.
147 if (MFI->hasTailCall())
150 // For now, ignore PseudoSourceValues which may alias LLVM IR values
151 // because the code that uses this function has no way to cope with
153 if (!PSV->isAliased(MFI)) {
154 bool MayAlias = PSV->mayAlias(MFI);
155 Objects.push_back(UnderlyingObjectsVector::value_type(PSV, MayAlias));
160 const Value *V = (*MI->memoperands_begin())->getValue();
164 SmallVector<Value *, 4> Objs;
165 getUnderlyingObjects(V, Objs, DL);
167 for (Value *V : Objs) {
168 if (!isIdentifiedObject(V)) {
173 Objects.push_back(UnderlyingObjectsVector::value_type(V, true));
177 void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
181 void ScheduleDAGInstrs::finishBlock() {
182 // Subclasses should no longer refer to the old block.
186 /// Initialize the DAG and common scheduler state for the current scheduling
187 /// region. This does not actually create the DAG, only clears it. The
188 /// scheduling driver may call BuildSchedGraph multiple times per scheduling
190 void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
191 MachineBasicBlock::iterator begin,
192 MachineBasicBlock::iterator end,
193 unsigned regioninstrs) {
194 assert(bb == BB && "startBlock should set BB");
197 NumRegionInstrs = regioninstrs;
200 /// Close the current scheduling region. Don't clear any state in case the
201 /// driver wants to refer to the previous scheduling region.
202 void ScheduleDAGInstrs::exitRegion() {
206 /// addSchedBarrierDeps - Add dependencies from instructions in the current
207 /// list of instructions being scheduled to scheduling barrier by adding
208 /// the exit SU to the register defs and use list. This is because we want to
209 /// make sure instructions which define registers that are either used by
210 /// the terminator or are live-out are properly scheduled. This is
211 /// especially important when the definition latency of the return value(s)
212 /// are too high to be hidden by the branch or when the liveout registers
213 /// used by instructions in the fallthrough block.
214 void ScheduleDAGInstrs::addSchedBarrierDeps() {
215 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : nullptr;
216 ExitSU.setInstr(ExitMI);
217 bool AllDepKnown = ExitMI &&
218 (ExitMI->isCall() || ExitMI->isBarrier());
219 if (ExitMI && AllDepKnown) {
220 // If it's a call or a barrier, add dependencies on the defs and uses of
222 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
223 const MachineOperand &MO = ExitMI->getOperand(i);
224 if (!MO.isReg() || MO.isDef()) continue;
225 unsigned Reg = MO.getReg();
226 if (Reg == 0) continue;
228 if (TRI->isPhysicalRegister(Reg))
229 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
230 else if (MO.readsReg()) // ignore undef operands
231 addVRegUseDeps(&ExitSU, i);
234 // For others, e.g. fallthrough, conditional branch, assume the exit
235 // uses all the registers that are livein to the successor blocks.
236 assert(Uses.empty() && "Uses in set before adding deps?");
237 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
238 SE = BB->succ_end(); SI != SE; ++SI)
239 for (const auto &LI : (*SI)->liveins()) {
240 if (!Uses.contains(LI.PhysReg))
241 Uses.insert(PhysRegSUOper(&ExitSU, -1, LI.PhysReg));
246 /// MO is an operand of SU's instruction that defines a physical register. Add
247 /// data dependencies from SU to any uses of the physical register.
248 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
249 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
250 assert(MO.isDef() && "expect physreg def");
252 // Ask the target if address-backscheduling is desirable, and if so how much.
253 const TargetSubtargetInfo &ST = MF.getSubtarget();
255 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
256 Alias.isValid(); ++Alias) {
257 if (!Uses.contains(*Alias))
259 for (Reg2SUnitsMap::iterator I = Uses.find(*Alias); I != Uses.end(); ++I) {
260 SUnit *UseSU = I->SU;
264 // Adjust the dependence latency using operand def/use information,
265 // then allow the target to perform its own adjustments.
266 int UseOp = I->OpIdx;
267 MachineInstr *RegUse = nullptr;
270 Dep = SDep(SU, SDep::Artificial);
272 // Set the hasPhysRegDefs only for physreg defs that have a use within
273 // the scheduling region.
274 SU->hasPhysRegDefs = true;
275 Dep = SDep(SU, SDep::Data, *Alias);
276 RegUse = UseSU->getInstr();
279 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,
282 ST.adjustSchedDependency(SU, UseSU, Dep);
288 /// addPhysRegDeps - Add register dependencies (data, anti, and output) from
289 /// this SUnit to following instructions in the same scheduling region that
290 /// depend the physical register referenced at OperIdx.
291 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
292 MachineInstr *MI = SU->getInstr();
293 MachineOperand &MO = MI->getOperand(OperIdx);
295 // Optionally add output and anti dependencies. For anti
296 // dependencies we use a latency of 0 because for a multi-issue
297 // target we want to allow the defining instruction to issue
298 // in the same cycle as the using instruction.
299 // TODO: Using a latency of 1 here for output dependencies assumes
300 // there's no cost for reusing registers.
301 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
302 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
303 Alias.isValid(); ++Alias) {
304 if (!Defs.contains(*Alias))
306 for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) {
307 SUnit *DefSU = I->SU;
308 if (DefSU == &ExitSU)
311 (Kind != SDep::Output || !MO.isDead() ||
312 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
313 if (Kind == SDep::Anti)
314 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
316 SDep Dep(SU, Kind, /*Reg=*/*Alias);
318 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
326 SU->hasPhysRegUses = true;
327 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
328 // retrieve the existing SUnits list for this register's uses.
329 // Push this SUnit on the use list.
330 Uses.insert(PhysRegSUOper(SU, OperIdx, MO.getReg()));
335 addPhysRegDataDeps(SU, OperIdx);
336 unsigned Reg = MO.getReg();
338 // clear this register's use list
339 if (Uses.contains(Reg))
344 } else if (SU->isCall) {
345 // Calls will not be reordered because of chain dependencies (see
346 // below). Since call operands are dead, calls may continue to be added
347 // to the DefList making dependence checking quadratic in the size of
348 // the block. Instead, we leave only one call at the back of the
350 Reg2SUnitsMap::RangePair P = Defs.equal_range(Reg);
351 Reg2SUnitsMap::iterator B = P.first;
352 Reg2SUnitsMap::iterator I = P.second;
353 for (bool isBegin = I == B; !isBegin; /* empty */) {
354 isBegin = (--I) == B;
361 // Defs are pushed in the order they are visited and never reordered.
362 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));
366 LaneBitmask ScheduleDAGInstrs::getLaneMaskForMO(const MachineOperand &MO) const
368 unsigned Reg = MO.getReg();
369 // No point in tracking lanemasks if we don't have interesting subregisters.
370 const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
371 if (!RC.HasDisjunctSubRegs)
374 unsigned SubReg = MO.getSubReg();
376 return RC.getLaneMask();
377 return TRI->getSubRegIndexLaneMask(SubReg);
380 /// addVRegDefDeps - Add register output and data dependencies from this SUnit
381 /// to instructions that occur later in the same scheduling region if they read
382 /// from or write to the virtual register defined at OperIdx.
384 /// TODO: Hoist loop induction variable increments. This has to be
385 /// reevaluated. Generally, IV scheduling should be done before coalescing.
386 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
387 MachineInstr *MI = SU->getInstr();
388 MachineOperand &MO = MI->getOperand(OperIdx);
389 unsigned Reg = MO.getReg();
391 LaneBitmask DefLaneMask;
392 LaneBitmask KillLaneMask;
393 if (TrackLaneMasks) {
394 bool IsKill = MO.getSubReg() == 0 || MO.isUndef();
395 DefLaneMask = getLaneMaskForMO(MO);
396 // If we have a <read-undef> flag, none of the lane values comes from an
397 // earlier instruction.
398 KillLaneMask = IsKill ? ~0u : DefLaneMask;
400 // Clear undef flag, we'll re-add it later once we know which subregister
402 MO.setIsUndef(false);
409 assert(CurrentVRegUses.find(Reg) == CurrentVRegUses.end() &&
410 "Dead defs should have no uses");
412 // Add data dependence to all uses we found so far.
413 const TargetSubtargetInfo &ST = MF.getSubtarget();
414 for (VReg2SUnitOperIdxMultiMap::iterator I = CurrentVRegUses.find(Reg),
415 E = CurrentVRegUses.end(); I != E; /*empty*/) {
416 LaneBitmask LaneMask = I->LaneMask;
417 // Ignore uses of other lanes.
418 if ((LaneMask & KillLaneMask) == 0) {
423 if ((LaneMask & DefLaneMask) != 0) {
424 SUnit *UseSU = I->SU;
425 MachineInstr *Use = UseSU->getInstr();
426 SDep Dep(SU, SDep::Data, Reg);
427 Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use,
429 ST.adjustSchedDependency(SU, UseSU, Dep);
433 LaneMask &= ~KillLaneMask;
434 // If we found a Def for all lanes of this use, remove it from the list.
436 I->LaneMask = LaneMask;
439 I = CurrentVRegUses.erase(I);
443 // Shortcut: Singly defined vregs do not have output/anti dependencies.
444 if (MRI.hasOneDef(Reg))
447 // Add output dependence to the next nearest defs of this vreg.
449 // Unless this definition is dead, the output dependence should be
450 // transitively redundant with antidependencies from this definition's
451 // uses. We're conservative for now until we have a way to guarantee the uses
452 // are not eliminated sometime during scheduling. The output dependence edge
453 // is also useful if output latency exceeds def-use latency.
454 LaneBitmask LaneMask = DefLaneMask;
455 for (VReg2SUnit &V2SU : make_range(CurrentVRegDefs.find(Reg),
456 CurrentVRegDefs.end())) {
457 // Ignore defs for other lanes.
458 if ((V2SU.LaneMask & LaneMask) == 0)
460 // Add an output dependence.
461 SUnit *DefSU = V2SU.SU;
462 // Ignore additional defs of the same lanes in one instruction. This can
463 // happen because lanemasks are shared for targets with too many
464 // subregisters. We also use some representration tricks/hacks where we
465 // add super-register defs/uses, to imply that although we only access parts
466 // of the reg we care about the full one.
469 SDep Dep(SU, SDep::Output, Reg);
471 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
474 // Update current definition. This can get tricky if the def was about a
475 // bigger lanemask before. We then have to shrink it and create a new
476 // VReg2SUnit for the non-overlapping part.
477 LaneBitmask OverlapMask = V2SU.LaneMask & LaneMask;
478 LaneBitmask NonOverlapMask = V2SU.LaneMask & ~LaneMask;
479 if (NonOverlapMask != 0)
480 CurrentVRegDefs.insert(VReg2SUnit(Reg, NonOverlapMask, V2SU.SU));
482 V2SU.LaneMask = OverlapMask;
484 // If there was no CurrentVRegDefs entry for some lanes yet, create one.
486 CurrentVRegDefs.insert(VReg2SUnit(Reg, LaneMask, SU));
489 /// addVRegUseDeps - Add a register data dependency if the instruction that
490 /// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
491 /// register antidependency from this SUnit to instructions that occur later in
492 /// the same scheduling region if they write the virtual register.
494 /// TODO: Handle ExitSU "uses" properly.
495 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
496 const MachineInstr *MI = SU->getInstr();
497 const MachineOperand &MO = MI->getOperand(OperIdx);
498 unsigned Reg = MO.getReg();
500 // Remember the use. Data dependencies will be added when we find the def.
501 LaneBitmask LaneMask = TrackLaneMasks ? getLaneMaskForMO(MO) : ~0u;
502 CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU));
504 // Add antidependences to the following defs of the vreg.
505 for (VReg2SUnit &V2SU : make_range(CurrentVRegDefs.find(Reg),
506 CurrentVRegDefs.end())) {
507 // Ignore defs for unrelated lanes.
508 LaneBitmask PrevDefLaneMask = V2SU.LaneMask;
509 if ((PrevDefLaneMask & LaneMask) == 0)
514 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg));
518 /// Return true if MI is an instruction we are unable to reason about
519 /// (like a call or something with unmodeled side effects).
520 static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
521 return MI->isCall() || MI->hasUnmodeledSideEffects() ||
522 (MI->hasOrderedMemoryRef() &&
523 (!MI->mayLoad() || !MI->isInvariantLoad(AA)));
526 // This MI might have either incomplete info, or known to be unsafe
527 // to deal with (i.e. volatile object).
528 static inline bool isUnsafeMemoryObject(MachineInstr *MI,
529 const MachineFrameInfo *MFI,
530 const DataLayout &DL) {
531 if (!MI || MI->memoperands_empty())
533 // We purposefully do no check for hasOneMemOperand() here
534 // in hope to trigger an assert downstream in order to
535 // finish implementation.
536 if ((*MI->memoperands_begin())->isVolatile() ||
537 MI->hasUnmodeledSideEffects())
540 if ((*MI->memoperands_begin())->getPseudoValue()) {
541 // Similarly to getUnderlyingObjectForInstr:
542 // For now, ignore PseudoSourceValues which may alias LLVM IR values
543 // because the code that uses this function has no way to cope with
548 const Value *V = (*MI->memoperands_begin())->getValue();
552 SmallVector<Value *, 4> Objs;
553 getUnderlyingObjects(V, Objs, DL);
554 for (Value *V : Objs) {
555 // Does this pointer refer to a distinct and identifiable object?
556 if (!isIdentifiedObject(V))
563 /// This returns true if the two MIs need a chain edge between them.
564 /// If these are not even memory operations, we still may need
565 /// chain deps between them. The question really is - could
566 /// these two MIs be reordered during scheduling from memory dependency
568 static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI,
569 const DataLayout &DL, MachineInstr *MIa,
571 const MachineFunction *MF = MIa->getParent()->getParent();
572 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
574 // Cover a trivial case - no edge is need to itself.
578 // Let the target decide if memory accesses cannot possibly overlap.
579 if ((MIa->mayLoad() || MIa->mayStore()) &&
580 (MIb->mayLoad() || MIb->mayStore()))
581 if (TII->areMemAccessesTriviallyDisjoint(MIa, MIb, AA))
584 // FIXME: Need to handle multiple memory operands to support all targets.
585 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())
588 if (isUnsafeMemoryObject(MIa, MFI, DL) || isUnsafeMemoryObject(MIb, MFI, DL))
591 // If we are dealing with two "normal" loads, we do not need an edge
592 // between them - they could be reordered.
593 if (!MIa->mayStore() && !MIb->mayStore())
596 // To this point analysis is generic. From here on we do need AA.
600 MachineMemOperand *MMOa = *MIa->memoperands_begin();
601 MachineMemOperand *MMOb = *MIb->memoperands_begin();
603 if (!MMOa->getValue() || !MMOb->getValue())
606 // The following interface to AA is fashioned after DAGCombiner::isAlias
607 // and operates with MachineMemOperand offset with some important
609 // - LLVM fundamentally assumes flat address spaces.
610 // - MachineOperand offset can *only* result from legalization and
611 // cannot affect queries other than the trivial case of overlap
613 // - These offsets never wrap and never step outside
614 // of allocated objects.
615 // - There should never be any negative offsets here.
617 // FIXME: Modify API to hide this math from "user"
618 // FIXME: Even before we go to AA we can reason locally about some
619 // memory objects. It can save compile time, and possibly catch some
620 // corner cases not currently covered.
622 assert ((MMOa->getOffset() >= 0) && "Negative MachineMemOperand offset");
623 assert ((MMOb->getOffset() >= 0) && "Negative MachineMemOperand offset");
625 int64_t MinOffset = std::min(MMOa->getOffset(), MMOb->getOffset());
626 int64_t Overlapa = MMOa->getSize() + MMOa->getOffset() - MinOffset;
627 int64_t Overlapb = MMOb->getSize() + MMOb->getOffset() - MinOffset;
629 AliasResult AAResult =
630 AA->alias(MemoryLocation(MMOa->getValue(), Overlapa,
631 UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
632 MemoryLocation(MMOb->getValue(), Overlapb,
633 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
635 return (AAResult != NoAlias);
638 /// This recursive function iterates over chain deps of SUb looking for
639 /// "latest" node that needs a chain edge to SUa.
640 static unsigned iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI,
641 const DataLayout &DL, SUnit *SUa, SUnit *SUb,
642 SUnit *ExitSU, unsigned *Depth,
643 SmallPtrSetImpl<const SUnit *> &Visited) {
644 if (!SUa || !SUb || SUb == ExitSU)
647 // Remember visited nodes.
648 if (!Visited.insert(SUb).second)
650 // If there is _some_ dependency already in place, do not
651 // descend any further.
652 // TODO: Need to make sure that if that dependency got eliminated or ignored
653 // for any reason in the future, we would not violate DAG topology.
654 // Currently it does not happen, but makes an implicit assumption about
655 // future implementation.
657 // Independently, if we encounter node that is some sort of global
658 // object (like a call) we already have full set of dependencies to it
659 // and we can stop descending.
660 if (SUa->isSucc(SUb) ||
661 isGlobalMemoryObject(AA, SUb->getInstr()))
664 // If we do need an edge, or we have exceeded depth budget,
665 // add that edge to the predecessors chain of SUb,
666 // and stop descending.
668 MIsNeedChainEdge(AA, MFI, DL, SUa->getInstr(), SUb->getInstr())) {
669 SUb->addPred(SDep(SUa, SDep::MayAliasMem));
672 // Track current depth.
674 // Iterate over memory dependencies only.
675 for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end();
677 if (I->isNormalMemoryOrBarrier())
678 iterateChainSucc(AA, MFI, DL, SUa, I->getSUnit(), ExitSU, Depth, Visited);
682 /// This function assumes that "downward" from SU there exist
683 /// tail/leaf of already constructed DAG. It iterates downward and
684 /// checks whether SU can be aliasing any node dominated
686 static void adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI,
687 const DataLayout &DL, SUnit *SU, SUnit *ExitSU,
688 std::set<SUnit *> &CheckList,
689 unsigned LatencyToLoad) {
693 SmallPtrSet<const SUnit*, 16> Visited;
696 for (std::set<SUnit *>::iterator I = CheckList.begin(), IE = CheckList.end();
700 if (MIsNeedChainEdge(AA, MFI, DL, SU->getInstr(), (*I)->getInstr())) {
701 SDep Dep(SU, SDep::MayAliasMem);
702 Dep.setLatency(((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0);
706 // Iterate recursively over all previously added memory chain
707 // successors. Keep track of visited nodes.
708 for (SUnit::const_succ_iterator J = (*I)->Succs.begin(),
709 JE = (*I)->Succs.end(); J != JE; ++J)
710 if (J->isNormalMemoryOrBarrier())
711 iterateChainSucc(AA, MFI, DL, SU, J->getSUnit(), ExitSU, &Depth,
716 /// Check whether two objects need a chain edge, if so, add it
717 /// otherwise remember the rejected SU.
718 static inline void addChainDependency(AliasAnalysis *AA,
719 const MachineFrameInfo *MFI,
720 const DataLayout &DL, SUnit *SUa,
721 SUnit *SUb, std::set<SUnit *> &RejectList,
722 unsigned TrueMemOrderLatency = 0,
723 bool isNormalMemory = false) {
724 // If this is a false dependency,
725 // do not add the edge, but remember the rejected node.
726 if (MIsNeedChainEdge(AA, MFI, DL, SUa->getInstr(), SUb->getInstr())) {
727 SDep Dep(SUa, isNormalMemory ? SDep::MayAliasMem : SDep::Barrier);
728 Dep.setLatency(TrueMemOrderLatency);
732 // Duplicate entries should be ignored.
733 RejectList.insert(SUb);
734 DEBUG(dbgs() << "\tReject chain dep between SU("
735 << SUa->NodeNum << ") and SU("
736 << SUb->NodeNum << ")\n");
740 /// Create an SUnit for each real instruction, numbered in top-down topological
741 /// order. The instruction order A < B, implies that no edge exists from B to A.
743 /// Map each real instruction to its SUnit.
745 /// After initSUnits, the SUnits vector cannot be resized and the scheduler may
746 /// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
747 /// instead of pointers.
749 /// MachineScheduler relies on initSUnits numbering the nodes by their order in
750 /// the original instruction list.
751 void ScheduleDAGInstrs::initSUnits() {
752 // We'll be allocating one SUnit for each real instruction in the region,
753 // which is contained within a basic block.
754 SUnits.reserve(NumRegionInstrs);
756 for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) {
757 MachineInstr *MI = I;
758 if (MI->isDebugValue())
761 SUnit *SU = newSUnit(MI);
764 SU->isCall = MI->isCall();
765 SU->isCommutable = MI->isCommutable();
767 // Assign the Latency field of SU using target-provided information.
768 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
770 // If this SUnit uses a reserved or unbuffered resource, mark it as such.
772 // Reserved resources block an instruction from issuing and stall the
773 // entire pipeline. These are identified by BufferSize=0.
775 // Unbuffered resources prevent execution of subsequent instructions that
776 // require the same resources. This is used for in-order execution pipelines
777 // within an out-of-order core. These are identified by BufferSize=1.
778 if (SchedModel.hasInstrSchedModel()) {
779 const MCSchedClassDesc *SC = getSchedClass(SU);
780 for (TargetSchedModel::ProcResIter
781 PI = SchedModel.getWriteProcResBegin(SC),
782 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
783 switch (SchedModel.getProcResource(PI->ProcResourceIdx)->BufferSize) {
785 SU->hasReservedResource = true;
788 SU->isUnbuffered = true;
798 void ScheduleDAGInstrs::collectVRegUses(SUnit *SU) {
799 const MachineInstr *MI = SU->getInstr();
800 for (const MachineOperand &MO : MI->operands()) {
805 if (TrackLaneMasks && !MO.isUse())
808 unsigned Reg = MO.getReg();
809 if (!TargetRegisterInfo::isVirtualRegister(Reg))
812 // Record this local VReg use.
813 VReg2SUnitMultiMap::iterator UI = VRegUses.find(Reg);
814 for (; UI != VRegUses.end(); ++UI) {
818 if (UI == VRegUses.end())
819 VRegUses.insert(VReg2SUnit(Reg, 0, SU));
823 /// If RegPressure is non-null, compute register pressure as a side effect. The
824 /// DAG builder is an efficient place to do it because it already visits
826 void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
827 RegPressureTracker *RPTracker,
828 PressureDiffs *PDiffs,
829 bool TrackLaneMasks) {
830 const TargetSubtargetInfo &ST = MF.getSubtarget();
831 bool UseAA = EnableAASchedMI.getNumOccurrences() > 0 ? EnableAASchedMI
833 AliasAnalysis *AAForDep = UseAA ? AA : nullptr;
835 this->TrackLaneMasks = TrackLaneMasks;
837 ScheduleDAG::clearDAG();
839 // Create an SUnit for each real instruction.
843 PDiffs->init(SUnits.size());
845 // We build scheduling units by walking a block's instruction list from bottom
848 // Remember where a generic side-effecting instruction is as we proceed.
849 SUnit *BarrierChain = nullptr, *AliasChain = nullptr;
851 // Memory references to specific known memory locations are tracked
852 // so that they can be given more precise dependencies. We track
853 // separately the known memory locations that may alias and those
854 // that are known not to alias
855 MapVector<ValueType, std::vector<SUnit *> > AliasMemDefs, NonAliasMemDefs;
856 MapVector<ValueType, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
857 std::set<SUnit*> RejectMemNodes;
859 // Remove any stale debug info; sometimes BuildSchedGraph is called again
860 // without emitting the info from the previous call.
862 FirstDbgValue = nullptr;
864 assert(Defs.empty() && Uses.empty() &&
865 "Only BuildGraph should update Defs/Uses");
866 Defs.setUniverse(TRI->getNumRegs());
867 Uses.setUniverse(TRI->getNumRegs());
869 assert(CurrentVRegDefs.empty() && "nobody else should use CurrentVRegDefs");
870 assert(CurrentVRegUses.empty() && "nobody else should use CurrentVRegUses");
871 unsigned NumVirtRegs = MRI.getNumVirtRegs();
872 CurrentVRegDefs.setUniverse(NumVirtRegs);
873 CurrentVRegUses.setUniverse(NumVirtRegs);
876 VRegUses.setUniverse(NumVirtRegs);
878 // Model data dependencies between instructions being scheduled and the
880 addSchedBarrierDeps();
882 // Walk the list of instructions, from bottom moving up.
883 MachineInstr *DbgMI = nullptr;
884 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
886 MachineInstr *MI = std::prev(MII);
888 DbgValues.push_back(std::make_pair(DbgMI, MI));
892 if (MI->isDebugValue()) {
896 SUnit *SU = MISUnitMap[MI];
897 assert(SU && "No SUnit mapped to this MI");
900 PressureDiff *PDiff = PDiffs ? &(*PDiffs)[SU->NodeNum] : nullptr;
901 RPTracker->recede(/*LiveUses=*/nullptr, PDiff);
902 assert(RPTracker->getPos() == std::prev(MII) &&
903 "RPTracker can't find MI");
908 (CanHandleTerminators || (!MI->isTerminator() && !MI->isPosition())) &&
909 "Cannot schedule terminators or labels!");
911 // Add register-based dependencies (data, anti, and output).
912 bool HasVRegDef = false;
913 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
914 const MachineOperand &MO = MI->getOperand(j);
915 if (!MO.isReg()) continue;
916 unsigned Reg = MO.getReg();
917 if (Reg == 0) continue;
919 if (TRI->isPhysicalRegister(Reg))
920 addPhysRegDeps(SU, j);
924 addVRegDefDeps(SU, j);
926 else if (MO.readsReg()) // ignore undef operands
927 addVRegUseDeps(SU, j);
930 // If we haven't seen any uses in this scheduling region, create a
931 // dependence edge to ExitSU to model the live-out latency. This is required
932 // for vreg defs with no in-region use, and prefetches with no vreg def.
934 // FIXME: NumDataSuccs would be more precise than NumSuccs here. This
935 // check currently relies on being called before adding chain deps.
936 if (SU->NumSuccs == 0 && SU->Latency > 1
937 && (HasVRegDef || MI->mayLoad())) {
938 SDep Dep(SU, SDep::Artificial);
939 Dep.setLatency(SU->Latency - 1);
943 // Add chain dependencies.
944 // Chain dependencies used to enforce memory order should have
945 // latency of 0 (except for true dependency of Store followed by
946 // aliased Load... we estimate that with a single cycle of latency
947 // assuming the hardware will bypass)
948 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
949 // after stack slots are lowered to actual addresses.
950 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and
951 // produce more precise dependence information.
952 unsigned TrueMemOrderLatency = MI->mayStore() ? 1 : 0;
953 if (isGlobalMemoryObject(AA, MI)) {
954 // Be conservative with these and add dependencies on all memory
955 // references, even those that are known to not alias.
956 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
957 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
958 for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
959 I->second[i]->addPred(SDep(SU, SDep::Barrier));
962 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
963 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
964 for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
965 SDep Dep(SU, SDep::Barrier);
966 Dep.setLatency(TrueMemOrderLatency);
967 I->second[i]->addPred(Dep);
970 // Add SU to the barrier chain.
972 BarrierChain->addPred(SDep(SU, SDep::Barrier));
974 // This is a barrier event that acts as a pivotal node in the DAG,
975 // so it is safe to clear list of exposed nodes.
976 adjustChainDeps(AA, MFI, MF.getDataLayout(), SU, &ExitSU, RejectMemNodes,
977 TrueMemOrderLatency);
978 RejectMemNodes.clear();
979 NonAliasMemDefs.clear();
980 NonAliasMemUses.clear();
984 // Chain all possibly aliasing memory references through SU.
986 unsigned ChainLatency = 0;
987 if (AliasChain->getInstr()->mayLoad())
988 ChainLatency = TrueMemOrderLatency;
989 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU, AliasChain,
990 RejectMemNodes, ChainLatency);
993 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
994 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
995 PendingLoads[k], RejectMemNodes,
996 TrueMemOrderLatency);
997 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
998 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I) {
999 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1000 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
1001 I->second[i], RejectMemNodes);
1003 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
1004 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
1005 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1006 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
1007 I->second[i], RejectMemNodes, TrueMemOrderLatency);
1009 adjustChainDeps(AA, MFI, MF.getDataLayout(), SU, &ExitSU, RejectMemNodes,
1010 TrueMemOrderLatency);
1011 PendingLoads.clear();
1012 AliasMemDefs.clear();
1013 AliasMemUses.clear();
1014 } else if (MI->mayStore()) {
1015 // Add dependence on barrier chain, if needed.
1016 // There is no point to check aliasing on barrier event. Even if
1017 // SU and barrier _could_ be reordered, they should not. In addition,
1018 // we have lost all RejectMemNodes below barrier.
1020 BarrierChain->addPred(SDep(SU, SDep::Barrier));
1022 UnderlyingObjectsVector Objs;
1023 getUnderlyingObjectsForInstr(MI, MFI, Objs, MF.getDataLayout());
1026 // Treat all other stores conservatively.
1027 goto new_alias_chain;
1030 bool MayAlias = false;
1031 for (UnderlyingObjectsVector::iterator K = Objs.begin(), KE = Objs.end();
1033 ValueType V = K->getPointer();
1034 bool ThisMayAlias = K->getInt();
1038 // A store to a specific PseudoSourceValue. Add precise dependencies.
1039 // Record the def in MemDefs, first adding a dep if there is
1041 MapVector<ValueType, std::vector<SUnit *> >::iterator I =
1042 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
1043 MapVector<ValueType, std::vector<SUnit *> >::iterator IE =
1044 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
1046 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1047 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
1048 I->second[i], RejectMemNodes, 0, true);
1050 // If we're not using AA, then we only need one store per object.
1053 I->second.push_back(SU);
1057 AliasMemDefs[V].clear();
1058 AliasMemDefs[V].push_back(SU);
1061 NonAliasMemDefs[V].clear();
1062 NonAliasMemDefs[V].push_back(SU);
1065 // Handle the uses in MemUses, if there are any.
1066 MapVector<ValueType, std::vector<SUnit *> >::iterator J =
1067 ((ThisMayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
1068 MapVector<ValueType, std::vector<SUnit *> >::iterator JE =
1069 ((ThisMayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
1071 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
1072 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
1073 J->second[i], RejectMemNodes,
1074 TrueMemOrderLatency, true);
1079 // Add dependencies from all the PendingLoads, i.e. loads
1080 // with no underlying object.
1081 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
1082 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
1083 PendingLoads[k], RejectMemNodes,
1084 TrueMemOrderLatency);
1085 // Add dependence on alias chain, if needed.
1087 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU, AliasChain,
1090 adjustChainDeps(AA, MFI, MF.getDataLayout(), SU, &ExitSU, RejectMemNodes,
1091 TrueMemOrderLatency);
1092 } else if (MI->mayLoad()) {
1093 bool MayAlias = true;
1094 if (MI->isInvariantLoad(AA)) {
1095 // Invariant load, no chain dependencies needed!
1097 UnderlyingObjectsVector Objs;
1098 getUnderlyingObjectsForInstr(MI, MFI, Objs, MF.getDataLayout());
1101 // A load with no underlying object. Depend on all
1102 // potentially aliasing stores.
1103 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
1104 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
1105 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1106 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
1107 I->second[i], RejectMemNodes);
1109 PendingLoads.push_back(SU);
1115 for (UnderlyingObjectsVector::iterator
1116 J = Objs.begin(), JE = Objs.end(); J != JE; ++J) {
1117 ValueType V = J->getPointer();
1118 bool ThisMayAlias = J->getInt();
1123 // A load from a specific PseudoSourceValue. Add precise dependencies.
1124 MapVector<ValueType, std::vector<SUnit *> >::iterator I =
1125 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
1126 MapVector<ValueType, std::vector<SUnit *> >::iterator IE =
1127 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
1129 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1130 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
1131 I->second[i], RejectMemNodes, 0, true);
1133 AliasMemUses[V].push_back(SU);
1135 NonAliasMemUses[V].push_back(SU);
1138 adjustChainDeps(AA, MFI, MF.getDataLayout(), SU, &ExitSU,
1139 RejectMemNodes, /*Latency=*/0);
1140 // Add dependencies on alias and barrier chains, if needed.
1141 if (MayAlias && AliasChain)
1142 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU, AliasChain,
1145 BarrierChain->addPred(SDep(SU, SDep::Barrier));
1150 FirstDbgValue = DbgMI;
1154 CurrentVRegDefs.clear();
1155 CurrentVRegUses.clear();
1156 PendingLoads.clear();
1159 /// \brief Initialize register live-range state for updating kills.
1160 void ScheduleDAGInstrs::startBlockForKills(MachineBasicBlock *BB) {
1161 // Start with no live registers.
1164 // Examine the live-in regs of all successors.
1165 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
1166 SE = BB->succ_end(); SI != SE; ++SI) {
1167 for (const auto &LI : (*SI)->liveins()) {
1168 // Repeat, for reg and all subregs.
1169 for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true);
1170 SubRegs.isValid(); ++SubRegs)
1171 LiveRegs.set(*SubRegs);
1176 /// \brief If we change a kill flag on the bundle instruction implicit register
1177 /// operands, then we also need to propagate that to any instructions inside
1178 /// the bundle which had the same kill state.
1179 static void toggleBundleKillFlag(MachineInstr *MI, unsigned Reg,
1180 bool NewKillState) {
1181 if (MI->getOpcode() != TargetOpcode::BUNDLE)
1184 // Walk backwards from the last instruction in the bundle to the first.
1185 // Once we set a kill flag on an instruction, we bail out, as otherwise we
1186 // might set it on too many operands. We will clear as many flags as we
1188 MachineBasicBlock::instr_iterator Begin = MI->getIterator();
1189 MachineBasicBlock::instr_iterator End = getBundleEnd(MI);
1190 while (Begin != End) {
1191 for (MachineOperand &MO : (--End)->operands()) {
1192 if (!MO.isReg() || MO.isDef() || Reg != MO.getReg())
1195 // DEBUG_VALUE nodes do not contribute to code generation and should
1196 // always be ignored. Failure to do so may result in trying to modify
1197 // KILL flags on DEBUG_VALUE nodes, which is distressing.
1201 // If the register has the internal flag then it could be killing an
1202 // internal def of the register. In this case, just skip. We only want
1203 // to toggle the flag on operands visible outside the bundle.
1204 if (MO.isInternalRead())
1207 if (MO.isKill() == NewKillState)
1209 MO.setIsKill(NewKillState);
1216 bool ScheduleDAGInstrs::toggleKillFlag(MachineInstr *MI, MachineOperand &MO) {
1217 // Setting kill flag...
1220 toggleBundleKillFlag(MI, MO.getReg(), true);
1224 // If MO itself is live, clear the kill flag...
1225 if (LiveRegs.test(MO.getReg())) {
1226 MO.setIsKill(false);
1227 toggleBundleKillFlag(MI, MO.getReg(), false);
1231 // If any subreg of MO is live, then create an imp-def for that
1232 // subreg and keep MO marked as killed.
1233 MO.setIsKill(false);
1234 toggleBundleKillFlag(MI, MO.getReg(), false);
1235 bool AllDead = true;
1236 const unsigned SuperReg = MO.getReg();
1237 MachineInstrBuilder MIB(MF, MI);
1238 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
1239 if (LiveRegs.test(*SubRegs)) {
1240 MIB.addReg(*SubRegs, RegState::ImplicitDefine);
1247 toggleBundleKillFlag(MI, MO.getReg(), true);
1252 // FIXME: Reuse the LivePhysRegs utility for this.
1253 void ScheduleDAGInstrs::fixupKills(MachineBasicBlock *MBB) {
1254 DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
1256 LiveRegs.resize(TRI->getNumRegs());
1257 BitVector killedRegs(TRI->getNumRegs());
1259 startBlockForKills(MBB);
1261 // Examine block from end to start...
1262 unsigned Count = MBB->size();
1263 for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
1265 MachineInstr *MI = --I;
1266 if (MI->isDebugValue())
1269 // Update liveness. Registers that are defed but not used in this
1270 // instruction are now dead. Mark register and all subregs as they
1271 // are completely defined.
1272 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1273 MachineOperand &MO = MI->getOperand(i);
1275 LiveRegs.clearBitsNotInMask(MO.getRegMask());
1276 if (!MO.isReg()) continue;
1277 unsigned Reg = MO.getReg();
1278 if (Reg == 0) continue;
1279 if (!MO.isDef()) continue;
1280 // Ignore two-addr defs.
1281 if (MI->isRegTiedToUseOperand(i)) continue;
1283 // Repeat for reg and all subregs.
1284 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1285 SubRegs.isValid(); ++SubRegs)
1286 LiveRegs.reset(*SubRegs);
1289 // Examine all used registers and set/clear kill flag. When a
1290 // register is used multiple times we only set the kill flag on
1291 // the first use. Don't set kill flags on undef operands.
1293 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1294 MachineOperand &MO = MI->getOperand(i);
1295 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
1296 unsigned Reg = MO.getReg();
1297 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1300 if (!killedRegs.test(Reg)) {
1302 // A register is not killed if any subregs are live...
1303 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
1304 if (LiveRegs.test(*SubRegs)) {
1310 // If subreg is not live, then register is killed if it became
1311 // live in this instruction
1313 kill = !LiveRegs.test(Reg);
1316 if (MO.isKill() != kill) {
1317 DEBUG(dbgs() << "Fixing " << MO << " in ");
1318 // Warning: toggleKillFlag may invalidate MO.
1319 toggleKillFlag(MI, MO);
1321 DEBUG(if (MI->getOpcode() == TargetOpcode::BUNDLE) {
1322 MachineBasicBlock::instr_iterator Begin = MI->getIterator();
1323 MachineBasicBlock::instr_iterator End = getBundleEnd(MI);
1324 while (++Begin != End)
1325 DEBUG(Begin->dump());
1329 killedRegs.set(Reg);
1332 // Mark any used register (that is not using undef) and subregs as
1334 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1335 MachineOperand &MO = MI->getOperand(i);
1336 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
1337 unsigned Reg = MO.getReg();
1338 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1340 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1341 SubRegs.isValid(); ++SubRegs)
1342 LiveRegs.set(*SubRegs);
1347 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
1348 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1349 SU->getInstr()->dump();
1353 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1355 raw_string_ostream oss(s);
1358 else if (SU == &ExitSU)
1361 SU->getInstr()->print(oss, /*SkipOpers=*/true);
1365 /// Return the basic block label. It is not necessarilly unique because a block
1366 /// contains multiple scheduling regions. But it is fine for visualization.
1367 std::string ScheduleDAGInstrs::getDAGName() const {
1368 return "dag." + BB->getFullName();
1371 //===----------------------------------------------------------------------===//
1372 // SchedDFSResult Implementation
1373 //===----------------------------------------------------------------------===//
1376 /// \brief Internal state used to compute SchedDFSResult.
1377 class SchedDFSImpl {
1380 /// Join DAG nodes into equivalence classes by their subtree.
1381 IntEqClasses SubtreeClasses;
1382 /// List PredSU, SuccSU pairs that represent data edges between subtrees.
1383 std::vector<std::pair<const SUnit*, const SUnit*> > ConnectionPairs;
1387 unsigned ParentNodeID; // Parent node (member of the parent subtree).
1388 unsigned SubInstrCount; // Instr count in this tree only, not children.
1390 RootData(unsigned id): NodeID(id),
1391 ParentNodeID(SchedDFSResult::InvalidSubtreeID),
1394 unsigned getSparseSetIndex() const { return NodeID; }
1397 SparseSet<RootData> RootSet;
1400 SchedDFSImpl(SchedDFSResult &r): R(r), SubtreeClasses(R.DFSNodeData.size()) {
1401 RootSet.setUniverse(R.DFSNodeData.size());
1404 /// Return true if this node been visited by the DFS traversal.
1406 /// During visitPostorderNode the Node's SubtreeID is assigned to the Node
1407 /// ID. Later, SubtreeID is updated but remains valid.
1408 bool isVisited(const SUnit *SU) const {
1409 return R.DFSNodeData[SU->NodeNum].SubtreeID
1410 != SchedDFSResult::InvalidSubtreeID;
1413 /// Initialize this node's instruction count. We don't need to flag the node
1414 /// visited until visitPostorder because the DAG cannot have cycles.
1415 void visitPreorder(const SUnit *SU) {
1416 R.DFSNodeData[SU->NodeNum].InstrCount =
1417 SU->getInstr()->isTransient() ? 0 : 1;
1420 /// Called once for each node after all predecessors are visited. Revisit this
1421 /// node's predecessors and potentially join them now that we know the ILP of
1422 /// the other predecessors.
1423 void visitPostorderNode(const SUnit *SU) {
1424 // Mark this node as the root of a subtree. It may be joined with its
1425 // successors later.
1426 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
1427 RootData RData(SU->NodeNum);
1428 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
1430 // If any predecessors are still in their own subtree, they either cannot be
1431 // joined or are large enough to remain separate. If this parent node's
1432 // total instruction count is not greater than a child subtree by at least
1433 // the subtree limit, then try to join it now since splitting subtrees is
1434 // only useful if multiple high-pressure paths are possible.
1435 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
1436 for (SUnit::const_pred_iterator
1437 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1438 if (PI->getKind() != SDep::Data)
1440 unsigned PredNum = PI->getSUnit()->NodeNum;
1441 if ((InstrCount - R.DFSNodeData[PredNum].InstrCount) < R.SubtreeLimit)
1442 joinPredSubtree(*PI, SU, /*CheckLimit=*/false);
1444 // Either link or merge the TreeData entry from the child to the parent.
1445 if (R.DFSNodeData[PredNum].SubtreeID == PredNum) {
1446 // If the predecessor's parent is invalid, this is a tree edge and the
1447 // current node is the parent.
1448 if (RootSet[PredNum].ParentNodeID == SchedDFSResult::InvalidSubtreeID)
1449 RootSet[PredNum].ParentNodeID = SU->NodeNum;
1451 else if (RootSet.count(PredNum)) {
1452 // The predecessor is not a root, but is still in the root set. This
1453 // must be the new parent that it was just joined to. Note that
1454 // RootSet[PredNum].ParentNodeID may either be invalid or may still be
1455 // set to the original parent.
1456 RData.SubInstrCount += RootSet[PredNum].SubInstrCount;
1457 RootSet.erase(PredNum);
1460 RootSet[SU->NodeNum] = RData;
1463 /// Called once for each tree edge after calling visitPostOrderNode on the
1464 /// predecessor. Increment the parent node's instruction count and
1465 /// preemptively join this subtree to its parent's if it is small enough.
1466 void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ) {
1467 R.DFSNodeData[Succ->NodeNum].InstrCount
1468 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount;
1469 joinPredSubtree(PredDep, Succ);
1472 /// Add a connection for cross edges.
1473 void visitCrossEdge(const SDep &PredDep, const SUnit *Succ) {
1474 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ));
1477 /// Set each node's subtree ID to the representative ID and record connections
1480 SubtreeClasses.compress();
1481 R.DFSTreeData.resize(SubtreeClasses.getNumClasses());
1482 assert(SubtreeClasses.getNumClasses() == RootSet.size()
1483 && "number of roots should match trees");
1484 for (SparseSet<RootData>::const_iterator
1485 RI = RootSet.begin(), RE = RootSet.end(); RI != RE; ++RI) {
1486 unsigned TreeID = SubtreeClasses[RI->NodeID];
1487 if (RI->ParentNodeID != SchedDFSResult::InvalidSubtreeID)
1488 R.DFSTreeData[TreeID].ParentTreeID = SubtreeClasses[RI->ParentNodeID];
1489 R.DFSTreeData[TreeID].SubInstrCount = RI->SubInstrCount;
1490 // Note that SubInstrCount may be greater than InstrCount if we joined
1491 // subtrees across a cross edge. InstrCount will be attributed to the
1492 // original parent, while SubInstrCount will be attributed to the joined
1495 R.SubtreeConnections.resize(SubtreeClasses.getNumClasses());
1496 R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses());
1497 DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n");
1498 for (unsigned Idx = 0, End = R.DFSNodeData.size(); Idx != End; ++Idx) {
1499 R.DFSNodeData[Idx].SubtreeID = SubtreeClasses[Idx];
1500 DEBUG(dbgs() << " SU(" << Idx << ") in tree "
1501 << R.DFSNodeData[Idx].SubtreeID << '\n');
1503 for (std::vector<std::pair<const SUnit*, const SUnit*> >::const_iterator
1504 I = ConnectionPairs.begin(), E = ConnectionPairs.end();
1506 unsigned PredTree = SubtreeClasses[I->first->NodeNum];
1507 unsigned SuccTree = SubtreeClasses[I->second->NodeNum];
1508 if (PredTree == SuccTree)
1510 unsigned Depth = I->first->getDepth();
1511 addConnection(PredTree, SuccTree, Depth);
1512 addConnection(SuccTree, PredTree, Depth);
1517 /// Join the predecessor subtree with the successor that is its DFS
1518 /// parent. Apply some heuristics before joining.
1519 bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ,
1520 bool CheckLimit = true) {
1521 assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges");
1523 // Check if the predecessor is already joined.
1524 const SUnit *PredSU = PredDep.getSUnit();
1525 unsigned PredNum = PredSU->NodeNum;
1526 if (R.DFSNodeData[PredNum].SubtreeID != PredNum)
1529 // Four is the magic number of successors before a node is considered a
1531 unsigned NumDataSucs = 0;
1532 for (SUnit::const_succ_iterator SI = PredSU->Succs.begin(),
1533 SE = PredSU->Succs.end(); SI != SE; ++SI) {
1534 if (SI->getKind() == SDep::Data) {
1535 if (++NumDataSucs >= 4)
1539 if (CheckLimit && R.DFSNodeData[PredNum].InstrCount > R.SubtreeLimit)
1541 R.DFSNodeData[PredNum].SubtreeID = Succ->NodeNum;
1542 SubtreeClasses.join(Succ->NodeNum, PredNum);
1546 /// Called by finalize() to record a connection between trees.
1547 void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth) {
1552 SmallVectorImpl<SchedDFSResult::Connection> &Connections =
1553 R.SubtreeConnections[FromTree];
1554 for (SmallVectorImpl<SchedDFSResult::Connection>::iterator
1555 I = Connections.begin(), E = Connections.end(); I != E; ++I) {
1556 if (I->TreeID == ToTree) {
1557 I->Level = std::max(I->Level, Depth);
1561 Connections.push_back(SchedDFSResult::Connection(ToTree, Depth));
1562 FromTree = R.DFSTreeData[FromTree].ParentTreeID;
1563 } while (FromTree != SchedDFSResult::InvalidSubtreeID);
1569 /// \brief Manage the stack used by a reverse depth-first search over the DAG.
1570 class SchedDAGReverseDFS {
1571 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack;
1573 bool isComplete() const { return DFSStack.empty(); }
1575 void follow(const SUnit *SU) {
1576 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
1578 void advance() { ++DFSStack.back().second; }
1580 const SDep *backtrack() {
1581 DFSStack.pop_back();
1582 return DFSStack.empty() ? nullptr : std::prev(DFSStack.back().second);
1585 const SUnit *getCurr() const { return DFSStack.back().first; }
1587 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; }
1589 SUnit::const_pred_iterator getPredEnd() const {
1590 return getCurr()->Preds.end();
1595 static bool hasDataSucc(const SUnit *SU) {
1596 for (SUnit::const_succ_iterator
1597 SI = SU->Succs.begin(), SE = SU->Succs.end(); SI != SE; ++SI) {
1598 if (SI->getKind() == SDep::Data && !SI->getSUnit()->isBoundaryNode())
1604 /// Compute an ILP metric for all nodes in the subDAG reachable via depth-first
1605 /// search from this root.
1606 void SchedDFSResult::compute(ArrayRef<SUnit> SUnits) {
1608 llvm_unreachable("Top-down ILP metric is unimplemnted");
1610 SchedDFSImpl Impl(*this);
1611 for (ArrayRef<SUnit>::const_iterator
1612 SI = SUnits.begin(), SE = SUnits.end(); SI != SE; ++SI) {
1613 const SUnit *SU = &*SI;
1614 if (Impl.isVisited(SU) || hasDataSucc(SU))
1617 SchedDAGReverseDFS DFS;
1618 Impl.visitPreorder(SU);
1621 // Traverse the leftmost path as far as possible.
1622 while (DFS.getPred() != DFS.getPredEnd()) {
1623 const SDep &PredDep = *DFS.getPred();
1625 // Ignore non-data edges.
1626 if (PredDep.getKind() != SDep::Data
1627 || PredDep.getSUnit()->isBoundaryNode()) {
1630 // An already visited edge is a cross edge, assuming an acyclic DAG.
1631 if (Impl.isVisited(PredDep.getSUnit())) {
1632 Impl.visitCrossEdge(PredDep, DFS.getCurr());
1635 Impl.visitPreorder(PredDep.getSUnit());
1636 DFS.follow(PredDep.getSUnit());
1638 // Visit the top of the stack in postorder and backtrack.
1639 const SUnit *Child = DFS.getCurr();
1640 const SDep *PredDep = DFS.backtrack();
1641 Impl.visitPostorderNode(Child);
1643 Impl.visitPostorderEdge(*PredDep, DFS.getCurr());
1644 if (DFS.isComplete())
1651 /// The root of the given SubtreeID was just scheduled. For all subtrees
1652 /// connected to this tree, record the depth of the connection so that the
1653 /// nearest connected subtrees can be prioritized.
1654 void SchedDFSResult::scheduleTree(unsigned SubtreeID) {
1655 for (SmallVectorImpl<Connection>::const_iterator
1656 I = SubtreeConnections[SubtreeID].begin(),
1657 E = SubtreeConnections[SubtreeID].end(); I != E; ++I) {
1658 SubtreeConnectLevels[I->TreeID] =
1659 std::max(SubtreeConnectLevels[I->TreeID], I->Level);
1660 DEBUG(dbgs() << " Tree: " << I->TreeID
1661 << " @" << SubtreeConnectLevels[I->TreeID] << '\n');
1666 void ILPValue::print(raw_ostream &OS) const {
1667 OS << InstrCount << " / " << Length << " = ";
1671 OS << format("%g", ((double)InstrCount / Length));
1675 void ILPValue::dump() const {
1676 dbgs() << *this << '\n';
1682 raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) {