1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAGInstrs class, which implements re-scheduling
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
16 #include "llvm/ADT/MapVector.h"
17 #include "llvm/ADT/SmallPtrSet.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/ValueTracking.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineMemOperand.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/RegisterPressure.h"
29 #include "llvm/CodeGen/ScheduleDFS.h"
30 #include "llvm/IR/Operator.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/Format.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetRegisterInfo.h"
38 #include "llvm/Target/TargetSubtargetInfo.h"
43 #define DEBUG_TYPE "misched"
45 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
46 cl::ZeroOrMore, cl::init(false),
47 cl::desc("Enable use of AA during MI DAG construction"));
49 static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
50 cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"));
52 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
53 const MachineLoopInfo *mli,
54 bool IsPostRAFlag, bool RemoveKillFlags,
56 : ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()), LIS(lis),
57 IsPostRA(IsPostRAFlag), RemoveKillFlags(RemoveKillFlags),
58 CanHandleTerminators(false), FirstDbgValue(nullptr) {
59 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
61 assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
62 "Virtual registers must be removed prior to PostRA scheduling");
64 const TargetSubtargetInfo &ST = mf.getSubtarget();
65 SchedModel.init(ST.getSchedModel(), &ST, TII);
68 /// getUnderlyingObjectFromInt - This is the function that does the work of
69 /// looking through basic ptrtoint+arithmetic+inttoptr sequences.
70 static const Value *getUnderlyingObjectFromInt(const Value *V) {
72 if (const Operator *U = dyn_cast<Operator>(V)) {
73 // If we find a ptrtoint, we can transfer control back to the
74 // regular getUnderlyingObjectFromInt.
75 if (U->getOpcode() == Instruction::PtrToInt)
76 return U->getOperand(0);
77 // If we find an add of a constant, a multiplied value, or a phi, it's
78 // likely that the other operand will lead us to the base
79 // object. We don't have to worry about the case where the
80 // object address is somehow being computed by the multiply,
81 // because our callers only care when the result is an
82 // identifiable object.
83 if (U->getOpcode() != Instruction::Add ||
84 (!isa<ConstantInt>(U->getOperand(1)) &&
85 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul &&
86 !isa<PHINode>(U->getOperand(1))))
92 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
96 /// getUnderlyingObjects - This is a wrapper around GetUnderlyingObjects
97 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
98 static void getUnderlyingObjects(const Value *V,
99 SmallVectorImpl<Value *> &Objects,
100 const DataLayout &DL) {
101 SmallPtrSet<const Value *, 16> Visited;
102 SmallVector<const Value *, 4> Working(1, V);
104 V = Working.pop_back_val();
106 SmallVector<Value *, 4> Objs;
107 GetUnderlyingObjects(const_cast<Value *>(V), Objs, DL);
109 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), IE = Objs.end();
112 if (!Visited.insert(V).second)
114 if (Operator::getOpcode(V) == Instruction::IntToPtr) {
116 getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
117 if (O->getType()->isPointerTy()) {
118 Working.push_back(O);
122 Objects.push_back(const_cast<Value *>(V));
124 } while (!Working.empty());
127 typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType;
128 typedef SmallVector<PointerIntPair<ValueType, 1, bool>, 4>
129 UnderlyingObjectsVector;
131 /// getUnderlyingObjectsForInstr - If this machine instr has memory reference
132 /// information and it can be tracked to a normal reference to a known
133 /// object, return the Value for that object.
134 static void getUnderlyingObjectsForInstr(const MachineInstr *MI,
135 const MachineFrameInfo *MFI,
136 UnderlyingObjectsVector &Objects,
137 const DataLayout &DL) {
138 if (!MI->hasOneMemOperand() ||
139 (!(*MI->memoperands_begin())->getValue() &&
140 !(*MI->memoperands_begin())->getPseudoValue()) ||
141 (*MI->memoperands_begin())->isVolatile())
144 if (const PseudoSourceValue *PSV =
145 (*MI->memoperands_begin())->getPseudoValue()) {
146 // Function that contain tail calls don't have unique PseudoSourceValue
147 // objects. Two PseudoSourceValues might refer to the same or overlapping
148 // locations. The client code calling this function assumes this is not the
149 // case. So return a conservative answer of no known object.
150 if (MFI->hasTailCall())
153 // For now, ignore PseudoSourceValues which may alias LLVM IR values
154 // because the code that uses this function has no way to cope with
156 if (!PSV->isAliased(MFI)) {
157 bool MayAlias = PSV->mayAlias(MFI);
158 Objects.push_back(UnderlyingObjectsVector::value_type(PSV, MayAlias));
163 const Value *V = (*MI->memoperands_begin())->getValue();
167 SmallVector<Value *, 4> Objs;
168 getUnderlyingObjects(V, Objs, DL);
170 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), IE = Objs.end();
174 if (!isIdentifiedObject(V)) {
179 Objects.push_back(UnderlyingObjectsVector::value_type(V, true));
183 void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
187 void ScheduleDAGInstrs::finishBlock() {
188 // Subclasses should no longer refer to the old block.
192 /// Initialize the DAG and common scheduler state for the current scheduling
193 /// region. This does not actually create the DAG, only clears it. The
194 /// scheduling driver may call BuildSchedGraph multiple times per scheduling
196 void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
197 MachineBasicBlock::iterator begin,
198 MachineBasicBlock::iterator end,
199 unsigned regioninstrs) {
200 assert(bb == BB && "startBlock should set BB");
203 NumRegionInstrs = regioninstrs;
206 /// Close the current scheduling region. Don't clear any state in case the
207 /// driver wants to refer to the previous scheduling region.
208 void ScheduleDAGInstrs::exitRegion() {
212 /// addSchedBarrierDeps - Add dependencies from instructions in the current
213 /// list of instructions being scheduled to scheduling barrier by adding
214 /// the exit SU to the register defs and use list. This is because we want to
215 /// make sure instructions which define registers that are either used by
216 /// the terminator or are live-out are properly scheduled. This is
217 /// especially important when the definition latency of the return value(s)
218 /// are too high to be hidden by the branch or when the liveout registers
219 /// used by instructions in the fallthrough block.
220 void ScheduleDAGInstrs::addSchedBarrierDeps() {
221 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : nullptr;
222 ExitSU.setInstr(ExitMI);
223 bool AllDepKnown = ExitMI &&
224 (ExitMI->isCall() || ExitMI->isBarrier());
225 if (ExitMI && AllDepKnown) {
226 // If it's a call or a barrier, add dependencies on the defs and uses of
228 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
229 const MachineOperand &MO = ExitMI->getOperand(i);
230 if (!MO.isReg() || MO.isDef()) continue;
231 unsigned Reg = MO.getReg();
232 if (Reg == 0) continue;
234 if (TRI->isPhysicalRegister(Reg))
235 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
237 assert(!IsPostRA && "Virtual register encountered after regalloc.");
238 if (MO.readsReg()) // ignore undef operands
239 addVRegUseDeps(&ExitSU, i);
243 // For others, e.g. fallthrough, conditional branch, assume the exit
244 // uses all the registers that are livein to the successor blocks.
245 assert(Uses.empty() && "Uses in set before adding deps?");
246 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
247 SE = BB->succ_end(); SI != SE; ++SI)
248 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
249 E = (*SI)->livein_end(); I != E; ++I) {
251 if (!Uses.contains(Reg))
252 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
257 /// MO is an operand of SU's instruction that defines a physical register. Add
258 /// data dependencies from SU to any uses of the physical register.
259 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
260 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
261 assert(MO.isDef() && "expect physreg def");
263 // Ask the target if address-backscheduling is desirable, and if so how much.
264 const TargetSubtargetInfo &ST = MF.getSubtarget();
266 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
267 Alias.isValid(); ++Alias) {
268 if (!Uses.contains(*Alias))
270 for (Reg2SUnitsMap::iterator I = Uses.find(*Alias); I != Uses.end(); ++I) {
271 SUnit *UseSU = I->SU;
275 // Adjust the dependence latency using operand def/use information,
276 // then allow the target to perform its own adjustments.
277 int UseOp = I->OpIdx;
278 MachineInstr *RegUse = nullptr;
281 Dep = SDep(SU, SDep::Artificial);
283 // Set the hasPhysRegDefs only for physreg defs that have a use within
284 // the scheduling region.
285 SU->hasPhysRegDefs = true;
286 Dep = SDep(SU, SDep::Data, *Alias);
287 RegUse = UseSU->getInstr();
290 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,
293 ST.adjustSchedDependency(SU, UseSU, Dep);
299 /// addPhysRegDeps - Add register dependencies (data, anti, and output) from
300 /// this SUnit to following instructions in the same scheduling region that
301 /// depend the physical register referenced at OperIdx.
302 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
303 MachineInstr *MI = SU->getInstr();
304 MachineOperand &MO = MI->getOperand(OperIdx);
306 // Optionally add output and anti dependencies. For anti
307 // dependencies we use a latency of 0 because for a multi-issue
308 // target we want to allow the defining instruction to issue
309 // in the same cycle as the using instruction.
310 // TODO: Using a latency of 1 here for output dependencies assumes
311 // there's no cost for reusing registers.
312 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
313 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
314 Alias.isValid(); ++Alias) {
315 if (!Defs.contains(*Alias))
317 for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) {
318 SUnit *DefSU = I->SU;
319 if (DefSU == &ExitSU)
322 (Kind != SDep::Output || !MO.isDead() ||
323 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
324 if (Kind == SDep::Anti)
325 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
327 SDep Dep(SU, Kind, /*Reg=*/*Alias);
329 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
337 SU->hasPhysRegUses = true;
338 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
339 // retrieve the existing SUnits list for this register's uses.
340 // Push this SUnit on the use list.
341 Uses.insert(PhysRegSUOper(SU, OperIdx, MO.getReg()));
346 addPhysRegDataDeps(SU, OperIdx);
347 unsigned Reg = MO.getReg();
349 // clear this register's use list
350 if (Uses.contains(Reg))
355 } else if (SU->isCall) {
356 // Calls will not be reordered because of chain dependencies (see
357 // below). Since call operands are dead, calls may continue to be added
358 // to the DefList making dependence checking quadratic in the size of
359 // the block. Instead, we leave only one call at the back of the
361 Reg2SUnitsMap::RangePair P = Defs.equal_range(Reg);
362 Reg2SUnitsMap::iterator B = P.first;
363 Reg2SUnitsMap::iterator I = P.second;
364 for (bool isBegin = I == B; !isBegin; /* empty */) {
365 isBegin = (--I) == B;
372 // Defs are pushed in the order they are visited and never reordered.
373 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));
377 /// addVRegDefDeps - Add register output and data dependencies from this SUnit
378 /// to instructions that occur later in the same scheduling region if they read
379 /// from or write to the virtual register defined at OperIdx.
381 /// TODO: Hoist loop induction variable increments. This has to be
382 /// reevaluated. Generally, IV scheduling should be done before coalescing.
383 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
384 const MachineInstr *MI = SU->getInstr();
385 unsigned Reg = MI->getOperand(OperIdx).getReg();
387 // Singly defined vregs do not have output/anti dependencies.
388 // The current operand is a def, so we have at least one.
389 // Check here if there are any others...
390 if (MRI.hasOneDef(Reg))
393 // Add output dependence to the next nearest def of this vreg.
395 // Unless this definition is dead, the output dependence should be
396 // transitively redundant with antidependencies from this definition's
397 // uses. We're conservative for now until we have a way to guarantee the uses
398 // are not eliminated sometime during scheduling. The output dependence edge
399 // is also useful if output latency exceeds def-use latency.
400 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
401 if (DefI == VRegDefs.end())
402 VRegDefs.insert(VReg2SUnit(Reg, SU));
404 SUnit *DefSU = DefI->SU;
405 if (DefSU != SU && DefSU != &ExitSU) {
406 SDep Dep(SU, SDep::Output, Reg);
408 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
415 /// addVRegUseDeps - Add a register data dependency if the instruction that
416 /// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
417 /// register antidependency from this SUnit to instructions that occur later in
418 /// the same scheduling region if they write the virtual register.
420 /// TODO: Handle ExitSU "uses" properly.
421 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
422 MachineInstr *MI = SU->getInstr();
423 unsigned Reg = MI->getOperand(OperIdx).getReg();
425 // Record this local VReg use.
426 VReg2UseMap::iterator UI = VRegUses.find(Reg);
427 for (; UI != VRegUses.end(); ++UI) {
431 if (UI == VRegUses.end())
432 VRegUses.insert(VReg2SUnit(Reg, SU));
434 // Lookup this operand's reaching definition.
435 assert(LIS && "vreg dependencies requires LiveIntervals");
437 = LIS->getInterval(Reg).Query(LIS->getInstructionIndex(MI));
438 VNInfo *VNI = LRQ.valueIn();
440 // VNI will be valid because MachineOperand::readsReg() is checked by caller.
441 assert(VNI && "No value to read by operand");
442 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
443 // Phis and other noninstructions (after coalescing) have a NULL Def.
445 SUnit *DefSU = getSUnit(Def);
447 // The reaching Def lives within this scheduling region.
448 // Create a data dependence.
449 SDep dep(DefSU, SDep::Data, Reg);
450 // Adjust the dependence latency using operand def/use information, then
451 // allow the target to perform its own adjustments.
452 int DefOp = Def->findRegisterDefOperandIdx(Reg);
453 dep.setLatency(SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx));
455 const TargetSubtargetInfo &ST = MF.getSubtarget();
456 ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
461 // Add antidependence to the following def of the vreg it uses.
462 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
463 if (DefI != VRegDefs.end() && DefI->SU != SU)
464 DefI->SU->addPred(SDep(SU, SDep::Anti, Reg));
467 /// Return true if MI is an instruction we are unable to reason about
468 /// (like a call or something with unmodeled side effects).
469 static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
470 if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
471 (MI->hasOrderedMemoryRef() &&
472 (!MI->mayLoad() || !MI->isInvariantLoad(AA))))
477 // This MI might have either incomplete info, or known to be unsafe
478 // to deal with (i.e. volatile object).
479 static inline bool isUnsafeMemoryObject(MachineInstr *MI,
480 const MachineFrameInfo *MFI,
481 const DataLayout &DL) {
482 if (!MI || MI->memoperands_empty())
484 // We purposefully do no check for hasOneMemOperand() here
485 // in hope to trigger an assert downstream in order to
486 // finish implementation.
487 if ((*MI->memoperands_begin())->isVolatile() ||
488 MI->hasUnmodeledSideEffects())
491 if ((*MI->memoperands_begin())->getPseudoValue()) {
492 // Similarly to getUnderlyingObjectForInstr:
493 // For now, ignore PseudoSourceValues which may alias LLVM IR values
494 // because the code that uses this function has no way to cope with
499 const Value *V = (*MI->memoperands_begin())->getValue();
503 SmallVector<Value *, 4> Objs;
504 getUnderlyingObjects(V, Objs, DL);
505 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(),
506 IE = Objs.end(); I != IE; ++I) {
507 // Does this pointer refer to a distinct and identifiable object?
508 if (!isIdentifiedObject(*I))
515 /// This returns true if the two MIs need a chain edge betwee them.
516 /// If these are not even memory operations, we still may need
517 /// chain deps between them. The question really is - could
518 /// these two MIs be reordered during scheduling from memory dependency
520 static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI,
521 const DataLayout &DL, MachineInstr *MIa,
523 const MachineFunction *MF = MIa->getParent()->getParent();
524 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
526 // Cover a trivial case - no edge is need to itself.
530 // Let the target decide if memory accesses cannot possibly overlap.
531 if ((MIa->mayLoad() || MIa->mayStore()) &&
532 (MIb->mayLoad() || MIb->mayStore()))
533 if (TII->areMemAccessesTriviallyDisjoint(MIa, MIb, AA))
536 // FIXME: Need to handle multiple memory operands to support all targets.
537 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())
540 if (isUnsafeMemoryObject(MIa, MFI, DL) || isUnsafeMemoryObject(MIb, MFI, DL))
543 // If we are dealing with two "normal" loads, we do not need an edge
544 // between them - they could be reordered.
545 if (!MIa->mayStore() && !MIb->mayStore())
548 // To this point analysis is generic. From here on we do need AA.
552 MachineMemOperand *MMOa = *MIa->memoperands_begin();
553 MachineMemOperand *MMOb = *MIb->memoperands_begin();
555 if (!MMOa->getValue() || !MMOb->getValue())
558 // The following interface to AA is fashioned after DAGCombiner::isAlias
559 // and operates with MachineMemOperand offset with some important
561 // - LLVM fundamentally assumes flat address spaces.
562 // - MachineOperand offset can *only* result from legalization and
563 // cannot affect queries other than the trivial case of overlap
565 // - These offsets never wrap and never step outside
566 // of allocated objects.
567 // - There should never be any negative offsets here.
569 // FIXME: Modify API to hide this math from "user"
570 // FIXME: Even before we go to AA we can reason locally about some
571 // memory objects. It can save compile time, and possibly catch some
572 // corner cases not currently covered.
574 assert ((MMOa->getOffset() >= 0) && "Negative MachineMemOperand offset");
575 assert ((MMOb->getOffset() >= 0) && "Negative MachineMemOperand offset");
577 int64_t MinOffset = std::min(MMOa->getOffset(), MMOb->getOffset());
578 int64_t Overlapa = MMOa->getSize() + MMOa->getOffset() - MinOffset;
579 int64_t Overlapb = MMOb->getSize() + MMOb->getOffset() - MinOffset;
581 AliasAnalysis::AliasResult AAResult = AA->alias(
582 AliasAnalysis::Location(MMOa->getValue(), Overlapa,
583 UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
584 AliasAnalysis::Location(MMOb->getValue(), Overlapb,
585 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
587 return (AAResult != AliasAnalysis::NoAlias);
590 /// This recursive function iterates over chain deps of SUb looking for
591 /// "latest" node that needs a chain edge to SUa.
592 static unsigned iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI,
593 const DataLayout &DL, SUnit *SUa, SUnit *SUb,
594 SUnit *ExitSU, unsigned *Depth,
595 SmallPtrSetImpl<const SUnit *> &Visited) {
596 if (!SUa || !SUb || SUb == ExitSU)
599 // Remember visited nodes.
600 if (!Visited.insert(SUb).second)
602 // If there is _some_ dependency already in place, do not
603 // descend any further.
604 // TODO: Need to make sure that if that dependency got eliminated or ignored
605 // for any reason in the future, we would not violate DAG topology.
606 // Currently it does not happen, but makes an implicit assumption about
607 // future implementation.
609 // Independently, if we encounter node that is some sort of global
610 // object (like a call) we already have full set of dependencies to it
611 // and we can stop descending.
612 if (SUa->isSucc(SUb) ||
613 isGlobalMemoryObject(AA, SUb->getInstr()))
616 // If we do need an edge, or we have exceeded depth budget,
617 // add that edge to the predecessors chain of SUb,
618 // and stop descending.
620 MIsNeedChainEdge(AA, MFI, DL, SUa->getInstr(), SUb->getInstr())) {
621 SUb->addPred(SDep(SUa, SDep::MayAliasMem));
624 // Track current depth.
626 // Iterate over memory dependencies only.
627 for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end();
629 if (I->isNormalMemoryOrBarrier())
630 iterateChainSucc(AA, MFI, DL, SUa, I->getSUnit(), ExitSU, Depth, Visited);
634 /// This function assumes that "downward" from SU there exist
635 /// tail/leaf of already constructed DAG. It iterates downward and
636 /// checks whether SU can be aliasing any node dominated
638 static void adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI,
639 const DataLayout &DL, SUnit *SU, SUnit *ExitSU,
640 std::set<SUnit *> &CheckList,
641 unsigned LatencyToLoad) {
645 SmallPtrSet<const SUnit*, 16> Visited;
648 for (std::set<SUnit *>::iterator I = CheckList.begin(), IE = CheckList.end();
652 if (MIsNeedChainEdge(AA, MFI, DL, SU->getInstr(), (*I)->getInstr())) {
653 SDep Dep(SU, SDep::MayAliasMem);
654 Dep.setLatency(((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0);
658 // Iterate recursively over all previously added memory chain
659 // successors. Keep track of visited nodes.
660 for (SUnit::const_succ_iterator J = (*I)->Succs.begin(),
661 JE = (*I)->Succs.end(); J != JE; ++J)
662 if (J->isNormalMemoryOrBarrier())
663 iterateChainSucc(AA, MFI, DL, SU, J->getSUnit(), ExitSU, &Depth,
668 /// Check whether two objects need a chain edge, if so, add it
669 /// otherwise remember the rejected SU.
670 static inline void addChainDependency(AliasAnalysis *AA,
671 const MachineFrameInfo *MFI,
672 const DataLayout &DL, SUnit *SUa,
673 SUnit *SUb, std::set<SUnit *> &RejectList,
674 unsigned TrueMemOrderLatency = 0,
675 bool isNormalMemory = false) {
676 // If this is a false dependency,
677 // do not add the edge, but rememeber the rejected node.
678 if (MIsNeedChainEdge(AA, MFI, DL, SUa->getInstr(), SUb->getInstr())) {
679 SDep Dep(SUa, isNormalMemory ? SDep::MayAliasMem : SDep::Barrier);
680 Dep.setLatency(TrueMemOrderLatency);
684 // Duplicate entries should be ignored.
685 RejectList.insert(SUb);
686 DEBUG(dbgs() << "\tReject chain dep between SU("
687 << SUa->NodeNum << ") and SU("
688 << SUb->NodeNum << ")\n");
692 /// Create an SUnit for each real instruction, numbered in top-down toplological
693 /// order. The instruction order A < B, implies that no edge exists from B to A.
695 /// Map each real instruction to its SUnit.
697 /// After initSUnits, the SUnits vector cannot be resized and the scheduler may
698 /// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
699 /// instead of pointers.
701 /// MachineScheduler relies on initSUnits numbering the nodes by their order in
702 /// the original instruction list.
703 void ScheduleDAGInstrs::initSUnits() {
704 // We'll be allocating one SUnit for each real instruction in the region,
705 // which is contained within a basic block.
706 SUnits.reserve(NumRegionInstrs);
708 for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) {
709 MachineInstr *MI = I;
710 if (MI->isDebugValue())
713 SUnit *SU = newSUnit(MI);
716 SU->isCall = MI->isCall();
717 SU->isCommutable = MI->isCommutable();
719 // Assign the Latency field of SU using target-provided information.
720 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
722 // If this SUnit uses a reserved or unbuffered resource, mark it as such.
724 // Reserved resources block an instruction from issuing and stall the
725 // entire pipeline. These are identified by BufferSize=0.
727 // Unbuffered resources prevent execution of subsequent instructions that
728 // require the same resources. This is used for in-order execution pipelines
729 // within an out-of-order core. These are identified by BufferSize=1.
730 if (SchedModel.hasInstrSchedModel()) {
731 const MCSchedClassDesc *SC = getSchedClass(SU);
732 for (TargetSchedModel::ProcResIter
733 PI = SchedModel.getWriteProcResBegin(SC),
734 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
735 switch (SchedModel.getProcResource(PI->ProcResourceIdx)->BufferSize) {
737 SU->hasReservedResource = true;
740 SU->isUnbuffered = true;
750 /// If RegPressure is non-null, compute register pressure as a side effect. The
751 /// DAG builder is an efficient place to do it because it already visits
753 void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
754 RegPressureTracker *RPTracker,
755 PressureDiffs *PDiffs) {
756 const TargetSubtargetInfo &ST = MF.getSubtarget();
757 bool UseAA = EnableAASchedMI.getNumOccurrences() > 0 ? EnableAASchedMI
759 AliasAnalysis *AAForDep = UseAA ? AA : nullptr;
762 ScheduleDAG::clearDAG();
764 // Create an SUnit for each real instruction.
768 PDiffs->init(SUnits.size());
770 // We build scheduling units by walking a block's instruction list from bottom
773 // Remember where a generic side-effecting instruction is as we procede.
774 SUnit *BarrierChain = nullptr, *AliasChain = nullptr;
776 // Memory references to specific known memory locations are tracked
777 // so that they can be given more precise dependencies. We track
778 // separately the known memory locations that may alias and those
779 // that are known not to alias
780 MapVector<ValueType, std::vector<SUnit *> > AliasMemDefs, NonAliasMemDefs;
781 MapVector<ValueType, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
782 std::set<SUnit*> RejectMemNodes;
784 // Remove any stale debug info; sometimes BuildSchedGraph is called again
785 // without emitting the info from the previous call.
787 FirstDbgValue = nullptr;
789 assert(Defs.empty() && Uses.empty() &&
790 "Only BuildGraph should update Defs/Uses");
791 Defs.setUniverse(TRI->getNumRegs());
792 Uses.setUniverse(TRI->getNumRegs());
794 assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs");
796 VRegDefs.setUniverse(MRI.getNumVirtRegs());
797 VRegUses.setUniverse(MRI.getNumVirtRegs());
799 // Model data dependencies between instructions being scheduled and the
801 addSchedBarrierDeps();
803 // Walk the list of instructions, from bottom moving up.
804 MachineInstr *DbgMI = nullptr;
805 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
807 MachineInstr *MI = std::prev(MII);
809 DbgValues.push_back(std::make_pair(DbgMI, MI));
813 if (MI->isDebugValue()) {
817 SUnit *SU = MISUnitMap[MI];
818 assert(SU && "No SUnit mapped to this MI");
821 PressureDiff *PDiff = PDiffs ? &(*PDiffs)[SU->NodeNum] : nullptr;
822 RPTracker->recede(/*LiveUses=*/nullptr, PDiff);
823 assert(RPTracker->getPos() == std::prev(MII) &&
824 "RPTracker can't find MI");
828 (CanHandleTerminators || (!MI->isTerminator() && !MI->isPosition())) &&
829 "Cannot schedule terminators or labels!");
831 // Add register-based dependencies (data, anti, and output).
832 bool HasVRegDef = false;
833 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
834 const MachineOperand &MO = MI->getOperand(j);
835 if (!MO.isReg()) continue;
836 unsigned Reg = MO.getReg();
837 if (Reg == 0) continue;
839 if (TRI->isPhysicalRegister(Reg))
840 addPhysRegDeps(SU, j);
842 assert(!IsPostRA && "Virtual register encountered!");
845 addVRegDefDeps(SU, j);
847 else if (MO.readsReg()) // ignore undef operands
848 addVRegUseDeps(SU, j);
851 // If we haven't seen any uses in this scheduling region, create a
852 // dependence edge to ExitSU to model the live-out latency. This is required
853 // for vreg defs with no in-region use, and prefetches with no vreg def.
855 // FIXME: NumDataSuccs would be more precise than NumSuccs here. This
856 // check currently relies on being called before adding chain deps.
857 if (SU->NumSuccs == 0 && SU->Latency > 1
858 && (HasVRegDef || MI->mayLoad())) {
859 SDep Dep(SU, SDep::Artificial);
860 Dep.setLatency(SU->Latency - 1);
864 // Add chain dependencies.
865 // Chain dependencies used to enforce memory order should have
866 // latency of 0 (except for true dependency of Store followed by
867 // aliased Load... we estimate that with a single cycle of latency
868 // assuming the hardware will bypass)
869 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
870 // after stack slots are lowered to actual addresses.
871 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and
872 // produce more precise dependence information.
873 unsigned TrueMemOrderLatency = MI->mayStore() ? 1 : 0;
874 if (isGlobalMemoryObject(AA, MI)) {
875 // Be conservative with these and add dependencies on all memory
876 // references, even those that are known to not alias.
877 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
878 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
879 for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
880 I->second[i]->addPred(SDep(SU, SDep::Barrier));
883 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
884 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
885 for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
886 SDep Dep(SU, SDep::Barrier);
887 Dep.setLatency(TrueMemOrderLatency);
888 I->second[i]->addPred(Dep);
891 // Add SU to the barrier chain.
893 BarrierChain->addPred(SDep(SU, SDep::Barrier));
895 // This is a barrier event that acts as a pivotal node in the DAG,
896 // so it is safe to clear list of exposed nodes.
897 adjustChainDeps(AA, MFI, *TM.getDataLayout(), SU, &ExitSU, RejectMemNodes,
898 TrueMemOrderLatency);
899 RejectMemNodes.clear();
900 NonAliasMemDefs.clear();
901 NonAliasMemUses.clear();
905 // Chain all possibly aliasing memory references through SU.
907 unsigned ChainLatency = 0;
908 if (AliasChain->getInstr()->mayLoad())
909 ChainLatency = TrueMemOrderLatency;
910 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU, AliasChain,
911 RejectMemNodes, ChainLatency);
914 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
915 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
916 PendingLoads[k], RejectMemNodes,
917 TrueMemOrderLatency);
918 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
919 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I) {
920 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
921 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
922 I->second[i], RejectMemNodes);
924 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
925 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
926 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
927 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
928 I->second[i], RejectMemNodes, TrueMemOrderLatency);
930 adjustChainDeps(AA, MFI, *TM.getDataLayout(), SU, &ExitSU, RejectMemNodes,
931 TrueMemOrderLatency);
932 PendingLoads.clear();
933 AliasMemDefs.clear();
934 AliasMemUses.clear();
935 } else if (MI->mayStore()) {
936 // Add dependence on barrier chain, if needed.
937 // There is no point to check aliasing on barrier event. Even if
938 // SU and barrier _could_ be reordered, they should not. In addition,
939 // we have lost all RejectMemNodes below barrier.
941 BarrierChain->addPred(SDep(SU, SDep::Barrier));
943 UnderlyingObjectsVector Objs;
944 getUnderlyingObjectsForInstr(MI, MFI, Objs, *TM.getDataLayout());
947 // Treat all other stores conservatively.
948 goto new_alias_chain;
951 bool MayAlias = false;
952 for (UnderlyingObjectsVector::iterator K = Objs.begin(), KE = Objs.end();
954 ValueType V = K->getPointer();
955 bool ThisMayAlias = K->getInt();
959 // A store to a specific PseudoSourceValue. Add precise dependencies.
960 // Record the def in MemDefs, first adding a dep if there is
962 MapVector<ValueType, std::vector<SUnit *> >::iterator I =
963 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
964 MapVector<ValueType, std::vector<SUnit *> >::iterator IE =
965 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
967 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
968 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
969 I->second[i], RejectMemNodes, 0, true);
971 // If we're not using AA, then we only need one store per object.
974 I->second.push_back(SU);
978 AliasMemDefs[V].clear();
979 AliasMemDefs[V].push_back(SU);
982 NonAliasMemDefs[V].clear();
983 NonAliasMemDefs[V].push_back(SU);
986 // Handle the uses in MemUses, if there are any.
987 MapVector<ValueType, std::vector<SUnit *> >::iterator J =
988 ((ThisMayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
989 MapVector<ValueType, std::vector<SUnit *> >::iterator JE =
990 ((ThisMayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
992 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
993 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
994 J->second[i], RejectMemNodes,
995 TrueMemOrderLatency, true);
1000 // Add dependencies from all the PendingLoads, i.e. loads
1001 // with no underlying object.
1002 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
1003 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
1004 PendingLoads[k], RejectMemNodes,
1005 TrueMemOrderLatency);
1006 // Add dependence on alias chain, if needed.
1008 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU, AliasChain,
1011 adjustChainDeps(AA, MFI, *TM.getDataLayout(), SU, &ExitSU, RejectMemNodes,
1012 TrueMemOrderLatency);
1013 } else if (MI->mayLoad()) {
1014 bool MayAlias = true;
1015 if (MI->isInvariantLoad(AA)) {
1016 // Invariant load, no chain dependencies needed!
1018 UnderlyingObjectsVector Objs;
1019 getUnderlyingObjectsForInstr(MI, MFI, Objs, *TM.getDataLayout());
1022 // A load with no underlying object. Depend on all
1023 // potentially aliasing stores.
1024 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
1025 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
1026 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1027 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
1028 I->second[i], RejectMemNodes);
1030 PendingLoads.push_back(SU);
1036 for (UnderlyingObjectsVector::iterator
1037 J = Objs.begin(), JE = Objs.end(); J != JE; ++J) {
1038 ValueType V = J->getPointer();
1039 bool ThisMayAlias = J->getInt();
1044 // A load from a specific PseudoSourceValue. Add precise dependencies.
1045 MapVector<ValueType, std::vector<SUnit *> >::iterator I =
1046 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
1047 MapVector<ValueType, std::vector<SUnit *> >::iterator IE =
1048 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
1050 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1051 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
1052 I->second[i], RejectMemNodes, 0, true);
1054 AliasMemUses[V].push_back(SU);
1056 NonAliasMemUses[V].push_back(SU);
1059 adjustChainDeps(AA, MFI, *TM.getDataLayout(), SU, &ExitSU,
1060 RejectMemNodes, /*Latency=*/0);
1061 // Add dependencies on alias and barrier chains, if needed.
1062 if (MayAlias && AliasChain)
1063 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU, AliasChain,
1066 BarrierChain->addPred(SDep(SU, SDep::Barrier));
1071 FirstDbgValue = DbgMI;
1076 PendingLoads.clear();
1079 /// \brief Initialize register live-range state for updating kills.
1080 void ScheduleDAGInstrs::startBlockForKills(MachineBasicBlock *BB) {
1081 // Start with no live registers.
1084 // Examine the live-in regs of all successors.
1085 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
1086 SE = BB->succ_end(); SI != SE; ++SI) {
1087 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
1088 E = (*SI)->livein_end(); I != E; ++I) {
1090 // Repeat, for reg and all subregs.
1091 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1092 SubRegs.isValid(); ++SubRegs)
1093 LiveRegs.set(*SubRegs);
1098 /// \brief If we change a kill flag on the bundle instruction implicit register
1099 /// operands, then we also need to propagate that to any instructions inside
1100 /// the bundle which had the same kill state.
1101 static void toggleBundleKillFlag(MachineInstr *MI, unsigned Reg,
1102 bool NewKillState) {
1103 if (MI->getOpcode() != TargetOpcode::BUNDLE)
1106 // Walk backwards from the last instruction in the bundle to the first.
1107 // Once we set a kill flag on an instruction, we bail out, as otherwise we
1108 // might set it on too many operands. We will clear as many flags as we
1110 MachineBasicBlock::instr_iterator Begin = MI;
1111 MachineBasicBlock::instr_iterator End = getBundleEnd(MI);
1112 while (Begin != End) {
1113 for (MIOperands MO(--End); MO.isValid(); ++MO) {
1114 if (!MO->isReg() || MO->isDef() || Reg != MO->getReg())
1117 // DEBUG_VALUE nodes do not contribute to code generation and should
1118 // always be ignored. Failure to do so may result in trying to modify
1119 // KILL flags on DEBUG_VALUE nodes, which is distressing.
1123 // If the register has the internal flag then it could be killing an
1124 // internal def of the register. In this case, just skip. We only want
1125 // to toggle the flag on operands visible outside the bundle.
1126 if (MO->isInternalRead())
1129 if (MO->isKill() == NewKillState)
1131 MO->setIsKill(NewKillState);
1138 bool ScheduleDAGInstrs::toggleKillFlag(MachineInstr *MI, MachineOperand &MO) {
1139 // Setting kill flag...
1142 toggleBundleKillFlag(MI, MO.getReg(), true);
1146 // If MO itself is live, clear the kill flag...
1147 if (LiveRegs.test(MO.getReg())) {
1148 MO.setIsKill(false);
1149 toggleBundleKillFlag(MI, MO.getReg(), false);
1153 // If any subreg of MO is live, then create an imp-def for that
1154 // subreg and keep MO marked as killed.
1155 MO.setIsKill(false);
1156 toggleBundleKillFlag(MI, MO.getReg(), false);
1157 bool AllDead = true;
1158 const unsigned SuperReg = MO.getReg();
1159 MachineInstrBuilder MIB(MF, MI);
1160 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
1161 if (LiveRegs.test(*SubRegs)) {
1162 MIB.addReg(*SubRegs, RegState::ImplicitDefine);
1169 toggleBundleKillFlag(MI, MO.getReg(), true);
1174 // FIXME: Reuse the LivePhysRegs utility for this.
1175 void ScheduleDAGInstrs::fixupKills(MachineBasicBlock *MBB) {
1176 DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
1178 LiveRegs.resize(TRI->getNumRegs());
1179 BitVector killedRegs(TRI->getNumRegs());
1181 startBlockForKills(MBB);
1183 // Examine block from end to start...
1184 unsigned Count = MBB->size();
1185 for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
1187 MachineInstr *MI = --I;
1188 if (MI->isDebugValue())
1191 // Update liveness. Registers that are defed but not used in this
1192 // instruction are now dead. Mark register and all subregs as they
1193 // are completely defined.
1194 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1195 MachineOperand &MO = MI->getOperand(i);
1197 LiveRegs.clearBitsNotInMask(MO.getRegMask());
1198 if (!MO.isReg()) continue;
1199 unsigned Reg = MO.getReg();
1200 if (Reg == 0) continue;
1201 if (!MO.isDef()) continue;
1202 // Ignore two-addr defs.
1203 if (MI->isRegTiedToUseOperand(i)) continue;
1205 // Repeat for reg and all subregs.
1206 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1207 SubRegs.isValid(); ++SubRegs)
1208 LiveRegs.reset(*SubRegs);
1211 // Examine all used registers and set/clear kill flag. When a
1212 // register is used multiple times we only set the kill flag on
1213 // the first use. Don't set kill flags on undef operands.
1215 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1216 MachineOperand &MO = MI->getOperand(i);
1217 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
1218 unsigned Reg = MO.getReg();
1219 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1222 if (!killedRegs.test(Reg)) {
1224 // A register is not killed if any subregs are live...
1225 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
1226 if (LiveRegs.test(*SubRegs)) {
1232 // If subreg is not live, then register is killed if it became
1233 // live in this instruction
1235 kill = !LiveRegs.test(Reg);
1238 if (MO.isKill() != kill) {
1239 DEBUG(dbgs() << "Fixing " << MO << " in ");
1240 // Warning: toggleKillFlag may invalidate MO.
1241 toggleKillFlag(MI, MO);
1243 DEBUG(if (MI->getOpcode() == TargetOpcode::BUNDLE) {
1244 MachineBasicBlock::instr_iterator Begin = MI;
1245 MachineBasicBlock::instr_iterator End = getBundleEnd(MI);
1246 while (++Begin != End)
1247 DEBUG(Begin->dump());
1251 killedRegs.set(Reg);
1254 // Mark any used register (that is not using undef) and subregs as
1256 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1257 MachineOperand &MO = MI->getOperand(i);
1258 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
1259 unsigned Reg = MO.getReg();
1260 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1262 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1263 SubRegs.isValid(); ++SubRegs)
1264 LiveRegs.set(*SubRegs);
1269 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
1270 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1271 SU->getInstr()->dump();
1275 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1277 raw_string_ostream oss(s);
1280 else if (SU == &ExitSU)
1283 SU->getInstr()->print(oss, /*SkipOpers=*/true);
1287 /// Return the basic block label. It is not necessarilly unique because a block
1288 /// contains multiple scheduling regions. But it is fine for visualization.
1289 std::string ScheduleDAGInstrs::getDAGName() const {
1290 return "dag." + BB->getFullName();
1293 //===----------------------------------------------------------------------===//
1294 // SchedDFSResult Implementation
1295 //===----------------------------------------------------------------------===//
1298 /// \brief Internal state used to compute SchedDFSResult.
1299 class SchedDFSImpl {
1302 /// Join DAG nodes into equivalence classes by their subtree.
1303 IntEqClasses SubtreeClasses;
1304 /// List PredSU, SuccSU pairs that represent data edges between subtrees.
1305 std::vector<std::pair<const SUnit*, const SUnit*> > ConnectionPairs;
1309 unsigned ParentNodeID; // Parent node (member of the parent subtree).
1310 unsigned SubInstrCount; // Instr count in this tree only, not children.
1312 RootData(unsigned id): NodeID(id),
1313 ParentNodeID(SchedDFSResult::InvalidSubtreeID),
1316 unsigned getSparseSetIndex() const { return NodeID; }
1319 SparseSet<RootData> RootSet;
1322 SchedDFSImpl(SchedDFSResult &r): R(r), SubtreeClasses(R.DFSNodeData.size()) {
1323 RootSet.setUniverse(R.DFSNodeData.size());
1326 /// Return true if this node been visited by the DFS traversal.
1328 /// During visitPostorderNode the Node's SubtreeID is assigned to the Node
1329 /// ID. Later, SubtreeID is updated but remains valid.
1330 bool isVisited(const SUnit *SU) const {
1331 return R.DFSNodeData[SU->NodeNum].SubtreeID
1332 != SchedDFSResult::InvalidSubtreeID;
1335 /// Initialize this node's instruction count. We don't need to flag the node
1336 /// visited until visitPostorder because the DAG cannot have cycles.
1337 void visitPreorder(const SUnit *SU) {
1338 R.DFSNodeData[SU->NodeNum].InstrCount =
1339 SU->getInstr()->isTransient() ? 0 : 1;
1342 /// Called once for each node after all predecessors are visited. Revisit this
1343 /// node's predecessors and potentially join them now that we know the ILP of
1344 /// the other predecessors.
1345 void visitPostorderNode(const SUnit *SU) {
1346 // Mark this node as the root of a subtree. It may be joined with its
1347 // successors later.
1348 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
1349 RootData RData(SU->NodeNum);
1350 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
1352 // If any predecessors are still in their own subtree, they either cannot be
1353 // joined or are large enough to remain separate. If this parent node's
1354 // total instruction count is not greater than a child subtree by at least
1355 // the subtree limit, then try to join it now since splitting subtrees is
1356 // only useful if multiple high-pressure paths are possible.
1357 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
1358 for (SUnit::const_pred_iterator
1359 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1360 if (PI->getKind() != SDep::Data)
1362 unsigned PredNum = PI->getSUnit()->NodeNum;
1363 if ((InstrCount - R.DFSNodeData[PredNum].InstrCount) < R.SubtreeLimit)
1364 joinPredSubtree(*PI, SU, /*CheckLimit=*/false);
1366 // Either link or merge the TreeData entry from the child to the parent.
1367 if (R.DFSNodeData[PredNum].SubtreeID == PredNum) {
1368 // If the predecessor's parent is invalid, this is a tree edge and the
1369 // current node is the parent.
1370 if (RootSet[PredNum].ParentNodeID == SchedDFSResult::InvalidSubtreeID)
1371 RootSet[PredNum].ParentNodeID = SU->NodeNum;
1373 else if (RootSet.count(PredNum)) {
1374 // The predecessor is not a root, but is still in the root set. This
1375 // must be the new parent that it was just joined to. Note that
1376 // RootSet[PredNum].ParentNodeID may either be invalid or may still be
1377 // set to the original parent.
1378 RData.SubInstrCount += RootSet[PredNum].SubInstrCount;
1379 RootSet.erase(PredNum);
1382 RootSet[SU->NodeNum] = RData;
1385 /// Called once for each tree edge after calling visitPostOrderNode on the
1386 /// predecessor. Increment the parent node's instruction count and
1387 /// preemptively join this subtree to its parent's if it is small enough.
1388 void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ) {
1389 R.DFSNodeData[Succ->NodeNum].InstrCount
1390 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount;
1391 joinPredSubtree(PredDep, Succ);
1394 /// Add a connection for cross edges.
1395 void visitCrossEdge(const SDep &PredDep, const SUnit *Succ) {
1396 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ));
1399 /// Set each node's subtree ID to the representative ID and record connections
1402 SubtreeClasses.compress();
1403 R.DFSTreeData.resize(SubtreeClasses.getNumClasses());
1404 assert(SubtreeClasses.getNumClasses() == RootSet.size()
1405 && "number of roots should match trees");
1406 for (SparseSet<RootData>::const_iterator
1407 RI = RootSet.begin(), RE = RootSet.end(); RI != RE; ++RI) {
1408 unsigned TreeID = SubtreeClasses[RI->NodeID];
1409 if (RI->ParentNodeID != SchedDFSResult::InvalidSubtreeID)
1410 R.DFSTreeData[TreeID].ParentTreeID = SubtreeClasses[RI->ParentNodeID];
1411 R.DFSTreeData[TreeID].SubInstrCount = RI->SubInstrCount;
1412 // Note that SubInstrCount may be greater than InstrCount if we joined
1413 // subtrees across a cross edge. InstrCount will be attributed to the
1414 // original parent, while SubInstrCount will be attributed to the joined
1417 R.SubtreeConnections.resize(SubtreeClasses.getNumClasses());
1418 R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses());
1419 DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n");
1420 for (unsigned Idx = 0, End = R.DFSNodeData.size(); Idx != End; ++Idx) {
1421 R.DFSNodeData[Idx].SubtreeID = SubtreeClasses[Idx];
1422 DEBUG(dbgs() << " SU(" << Idx << ") in tree "
1423 << R.DFSNodeData[Idx].SubtreeID << '\n');
1425 for (std::vector<std::pair<const SUnit*, const SUnit*> >::const_iterator
1426 I = ConnectionPairs.begin(), E = ConnectionPairs.end();
1428 unsigned PredTree = SubtreeClasses[I->first->NodeNum];
1429 unsigned SuccTree = SubtreeClasses[I->second->NodeNum];
1430 if (PredTree == SuccTree)
1432 unsigned Depth = I->first->getDepth();
1433 addConnection(PredTree, SuccTree, Depth);
1434 addConnection(SuccTree, PredTree, Depth);
1439 /// Join the predecessor subtree with the successor that is its DFS
1440 /// parent. Apply some heuristics before joining.
1441 bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ,
1442 bool CheckLimit = true) {
1443 assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges");
1445 // Check if the predecessor is already joined.
1446 const SUnit *PredSU = PredDep.getSUnit();
1447 unsigned PredNum = PredSU->NodeNum;
1448 if (R.DFSNodeData[PredNum].SubtreeID != PredNum)
1451 // Four is the magic number of successors before a node is considered a
1453 unsigned NumDataSucs = 0;
1454 for (SUnit::const_succ_iterator SI = PredSU->Succs.begin(),
1455 SE = PredSU->Succs.end(); SI != SE; ++SI) {
1456 if (SI->getKind() == SDep::Data) {
1457 if (++NumDataSucs >= 4)
1461 if (CheckLimit && R.DFSNodeData[PredNum].InstrCount > R.SubtreeLimit)
1463 R.DFSNodeData[PredNum].SubtreeID = Succ->NodeNum;
1464 SubtreeClasses.join(Succ->NodeNum, PredNum);
1468 /// Called by finalize() to record a connection between trees.
1469 void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth) {
1474 SmallVectorImpl<SchedDFSResult::Connection> &Connections =
1475 R.SubtreeConnections[FromTree];
1476 for (SmallVectorImpl<SchedDFSResult::Connection>::iterator
1477 I = Connections.begin(), E = Connections.end(); I != E; ++I) {
1478 if (I->TreeID == ToTree) {
1479 I->Level = std::max(I->Level, Depth);
1483 Connections.push_back(SchedDFSResult::Connection(ToTree, Depth));
1484 FromTree = R.DFSTreeData[FromTree].ParentTreeID;
1485 } while (FromTree != SchedDFSResult::InvalidSubtreeID);
1491 /// \brief Manage the stack used by a reverse depth-first search over the DAG.
1492 class SchedDAGReverseDFS {
1493 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack;
1495 bool isComplete() const { return DFSStack.empty(); }
1497 void follow(const SUnit *SU) {
1498 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
1500 void advance() { ++DFSStack.back().second; }
1502 const SDep *backtrack() {
1503 DFSStack.pop_back();
1504 return DFSStack.empty() ? nullptr : std::prev(DFSStack.back().second);
1507 const SUnit *getCurr() const { return DFSStack.back().first; }
1509 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; }
1511 SUnit::const_pred_iterator getPredEnd() const {
1512 return getCurr()->Preds.end();
1517 static bool hasDataSucc(const SUnit *SU) {
1518 for (SUnit::const_succ_iterator
1519 SI = SU->Succs.begin(), SE = SU->Succs.end(); SI != SE; ++SI) {
1520 if (SI->getKind() == SDep::Data && !SI->getSUnit()->isBoundaryNode())
1526 /// Compute an ILP metric for all nodes in the subDAG reachable via depth-first
1527 /// search from this root.
1528 void SchedDFSResult::compute(ArrayRef<SUnit> SUnits) {
1530 llvm_unreachable("Top-down ILP metric is unimplemnted");
1532 SchedDFSImpl Impl(*this);
1533 for (ArrayRef<SUnit>::const_iterator
1534 SI = SUnits.begin(), SE = SUnits.end(); SI != SE; ++SI) {
1535 const SUnit *SU = &*SI;
1536 if (Impl.isVisited(SU) || hasDataSucc(SU))
1539 SchedDAGReverseDFS DFS;
1540 Impl.visitPreorder(SU);
1543 // Traverse the leftmost path as far as possible.
1544 while (DFS.getPred() != DFS.getPredEnd()) {
1545 const SDep &PredDep = *DFS.getPred();
1547 // Ignore non-data edges.
1548 if (PredDep.getKind() != SDep::Data
1549 || PredDep.getSUnit()->isBoundaryNode()) {
1552 // An already visited edge is a cross edge, assuming an acyclic DAG.
1553 if (Impl.isVisited(PredDep.getSUnit())) {
1554 Impl.visitCrossEdge(PredDep, DFS.getCurr());
1557 Impl.visitPreorder(PredDep.getSUnit());
1558 DFS.follow(PredDep.getSUnit());
1560 // Visit the top of the stack in postorder and backtrack.
1561 const SUnit *Child = DFS.getCurr();
1562 const SDep *PredDep = DFS.backtrack();
1563 Impl.visitPostorderNode(Child);
1565 Impl.visitPostorderEdge(*PredDep, DFS.getCurr());
1566 if (DFS.isComplete())
1573 /// The root of the given SubtreeID was just scheduled. For all subtrees
1574 /// connected to this tree, record the depth of the connection so that the
1575 /// nearest connected subtrees can be prioritized.
1576 void SchedDFSResult::scheduleTree(unsigned SubtreeID) {
1577 for (SmallVectorImpl<Connection>::const_iterator
1578 I = SubtreeConnections[SubtreeID].begin(),
1579 E = SubtreeConnections[SubtreeID].end(); I != E; ++I) {
1580 SubtreeConnectLevels[I->TreeID] =
1581 std::max(SubtreeConnectLevels[I->TreeID], I->Level);
1582 DEBUG(dbgs() << " Tree: " << I->TreeID
1583 << " @" << SubtreeConnectLevels[I->TreeID] << '\n');
1588 void ILPValue::print(raw_ostream &OS) const {
1589 OS << InstrCount << " / " << Length << " = ";
1593 OS << format("%g", ((double)InstrCount / Length));
1597 void ILPValue::dump() const {
1598 dbgs() << *this << '\n';
1604 raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) {