1 //===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine register scavenger. It can provide
11 // information, such as unused registers, at any point in a machine basic block.
12 // It also provides a mechanism to make registers available by evicting them to
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "reg-scavenging"
18 #include "llvm/CodeGen/RegisterScavenging.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/ADT/STLExtras.h"
28 /// RedefinesSuperRegPart - Return true if the specified register is redefining
29 /// part of a super-register.
30 static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
31 const TargetRegisterInfo *TRI) {
32 bool SeenSuperUse = false;
33 bool SeenSuperDef = false;
34 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
35 const MachineOperand &MO = MI->getOperand(i);
38 if (TRI->isSuperRegister(SubReg, MO.getReg()))
41 else if (MO.isImplicit())
45 return SeenSuperDef && SeenSuperUse;
48 static bool RedefinesSuperRegPart(const MachineInstr *MI,
49 const MachineOperand &MO,
50 const TargetRegisterInfo *TRI) {
51 assert(MO.isRegister() && MO.isDef() && "Not a register def!");
52 return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
55 /// setUsed - Set the register and its sub-registers as being used.
56 void RegScavenger::setUsed(unsigned Reg) {
57 RegsAvailable.reset(Reg);
59 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
60 unsigned SubReg = *SubRegs; ++SubRegs)
61 RegsAvailable.reset(SubReg);
64 /// setUnused - Set the register and its sub-registers as being unused.
65 void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
66 RegsAvailable.set(Reg);
68 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
69 unsigned SubReg = *SubRegs; ++SubRegs)
70 if (!RedefinesSuperRegPart(MI, Reg, TRI))
71 RegsAvailable.set(SubReg);
74 void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
75 const MachineFunction &MF = *mbb->getParent();
76 const TargetMachine &TM = MF.getTarget();
77 TII = TM.getInstrInfo();
78 TRI = TM.getRegisterInfo();
80 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
84 NumPhysRegs = TRI->getNumRegs();
85 RegsAvailable.resize(NumPhysRegs);
87 // Create reserved registers bitvector.
88 ReservedRegs = TRI->getReservedRegs(MF);
90 // Create callee-saved registers bitvector.
91 CalleeSavedRegs.resize(NumPhysRegs);
92 const unsigned *CSRegs = TRI->getCalleeSavedRegs();
94 for (unsigned i = 0; CSRegs[i]; ++i)
95 CalleeSavedRegs.set(CSRegs[i]);
102 // All registers started out unused.
105 // Reserved registers are always used.
106 RegsAvailable ^= ReservedRegs;
108 // Live-in registers are in use.
109 if (!MBB->livein_empty())
110 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
111 E = MBB->livein_end(); I != E; ++I)
117 void RegScavenger::restoreScavengedReg() {
121 TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
122 ScavengingFrameIndex, ScavengedRC);
123 MachineBasicBlock::iterator II = prior(MBBI);
124 TRI->eliminateFrameIndex(II, 0, this);
125 setUsed(ScavengedReg);
130 void RegScavenger::forward() {
136 assert(MBBI != MBB->end() && "Already at the end of the basic block!");
140 MachineInstr *MI = MBBI;
141 const TargetInstrDesc &TID = MI->getDesc();
143 // Reaching a terminator instruction. Restore a scavenged register (which
145 if (TID.isTerminator())
146 restoreScavengedReg();
148 // Process uses first.
149 BitVector ChangedRegs(NumPhysRegs);
150 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
151 const MachineOperand &MO = MI->getOperand(i);
152 if (!MO.isRegister() || !MO.isUse())
155 unsigned Reg = MO.getReg();
156 if (Reg == 0) continue;
159 // Register has been scavenged. Restore it!
160 if (Reg != ScavengedReg)
161 assert(false && "Using an undefined register!");
163 restoreScavengedReg();
166 if (MO.isKill() && !isReserved(Reg)) {
167 ChangedRegs.set(Reg);
169 // Mark sub-registers as changed if they aren't defined in the same
171 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
172 unsigned SubReg = *SubRegs; ++SubRegs)
173 ChangedRegs.set(SubReg);
177 // Change states of all registers after all the uses are processed to guard
178 // against multiple uses.
179 setUnused(ChangedRegs);
182 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
183 const MachineOperand &MO = MI->getOperand(i);
185 if (!MO.isRegister() || !MO.isDef())
188 unsigned Reg = MO.getReg();
190 // If it's dead upon def, then it is now free.
196 // Skip two-address destination operand.
197 if (TID.findTiedToSrcOperand(i) != -1) {
198 assert(isUsed(Reg) && "Using an undefined register!");
202 // Skip is this is merely redefining part of a super-register.
203 if (RedefinesSuperRegPart(MI, MO, TRI))
206 assert((isUnused(Reg) || isReserved(Reg)) &&
207 "Re-defining a live register!");
212 void RegScavenger::backward() {
213 assert(Tracking && "Not tracking states!");
214 assert(MBBI != MBB->begin() && "Already at start of basic block!");
215 // Move ptr backward.
218 MachineInstr *MI = MBBI;
219 // Process defs first.
220 const TargetInstrDesc &TID = MI->getDesc();
221 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
222 const MachineOperand &MO = MI->getOperand(i);
223 if (!MO.isRegister() || !MO.isDef())
225 // Skip two-address destination operand.
226 if (TID.findTiedToSrcOperand(i) != -1)
228 unsigned Reg = MO.getReg();
230 if (!isReserved(Reg))
235 BitVector ChangedRegs(NumPhysRegs);
236 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
237 const MachineOperand &MO = MI->getOperand(i);
238 if (!MO.isRegister() || !MO.isUse())
240 unsigned Reg = MO.getReg();
243 assert(isUnused(Reg) || isReserved(Reg));
244 ChangedRegs.set(Reg);
246 // Set the sub-registers as "used".
247 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
248 unsigned SubReg = *SubRegs; ++SubRegs)
249 ChangedRegs.set(SubReg);
251 setUsed(ChangedRegs);
254 void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
256 used = ~RegsAvailable;
258 used = ~RegsAvailable & ~ReservedRegs;
261 /// CreateRegClassMask - Set the bits that represent the registers in the
262 /// TargetRegisterClass.
263 static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
264 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
269 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
270 const BitVector &Candidates) const {
271 // Mask off the registers which are not in the TargetRegisterClass.
272 BitVector RegsAvailableCopy(NumPhysRegs, false);
273 CreateRegClassMask(RegClass, RegsAvailableCopy);
274 RegsAvailableCopy &= RegsAvailable;
276 // Restrict the search to candidates.
277 RegsAvailableCopy &= Candidates;
279 // Returns the first unused (bit is set) register, or 0 is none is found.
280 int Reg = RegsAvailableCopy.find_first();
281 return (Reg == -1) ? 0 : Reg;
284 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
285 bool ExCalleeSaved) const {
286 // Mask off the registers which are not in the TargetRegisterClass.
287 BitVector RegsAvailableCopy(NumPhysRegs, false);
288 CreateRegClassMask(RegClass, RegsAvailableCopy);
289 RegsAvailableCopy &= RegsAvailable;
291 // If looking for a non-callee-saved register, mask off all the callee-saved
294 RegsAvailableCopy &= ~CalleeSavedRegs;
296 // Returns the first unused (bit is set) register, or 0 is none is found.
297 int Reg = RegsAvailableCopy.find_first();
298 return (Reg == -1) ? 0 : Reg;
301 /// calcDistanceToUse - Calculate the distance to the first use of the
302 /// specified register.
303 static unsigned calcDistanceToUse(MachineBasicBlock *MBB,
304 MachineBasicBlock::iterator I, unsigned Reg,
305 const TargetRegisterInfo *TRI) {
308 while (I != MBB->end()) {
310 if (I->readsRegister(Reg, TRI))
317 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
318 MachineBasicBlock::iterator I,
320 assert(ScavengingFrameIndex >= 0 &&
321 "Cannot scavenge a register without an emergency spill slot!");
323 // Mask off the registers which are not in the TargetRegisterClass.
324 BitVector Candidates(NumPhysRegs, false);
325 CreateRegClassMask(RC, Candidates);
326 Candidates ^= ReservedRegs; // Do not include reserved registers.
328 // Exclude all the registers being used by the instruction.
329 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
330 MachineOperand &MO = I->getOperand(i);
332 Candidates.reset(MO.getReg());
335 // Find the register whose use is furthest away.
337 unsigned MaxDist = 0;
338 int Reg = Candidates.find_first();
340 unsigned Dist = calcDistanceToUse(MBB, I, Reg, TRI);
341 if (Dist >= MaxDist) {
345 Reg = Candidates.find_next(Reg);
348 if (ScavengedReg != 0) {
349 // First restore previously scavenged register.
350 TII->loadRegFromStackSlot(*MBB, I, ScavengedReg,
351 ScavengingFrameIndex, ScavengedRC);
352 MachineBasicBlock::iterator II = prior(I);
353 TRI->eliminateFrameIndex(II, SPAdj, this);
356 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
357 MachineBasicBlock::iterator II = prior(I);
358 TRI->eliminateFrameIndex(II, SPAdj, this);