1 //===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine register scavenger. It can provide
11 // information, such as unused registers, at any point in a machine basic block.
12 // It also provides a mechanism to make registers available by evicting them to
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "reg-scavenging"
18 #include "llvm/CodeGen/RegisterScavenging.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/ADT/STLExtras.h"
28 /// RedefinesSuperRegPart - Return true if the specified register is redefining
29 /// part of a super-register.
30 static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
31 const TargetRegisterInfo *TRI) {
32 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
33 const MachineOperand &MO = MI->getOperand(i);
34 if (!MO.isRegister() || !MO.isUse())
36 if (TRI->isSuperRegister(SubReg, MO.getReg()))
43 static bool RedefinesSuperRegPart(const MachineInstr *MI,
44 const MachineOperand &MO,
45 const TargetRegisterInfo *TRI) {
46 assert(MO.isRegister() && MO.isDef() && "Not a register def!");
47 return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
50 /// setUsed - Set the register and its sub-registers as being used.
51 void RegScavenger::setUsed(unsigned Reg) {
52 RegsAvailable.reset(Reg);
54 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
55 unsigned SubReg = *SubRegs; ++SubRegs)
56 RegsAvailable.reset(SubReg);
59 /// setUnused - Set the register and its sub-registers as being unused.
60 void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
61 RegsAvailable.set(Reg);
63 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
64 unsigned SubReg = *SubRegs; ++SubRegs)
65 if (!RedefinesSuperRegPart(MI, Reg, TRI))
66 RegsAvailable.set(SubReg);
69 void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
70 const MachineFunction &MF = *mbb->getParent();
71 const TargetMachine &TM = MF.getTarget();
72 TII = TM.getInstrInfo();
73 TRI = TM.getRegisterInfo();
75 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
79 NumPhysRegs = TRI->getNumRegs();
80 RegsAvailable.resize(NumPhysRegs);
82 // Create reserved registers bitvector.
83 ReservedRegs = TRI->getReservedRegs(MF);
85 // Create callee-saved registers bitvector.
86 CalleeSavedRegs.resize(NumPhysRegs);
87 const unsigned *CSRegs = TRI->getCalleeSavedRegs();
89 for (unsigned i = 0; CSRegs[i]; ++i)
90 CalleeSavedRegs.set(CSRegs[i]);
97 // All registers started out unused.
100 // Reserved registers are always used.
101 RegsAvailable ^= ReservedRegs;
103 // Live-in registers are in use.
104 if (!MBB->livein_empty())
105 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
106 E = MBB->livein_end(); I != E; ++I)
112 void RegScavenger::restoreScavengedReg() {
116 TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
117 ScavengingFrameIndex, ScavengedRC);
118 MachineBasicBlock::iterator II = prior(MBBI);
119 TRI->eliminateFrameIndex(II, 0, this);
120 setUsed(ScavengedReg);
125 void RegScavenger::forward() {
131 assert(MBBI != MBB->end() && "Already at the end of the basic block!");
135 MachineInstr *MI = MBBI;
136 const TargetInstrDesc &TID = MI->getDesc();
138 // Reaching a terminator instruction. Restore a scavenged register (which
140 if (TID.isTerminator())
141 restoreScavengedReg();
143 // Process uses first.
144 BitVector ChangedRegs(NumPhysRegs);
145 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
146 const MachineOperand &MO = MI->getOperand(i);
147 if (!MO.isRegister() || !MO.isUse())
150 unsigned Reg = MO.getReg();
151 if (Reg == 0) continue;
154 // Register has been scavenged. Restore it!
155 if (Reg != ScavengedReg)
156 assert(false && "Using an undefined register!");
158 restoreScavengedReg();
161 if (MO.isKill() && !isReserved(Reg)) {
162 ChangedRegs.set(Reg);
164 // Mark sub-registers as changed if they aren't defined in the same
166 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
167 unsigned SubReg = *SubRegs; ++SubRegs)
168 if (!RedefinesSuperRegPart(MI, Reg, TRI))
169 ChangedRegs.set(SubReg);
173 // Change states of all registers after all the uses are processed to guard
174 // against multiple uses.
175 setUnused(ChangedRegs);
178 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
179 const MachineOperand &MO = MI->getOperand(i);
181 if (!MO.isRegister() || !MO.isDef())
184 unsigned Reg = MO.getReg();
186 // If it's dead upon def, then it is now free.
192 // Skip two-address destination operand.
193 if (TID.findTiedToSrcOperand(i) != -1) {
194 assert(isUsed(Reg) && "Using an undefined register!");
198 // Skip is this is merely redefining part of a super-register.
199 if (RedefinesSuperRegPart(MI, MO, TRI))
202 assert((isUnused(Reg) || isReserved(Reg)) &&
203 "Re-defining a live register!");
208 void RegScavenger::backward() {
209 assert(Tracking && "Not tracking states!");
210 assert(MBBI != MBB->begin() && "Already at start of basic block!");
211 // Move ptr backward.
214 MachineInstr *MI = MBBI;
215 // Process defs first.
216 const TargetInstrDesc &TID = MI->getDesc();
217 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
218 const MachineOperand &MO = MI->getOperand(i);
219 if (!MO.isRegister() || !MO.isDef())
221 // Skip two-address destination operand.
222 if (TID.findTiedToSrcOperand(i) != -1)
224 unsigned Reg = MO.getReg();
226 if (!isReserved(Reg))
231 BitVector ChangedRegs(NumPhysRegs);
232 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
233 const MachineOperand &MO = MI->getOperand(i);
234 if (!MO.isRegister() || !MO.isUse())
236 unsigned Reg = MO.getReg();
239 assert(isUnused(Reg) || isReserved(Reg));
240 ChangedRegs.set(Reg);
242 // Set the sub-registers as "used".
243 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
244 unsigned SubReg = *SubRegs; ++SubRegs)
245 ChangedRegs.set(SubReg);
247 setUsed(ChangedRegs);
250 void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
252 used = ~RegsAvailable;
254 used = ~RegsAvailable & ~ReservedRegs;
257 /// CreateRegClassMask - Set the bits that represent the registers in the
258 /// TargetRegisterClass.
259 static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
260 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
265 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
266 const BitVector &Candidates) const {
267 // Mask off the registers which are not in the TargetRegisterClass.
268 BitVector RegsAvailableCopy(NumPhysRegs, false);
269 CreateRegClassMask(RegClass, RegsAvailableCopy);
270 RegsAvailableCopy &= RegsAvailable;
272 // Restrict the search to candidates.
273 RegsAvailableCopy &= Candidates;
275 // Returns the first unused (bit is set) register, or 0 is none is found.
276 int Reg = RegsAvailableCopy.find_first();
277 return (Reg == -1) ? 0 : Reg;
280 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
281 bool ExCalleeSaved) const {
282 // Mask off the registers which are not in the TargetRegisterClass.
283 BitVector RegsAvailableCopy(NumPhysRegs, false);
284 CreateRegClassMask(RegClass, RegsAvailableCopy);
285 RegsAvailableCopy &= RegsAvailable;
287 // If looking for a non-callee-saved register, mask off all the callee-saved
290 RegsAvailableCopy &= ~CalleeSavedRegs;
292 // Returns the first unused (bit is set) register, or 0 is none is found.
293 int Reg = RegsAvailableCopy.find_first();
294 return (Reg == -1) ? 0 : Reg;
297 /// calcDistanceToUse - Calculate the distance to the first use of the
298 /// specified register.
299 static unsigned calcDistanceToUse(MachineBasicBlock *MBB,
300 MachineBasicBlock::iterator I, unsigned Reg,
301 const TargetRegisterInfo *TRI) {
304 while (I != MBB->end()) {
306 if (I->readsRegister(Reg, TRI))
313 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
314 MachineBasicBlock::iterator I,
316 assert(ScavengingFrameIndex >= 0 &&
317 "Cannot scavenge a register without an emergency spill slot!");
319 // Mask off the registers which are not in the TargetRegisterClass.
320 BitVector Candidates(NumPhysRegs, false);
321 CreateRegClassMask(RC, Candidates);
322 Candidates ^= ReservedRegs; // Do not include reserved registers.
324 // Exclude all the registers being used by the instruction.
325 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
326 MachineOperand &MO = I->getOperand(i);
328 Candidates.reset(MO.getReg());
331 // Find the register whose use is furthest away.
333 unsigned MaxDist = 0;
334 int Reg = Candidates.find_first();
336 unsigned Dist = calcDistanceToUse(MBB, I, Reg, TRI);
337 if (Dist >= MaxDist) {
341 Reg = Candidates.find_next(Reg);
344 if (ScavengedReg != 0) {
345 // First restore previously scavenged register.
346 TII->loadRegFromStackSlot(*MBB, I, ScavengedReg,
347 ScavengingFrameIndex, ScavengedRC);
348 MachineBasicBlock::iterator II = prior(I);
349 TRI->eliminateFrameIndex(II, SPAdj, this);
352 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
353 MachineBasicBlock::iterator II = prior(I);
354 TRI->eliminateFrameIndex(II, SPAdj, this);