1 //===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the generic RegisterCoalescer interface which
11 // is used as the common interface used by all clients and
12 // implementations of register coalescing.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "regalloc"
17 #include "RegisterCoalescer.h"
18 #include "LiveDebugVariables.h"
19 #include "RegisterClassInfo.h"
20 #include "VirtRegMap.h"
22 #include "llvm/Pass.h"
23 #include "llvm/Value.h"
24 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
30 #include "llvm/Analysis/AliasAnalysis.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineLoopInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/ADT/OwningPtr.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/STLExtras.h"
51 STATISTIC(numJoins , "Number of interval joins performed");
52 STATISTIC(numCrossRCs , "Number of cross class joins performed");
53 STATISTIC(numCommutes , "Number of instruction commuting performed");
54 STATISTIC(numExtends , "Number of copies extended");
55 STATISTIC(NumReMats , "Number of instructions re-materialized");
56 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
57 STATISTIC(numAborts , "Number of times interval joining aborted");
58 STATISTIC(NumInflated , "Number of register classes inflated");
61 EnableJoining("join-liveintervals",
62 cl::desc("Coalesce copies (default=true)"),
66 DisableCrossClassJoin("disable-cross-class-join",
67 cl::desc("Avoid coalescing cross register class copies"),
68 cl::init(false), cl::Hidden);
71 EnablePhysicalJoin("join-physregs",
72 cl::desc("Join physical register copies"),
73 cl::init(false), cl::Hidden);
76 VerifyCoalescing("verify-coalescing",
77 cl::desc("Verify machine instrs before and after register coalescing"),
81 class RegisterCoalescer : public MachineFunctionPass {
83 MachineRegisterInfo* MRI;
84 const TargetMachine* TM;
85 const TargetRegisterInfo* TRI;
86 const TargetInstrInfo* TII;
88 LiveDebugVariables *LDV;
89 const MachineLoopInfo* Loops;
91 RegisterClassInfo RegClassInfo;
93 /// JoinedCopies - Keep track of copies eliminated due to coalescing.
95 SmallPtrSet<MachineInstr*, 32> JoinedCopies;
97 /// ReMatCopies - Keep track of copies eliminated due to remat.
99 SmallPtrSet<MachineInstr*, 32> ReMatCopies;
101 /// ReMatDefs - Keep track of definition instructions which have
103 SmallPtrSet<MachineInstr*, 8> ReMatDefs;
105 /// joinIntervals - join compatible live intervals
106 void joinIntervals();
108 /// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
109 /// copies that cannot yet be coalesced into the "TryAgain" list.
110 void CopyCoalesceInMBB(MachineBasicBlock *MBB,
111 std::vector<MachineInstr*> &TryAgain);
113 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
114 /// which are the src/dst of the copy instruction CopyMI. This returns
115 /// true if the copy was successfully coalesced away. If it is not
116 /// currently possible to coalesce this interval, but it may be possible if
117 /// other things get coalesced, then it returns true by reference in
119 bool JoinCopy(MachineInstr *TheCopy, bool &Again);
121 /// JoinIntervals - Attempt to join these two intervals. On failure, this
122 /// returns false. The output "SrcInt" will not have been modified, so we
123 /// can use this information below to update aliases.
124 bool JoinIntervals(CoalescerPair &CP);
126 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
127 /// the source value number is defined by a copy from the destination reg
128 /// see if we can merge these two destination reg valno# into a single
129 /// value number, eliminating a copy.
130 bool AdjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
132 /// HasOtherReachingDefs - Return true if there are definitions of IntB
133 /// other than BValNo val# that can reach uses of AValno val# of IntA.
134 bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
135 VNInfo *AValNo, VNInfo *BValNo);
137 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy.
138 /// If the source value number is defined by a commutable instruction and
139 /// its other operand is coalesced to the copy dest register, see if we
140 /// can transform the copy into a noop by commuting the definition.
141 bool RemoveCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
143 /// ReMaterializeTrivialDef - If the source of a copy is defined by a
144 /// trivial computation, replace the copy by rematerialize the definition.
145 /// If PreserveSrcInt is true, make sure SrcInt is valid after the call.
146 bool ReMaterializeTrivialDef(LiveInterval &SrcInt, bool PreserveSrcInt,
147 unsigned DstReg, MachineInstr *CopyMI);
149 /// shouldJoinPhys - Return true if a physreg copy should be joined.
150 bool shouldJoinPhys(CoalescerPair &CP);
152 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
153 /// two virtual registers from different register classes.
154 bool isWinToJoinCrossClass(unsigned SrcReg,
156 const TargetRegisterClass *SrcRC,
157 const TargetRegisterClass *DstRC,
158 const TargetRegisterClass *NewRC);
160 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
161 /// update the subregister number if it is not zero. If DstReg is a
162 /// physical register and the existing subregister number of the def / use
163 /// being updated is not zero, make sure to set it to the correct physical
165 void UpdateRegDefsUses(const CoalescerPair &CP);
167 /// RemoveDeadDef - If a def of a live interval is now determined dead,
168 /// remove the val# it defines. If the live interval becomes empty, remove
170 bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
172 /// RemoveCopyFlag - If DstReg is no longer defined by CopyMI, clear the
173 /// VNInfo copy flag for DstReg and all aliases.
174 void RemoveCopyFlag(unsigned DstReg, const MachineInstr *CopyMI);
176 /// markAsJoined - Remember that CopyMI has already been joined.
177 void markAsJoined(MachineInstr *CopyMI);
179 /// eliminateUndefCopy - Handle copies of undef values.
180 bool eliminateUndefCopy(MachineInstr *CopyMI, const CoalescerPair &CP);
183 static char ID; // Class identification, replacement for typeinfo
184 RegisterCoalescer() : MachineFunctionPass(ID) {
185 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
188 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
190 virtual void releaseMemory();
192 /// runOnMachineFunction - pass entry point
193 virtual bool runOnMachineFunction(MachineFunction&);
195 /// print - Implement the dump method.
196 virtual void print(raw_ostream &O, const Module* = 0) const;
198 } /// end anonymous namespace
200 char &llvm::RegisterCoalescerPassID = RegisterCoalescer::ID;
202 INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
203 "Simple Register Coalescing", false, false)
204 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
205 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
206 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
207 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
208 INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
209 INITIALIZE_PASS_DEPENDENCY(PHIElimination)
210 INITIALIZE_PASS_DEPENDENCY(TwoAddressInstructionPass)
211 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
212 INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
213 "Simple Register Coalescing", false, false)
215 char RegisterCoalescer::ID = 0;
217 static unsigned compose(const TargetRegisterInfo &tri, unsigned a, unsigned b) {
220 return tri.composeSubRegIndices(a, b);
223 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
224 unsigned &Src, unsigned &Dst,
225 unsigned &SrcSub, unsigned &DstSub) {
227 Dst = MI->getOperand(0).getReg();
228 DstSub = MI->getOperand(0).getSubReg();
229 Src = MI->getOperand(1).getReg();
230 SrcSub = MI->getOperand(1).getSubReg();
231 } else if (MI->isSubregToReg()) {
232 Dst = MI->getOperand(0).getReg();
233 DstSub = compose(tri, MI->getOperand(0).getSubReg(),
234 MI->getOperand(3).getImm());
235 Src = MI->getOperand(2).getReg();
236 SrcSub = MI->getOperand(2).getSubReg();
242 bool CoalescerPair::setRegisters(const MachineInstr *MI) {
243 SrcReg = DstReg = SubIdx = 0;
245 Flipped = CrossClass = false;
247 unsigned Src, Dst, SrcSub, DstSub;
248 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
250 Partial = SrcSub || DstSub;
252 // If one register is a physreg, it must be Dst.
253 if (TargetRegisterInfo::isPhysicalRegister(Src)) {
254 if (TargetRegisterInfo::isPhysicalRegister(Dst))
257 std::swap(SrcSub, DstSub);
261 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
263 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
264 // Eliminate DstSub on a physreg.
266 Dst = TRI.getSubReg(Dst, DstSub);
267 if (!Dst) return false;
271 // Eliminate SrcSub by picking a corresponding Dst superregister.
273 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
274 if (!Dst) return false;
276 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
280 // Both registers are virtual.
282 // Both registers have subreg indices.
283 if (SrcSub && DstSub) {
284 // For now we only handle the case of identical indices in commensurate
285 // registers: Dreg:ssub_1 + Dreg:ssub_1 -> Dreg
286 // FIXME: Handle Qreg:ssub_3 + Dreg:ssub_1 as QReg:dsub_1 + Dreg.
287 if (SrcSub != DstSub)
289 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
290 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
291 if (!TRI.getCommonSubClass(DstRC, SrcRC))
296 // There can be no SrcSub.
301 assert(!Flipped && "Unexpected flip");
305 // Find the new register class.
306 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
307 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
309 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
311 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
314 CrossClass = NewRC != DstRC || NewRC != SrcRC;
316 // Check our invariants
317 assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
318 assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
319 "Cannot have a physical SubIdx");
326 bool CoalescerPair::flip() {
327 if (SubIdx || TargetRegisterInfo::isPhysicalRegister(DstReg))
329 std::swap(SrcReg, DstReg);
334 bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
337 unsigned Src, Dst, SrcSub, DstSub;
338 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
341 // Find the virtual register that is SrcReg.
344 std::swap(SrcSub, DstSub);
345 } else if (Src != SrcReg) {
349 // Now check that Dst matches DstReg.
350 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
351 if (!TargetRegisterInfo::isPhysicalRegister(Dst))
353 assert(!SubIdx && "Inconsistent CoalescerPair state.");
354 // DstSub could be set for a physreg from INSERT_SUBREG.
356 Dst = TRI.getSubReg(Dst, DstSub);
359 return DstReg == Dst;
360 // This is a partial register copy. Check that the parts match.
361 return TRI.getSubReg(DstReg, SrcSub) == Dst;
363 // DstReg is virtual.
366 // Registers match, do the subregisters line up?
367 return compose(TRI, SubIdx, SrcSub) == DstSub;
371 void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
372 AU.setPreservesCFG();
373 AU.addRequired<AliasAnalysis>();
374 AU.addRequired<LiveIntervals>();
375 AU.addPreserved<LiveIntervals>();
376 AU.addRequired<LiveDebugVariables>();
377 AU.addPreserved<LiveDebugVariables>();
378 AU.addPreserved<SlotIndexes>();
379 AU.addRequired<MachineLoopInfo>();
380 AU.addPreserved<MachineLoopInfo>();
381 AU.addPreservedID(MachineDominatorsID);
382 AU.addPreservedID(StrongPHIEliminationID);
383 AU.addPreservedID(PHIEliminationID);
384 AU.addPreservedID(TwoAddressInstructionPassID);
385 MachineFunctionPass::getAnalysisUsage(AU);
388 void RegisterCoalescer::markAsJoined(MachineInstr *CopyMI) {
389 /// Joined copies are not deleted immediately, but kept in JoinedCopies.
390 JoinedCopies.insert(CopyMI);
392 /// Mark all register operands of CopyMI as <undef> so they won't affect dead
393 /// code elimination.
394 for (MachineInstr::mop_iterator I = CopyMI->operands_begin(),
395 E = CopyMI->operands_end(); I != E; ++I)
400 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
401 /// being the source and IntB being the dest, thus this defines a value number
402 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
403 /// see if we can merge these two pieces of B into a single value number,
404 /// eliminating a copy. For example:
408 /// B1 = A3 <- this copy
410 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
411 /// value number to be replaced with B0 (which simplifies the B liveinterval).
413 /// This returns true if an interval was modified.
415 bool RegisterCoalescer::AdjustCopiesBackFrom(const CoalescerPair &CP,
416 MachineInstr *CopyMI) {
417 // Bail if there is no dst interval - can happen when merging physical subreg
419 if (!LIS->hasInterval(CP.getDstReg()))
423 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
425 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
426 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
428 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
429 // the example above.
430 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
431 if (BLR == IntB.end()) return false;
432 VNInfo *BValNo = BLR->valno;
434 // Get the location that B is defined at. Two options: either this value has
435 // an unknown definition point or it is defined at CopyIdx. If unknown, we
437 if (!BValNo->isDefByCopy()) return false;
438 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
440 // AValNo is the value number in A that defines the copy, A3 in the example.
441 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
442 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
443 // The live range might not exist after fun with physreg coalescing.
444 if (ALR == IntA.end()) return false;
445 VNInfo *AValNo = ALR->valno;
446 // If it's re-defined by an early clobber somewhere in the live range, then
447 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
449 // 172 %ECX<def> = MOV32rr %reg1039<kill>
450 // 180 INLINEASM <es:subl $5,$1
451 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9,
453 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
454 // 188 %EAX<def> = MOV32rr %EAX<kill>
455 // 196 %ECX<def> = MOV32rr %ECX<kill>
456 // 204 %ECX<def> = MOV32rr %ECX<kill>
457 // 212 %EAX<def> = MOV32rr %EAX<kill>
458 // 220 %EAX<def> = MOV32rr %EAX
459 // 228 %reg1039<def> = MOV32rr %ECX<kill>
460 // The early clobber operand ties ECX input to the ECX def.
462 // The live interval of ECX is represented as this:
463 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
464 // The coalescer has no idea there was a def in the middle of [174,230].
465 if (AValNo->hasRedefByEC())
468 // If AValNo is defined as a copy from IntB, we can potentially process this.
469 // Get the instruction that defines this value number.
470 if (!CP.isCoalescable(AValNo->getCopy()))
473 // Get the LiveRange in IntB that this value number starts with.
474 LiveInterval::iterator ValLR =
475 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
476 if (ValLR == IntB.end())
479 // Make sure that the end of the live range is inside the same block as
481 MachineInstr *ValLREndInst =
482 LIS->getInstructionFromIndex(ValLR->end.getPrevSlot());
483 if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent())
486 // Okay, we now know that ValLR ends in the same block that the CopyMI
487 // live-range starts. If there are no intervening live ranges between them in
488 // IntB, we can merge them.
489 if (ValLR+1 != BLR) return false;
491 // If a live interval is a physical register, conservatively check if any
492 // of its aliases is overlapping the live interval of the virtual register.
493 // If so, do not coalesce.
494 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
495 for (const unsigned *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS)
496 if (LIS->hasInterval(*AS) && IntA.overlaps(LIS->getInterval(*AS))) {
498 dbgs() << "\t\tInterfere with alias ";
499 LIS->getInterval(*AS).print(dbgs(), TRI);
506 dbgs() << "Extending: ";
507 IntB.print(dbgs(), TRI);
510 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
511 // We are about to delete CopyMI, so need to remove it as the 'instruction
512 // that defines this value #'. Update the valnum with the new defining
514 BValNo->def = FillerStart;
517 // Okay, we can merge them. We need to insert a new liverange:
518 // [ValLR.end, BLR.begin) of either value number, then we merge the
519 // two value numbers.
520 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
522 // If the IntB live range is assigned to a physical register, and if that
523 // physreg has sub-registers, update their live intervals as well.
524 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
525 for (const unsigned *SR = TRI->getSubRegisters(IntB.reg); *SR; ++SR) {
526 if (!LIS->hasInterval(*SR))
528 LiveInterval &SRLI = LIS->getInterval(*SR);
529 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
530 SRLI.getNextValue(FillerStart, 0,
531 LIS->getVNInfoAllocator())));
535 // Okay, merge "B1" into the same value number as "B0".
536 if (BValNo != ValLR->valno) {
537 // If B1 is killed by a PHI, then the merged live range must also be killed
538 // by the same PHI, as B0 and B1 can not overlap.
539 bool HasPHIKill = BValNo->hasPHIKill();
540 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
542 ValLR->valno->setHasPHIKill(true);
545 dbgs() << " result = ";
546 IntB.print(dbgs(), TRI);
550 // If the source instruction was killing the source register before the
551 // merge, unset the isKill marker given the live range has been extended.
552 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
554 ValLREndInst->getOperand(UIdx).setIsKill(false);
557 // Rewrite the copy. If the copy instruction was killing the destination
558 // register before the merge, find the last use and trim the live range. That
559 // will also add the isKill marker.
560 CopyMI->substituteRegister(IntA.reg, IntB.reg, CP.getSubIdx(),
562 if (ALR->end == CopyIdx)
563 LIS->shrinkToUses(&IntA);
569 /// HasOtherReachingDefs - Return true if there are definitions of IntB
570 /// other than BValNo val# that can reach uses of AValno val# of IntA.
571 bool RegisterCoalescer::HasOtherReachingDefs(LiveInterval &IntA,
575 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
577 if (AI->valno != AValNo) continue;
578 LiveInterval::Ranges::iterator BI =
579 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
580 if (BI != IntB.ranges.begin())
582 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
583 if (BI->valno == BValNo)
585 if (BI->start <= AI->start && BI->end > AI->start)
587 if (BI->start > AI->start && BI->start < AI->end)
594 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with
595 /// IntA being the source and IntB being the dest, thus this defines a value
596 /// number in IntB. If the source value number (in IntA) is defined by a
597 /// commutable instruction and its other operand is coalesced to the copy dest
598 /// register, see if we can transform the copy into a noop by commuting the
599 /// definition. For example,
601 /// A3 = op A2 B0<kill>
603 /// B1 = A3 <- this copy
605 /// = op A3 <- more uses
609 /// B2 = op B0 A2<kill>
611 /// B1 = B2 <- now an identify copy
613 /// = op B2 <- more uses
615 /// This returns true if an interval was modified.
617 bool RegisterCoalescer::RemoveCopyByCommutingDef(const CoalescerPair &CP,
618 MachineInstr *CopyMI) {
619 // FIXME: For now, only eliminate the copy by commuting its def when the
620 // source register is a virtual register. We want to guard against cases
621 // where the copy is a back edge copy and commuting the def lengthen the
622 // live interval of the source register to the entire loop.
623 if (CP.isPhys() && CP.isFlipped())
626 // Bail if there is no dst interval.
627 if (!LIS->hasInterval(CP.getDstReg()))
630 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
633 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
635 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
637 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
638 // the example above.
639 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
640 if (!BValNo || !BValNo->isDefByCopy())
643 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
645 // AValNo is the value number in A that defines the copy, A3 in the example.
646 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
647 assert(AValNo && "COPY source not live");
649 // If other defs can reach uses of this def, then it's not safe to perform
651 if (AValNo->isPHIDef() || AValNo->isUnused() || AValNo->hasPHIKill())
653 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
656 if (!DefMI->isCommutable())
658 // If DefMI is a two-address instruction then commuting it will change the
659 // destination register.
660 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
661 assert(DefIdx != -1);
663 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
665 unsigned Op1, Op2, NewDstIdx;
666 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
670 else if (Op2 == UseOpIdx)
675 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
676 unsigned NewReg = NewDstMO.getReg();
677 if (NewReg != IntB.reg || !NewDstMO.isKill())
680 // Make sure there are no other definitions of IntB that would reach the
681 // uses which the new definition can reach.
682 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
685 // Abort if the aliases of IntB.reg have values that are not simply the
686 // clobbers from the superreg.
687 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
688 for (const unsigned *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS)
689 if (LIS->hasInterval(*AS) &&
690 HasOtherReachingDefs(IntA, LIS->getInterval(*AS), AValNo, 0))
693 // If some of the uses of IntA.reg is already coalesced away, return false.
694 // It's not possible to determine whether it's safe to perform the coalescing.
695 for (MachineRegisterInfo::use_nodbg_iterator UI =
696 MRI->use_nodbg_begin(IntA.reg),
697 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
698 MachineInstr *UseMI = &*UI;
699 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
700 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
701 if (ULR == IntA.end())
703 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
707 DEBUG(dbgs() << "\tRemoveCopyByCommutingDef: " << AValNo->def << '\t'
710 // At this point we have decided that it is legal to do this
711 // transformation. Start by commuting the instruction.
712 MachineBasicBlock *MBB = DefMI->getParent();
713 MachineInstr *NewMI = TII->commuteInstruction(DefMI);
716 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
717 TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
718 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
720 if (NewMI != DefMI) {
721 LIS->ReplaceMachineInstrInMaps(DefMI, NewMI);
722 MachineBasicBlock::iterator Pos = DefMI;
723 MBB->insert(Pos, NewMI);
726 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
727 NewMI->getOperand(OpIdx).setIsKill();
729 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
738 // Update uses of IntA of the specific Val# with IntB.
739 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
740 UE = MRI->use_end(); UI != UE;) {
741 MachineOperand &UseMO = UI.getOperand();
742 MachineInstr *UseMI = &*UI;
744 if (JoinedCopies.count(UseMI))
746 if (UseMI->isDebugValue()) {
747 // FIXME These don't have an instruction index. Not clear we have enough
748 // info to decide whether to do this replacement or not. For now do it.
749 UseMO.setReg(NewReg);
752 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
753 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
754 if (ULR == IntA.end() || ULR->valno != AValNo)
756 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
757 UseMO.substPhysReg(NewReg, *TRI);
759 UseMO.setReg(NewReg);
762 if (!UseMI->isCopy())
764 if (UseMI->getOperand(0).getReg() != IntB.reg ||
765 UseMI->getOperand(0).getSubReg())
768 // This copy will become a noop. If it's defining a new val#, merge it into
770 SlotIndex DefIdx = UseIdx.getRegSlot();
771 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
774 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
775 assert(DVNI->def == DefIdx);
776 BValNo = IntB.MergeValueNumberInto(BValNo, DVNI);
780 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
782 VNInfo *ValNo = BValNo;
783 ValNo->def = AValNo->def;
785 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
787 if (AI->valno != AValNo) continue;
788 IntB.addRange(LiveRange(AI->start, AI->end, ValNo));
790 DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
792 IntA.removeValNo(AValNo);
793 DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
798 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
799 /// computation, replace the copy by rematerialize the definition.
800 bool RegisterCoalescer::ReMaterializeTrivialDef(LiveInterval &SrcInt,
803 MachineInstr *CopyMI) {
804 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
805 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
806 assert(SrcLR != SrcInt.end() && "Live range not found!");
807 VNInfo *ValNo = SrcLR->valno;
808 if (ValNo->isPHIDef() || ValNo->isUnused())
810 MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
813 assert(DefMI && "Defining instruction disappeared");
814 if (!DefMI->isAsCheapAsAMove())
816 if (!TII->isTriviallyReMaterializable(DefMI, AA))
818 bool SawStore = false;
819 if (!DefMI->isSafeToMove(TII, AA, SawStore))
821 const MCInstrDesc &MCID = DefMI->getDesc();
822 if (MCID.getNumDefs() != 1)
824 if (!DefMI->isImplicitDef()) {
825 // Make sure the copy destination register class fits the instruction
826 // definition register class. The mismatch can happen as a result of earlier
827 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
828 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI);
829 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
830 if (MRI->getRegClass(DstReg) != RC)
832 } else if (!RC->contains(DstReg))
836 RemoveCopyFlag(DstReg, CopyMI);
838 MachineBasicBlock *MBB = CopyMI->getParent();
839 MachineBasicBlock::iterator MII =
840 llvm::next(MachineBasicBlock::iterator(CopyMI));
841 TII->reMaterialize(*MBB, MII, DstReg, 0, DefMI, *TRI);
842 MachineInstr *NewMI = prior(MII);
844 // CopyMI may have implicit operands, transfer them over to the newly
845 // rematerialized instruction. And update implicit def interval valnos.
846 for (unsigned i = CopyMI->getDesc().getNumOperands(),
847 e = CopyMI->getNumOperands(); i != e; ++i) {
848 MachineOperand &MO = CopyMI->getOperand(i);
849 if (MO.isReg() && MO.isImplicit())
850 NewMI->addOperand(MO);
852 RemoveCopyFlag(MO.getReg(), CopyMI);
855 LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
856 CopyMI->eraseFromParent();
857 ReMatCopies.insert(CopyMI);
858 ReMatDefs.insert(DefMI);
859 DEBUG(dbgs() << "Remat: " << *NewMI);
862 // The source interval can become smaller because we removed a use.
864 LIS->shrinkToUses(&SrcInt);
869 /// eliminateUndefCopy - ProcessImpicitDefs may leave some copies of <undef>
870 /// values, it only removes local variables. When we have a copy like:
872 /// %vreg1 = COPY %vreg2<undef>
874 /// We delete the copy and remove the corresponding value number from %vreg1.
875 /// Any uses of that value number are marked as <undef>.
876 bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI,
877 const CoalescerPair &CP) {
878 SlotIndex Idx = LIS->getInstructionIndex(CopyMI);
879 LiveInterval *SrcInt = &LIS->getInterval(CP.getSrcReg());
880 if (SrcInt->liveAt(Idx))
882 LiveInterval *DstInt = &LIS->getInterval(CP.getDstReg());
883 if (DstInt->liveAt(Idx))
886 // No intervals are live-in to CopyMI - it is undef.
891 VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getRegSlot());
892 assert(DeadVNI && "No value defined in DstInt");
893 DstInt->removeValNo(DeadVNI);
895 // Find new undef uses.
896 for (MachineRegisterInfo::reg_nodbg_iterator
897 I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end();
899 MachineOperand &MO = I.getOperand();
900 if (MO.isDef() || MO.isUndef())
902 MachineInstr *MI = MO.getParent();
903 SlotIndex Idx = LIS->getInstructionIndex(MI);
904 if (DstInt->liveAt(Idx))
907 DEBUG(dbgs() << "\tnew undef: " << Idx << '\t' << *MI);
912 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
913 /// update the subregister number if it is not zero. If DstReg is a
914 /// physical register and the existing subregister number of the def / use
915 /// being updated is not zero, make sure to set it to the correct physical
918 RegisterCoalescer::UpdateRegDefsUses(const CoalescerPair &CP) {
919 bool DstIsPhys = CP.isPhys();
920 unsigned SrcReg = CP.getSrcReg();
921 unsigned DstReg = CP.getDstReg();
922 unsigned SubIdx = CP.getSubIdx();
924 // Update LiveDebugVariables.
925 LDV->renameRegister(SrcReg, DstReg, SubIdx);
927 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);
928 MachineInstr *UseMI = I.skipInstruction();) {
929 // A PhysReg copy that won't be coalesced can perhaps be rematerialized
932 if (UseMI->isFullCopy() &&
933 UseMI->getOperand(1).getReg() == SrcReg &&
934 UseMI->getOperand(0).getReg() != SrcReg &&
935 UseMI->getOperand(0).getReg() != DstReg &&
936 !JoinedCopies.count(UseMI) &&
937 ReMaterializeTrivialDef(LIS->getInterval(SrcReg), false,
938 UseMI->getOperand(0).getReg(), UseMI))
942 SmallVector<unsigned,8> Ops;
944 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
945 bool Kills = false, Deads = false;
947 // Replace SrcReg with DstReg in all UseMI operands.
948 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
949 MachineOperand &MO = UseMI->getOperand(Ops[i]);
950 Kills |= MO.isKill();
951 Deads |= MO.isDead();
953 // Make sure we don't create read-modify-write defs accidentally. We
954 // assume here that a SrcReg def cannot be joined into a live DstReg. If
955 // RegisterCoalescer starts tracking partially live registers, we will
956 // need to check the actual LiveInterval to determine if DstReg is live
958 if (SubIdx && !Reads)
962 MO.substPhysReg(DstReg, *TRI);
964 MO.substVirtReg(DstReg, SubIdx, *TRI);
967 // This instruction is a copy that will be removed.
968 if (JoinedCopies.count(UseMI))
972 // If UseMI was a simple SrcReg def, make sure we didn't turn it into a
973 // read-modify-write of DstReg.
975 UseMI->addRegisterDead(DstReg, TRI);
976 else if (!Reads && Writes)
977 UseMI->addRegisterDefined(DstReg, TRI);
979 // Kill flags apply to the whole physical register.
980 if (DstIsPhys && Kills)
981 UseMI->addRegisterKilled(DstReg, TRI);
985 dbgs() << "\t\tupdated: ";
986 if (!UseMI->isDebugValue())
987 dbgs() << LIS->getInstructionIndex(UseMI) << "\t";
993 /// removeIntervalIfEmpty - Check if the live interval of a physical register
994 /// is empty, if so remove it and also remove the empty intervals of its
995 /// sub-registers. Return true if live interval is removed.
996 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *LIS,
997 const TargetRegisterInfo *TRI) {
999 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
1000 for (const unsigned* SR = TRI->getSubRegisters(li.reg); *SR; ++SR) {
1001 if (!LIS->hasInterval(*SR))
1003 LiveInterval &sli = LIS->getInterval(*SR);
1005 LIS->removeInterval(*SR);
1007 LIS->removeInterval(li.reg);
1013 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
1014 /// the val# it defines. If the live interval becomes empty, remove it as well.
1015 bool RegisterCoalescer::RemoveDeadDef(LiveInterval &li,
1016 MachineInstr *DefMI) {
1017 SlotIndex DefIdx = LIS->getInstructionIndex(DefMI).getRegSlot();
1018 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
1019 if (DefIdx != MLR->valno->def)
1021 li.removeValNo(MLR->valno);
1022 return removeIntervalIfEmpty(li, LIS, TRI);
1025 void RegisterCoalescer::RemoveCopyFlag(unsigned DstReg,
1026 const MachineInstr *CopyMI) {
1027 SlotIndex DefIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
1028 if (LIS->hasInterval(DstReg)) {
1029 LiveInterval &LI = LIS->getInterval(DstReg);
1030 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
1031 if (LR->valno->def == DefIdx)
1032 LR->valno->setCopy(0);
1034 if (!TargetRegisterInfo::isPhysicalRegister(DstReg))
1036 for (const unsigned* AS = TRI->getAliasSet(DstReg); *AS; ++AS) {
1037 if (!LIS->hasInterval(*AS))
1039 LiveInterval &LI = LIS->getInterval(*AS);
1040 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
1041 if (LR->valno->def == DefIdx)
1042 LR->valno->setCopy(0);
1046 /// shouldJoinPhys - Return true if a copy involving a physreg should be joined.
1047 /// We need to be careful about coalescing a source physical register with a
1048 /// virtual register. Once the coalescing is done, it cannot be broken and these
1049 /// are not spillable! If the destination interval uses are far away, think
1050 /// twice about coalescing them!
1051 bool RegisterCoalescer::shouldJoinPhys(CoalescerPair &CP) {
1052 bool Allocatable = LIS->isAllocatable(CP.getDstReg());
1053 LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
1055 /// Always join simple intervals that are defined by a single copy from a
1056 /// reserved register. This doesn't increase register pressure, so it is
1057 /// always beneficial.
1058 if (!Allocatable && CP.isFlipped() && JoinVInt.containsOneValue())
1061 if (!EnablePhysicalJoin) {
1062 DEBUG(dbgs() << "\tPhysreg joins disabled.\n");
1066 // Only coalesce to allocatable physreg, we don't want to risk modifying
1067 // reserved registers.
1069 DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n");
1070 return false; // Not coalescable.
1073 // Don't join with physregs that have a ridiculous number of live
1074 // ranges. The data structure performance is really bad when that
1076 if (LIS->hasInterval(CP.getDstReg()) &&
1077 LIS->getInterval(CP.getDstReg()).ranges.size() > 1000) {
1080 << "\tPhysical register live interval too complicated, abort!\n");
1084 // FIXME: Why are we skipping this test for partial copies?
1085 // CodeGen/X86/phys_subreg_coalesce-3.ll needs it.
1086 if (!CP.isPartial()) {
1087 const TargetRegisterClass *RC = MRI->getRegClass(CP.getSrcReg());
1088 unsigned Threshold = RegClassInfo.getNumAllocatableRegs(RC) * 2;
1089 unsigned Length = LIS->getApproximateInstructionCount(JoinVInt);
1090 if (Length > Threshold) {
1092 DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
1099 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
1100 /// two virtual registers from different register classes.
1102 RegisterCoalescer::isWinToJoinCrossClass(unsigned SrcReg,
1104 const TargetRegisterClass *SrcRC,
1105 const TargetRegisterClass *DstRC,
1106 const TargetRegisterClass *NewRC) {
1107 unsigned NewRCCount = RegClassInfo.getNumAllocatableRegs(NewRC);
1108 // This heuristics is good enough in practice, but it's obviously not *right*.
1109 // 4 is a magic number that works well enough for x86, ARM, etc. It filter
1110 // out all but the most restrictive register classes.
1111 if (NewRCCount > 4 ||
1112 // Early exit if the function is fairly small, coalesce aggressively if
1113 // that's the case. For really special register classes with 3 or
1114 // fewer registers, be a bit more careful.
1115 (LIS->getFuncInstructionCount() / NewRCCount) < 8)
1117 LiveInterval &SrcInt = LIS->getInterval(SrcReg);
1118 LiveInterval &DstInt = LIS->getInterval(DstReg);
1119 unsigned SrcSize = LIS->getApproximateInstructionCount(SrcInt);
1120 unsigned DstSize = LIS->getApproximateInstructionCount(DstInt);
1122 // Coalesce aggressively if the intervals are small compared to the number of
1123 // registers in the new class. The number 4 is fairly arbitrary, chosen to be
1124 // less aggressive than the 8 used for the whole function size.
1125 const unsigned ThresSize = 4 * NewRCCount;
1126 if (SrcSize <= ThresSize && DstSize <= ThresSize)
1129 // Estimate *register use density*. If it doubles or more, abort.
1130 unsigned SrcUses = std::distance(MRI->use_nodbg_begin(SrcReg),
1131 MRI->use_nodbg_end());
1132 unsigned DstUses = std::distance(MRI->use_nodbg_begin(DstReg),
1133 MRI->use_nodbg_end());
1134 unsigned NewUses = SrcUses + DstUses;
1135 unsigned NewSize = SrcSize + DstSize;
1136 if (SrcRC != NewRC && SrcSize > ThresSize) {
1137 unsigned SrcRCCount = RegClassInfo.getNumAllocatableRegs(SrcRC);
1138 if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount)
1141 if (DstRC != NewRC && DstSize > ThresSize) {
1142 unsigned DstRCCount = RegClassInfo.getNumAllocatableRegs(DstRC);
1143 if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount)
1150 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1151 /// which are the src/dst of the copy instruction CopyMI. This returns true
1152 /// if the copy was successfully coalesced away. If it is not currently
1153 /// possible to coalesce this interval, but it may be possible if other
1154 /// things get coalesced, then it returns true by reference in 'Again'.
1155 bool RegisterCoalescer::JoinCopy(MachineInstr *CopyMI, bool &Again) {
1158 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1159 return false; // Already done.
1161 DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1163 CoalescerPair CP(*TII, *TRI);
1164 if (!CP.setRegisters(CopyMI)) {
1165 DEBUG(dbgs() << "\tNot coalescable.\n");
1169 // If they are already joined we continue.
1170 if (CP.getSrcReg() == CP.getDstReg()) {
1171 markAsJoined(CopyMI);
1172 DEBUG(dbgs() << "\tCopy already coalesced.\n");
1173 return false; // Not coalescable.
1176 // Eliminate undefs.
1177 if (!CP.isPhys() && eliminateUndefCopy(CopyMI, CP)) {
1178 markAsJoined(CopyMI);
1179 DEBUG(dbgs() << "\tEliminated copy of <undef> value.\n");
1180 return false; // Not coalescable.
1183 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI)
1184 << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSubIdx())
1187 // Enforce policies.
1189 if (!shouldJoinPhys(CP)) {
1190 // Before giving up coalescing, if definition of source is defined by
1191 // trivial computation, try rematerializing it.
1192 if (!CP.isFlipped() &&
1193 ReMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()), true,
1194 CP.getDstReg(), CopyMI))
1199 // Avoid constraining virtual register regclass too much.
1200 if (CP.isCrossClass()) {
1201 DEBUG(dbgs() << "\tCross-class to " << CP.getNewRC()->getName() << ".\n");
1202 if (DisableCrossClassJoin) {
1203 DEBUG(dbgs() << "\tCross-class joins disabled.\n");
1206 if (!isWinToJoinCrossClass(CP.getSrcReg(), CP.getDstReg(),
1207 MRI->getRegClass(CP.getSrcReg()),
1208 MRI->getRegClass(CP.getDstReg()),
1210 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class.\n");
1211 Again = true; // May be possible to coalesce later.
1216 // When possible, let DstReg be the larger interval.
1217 if (!CP.getSubIdx() && LIS->getInterval(CP.getSrcReg()).ranges.size() >
1218 LIS->getInterval(CP.getDstReg()).ranges.size())
1222 // Okay, attempt to join these two intervals. On failure, this returns false.
1223 // Otherwise, if one of the intervals being joined is a physreg, this method
1224 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1225 // been modified, so we can use this information below to update aliases.
1226 if (!JoinIntervals(CP)) {
1227 // Coalescing failed.
1229 // If definition of source is defined by trivial computation, try
1230 // rematerializing it.
1231 if (!CP.isFlipped() &&
1232 ReMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()), true,
1233 CP.getDstReg(), CopyMI))
1236 // If we can eliminate the copy without merging the live ranges, do so now.
1237 if (!CP.isPartial()) {
1238 if (AdjustCopiesBackFrom(CP, CopyMI) ||
1239 RemoveCopyByCommutingDef(CP, CopyMI)) {
1240 markAsJoined(CopyMI);
1241 DEBUG(dbgs() << "\tTrivial!\n");
1246 // Otherwise, we are unable to join the intervals.
1247 DEBUG(dbgs() << "\tInterference!\n");
1248 Again = true; // May be possible to coalesce later.
1252 // Coalescing to a virtual register that is of a sub-register class of the
1253 // other. Make sure the resulting register is set to the right register class.
1254 if (CP.isCrossClass()) {
1256 MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
1259 // Remember to delete the copy instruction.
1260 markAsJoined(CopyMI);
1262 UpdateRegDefsUses(CP);
1264 // If we have extended the live range of a physical register, make sure we
1265 // update live-in lists as well.
1267 SmallVector<MachineBasicBlock*, 16> BlockSeq;
1268 // JoinIntervals invalidates the VNInfos in SrcInt, but we only need the
1269 // ranges for this, and they are preserved.
1270 LiveInterval &SrcInt = LIS->getInterval(CP.getSrcReg());
1271 for (LiveInterval::const_iterator I = SrcInt.begin(), E = SrcInt.end();
1273 LIS->findLiveInMBBs(I->start, I->end, BlockSeq);
1274 for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) {
1275 MachineBasicBlock &block = *BlockSeq[idx];
1276 if (!block.isLiveIn(CP.getDstReg()))
1277 block.addLiveIn(CP.getDstReg());
1283 // SrcReg is guaranteed to be the register whose live interval that is
1285 LIS->removeInterval(CP.getSrcReg());
1287 // Update regalloc hint.
1288 TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
1291 LiveInterval &DstInt = LIS->getInterval(CP.getDstReg());
1292 dbgs() << "\tJoined. Result = ";
1293 DstInt.print(dbgs(), TRI);
1301 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1302 /// compute what the resultant value numbers for each value in the input two
1303 /// ranges will be. This is complicated by copies between the two which can
1304 /// and will commonly cause multiple value numbers to be merged into one.
1306 /// VN is the value number that we're trying to resolve. InstDefiningValue
1307 /// keeps track of the new InstDefiningValue assignment for the result
1308 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1309 /// whether a value in this or other is a copy from the opposite set.
1310 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1311 /// already been assigned.
1313 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1314 /// contains the value number the copy is from.
1316 static unsigned ComputeUltimateVN(VNInfo *VNI,
1317 SmallVector<VNInfo*, 16> &NewVNInfo,
1318 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1319 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1320 SmallVector<int, 16> &ThisValNoAssignments,
1321 SmallVector<int, 16> &OtherValNoAssignments) {
1322 unsigned VN = VNI->id;
1324 // If the VN has already been computed, just return it.
1325 if (ThisValNoAssignments[VN] >= 0)
1326 return ThisValNoAssignments[VN];
1327 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1329 // If this val is not a copy from the other val, then it must be a new value
1330 // number in the destination.
1331 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1332 if (I == ThisFromOther.end()) {
1333 NewVNInfo.push_back(VNI);
1334 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1336 VNInfo *OtherValNo = I->second;
1338 // Otherwise, this *is* a copy from the RHS. If the other side has already
1339 // been computed, return it.
1340 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1341 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1343 // Mark this value number as currently being computed, then ask what the
1344 // ultimate value # of the other value is.
1345 ThisValNoAssignments[VN] = -2;
1346 unsigned UltimateVN =
1347 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1348 OtherValNoAssignments, ThisValNoAssignments);
1349 return ThisValNoAssignments[VN] = UltimateVN;
1353 // Find out if we have something like
1356 // if so, we can pretend this is actually
1359 // which allows us to coalesce A and B.
1360 // VNI is the definition of B. LR is the life range of A that includes
1361 // the slot just before B. If we return true, we add "B = X" to DupCopies.
1362 // This implies that A dominates B.
1363 static bool RegistersDefinedFromSameValue(LiveIntervals &li,
1364 const TargetRegisterInfo &tri,
1368 SmallVector<MachineInstr*, 8> &DupCopies) {
1369 // FIXME: This is very conservative. For example, we don't handle
1370 // physical registers.
1372 MachineInstr *MI = VNI->getCopy();
1374 if (!MI->isFullCopy() || CP.isPartial() || CP.isPhys())
1377 unsigned Dst = MI->getOperand(0).getReg();
1378 unsigned Src = MI->getOperand(1).getReg();
1380 if (!TargetRegisterInfo::isVirtualRegister(Src) ||
1381 !TargetRegisterInfo::isVirtualRegister(Dst))
1384 unsigned A = CP.getDstReg();
1385 unsigned B = CP.getSrcReg();
1391 VNInfo *Other = LR->valno;
1392 if (!Other->isDefByCopy())
1394 const MachineInstr *OtherMI = Other->getCopy();
1396 if (!OtherMI->isFullCopy())
1399 unsigned OtherDst = OtherMI->getOperand(0).getReg();
1400 unsigned OtherSrc = OtherMI->getOperand(1).getReg();
1402 if (!TargetRegisterInfo::isVirtualRegister(OtherSrc) ||
1403 !TargetRegisterInfo::isVirtualRegister(OtherDst))
1406 assert(OtherDst == B);
1408 if (Src != OtherSrc)
1411 // If the copies use two different value numbers of X, we cannot merge
1413 LiveInterval &SrcInt = li.getInterval(Src);
1414 // getVNInfoBefore returns NULL for undef copies. In this case, the
1415 // optimization is still safe.
1416 if (SrcInt.getVNInfoBefore(Other->def) != SrcInt.getVNInfoBefore(VNI->def))
1419 DupCopies.push_back(MI);
1424 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1426 bool RegisterCoalescer::JoinIntervals(CoalescerPair &CP) {
1427 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1428 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), TRI); dbgs() << "\n"; });
1430 // If a live interval is a physical register, check for interference with any
1431 // aliases. The interference check implemented here is a bit more conservative
1432 // than the full interfeence check below. We allow overlapping live ranges
1433 // only when one is a copy of the other.
1435 // Optimization for reserved registers like ESP.
1436 // We can only merge with a reserved physreg if RHS has a single value that
1437 // is a copy of CP.DstReg(). The live range of the reserved register will
1438 // look like a set of dead defs - we don't properly track the live range of
1439 // reserved registers.
1440 if (RegClassInfo.isReserved(CP.getDstReg())) {
1441 assert(CP.isFlipped() && RHS.containsOneValue() &&
1442 "Invalid join with reserved register");
1443 // Deny any overlapping intervals. This depends on all the reserved
1444 // register live ranges to look like dead defs.
1445 for (const unsigned *AS = TRI->getOverlaps(CP.getDstReg()); *AS; ++AS) {
1446 if (!LIS->hasInterval(*AS))
1448 if (RHS.overlaps(LIS->getInterval(*AS))) {
1449 DEBUG(dbgs() << "\t\tInterference: " << PrintReg(*AS, TRI) << '\n');
1453 // Skip any value computations, we are not adding new values to the
1454 // reserved register. Also skip merging the live ranges, the reserved
1455 // register live range doesn't need to be accurate as long as all the
1460 for (const unsigned *AS = TRI->getAliasSet(CP.getDstReg()); *AS; ++AS){
1461 if (!LIS->hasInterval(*AS))
1463 const LiveInterval &LHS = LIS->getInterval(*AS);
1464 LiveInterval::const_iterator LI = LHS.begin();
1465 for (LiveInterval::const_iterator RI = RHS.begin(), RE = RHS.end();
1467 LI = std::lower_bound(LI, LHS.end(), RI->start);
1468 // Does LHS have an overlapping live range starting before RI?
1469 if ((LI != LHS.begin() && LI[-1].end > RI->start) &&
1470 (RI->start != RI->valno->def ||
1471 !CP.isCoalescable(LIS->getInstructionFromIndex(RI->start)))) {
1473 dbgs() << "\t\tInterference from alias: ";
1474 LHS.print(dbgs(), TRI);
1475 dbgs() << "\n\t\tOverlap at " << RI->start << " and no copy.\n";
1480 // Check that LHS ranges beginning in this range are copies.
1481 for (; LI != LHS.end() && LI->start < RI->end; ++LI) {
1482 if (LI->start != LI->valno->def ||
1483 !CP.isCoalescable(LIS->getInstructionFromIndex(LI->start))) {
1485 dbgs() << "\t\tInterference from alias: ";
1486 LHS.print(dbgs(), TRI);
1487 dbgs() << "\n\t\tDef at " << LI->start << " is not a copy.\n";
1496 // Compute the final value assignment, assuming that the live ranges can be
1498 SmallVector<int, 16> LHSValNoAssignments;
1499 SmallVector<int, 16> RHSValNoAssignments;
1500 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1501 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1502 SmallVector<VNInfo*, 16> NewVNInfo;
1504 SmallVector<MachineInstr*, 8> DupCopies;
1506 LiveInterval &LHS = LIS->getOrCreateInterval(CP.getDstReg());
1507 DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), TRI); dbgs() << "\n"; });
1509 // Loop over the value numbers of the LHS, seeing if any are defined from
1511 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1514 if (VNI->isUnused() || !VNI->isDefByCopy()) // Src not defined by a copy?
1517 // Never join with a register that has EarlyClobber redefs.
1518 if (VNI->hasRedefByEC())
1521 // Figure out the value # from the RHS.
1522 LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1523 // The copy could be to an aliased physreg.
1526 // DstReg is known to be a register in the LHS interval. If the src is
1527 // from the RHS interval, we can use its value #.
1528 MachineInstr *MI = VNI->getCopy();
1529 if (!CP.isCoalescable(MI) &&
1530 !RegistersDefinedFromSameValue(*LIS, *TRI, CP, VNI, lr, DupCopies))
1533 LHSValsDefinedFromRHS[VNI] = lr->valno;
1536 // Loop over the value numbers of the RHS, seeing if any are defined from
1538 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1541 if (VNI->isUnused() || !VNI->isDefByCopy()) // Src not defined by a copy?
1544 // Never join with a register that has EarlyClobber redefs.
1545 if (VNI->hasRedefByEC())
1548 // Figure out the value # from the LHS.
1549 LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1550 // The copy could be to an aliased physreg.
1553 // DstReg is known to be a register in the RHS interval. If the src is
1554 // from the LHS interval, we can use its value #.
1555 MachineInstr *MI = VNI->getCopy();
1556 if (!CP.isCoalescable(MI) &&
1557 !RegistersDefinedFromSameValue(*LIS, *TRI, CP, VNI, lr, DupCopies))
1560 RHSValsDefinedFromLHS[VNI] = lr->valno;
1563 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1564 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1565 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1567 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1570 unsigned VN = VNI->id;
1571 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1573 ComputeUltimateVN(VNI, NewVNInfo,
1574 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1575 LHSValNoAssignments, RHSValNoAssignments);
1577 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1580 unsigned VN = VNI->id;
1581 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1583 // If this value number isn't a copy from the LHS, it's a new number.
1584 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1585 NewVNInfo.push_back(VNI);
1586 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1590 ComputeUltimateVN(VNI, NewVNInfo,
1591 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1592 RHSValNoAssignments, LHSValNoAssignments);
1595 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1596 // interval lists to see if these intervals are coalescable.
1597 LiveInterval::const_iterator I = LHS.begin();
1598 LiveInterval::const_iterator IE = LHS.end();
1599 LiveInterval::const_iterator J = RHS.begin();
1600 LiveInterval::const_iterator JE = RHS.end();
1602 // Skip ahead until the first place of potential sharing.
1603 if (I != IE && J != JE) {
1604 if (I->start < J->start) {
1605 I = std::upper_bound(I, IE, J->start);
1606 if (I != LHS.begin()) --I;
1607 } else if (J->start < I->start) {
1608 J = std::upper_bound(J, JE, I->start);
1609 if (J != RHS.begin()) --J;
1613 while (I != IE && J != JE) {
1614 // Determine if these two live ranges overlap.
1616 if (I->start < J->start) {
1617 Overlaps = I->end > J->start;
1619 Overlaps = J->end > I->start;
1622 // If so, check value # info to determine if they are really different.
1624 // If the live range overlap will map to the same value number in the
1625 // result liverange, we can still coalesce them. If not, we can't.
1626 if (LHSValNoAssignments[I->valno->id] !=
1627 RHSValNoAssignments[J->valno->id])
1629 // If it's re-defined by an early clobber somewhere in the live range,
1630 // then conservatively abort coalescing.
1631 if (NewVNInfo[LHSValNoAssignments[I->valno->id]]->hasRedefByEC())
1635 if (I->end < J->end)
1641 // Update kill info. Some live ranges are extended due to copy coalescing.
1642 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1643 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1644 VNInfo *VNI = I->first;
1645 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1646 if (VNI->hasPHIKill())
1647 NewVNInfo[LHSValID]->setHasPHIKill(true);
1650 // Update kill info. Some live ranges are extended due to copy coalescing.
1651 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1652 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1653 VNInfo *VNI = I->first;
1654 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1655 if (VNI->hasPHIKill())
1656 NewVNInfo[RHSValID]->setHasPHIKill(true);
1659 if (LHSValNoAssignments.empty())
1660 LHSValNoAssignments.push_back(-1);
1661 if (RHSValNoAssignments.empty())
1662 RHSValNoAssignments.push_back(-1);
1664 SmallVector<unsigned, 8> SourceRegisters;
1665 for (SmallVector<MachineInstr*, 8>::iterator I = DupCopies.begin(),
1666 E = DupCopies.end(); I != E; ++I) {
1667 MachineInstr *MI = *I;
1669 // We have pretended that the assignment to B in
1672 // was actually a copy from A. Now that we decided to coalesce A and B,
1673 // transform the code into
1676 // and mark the X as coalesced to keep the illusion.
1677 unsigned Src = MI->getOperand(1).getReg();
1678 SourceRegisters.push_back(Src);
1679 MI->getOperand(0).substVirtReg(Src, 0, *TRI);
1684 // If B = X was the last use of X in a liverange, we have to shrink it now
1685 // that B = X is gone.
1686 for (SmallVector<unsigned, 8>::iterator I = SourceRegisters.begin(),
1687 E = SourceRegisters.end(); I != E; ++I) {
1688 LIS->shrinkToUses(&LIS->getInterval(*I));
1691 // If we get here, we know that we can coalesce the live ranges. Ask the
1692 // intervals to coalesce themselves now.
1693 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
1699 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1700 // depth of the basic block (the unsigned), and then on the MBB number.
1701 struct DepthMBBCompare {
1702 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1703 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1704 // Deeper loops first
1705 if (LHS.first != RHS.first)
1706 return LHS.first > RHS.first;
1708 // Prefer blocks that are more connected in the CFG. This takes care of
1709 // the most difficult copies first while intervals are short.
1710 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
1711 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
1715 // As a last resort, sort by block number.
1716 return LHS.second->getNumber() < RHS.second->getNumber();
1721 void RegisterCoalescer::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1722 std::vector<MachineInstr*> &TryAgain) {
1723 DEBUG(dbgs() << MBB->getName() << ":\n");
1725 SmallVector<MachineInstr*, 8> VirtCopies;
1726 SmallVector<MachineInstr*, 8> PhysCopies;
1727 SmallVector<MachineInstr*, 8> ImpDefCopies;
1728 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1730 MachineInstr *Inst = MII++;
1732 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1733 unsigned SrcReg, DstReg;
1734 if (Inst->isCopy()) {
1735 DstReg = Inst->getOperand(0).getReg();
1736 SrcReg = Inst->getOperand(1).getReg();
1737 } else if (Inst->isSubregToReg()) {
1738 DstReg = Inst->getOperand(0).getReg();
1739 SrcReg = Inst->getOperand(2).getReg();
1743 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1744 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1745 if (LIS->hasInterval(SrcReg) && LIS->getInterval(SrcReg).empty())
1746 ImpDefCopies.push_back(Inst);
1747 else if (SrcIsPhys || DstIsPhys)
1748 PhysCopies.push_back(Inst);
1750 VirtCopies.push_back(Inst);
1753 // Try coalescing implicit copies and insert_subreg <undef> first,
1754 // followed by copies to / from physical registers, then finally copies
1755 // from virtual registers to virtual registers.
1756 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
1757 MachineInstr *TheCopy = ImpDefCopies[i];
1759 if (!JoinCopy(TheCopy, Again))
1761 TryAgain.push_back(TheCopy);
1763 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
1764 MachineInstr *TheCopy = PhysCopies[i];
1766 if (!JoinCopy(TheCopy, Again))
1768 TryAgain.push_back(TheCopy);
1770 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
1771 MachineInstr *TheCopy = VirtCopies[i];
1773 if (!JoinCopy(TheCopy, Again))
1775 TryAgain.push_back(TheCopy);
1779 void RegisterCoalescer::joinIntervals() {
1780 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
1782 std::vector<MachineInstr*> TryAgainList;
1783 if (Loops->empty()) {
1784 // If there are no loops in the function, join intervals in function order.
1785 for (MachineFunction::iterator I = MF->begin(), E = MF->end();
1787 CopyCoalesceInMBB(I, TryAgainList);
1789 // Otherwise, join intervals in inner loops before other intervals.
1790 // Unfortunately we can't just iterate over loop hierarchy here because
1791 // there may be more MBB's than BB's. Collect MBB's for sorting.
1793 // Join intervals in the function prolog first. We want to join physical
1794 // registers with virtual registers before the intervals got too long.
1795 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1796 for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
1797 MachineBasicBlock *MBB = I;
1798 MBBs.push_back(std::make_pair(Loops->getLoopDepth(MBB), I));
1801 // Sort by loop depth.
1802 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1804 // Finally, join intervals in loop nest order.
1805 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1806 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
1809 // Joining intervals can allow other intervals to be joined. Iteratively join
1810 // until we make no progress.
1811 bool ProgressMade = true;
1812 while (ProgressMade) {
1813 ProgressMade = false;
1815 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1816 MachineInstr *&TheCopy = TryAgainList[i];
1821 bool Success = JoinCopy(TheCopy, Again);
1822 if (Success || !Again) {
1823 TheCopy= 0; // Mark this one as done.
1824 ProgressMade = true;
1830 void RegisterCoalescer::releaseMemory() {
1831 JoinedCopies.clear();
1832 ReMatCopies.clear();
1836 bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
1838 MRI = &fn.getRegInfo();
1839 TM = &fn.getTarget();
1840 TRI = TM->getRegisterInfo();
1841 TII = TM->getInstrInfo();
1842 LIS = &getAnalysis<LiveIntervals>();
1843 LDV = &getAnalysis<LiveDebugVariables>();
1844 AA = &getAnalysis<AliasAnalysis>();
1845 Loops = &getAnalysis<MachineLoopInfo>();
1847 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
1848 << "********** Function: "
1849 << ((Value*)MF->getFunction())->getName() << '\n');
1851 if (VerifyCoalescing)
1852 MF->verify(this, "Before register coalescing");
1854 RegClassInfo.runOnMachineFunction(fn);
1856 // Join (coalesce) intervals if requested.
1857 if (EnableJoining) {
1860 dbgs() << "********** INTERVALS POST JOINING **********\n";
1861 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end();
1863 I->second->print(dbgs(), TRI);
1869 // Perform a final pass over the instructions and compute spill weights
1870 // and remove identity moves.
1871 SmallVector<unsigned, 4> DeadDefs, InflateRegs;
1872 for (MachineFunction::iterator mbbi = MF->begin(), mbbe = MF->end();
1873 mbbi != mbbe; ++mbbi) {
1874 MachineBasicBlock* mbb = mbbi;
1875 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1877 MachineInstr *MI = mii;
1878 if (JoinedCopies.count(MI)) {
1879 // Delete all coalesced copies.
1880 bool DoDelete = true;
1881 assert(MI->isCopyLike() && "Unrecognized copy instruction");
1882 unsigned SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
1883 unsigned DstReg = MI->getOperand(0).getReg();
1885 // Collect candidates for register class inflation.
1886 if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1887 RegClassInfo.isProperSubClass(MRI->getRegClass(SrcReg)))
1888 InflateRegs.push_back(SrcReg);
1889 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
1890 RegClassInfo.isProperSubClass(MRI->getRegClass(DstReg)))
1891 InflateRegs.push_back(DstReg);
1893 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
1894 MI->getNumOperands() > 2)
1895 // Do not delete extract_subreg, insert_subreg of physical
1896 // registers unless the definition is dead. e.g.
1897 // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
1898 // or else the scavenger may complain. LowerSubregs will
1899 // delete them later.
1902 if (MI->allDefsAreDead()) {
1903 if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1904 LIS->hasInterval(SrcReg))
1905 LIS->shrinkToUses(&LIS->getInterval(SrcReg));
1909 // We need the instruction to adjust liveness, so make it a KILL.
1910 if (MI->isSubregToReg()) {
1911 MI->RemoveOperand(3);
1912 MI->RemoveOperand(1);
1914 MI->setDesc(TII->get(TargetOpcode::KILL));
1915 mii = llvm::next(mii);
1917 LIS->RemoveMachineInstrFromMaps(MI);
1918 mii = mbbi->erase(mii);
1924 // Now check if this is a remat'ed def instruction which is now dead.
1925 if (ReMatDefs.count(MI)) {
1927 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1928 const MachineOperand &MO = MI->getOperand(i);
1931 unsigned Reg = MO.getReg();
1934 DeadDefs.push_back(Reg);
1935 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1936 // Remat may also enable register class inflation.
1937 if (RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)))
1938 InflateRegs.push_back(Reg);
1942 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
1943 !MRI->use_nodbg_empty(Reg)) {
1949 while (!DeadDefs.empty()) {
1950 unsigned DeadDef = DeadDefs.back();
1951 DeadDefs.pop_back();
1952 RemoveDeadDef(LIS->getInterval(DeadDef), MI);
1954 LIS->RemoveMachineInstrFromMaps(mii);
1955 mii = mbbi->erase(mii);
1963 // Check for now unnecessary kill flags.
1964 if (LIS->isNotInMIMap(MI)) continue;
1965 SlotIndex DefIdx = LIS->getInstructionIndex(MI).getRegSlot();
1966 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1967 MachineOperand &MO = MI->getOperand(i);
1968 if (!MO.isReg() || !MO.isKill()) continue;
1969 unsigned reg = MO.getReg();
1970 if (!reg || !LIS->hasInterval(reg)) continue;
1971 if (!LIS->getInterval(reg).killedAt(DefIdx)) {
1972 MO.setIsKill(false);
1975 // When leaving a kill flag on a physreg, check if any subregs should
1977 if (!TargetRegisterInfo::isPhysicalRegister(reg))
1979 for (const unsigned *SR = TRI->getSubRegisters(reg);
1980 unsigned S = *SR; ++SR)
1981 if (LIS->hasInterval(S) && LIS->getInterval(S).liveAt(DefIdx))
1982 MI->addRegisterDefined(S, TRI);
1987 // After deleting a lot of copies, register classes may be less constrained.
1988 // Removing sub-register opreands may alow GR32_ABCD -> GR32 and DPR_VFP2 ->
1990 array_pod_sort(InflateRegs.begin(), InflateRegs.end());
1991 InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
1993 DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n");
1994 for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
1995 unsigned Reg = InflateRegs[i];
1996 if (MRI->reg_nodbg_empty(Reg))
1998 if (MRI->recomputeRegClass(Reg, *TM)) {
1999 DEBUG(dbgs() << PrintReg(Reg) << " inflated to "
2000 << MRI->getRegClass(Reg)->getName() << '\n');
2007 if (VerifyCoalescing)
2008 MF->verify(this, "After register coalescing");
2012 /// print - Implement the dump method.
2013 void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {