1 //===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the generic RegisterCoalescer interface which
11 // is used as the common interface used by all clients and
12 // implementations of register coalescing.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "regalloc"
17 #include "RegisterCoalescer.h"
18 #include "LiveDebugVariables.h"
19 #include "RegisterClassInfo.h"
20 #include "VirtRegMap.h"
22 #include "llvm/Pass.h"
23 #include "llvm/Value.h"
24 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
30 #include "llvm/Analysis/AliasAnalysis.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineLoopInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/ADT/OwningPtr.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/STLExtras.h"
51 STATISTIC(numJoins , "Number of interval joins performed");
52 STATISTIC(numCrossRCs , "Number of cross class joins performed");
53 STATISTIC(numCommutes , "Number of instruction commuting performed");
54 STATISTIC(numExtends , "Number of copies extended");
55 STATISTIC(NumReMats , "Number of instructions re-materialized");
56 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
57 STATISTIC(numAborts , "Number of times interval joining aborted");
58 STATISTIC(NumInflated , "Number of register classes inflated");
61 EnableJoining("join-liveintervals",
62 cl::desc("Coalesce copies (default=true)"),
66 DisableCrossClassJoin("disable-cross-class-join",
67 cl::desc("Avoid coalescing cross register class copies"),
68 cl::init(false), cl::Hidden);
71 EnablePhysicalJoin("join-physregs",
72 cl::desc("Join physical register copies"),
73 cl::init(false), cl::Hidden);
76 VerifyCoalescing("verify-coalescing",
77 cl::desc("Verify machine instrs before and after register coalescing"),
81 class RegisterCoalescer : public MachineFunctionPass {
83 MachineRegisterInfo* MRI;
84 const TargetMachine* TM;
85 const TargetRegisterInfo* TRI;
86 const TargetInstrInfo* TII;
88 LiveDebugVariables *LDV;
89 const MachineLoopInfo* Loops;
91 RegisterClassInfo RegClassInfo;
93 /// JoinedCopies - Keep track of copies eliminated due to coalescing.
95 SmallPtrSet<MachineInstr*, 32> JoinedCopies;
97 /// ReMatCopies - Keep track of copies eliminated due to remat.
99 SmallPtrSet<MachineInstr*, 32> ReMatCopies;
101 /// ReMatDefs - Keep track of definition instructions which have
103 SmallPtrSet<MachineInstr*, 8> ReMatDefs;
105 /// joinIntervals - join compatible live intervals
106 void joinIntervals();
108 /// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
109 /// copies that cannot yet be coalesced into the "TryAgain" list.
110 void CopyCoalesceInMBB(MachineBasicBlock *MBB,
111 std::vector<MachineInstr*> &TryAgain);
113 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
114 /// which are the src/dst of the copy instruction CopyMI. This returns
115 /// true if the copy was successfully coalesced away. If it is not
116 /// currently possible to coalesce this interval, but it may be possible if
117 /// other things get coalesced, then it returns true by reference in
119 bool JoinCopy(MachineInstr *TheCopy, bool &Again);
121 /// JoinIntervals - Attempt to join these two intervals. On failure, this
122 /// returns false. The output "SrcInt" will not have been modified, so we
123 /// can use this information below to update aliases.
124 bool JoinIntervals(CoalescerPair &CP);
126 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
127 /// the source value number is defined by a copy from the destination reg
128 /// see if we can merge these two destination reg valno# into a single
129 /// value number, eliminating a copy.
130 bool AdjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
132 /// HasOtherReachingDefs - Return true if there are definitions of IntB
133 /// other than BValNo val# that can reach uses of AValno val# of IntA.
134 bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
135 VNInfo *AValNo, VNInfo *BValNo);
137 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy.
138 /// If the source value number is defined by a commutable instruction and
139 /// its other operand is coalesced to the copy dest register, see if we
140 /// can transform the copy into a noop by commuting the definition.
141 bool RemoveCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
143 /// ReMaterializeTrivialDef - If the source of a copy is defined by a
144 /// trivial computation, replace the copy by rematerialize the definition.
145 /// If PreserveSrcInt is true, make sure SrcInt is valid after the call.
146 bool ReMaterializeTrivialDef(LiveInterval &SrcInt, bool PreserveSrcInt,
147 unsigned DstReg, MachineInstr *CopyMI);
149 /// shouldJoinPhys - Return true if a physreg copy should be joined.
150 bool shouldJoinPhys(CoalescerPair &CP);
152 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
153 /// two virtual registers from different register classes.
154 bool isWinToJoinCrossClass(unsigned SrcReg,
156 const TargetRegisterClass *SrcRC,
157 const TargetRegisterClass *DstRC,
158 const TargetRegisterClass *NewRC);
160 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
161 /// update the subregister number if it is not zero. If DstReg is a
162 /// physical register and the existing subregister number of the def / use
163 /// being updated is not zero, make sure to set it to the correct physical
165 void UpdateRegDefsUses(const CoalescerPair &CP);
167 /// RemoveDeadDef - If a def of a live interval is now determined dead,
168 /// remove the val# it defines. If the live interval becomes empty, remove
170 bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
172 /// markAsJoined - Remember that CopyMI has already been joined.
173 void markAsJoined(MachineInstr *CopyMI);
175 /// eliminateUndefCopy - Handle copies of undef values.
176 bool eliminateUndefCopy(MachineInstr *CopyMI, const CoalescerPair &CP);
179 static char ID; // Class identification, replacement for typeinfo
180 RegisterCoalescer() : MachineFunctionPass(ID) {
181 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
184 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
186 virtual void releaseMemory();
188 /// runOnMachineFunction - pass entry point
189 virtual bool runOnMachineFunction(MachineFunction&);
191 /// print - Implement the dump method.
192 virtual void print(raw_ostream &O, const Module* = 0) const;
194 } /// end anonymous namespace
196 char &llvm::RegisterCoalescerPassID = RegisterCoalescer::ID;
198 INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
199 "Simple Register Coalescing", false, false)
200 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
201 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
202 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
203 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
204 INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
205 INITIALIZE_PASS_DEPENDENCY(PHIElimination)
206 INITIALIZE_PASS_DEPENDENCY(TwoAddressInstructionPass)
207 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
208 INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
209 "Simple Register Coalescing", false, false)
211 char RegisterCoalescer::ID = 0;
213 static unsigned compose(const TargetRegisterInfo &tri, unsigned a, unsigned b) {
216 return tri.composeSubRegIndices(a, b);
219 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
220 unsigned &Src, unsigned &Dst,
221 unsigned &SrcSub, unsigned &DstSub) {
223 Dst = MI->getOperand(0).getReg();
224 DstSub = MI->getOperand(0).getSubReg();
225 Src = MI->getOperand(1).getReg();
226 SrcSub = MI->getOperand(1).getSubReg();
227 } else if (MI->isSubregToReg()) {
228 Dst = MI->getOperand(0).getReg();
229 DstSub = compose(tri, MI->getOperand(0).getSubReg(),
230 MI->getOperand(3).getImm());
231 Src = MI->getOperand(2).getReg();
232 SrcSub = MI->getOperand(2).getSubReg();
238 bool CoalescerPair::setRegisters(const MachineInstr *MI) {
239 SrcReg = DstReg = SubIdx = 0;
241 Flipped = CrossClass = false;
243 unsigned Src, Dst, SrcSub, DstSub;
244 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
246 Partial = SrcSub || DstSub;
248 // If one register is a physreg, it must be Dst.
249 if (TargetRegisterInfo::isPhysicalRegister(Src)) {
250 if (TargetRegisterInfo::isPhysicalRegister(Dst))
253 std::swap(SrcSub, DstSub);
257 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
259 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
260 // Eliminate DstSub on a physreg.
262 Dst = TRI.getSubReg(Dst, DstSub);
263 if (!Dst) return false;
267 // Eliminate SrcSub by picking a corresponding Dst superregister.
269 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
270 if (!Dst) return false;
272 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
276 // Both registers are virtual.
278 // Both registers have subreg indices.
279 if (SrcSub && DstSub) {
280 // For now we only handle the case of identical indices in commensurate
281 // registers: Dreg:ssub_1 + Dreg:ssub_1 -> Dreg
282 // FIXME: Handle Qreg:ssub_3 + Dreg:ssub_1 as QReg:dsub_1 + Dreg.
283 if (SrcSub != DstSub)
285 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
286 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
287 if (!TRI.getCommonSubClass(DstRC, SrcRC))
292 // There can be no SrcSub.
297 assert(!Flipped && "Unexpected flip");
301 // Find the new register class.
302 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
303 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
305 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
307 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
310 CrossClass = NewRC != DstRC || NewRC != SrcRC;
312 // Check our invariants
313 assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
314 assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
315 "Cannot have a physical SubIdx");
322 bool CoalescerPair::flip() {
323 if (SubIdx || TargetRegisterInfo::isPhysicalRegister(DstReg))
325 std::swap(SrcReg, DstReg);
330 bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
333 unsigned Src, Dst, SrcSub, DstSub;
334 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
337 // Find the virtual register that is SrcReg.
340 std::swap(SrcSub, DstSub);
341 } else if (Src != SrcReg) {
345 // Now check that Dst matches DstReg.
346 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
347 if (!TargetRegisterInfo::isPhysicalRegister(Dst))
349 assert(!SubIdx && "Inconsistent CoalescerPair state.");
350 // DstSub could be set for a physreg from INSERT_SUBREG.
352 Dst = TRI.getSubReg(Dst, DstSub);
355 return DstReg == Dst;
356 // This is a partial register copy. Check that the parts match.
357 return TRI.getSubReg(DstReg, SrcSub) == Dst;
359 // DstReg is virtual.
362 // Registers match, do the subregisters line up?
363 return compose(TRI, SubIdx, SrcSub) == DstSub;
367 void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
368 AU.setPreservesCFG();
369 AU.addRequired<AliasAnalysis>();
370 AU.addRequired<LiveIntervals>();
371 AU.addPreserved<LiveIntervals>();
372 AU.addRequired<LiveDebugVariables>();
373 AU.addPreserved<LiveDebugVariables>();
374 AU.addPreserved<SlotIndexes>();
375 AU.addRequired<MachineLoopInfo>();
376 AU.addPreserved<MachineLoopInfo>();
377 AU.addPreservedID(MachineDominatorsID);
378 AU.addPreservedID(StrongPHIEliminationID);
379 AU.addPreservedID(PHIEliminationID);
380 AU.addPreservedID(TwoAddressInstructionPassID);
381 MachineFunctionPass::getAnalysisUsage(AU);
384 void RegisterCoalescer::markAsJoined(MachineInstr *CopyMI) {
385 /// Joined copies are not deleted immediately, but kept in JoinedCopies.
386 JoinedCopies.insert(CopyMI);
388 /// Mark all register operands of CopyMI as <undef> so they won't affect dead
389 /// code elimination.
390 for (MachineInstr::mop_iterator I = CopyMI->operands_begin(),
391 E = CopyMI->operands_end(); I != E; ++I)
396 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
397 /// being the source and IntB being the dest, thus this defines a value number
398 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
399 /// see if we can merge these two pieces of B into a single value number,
400 /// eliminating a copy. For example:
404 /// B1 = A3 <- this copy
406 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
407 /// value number to be replaced with B0 (which simplifies the B liveinterval).
409 /// This returns true if an interval was modified.
411 bool RegisterCoalescer::AdjustCopiesBackFrom(const CoalescerPair &CP,
412 MachineInstr *CopyMI) {
413 // Bail if there is no dst interval - can happen when merging physical subreg
415 if (!LIS->hasInterval(CP.getDstReg()))
419 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
421 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
422 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
424 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
425 // the example above.
426 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
427 if (BLR == IntB.end()) return false;
428 VNInfo *BValNo = BLR->valno;
430 // Get the location that B is defined at. Two options: either this value has
431 // an unknown definition point or it is defined at CopyIdx. If unknown, we
433 if (BValNo->def != CopyIdx) return false;
435 // AValNo is the value number in A that defines the copy, A3 in the example.
436 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
437 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
438 // The live range might not exist after fun with physreg coalescing.
439 if (ALR == IntA.end()) return false;
440 VNInfo *AValNo = ALR->valno;
442 // If AValNo is defined as a copy from IntB, we can potentially process this.
443 // Get the instruction that defines this value number.
444 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
445 if (!CP.isCoalescable(ACopyMI))
448 // Get the LiveRange in IntB that this value number starts with.
449 LiveInterval::iterator ValLR =
450 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
451 if (ValLR == IntB.end())
454 // Make sure that the end of the live range is inside the same block as
456 MachineInstr *ValLREndInst =
457 LIS->getInstructionFromIndex(ValLR->end.getPrevSlot());
458 if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent())
461 // Okay, we now know that ValLR ends in the same block that the CopyMI
462 // live-range starts. If there are no intervening live ranges between them in
463 // IntB, we can merge them.
464 if (ValLR+1 != BLR) return false;
466 // If a live interval is a physical register, conservatively check if any
467 // of its aliases is overlapping the live interval of the virtual register.
468 // If so, do not coalesce.
469 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
470 for (const unsigned *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS)
471 if (LIS->hasInterval(*AS) && IntA.overlaps(LIS->getInterval(*AS))) {
473 dbgs() << "\t\tInterfere with alias ";
474 LIS->getInterval(*AS).print(dbgs(), TRI);
481 dbgs() << "Extending: ";
482 IntB.print(dbgs(), TRI);
485 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
486 // We are about to delete CopyMI, so need to remove it as the 'instruction
487 // that defines this value #'. Update the valnum with the new defining
489 BValNo->def = FillerStart;
491 // Okay, we can merge them. We need to insert a new liverange:
492 // [ValLR.end, BLR.begin) of either value number, then we merge the
493 // two value numbers.
494 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
496 // If the IntB live range is assigned to a physical register, and if that
497 // physreg has sub-registers, update their live intervals as well.
498 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
499 for (const unsigned *SR = TRI->getSubRegisters(IntB.reg); *SR; ++SR) {
500 if (!LIS->hasInterval(*SR))
502 LiveInterval &SRLI = LIS->getInterval(*SR);
503 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
504 SRLI.getNextValue(FillerStart,
505 LIS->getVNInfoAllocator())));
509 // Okay, merge "B1" into the same value number as "B0".
510 if (BValNo != ValLR->valno) {
511 // If B1 is killed by a PHI, then the merged live range must also be killed
512 // by the same PHI, as B0 and B1 can not overlap.
513 bool HasPHIKill = BValNo->hasPHIKill();
514 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
516 ValLR->valno->setHasPHIKill(true);
519 dbgs() << " result = ";
520 IntB.print(dbgs(), TRI);
524 // If the source instruction was killing the source register before the
525 // merge, unset the isKill marker given the live range has been extended.
526 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
528 ValLREndInst->getOperand(UIdx).setIsKill(false);
531 // Rewrite the copy. If the copy instruction was killing the destination
532 // register before the merge, find the last use and trim the live range. That
533 // will also add the isKill marker.
534 CopyMI->substituteRegister(IntA.reg, IntB.reg, CP.getSubIdx(),
536 if (ALR->end == CopyIdx)
537 LIS->shrinkToUses(&IntA);
543 /// HasOtherReachingDefs - Return true if there are definitions of IntB
544 /// other than BValNo val# that can reach uses of AValno val# of IntA.
545 bool RegisterCoalescer::HasOtherReachingDefs(LiveInterval &IntA,
549 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
551 if (AI->valno != AValNo) continue;
552 LiveInterval::Ranges::iterator BI =
553 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
554 if (BI != IntB.ranges.begin())
556 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
557 if (BI->valno == BValNo)
559 if (BI->start <= AI->start && BI->end > AI->start)
561 if (BI->start > AI->start && BI->start < AI->end)
568 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with
569 /// IntA being the source and IntB being the dest, thus this defines a value
570 /// number in IntB. If the source value number (in IntA) is defined by a
571 /// commutable instruction and its other operand is coalesced to the copy dest
572 /// register, see if we can transform the copy into a noop by commuting the
573 /// definition. For example,
575 /// A3 = op A2 B0<kill>
577 /// B1 = A3 <- this copy
579 /// = op A3 <- more uses
583 /// B2 = op B0 A2<kill>
585 /// B1 = B2 <- now an identify copy
587 /// = op B2 <- more uses
589 /// This returns true if an interval was modified.
591 bool RegisterCoalescer::RemoveCopyByCommutingDef(const CoalescerPair &CP,
592 MachineInstr *CopyMI) {
593 // FIXME: For now, only eliminate the copy by commuting its def when the
594 // source register is a virtual register. We want to guard against cases
595 // where the copy is a back edge copy and commuting the def lengthen the
596 // live interval of the source register to the entire loop.
597 if (CP.isPhys() && CP.isFlipped())
600 // Bail if there is no dst interval.
601 if (!LIS->hasInterval(CP.getDstReg()))
604 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
607 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
609 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
611 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
612 // the example above.
613 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
614 if (!BValNo || BValNo->def != CopyIdx)
617 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
619 // AValNo is the value number in A that defines the copy, A3 in the example.
620 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
621 assert(AValNo && "COPY source not live");
623 // If other defs can reach uses of this def, then it's not safe to perform
625 if (AValNo->isPHIDef() || AValNo->isUnused() || AValNo->hasPHIKill())
627 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
630 if (!DefMI->isCommutable())
632 // If DefMI is a two-address instruction then commuting it will change the
633 // destination register.
634 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
635 assert(DefIdx != -1);
637 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
639 unsigned Op1, Op2, NewDstIdx;
640 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
644 else if (Op2 == UseOpIdx)
649 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
650 unsigned NewReg = NewDstMO.getReg();
651 if (NewReg != IntB.reg || !NewDstMO.isKill())
654 // Make sure there are no other definitions of IntB that would reach the
655 // uses which the new definition can reach.
656 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
659 // Abort if the aliases of IntB.reg have values that are not simply the
660 // clobbers from the superreg.
661 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
662 for (const unsigned *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS)
663 if (LIS->hasInterval(*AS) &&
664 HasOtherReachingDefs(IntA, LIS->getInterval(*AS), AValNo, 0))
667 // If some of the uses of IntA.reg is already coalesced away, return false.
668 // It's not possible to determine whether it's safe to perform the coalescing.
669 for (MachineRegisterInfo::use_nodbg_iterator UI =
670 MRI->use_nodbg_begin(IntA.reg),
671 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
672 MachineInstr *UseMI = &*UI;
673 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
674 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
675 if (ULR == IntA.end())
677 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
681 DEBUG(dbgs() << "\tRemoveCopyByCommutingDef: " << AValNo->def << '\t'
684 // At this point we have decided that it is legal to do this
685 // transformation. Start by commuting the instruction.
686 MachineBasicBlock *MBB = DefMI->getParent();
687 MachineInstr *NewMI = TII->commuteInstruction(DefMI);
690 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
691 TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
692 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
694 if (NewMI != DefMI) {
695 LIS->ReplaceMachineInstrInMaps(DefMI, NewMI);
696 MachineBasicBlock::iterator Pos = DefMI;
697 MBB->insert(Pos, NewMI);
700 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
701 NewMI->getOperand(OpIdx).setIsKill();
703 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
712 // Update uses of IntA of the specific Val# with IntB.
713 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
714 UE = MRI->use_end(); UI != UE;) {
715 MachineOperand &UseMO = UI.getOperand();
716 MachineInstr *UseMI = &*UI;
718 if (JoinedCopies.count(UseMI))
720 if (UseMI->isDebugValue()) {
721 // FIXME These don't have an instruction index. Not clear we have enough
722 // info to decide whether to do this replacement or not. For now do it.
723 UseMO.setReg(NewReg);
726 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
727 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
728 if (ULR == IntA.end() || ULR->valno != AValNo)
730 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
731 UseMO.substPhysReg(NewReg, *TRI);
733 UseMO.setReg(NewReg);
736 if (!UseMI->isCopy())
738 if (UseMI->getOperand(0).getReg() != IntB.reg ||
739 UseMI->getOperand(0).getSubReg())
742 // This copy will become a noop. If it's defining a new val#, merge it into
744 SlotIndex DefIdx = UseIdx.getRegSlot();
745 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
748 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
749 assert(DVNI->def == DefIdx);
750 BValNo = IntB.MergeValueNumberInto(BValNo, DVNI);
754 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
756 VNInfo *ValNo = BValNo;
757 ValNo->def = AValNo->def;
758 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
760 if (AI->valno != AValNo) continue;
761 IntB.addRange(LiveRange(AI->start, AI->end, ValNo));
763 DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
765 IntA.removeValNo(AValNo);
766 DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
771 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
772 /// computation, replace the copy by rematerialize the definition.
773 bool RegisterCoalescer::ReMaterializeTrivialDef(LiveInterval &SrcInt,
776 MachineInstr *CopyMI) {
777 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
778 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
779 assert(SrcLR != SrcInt.end() && "Live range not found!");
780 VNInfo *ValNo = SrcLR->valno;
781 if (ValNo->isPHIDef() || ValNo->isUnused())
783 MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
786 assert(DefMI && "Defining instruction disappeared");
787 if (!DefMI->isAsCheapAsAMove())
789 if (!TII->isTriviallyReMaterializable(DefMI, AA))
791 bool SawStore = false;
792 if (!DefMI->isSafeToMove(TII, AA, SawStore))
794 const MCInstrDesc &MCID = DefMI->getDesc();
795 if (MCID.getNumDefs() != 1)
797 if (!DefMI->isImplicitDef()) {
798 // Make sure the copy destination register class fits the instruction
799 // definition register class. The mismatch can happen as a result of earlier
800 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
801 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI);
802 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
803 if (MRI->getRegClass(DstReg) != RC)
805 } else if (!RC->contains(DstReg))
809 MachineBasicBlock *MBB = CopyMI->getParent();
810 MachineBasicBlock::iterator MII =
811 llvm::next(MachineBasicBlock::iterator(CopyMI));
812 TII->reMaterialize(*MBB, MII, DstReg, 0, DefMI, *TRI);
813 MachineInstr *NewMI = prior(MII);
815 // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
816 // We need to remember these so we can add intervals once we insert
817 // NewMI into SlotIndexes.
818 SmallVector<unsigned, 4> NewMIImplDefs;
819 for (unsigned i = NewMI->getDesc().getNumOperands(),
820 e = NewMI->getNumOperands(); i != e; ++i) {
821 MachineOperand &MO = NewMI->getOperand(i);
823 assert(MO.isDef() && MO.isImplicit() && MO.isDead());
824 NewMIImplDefs.push_back(MO.getReg());
828 // CopyMI may have implicit operands, transfer them over to the newly
829 // rematerialized instruction. And update implicit def interval valnos.
830 for (unsigned i = CopyMI->getDesc().getNumOperands(),
831 e = CopyMI->getNumOperands(); i != e; ++i) {
832 MachineOperand &MO = CopyMI->getOperand(i);
833 if (MO.isReg() && MO.isImplicit())
834 NewMI->addOperand(MO);
837 LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
839 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
840 for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
841 unsigned reg = NewMIImplDefs[i];
842 LiveInterval &li = LIS->getInterval(reg);
843 VNInfo *DeadDefVN = li.getNextValue(NewMIIdx.getRegSlot(),
844 LIS->getVNInfoAllocator());
845 LiveRange lr(NewMIIdx.getRegSlot(), NewMIIdx.getDeadSlot(), DeadDefVN);
849 NewMI->copyImplicitOps(CopyMI);
850 CopyMI->eraseFromParent();
851 ReMatCopies.insert(CopyMI);
852 ReMatDefs.insert(DefMI);
853 DEBUG(dbgs() << "Remat: " << *NewMI);
856 // The source interval can become smaller because we removed a use.
858 LIS->shrinkToUses(&SrcInt);
863 /// eliminateUndefCopy - ProcessImpicitDefs may leave some copies of <undef>
864 /// values, it only removes local variables. When we have a copy like:
866 /// %vreg1 = COPY %vreg2<undef>
868 /// We delete the copy and remove the corresponding value number from %vreg1.
869 /// Any uses of that value number are marked as <undef>.
870 bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI,
871 const CoalescerPair &CP) {
872 SlotIndex Idx = LIS->getInstructionIndex(CopyMI);
873 LiveInterval *SrcInt = &LIS->getInterval(CP.getSrcReg());
874 if (SrcInt->liveAt(Idx))
876 LiveInterval *DstInt = &LIS->getInterval(CP.getDstReg());
877 if (DstInt->liveAt(Idx))
880 // No intervals are live-in to CopyMI - it is undef.
885 VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getRegSlot());
886 assert(DeadVNI && "No value defined in DstInt");
887 DstInt->removeValNo(DeadVNI);
889 // Find new undef uses.
890 for (MachineRegisterInfo::reg_nodbg_iterator
891 I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end();
893 MachineOperand &MO = I.getOperand();
894 if (MO.isDef() || MO.isUndef())
896 MachineInstr *MI = MO.getParent();
897 SlotIndex Idx = LIS->getInstructionIndex(MI);
898 if (DstInt->liveAt(Idx))
901 DEBUG(dbgs() << "\tnew undef: " << Idx << '\t' << *MI);
906 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
907 /// update the subregister number if it is not zero. If DstReg is a
908 /// physical register and the existing subregister number of the def / use
909 /// being updated is not zero, make sure to set it to the correct physical
912 RegisterCoalescer::UpdateRegDefsUses(const CoalescerPair &CP) {
913 bool DstIsPhys = CP.isPhys();
914 unsigned SrcReg = CP.getSrcReg();
915 unsigned DstReg = CP.getDstReg();
916 unsigned SubIdx = CP.getSubIdx();
918 // Update LiveDebugVariables.
919 LDV->renameRegister(SrcReg, DstReg, SubIdx);
921 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);
922 MachineInstr *UseMI = I.skipInstruction();) {
923 // A PhysReg copy that won't be coalesced can perhaps be rematerialized
926 if (UseMI->isFullCopy() &&
927 UseMI->getOperand(1).getReg() == SrcReg &&
928 UseMI->getOperand(0).getReg() != SrcReg &&
929 UseMI->getOperand(0).getReg() != DstReg &&
930 !JoinedCopies.count(UseMI) &&
931 ReMaterializeTrivialDef(LIS->getInterval(SrcReg), false,
932 UseMI->getOperand(0).getReg(), UseMI))
936 SmallVector<unsigned,8> Ops;
938 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
939 bool Kills = false, Deads = false;
941 // Replace SrcReg with DstReg in all UseMI operands.
942 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
943 MachineOperand &MO = UseMI->getOperand(Ops[i]);
944 Kills |= MO.isKill();
945 Deads |= MO.isDead();
947 // Make sure we don't create read-modify-write defs accidentally. We
948 // assume here that a SrcReg def cannot be joined into a live DstReg. If
949 // RegisterCoalescer starts tracking partially live registers, we will
950 // need to check the actual LiveInterval to determine if DstReg is live
952 if (SubIdx && !Reads)
956 MO.substPhysReg(DstReg, *TRI);
958 MO.substVirtReg(DstReg, SubIdx, *TRI);
961 // This instruction is a copy that will be removed.
962 if (JoinedCopies.count(UseMI))
966 // If UseMI was a simple SrcReg def, make sure we didn't turn it into a
967 // read-modify-write of DstReg.
969 UseMI->addRegisterDead(DstReg, TRI);
970 else if (!Reads && Writes)
971 UseMI->addRegisterDefined(DstReg, TRI);
973 // Kill flags apply to the whole physical register.
974 if (DstIsPhys && Kills)
975 UseMI->addRegisterKilled(DstReg, TRI);
979 dbgs() << "\t\tupdated: ";
980 if (!UseMI->isDebugValue())
981 dbgs() << LIS->getInstructionIndex(UseMI) << "\t";
987 /// removeIntervalIfEmpty - Check if the live interval of a physical register
988 /// is empty, if so remove it and also remove the empty intervals of its
989 /// sub-registers. Return true if live interval is removed.
990 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *LIS,
991 const TargetRegisterInfo *TRI) {
993 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
994 for (const unsigned* SR = TRI->getSubRegisters(li.reg); *SR; ++SR) {
995 if (!LIS->hasInterval(*SR))
997 LiveInterval &sli = LIS->getInterval(*SR);
999 LIS->removeInterval(*SR);
1001 LIS->removeInterval(li.reg);
1007 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
1008 /// the val# it defines. If the live interval becomes empty, remove it as well.
1009 bool RegisterCoalescer::RemoveDeadDef(LiveInterval &li,
1010 MachineInstr *DefMI) {
1011 SlotIndex DefIdx = LIS->getInstructionIndex(DefMI).getRegSlot();
1012 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
1013 if (DefIdx != MLR->valno->def)
1015 li.removeValNo(MLR->valno);
1016 return removeIntervalIfEmpty(li, LIS, TRI);
1019 /// shouldJoinPhys - Return true if a copy involving a physreg should be joined.
1020 /// We need to be careful about coalescing a source physical register with a
1021 /// virtual register. Once the coalescing is done, it cannot be broken and these
1022 /// are not spillable! If the destination interval uses are far away, think
1023 /// twice about coalescing them!
1024 bool RegisterCoalescer::shouldJoinPhys(CoalescerPair &CP) {
1025 bool Allocatable = LIS->isAllocatable(CP.getDstReg());
1026 LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
1028 /// Always join simple intervals that are defined by a single copy from a
1029 /// reserved register. This doesn't increase register pressure, so it is
1030 /// always beneficial.
1031 if (!Allocatable && CP.isFlipped() && JoinVInt.containsOneValue())
1034 if (!EnablePhysicalJoin) {
1035 DEBUG(dbgs() << "\tPhysreg joins disabled.\n");
1039 // Only coalesce to allocatable physreg, we don't want to risk modifying
1040 // reserved registers.
1042 DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n");
1043 return false; // Not coalescable.
1046 // Don't join with physregs that have a ridiculous number of live
1047 // ranges. The data structure performance is really bad when that
1049 if (LIS->hasInterval(CP.getDstReg()) &&
1050 LIS->getInterval(CP.getDstReg()).ranges.size() > 1000) {
1053 << "\tPhysical register live interval too complicated, abort!\n");
1057 // FIXME: Why are we skipping this test for partial copies?
1058 // CodeGen/X86/phys_subreg_coalesce-3.ll needs it.
1059 if (!CP.isPartial()) {
1060 const TargetRegisterClass *RC = MRI->getRegClass(CP.getSrcReg());
1061 unsigned Threshold = RegClassInfo.getNumAllocatableRegs(RC) * 2;
1062 unsigned Length = LIS->getApproximateInstructionCount(JoinVInt);
1063 if (Length > Threshold) {
1065 DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
1072 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
1073 /// two virtual registers from different register classes.
1075 RegisterCoalescer::isWinToJoinCrossClass(unsigned SrcReg,
1077 const TargetRegisterClass *SrcRC,
1078 const TargetRegisterClass *DstRC,
1079 const TargetRegisterClass *NewRC) {
1080 unsigned NewRCCount = RegClassInfo.getNumAllocatableRegs(NewRC);
1081 // This heuristics is good enough in practice, but it's obviously not *right*.
1082 // 4 is a magic number that works well enough for x86, ARM, etc. It filter
1083 // out all but the most restrictive register classes.
1084 if (NewRCCount > 4 ||
1085 // Early exit if the function is fairly small, coalesce aggressively if
1086 // that's the case. For really special register classes with 3 or
1087 // fewer registers, be a bit more careful.
1088 (LIS->getFuncInstructionCount() / NewRCCount) < 8)
1090 LiveInterval &SrcInt = LIS->getInterval(SrcReg);
1091 LiveInterval &DstInt = LIS->getInterval(DstReg);
1092 unsigned SrcSize = LIS->getApproximateInstructionCount(SrcInt);
1093 unsigned DstSize = LIS->getApproximateInstructionCount(DstInt);
1095 // Coalesce aggressively if the intervals are small compared to the number of
1096 // registers in the new class. The number 4 is fairly arbitrary, chosen to be
1097 // less aggressive than the 8 used for the whole function size.
1098 const unsigned ThresSize = 4 * NewRCCount;
1099 if (SrcSize <= ThresSize && DstSize <= ThresSize)
1102 // Estimate *register use density*. If it doubles or more, abort.
1103 unsigned SrcUses = std::distance(MRI->use_nodbg_begin(SrcReg),
1104 MRI->use_nodbg_end());
1105 unsigned DstUses = std::distance(MRI->use_nodbg_begin(DstReg),
1106 MRI->use_nodbg_end());
1107 unsigned NewUses = SrcUses + DstUses;
1108 unsigned NewSize = SrcSize + DstSize;
1109 if (SrcRC != NewRC && SrcSize > ThresSize) {
1110 unsigned SrcRCCount = RegClassInfo.getNumAllocatableRegs(SrcRC);
1111 if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount)
1114 if (DstRC != NewRC && DstSize > ThresSize) {
1115 unsigned DstRCCount = RegClassInfo.getNumAllocatableRegs(DstRC);
1116 if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount)
1123 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1124 /// which are the src/dst of the copy instruction CopyMI. This returns true
1125 /// if the copy was successfully coalesced away. If it is not currently
1126 /// possible to coalesce this interval, but it may be possible if other
1127 /// things get coalesced, then it returns true by reference in 'Again'.
1128 bool RegisterCoalescer::JoinCopy(MachineInstr *CopyMI, bool &Again) {
1131 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1132 return false; // Already done.
1134 DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1136 CoalescerPair CP(*TII, *TRI);
1137 if (!CP.setRegisters(CopyMI)) {
1138 DEBUG(dbgs() << "\tNot coalescable.\n");
1142 // If they are already joined we continue.
1143 if (CP.getSrcReg() == CP.getDstReg()) {
1144 markAsJoined(CopyMI);
1145 DEBUG(dbgs() << "\tCopy already coalesced.\n");
1146 return false; // Not coalescable.
1149 // Eliminate undefs.
1150 if (!CP.isPhys() && eliminateUndefCopy(CopyMI, CP)) {
1151 markAsJoined(CopyMI);
1152 DEBUG(dbgs() << "\tEliminated copy of <undef> value.\n");
1153 return false; // Not coalescable.
1156 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI)
1157 << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSubIdx())
1160 // Enforce policies.
1162 if (!shouldJoinPhys(CP)) {
1163 // Before giving up coalescing, if definition of source is defined by
1164 // trivial computation, try rematerializing it.
1165 if (!CP.isFlipped() &&
1166 ReMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()), true,
1167 CP.getDstReg(), CopyMI))
1172 // Avoid constraining virtual register regclass too much.
1173 if (CP.isCrossClass()) {
1174 DEBUG(dbgs() << "\tCross-class to " << CP.getNewRC()->getName() << ".\n");
1175 if (DisableCrossClassJoin) {
1176 DEBUG(dbgs() << "\tCross-class joins disabled.\n");
1179 if (!isWinToJoinCrossClass(CP.getSrcReg(), CP.getDstReg(),
1180 MRI->getRegClass(CP.getSrcReg()),
1181 MRI->getRegClass(CP.getDstReg()),
1183 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class.\n");
1184 Again = true; // May be possible to coalesce later.
1189 // When possible, let DstReg be the larger interval.
1190 if (!CP.getSubIdx() && LIS->getInterval(CP.getSrcReg()).ranges.size() >
1191 LIS->getInterval(CP.getDstReg()).ranges.size())
1195 // Okay, attempt to join these two intervals. On failure, this returns false.
1196 // Otherwise, if one of the intervals being joined is a physreg, this method
1197 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1198 // been modified, so we can use this information below to update aliases.
1199 if (!JoinIntervals(CP)) {
1200 // Coalescing failed.
1202 // If definition of source is defined by trivial computation, try
1203 // rematerializing it.
1204 if (!CP.isFlipped() &&
1205 ReMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()), true,
1206 CP.getDstReg(), CopyMI))
1209 // If we can eliminate the copy without merging the live ranges, do so now.
1210 if (!CP.isPartial()) {
1211 if (AdjustCopiesBackFrom(CP, CopyMI) ||
1212 RemoveCopyByCommutingDef(CP, CopyMI)) {
1213 markAsJoined(CopyMI);
1214 DEBUG(dbgs() << "\tTrivial!\n");
1219 // Otherwise, we are unable to join the intervals.
1220 DEBUG(dbgs() << "\tInterference!\n");
1221 Again = true; // May be possible to coalesce later.
1225 // Coalescing to a virtual register that is of a sub-register class of the
1226 // other. Make sure the resulting register is set to the right register class.
1227 if (CP.isCrossClass()) {
1229 MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
1232 // Remember to delete the copy instruction.
1233 markAsJoined(CopyMI);
1235 UpdateRegDefsUses(CP);
1237 // If we have extended the live range of a physical register, make sure we
1238 // update live-in lists as well.
1240 SmallVector<MachineBasicBlock*, 16> BlockSeq;
1241 // JoinIntervals invalidates the VNInfos in SrcInt, but we only need the
1242 // ranges for this, and they are preserved.
1243 LiveInterval &SrcInt = LIS->getInterval(CP.getSrcReg());
1244 for (LiveInterval::const_iterator I = SrcInt.begin(), E = SrcInt.end();
1246 LIS->findLiveInMBBs(I->start, I->end, BlockSeq);
1247 for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) {
1248 MachineBasicBlock &block = *BlockSeq[idx];
1249 if (!block.isLiveIn(CP.getDstReg()))
1250 block.addLiveIn(CP.getDstReg());
1256 // SrcReg is guaranteed to be the register whose live interval that is
1258 LIS->removeInterval(CP.getSrcReg());
1260 // Update regalloc hint.
1261 TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
1264 LiveInterval &DstInt = LIS->getInterval(CP.getDstReg());
1265 dbgs() << "\tJoined. Result = ";
1266 DstInt.print(dbgs(), TRI);
1274 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1275 /// compute what the resultant value numbers for each value in the input two
1276 /// ranges will be. This is complicated by copies between the two which can
1277 /// and will commonly cause multiple value numbers to be merged into one.
1279 /// VN is the value number that we're trying to resolve. InstDefiningValue
1280 /// keeps track of the new InstDefiningValue assignment for the result
1281 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1282 /// whether a value in this or other is a copy from the opposite set.
1283 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1284 /// already been assigned.
1286 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1287 /// contains the value number the copy is from.
1289 static unsigned ComputeUltimateVN(VNInfo *VNI,
1290 SmallVector<VNInfo*, 16> &NewVNInfo,
1291 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1292 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1293 SmallVector<int, 16> &ThisValNoAssignments,
1294 SmallVector<int, 16> &OtherValNoAssignments) {
1295 unsigned VN = VNI->id;
1297 // If the VN has already been computed, just return it.
1298 if (ThisValNoAssignments[VN] >= 0)
1299 return ThisValNoAssignments[VN];
1300 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1302 // If this val is not a copy from the other val, then it must be a new value
1303 // number in the destination.
1304 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1305 if (I == ThisFromOther.end()) {
1306 NewVNInfo.push_back(VNI);
1307 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1309 VNInfo *OtherValNo = I->second;
1311 // Otherwise, this *is* a copy from the RHS. If the other side has already
1312 // been computed, return it.
1313 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1314 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1316 // Mark this value number as currently being computed, then ask what the
1317 // ultimate value # of the other value is.
1318 ThisValNoAssignments[VN] = -2;
1319 unsigned UltimateVN =
1320 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1321 OtherValNoAssignments, ThisValNoAssignments);
1322 return ThisValNoAssignments[VN] = UltimateVN;
1326 // Find out if we have something like
1329 // if so, we can pretend this is actually
1332 // which allows us to coalesce A and B.
1333 // VNI is the definition of B. LR is the life range of A that includes
1334 // the slot just before B. If we return true, we add "B = X" to DupCopies.
1335 // This implies that A dominates B.
1336 static bool RegistersDefinedFromSameValue(LiveIntervals &li,
1337 const TargetRegisterInfo &tri,
1341 SmallVector<MachineInstr*, 8> &DupCopies) {
1342 // FIXME: This is very conservative. For example, we don't handle
1343 // physical registers.
1345 MachineInstr *MI = li.getInstructionFromIndex(VNI->def);
1347 if (!MI || !MI->isFullCopy() || CP.isPartial() || CP.isPhys())
1350 unsigned Dst = MI->getOperand(0).getReg();
1351 unsigned Src = MI->getOperand(1).getReg();
1353 if (!TargetRegisterInfo::isVirtualRegister(Src) ||
1354 !TargetRegisterInfo::isVirtualRegister(Dst))
1357 unsigned A = CP.getDstReg();
1358 unsigned B = CP.getSrcReg();
1364 VNInfo *Other = LR->valno;
1365 const MachineInstr *OtherMI = li.getInstructionFromIndex(Other->def);
1367 if (!OtherMI || !OtherMI->isFullCopy())
1370 unsigned OtherDst = OtherMI->getOperand(0).getReg();
1371 unsigned OtherSrc = OtherMI->getOperand(1).getReg();
1373 if (!TargetRegisterInfo::isVirtualRegister(OtherSrc) ||
1374 !TargetRegisterInfo::isVirtualRegister(OtherDst))
1377 assert(OtherDst == B);
1379 if (Src != OtherSrc)
1382 // If the copies use two different value numbers of X, we cannot merge
1384 LiveInterval &SrcInt = li.getInterval(Src);
1385 // getVNInfoBefore returns NULL for undef copies. In this case, the
1386 // optimization is still safe.
1387 if (SrcInt.getVNInfoBefore(Other->def) != SrcInt.getVNInfoBefore(VNI->def))
1390 DupCopies.push_back(MI);
1395 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1397 bool RegisterCoalescer::JoinIntervals(CoalescerPair &CP) {
1398 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1399 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), TRI); dbgs() << "\n"; });
1401 // If a live interval is a physical register, check for interference with any
1402 // aliases. The interference check implemented here is a bit more conservative
1403 // than the full interfeence check below. We allow overlapping live ranges
1404 // only when one is a copy of the other.
1406 // Optimization for reserved registers like ESP.
1407 // We can only merge with a reserved physreg if RHS has a single value that
1408 // is a copy of CP.DstReg(). The live range of the reserved register will
1409 // look like a set of dead defs - we don't properly track the live range of
1410 // reserved registers.
1411 if (RegClassInfo.isReserved(CP.getDstReg())) {
1412 assert(CP.isFlipped() && RHS.containsOneValue() &&
1413 "Invalid join with reserved register");
1414 // Deny any overlapping intervals. This depends on all the reserved
1415 // register live ranges to look like dead defs.
1416 for (const unsigned *AS = TRI->getOverlaps(CP.getDstReg()); *AS; ++AS) {
1417 if (!LIS->hasInterval(*AS)) {
1418 // Make sure at least DstReg itself exists before attempting a join.
1419 if (*AS == CP.getDstReg())
1420 LIS->getOrCreateInterval(CP.getDstReg());
1423 if (RHS.overlaps(LIS->getInterval(*AS))) {
1424 DEBUG(dbgs() << "\t\tInterference: " << PrintReg(*AS, TRI) << '\n');
1428 // Skip any value computations, we are not adding new values to the
1429 // reserved register. Also skip merging the live ranges, the reserved
1430 // register live range doesn't need to be accurate as long as all the
1435 for (const unsigned *AS = TRI->getAliasSet(CP.getDstReg()); *AS; ++AS){
1436 if (!LIS->hasInterval(*AS))
1438 const LiveInterval &LHS = LIS->getInterval(*AS);
1439 LiveInterval::const_iterator LI = LHS.begin();
1440 for (LiveInterval::const_iterator RI = RHS.begin(), RE = RHS.end();
1442 LI = std::lower_bound(LI, LHS.end(), RI->start);
1443 // Does LHS have an overlapping live range starting before RI?
1444 if ((LI != LHS.begin() && LI[-1].end > RI->start) &&
1445 (RI->start != RI->valno->def ||
1446 !CP.isCoalescable(LIS->getInstructionFromIndex(RI->start)))) {
1448 dbgs() << "\t\tInterference from alias: ";
1449 LHS.print(dbgs(), TRI);
1450 dbgs() << "\n\t\tOverlap at " << RI->start << " and no copy.\n";
1455 // Check that LHS ranges beginning in this range are copies.
1456 for (; LI != LHS.end() && LI->start < RI->end; ++LI) {
1457 if (LI->start != LI->valno->def ||
1458 !CP.isCoalescable(LIS->getInstructionFromIndex(LI->start))) {
1460 dbgs() << "\t\tInterference from alias: ";
1461 LHS.print(dbgs(), TRI);
1462 dbgs() << "\n\t\tDef at " << LI->start << " is not a copy.\n";
1471 // Compute the final value assignment, assuming that the live ranges can be
1473 SmallVector<int, 16> LHSValNoAssignments;
1474 SmallVector<int, 16> RHSValNoAssignments;
1475 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1476 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1477 SmallVector<VNInfo*, 16> NewVNInfo;
1479 SmallVector<MachineInstr*, 8> DupCopies;
1481 LiveInterval &LHS = LIS->getOrCreateInterval(CP.getDstReg());
1482 DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), TRI); dbgs() << "\n"; });
1484 // Loop over the value numbers of the LHS, seeing if any are defined from
1486 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1489 if (VNI->isUnused() || VNI->isPHIDef())
1491 MachineInstr *MI = LIS->getInstructionFromIndex(VNI->def);
1492 assert(MI && "Missing def");
1493 if (!MI->isCopyLike()) // Src not defined by a copy?
1496 // Figure out the value # from the RHS.
1497 LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1498 // The copy could be to an aliased physreg.
1501 // DstReg is known to be a register in the LHS interval. If the src is
1502 // from the RHS interval, we can use its value #.
1503 if (!CP.isCoalescable(MI) &&
1504 !RegistersDefinedFromSameValue(*LIS, *TRI, CP, VNI, lr, DupCopies))
1507 LHSValsDefinedFromRHS[VNI] = lr->valno;
1510 // Loop over the value numbers of the RHS, seeing if any are defined from
1512 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1515 if (VNI->isUnused() || VNI->isPHIDef())
1517 MachineInstr *MI = LIS->getInstructionFromIndex(VNI->def);
1518 assert(MI && "Missing def");
1519 if (!MI->isCopyLike()) // Src not defined by a copy?
1522 // Figure out the value # from the LHS.
1523 LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1524 // The copy could be to an aliased physreg.
1527 // DstReg is known to be a register in the RHS interval. If the src is
1528 // from the LHS interval, we can use its value #.
1529 if (!CP.isCoalescable(MI) &&
1530 !RegistersDefinedFromSameValue(*LIS, *TRI, CP, VNI, lr, DupCopies))
1533 RHSValsDefinedFromLHS[VNI] = lr->valno;
1536 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1537 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1538 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1540 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1543 unsigned VN = VNI->id;
1544 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1546 ComputeUltimateVN(VNI, NewVNInfo,
1547 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1548 LHSValNoAssignments, RHSValNoAssignments);
1550 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1553 unsigned VN = VNI->id;
1554 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1556 // If this value number isn't a copy from the LHS, it's a new number.
1557 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1558 NewVNInfo.push_back(VNI);
1559 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1563 ComputeUltimateVN(VNI, NewVNInfo,
1564 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1565 RHSValNoAssignments, LHSValNoAssignments);
1568 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1569 // interval lists to see if these intervals are coalescable.
1570 LiveInterval::const_iterator I = LHS.begin();
1571 LiveInterval::const_iterator IE = LHS.end();
1572 LiveInterval::const_iterator J = RHS.begin();
1573 LiveInterval::const_iterator JE = RHS.end();
1575 // Skip ahead until the first place of potential sharing.
1576 if (I != IE && J != JE) {
1577 if (I->start < J->start) {
1578 I = std::upper_bound(I, IE, J->start);
1579 if (I != LHS.begin()) --I;
1580 } else if (J->start < I->start) {
1581 J = std::upper_bound(J, JE, I->start);
1582 if (J != RHS.begin()) --J;
1586 while (I != IE && J != JE) {
1587 // Determine if these two live ranges overlap.
1589 if (I->start < J->start) {
1590 Overlaps = I->end > J->start;
1592 Overlaps = J->end > I->start;
1595 // If so, check value # info to determine if they are really different.
1597 // If the live range overlap will map to the same value number in the
1598 // result liverange, we can still coalesce them. If not, we can't.
1599 if (LHSValNoAssignments[I->valno->id] !=
1600 RHSValNoAssignments[J->valno->id])
1604 if (I->end < J->end)
1610 // Update kill info. Some live ranges are extended due to copy coalescing.
1611 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1612 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1613 VNInfo *VNI = I->first;
1614 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1615 if (VNI->hasPHIKill())
1616 NewVNInfo[LHSValID]->setHasPHIKill(true);
1619 // Update kill info. Some live ranges are extended due to copy coalescing.
1620 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1621 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1622 VNInfo *VNI = I->first;
1623 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1624 if (VNI->hasPHIKill())
1625 NewVNInfo[RHSValID]->setHasPHIKill(true);
1628 if (LHSValNoAssignments.empty())
1629 LHSValNoAssignments.push_back(-1);
1630 if (RHSValNoAssignments.empty())
1631 RHSValNoAssignments.push_back(-1);
1633 SmallVector<unsigned, 8> SourceRegisters;
1634 for (SmallVector<MachineInstr*, 8>::iterator I = DupCopies.begin(),
1635 E = DupCopies.end(); I != E; ++I) {
1636 MachineInstr *MI = *I;
1638 // We have pretended that the assignment to B in
1641 // was actually a copy from A. Now that we decided to coalesce A and B,
1642 // transform the code into
1645 // and mark the X as coalesced to keep the illusion.
1646 unsigned Src = MI->getOperand(1).getReg();
1647 SourceRegisters.push_back(Src);
1648 MI->getOperand(0).substVirtReg(Src, 0, *TRI);
1653 // If B = X was the last use of X in a liverange, we have to shrink it now
1654 // that B = X is gone.
1655 for (SmallVector<unsigned, 8>::iterator I = SourceRegisters.begin(),
1656 E = SourceRegisters.end(); I != E; ++I) {
1657 LIS->shrinkToUses(&LIS->getInterval(*I));
1660 // If we get here, we know that we can coalesce the live ranges. Ask the
1661 // intervals to coalesce themselves now.
1662 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
1668 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1669 // depth of the basic block (the unsigned), and then on the MBB number.
1670 struct DepthMBBCompare {
1671 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1672 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1673 // Deeper loops first
1674 if (LHS.first != RHS.first)
1675 return LHS.first > RHS.first;
1677 // Prefer blocks that are more connected in the CFG. This takes care of
1678 // the most difficult copies first while intervals are short.
1679 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
1680 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
1684 // As a last resort, sort by block number.
1685 return LHS.second->getNumber() < RHS.second->getNumber();
1690 void RegisterCoalescer::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1691 std::vector<MachineInstr*> &TryAgain) {
1692 DEBUG(dbgs() << MBB->getName() << ":\n");
1694 SmallVector<MachineInstr*, 8> VirtCopies;
1695 SmallVector<MachineInstr*, 8> PhysCopies;
1696 SmallVector<MachineInstr*, 8> ImpDefCopies;
1697 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1699 MachineInstr *Inst = MII++;
1701 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1702 unsigned SrcReg, DstReg;
1703 if (Inst->isCopy()) {
1704 DstReg = Inst->getOperand(0).getReg();
1705 SrcReg = Inst->getOperand(1).getReg();
1706 } else if (Inst->isSubregToReg()) {
1707 DstReg = Inst->getOperand(0).getReg();
1708 SrcReg = Inst->getOperand(2).getReg();
1712 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1713 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1714 if (LIS->hasInterval(SrcReg) && LIS->getInterval(SrcReg).empty())
1715 ImpDefCopies.push_back(Inst);
1716 else if (SrcIsPhys || DstIsPhys)
1717 PhysCopies.push_back(Inst);
1719 VirtCopies.push_back(Inst);
1722 // Try coalescing implicit copies and insert_subreg <undef> first,
1723 // followed by copies to / from physical registers, then finally copies
1724 // from virtual registers to virtual registers.
1725 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
1726 MachineInstr *TheCopy = ImpDefCopies[i];
1728 if (!JoinCopy(TheCopy, Again))
1730 TryAgain.push_back(TheCopy);
1732 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
1733 MachineInstr *TheCopy = PhysCopies[i];
1735 if (!JoinCopy(TheCopy, Again))
1737 TryAgain.push_back(TheCopy);
1739 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
1740 MachineInstr *TheCopy = VirtCopies[i];
1742 if (!JoinCopy(TheCopy, Again))
1744 TryAgain.push_back(TheCopy);
1748 void RegisterCoalescer::joinIntervals() {
1749 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
1751 std::vector<MachineInstr*> TryAgainList;
1752 if (Loops->empty()) {
1753 // If there are no loops in the function, join intervals in function order.
1754 for (MachineFunction::iterator I = MF->begin(), E = MF->end();
1756 CopyCoalesceInMBB(I, TryAgainList);
1758 // Otherwise, join intervals in inner loops before other intervals.
1759 // Unfortunately we can't just iterate over loop hierarchy here because
1760 // there may be more MBB's than BB's. Collect MBB's for sorting.
1762 // Join intervals in the function prolog first. We want to join physical
1763 // registers with virtual registers before the intervals got too long.
1764 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1765 for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
1766 MachineBasicBlock *MBB = I;
1767 MBBs.push_back(std::make_pair(Loops->getLoopDepth(MBB), I));
1770 // Sort by loop depth.
1771 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1773 // Finally, join intervals in loop nest order.
1774 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1775 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
1778 // Joining intervals can allow other intervals to be joined. Iteratively join
1779 // until we make no progress.
1780 bool ProgressMade = true;
1781 while (ProgressMade) {
1782 ProgressMade = false;
1784 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1785 MachineInstr *&TheCopy = TryAgainList[i];
1790 bool Success = JoinCopy(TheCopy, Again);
1791 if (Success || !Again) {
1792 TheCopy= 0; // Mark this one as done.
1793 ProgressMade = true;
1799 void RegisterCoalescer::releaseMemory() {
1800 JoinedCopies.clear();
1801 ReMatCopies.clear();
1805 bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
1807 MRI = &fn.getRegInfo();
1808 TM = &fn.getTarget();
1809 TRI = TM->getRegisterInfo();
1810 TII = TM->getInstrInfo();
1811 LIS = &getAnalysis<LiveIntervals>();
1812 LDV = &getAnalysis<LiveDebugVariables>();
1813 AA = &getAnalysis<AliasAnalysis>();
1814 Loops = &getAnalysis<MachineLoopInfo>();
1816 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
1817 << "********** Function: "
1818 << ((Value*)MF->getFunction())->getName() << '\n');
1820 if (VerifyCoalescing)
1821 MF->verify(this, "Before register coalescing");
1823 RegClassInfo.runOnMachineFunction(fn);
1825 // Join (coalesce) intervals if requested.
1826 if (EnableJoining) {
1829 dbgs() << "********** INTERVALS POST JOINING **********\n";
1830 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end();
1832 I->second->print(dbgs(), TRI);
1838 // Perform a final pass over the instructions and compute spill weights
1839 // and remove identity moves.
1840 SmallVector<unsigned, 4> DeadDefs, InflateRegs;
1841 for (MachineFunction::iterator mbbi = MF->begin(), mbbe = MF->end();
1842 mbbi != mbbe; ++mbbi) {
1843 MachineBasicBlock* mbb = mbbi;
1844 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1846 MachineInstr *MI = mii;
1847 if (JoinedCopies.count(MI)) {
1848 // Delete all coalesced copies.
1849 bool DoDelete = true;
1850 assert(MI->isCopyLike() && "Unrecognized copy instruction");
1851 unsigned SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
1852 unsigned DstReg = MI->getOperand(0).getReg();
1854 // Collect candidates for register class inflation.
1855 if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1856 RegClassInfo.isProperSubClass(MRI->getRegClass(SrcReg)))
1857 InflateRegs.push_back(SrcReg);
1858 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
1859 RegClassInfo.isProperSubClass(MRI->getRegClass(DstReg)))
1860 InflateRegs.push_back(DstReg);
1862 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
1863 MI->getNumOperands() > 2)
1864 // Do not delete extract_subreg, insert_subreg of physical
1865 // registers unless the definition is dead. e.g.
1866 // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
1867 // or else the scavenger may complain. LowerSubregs will
1868 // delete them later.
1871 if (MI->allDefsAreDead()) {
1872 if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1873 LIS->hasInterval(SrcReg))
1874 LIS->shrinkToUses(&LIS->getInterval(SrcReg));
1878 // We need the instruction to adjust liveness, so make it a KILL.
1879 if (MI->isSubregToReg()) {
1880 MI->RemoveOperand(3);
1881 MI->RemoveOperand(1);
1883 MI->setDesc(TII->get(TargetOpcode::KILL));
1884 mii = llvm::next(mii);
1886 LIS->RemoveMachineInstrFromMaps(MI);
1887 mii = mbbi->erase(mii);
1893 // Now check if this is a remat'ed def instruction which is now dead.
1894 if (ReMatDefs.count(MI)) {
1896 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1897 const MachineOperand &MO = MI->getOperand(i);
1900 unsigned Reg = MO.getReg();
1903 DeadDefs.push_back(Reg);
1904 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1905 // Remat may also enable register class inflation.
1906 if (RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)))
1907 InflateRegs.push_back(Reg);
1911 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
1912 !MRI->use_nodbg_empty(Reg)) {
1918 while (!DeadDefs.empty()) {
1919 unsigned DeadDef = DeadDefs.back();
1920 DeadDefs.pop_back();
1921 RemoveDeadDef(LIS->getInterval(DeadDef), MI);
1923 LIS->RemoveMachineInstrFromMaps(mii);
1924 mii = mbbi->erase(mii);
1932 // Check for now unnecessary kill flags.
1933 if (LIS->isNotInMIMap(MI)) continue;
1934 SlotIndex DefIdx = LIS->getInstructionIndex(MI).getRegSlot();
1935 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1936 MachineOperand &MO = MI->getOperand(i);
1937 if (!MO.isReg() || !MO.isKill()) continue;
1938 unsigned reg = MO.getReg();
1939 if (!reg || !LIS->hasInterval(reg)) continue;
1940 if (!LIS->getInterval(reg).killedAt(DefIdx)) {
1941 MO.setIsKill(false);
1944 // When leaving a kill flag on a physreg, check if any subregs should
1946 if (!TargetRegisterInfo::isPhysicalRegister(reg))
1948 for (const unsigned *SR = TRI->getSubRegisters(reg);
1949 unsigned S = *SR; ++SR)
1950 if (LIS->hasInterval(S) && LIS->getInterval(S).liveAt(DefIdx))
1951 MI->addRegisterDefined(S, TRI);
1956 // After deleting a lot of copies, register classes may be less constrained.
1957 // Removing sub-register opreands may alow GR32_ABCD -> GR32 and DPR_VFP2 ->
1959 array_pod_sort(InflateRegs.begin(), InflateRegs.end());
1960 InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
1962 DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n");
1963 for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
1964 unsigned Reg = InflateRegs[i];
1965 if (MRI->reg_nodbg_empty(Reg))
1967 if (MRI->recomputeRegClass(Reg, *TM)) {
1968 DEBUG(dbgs() << PrintReg(Reg) << " inflated to "
1969 << MRI->getRegClass(Reg)->getName() << '\n');
1976 if (VerifyCoalescing)
1977 MF->verify(this, "After register coalescing");
1981 /// print - Implement the dump method.
1982 void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {