1 //===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the generic RegisterCoalescer interface which
11 // is used as the common interface used by all clients and
12 // implementations of register coalescing.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterCoalescer.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/LiveRangeEdit.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineLoopInfo.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/CodeGen/RegisterClassInfo.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Value.h"
31 #include "llvm/Pass.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/Format.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/Target/TargetSubtargetInfo.h"
45 #define DEBUG_TYPE "regalloc"
47 STATISTIC(numJoins , "Number of interval joins performed");
48 STATISTIC(numCrossRCs , "Number of cross class joins performed");
49 STATISTIC(numCommutes , "Number of instruction commuting performed");
50 STATISTIC(numExtends , "Number of copies extended");
51 STATISTIC(NumReMats , "Number of instructions re-materialized");
52 STATISTIC(NumInflated , "Number of register classes inflated");
53 STATISTIC(NumLaneConflicts, "Number of dead lane conflicts tested");
54 STATISTIC(NumLaneResolves, "Number of dead lane conflicts resolved");
57 EnableJoining("join-liveintervals",
58 cl::desc("Coalesce copies (default=true)"),
61 // Temporary flag to test critical edge unsplitting.
63 EnableJoinSplits("join-splitedges",
64 cl::desc("Coalesce copies on split edges (default=subtarget)"), cl::Hidden);
66 // Temporary flag to test global copy optimization.
67 static cl::opt<cl::boolOrDefault>
68 EnableGlobalCopies("join-globalcopies",
69 cl::desc("Coalesce copies that span blocks (default=subtarget)"),
70 cl::init(cl::BOU_UNSET), cl::Hidden);
73 VerifyCoalescing("verify-coalescing",
74 cl::desc("Verify machine instrs before and after register coalescing"),
78 class RegisterCoalescer : public MachineFunctionPass,
79 private LiveRangeEdit::Delegate {
81 MachineRegisterInfo* MRI;
82 const TargetMachine* TM;
83 const TargetRegisterInfo* TRI;
84 const TargetInstrInfo* TII;
86 const MachineLoopInfo* Loops;
88 RegisterClassInfo RegClassInfo;
90 /// A LaneMask to remember on which subregister live ranges we need to call
91 /// shrinkToUses() later.
94 /// True if the main range of the currently coalesced intervals should be
95 /// checked for smaller live intervals.
98 /// \brief True if the coalescer should aggressively coalesce global copies
99 /// in favor of keeping local copies.
100 bool JoinGlobalCopies;
102 /// \brief True if the coalescer should aggressively coalesce fall-thru
103 /// blocks exclusively containing copies.
106 /// Copy instructions yet to be coalesced.
107 SmallVector<MachineInstr*, 8> WorkList;
108 SmallVector<MachineInstr*, 8> LocalWorkList;
110 /// Set of instruction pointers that have been erased, and
111 /// that may be present in WorkList.
112 SmallPtrSet<MachineInstr*, 8> ErasedInstrs;
114 /// Dead instructions that are about to be deleted.
115 SmallVector<MachineInstr*, 8> DeadDefs;
117 /// Virtual registers to be considered for register class inflation.
118 SmallVector<unsigned, 8> InflateRegs;
120 /// Recursively eliminate dead defs in DeadDefs.
121 void eliminateDeadDefs();
123 /// LiveRangeEdit callback.
124 void LRE_WillEraseInstruction(MachineInstr *MI) override;
126 /// Coalesce the LocalWorkList.
127 void coalesceLocals();
129 /// Join compatible live intervals
130 void joinAllIntervals();
132 /// Coalesce copies in the specified MBB, putting
133 /// copies that cannot yet be coalesced into WorkList.
134 void copyCoalesceInMBB(MachineBasicBlock *MBB);
136 /// Try to coalesce all copies in CurrList. Return
137 /// true if any progress was made.
138 bool copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList);
140 /// Attempt to join intervals corresponding to SrcReg/DstReg,
141 /// which are the src/dst of the copy instruction CopyMI. This returns
142 /// true if the copy was successfully coalesced away. If it is not
143 /// currently possible to coalesce this interval, but it may be possible if
144 /// other things get coalesced, then it returns true by reference in
146 bool joinCopy(MachineInstr *TheCopy, bool &Again);
148 /// Attempt to join these two intervals. On failure, this
149 /// returns false. The output "SrcInt" will not have been modified, so we
150 /// can use this information below to update aliases.
151 bool joinIntervals(CoalescerPair &CP);
153 /// Attempt joining two virtual registers. Return true on success.
154 bool joinVirtRegs(CoalescerPair &CP);
156 /// Attempt joining with a reserved physreg.
157 bool joinReservedPhysReg(CoalescerPair &CP);
159 /// Add the LiveRange @p ToMerge as a subregister liverange of @p LI.
160 /// Subranges in @p LI which only partially interfere with the desired
161 /// LaneMask are split as necessary. @p LaneMask are the lanes that
162 /// @p ToMerge will occupy in the coalescer register. @p LI has its subrange
163 /// lanemasks already adjusted to the coalesced register.
164 void mergeSubRangeInto(LiveInterval &LI, const LiveRange &ToMerge,
165 unsigned LaneMask, CoalescerPair &CP);
167 /// Join the liveranges of two subregisters. Joins @p RRange into
168 /// @p LRange, @p RRange may be invalid afterwards.
169 void joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
170 unsigned LaneMask, const CoalescerPair &CP);
172 /// We found a non-trivially-coalescable copy. If
173 /// the source value number is defined by a copy from the destination reg
174 /// see if we can merge these two destination reg valno# into a single
175 /// value number, eliminating a copy.
176 bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
178 /// Return true if there are definitions of IntB
179 /// other than BValNo val# that can reach uses of AValno val# of IntA.
180 bool hasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
181 VNInfo *AValNo, VNInfo *BValNo);
183 /// We found a non-trivially-coalescable copy.
184 /// If the source value number is defined by a commutable instruction and
185 /// its other operand is coalesced to the copy dest register, see if we
186 /// can transform the copy into a noop by commuting the definition.
187 bool removeCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
189 /// If the source of a copy is defined by a
190 /// trivial computation, replace the copy by rematerialize the definition.
191 bool reMaterializeTrivialDef(CoalescerPair &CP, MachineInstr *CopyMI,
194 /// Return true if a physreg copy should be joined.
195 bool canJoinPhys(const CoalescerPair &CP);
197 /// Replace all defs and uses of SrcReg to DstReg and
198 /// update the subregister number if it is not zero. If DstReg is a
199 /// physical register and the existing subregister number of the def / use
200 /// being updated is not zero, make sure to set it to the correct physical
202 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
204 /// Handle copies of undef values.
205 bool eliminateUndefCopy(MachineInstr *CopyMI);
208 static char ID; // Class identification, replacement for typeinfo
209 RegisterCoalescer() : MachineFunctionPass(ID) {
210 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
213 void getAnalysisUsage(AnalysisUsage &AU) const override;
215 void releaseMemory() override;
217 /// This is the pass entry point.
218 bool runOnMachineFunction(MachineFunction&) override;
220 /// Implement the dump method.
221 void print(raw_ostream &O, const Module* = nullptr) const override;
223 } /// end anonymous namespace
225 char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
227 INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
228 "Simple Register Coalescing", false, false)
229 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
230 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
231 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
232 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
233 INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
234 "Simple Register Coalescing", false, false)
236 char RegisterCoalescer::ID = 0;
238 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
239 unsigned &Src, unsigned &Dst,
240 unsigned &SrcSub, unsigned &DstSub) {
242 Dst = MI->getOperand(0).getReg();
243 DstSub = MI->getOperand(0).getSubReg();
244 Src = MI->getOperand(1).getReg();
245 SrcSub = MI->getOperand(1).getSubReg();
246 } else if (MI->isSubregToReg()) {
247 Dst = MI->getOperand(0).getReg();
248 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
249 MI->getOperand(3).getImm());
250 Src = MI->getOperand(2).getReg();
251 SrcSub = MI->getOperand(2).getSubReg();
257 // Return true if this block should be vacated by the coalescer to eliminate
258 // branches. The important cases to handle in the coalescer are critical edges
259 // split during phi elimination which contain only copies. Simple blocks that
260 // contain non-branches should also be vacated, but this can be handled by an
261 // earlier pass similar to early if-conversion.
262 static bool isSplitEdge(const MachineBasicBlock *MBB) {
263 if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
266 for (const auto &MI : *MBB) {
267 if (!MI.isCopyLike() && !MI.isUnconditionalBranch())
273 bool CoalescerPair::setRegisters(const MachineInstr *MI) {
277 Flipped = CrossClass = false;
279 unsigned Src, Dst, SrcSub, DstSub;
280 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
282 Partial = SrcSub || DstSub;
284 // If one register is a physreg, it must be Dst.
285 if (TargetRegisterInfo::isPhysicalRegister(Src)) {
286 if (TargetRegisterInfo::isPhysicalRegister(Dst))
289 std::swap(SrcSub, DstSub);
293 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
295 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
296 // Eliminate DstSub on a physreg.
298 Dst = TRI.getSubReg(Dst, DstSub);
299 if (!Dst) return false;
303 // Eliminate SrcSub by picking a corresponding Dst superregister.
305 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
306 if (!Dst) return false;
307 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
311 // Both registers are virtual.
312 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
313 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
315 // Both registers have subreg indices.
316 if (SrcSub && DstSub) {
317 // Copies between different sub-registers are never coalescable.
318 if (Src == Dst && SrcSub != DstSub)
321 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
326 // SrcReg will be merged with a sub-register of DstReg.
328 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
330 // DstReg will be merged with a sub-register of SrcReg.
332 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
334 // This is a straight copy without sub-registers.
335 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
338 // The combined constraint may be impossible to satisfy.
342 // Prefer SrcReg to be a sub-register of DstReg.
343 // FIXME: Coalescer should support subregs symmetrically.
344 if (DstIdx && !SrcIdx) {
346 std::swap(SrcIdx, DstIdx);
350 CrossClass = NewRC != DstRC || NewRC != SrcRC;
352 // Check our invariants
353 assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
354 assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
355 "Cannot have a physical SubIdx");
361 bool CoalescerPair::flip() {
362 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
364 std::swap(SrcReg, DstReg);
365 std::swap(SrcIdx, DstIdx);
370 bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
373 unsigned Src, Dst, SrcSub, DstSub;
374 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
377 // Find the virtual register that is SrcReg.
380 std::swap(SrcSub, DstSub);
381 } else if (Src != SrcReg) {
385 // Now check that Dst matches DstReg.
386 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
387 if (!TargetRegisterInfo::isPhysicalRegister(Dst))
389 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
390 // DstSub could be set for a physreg from INSERT_SUBREG.
392 Dst = TRI.getSubReg(Dst, DstSub);
395 return DstReg == Dst;
396 // This is a partial register copy. Check that the parts match.
397 return TRI.getSubReg(DstReg, SrcSub) == Dst;
399 // DstReg is virtual.
402 // Registers match, do the subregisters line up?
403 return TRI.composeSubRegIndices(SrcIdx, SrcSub) ==
404 TRI.composeSubRegIndices(DstIdx, DstSub);
408 void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
409 AU.setPreservesCFG();
410 AU.addRequired<AliasAnalysis>();
411 AU.addRequired<LiveIntervals>();
412 AU.addPreserved<LiveIntervals>();
413 AU.addPreserved<SlotIndexes>();
414 AU.addRequired<MachineLoopInfo>();
415 AU.addPreserved<MachineLoopInfo>();
416 AU.addPreservedID(MachineDominatorsID);
417 MachineFunctionPass::getAnalysisUsage(AU);
420 void RegisterCoalescer::eliminateDeadDefs() {
421 SmallVector<unsigned, 8> NewRegs;
422 LiveRangeEdit(nullptr, NewRegs, *MF, *LIS,
423 nullptr, this).eliminateDeadDefs(DeadDefs);
426 // Callback from eliminateDeadDefs().
427 void RegisterCoalescer::LRE_WillEraseInstruction(MachineInstr *MI) {
428 // MI may be in WorkList. Make sure we don't visit it.
429 ErasedInstrs.insert(MI);
432 /// We found a non-trivially-coalescable copy with IntA
433 /// being the source and IntB being the dest, thus this defines a value number
434 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
435 /// see if we can merge these two pieces of B into a single value number,
436 /// eliminating a copy. For example:
440 /// B1 = A3 <- this copy
442 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
443 /// value number to be replaced with B0 (which simplifies the B liveinterval).
445 /// This returns true if an interval was modified.
447 bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
448 MachineInstr *CopyMI) {
449 assert(!CP.isPartial() && "This doesn't work for partial copies.");
450 assert(!CP.isPhys() && "This doesn't work for physreg copies.");
453 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
455 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
456 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
458 // BValNo is a value number in B that is defined by a copy from A. 'B1' in
459 // the example above.
460 LiveInterval::iterator BS = IntB.FindSegmentContaining(CopyIdx);
461 if (BS == IntB.end()) return false;
462 VNInfo *BValNo = BS->valno;
464 // Get the location that B is defined at. Two options: either this value has
465 // an unknown definition point or it is defined at CopyIdx. If unknown, we
467 if (BValNo->def != CopyIdx) return false;
469 // AValNo is the value number in A that defines the copy, A3 in the example.
470 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
471 LiveInterval::iterator AS = IntA.FindSegmentContaining(CopyUseIdx);
472 // The live segment might not exist after fun with physreg coalescing.
473 if (AS == IntA.end()) return false;
474 VNInfo *AValNo = AS->valno;
476 // If AValNo is defined as a copy from IntB, we can potentially process this.
477 // Get the instruction that defines this value number.
478 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
479 // Don't allow any partial copies, even if isCoalescable() allows them.
480 if (!CP.isCoalescable(ACopyMI) || !ACopyMI->isFullCopy())
483 // Get the Segment in IntB that this value number starts with.
484 LiveInterval::iterator ValS =
485 IntB.FindSegmentContaining(AValNo->def.getPrevSlot());
486 if (ValS == IntB.end())
489 // Make sure that the end of the live segment is inside the same block as
491 MachineInstr *ValSEndInst =
492 LIS->getInstructionFromIndex(ValS->end.getPrevSlot());
493 if (!ValSEndInst || ValSEndInst->getParent() != CopyMI->getParent())
496 // Okay, we now know that ValS ends in the same block that the CopyMI
497 // live-range starts. If there are no intervening live segments between them
498 // in IntB, we can merge them.
499 if (ValS+1 != BS) return false;
501 DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI));
503 SlotIndex FillerStart = ValS->end, FillerEnd = BS->start;
504 // We are about to delete CopyMI, so need to remove it as the 'instruction
505 // that defines this value #'. Update the valnum with the new defining
507 BValNo->def = FillerStart;
509 // Okay, we can merge them. We need to insert a new liverange:
510 // [ValS.end, BS.begin) of either value number, then we merge the
511 // two value numbers.
512 IntB.addSegment(LiveInterval::Segment(FillerStart, FillerEnd, BValNo));
514 // Okay, merge "B1" into the same value number as "B0".
515 if (BValNo != ValS->valno)
516 IntB.MergeValueNumberInto(BValNo, ValS->valno);
518 // Do the same for the subregister segments.
519 for (LiveInterval::SubRange &S : IntB.subranges()) {
520 VNInfo *SubBValNo = S.getVNInfoAt(CopyIdx);
521 S.addSegment(LiveInterval::Segment(FillerStart, FillerEnd, SubBValNo));
522 VNInfo *SubValSNo = S.getVNInfoAt(AValNo->def.getPrevSlot());
523 if (SubBValNo != SubValSNo)
524 S.MergeValueNumberInto(SubBValNo, SubValSNo);
527 DEBUG(dbgs() << " result = " << IntB << '\n');
529 // If the source instruction was killing the source register before the
530 // merge, unset the isKill marker given the live range has been extended.
531 int UIdx = ValSEndInst->findRegisterUseOperandIdx(IntB.reg, true);
533 ValSEndInst->getOperand(UIdx).setIsKill(false);
536 // Rewrite the copy. If the copy instruction was killing the destination
537 // register before the merge, find the last use and trim the live range. That
538 // will also add the isKill marker.
539 CopyMI->substituteRegister(IntA.reg, IntB.reg, 0, *TRI);
540 if (AS->end == CopyIdx)
541 LIS->shrinkToUses(&IntA);
547 /// Return true if there are definitions of IntB
548 /// other than BValNo val# that can reach uses of AValno val# of IntA.
549 bool RegisterCoalescer::hasOtherReachingDefs(LiveInterval &IntA,
553 // If AValNo has PHI kills, conservatively assume that IntB defs can reach
555 if (LIS->hasPHIKill(IntA, AValNo))
558 for (LiveRange::Segment &ASeg : IntA.segments) {
559 if (ASeg.valno != AValNo) continue;
560 LiveInterval::iterator BI =
561 std::upper_bound(IntB.begin(), IntB.end(), ASeg.start);
562 if (BI != IntB.begin())
564 for (; BI != IntB.end() && ASeg.end >= BI->start; ++BI) {
565 if (BI->valno == BValNo)
567 if (BI->start <= ASeg.start && BI->end > ASeg.start)
569 if (BI->start > ASeg.start && BI->start < ASeg.end)
576 /// Copy segements with value number @p SrcValNo from liverange @p Src to live
577 /// range @Dst and use value number @p DstValNo there.
578 static void addSegmentsWithValNo(LiveRange &Dst, VNInfo *DstValNo,
579 const LiveRange &Src, const VNInfo *SrcValNo)
581 for (const LiveRange::Segment &S : Src.segments) {
582 if (S.valno != SrcValNo)
584 Dst.addSegment(LiveRange::Segment(S.start, S.end, DstValNo));
588 /// We found a non-trivially-coalescable copy with
589 /// IntA being the source and IntB being the dest, thus this defines a value
590 /// number in IntB. If the source value number (in IntA) is defined by a
591 /// commutable instruction and its other operand is coalesced to the copy dest
592 /// register, see if we can transform the copy into a noop by commuting the
593 /// definition. For example,
595 /// A3 = op A2 B0<kill>
597 /// B1 = A3 <- this copy
599 /// = op A3 <- more uses
603 /// B2 = op B0 A2<kill>
605 /// B1 = B2 <- now an identity copy
607 /// = op B2 <- more uses
609 /// This returns true if an interval was modified.
611 bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
612 MachineInstr *CopyMI) {
613 assert(!CP.isPhys());
616 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
618 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
620 // BValNo is a value number in B that is defined by a copy from A. 'B1' in
621 // the example above.
622 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
623 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
624 assert(BValNo != nullptr && BValNo->def == CopyIdx);
626 // AValNo is the value number in A that defines the copy, A3 in the example.
627 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
628 assert(AValNo && !AValNo->isUnused() && "COPY source not live");
629 if (AValNo->isPHIDef())
631 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
634 if (!DefMI->isCommutable())
636 // If DefMI is a two-address instruction then commuting it will change the
637 // destination register.
638 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
639 assert(DefIdx != -1);
641 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
643 unsigned Op1, Op2, NewDstIdx;
644 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
648 else if (Op2 == UseOpIdx)
653 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
654 unsigned NewReg = NewDstMO.getReg();
655 if (NewReg != IntB.reg || !IntB.Query(AValNo->def).isKill())
658 // Make sure there are no other definitions of IntB that would reach the
659 // uses which the new definition can reach.
660 if (hasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
663 // If some of the uses of IntA.reg is already coalesced away, return false.
664 // It's not possible to determine whether it's safe to perform the coalescing.
665 for (MachineOperand &MO : MRI->use_nodbg_operands(IntA.reg)) {
666 MachineInstr *UseMI = MO.getParent();
667 unsigned OpNo = &MO - &UseMI->getOperand(0);
668 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
669 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
670 if (US == IntA.end() || US->valno != AValNo)
672 // If this use is tied to a def, we can't rewrite the register.
673 if (UseMI->isRegTiedToDefOperand(OpNo))
677 DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t'
680 // At this point we have decided that it is legal to do this
681 // transformation. Start by commuting the instruction.
682 MachineBasicBlock *MBB = DefMI->getParent();
683 MachineInstr *NewMI = TII->commuteInstruction(DefMI);
686 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
687 TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
688 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
690 if (NewMI != DefMI) {
691 LIS->ReplaceMachineInstrInMaps(DefMI, NewMI);
692 MachineBasicBlock::iterator Pos = DefMI;
693 MBB->insert(Pos, NewMI);
697 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
706 // Update uses of IntA of the specific Val# with IntB.
707 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
710 MachineOperand &UseMO = *UI;
713 MachineInstr *UseMI = UseMO.getParent();
715 if (UseMI->isDebugValue()) {
716 // FIXME These don't have an instruction index. Not clear we have enough
717 // info to decide whether to do this replacement or not. For now do it.
718 UseMO.setReg(NewReg);
721 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
722 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
723 assert(US != IntA.end() && "Use must be live");
724 if (US->valno != AValNo)
726 // Kill flags are no longer accurate. They are recomputed after RA.
727 UseMO.setIsKill(false);
728 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
729 UseMO.substPhysReg(NewReg, *TRI);
731 UseMO.setReg(NewReg);
734 if (!UseMI->isCopy())
736 if (UseMI->getOperand(0).getReg() != IntB.reg ||
737 UseMI->getOperand(0).getSubReg())
740 // This copy will become a noop. If it's defining a new val#, merge it into
742 SlotIndex DefIdx = UseIdx.getRegSlot();
743 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
746 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
747 assert(DVNI->def == DefIdx);
748 BValNo = IntB.MergeValueNumberInto(BValNo, DVNI);
749 for (LiveInterval::SubRange &S : IntB.subranges()) {
750 VNInfo *SubDVNI = S.getVNInfoAt(DefIdx);
753 VNInfo *SubBValNo = S.getVNInfoAt(CopyIdx);
754 S.MergeValueNumberInto(SubBValNo, SubDVNI);
757 ErasedInstrs.insert(UseMI);
758 LIS->RemoveMachineInstrFromMaps(UseMI);
759 UseMI->eraseFromParent();
762 // Extend BValNo by merging in IntA live segments of AValNo. Val# definition
764 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
765 if (IntB.hasSubRanges()) {
766 if (!IntA.hasSubRanges()) {
767 unsigned Mask = MRI->getMaxLaneMaskForVReg(IntA.reg);
768 IntA.createSubRangeFrom(Allocator, Mask, IntA);
770 SlotIndex AIdx = CopyIdx.getRegSlot(true);
771 for (LiveInterval::SubRange &SA : IntA.subranges()) {
772 VNInfo *ASubValNo = SA.getVNInfoAt(AIdx);
773 assert(ASubValNo != nullptr);
775 unsigned AMask = SA.LaneMask;
776 for (LiveInterval::SubRange &SB : IntB.subranges()) {
777 unsigned BMask = SB.LaneMask;
778 unsigned Common = BMask & AMask;
783 dbgs() << format("\t\tCopy+Merge %04X into %04X\n", BMask, Common));
784 unsigned BRest = BMask & ~AMask;
785 LiveInterval::SubRange *CommonRange;
788 DEBUG(dbgs() << format("\t\tReduce Lane to %04X\n", BRest));
789 // Duplicate SubRange for newly merged common stuff.
790 CommonRange = IntB.createSubRangeFrom(Allocator, Common, SB);
792 // We van reuse the L SubRange.
793 SB.LaneMask = Common;
796 LiveRange RangeCopy(SB, Allocator);
798 VNInfo *BSubValNo = CommonRange->getVNInfoAt(CopyIdx);
799 assert(BSubValNo->def == CopyIdx);
800 BSubValNo->def = ASubValNo->def;
801 addSegmentsWithValNo(*CommonRange, BSubValNo, SA, ASubValNo);
805 DEBUG(dbgs() << format("\t\tNew Lane %04X\n", AMask));
806 LiveRange *NewRange = IntB.createSubRange(Allocator, AMask);
807 VNInfo *BSubValNo = NewRange->getNextValue(CopyIdx, Allocator);
808 addSegmentsWithValNo(*NewRange, BSubValNo, SA, ASubValNo);
810 SA.removeValNo(ASubValNo);
814 BValNo->def = AValNo->def;
815 addSegmentsWithValNo(IntB, BValNo, IntA, AValNo);
816 DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
818 IntA.removeValNo(AValNo);
819 // Remove valuenos in subranges (the A+B have subranges case has already been
821 if (!IntB.hasSubRanges()) {
822 SlotIndex AIdx = CopyIdx.getRegSlot(true);
823 for (LiveInterval::SubRange &SA : IntA.subranges()) {
824 VNInfo *ASubValNo = SA.getVNInfoAt(AIdx);
825 assert(ASubValNo != nullptr);
826 SA.removeValNo(ASubValNo);
829 DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
834 /// If the source of a copy is defined by a trivial
835 /// computation, replace the copy by rematerialize the definition.
836 bool RegisterCoalescer::reMaterializeTrivialDef(CoalescerPair &CP,
837 MachineInstr *CopyMI,
840 unsigned SrcReg = CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg();
841 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx();
842 unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
843 unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx();
844 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
847 LiveInterval &SrcInt = LIS->getInterval(SrcReg);
848 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI);
849 VNInfo *ValNo = SrcInt.Query(CopyIdx).valueIn();
850 assert(ValNo && "CopyMI input register not live");
851 if (ValNo->isPHIDef() || ValNo->isUnused())
853 MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
856 if (DefMI->isCopyLike()) {
860 if (!TII->isAsCheapAsAMove(DefMI))
862 if (!TII->isTriviallyReMaterializable(DefMI, AA))
864 bool SawStore = false;
865 if (!DefMI->isSafeToMove(TII, AA, SawStore))
867 const MCInstrDesc &MCID = DefMI->getDesc();
868 if (MCID.getNumDefs() != 1)
870 // Only support subregister destinations when the def is read-undef.
871 MachineOperand &DstOperand = CopyMI->getOperand(0);
872 unsigned CopyDstReg = DstOperand.getReg();
873 if (DstOperand.getSubReg() && !DstOperand.isUndef())
876 // If both SrcIdx and DstIdx are set, correct rematerialization would widen
877 // the register substantially (beyond both source and dest size). This is bad
878 // for performance since it can cascade through a function, introducing many
879 // extra spills and fills (e.g. ARM can easily end up copying QQQQPR registers
880 // around after a few subreg copies).
881 if (SrcIdx && DstIdx)
884 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF);
885 if (!DefMI->isImplicitDef()) {
886 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
887 unsigned NewDstReg = DstReg;
889 unsigned NewDstIdx = TRI->composeSubRegIndices(CP.getSrcIdx(),
890 DefMI->getOperand(0).getSubReg());
892 NewDstReg = TRI->getSubReg(DstReg, NewDstIdx);
894 // Finally, make sure that the physical subregister that will be
895 // constructed later is permitted for the instruction.
896 if (!DefRC->contains(NewDstReg))
899 // Theoretically, some stack frame reference could exist. Just make sure
900 // it hasn't actually happened.
901 assert(TargetRegisterInfo::isVirtualRegister(DstReg) &&
902 "Only expect to deal with virtual or physical registers");
906 MachineBasicBlock *MBB = CopyMI->getParent();
907 MachineBasicBlock::iterator MII =
908 std::next(MachineBasicBlock::iterator(CopyMI));
909 TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, DefMI, *TRI);
910 MachineInstr *NewMI = std::prev(MII);
912 LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
913 CopyMI->eraseFromParent();
914 ErasedInstrs.insert(CopyMI);
916 // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
917 // We need to remember these so we can add intervals once we insert
918 // NewMI into SlotIndexes.
919 SmallVector<unsigned, 4> NewMIImplDefs;
920 for (unsigned i = NewMI->getDesc().getNumOperands(),
921 e = NewMI->getNumOperands(); i != e; ++i) {
922 MachineOperand &MO = NewMI->getOperand(i);
924 assert(MO.isDef() && MO.isImplicit() && MO.isDead() &&
925 TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
926 NewMIImplDefs.push_back(MO.getReg());
930 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
931 const TargetRegisterClass *NewRC = CP.getNewRC();
932 unsigned NewIdx = NewMI->getOperand(0).getSubReg();
935 NewRC = TRI->getMatchingSuperRegClass(NewRC, DefRC, NewIdx);
937 NewRC = TRI->getCommonSubClass(NewRC, DefRC);
939 assert(NewRC && "subreg chosen for remat incompatible with instruction");
940 MRI->setRegClass(DstReg, NewRC);
942 updateRegDefsUses(DstReg, DstReg, DstIdx);
943 NewMI->getOperand(0).setSubReg(NewIdx);
944 } else if (NewMI->getOperand(0).getReg() != CopyDstReg) {
945 // The New instruction may be defining a sub-register of what's actually
946 // been asked for. If so it must implicitly define the whole thing.
947 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
948 "Only expect virtual or physical registers in remat");
949 NewMI->getOperand(0).setIsDead(true);
950 NewMI->addOperand(MachineOperand::CreateReg(CopyDstReg,
954 // Record small dead def live-ranges for all the subregisters
955 // of the destination register.
956 // Otherwise, variables that live through may miss some
957 // interferences, thus creating invalid allocation.
959 // vreg1 = somedef ; vreg1 GR8
960 // vreg2 = remat ; vreg2 GR32
961 // CL = COPY vreg2.sub_8bit
962 // = somedef vreg1 ; vreg1 GR8
964 // vreg1 = somedef ; vreg1 GR8
965 // ECX<def, dead> = remat ; CL<imp-def>
966 // = somedef vreg1 ; vreg1 GR8
967 // vreg1 will see the inteferences with CL but not with CH since
968 // no live-ranges would have been created for ECX.
970 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
971 for (MCRegUnitIterator Units(NewMI->getOperand(0).getReg(), TRI);
972 Units.isValid(); ++Units)
973 if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
974 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
977 if (NewMI->getOperand(0).getSubReg())
978 NewMI->getOperand(0).setIsUndef();
980 // CopyMI may have implicit operands, transfer them over to the newly
981 // rematerialized instruction. And update implicit def interval valnos.
982 for (unsigned i = CopyMI->getDesc().getNumOperands(),
983 e = CopyMI->getNumOperands(); i != e; ++i) {
984 MachineOperand &MO = CopyMI->getOperand(i);
986 assert(MO.isImplicit() && "No explicit operands after implict operands.");
987 // Discard VReg implicit defs.
988 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
989 NewMI->addOperand(MO);
994 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
995 for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
996 unsigned Reg = NewMIImplDefs[i];
997 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
998 if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
999 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
1002 DEBUG(dbgs() << "Remat: " << *NewMI);
1005 // The source interval can become smaller because we removed a use.
1006 LIS->shrinkToUses(&SrcInt, &DeadDefs);
1007 if (!DeadDefs.empty()) {
1008 // If the virtual SrcReg is completely eliminated, update all DBG_VALUEs
1009 // to describe DstReg instead.
1010 for (MachineOperand &UseMO : MRI->use_operands(SrcReg)) {
1011 MachineInstr *UseMI = UseMO.getParent();
1012 if (UseMI->isDebugValue()) {
1013 UseMO.setReg(DstReg);
1014 DEBUG(dbgs() << "\t\tupdated: " << *UseMI);
1017 eliminateDeadDefs();
1023 static void removeUndefValue(LiveRange &LR, SlotIndex At)
1025 VNInfo *VNInfo = LR.getVNInfoAt(At);
1026 assert(VNInfo != nullptr && SlotIndex::isSameInstr(VNInfo->def, At));
1027 LR.removeValNo(VNInfo);
1030 /// ProcessImpicitDefs may leave some copies of <undef>
1031 /// values, it only removes local variables. When we have a copy like:
1033 /// %vreg1 = COPY %vreg2<undef>
1035 /// We delete the copy and remove the corresponding value number from %vreg1.
1036 /// Any uses of that value number are marked as <undef>.
1037 bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
1038 // Note that we do not query CoalescerPair here but redo isMoveInstr as the
1039 // CoalescerPair may have a new register class with adjusted subreg indices
1041 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1042 isMoveInstr(*TRI, CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
1044 SlotIndex Idx = LIS->getInstructionIndex(CopyMI);
1045 const LiveInterval &SrcLI = LIS->getInterval(SrcReg);
1046 // CopyMI is undef iff SrcReg is not live before the instruction.
1047 if (SrcSubIdx != 0 && SrcLI.hasSubRanges()) {
1048 unsigned SrcMask = TRI->getSubRegIndexLaneMask(SrcSubIdx);
1049 for (const LiveInterval::SubRange &SR : SrcLI.subranges()) {
1050 if ((SR.LaneMask & SrcMask) == 0)
1055 } else if (SrcLI.liveAt(Idx))
1058 DEBUG(dbgs() << "\tEliminating copy of <undef> value\n");
1060 // Remove any DstReg segments starting at the instruction.
1061 LiveInterval &DstLI = LIS->getInterval(DstReg);
1062 unsigned DstMask = TRI->getSubRegIndexLaneMask(DstSubIdx);
1063 SlotIndex RegIndex = Idx.getRegSlot();
1064 for (LiveInterval::SubRange &SR : DstLI.subranges()) {
1065 if ((SR.LaneMask & DstMask) == 0)
1067 removeUndefValue(SR, RegIndex);
1069 DstLI.removeEmptySubRanges();
1071 // Remove value or merge with previous one in case of a subregister def.
1072 if (VNInfo *PrevVNI = DstLI.getVNInfoAt(Idx)) {
1073 VNInfo *VNInfo = DstLI.getVNInfoAt(RegIndex);
1074 DstLI.MergeValueNumberInto(VNInfo, PrevVNI);
1076 removeUndefValue(DstLI, RegIndex);
1079 // Mark uses as undef.
1080 for (MachineOperand &MO : MRI->reg_nodbg_operands(DstReg)) {
1081 if (MO.isDef() /*|| MO.isUndef()*/)
1083 const MachineInstr &MI = *MO.getParent();
1084 SlotIndex UseIdx = LIS->getInstructionIndex(&MI);
1085 unsigned UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
1087 if (UseMask != ~0u && DstLI.hasSubRanges()) {
1089 for (const LiveInterval::SubRange &SR : DstLI.subranges()) {
1090 if ((SR.LaneMask & UseMask) == 0)
1092 if (SR.liveAt(UseIdx)) {
1098 isLive = DstLI.liveAt(UseIdx);
1101 MO.setIsUndef(true);
1102 DEBUG(dbgs() << "\tnew undef: " << UseIdx << '\t' << MI);
1107 /// Replace all defs and uses of SrcReg to DstReg and update the subregister
1108 /// number if it is not zero. If DstReg is a physical register and the existing
1109 /// subregister number of the def / use being updated is not zero, make sure to
1110 /// set it to the correct physical subregister.
1111 void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg,
1114 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1115 LiveInterval *DstInt = DstIsPhys ? nullptr : &LIS->getInterval(DstReg);
1117 SmallPtrSet<MachineInstr*, 8> Visited;
1118 for (MachineRegisterInfo::reg_instr_iterator
1119 I = MRI->reg_instr_begin(SrcReg), E = MRI->reg_instr_end();
1121 MachineInstr *UseMI = &*(I++);
1123 // Each instruction can only be rewritten once because sub-register
1124 // composition is not always idempotent. When SrcReg != DstReg, rewriting
1125 // the UseMI operands removes them from the SrcReg use-def chain, but when
1126 // SrcReg is DstReg we could encounter UseMI twice if it has multiple
1127 // operands mentioning the virtual register.
1128 if (SrcReg == DstReg && !Visited.insert(UseMI).second)
1131 SmallVector<unsigned,8> Ops;
1133 std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
1135 // If SrcReg wasn't read, it may still be the case that DstReg is live-in
1136 // because SrcReg is a sub-register.
1137 if (DstInt && !Reads && SubIdx)
1138 Reads = DstInt->liveAt(LIS->getInstructionIndex(UseMI));
1140 // Replace SrcReg with DstReg in all UseMI operands.
1141 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
1142 MachineOperand &MO = UseMI->getOperand(Ops[i]);
1144 // Adjust <undef> flags in case of sub-register joins. We don't want to
1145 // turn a full def into a read-modify-write sub-register def and vice
1147 if (SubIdx && MO.isDef())
1148 MO.setIsUndef(!Reads);
1150 // A subreg use of a partially undef (super) register may be a complete
1151 // undef use now and then has to be marked that way.
1152 if (SubIdx != 0 && MO.isUse() && MRI->tracksSubRegLiveness()) {
1153 if (!DstInt->hasSubRanges()) {
1154 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
1155 unsigned Mask = MRI->getMaxLaneMaskForVReg(DstInt->reg);
1156 DstInt->createSubRangeFrom(Allocator, Mask, *DstInt);
1158 unsigned Mask = TRI->getSubRegIndexLaneMask(SubIdx);
1159 bool IsUndef = true;
1160 SlotIndex MIIdx = UseMI->isDebugValue()
1161 ? LIS->getSlotIndexes()->getIndexBefore(UseMI)
1162 : LIS->getInstructionIndex(UseMI);
1163 SlotIndex UseIdx = MIIdx.getRegSlot(true);
1164 for (LiveInterval::SubRange &S : DstInt->subranges()) {
1165 if ((S.LaneMask & Mask) == 0)
1167 if (S.liveAt(UseIdx)) {
1173 MO.setIsUndef(true);
1174 // We found out some subregister use is actually reading an undefined
1175 // value. In some cases the whole vreg has become undefined at this
1176 // point so we have to potentially shrink the main range if the
1177 // use was ending a live segment there.
1178 LiveQueryResult Q = DstInt->Query(MIIdx);
1179 if (Q.valueOut() == nullptr)
1180 ShrinkMainRange = true;
1185 MO.substPhysReg(DstReg, *TRI);
1187 MO.substVirtReg(DstReg, SubIdx, *TRI);
1191 dbgs() << "\t\tupdated: ";
1192 if (!UseMI->isDebugValue())
1193 dbgs() << LIS->getInstructionIndex(UseMI) << "\t";
1199 /// Return true if a copy involving a physreg should be joined.
1200 bool RegisterCoalescer::canJoinPhys(const CoalescerPair &CP) {
1201 /// Always join simple intervals that are defined by a single copy from a
1202 /// reserved register. This doesn't increase register pressure, so it is
1203 /// always beneficial.
1204 if (!MRI->isReserved(CP.getDstReg())) {
1205 DEBUG(dbgs() << "\tCan only merge into reserved registers.\n");
1209 LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
1210 if (CP.isFlipped() && JoinVInt.containsOneValue())
1213 DEBUG(dbgs() << "\tCannot join defs into reserved register.\n");
1217 /// Attempt to join intervals corresponding to SrcReg/DstReg,
1218 /// which are the src/dst of the copy instruction CopyMI. This returns true
1219 /// if the copy was successfully coalesced away. If it is not currently
1220 /// possible to coalesce this interval, but it may be possible if other
1221 /// things get coalesced, then it returns true by reference in 'Again'.
1222 bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
1225 DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1227 CoalescerPair CP(*TRI);
1228 if (!CP.setRegisters(CopyMI)) {
1229 DEBUG(dbgs() << "\tNot coalescable.\n");
1233 if (CP.getNewRC()) {
1234 auto SrcRC = MRI->getRegClass(CP.getSrcReg());
1235 auto DstRC = MRI->getRegClass(CP.getDstReg());
1236 unsigned SrcIdx = CP.getSrcIdx();
1237 unsigned DstIdx = CP.getDstIdx();
1238 if (CP.isFlipped()) {
1239 std::swap(SrcIdx, DstIdx);
1240 std::swap(SrcRC, DstRC);
1242 if (!TRI->shouldCoalesce(CopyMI, SrcRC, SrcIdx, DstRC, DstIdx,
1244 DEBUG(dbgs() << "\tSubtarget bailed on coalescing.\n");
1249 // Dead code elimination. This really should be handled by MachineDCE, but
1250 // sometimes dead copies slip through, and we can't generate invalid live
1252 if (!CP.isPhys() && CopyMI->allDefsAreDead()) {
1253 DEBUG(dbgs() << "\tCopy is dead.\n");
1254 DeadDefs.push_back(CopyMI);
1255 eliminateDeadDefs();
1259 // Eliminate undefs.
1260 if (!CP.isPhys() && eliminateUndefCopy(CopyMI)) {
1261 LIS->RemoveMachineInstrFromMaps(CopyMI);
1262 CopyMI->eraseFromParent();
1263 return false; // Not coalescable.
1266 // Coalesced copies are normally removed immediately, but transformations
1267 // like removeCopyByCommutingDef() can inadvertently create identity copies.
1268 // When that happens, just join the values and remove the copy.
1269 if (CP.getSrcReg() == CP.getDstReg()) {
1270 LiveInterval &LI = LIS->getInterval(CP.getSrcReg());
1271 DEBUG(dbgs() << "\tCopy already coalesced: " << LI << '\n');
1272 const SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI);
1273 LiveQueryResult LRQ = LI.Query(CopyIdx);
1274 if (VNInfo *DefVNI = LRQ.valueDefined()) {
1275 VNInfo *ReadVNI = LRQ.valueIn();
1276 assert(ReadVNI && "No value before copy and no <undef> flag.");
1277 assert(ReadVNI != DefVNI && "Cannot read and define the same value.");
1278 LI.MergeValueNumberInto(DefVNI, ReadVNI);
1280 // Process subregister liveranges.
1281 for (LiveInterval::SubRange &S : LI.subranges()) {
1282 LiveQueryResult SLRQ = S.Query(CopyIdx);
1283 if (VNInfo *SDefVNI = SLRQ.valueDefined()) {
1284 VNInfo *SReadVNI = SLRQ.valueIn();
1285 S.MergeValueNumberInto(SDefVNI, SReadVNI);
1288 DEBUG(dbgs() << "\tMerged values: " << LI << '\n');
1290 LIS->RemoveMachineInstrFromMaps(CopyMI);
1291 CopyMI->eraseFromParent();
1295 // Enforce policies.
1297 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI)
1298 << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx())
1300 if (!canJoinPhys(CP)) {
1301 // Before giving up coalescing, if definition of source is defined by
1302 // trivial computation, try rematerializing it.
1304 if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
1307 Again = true; // May be possible to coalesce later.
1311 // When possible, let DstReg be the larger interval.
1312 if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).size() >
1313 LIS->getInterval(CP.getDstReg()).size())
1317 dbgs() << "\tConsidering merging to "
1318 << TRI->getRegClassName(CP.getNewRC()) << " with ";
1319 if (CP.getDstIdx() && CP.getSrcIdx())
1320 dbgs() << PrintReg(CP.getDstReg()) << " in "
1321 << TRI->getSubRegIndexName(CP.getDstIdx()) << " and "
1322 << PrintReg(CP.getSrcReg()) << " in "
1323 << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';
1325 dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in "
1326 << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
1331 ShrinkMainRange = false;
1333 // Okay, attempt to join these two intervals. On failure, this returns false.
1334 // Otherwise, if one of the intervals being joined is a physreg, this method
1335 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1336 // been modified, so we can use this information below to update aliases.
1337 if (!joinIntervals(CP)) {
1338 // Coalescing failed.
1340 // If definition of source is defined by trivial computation, try
1341 // rematerializing it.
1343 if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
1346 // If we can eliminate the copy without merging the live segments, do so
1348 if (!CP.isPartial() && !CP.isPhys()) {
1349 if (adjustCopiesBackFrom(CP, CopyMI) ||
1350 removeCopyByCommutingDef(CP, CopyMI)) {
1351 LIS->RemoveMachineInstrFromMaps(CopyMI);
1352 CopyMI->eraseFromParent();
1353 DEBUG(dbgs() << "\tTrivial!\n");
1358 // Otherwise, we are unable to join the intervals.
1359 DEBUG(dbgs() << "\tInterference!\n");
1360 Again = true; // May be possible to coalesce later.
1364 // Coalescing to a virtual register that is of a sub-register class of the
1365 // other. Make sure the resulting register is set to the right register class.
1366 if (CP.isCrossClass()) {
1368 MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
1371 // Removing sub-register copies can ease the register class constraints.
1372 // Make sure we attempt to inflate the register class of DstReg.
1373 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
1374 InflateRegs.push_back(CP.getDstReg());
1376 // CopyMI has been erased by joinIntervals at this point. Remove it from
1377 // ErasedInstrs since copyCoalesceWorkList() won't add a successful join back
1378 // to the work list. This keeps ErasedInstrs from growing needlessly.
1379 ErasedInstrs.erase(CopyMI);
1381 // Rewrite all SrcReg operands to DstReg.
1382 // Also update DstReg operands to include DstIdx if it is set.
1384 updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx());
1385 updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx());
1387 // Shrink subregister ranges if necessary.
1388 if (ShrinkMask != 0) {
1389 LiveInterval &LI = LIS->getInterval(CP.getDstReg());
1390 for (LiveInterval::SubRange &S : LI.subranges()) {
1391 if ((S.LaneMask & ShrinkMask) == 0)
1393 DEBUG(dbgs() << "Shrink LaneUses (Lane "
1394 << format("%04X", S.LaneMask) << ")\n");
1395 LIS->shrinkToUses(S, LI.reg);
1398 if (ShrinkMainRange) {
1399 LiveInterval &LI = LIS->getInterval(CP.getDstReg());
1400 LIS->shrinkToUses(&LI);
1403 // SrcReg is guaranteed to be the register whose live interval that is
1405 LIS->removeInterval(CP.getSrcReg());
1407 // Update regalloc hint.
1408 TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
1411 dbgs() << "\tSuccess: " << PrintReg(CP.getSrcReg(), TRI, CP.getSrcIdx())
1412 << " -> " << PrintReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
1413 dbgs() << "\tResult = ";
1415 dbgs() << PrintReg(CP.getDstReg(), TRI);
1417 dbgs() << LIS->getInterval(CP.getDstReg());
1425 /// Attempt joining with a reserved physreg.
1426 bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
1427 assert(CP.isPhys() && "Must be a physreg copy");
1428 assert(MRI->isReserved(CP.getDstReg()) && "Not a reserved register");
1429 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1430 DEBUG(dbgs() << "\t\tRHS = " << RHS << '\n');
1432 assert(CP.isFlipped() && RHS.containsOneValue() &&
1433 "Invalid join with reserved register");
1435 // Optimization for reserved registers like ESP. We can only merge with a
1436 // reserved physreg if RHS has a single value that is a copy of CP.DstReg().
1437 // The live range of the reserved register will look like a set of dead defs
1438 // - we don't properly track the live range of reserved registers.
1440 // Deny any overlapping intervals. This depends on all the reserved
1441 // register live ranges to look like dead defs.
1442 for (MCRegUnitIterator UI(CP.getDstReg(), TRI); UI.isValid(); ++UI)
1443 if (RHS.overlaps(LIS->getRegUnit(*UI))) {
1444 DEBUG(dbgs() << "\t\tInterference: " << PrintRegUnit(*UI, TRI) << '\n');
1448 // Skip any value computations, we are not adding new values to the
1449 // reserved register. Also skip merging the live ranges, the reserved
1450 // register live range doesn't need to be accurate as long as all the
1453 // Delete the identity copy.
1454 MachineInstr *CopyMI = MRI->getVRegDef(RHS.reg);
1455 LIS->RemoveMachineInstrFromMaps(CopyMI);
1456 CopyMI->eraseFromParent();
1458 // We don't track kills for reserved registers.
1459 MRI->clearKillFlags(CP.getSrcReg());
1464 //===----------------------------------------------------------------------===//
1465 // Interference checking and interval joining
1466 //===----------------------------------------------------------------------===//
1468 // In the easiest case, the two live ranges being joined are disjoint, and
1469 // there is no interference to consider. It is quite common, though, to have
1470 // overlapping live ranges, and we need to check if the interference can be
1473 // The live range of a single SSA value forms a sub-tree of the dominator tree.
1474 // This means that two SSA values overlap if and only if the def of one value
1475 // is contained in the live range of the other value. As a special case, the
1476 // overlapping values can be defined at the same index.
1478 // The interference from an overlapping def can be resolved in these cases:
1480 // 1. Coalescable copies. The value is defined by a copy that would become an
1481 // identity copy after joining SrcReg and DstReg. The copy instruction will
1482 // be removed, and the value will be merged with the source value.
1484 // There can be several copies back and forth, causing many values to be
1485 // merged into one. We compute a list of ultimate values in the joined live
1486 // range as well as a mappings from the old value numbers.
1488 // 2. IMPLICIT_DEF. This instruction is only inserted to ensure all PHI
1489 // predecessors have a live out value. It doesn't cause real interference,
1490 // and can be merged into the value it overlaps. Like a coalescable copy, it
1491 // can be erased after joining.
1493 // 3. Copy of external value. The overlapping def may be a copy of a value that
1494 // is already in the other register. This is like a coalescable copy, but
1495 // the live range of the source register must be trimmed after erasing the
1496 // copy instruction:
1499 // %dst = COPY %ext <-- Remove this COPY, trim the live range of %ext.
1501 // 4. Clobbering undefined lanes. Vector registers are sometimes built by
1502 // defining one lane at a time:
1504 // %dst:ssub0<def,read-undef> = FOO
1506 // %dst:ssub1<def> = COPY %src
1508 // The live range of %src overlaps the %dst value defined by FOO, but
1509 // merging %src into %dst:ssub1 is only going to clobber the ssub1 lane
1510 // which was undef anyway.
1512 // The value mapping is more complicated in this case. The final live range
1513 // will have different value numbers for both FOO and BAR, but there is no
1514 // simple mapping from old to new values. It may even be necessary to add
1517 // 5. Clobbering dead lanes. A def may clobber a lane of a vector register that
1518 // is live, but never read. This can happen because we don't compute
1519 // individual live ranges per lane.
1523 // %dst:ssub1<def> = COPY %src
1525 // This kind of interference is only resolved locally. If the clobbered
1526 // lane value escapes the block, the join is aborted.
1529 /// Track information about values in a single virtual register about to be
1530 /// joined. Objects of this class are always created in pairs - one for each
1531 /// side of the CoalescerPair (or one for each lane of a side of the coalescer
1534 /// Live range we work on.
1536 /// (Main) register we work on.
1539 // Reg (and therefore the values in this liverange) will end up as subregister
1540 // SubIdx in the coalesced register. Either CP.DstIdx or CP.SrcIdx.
1541 const unsigned SubIdx;
1542 // The LaneMask that this liverange will occupy the coalesced register. May be
1543 // smaller than the lanemask produced by SubIdx when merging subranges.
1544 const unsigned LaneMask;
1546 /// This is true when joining sub register ranges, false when joining main
1548 const bool SubRangeJoin;
1549 /// Whether the current LiveInterval tracks subregister liveness.
1550 const bool TrackSubRegLiveness;
1552 // Values that will be present in the final live range.
1553 SmallVectorImpl<VNInfo*> &NewVNInfo;
1555 const CoalescerPair &CP;
1557 SlotIndexes *Indexes;
1558 const TargetRegisterInfo *TRI;
1560 // Value number assignments. Maps value numbers in LI to entries in NewVNInfo.
1561 // This is suitable for passing to LiveInterval::join().
1562 SmallVector<int, 8> Assignments;
1564 // Conflict resolution for overlapping values.
1565 enum ConflictResolution {
1566 // No overlap, simply keep this value.
1569 // Merge this value into OtherVNI and erase the defining instruction.
1570 // Used for IMPLICIT_DEF, coalescable copies, and copies from external
1574 // Merge this value into OtherVNI but keep the defining instruction.
1575 // This is for the special case where OtherVNI is defined by the same
1579 // Keep this value, and have it replace OtherVNI where possible. This
1580 // complicates value mapping since OtherVNI maps to two different values
1581 // before and after this def.
1582 // Used when clobbering undefined or dead lanes.
1585 // Unresolved conflict. Visit later when all values have been mapped.
1588 // Unresolvable conflict. Abort the join.
1592 // Per-value info for LI. The lane bit masks are all relative to the final
1593 // joined register, so they can be compared directly between SrcReg and
1596 ConflictResolution Resolution;
1598 // Lanes written by this def, 0 for unanalyzed values.
1599 unsigned WriteLanes;
1601 // Lanes with defined values in this register. Other lanes are undef and
1603 unsigned ValidLanes;
1605 // Value in LI being redefined by this def.
1608 // Value in the other live range that overlaps this def, if any.
1611 // Is this value an IMPLICIT_DEF that can be erased?
1613 // IMPLICIT_DEF values should only exist at the end of a basic block that
1614 // is a predecessor to a phi-value. These IMPLICIT_DEF instructions can be
1615 // safely erased if they are overlapping a live value in the other live
1618 // Weird control flow graphs and incomplete PHI handling in
1619 // ProcessImplicitDefs can very rarely create IMPLICIT_DEF values with
1620 // longer live ranges. Such IMPLICIT_DEF values should be treated like
1622 bool ErasableImplicitDef;
1624 // True when the live range of this value will be pruned because of an
1625 // overlapping CR_Replace value in the other live range.
1628 // True once Pruned above has been computed.
1629 bool PrunedComputed;
1631 Val() : Resolution(CR_Keep), WriteLanes(0), ValidLanes(0),
1632 RedefVNI(nullptr), OtherVNI(nullptr), ErasableImplicitDef(false),
1633 Pruned(false), PrunedComputed(false) {}
1635 bool isAnalyzed() const { return WriteLanes != 0; }
1638 // One entry per value number in LI.
1639 SmallVector<Val, 8> Vals;
1641 unsigned computeWriteLanes(const MachineInstr *DefMI, bool &Redef) const;
1642 std::pair<const VNInfo*,unsigned> followCopyChain(const VNInfo *VNI) const;
1643 bool valuesIdentical(VNInfo *Val0, VNInfo *Val1, const JoinVals &Other) const;
1644 ConflictResolution analyzeValue(unsigned ValNo, JoinVals &Other);
1645 void computeAssignment(unsigned ValNo, JoinVals &Other);
1646 bool taintExtent(unsigned, unsigned, JoinVals&,
1647 SmallVectorImpl<std::pair<SlotIndex, unsigned> >&);
1648 bool usesLanes(const MachineInstr *MI, unsigned, unsigned, unsigned) const;
1649 bool isPrunedValue(unsigned ValNo, JoinVals &Other);
1652 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, unsigned LaneMask,
1653 SmallVectorImpl<VNInfo*> &newVNInfo, const CoalescerPair &cp,
1654 LiveIntervals *lis, const TargetRegisterInfo *TRI, bool SubRangeJoin,
1655 bool TrackSubRegLiveness)
1656 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask),
1657 SubRangeJoin(SubRangeJoin), TrackSubRegLiveness(TrackSubRegLiveness),
1658 NewVNInfo(newVNInfo), CP(cp), LIS(lis), Indexes(LIS->getSlotIndexes()),
1659 TRI(TRI), Assignments(LR.getNumValNums(), -1), Vals(LR.getNumValNums())
1662 /// Analyze defs in LR and compute a value mapping in NewVNInfo.
1663 /// Returns false if any conflicts were impossible to resolve.
1664 bool mapValues(JoinVals &Other);
1666 /// Try to resolve conflicts that require all values to be mapped.
1667 /// Returns false if any conflicts were impossible to resolve.
1668 bool resolveConflicts(JoinVals &Other);
1670 /// Prune the live range of values in Other.LR where they would conflict with
1671 /// CR_Replace values in LR. Collect end points for restoring the live range
1673 void pruneValues(JoinVals &Other, SmallVectorImpl<SlotIndex> &EndPoints,
1676 // Removes subranges starting at copies that get removed. This sometimes
1677 // happens when undefined subranges are copied around. These ranges contain
1678 // no usefull information and can be removed.
1679 void pruneSubRegValues(LiveInterval &LI, unsigned &ShrinkMask);
1681 /// Erase any machine instructions that have been coalesced away.
1682 /// Add erased instructions to ErasedInstrs.
1683 /// Add foreign virtual registers to ShrinkRegs if their live range ended at
1684 /// the erased instrs.
1685 void eraseInstrs(SmallPtrSetImpl<MachineInstr*> &ErasedInstrs,
1686 SmallVectorImpl<unsigned> &ShrinkRegs);
1688 /// Get the value assignments suitable for passing to LiveInterval::join.
1689 const int *getAssignments() const { return Assignments.data(); }
1691 } // end anonymous namespace
1693 /// Compute the bitmask of lanes actually written by DefMI.
1694 /// Set Redef if there are any partial register definitions that depend on the
1695 /// previous value of the register.
1696 unsigned JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef)
1699 for (ConstMIOperands MO(DefMI); MO.isValid(); ++MO) {
1700 if (!MO->isReg() || MO->getReg() != Reg || !MO->isDef())
1702 L |= TRI->getSubRegIndexLaneMask(
1703 TRI->composeSubRegIndices(SubIdx, MO->getSubReg()));
1710 /// Find the ultimate value that VNI was copied from.
1711 std::pair<const VNInfo*, unsigned> JoinVals::followCopyChain(
1712 const VNInfo *VNI) const {
1713 unsigned Reg = this->Reg;
1715 while (!VNI->isPHIDef()) {
1716 SlotIndex Def = VNI->def;
1717 MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
1718 assert(MI && "No defining instruction");
1719 if (!MI->isFullCopy())
1720 return std::make_pair(VNI, Reg);
1721 unsigned SrcReg = MI->getOperand(1).getReg();
1722 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
1723 return std::make_pair(VNI, Reg);
1725 const LiveInterval &LI = LIS->getInterval(SrcReg);
1726 const VNInfo *ValueIn;
1727 // No subrange involved.
1728 if (!SubRangeJoin || !LI.hasSubRanges()) {
1729 LiveQueryResult LRQ = LI.Query(Def);
1730 ValueIn = LRQ.valueIn();
1732 // Query subranges. Pick the first matching one.
1734 for (const LiveInterval::SubRange &S : LI.subranges()) {
1735 // Transform lanemask to a mask in the joined live interval.
1736 unsigned SMask = TRI->composeSubRegIndexLaneMask(SubIdx, S.LaneMask);
1737 if ((SMask & LaneMask) == 0)
1739 LiveQueryResult LRQ = S.Query(Def);
1740 ValueIn = LRQ.valueIn();
1744 if (ValueIn == nullptr)
1749 return std::make_pair(VNI, Reg);
1752 bool JoinVals::valuesIdentical(VNInfo *Value0, VNInfo *Value1,
1753 const JoinVals &Other) const {
1754 const VNInfo *Orig0;
1756 std::tie(Orig0, Reg0) = followCopyChain(Value0);
1757 if (Orig0 == Value1)
1760 const VNInfo *Orig1;
1762 std::tie(Orig1, Reg1) = Other.followCopyChain(Value1);
1764 // The values are equal if they are defined at the same place and use the
1765 // same register. Note that we cannot compare VNInfos directly as some of
1766 // them might be from a copy created in mergeSubRangeInto() while the other
1767 // is from the original LiveInterval.
1768 return Orig0->def == Orig1->def && Reg0 == Reg1;
1771 /// Analyze ValNo in this live range, and set all fields of Vals[ValNo].
1772 /// Return a conflict resolution when possible, but leave the hard cases as
1774 /// Recursively calls computeAssignment() on this and Other, guaranteeing that
1775 /// both OtherVNI and RedefVNI have been analyzed and mapped before returning.
1776 /// The recursion always goes upwards in the dominator tree, making loops
1778 JoinVals::ConflictResolution
1779 JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) {
1780 Val &V = Vals[ValNo];
1781 assert(!V.isAnalyzed() && "Value has already been analyzed!");
1782 VNInfo *VNI = LR.getValNumInfo(ValNo);
1783 if (VNI->isUnused()) {
1788 // Get the instruction defining this value, compute the lanes written.
1789 const MachineInstr *DefMI = nullptr;
1790 if (VNI->isPHIDef()) {
1791 // Conservatively assume that all lanes in a PHI are valid.
1792 unsigned Lanes = SubRangeJoin ? 1 : TRI->getSubRegIndexLaneMask(SubIdx);
1793 V.ValidLanes = V.WriteLanes = Lanes;
1795 DefMI = Indexes->getInstructionFromIndex(VNI->def);
1796 assert(DefMI != nullptr);
1798 // We don't care about the lanes when joining subregister ranges.
1799 V.ValidLanes = V.WriteLanes = 1;
1802 V.ValidLanes = V.WriteLanes = computeWriteLanes(DefMI, Redef);
1804 // If this is a read-modify-write instruction, there may be more valid
1805 // lanes than the ones written by this instruction.
1806 // This only covers partial redef operands. DefMI may have normal use
1807 // operands reading the register. They don't contribute valid lanes.
1809 // This adds ssub1 to the set of valid lanes in %src:
1811 // %src:ssub1<def> = FOO
1813 // This leaves only ssub1 valid, making any other lanes undef:
1815 // %src:ssub1<def,read-undef> = FOO %src:ssub2
1817 // The <read-undef> flag on the def operand means that old lane values are
1820 V.RedefVNI = LR.Query(VNI->def).valueIn();
1821 assert((TrackSubRegLiveness || V.RedefVNI) &&
1822 "Instruction is reading nonexistent value");
1823 if (V.RedefVNI != nullptr) {
1824 computeAssignment(V.RedefVNI->id, Other);
1825 V.ValidLanes |= Vals[V.RedefVNI->id].ValidLanes;
1829 // An IMPLICIT_DEF writes undef values.
1830 if (DefMI->isImplicitDef()) {
1831 // We normally expect IMPLICIT_DEF values to be live only until the end
1832 // of their block. If the value is really live longer and gets pruned in
1833 // another block, this flag is cleared again.
1834 V.ErasableImplicitDef = true;
1835 V.ValidLanes &= ~V.WriteLanes;
1840 // Find the value in Other that overlaps VNI->def, if any.
1841 LiveQueryResult OtherLRQ = Other.LR.Query(VNI->def);
1843 // It is possible that both values are defined by the same instruction, or
1844 // the values are PHIs defined in the same block. When that happens, the two
1845 // values should be merged into one, but not into any preceding value.
1846 // The first value defined or visited gets CR_Keep, the other gets CR_Merge.
1847 if (VNInfo *OtherVNI = OtherLRQ.valueDefined()) {
1848 assert(SlotIndex::isSameInstr(VNI->def, OtherVNI->def) && "Broken LRQ");
1850 // One value stays, the other is merged. Keep the earlier one, or the first
1852 if (OtherVNI->def < VNI->def)
1853 Other.computeAssignment(OtherVNI->id, *this);
1854 else if (VNI->def < OtherVNI->def && OtherLRQ.valueIn()) {
1855 // This is an early-clobber def overlapping a live-in value in the other
1856 // register. Not mergeable.
1857 V.OtherVNI = OtherLRQ.valueIn();
1858 return CR_Impossible;
1860 V.OtherVNI = OtherVNI;
1861 Val &OtherV = Other.Vals[OtherVNI->id];
1862 // Keep this value, check for conflicts when analyzing OtherVNI.
1863 if (!OtherV.isAnalyzed())
1865 // Both sides have been analyzed now.
1866 // Allow overlapping PHI values. Any real interference would show up in a
1867 // predecessor, the PHI itself can't introduce any conflicts.
1868 if (VNI->isPHIDef())
1870 if (V.ValidLanes & OtherV.ValidLanes)
1871 // Overlapping lanes can't be resolved.
1872 return CR_Impossible;
1877 // No simultaneous def. Is Other live at the def?
1878 V.OtherVNI = OtherLRQ.valueIn();
1880 // No overlap, no conflict.
1883 assert(!SlotIndex::isSameInstr(VNI->def, V.OtherVNI->def) && "Broken LRQ");
1885 // We have overlapping values, or possibly a kill of Other.
1886 // Recursively compute assignments up the dominator tree.
1887 Other.computeAssignment(V.OtherVNI->id, *this);
1888 Val &OtherV = Other.Vals[V.OtherVNI->id];
1890 // Check if OtherV is an IMPLICIT_DEF that extends beyond its basic block.
1891 // This shouldn't normally happen, but ProcessImplicitDefs can leave such
1892 // IMPLICIT_DEF instructions behind, and there is nothing wrong with it
1895 // WHen it happens, treat that IMPLICIT_DEF as a normal value, and don't try
1896 // to erase the IMPLICIT_DEF instruction.
1897 if (OtherV.ErasableImplicitDef && DefMI &&
1898 DefMI->getParent() != Indexes->getMBBFromIndex(V.OtherVNI->def)) {
1899 DEBUG(dbgs() << "IMPLICIT_DEF defined at " << V.OtherVNI->def
1900 << " extends into BB#" << DefMI->getParent()->getNumber()
1901 << ", keeping it.\n");
1902 OtherV.ErasableImplicitDef = false;
1905 // Allow overlapping PHI values. Any real interference would show up in a
1906 // predecessor, the PHI itself can't introduce any conflicts.
1907 if (VNI->isPHIDef())
1910 // Check for simple erasable conflicts.
1911 if (DefMI->isImplicitDef()) {
1912 // We need the def for the subregister if there is nothing else live at the
1913 // subrange at this point.
1914 if (TrackSubRegLiveness
1915 && (V.WriteLanes & (OtherV.ValidLanes | OtherV.WriteLanes)) == 0)
1920 // Include the non-conflict where DefMI is a coalescable copy that kills
1921 // OtherVNI. We still want the copy erased and value numbers merged.
1922 if (CP.isCoalescable(DefMI)) {
1923 // Some of the lanes copied from OtherVNI may be undef, making them undef
1925 V.ValidLanes &= ~V.WriteLanes | OtherV.ValidLanes;
1929 // This may not be a real conflict if DefMI simply kills Other and defines
1931 if (OtherLRQ.isKill() && OtherLRQ.endPoint() <= VNI->def)
1934 // Handle the case where VNI and OtherVNI can be proven to be identical:
1936 // %other = COPY %ext
1937 // %this = COPY %ext <-- Erase this copy
1939 if (DefMI->isFullCopy() && !CP.isPartial()
1940 && valuesIdentical(VNI, V.OtherVNI, Other))
1943 // If the lanes written by this instruction were all undef in OtherVNI, it is
1944 // still safe to join the live ranges. This can't be done with a simple value
1945 // mapping, though - OtherVNI will map to multiple values:
1947 // 1 %dst:ssub0 = FOO <-- OtherVNI
1948 // 2 %src = BAR <-- VNI
1949 // 3 %dst:ssub1 = COPY %src<kill> <-- Eliminate this copy.
1951 // 5 QUUX %src<kill>
1953 // Here OtherVNI will map to itself in [1;2), but to VNI in [2;5). CR_Replace
1954 // handles this complex value mapping.
1955 if ((V.WriteLanes & OtherV.ValidLanes) == 0)
1958 // If the other live range is killed by DefMI and the live ranges are still
1959 // overlapping, it must be because we're looking at an early clobber def:
1961 // %dst<def,early-clobber> = ASM %src<kill>
1963 // In this case, it is illegal to merge the two live ranges since the early
1964 // clobber def would clobber %src before it was read.
1965 if (OtherLRQ.isKill()) {
1966 // This case where the def doesn't overlap the kill is handled above.
1967 assert(VNI->def.isEarlyClobber() &&
1968 "Only early clobber defs can overlap a kill");
1969 return CR_Impossible;
1972 // VNI is clobbering live lanes in OtherVNI, but there is still the
1973 // possibility that no instructions actually read the clobbered lanes.
1974 // If we're clobbering all the lanes in OtherVNI, at least one must be read.
1975 // Otherwise Other.RI wouldn't be live here.
1976 if ((TRI->getSubRegIndexLaneMask(Other.SubIdx) & ~V.WriteLanes) == 0)
1977 return CR_Impossible;
1979 // We need to verify that no instructions are reading the clobbered lanes. To
1980 // save compile time, we'll only check that locally. Don't allow the tainted
1981 // value to escape the basic block.
1982 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
1983 if (OtherLRQ.endPoint() >= Indexes->getMBBEndIdx(MBB))
1984 return CR_Impossible;
1986 // There are still some things that could go wrong besides clobbered lanes
1987 // being read, for example OtherVNI may be only partially redefined in MBB,
1988 // and some clobbered lanes could escape the block. Save this analysis for
1989 // resolveConflicts() when all values have been mapped. We need to know
1990 // RedefVNI and WriteLanes for any later defs in MBB, and we can't compute
1991 // that now - the recursive analyzeValue() calls must go upwards in the
1993 return CR_Unresolved;
1996 /// Compute the value assignment for ValNo in RI.
1997 /// This may be called recursively by analyzeValue(), but never for a ValNo on
1999 void JoinVals::computeAssignment(unsigned ValNo, JoinVals &Other) {
2000 Val &V = Vals[ValNo];
2001 if (V.isAnalyzed()) {
2002 // Recursion should always move up the dominator tree, so ValNo is not
2003 // supposed to reappear before it has been assigned.
2004 assert(Assignments[ValNo] != -1 && "Bad recursion?");
2007 switch ((V.Resolution = analyzeValue(ValNo, Other))) {
2010 // Merge this ValNo into OtherVNI.
2011 assert(V.OtherVNI && "OtherVNI not assigned, can't merge.");
2012 assert(Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion");
2013 Assignments[ValNo] = Other.Assignments[V.OtherVNI->id];
2014 DEBUG(dbgs() << "\t\tmerge " << PrintReg(Reg) << ':' << ValNo << '@'
2015 << LR.getValNumInfo(ValNo)->def << " into "
2016 << PrintReg(Other.Reg) << ':' << V.OtherVNI->id << '@'
2017 << V.OtherVNI->def << " --> @"
2018 << NewVNInfo[Assignments[ValNo]]->def << '\n');
2021 case CR_Unresolved: {
2022 // The other value is going to be pruned if this join is successful.
2023 assert(V.OtherVNI && "OtherVNI not assigned, can't prune");
2024 Val &OtherV = Other.Vals[V.OtherVNI->id];
2025 // We cannot erase an IMPLICIT_DEF if we don't have valid values for all
2027 if ((OtherV.WriteLanes & ~V.ValidLanes) != 0 && TrackSubRegLiveness)
2028 OtherV.ErasableImplicitDef = false;
2029 OtherV.Pruned = true;
2033 // This value number needs to go in the final joined live range.
2034 Assignments[ValNo] = NewVNInfo.size();
2035 NewVNInfo.push_back(LR.getValNumInfo(ValNo));
2040 bool JoinVals::mapValues(JoinVals &Other) {
2041 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
2042 computeAssignment(i, Other);
2043 if (Vals[i].Resolution == CR_Impossible) {
2044 DEBUG(dbgs() << "\t\tinterference at " << PrintReg(Reg) << ':' << i
2045 << '@' << LR.getValNumInfo(i)->def << '\n');
2052 /// Assuming ValNo is going to clobber some valid lanes in Other.LR, compute
2053 /// the extent of the tainted lanes in the block.
2055 /// Multiple values in Other.LR can be affected since partial redefinitions can
2056 /// preserve previously tainted lanes.
2058 /// 1 %dst = VLOAD <-- Define all lanes in %dst
2059 /// 2 %src = FOO <-- ValNo to be joined with %dst:ssub0
2060 /// 3 %dst:ssub1 = BAR <-- Partial redef doesn't clear taint in ssub0
2061 /// 4 %dst:ssub0 = COPY %src <-- Conflict resolved, ssub0 wasn't read
2063 /// For each ValNo in Other that is affected, add an (EndIndex, TaintedLanes)
2064 /// entry to TaintedVals.
2066 /// Returns false if the tainted lanes extend beyond the basic block.
2068 taintExtent(unsigned ValNo, unsigned TaintedLanes, JoinVals &Other,
2069 SmallVectorImpl<std::pair<SlotIndex, unsigned> > &TaintExtent) {
2070 VNInfo *VNI = LR.getValNumInfo(ValNo);
2071 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
2072 SlotIndex MBBEnd = Indexes->getMBBEndIdx(MBB);
2074 // Scan Other.LR from VNI.def to MBBEnd.
2075 LiveInterval::iterator OtherI = Other.LR.find(VNI->def);
2076 assert(OtherI != Other.LR.end() && "No conflict?");
2078 // OtherI is pointing to a tainted value. Abort the join if the tainted
2079 // lanes escape the block.
2080 SlotIndex End = OtherI->end;
2081 if (End >= MBBEnd) {
2082 DEBUG(dbgs() << "\t\ttaints global " << PrintReg(Other.Reg) << ':'
2083 << OtherI->valno->id << '@' << OtherI->start << '\n');
2086 DEBUG(dbgs() << "\t\ttaints local " << PrintReg(Other.Reg) << ':'
2087 << OtherI->valno->id << '@' << OtherI->start
2088 << " to " << End << '\n');
2089 // A dead def is not a problem.
2092 TaintExtent.push_back(std::make_pair(End, TaintedLanes));
2094 // Check for another def in the MBB.
2095 if (++OtherI == Other.LR.end() || OtherI->start >= MBBEnd)
2098 // Lanes written by the new def are no longer tainted.
2099 const Val &OV = Other.Vals[OtherI->valno->id];
2100 TaintedLanes &= ~OV.WriteLanes;
2103 } while (TaintedLanes);
2107 /// Return true if MI uses any of the given Lanes from Reg.
2108 /// This does not include partial redefinitions of Reg.
2109 bool JoinVals::usesLanes(const MachineInstr *MI, unsigned Reg, unsigned SubIdx,
2110 unsigned Lanes) const {
2111 if (MI->isDebugValue())
2113 for (ConstMIOperands MO(MI); MO.isValid(); ++MO) {
2114 if (!MO->isReg() || MO->isDef() || MO->getReg() != Reg)
2116 if (!MO->readsReg())
2118 if (Lanes & TRI->getSubRegIndexLaneMask(
2119 TRI->composeSubRegIndices(SubIdx, MO->getSubReg())))
2125 bool JoinVals::resolveConflicts(JoinVals &Other) {
2126 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
2128 assert (V.Resolution != CR_Impossible && "Unresolvable conflict");
2129 if (V.Resolution != CR_Unresolved)
2131 DEBUG(dbgs() << "\t\tconflict at " << PrintReg(Reg) << ':' << i
2132 << '@' << LR.getValNumInfo(i)->def << '\n');
2137 assert(V.OtherVNI && "Inconsistent conflict resolution.");
2138 VNInfo *VNI = LR.getValNumInfo(i);
2139 const Val &OtherV = Other.Vals[V.OtherVNI->id];
2141 // VNI is known to clobber some lanes in OtherVNI. If we go ahead with the
2142 // join, those lanes will be tainted with a wrong value. Get the extent of
2143 // the tainted lanes.
2144 unsigned TaintedLanes = V.WriteLanes & OtherV.ValidLanes;
2145 SmallVector<std::pair<SlotIndex, unsigned>, 8> TaintExtent;
2146 if (!taintExtent(i, TaintedLanes, Other, TaintExtent))
2147 // Tainted lanes would extend beyond the basic block.
2150 assert(!TaintExtent.empty() && "There should be at least one conflict.");
2152 // Now look at the instructions from VNI->def to TaintExtent (inclusive).
2153 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
2154 MachineBasicBlock::iterator MI = MBB->begin();
2155 if (!VNI->isPHIDef()) {
2156 MI = Indexes->getInstructionFromIndex(VNI->def);
2157 // No need to check the instruction defining VNI for reads.
2160 assert(!SlotIndex::isSameInstr(VNI->def, TaintExtent.front().first) &&
2161 "Interference ends on VNI->def. Should have been handled earlier");
2162 MachineInstr *LastMI =
2163 Indexes->getInstructionFromIndex(TaintExtent.front().first);
2164 assert(LastMI && "Range must end at a proper instruction");
2165 unsigned TaintNum = 0;
2167 assert(MI != MBB->end() && "Bad LastMI");
2168 if (usesLanes(MI, Other.Reg, Other.SubIdx, TaintedLanes)) {
2169 DEBUG(dbgs() << "\t\ttainted lanes used by: " << *MI);
2172 // LastMI is the last instruction to use the current value.
2173 if (&*MI == LastMI) {
2174 if (++TaintNum == TaintExtent.size())
2176 LastMI = Indexes->getInstructionFromIndex(TaintExtent[TaintNum].first);
2177 assert(LastMI && "Range must end at a proper instruction");
2178 TaintedLanes = TaintExtent[TaintNum].second;
2183 // The tainted lanes are unused.
2184 V.Resolution = CR_Replace;
2190 // Determine if ValNo is a copy of a value number in LR or Other.LR that will
2194 // %src = COPY %dst <-- This value to be pruned.
2195 // %dst = COPY %src <-- This value is a copy of a pruned value.
2197 bool JoinVals::isPrunedValue(unsigned ValNo, JoinVals &Other) {
2198 Val &V = Vals[ValNo];
2199 if (V.Pruned || V.PrunedComputed)
2202 if (V.Resolution != CR_Erase && V.Resolution != CR_Merge)
2205 // Follow copies up the dominator tree and check if any intermediate value
2207 V.PrunedComputed = true;
2208 V.Pruned = Other.isPrunedValue(V.OtherVNI->id, *this);
2212 void JoinVals::pruneValues(JoinVals &Other,
2213 SmallVectorImpl<SlotIndex> &EndPoints,
2214 bool changeInstrs) {
2215 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
2216 SlotIndex Def = LR.getValNumInfo(i)->def;
2217 switch (Vals[i].Resolution) {
2221 // This value takes precedence over the value in Other.LR.
2222 LIS->pruneValue(Other.LR, Def, &EndPoints);
2223 // Check if we're replacing an IMPLICIT_DEF value. The IMPLICIT_DEF
2224 // instructions are only inserted to provide a live-out value for PHI
2225 // predecessors, so the instruction should simply go away once its value
2226 // has been replaced.
2227 Val &OtherV = Other.Vals[Vals[i].OtherVNI->id];
2228 bool EraseImpDef = OtherV.ErasableImplicitDef &&
2229 OtherV.Resolution == CR_Keep;
2230 if (!Def.isBlock()) {
2232 // Remove <def,read-undef> flags. This def is now a partial redef.
2233 // Also remove <def,dead> flags since the joined live range will
2234 // continue past this instruction.
2235 for (MIOperands MO(Indexes->getInstructionFromIndex(Def));
2236 MO.isValid(); ++MO) {
2237 if (MO->isReg() && MO->isDef() && MO->getReg() == Reg) {
2238 MO->setIsUndef(EraseImpDef);
2239 MO->setIsDead(false);
2243 // This value will reach instructions below, but we need to make sure
2244 // the live range also reaches the instruction at Def.
2246 EndPoints.push_back(Def);
2248 DEBUG(dbgs() << "\t\tpruned " << PrintReg(Other.Reg) << " at " << Def
2249 << ": " << Other.LR << '\n');
2254 if (isPrunedValue(i, Other)) {
2255 // This value is ultimately a copy of a pruned value in LR or Other.LR.
2256 // We can no longer trust the value mapping computed by
2257 // computeAssignment(), the value that was originally copied could have
2259 LIS->pruneValue(LR, Def, &EndPoints);
2260 DEBUG(dbgs() << "\t\tpruned all of " << PrintReg(Reg) << " at "
2261 << Def << ": " << LR << '\n');
2266 llvm_unreachable("Unresolved conflicts");
2271 void JoinVals::pruneSubRegValues(LiveInterval &LI, unsigned &ShrinkMask)
2273 // Look for values being erased.
2274 bool DidPrune = false;
2275 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
2276 if (Vals[i].Resolution != CR_Erase)
2279 // Check subranges at the point where the copy will be removed.
2280 SlotIndex Def = LR.getValNumInfo(i)->def;
2281 for (LiveInterval::SubRange &S : LI.subranges()) {
2282 LiveQueryResult Q = S.Query(Def);
2284 // If a subrange starts at the copy then an undefined value has been
2285 // copied and we must remove that subrange value as well.
2286 VNInfo *ValueOut = Q.valueOutOrDead();
2287 if (ValueOut != nullptr && Q.valueIn() == nullptr) {
2288 DEBUG(dbgs() << "\t\tPrune sublane " << format("%04X", S.LaneMask)
2289 << " at " << Def << "\n");
2290 LIS->pruneValue(S, Def, nullptr);
2292 // Mark value number as unused.
2293 ValueOut->markUnused();
2296 // If a subrange ends at the copy, then a value was copied but only
2297 // partially used later. Shrink the subregister range apropriately.
2298 if (Q.valueIn() != nullptr && Q.valueOut() == nullptr) {
2299 DEBUG(dbgs() << "\t\tDead uses at sublane "
2300 << format("%04X", S.LaneMask) << " at " << Def << "\n");
2301 ShrinkMask |= S.LaneMask;
2306 LI.removeEmptySubRanges();
2309 void JoinVals::eraseInstrs(SmallPtrSetImpl<MachineInstr*> &ErasedInstrs,
2310 SmallVectorImpl<unsigned> &ShrinkRegs) {
2311 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
2312 // Get the def location before markUnused() below invalidates it.
2313 SlotIndex Def = LR.getValNumInfo(i)->def;
2314 switch (Vals[i].Resolution) {
2316 // If an IMPLICIT_DEF value is pruned, it doesn't serve a purpose any
2317 // longer. The IMPLICIT_DEF instructions are only inserted by
2318 // PHIElimination to guarantee that all PHI predecessors have a value.
2319 if (!Vals[i].ErasableImplicitDef || !Vals[i].Pruned)
2321 // Remove value number i from LR. Note that this VNInfo is still present
2322 // in NewVNInfo, so it will appear as an unused value number in the final
2324 LR.getValNumInfo(i)->markUnused();
2325 LR.removeValNo(LR.getValNumInfo(i));
2326 DEBUG(dbgs() << "\t\tremoved " << i << '@' << Def << ": " << LR << '\n');
2330 MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
2331 assert(MI && "No instruction to erase");
2333 unsigned Reg = MI->getOperand(1).getReg();
2334 if (TargetRegisterInfo::isVirtualRegister(Reg) &&
2335 Reg != CP.getSrcReg() && Reg != CP.getDstReg())
2336 ShrinkRegs.push_back(Reg);
2338 ErasedInstrs.insert(MI);
2339 DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI);
2340 LIS->RemoveMachineInstrFromMaps(MI);
2341 MI->eraseFromParent();
2350 void RegisterCoalescer::joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
2352 const CoalescerPair &CP) {
2353 SmallVector<VNInfo*, 16> NewVNInfo;
2354 JoinVals RHSVals(RRange, CP.getSrcReg(), CP.getSrcIdx(), LaneMask,
2355 NewVNInfo, CP, LIS, TRI, true, true);
2356 JoinVals LHSVals(LRange, CP.getDstReg(), CP.getDstIdx(), LaneMask,
2357 NewVNInfo, CP, LIS, TRI, true, true);
2359 /// Compute NewVNInfo and resolve conflicts (see also joinVirtRegs())
2360 /// Conflicts should already be resolved so the mapping/resolution should
2362 if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals))
2363 llvm_unreachable("Can't join subrange although main ranges are compatible");
2364 if (!LHSVals.resolveConflicts(RHSVals) || !RHSVals.resolveConflicts(LHSVals))
2365 llvm_unreachable("Can't join subrange although main ranges are compatible");
2367 // The merging algorithm in LiveInterval::join() can't handle conflicting
2368 // value mappings, so we need to remove any live ranges that overlap a
2369 // CR_Replace resolution. Collect a set of end points that can be used to
2370 // restore the live range after joining.
2371 SmallVector<SlotIndex, 8> EndPoints;
2372 LHSVals.pruneValues(RHSVals, EndPoints, false);
2373 RHSVals.pruneValues(LHSVals, EndPoints, false);
2378 // Join RRange into LHS.
2379 LRange.join(RRange, LHSVals.getAssignments(), RHSVals.getAssignments(),
2382 DEBUG(dbgs() << "\t\tjoined lanes: " << LRange << "\n");
2383 if (EndPoints.empty())
2386 // Recompute the parts of the live range we had to remove because of
2387 // CR_Replace conflicts.
2388 DEBUG(dbgs() << "\t\trestoring liveness to " << EndPoints.size()
2389 << " points: " << LRange << '\n');
2390 LIS->extendToIndices(LRange, EndPoints);
2393 void RegisterCoalescer::mergeSubRangeInto(LiveInterval &LI,
2394 const LiveRange &ToMerge,
2395 unsigned LaneMask, CoalescerPair &CP) {
2396 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
2397 for (LiveInterval::SubRange &R : LI.subranges()) {
2398 unsigned RMask = R.LaneMask;
2399 // LaneMask of subregisters common to subrange R and ToMerge.
2400 unsigned Common = RMask & LaneMask;
2401 // There is nothing to do without common subregs.
2405 DEBUG(dbgs() << format("\t\tCopy+Merge %04X into %04X\n", RMask, Common));
2406 // LaneMask of subregisters contained in the R range but not in ToMerge,
2407 // they have to split into their own subrange.
2408 unsigned LRest = RMask & ~LaneMask;
2409 LiveInterval::SubRange *CommonRange;
2412 DEBUG(dbgs() << format("\t\tReduce Lane to %04X\n", LRest));
2413 // Duplicate SubRange for newly merged common stuff.
2414 CommonRange = LI.createSubRangeFrom(Allocator, Common, R);
2416 // Reuse the existing range.
2417 R.LaneMask = Common;
2420 LiveRange RangeCopy(ToMerge, Allocator);
2421 joinSubRegRanges(*CommonRange, RangeCopy, Common, CP);
2425 if (LaneMask != 0) {
2426 DEBUG(dbgs() << format("\t\tNew Lane %04X\n", LaneMask));
2427 LI.createSubRangeFrom(Allocator, LaneMask, ToMerge);
2431 bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
2432 SmallVector<VNInfo*, 16> NewVNInfo;
2433 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
2434 LiveInterval &LHS = LIS->getInterval(CP.getDstReg());
2435 bool TrackSubRegLiveness = MRI->tracksSubRegLiveness();
2436 JoinVals RHSVals(RHS, CP.getSrcReg(), CP.getSrcIdx(), 0, NewVNInfo, CP, LIS,
2437 TRI, false, TrackSubRegLiveness);
2438 JoinVals LHSVals(LHS, CP.getDstReg(), CP.getDstIdx(), 0, NewVNInfo, CP, LIS,
2439 TRI, false, TrackSubRegLiveness);
2441 DEBUG(dbgs() << "\t\tRHS = " << RHS
2442 << "\n\t\tLHS = " << LHS
2445 // First compute NewVNInfo and the simple value mappings.
2446 // Detect impossible conflicts early.
2447 if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals))
2450 // Some conflicts can only be resolved after all values have been mapped.
2451 if (!LHSVals.resolveConflicts(RHSVals) || !RHSVals.resolveConflicts(LHSVals))
2454 // All clear, the live ranges can be merged.
2455 if (RHS.hasSubRanges() || LHS.hasSubRanges()) {
2456 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
2458 // Transform lanemasks from the LHS to masks in the coalesced register and
2459 // create initial subranges if necessary.
2460 unsigned DstIdx = CP.getDstIdx();
2461 if (!LHS.hasSubRanges()) {
2462 unsigned Mask = DstIdx == 0 ? CP.getNewRC()->getLaneMask()
2463 : TRI->getSubRegIndexLaneMask(DstIdx);
2464 // LHS must support subregs or we wouldn't be in this codepath.
2466 LHS.createSubRangeFrom(Allocator, Mask, LHS);
2467 } else if (DstIdx != 0) {
2468 // Transform LHS lanemasks to new register class if necessary.
2469 for (LiveInterval::SubRange &R : LHS.subranges()) {
2470 unsigned Mask = TRI->composeSubRegIndexLaneMask(DstIdx, R.LaneMask);
2474 DEBUG(dbgs() << "\t\tLHST = " << PrintReg(CP.getDstReg())
2475 << ' ' << LHS << '\n');
2477 // Determine lanemasks of RHS in the coalesced register and merge subranges.
2478 unsigned SrcIdx = CP.getSrcIdx();
2479 if (!RHS.hasSubRanges()) {
2480 unsigned Mask = SrcIdx == 0 ? CP.getNewRC()->getLaneMask()
2481 : TRI->getSubRegIndexLaneMask(SrcIdx);
2482 mergeSubRangeInto(LHS, RHS, Mask, CP);
2484 // Pair up subranges and merge.
2485 for (LiveInterval::SubRange &R : RHS.subranges()) {
2486 unsigned Mask = TRI->composeSubRegIndexLaneMask(SrcIdx, R.LaneMask);
2487 mergeSubRangeInto(LHS, R, Mask, CP);
2491 DEBUG(dbgs() << "\tJoined SubRanges " << LHS << "\n");
2493 LHSVals.pruneSubRegValues(LHS, ShrinkMask);
2494 RHSVals.pruneSubRegValues(LHS, ShrinkMask);
2497 // The merging algorithm in LiveInterval::join() can't handle conflicting
2498 // value mappings, so we need to remove any live ranges that overlap a
2499 // CR_Replace resolution. Collect a set of end points that can be used to
2500 // restore the live range after joining.
2501 SmallVector<SlotIndex, 8> EndPoints;
2502 LHSVals.pruneValues(RHSVals, EndPoints, true);
2503 RHSVals.pruneValues(LHSVals, EndPoints, true);
2505 // Erase COPY and IMPLICIT_DEF instructions. This may cause some external
2506 // registers to require trimming.
2507 SmallVector<unsigned, 8> ShrinkRegs;
2508 LHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
2509 RHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
2510 while (!ShrinkRegs.empty())
2511 LIS->shrinkToUses(&LIS->getInterval(ShrinkRegs.pop_back_val()));
2513 // Join RHS into LHS.
2514 LHS.join(RHS, LHSVals.getAssignments(), RHSVals.getAssignments(), NewVNInfo);
2516 // Kill flags are going to be wrong if the live ranges were overlapping.
2517 // Eventually, we should simply clear all kill flags when computing live
2518 // ranges. They are reinserted after register allocation.
2519 MRI->clearKillFlags(LHS.reg);
2520 MRI->clearKillFlags(RHS.reg);
2522 if (!EndPoints.empty()) {
2523 // Recompute the parts of the live range we had to remove because of
2524 // CR_Replace conflicts.
2525 DEBUG(dbgs() << "\t\trestoring liveness to " << EndPoints.size()
2526 << " points: " << LHS << '\n');
2527 LIS->extendToIndices((LiveRange&)LHS, EndPoints);
2533 /// Attempt to join these two intervals. On failure, this returns false.
2534 bool RegisterCoalescer::joinIntervals(CoalescerPair &CP) {
2535 return CP.isPhys() ? joinReservedPhysReg(CP) : joinVirtRegs(CP);
2539 // Information concerning MBB coalescing priority.
2540 struct MBBPriorityInfo {
2541 MachineBasicBlock *MBB;
2545 MBBPriorityInfo(MachineBasicBlock *mbb, unsigned depth, bool issplit)
2546 : MBB(mbb), Depth(depth), IsSplit(issplit) {}
2550 // C-style comparator that sorts first based on the loop depth of the basic
2551 // block (the unsigned), and then on the MBB number.
2553 // EnableGlobalCopies assumes that the primary sort key is loop depth.
2554 static int compareMBBPriority(const MBBPriorityInfo *LHS,
2555 const MBBPriorityInfo *RHS) {
2556 // Deeper loops first
2557 if (LHS->Depth != RHS->Depth)
2558 return LHS->Depth > RHS->Depth ? -1 : 1;
2560 // Try to unsplit critical edges next.
2561 if (LHS->IsSplit != RHS->IsSplit)
2562 return LHS->IsSplit ? -1 : 1;
2564 // Prefer blocks that are more connected in the CFG. This takes care of
2565 // the most difficult copies first while intervals are short.
2566 unsigned cl = LHS->MBB->pred_size() + LHS->MBB->succ_size();
2567 unsigned cr = RHS->MBB->pred_size() + RHS->MBB->succ_size();
2569 return cl > cr ? -1 : 1;
2571 // As a last resort, sort by block number.
2572 return LHS->MBB->getNumber() < RHS->MBB->getNumber() ? -1 : 1;
2575 /// \returns true if the given copy uses or defines a local live range.
2576 static bool isLocalCopy(MachineInstr *Copy, const LiveIntervals *LIS) {
2577 if (!Copy->isCopy())
2580 if (Copy->getOperand(1).isUndef())
2583 unsigned SrcReg = Copy->getOperand(1).getReg();
2584 unsigned DstReg = Copy->getOperand(0).getReg();
2585 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)
2586 || TargetRegisterInfo::isPhysicalRegister(DstReg))
2589 return LIS->intervalIsInOneMBB(LIS->getInterval(SrcReg))
2590 || LIS->intervalIsInOneMBB(LIS->getInterval(DstReg));
2593 // Try joining WorkList copies starting from index From.
2594 // Null out any successful joins.
2595 bool RegisterCoalescer::
2596 copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList) {
2597 bool Progress = false;
2598 for (unsigned i = 0, e = CurrList.size(); i != e; ++i) {
2601 // Skip instruction pointers that have already been erased, for example by
2602 // dead code elimination.
2603 if (ErasedInstrs.erase(CurrList[i])) {
2604 CurrList[i] = nullptr;
2608 bool Success = joinCopy(CurrList[i], Again);
2609 Progress |= Success;
2610 if (Success || !Again)
2611 CurrList[i] = nullptr;
2617 RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
2618 DEBUG(dbgs() << MBB->getName() << ":\n");
2620 // Collect all copy-like instructions in MBB. Don't start coalescing anything
2621 // yet, it might invalidate the iterator.
2622 const unsigned PrevSize = WorkList.size();
2623 if (JoinGlobalCopies) {
2624 // Coalesce copies bottom-up to coalesce local defs before local uses. They
2625 // are not inherently easier to resolve, but slightly preferable until we
2626 // have local live range splitting. In particular this is required by
2627 // cmp+jmp macro fusion.
2628 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2630 if (!MII->isCopyLike())
2632 if (isLocalCopy(&(*MII), LIS))
2633 LocalWorkList.push_back(&(*MII));
2635 WorkList.push_back(&(*MII));
2639 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2641 if (MII->isCopyLike())
2642 WorkList.push_back(MII);
2644 // Try coalescing the collected copies immediately, and remove the nulls.
2645 // This prevents the WorkList from getting too large since most copies are
2646 // joinable on the first attempt.
2647 MutableArrayRef<MachineInstr*>
2648 CurrList(WorkList.begin() + PrevSize, WorkList.end());
2649 if (copyCoalesceWorkList(CurrList))
2650 WorkList.erase(std::remove(WorkList.begin() + PrevSize, WorkList.end(),
2651 (MachineInstr*)nullptr), WorkList.end());
2654 void RegisterCoalescer::coalesceLocals() {
2655 copyCoalesceWorkList(LocalWorkList);
2656 for (unsigned j = 0, je = LocalWorkList.size(); j != je; ++j) {
2657 if (LocalWorkList[j])
2658 WorkList.push_back(LocalWorkList[j]);
2660 LocalWorkList.clear();
2663 void RegisterCoalescer::joinAllIntervals() {
2664 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
2665 assert(WorkList.empty() && LocalWorkList.empty() && "Old data still around.");
2667 std::vector<MBBPriorityInfo> MBBs;
2668 MBBs.reserve(MF->size());
2669 for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
2670 MachineBasicBlock *MBB = I;
2671 MBBs.push_back(MBBPriorityInfo(MBB, Loops->getLoopDepth(MBB),
2672 JoinSplitEdges && isSplitEdge(MBB)));
2674 array_pod_sort(MBBs.begin(), MBBs.end(), compareMBBPriority);
2676 // Coalesce intervals in MBB priority order.
2677 unsigned CurrDepth = UINT_MAX;
2678 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
2679 // Try coalescing the collected local copies for deeper loops.
2680 if (JoinGlobalCopies && MBBs[i].Depth < CurrDepth) {
2682 CurrDepth = MBBs[i].Depth;
2684 copyCoalesceInMBB(MBBs[i].MBB);
2688 // Joining intervals can allow other intervals to be joined. Iteratively join
2689 // until we make no progress.
2690 while (copyCoalesceWorkList(WorkList))
2694 void RegisterCoalescer::releaseMemory() {
2695 ErasedInstrs.clear();
2698 InflateRegs.clear();
2701 bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
2703 MRI = &fn.getRegInfo();
2704 TM = &fn.getTarget();
2705 TRI = TM->getSubtargetImpl()->getRegisterInfo();
2706 TII = TM->getSubtargetImpl()->getInstrInfo();
2707 LIS = &getAnalysis<LiveIntervals>();
2708 AA = &getAnalysis<AliasAnalysis>();
2709 Loops = &getAnalysis<MachineLoopInfo>();
2711 const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>();
2712 if (EnableGlobalCopies == cl::BOU_UNSET)
2713 JoinGlobalCopies = ST.useMachineScheduler();
2715 JoinGlobalCopies = (EnableGlobalCopies == cl::BOU_TRUE);
2717 // The MachineScheduler does not currently require JoinSplitEdges. This will
2718 // either be enabled unconditionally or replaced by a more general live range
2719 // splitting optimization.
2720 JoinSplitEdges = EnableJoinSplits;
2722 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
2723 << "********** Function: " << MF->getName() << '\n');
2725 if (VerifyCoalescing)
2726 MF->verify(this, "Before register coalescing");
2728 RegClassInfo.runOnMachineFunction(fn);
2730 // Join (coalesce) intervals if requested.
2734 // After deleting a lot of copies, register classes may be less constrained.
2735 // Removing sub-register operands may allow GR32_ABCD -> GR32 and DPR_VFP2 ->
2737 array_pod_sort(InflateRegs.begin(), InflateRegs.end());
2738 InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
2740 DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n");
2741 for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
2742 unsigned Reg = InflateRegs[i];
2743 if (MRI->reg_nodbg_empty(Reg))
2745 if (MRI->recomputeRegClass(Reg, *TM)) {
2746 DEBUG(dbgs() << PrintReg(Reg) << " inflated to "
2747 << TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n');
2748 LiveInterval &LI = LIS->getInterval(Reg);
2749 unsigned MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
2751 // If the inflated register class does not support subregisters anymore
2752 // remove the subranges.
2753 LI.clearSubRanges();
2755 // If subranges are still supported, then the same subregs should still
2758 for (LiveInterval::SubRange &S : LI.subranges()) {
2759 assert ((S.LaneMask & ~MaxMask) == 0);
2768 if (VerifyCoalescing)
2769 MF->verify(this, "After register coalescing");
2773 /// Implement the dump method.
2774 void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {