1 //===-- RegAllocLocal.cpp - A BasicBlock generic register allocator -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/BasicBlock.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/IndexedMap.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/ADT/STLExtras.h"
36 STATISTIC(NumStores, "Number of stores added");
37 STATISTIC(NumLoads , "Number of loads added");
39 static RegisterRegAlloc
40 localRegAlloc("local", " local register allocator",
41 createLocalRegisterAllocator);
44 class VISIBILITY_HIDDEN RALocal : public MachineFunctionPass {
47 RALocal() : MachineFunctionPass((intptr_t)&ID),
48 StackSlotForVirtReg(-1) {}
50 const TargetMachine *TM;
52 const TargetRegisterInfo *TRI;
53 const TargetInstrInfo *TII;
55 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
56 // values are spilled.
57 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
59 // Virt2PhysRegMap - This map contains entries for each virtual register
60 // that is currently available in a physical register.
61 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysRegMap;
63 unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
64 return Virt2PhysRegMap[VirtReg];
67 // PhysRegsUsed - This array is effectively a map, containing entries for
68 // each physical register that currently has a value (ie, it is in
69 // Virt2PhysRegMap). The value mapped to is the virtual register
70 // corresponding to the physical register (the inverse of the
71 // Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned
72 // because it is used by a future instruction, and to -2 if it is not
73 // allocatable. If the entry for a physical register is -1, then the
74 // physical register is "not in the map".
76 std::vector<int> PhysRegsUsed;
78 // PhysRegsUseOrder - This contains a list of the physical registers that
79 // currently have a virtual register value in them. This list provides an
80 // ordering of registers, imposing a reallocation order. This list is only
81 // used if all registers are allocated and we have to spill one, in which
82 // case we spill the least recently used register. Entries at the front of
83 // the list are the least recently used registers, entries at the back are
84 // the most recently used.
86 std::vector<unsigned> PhysRegsUseOrder;
88 // Virt2LastUseMap - This maps each virtual register to its last use
89 // (MachineInstr*, operand index pair).
90 IndexedMap<std::pair<MachineInstr*, unsigned>, VirtReg2IndexFunctor>
93 std::pair<MachineInstr*,unsigned>& getVirtRegLastUse(unsigned Reg) {
94 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
95 return Virt2LastUseMap[Reg];
98 // VirtRegModified - This bitset contains information about which virtual
99 // registers need to be spilled back to memory when their registers are
100 // scavenged. If a virtual register has simply been rematerialized, there
101 // is no reason to spill it to memory when we need the register back.
103 BitVector VirtRegModified;
105 // UsedInMultipleBlocks - Tracks whether a particular register is used in
106 // more than one block.
107 BitVector UsedInMultipleBlocks;
109 void markVirtRegModified(unsigned Reg, bool Val = true) {
110 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
111 Reg -= TargetRegisterInfo::FirstVirtualRegister;
113 VirtRegModified.set(Reg);
115 VirtRegModified.reset(Reg);
118 bool isVirtRegModified(unsigned Reg) const {
119 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
120 assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
121 && "Illegal virtual register!");
122 return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
125 void AddToPhysRegsUseOrder(unsigned Reg) {
126 std::vector<unsigned>::iterator It =
127 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), Reg);
128 if (It != PhysRegsUseOrder.end())
129 PhysRegsUseOrder.erase(It);
130 PhysRegsUseOrder.push_back(Reg);
133 void MarkPhysRegRecentlyUsed(unsigned Reg) {
134 if (PhysRegsUseOrder.empty() ||
135 PhysRegsUseOrder.back() == Reg) return; // Already most recently used
137 for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i)
138 if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) {
139 unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle
140 PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1);
141 // Add it to the end of the list
142 PhysRegsUseOrder.push_back(RegMatch);
144 return; // Found an exact match, exit early
149 virtual const char *getPassName() const {
150 return "Local Register Allocator";
153 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
154 AU.addRequiredID(PHIEliminationID);
155 AU.addRequiredID(TwoAddressInstructionPassID);
156 MachineFunctionPass::getAnalysisUsage(AU);
160 /// runOnMachineFunction - Register allocate the whole function
161 bool runOnMachineFunction(MachineFunction &Fn);
163 /// AllocateBasicBlock - Register allocate the specified basic block.
164 void AllocateBasicBlock(MachineBasicBlock &MBB);
167 /// areRegsEqual - This method returns true if the specified registers are
168 /// related to each other. To do this, it checks to see if they are equal
169 /// or if the first register is in the alias set of the second register.
171 bool areRegsEqual(unsigned R1, unsigned R2) const {
172 if (R1 == R2) return true;
173 for (const unsigned *AliasSet = TRI->getAliasSet(R2);
174 *AliasSet; ++AliasSet) {
175 if (*AliasSet == R1) return true;
180 /// getStackSpaceFor - This returns the frame index of the specified virtual
181 /// register on the stack, allocating space if necessary.
182 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
184 /// removePhysReg - This method marks the specified physical register as no
185 /// longer being in use.
187 void removePhysReg(unsigned PhysReg);
189 /// spillVirtReg - This method spills the value specified by PhysReg into
190 /// the virtual register slot specified by VirtReg. It then updates the RA
191 /// data structures to indicate the fact that PhysReg is now available.
193 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
194 unsigned VirtReg, unsigned PhysReg);
196 /// spillPhysReg - This method spills the specified physical register into
197 /// the virtual register slot associated with it. If OnlyVirtRegs is set to
198 /// true, then the request is ignored if the physical register does not
199 /// contain a virtual register.
201 void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
202 unsigned PhysReg, bool OnlyVirtRegs = false);
204 /// assignVirtToPhysReg - This method updates local state so that we know
205 /// that PhysReg is the proper container for VirtReg now. The physical
206 /// register must not be used for anything else when this is called.
208 void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
210 /// isPhysRegAvailable - Return true if the specified physical register is
211 /// free and available for use. This also includes checking to see if
212 /// aliased registers are all free...
214 bool isPhysRegAvailable(unsigned PhysReg) const;
216 /// getFreeReg - Look to see if there is a free register available in the
217 /// specified register class. If not, return 0.
219 unsigned getFreeReg(const TargetRegisterClass *RC);
221 /// getReg - Find a physical register to hold the specified virtual
222 /// register. If all compatible physical registers are used, this method
223 /// spills the last used virtual register to the stack, and uses that
226 unsigned getReg(MachineBasicBlock &MBB, MachineInstr *MI,
229 /// reloadVirtReg - This method transforms the specified specified virtual
230 /// register use to refer to a physical register. This method may do this
231 /// in one of several ways: if the register is available in a physical
232 /// register already, it uses that physical register. If the value is not
233 /// in a physical register, and if there are physical registers available,
234 /// it loads it into a register. If register pressure is high, and it is
235 /// possible, it tries to fold the load of the virtual register into the
236 /// instruction itself. It avoids doing this if register pressure is low to
237 /// improve the chance that subsequent instructions can use the reloaded
238 /// value. This method returns the modified instruction.
240 MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
243 /// ComputeLocalLiveness - Computes liveness of registers within a basic
244 /// block, setting the killed/dead flags as appropriate.
245 void ComputeLocalLiveness(MachineBasicBlock& MBB);
247 void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
250 char RALocal::ID = 0;
253 /// getStackSpaceFor - This allocates space for the specified virtual register
254 /// to be held on the stack.
255 int RALocal::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
256 // Find the location Reg would belong...
257 int SS = StackSlotForVirtReg[VirtReg];
259 return SS; // Already has space allocated?
261 // Allocate a new stack object for this spill location...
262 int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
265 // Assign the slot...
266 StackSlotForVirtReg[VirtReg] = FrameIdx;
271 /// removePhysReg - This method marks the specified physical register as no
272 /// longer being in use.
274 void RALocal::removePhysReg(unsigned PhysReg) {
275 PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used
277 std::vector<unsigned>::iterator It =
278 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), PhysReg);
279 if (It != PhysRegsUseOrder.end())
280 PhysRegsUseOrder.erase(It);
284 /// spillVirtReg - This method spills the value specified by PhysReg into the
285 /// virtual register slot specified by VirtReg. It then updates the RA data
286 /// structures to indicate the fact that PhysReg is now available.
288 void RALocal::spillVirtReg(MachineBasicBlock &MBB,
289 MachineBasicBlock::iterator I,
290 unsigned VirtReg, unsigned PhysReg) {
291 assert(VirtReg && "Spilling a physical register is illegal!"
292 " Must not have appropriate kill for the register or use exists beyond"
293 " the intended one.");
294 DOUT << " Spilling register " << TRI->getName(PhysReg)
295 << " containing %reg" << VirtReg;
297 if (!isVirtRegModified(VirtReg)) {
298 DOUT << " which has not been modified, so no store necessary!";
299 std::pair<MachineInstr*, unsigned> &LastUse = getVirtRegLastUse(VirtReg);
301 LastUse.first->getOperand(LastUse.second).setIsKill();
303 // Otherwise, there is a virtual register corresponding to this physical
304 // register. We only need to spill it into its stack slot if it has been
306 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
307 int FrameIndex = getStackSpaceFor(VirtReg, RC);
308 DOUT << " to stack slot #" << FrameIndex;
309 // If the instruction reads the register that's spilled, (e.g. this can
310 // happen if it is a move to a physical register), then the spill
311 // instruction is not a kill.
312 bool isKill = !(I != MBB.end() && I->readsRegister(PhysReg));
313 TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC);
314 ++NumStores; // Update statistics
317 getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available
320 removePhysReg(PhysReg);
324 /// spillPhysReg - This method spills the specified physical register into the
325 /// virtual register slot associated with it. If OnlyVirtRegs is set to true,
326 /// then the request is ignored if the physical register does not contain a
327 /// virtual register.
329 void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
330 unsigned PhysReg, bool OnlyVirtRegs) {
331 if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used!
332 assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
333 if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
334 spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
336 // If the selected register aliases any other registers, we must make
337 // sure that one of the aliases isn't alive.
338 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
339 *AliasSet; ++AliasSet)
340 if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register.
341 PhysRegsUsed[*AliasSet] != -2) // If allocatable.
342 if (PhysRegsUsed[*AliasSet])
343 spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
348 /// assignVirtToPhysReg - This method updates local state so that we know
349 /// that PhysReg is the proper container for VirtReg now. The physical
350 /// register must not be used for anything else when this is called.
352 void RALocal::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
353 assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
354 // Update information to note the fact that this register was just used, and
356 PhysRegsUsed[PhysReg] = VirtReg;
357 getVirt2PhysRegMapSlot(VirtReg) = PhysReg;
358 AddToPhysRegsUseOrder(PhysReg); // New use of PhysReg
362 /// isPhysRegAvailable - Return true if the specified physical register is free
363 /// and available for use. This also includes checking to see if aliased
364 /// registers are all free...
366 bool RALocal::isPhysRegAvailable(unsigned PhysReg) const {
367 if (PhysRegsUsed[PhysReg] != -1) return false;
369 // If the selected register aliases any other allocated registers, it is
371 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
372 *AliasSet; ++AliasSet)
373 if (PhysRegsUsed[*AliasSet] >= 0) // Aliased register in use?
374 return false; // Can't use this reg then.
379 /// getFreeReg - Look to see if there is a free register available in the
380 /// specified register class. If not, return 0.
382 unsigned RALocal::getFreeReg(const TargetRegisterClass *RC) {
383 // Get iterators defining the range of registers that are valid to allocate in
384 // this class, which also specifies the preferred allocation order.
385 TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
386 TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
388 for (; RI != RE; ++RI)
389 if (isPhysRegAvailable(*RI)) { // Is reg unused?
390 assert(*RI != 0 && "Cannot use register!");
391 return *RI; // Found an unused register!
397 /// getReg - Find a physical register to hold the specified virtual
398 /// register. If all compatible physical registers are used, this method spills
399 /// the last used virtual register to the stack, and uses that register.
401 unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
403 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
405 // First check to see if we have a free register of the requested type...
406 unsigned PhysReg = getFreeReg(RC);
408 // If we didn't find an unused register, scavenge one now!
410 assert(!PhysRegsUseOrder.empty() && "No allocated registers??");
412 // Loop over all of the preallocated registers from the least recently used
413 // to the most recently used. When we find one that is capable of holding
414 // our register, use it.
415 for (unsigned i = 0; PhysReg == 0; ++i) {
416 assert(i != PhysRegsUseOrder.size() &&
417 "Couldn't find a register of the appropriate class!");
419 unsigned R = PhysRegsUseOrder[i];
421 // We can only use this register if it holds a virtual register (ie, it
422 // can be spilled). Do not use it if it is an explicitly allocated
423 // physical register!
424 assert(PhysRegsUsed[R] != -1 &&
425 "PhysReg in PhysRegsUseOrder, but is not allocated?");
426 if (PhysRegsUsed[R] && PhysRegsUsed[R] != -2) {
427 // If the current register is compatible, use it.
428 if (RC->contains(R)) {
432 // If one of the registers aliased to the current register is
433 // compatible, use it.
434 for (const unsigned *AliasIt = TRI->getAliasSet(R);
435 *AliasIt; ++AliasIt) {
436 if (RC->contains(*AliasIt) &&
437 // If this is pinned down for some reason, don't use it. For
438 // example, if CL is pinned, and we run across CH, don't use
439 // CH as justification for using scavenging ECX (which will
441 PhysRegsUsed[*AliasIt] != 0 &&
443 // Make sure the register is allocatable. Don't allocate SIL on
445 PhysRegsUsed[*AliasIt] != -2) {
446 PhysReg = *AliasIt; // Take an aliased register
454 assert(PhysReg && "Physical register not assigned!?!?");
456 // At this point PhysRegsUseOrder[i] is the least recently used register of
457 // compatible register class. Spill it to memory and reap its remains.
458 spillPhysReg(MBB, I, PhysReg);
461 // Now that we know which register we need to assign this to, do it now!
462 assignVirtToPhysReg(VirtReg, PhysReg);
467 /// reloadVirtReg - This method transforms the specified specified virtual
468 /// register use to refer to a physical register. This method may do this in
469 /// one of several ways: if the register is available in a physical register
470 /// already, it uses that physical register. If the value is not in a physical
471 /// register, and if there are physical registers available, it loads it into a
472 /// register. If register pressure is high, and it is possible, it tries to
473 /// fold the load of the virtual register into the instruction itself. It
474 /// avoids doing this if register pressure is low to improve the chance that
475 /// subsequent instructions can use the reloaded value. This method returns the
476 /// modified instruction.
478 MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
480 unsigned VirtReg = MI->getOperand(OpNum).getReg();
482 // If the virtual register is already available, just update the instruction
484 if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
485 MarkPhysRegRecentlyUsed(PR); // Already have this value available!
486 MI->getOperand(OpNum).setReg(PR); // Assign the input register
487 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
491 // Otherwise, we need to fold it into the current instruction, or reload it.
492 // If we have registers available to hold the value, use them.
493 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
494 unsigned PhysReg = getFreeReg(RC);
495 int FrameIndex = getStackSpaceFor(VirtReg, RC);
497 if (PhysReg) { // Register is available, allocate it!
498 assignVirtToPhysReg(VirtReg, PhysReg);
499 } else { // No registers available.
500 // Force some poor hapless value out of the register file to
501 // make room for the new register, and reload it.
502 PhysReg = getReg(MBB, MI, VirtReg);
505 markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
507 DOUT << " Reloading %reg" << VirtReg << " into "
508 << TRI->getName(PhysReg) << "\n";
510 // Add move instruction(s)
511 TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
512 ++NumLoads; // Update statistics
514 MF->getRegInfo().setPhysRegUsed(PhysReg);
515 MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
516 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
520 /// isReadModWriteImplicitKill - True if this is an implicit kill for a
521 /// read/mod/write register, i.e. update partial register.
522 static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
523 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
524 MachineOperand& MO = MI->getOperand(i);
525 if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() &&
526 MO.isDef() && !MO.isDead())
532 /// isReadModWriteImplicitDef - True if this is an implicit def for a
533 /// read/mod/write register, i.e. update partial register.
534 static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
535 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
536 MachineOperand& MO = MI->getOperand(i);
537 if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() &&
538 !MO.isDef() && MO.isKill())
544 // precedes - Helper function to determine with MachineInstr A
545 // precedes MachineInstr B within the same MBB.
546 static bool precedes(MachineBasicBlock::iterator A,
547 MachineBasicBlock::iterator B) {
551 MachineBasicBlock::iterator I = A->getParent()->begin();
552 while (I != A->getParent()->end()) {
565 template<> struct DenseMapInfo<uint32_t> {
566 static inline uint32_t getEmptyKey() { return ~0; }
567 static inline uint32_t getTombstoneKey() { return ~0 - 1; }
568 static unsigned getHashValue(const uint32_t& Val) { return Val * 37; }
569 static bool isPod() { return true; }
570 static bool isEqual(const uint32_t& LHS, const uint32_t& RHS) {
576 /// ComputeLocalLiveness - Computes liveness of registers within a basic
577 /// block, setting the killed/dead flags as appropriate.
578 void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
579 MachineRegisterInfo& MRI = MBB.getParent()->getRegInfo();
580 // Keep track of the most recently seen previous use or def of each reg,
581 // so that we can update them with dead/kill markers.
582 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> > LastUseDef;
583 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
585 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
586 MachineOperand& MO = I->getOperand(i);
587 // Uses don't trigger any flags, but we need to save
588 // them for later. Also, we have to process these
589 // _before_ processing the defs, since an instr
590 // uses regs before it defs them.
591 if (MO.isReg() && MO.getReg() && MO.isUse())
592 LastUseDef[MO.getReg()] = std::make_pair(I, i);
595 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
596 MachineOperand& MO = I->getOperand(i);
597 // Defs others than 2-addr redefs _do_ trigger flag changes:
598 // - A def followed by a def is dead
599 // - A use followed by a def is a kill
600 if (MO.isReg() && MO.getReg() && MO.isDef()) {
601 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
602 last = LastUseDef.find(MO.getReg());
603 if (last != LastUseDef.end()) {
604 // Check if this is a two address instruction. If so, then
605 // the def does not kill the use.
606 if (last->second.first == I &&
607 I->isRegReDefinedByTwoAddr(MO.getReg(), i))
610 MachineOperand& lastUD =
611 last->second.first->getOperand(last->second.second);
613 lastUD.setIsDead(true);
615 lastUD.setIsKill(true);
618 LastUseDef[MO.getReg()] = std::make_pair(I, i);
623 // Live-out (of the function) registers contain return values of the function,
624 // so we need to make sure they are alive at return time.
625 if (!MBB.empty() && MBB.back().getDesc().isReturn()) {
626 MachineInstr* Ret = &MBB.back();
627 for (MachineRegisterInfo::liveout_iterator
628 I = MF->getRegInfo().liveout_begin(),
629 E = MF->getRegInfo().liveout_end(); I != E; ++I)
630 if (!Ret->readsRegister(*I)) {
631 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
632 LastUseDef[*I] = std::make_pair(Ret, Ret->getNumOperands()-1);
636 // Finally, loop over the final use/def of each reg
637 // in the block and determine if it is dead.
638 for (DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
639 I = LastUseDef.begin(), E = LastUseDef.end(); I != E; ++I) {
640 MachineInstr* MI = I->second.first;
641 unsigned idx = I->second.second;
642 MachineOperand& MO = MI->getOperand(idx);
644 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(MO.getReg());
646 // A crude approximation of "live-out" calculation
647 bool usedOutsideBlock = isPhysReg ? false :
648 UsedInMultipleBlocks.test(MO.getReg() -
649 TargetRegisterInfo::FirstVirtualRegister);
650 if (!isPhysReg && !usedOutsideBlock)
651 for (MachineRegisterInfo::reg_iterator UI = MRI.reg_begin(MO.getReg()),
652 UE = MRI.reg_end(); UI != UE; ++UI)
654 // - used in another block
655 // - used in the same block before it is defined (loop)
656 if (UI->getParent() != &MBB ||
657 (MO.isDef() && UI.getOperand().isUse() && precedes(&*UI, MI))) {
658 UsedInMultipleBlocks.set(MO.getReg() -
659 TargetRegisterInfo::FirstVirtualRegister);
660 usedOutsideBlock = true;
664 // Physical registers and those that are not live-out of the block
665 // are killed/dead at their last use/def within this block.
666 if (isPhysReg || !usedOutsideBlock) {
675 void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
676 // loop over each instruction
677 MachineBasicBlock::iterator MII = MBB.begin();
679 DEBUG(const BasicBlock *LBB = MBB.getBasicBlock();
680 if (LBB) DOUT << "\nStarting RegAlloc of BB: " << LBB->getName());
682 // If this is the first basic block in the machine function, add live-in
683 // registers as active.
684 if (&MBB == &*MF->begin() || MBB.isLandingPad()) {
685 for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
686 E = MBB.livein_end(); I != E; ++I) {
688 MF->getRegInfo().setPhysRegUsed(Reg);
689 PhysRegsUsed[Reg] = 0; // It is free and reserved now
690 AddToPhysRegsUseOrder(Reg);
691 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
692 *AliasSet; ++AliasSet) {
693 if (PhysRegsUsed[*AliasSet] != -2) {
694 AddToPhysRegsUseOrder(*AliasSet);
695 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
696 MF->getRegInfo().setPhysRegUsed(*AliasSet);
702 ComputeLocalLiveness(MBB);
704 // Otherwise, sequentially allocate each instruction in the MBB.
705 while (MII != MBB.end()) {
706 MachineInstr *MI = MII++;
707 const TargetInstrDesc &TID = MI->getDesc();
708 DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI;
709 DOUT << " Regs have values: ";
710 for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
711 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
712 DOUT << "[" << TRI->getName(i)
713 << ",%reg" << PhysRegsUsed[i] << "] ";
716 // Loop over the implicit uses, making sure that they are at the head of the
717 // use order list, so they don't get reallocated.
718 if (TID.ImplicitUses) {
719 for (const unsigned *ImplicitUses = TID.ImplicitUses;
720 *ImplicitUses; ++ImplicitUses)
721 MarkPhysRegRecentlyUsed(*ImplicitUses);
724 SmallVector<unsigned, 8> Kills;
725 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
726 MachineOperand& MO = MI->getOperand(i);
727 if (MO.isRegister() && MO.isKill()) {
728 if (!MO.isImplicit())
729 Kills.push_back(MO.getReg());
730 else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
731 // These are extra physical register kills when a sub-register
732 // is defined (def of a sub-register is a read/mod/write of the
733 // larger registers). Ignore.
734 Kills.push_back(MO.getReg());
738 // Get the used operands into registers. This has the potential to spill
739 // incoming values if we are out of registers. Note that we completely
740 // ignore physical register uses here. We assume that if an explicit
741 // physical register is referenced by the instruction, that it is guaranteed
742 // to be live-in, or the input is badly hosed.
744 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
745 MachineOperand& MO = MI->getOperand(i);
746 // here we are looking for only used operands (never def&use)
747 if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
748 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
749 MI = reloadVirtReg(MBB, MI, i);
752 // If this instruction is the last user of this register, kill the
753 // value, freeing the register being used, so it doesn't need to be
754 // spilled to memory.
756 for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
757 unsigned VirtReg = Kills[i];
758 unsigned PhysReg = VirtReg;
759 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
760 // If the virtual register was never materialized into a register, it
761 // might not be in the map, but it won't hurt to zero it out anyway.
762 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
763 PhysReg = PhysRegSlot;
765 } else if (PhysRegsUsed[PhysReg] == -2) {
766 // Unallocatable register dead, ignore.
769 assert((!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1) &&
770 "Silently clearing a virtual register?");
774 DOUT << " Last use of " << TRI->getName(PhysReg)
775 << "[%reg" << VirtReg <<"], removing it from live set\n";
776 removePhysReg(PhysReg);
777 for (const unsigned *AliasSet = TRI->getSubRegisters(PhysReg);
778 *AliasSet; ++AliasSet) {
779 if (PhysRegsUsed[*AliasSet] != -2) {
780 DOUT << " Last use of "
781 << TRI->getName(*AliasSet)
782 << "[%reg" << VirtReg <<"], removing it from live set\n";
783 removePhysReg(*AliasSet);
789 // Loop over all of the operands of the instruction, spilling registers that
790 // are defined, and marking explicit destinations in the PhysRegsUsed map.
791 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
792 MachineOperand& MO = MI->getOperand(i);
793 if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
794 TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
795 unsigned Reg = MO.getReg();
796 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
797 // These are extra physical register defs when a sub-register
798 // is defined (def of a sub-register is a read/mod/write of the
799 // larger registers). Ignore.
800 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
802 MF->getRegInfo().setPhysRegUsed(Reg);
803 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
804 PhysRegsUsed[Reg] = 0; // It is free and reserved now
805 AddToPhysRegsUseOrder(Reg);
807 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
808 *AliasSet; ++AliasSet) {
809 if (PhysRegsUsed[*AliasSet] != -2) {
810 MF->getRegInfo().setPhysRegUsed(*AliasSet);
811 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
812 AddToPhysRegsUseOrder(*AliasSet);
818 // Loop over the implicit defs, spilling them as well.
819 if (TID.ImplicitDefs) {
820 for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
821 *ImplicitDefs; ++ImplicitDefs) {
822 unsigned Reg = *ImplicitDefs;
823 if (PhysRegsUsed[Reg] != -2) {
824 spillPhysReg(MBB, MI, Reg, true);
825 AddToPhysRegsUseOrder(Reg);
826 PhysRegsUsed[Reg] = 0; // It is free and reserved now
828 MF->getRegInfo().setPhysRegUsed(Reg);
829 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
830 *AliasSet; ++AliasSet) {
831 if (PhysRegsUsed[*AliasSet] != -2) {
832 AddToPhysRegsUseOrder(*AliasSet);
833 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
834 MF->getRegInfo().setPhysRegUsed(*AliasSet);
840 SmallVector<unsigned, 8> DeadDefs;
841 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
842 MachineOperand& MO = MI->getOperand(i);
843 if (MO.isRegister() && MO.isDead())
844 DeadDefs.push_back(MO.getReg());
847 // Okay, we have allocated all of the source operands and spilled any values
848 // that would be destroyed by defs of this instruction. Loop over the
849 // explicit defs and assign them to a register, spilling incoming values if
850 // we need to scavenge a register.
852 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
853 MachineOperand& MO = MI->getOperand(i);
854 if (MO.isRegister() && MO.isDef() && MO.getReg() &&
855 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
856 unsigned DestVirtReg = MO.getReg();
857 unsigned DestPhysReg;
859 // If DestVirtReg already has a value, use it.
860 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
861 DestPhysReg = getReg(MBB, MI, DestVirtReg);
862 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
863 markVirtRegModified(DestVirtReg);
864 getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
865 DOUT << " Assigning " << TRI->getName(DestPhysReg)
866 << " to %reg" << DestVirtReg << "\n";
867 MO.setReg(DestPhysReg); // Assign the output register
871 // If this instruction defines any registers that are immediately dead,
874 for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
875 unsigned VirtReg = DeadDefs[i];
876 unsigned PhysReg = VirtReg;
877 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
878 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
879 PhysReg = PhysRegSlot;
880 assert(PhysReg != 0);
882 } else if (PhysRegsUsed[PhysReg] == -2) {
883 // Unallocatable register dead, ignore.
888 DOUT << " Register " << TRI->getName(PhysReg)
889 << " [%reg" << VirtReg
890 << "] is never used, removing it frame live list\n";
891 removePhysReg(PhysReg);
892 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
893 *AliasSet; ++AliasSet) {
894 if (PhysRegsUsed[*AliasSet] != -2) {
895 DOUT << " Register " << TRI->getName(*AliasSet)
896 << " [%reg" << *AliasSet
897 << "] is never used, removing it frame live list\n";
898 removePhysReg(*AliasSet);
904 // Finally, if this is a noop copy instruction, zap it.
905 unsigned SrcReg, DstReg;
906 if (TII->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)
910 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
912 // Spill all physical registers holding virtual registers now.
913 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
914 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
915 if (unsigned VirtReg = PhysRegsUsed[i])
916 spillVirtReg(MBB, MI, VirtReg, i);
922 // This checking code is very expensive.
924 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
925 e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
926 if (unsigned PR = Virt2PhysRegMap[i]) {
927 cerr << "Register still mapped: " << i << " -> " << PR << "\n";
930 assert(AllOk && "Virtual registers still in phys regs?");
933 // Clear any physical register which appear live at the end of the basic
934 // block, but which do not hold any virtual registers. e.g., the stack
936 PhysRegsUseOrder.clear();
939 /// runOnMachineFunction - Register allocate the whole function
941 bool RALocal::runOnMachineFunction(MachineFunction &Fn) {
942 DOUT << "Machine Function " << "\n";
944 TM = &Fn.getTarget();
945 TRI = TM->getRegisterInfo();
946 TII = TM->getInstrInfo();
948 PhysRegsUsed.assign(TRI->getNumRegs(), -1);
950 // At various places we want to efficiently check to see whether a register
951 // is allocatable. To handle this, we mark all unallocatable registers as
952 // being pinned down, permanently.
954 BitVector Allocable = TRI->getAllocatableSet(Fn);
955 for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
957 PhysRegsUsed[i] = -2; // Mark the reg unallocable.
960 // initialize the virtual->physical register map to have a 'null'
961 // mapping for all virtual registers
962 unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
963 StackSlotForVirtReg.grow(LastVirtReg);
964 Virt2PhysRegMap.grow(LastVirtReg);
965 Virt2LastUseMap.grow(LastVirtReg);
966 VirtRegModified.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister);
967 UsedInMultipleBlocks.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister);
969 // Loop over all of the basic blocks, eliminating virtual register references
970 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
972 AllocateBasicBlock(*MBB);
974 StackSlotForVirtReg.clear();
975 PhysRegsUsed.clear();
976 VirtRegModified.clear();
977 UsedInMultipleBlocks.clear();
978 Virt2PhysRegMap.clear();
979 Virt2LastUseMap.clear();
983 FunctionPass *llvm::createLocalRegisterAllocator() {
984 return new RALocal();