1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/LiveStackAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegAllocRegistry.h"
27 #include "llvm/CodeGen/RegisterCoalescer.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/ADT/EquivalenceClasses.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/Compiler.h"
46 STATISTIC(NumIters , "Number of iterations performed");
47 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
48 STATISTIC(NumCoalesce, "Number of copies coalesced");
49 STATISTIC(NumDowngrade, "Number of registers downgraded");
52 NewHeuristic("new-spilling-heuristic",
53 cl::desc("Use new spilling heuristic"),
54 cl::init(false), cl::Hidden);
57 PreSplitIntervals("pre-alloc-split",
58 cl::desc("Pre-register allocation live interval splitting"),
59 cl::init(false), cl::Hidden);
62 NewSpillFramework("new-spill-framework",
63 cl::desc("New spilling framework"),
64 cl::init(false), cl::Hidden);
66 static RegisterRegAlloc
67 linearscanRegAlloc("linearscan", "linear scan register allocator",
68 createLinearScanRegisterAllocator);
71 struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
73 RALinScan() : MachineFunctionPass(&ID) {}
75 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
76 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
78 /// RelatedRegClasses - This structure is built the first time a function is
79 /// compiled, and keeps track of which register classes have registers that
80 /// belong to multiple classes or have aliases that are in other classes.
81 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
82 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
84 // NextReloadMap - For each register in the map, it maps to the another
85 // register which is defined by a reload from the same stack slot and
86 // both reloads are in the same basic block.
87 DenseMap<unsigned, unsigned> NextReloadMap;
89 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
90 // un-favored for allocation.
91 SmallSet<unsigned, 8> DowngradedRegs;
93 // DowngradeMap - A map from virtual registers to physical registers being
94 // downgraded for the virtual registers.
95 DenseMap<unsigned, unsigned> DowngradeMap;
98 MachineRegisterInfo* mri_;
99 const TargetMachine* tm_;
100 const TargetRegisterInfo* tri_;
101 const TargetInstrInfo* tii_;
102 BitVector allocatableRegs_;
105 const MachineLoopInfo *loopInfo;
107 /// handled_ - Intervals are added to the handled_ set in the order of their
108 /// start value. This is uses for backtracking.
109 std::vector<LiveInterval*> handled_;
111 /// fixed_ - Intervals that correspond to machine registers.
115 /// active_ - Intervals that are currently being processed, and which have a
116 /// live range active for the current point.
117 IntervalPtrs active_;
119 /// inactive_ - Intervals that are currently being processed, but which have
120 /// a hold at the current point.
121 IntervalPtrs inactive_;
123 typedef std::priority_queue<LiveInterval*,
124 SmallVector<LiveInterval*, 64>,
125 greater_ptr<LiveInterval> > IntervalHeap;
126 IntervalHeap unhandled_;
128 /// regUse_ - Tracks register usage.
129 SmallVector<unsigned, 32> regUse_;
130 SmallVector<unsigned, 32> regUseBackUp_;
132 /// vrm_ - Tracks register assignments.
135 std::auto_ptr<VirtRegRewriter> rewriter_;
137 std::auto_ptr<Spiller> spiller_;
140 virtual const char* getPassName() const {
141 return "Linear Scan Register Allocator";
144 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
145 AU.addRequired<LiveIntervals>();
147 AU.addRequiredID(StrongPHIEliminationID);
148 // Make sure PassManager knows which analyses to make available
149 // to coalescing and which analyses coalescing invalidates.
150 AU.addRequiredTransitive<RegisterCoalescer>();
151 if (PreSplitIntervals)
152 AU.addRequiredID(PreAllocSplittingID);
153 AU.addRequired<LiveStacks>();
154 AU.addPreserved<LiveStacks>();
155 AU.addRequired<MachineLoopInfo>();
156 AU.addPreserved<MachineLoopInfo>();
157 AU.addRequired<VirtRegMap>();
158 AU.addPreserved<VirtRegMap>();
159 AU.addPreservedID(MachineDominatorsID);
160 MachineFunctionPass::getAnalysisUsage(AU);
163 /// runOnMachineFunction - register allocate the whole function
164 bool runOnMachineFunction(MachineFunction&);
167 /// linearScan - the linear scan algorithm
170 /// initIntervalSets - initialize the interval sets.
172 void initIntervalSets();
174 /// processActiveIntervals - expire old intervals and move non-overlapping
175 /// ones to the inactive list.
176 void processActiveIntervals(unsigned CurPoint);
178 /// processInactiveIntervals - expire old intervals and move overlapping
179 /// ones to the active list.
180 void processInactiveIntervals(unsigned CurPoint);
182 /// hasNextReloadInterval - Return the next liveinterval that's being
183 /// defined by a reload from the same SS as the specified one.
184 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
186 /// DowngradeRegister - Downgrade a register for allocation.
187 void DowngradeRegister(LiveInterval *li, unsigned Reg);
189 /// UpgradeRegister - Upgrade a register for allocation.
190 void UpgradeRegister(unsigned Reg);
192 /// assignRegOrStackSlotAtInterval - assign a register if one
193 /// is available, or spill.
194 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
196 void updateSpillWeights(std::vector<float> &Weights,
197 unsigned reg, float weight,
198 const TargetRegisterClass *RC);
200 /// findIntervalsToSpill - Determine the intervals to spill for the
201 /// specified interval. It's passed the physical registers whose spill
202 /// weight is the lowest among all the registers whose live intervals
203 /// conflict with the interval.
204 void findIntervalsToSpill(LiveInterval *cur,
205 std::vector<std::pair<unsigned,float> > &Candidates,
207 SmallVector<LiveInterval*, 8> &SpillIntervals);
209 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
210 /// try allocate the definition the same register as the source register
211 /// if the register is not defined during live time of the interval. This
212 /// eliminate a copy. This is used to coalesce copies which were not
213 /// coalesced away before allocation either due to dest and src being in
214 /// different register classes or because the coalescer was overly
216 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
219 /// Register usage / availability tracking helpers.
223 regUse_.resize(tri_->getNumRegs(), 0);
224 regUseBackUp_.resize(tri_->getNumRegs(), 0);
227 void finalizeRegUses() {
229 // Verify all the registers are "freed".
231 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
232 if (regUse_[i] != 0) {
233 cerr << tri_->getName(i) << " is still in use!\n";
241 regUseBackUp_.clear();
244 void addRegUse(unsigned physReg) {
245 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
246 "should be physical register!");
248 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
252 void delRegUse(unsigned physReg) {
253 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
254 "should be physical register!");
255 assert(regUse_[physReg] != 0);
257 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
258 assert(regUse_[*as] != 0);
263 bool isRegAvail(unsigned physReg) const {
264 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
265 "should be physical register!");
266 return regUse_[physReg] == 0;
269 void backUpRegUses() {
270 regUseBackUp_ = regUse_;
273 void restoreRegUses() {
274 regUse_ = regUseBackUp_;
278 /// Register handling helpers.
281 /// getFreePhysReg - return a free physical register for this virtual
282 /// register interval if we have one, otherwise return 0.
283 unsigned getFreePhysReg(LiveInterval* cur);
284 unsigned getFreePhysReg(const TargetRegisterClass *RC,
285 unsigned MaxInactiveCount,
286 SmallVector<unsigned, 256> &inactiveCounts,
289 /// assignVirt2StackSlot - assigns this virtual register to a
290 /// stack slot. returns the stack slot
291 int assignVirt2StackSlot(unsigned virtReg);
293 void ComputeRelatedRegClasses();
295 template <typename ItTy>
296 void printIntervals(const char* const str, ItTy i, ItTy e) const {
297 if (str) DOUT << str << " intervals:\n";
298 for (; i != e; ++i) {
299 DOUT << "\t" << *i->first << " -> ";
300 unsigned reg = i->first->reg;
301 if (TargetRegisterInfo::isVirtualRegister(reg)) {
302 reg = vrm_->getPhys(reg);
304 DOUT << tri_->getName(reg) << '\n';
308 char RALinScan::ID = 0;
311 static RegisterPass<RALinScan>
312 X("linearscan-regalloc", "Linear Scan Register Allocator");
314 void RALinScan::ComputeRelatedRegClasses() {
315 // First pass, add all reg classes to the union, and determine at least one
316 // reg class that each register is in.
317 bool HasAliases = false;
318 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
319 E = tri_->regclass_end(); RCI != E; ++RCI) {
320 RelatedRegClasses.insert(*RCI);
321 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
323 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
325 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
327 // Already processed this register. Just make sure we know that
328 // multiple register classes share a register.
329 RelatedRegClasses.unionSets(PRC, *RCI);
336 // Second pass, now that we know conservatively what register classes each reg
337 // belongs to, add info about aliases. We don't need to do this for targets
338 // without register aliases.
340 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
341 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
343 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
344 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
347 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
348 /// try allocate the definition the same register as the source register
349 /// if the register is not defined during live time of the interval. This
350 /// eliminate a copy. This is used to coalesce copies which were not
351 /// coalesced away before allocation either due to dest and src being in
352 /// different register classes or because the coalescer was overly
354 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
355 unsigned Preference = vrm_->getRegAllocPref(cur.reg);
356 if ((Preference && Preference == Reg) || !cur.containsOneValue())
359 VNInfo *vni = cur.begin()->valno;
360 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
362 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
363 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg, PhysReg;
365 !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
368 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
369 if (!vrm_->isAssignedReg(SrcReg))
371 PhysReg = vrm_->getPhys(SrcReg);
376 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
377 if (!RC->contains(PhysReg))
381 if (!li_->conflictsWithPhysRegDef(cur, *vrm_, PhysReg)) {
382 DOUT << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg)
384 vrm_->clearVirt(cur.reg);
385 vrm_->assignVirt2Phys(cur.reg, PhysReg);
387 // Remove unnecessary kills since a copy does not clobber the register.
388 if (li_->hasInterval(SrcReg)) {
389 LiveInterval &SrcLI = li_->getInterval(SrcReg);
390 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(cur.reg),
391 E = mri_->reg_end(); I != E; ++I) {
392 MachineOperand &O = I.getOperand();
393 if (!O.isUse() || !O.isKill())
395 MachineInstr *MI = &*I;
396 if (SrcLI.liveAt(li_->getDefIndex(li_->getInstructionIndex(MI))))
408 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
410 mri_ = &fn.getRegInfo();
411 tm_ = &fn.getTarget();
412 tri_ = tm_->getRegisterInfo();
413 tii_ = tm_->getInstrInfo();
414 allocatableRegs_ = tri_->getAllocatableSet(fn);
415 li_ = &getAnalysis<LiveIntervals>();
416 ls_ = &getAnalysis<LiveStacks>();
417 loopInfo = &getAnalysis<MachineLoopInfo>();
419 // We don't run the coalescer here because we have no reason to
420 // interact with it. If the coalescer requires interaction, it
421 // won't do anything. If it doesn't require interaction, we assume
422 // it was run as a separate pass.
424 // If this is the first function compiled, compute the related reg classes.
425 if (RelatedRegClasses.empty())
426 ComputeRelatedRegClasses();
428 // Also resize register usage trackers.
431 vrm_ = &getAnalysis<VirtRegMap>();
432 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
434 if (NewSpillFramework) {
435 spiller_.reset(createSpiller(mf_, li_, ls_, vrm_));
442 // Rewrite spill code and update the PhysRegsUsed set.
443 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
445 assert(unhandled_.empty() && "Unhandled live intervals remain!");
453 NextReloadMap.clear();
454 DowngradedRegs.clear();
455 DowngradeMap.clear();
461 /// initIntervalSets - initialize the interval sets.
463 void RALinScan::initIntervalSets()
465 assert(unhandled_.empty() && fixed_.empty() &&
466 active_.empty() && inactive_.empty() &&
467 "interval sets should be empty on initialization");
469 handled_.reserve(li_->getNumIntervals());
471 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
472 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
473 mri_->setPhysRegUsed(i->second->reg);
474 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
476 unhandled_.push(i->second);
480 void RALinScan::linearScan()
482 // linear scan algorithm
483 DOUT << "********** LINEAR SCAN **********\n";
484 DOUT << "********** Function: " << mf_->getFunction()->getName() << '\n';
486 DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end()));
488 while (!unhandled_.empty()) {
489 // pick the interval with the earliest start point
490 LiveInterval* cur = unhandled_.top();
493 DOUT << "\n*** CURRENT ***: " << *cur << '\n';
496 processActiveIntervals(cur->beginNumber());
497 processInactiveIntervals(cur->beginNumber());
499 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
500 "Can only allocate virtual registers!");
503 // Allocating a virtual register. try to find a free
504 // physical register or spill an interval (possibly this one) in order to
506 assignRegOrStackSlotAtInterval(cur);
508 DEBUG(printIntervals("active", active_.begin(), active_.end()));
509 DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
512 // Expire any remaining active intervals
513 while (!active_.empty()) {
514 IntervalPtr &IP = active_.back();
515 unsigned reg = IP.first->reg;
516 DOUT << "\tinterval " << *IP.first << " expired\n";
517 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
518 "Can only allocate virtual registers!");
519 reg = vrm_->getPhys(reg);
524 // Expire any remaining inactive intervals
525 DEBUG(for (IntervalPtrs::reverse_iterator
526 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
527 DOUT << "\tinterval " << *i->first << " expired\n");
530 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
531 MachineFunction::iterator EntryMBB = mf_->begin();
532 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
533 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
534 LiveInterval &cur = *i->second;
536 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
539 else if (vrm_->isAssignedReg(cur.reg))
540 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
543 // Ignore splited live intervals.
544 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
547 // A register defined by an implicit_def can be liveout the def BB and livein
548 // to a use BB. Add it to the livein set of the use BB's.
549 if (!isPhys && cur.empty()) {
550 if (MachineInstr *DefMI = mri_->getVRegDef(cur.reg)) {
551 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
552 MachineBasicBlock *DefMBB = DefMI->getParent();
553 SmallPtrSet<MachineBasicBlock*, 4> Seen;
555 for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(cur.reg),
556 re = mri_->reg_end(); ri != re; ++ri) {
557 MachineInstr *UseMI = &*ri;
558 MachineBasicBlock *UseMBB = UseMI->getParent();
559 if (Seen.insert(UseMBB)) {
560 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
561 "Adding a virtual register to livein set?");
562 UseMBB->addLiveIn(Reg);
567 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
569 const LiveRange &LR = *I;
570 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
571 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
572 if (LiveInMBBs[i] != EntryMBB) {
573 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
574 "Adding a virtual register to livein set?");
575 LiveInMBBs[i]->addLiveIn(Reg);
584 // Look for physical registers that end up not being allocated even though
585 // register allocator had to spill other registers in its register class.
586 if (ls_->getNumIntervals() == 0)
588 if (!vrm_->FindUnusedRegisters(li_))
592 /// processActiveIntervals - expire old intervals and move non-overlapping ones
593 /// to the inactive list.
594 void RALinScan::processActiveIntervals(unsigned CurPoint)
596 DOUT << "\tprocessing active intervals:\n";
598 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
599 LiveInterval *Interval = active_[i].first;
600 LiveInterval::iterator IntervalPos = active_[i].second;
601 unsigned reg = Interval->reg;
603 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
605 if (IntervalPos == Interval->end()) { // Remove expired intervals.
606 DOUT << "\t\tinterval " << *Interval << " expired\n";
607 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
608 "Can only allocate virtual registers!");
609 reg = vrm_->getPhys(reg);
612 // Pop off the end of the list.
613 active_[i] = active_.back();
617 } else if (IntervalPos->start > CurPoint) {
618 // Move inactive intervals to inactive list.
619 DOUT << "\t\tinterval " << *Interval << " inactive\n";
620 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
621 "Can only allocate virtual registers!");
622 reg = vrm_->getPhys(reg);
625 inactive_.push_back(std::make_pair(Interval, IntervalPos));
627 // Pop off the end of the list.
628 active_[i] = active_.back();
632 // Otherwise, just update the iterator position.
633 active_[i].second = IntervalPos;
638 /// processInactiveIntervals - expire old intervals and move overlapping
639 /// ones to the active list.
640 void RALinScan::processInactiveIntervals(unsigned CurPoint)
642 DOUT << "\tprocessing inactive intervals:\n";
644 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
645 LiveInterval *Interval = inactive_[i].first;
646 LiveInterval::iterator IntervalPos = inactive_[i].second;
647 unsigned reg = Interval->reg;
649 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
651 if (IntervalPos == Interval->end()) { // remove expired intervals.
652 DOUT << "\t\tinterval " << *Interval << " expired\n";
654 // Pop off the end of the list.
655 inactive_[i] = inactive_.back();
656 inactive_.pop_back();
658 } else if (IntervalPos->start <= CurPoint) {
659 // move re-activated intervals in active list
660 DOUT << "\t\tinterval " << *Interval << " active\n";
661 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
662 "Can only allocate virtual registers!");
663 reg = vrm_->getPhys(reg);
666 active_.push_back(std::make_pair(Interval, IntervalPos));
668 // Pop off the end of the list.
669 inactive_[i] = inactive_.back();
670 inactive_.pop_back();
673 // Otherwise, just update the iterator position.
674 inactive_[i].second = IntervalPos;
679 /// updateSpillWeights - updates the spill weights of the specifed physical
680 /// register and its weight.
681 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
682 unsigned reg, float weight,
683 const TargetRegisterClass *RC) {
684 SmallSet<unsigned, 4> Processed;
685 SmallSet<unsigned, 4> SuperAdded;
686 SmallVector<unsigned, 4> Supers;
687 Weights[reg] += weight;
688 Processed.insert(reg);
689 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
690 Weights[*as] += weight;
691 Processed.insert(*as);
692 if (tri_->isSubRegister(*as, reg) &&
693 SuperAdded.insert(*as) &&
695 Supers.push_back(*as);
699 // If the alias is a super-register, and the super-register is in the
700 // register class we are trying to allocate. Then add the weight to all
701 // sub-registers of the super-register even if they are not aliases.
702 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
703 // bl should get the same spill weight otherwise it will be choosen
704 // as a spill candidate since spilling bh doesn't make ebx available.
705 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
706 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
707 if (!Processed.count(*sr))
708 Weights[*sr] += weight;
713 RALinScan::IntervalPtrs::iterator
714 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
715 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
717 if (I->first == LI) return I;
721 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
722 for (unsigned i = 0, e = V.size(); i != e; ++i) {
723 RALinScan::IntervalPtr &IP = V[i];
724 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
726 if (I != IP.first->begin()) --I;
731 /// addStackInterval - Create a LiveInterval for stack if the specified live
732 /// interval has been spilled.
733 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
735 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
736 int SS = vrm_.getStackSlot(cur->reg);
737 if (SS == VirtRegMap::NO_STACK_SLOT)
740 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
741 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
744 if (SI.hasAtLeastOneValue())
745 VNI = SI.getValNumInfo(0);
747 VNI = SI.getNextValue(~0U, 0, ls_->getVNInfoAllocator());
749 LiveInterval &RI = li_->getInterval(cur->reg);
750 // FIXME: This may be overly conservative.
751 SI.MergeRangesInAsValue(RI, VNI);
754 /// getConflictWeight - Return the number of conflicts between cur
755 /// live interval and defs and uses of Reg weighted by loop depthes.
757 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
758 MachineRegisterInfo *mri_,
759 const MachineLoopInfo *loopInfo) {
761 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
762 E = mri_->reg_end(); I != E; ++I) {
763 MachineInstr *MI = &*I;
764 if (cur->liveAt(li_->getInstructionIndex(MI))) {
765 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
766 Conflicts += powf(10.0f, (float)loopDepth);
772 /// findIntervalsToSpill - Determine the intervals to spill for the
773 /// specified interval. It's passed the physical registers whose spill
774 /// weight is the lowest among all the registers whose live intervals
775 /// conflict with the interval.
776 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
777 std::vector<std::pair<unsigned,float> > &Candidates,
779 SmallVector<LiveInterval*, 8> &SpillIntervals) {
780 // We have figured out the *best* register to spill. But there are other
781 // registers that are pretty good as well (spill weight within 3%). Spill
782 // the one that has fewest defs and uses that conflict with cur.
783 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
784 SmallVector<LiveInterval*, 8> SLIs[3];
786 DOUT << "\tConsidering " << NumCands << " candidates: ";
787 DEBUG(for (unsigned i = 0; i != NumCands; ++i)
788 DOUT << tri_->getName(Candidates[i].first) << " ";
791 // Calculate the number of conflicts of each candidate.
792 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
793 unsigned Reg = i->first->reg;
794 unsigned PhysReg = vrm_->getPhys(Reg);
795 if (!cur->overlapsFrom(*i->first, i->second))
797 for (unsigned j = 0; j < NumCands; ++j) {
798 unsigned Candidate = Candidates[j].first;
799 if (tri_->regsOverlap(PhysReg, Candidate)) {
801 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
802 SLIs[j].push_back(i->first);
807 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
808 unsigned Reg = i->first->reg;
809 unsigned PhysReg = vrm_->getPhys(Reg);
810 if (!cur->overlapsFrom(*i->first, i->second-1))
812 for (unsigned j = 0; j < NumCands; ++j) {
813 unsigned Candidate = Candidates[j].first;
814 if (tri_->regsOverlap(PhysReg, Candidate)) {
816 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
817 SLIs[j].push_back(i->first);
822 // Which is the best candidate?
823 unsigned BestCandidate = 0;
824 float MinConflicts = Conflicts[0];
825 for (unsigned i = 1; i != NumCands; ++i) {
826 if (Conflicts[i] < MinConflicts) {
828 MinConflicts = Conflicts[i];
832 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
833 std::back_inserter(SpillIntervals));
837 struct WeightCompare {
838 typedef std::pair<unsigned, float> RegWeightPair;
839 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
840 return LHS.second < RHS.second;
845 static bool weightsAreClose(float w1, float w2) {
849 float diff = w1 - w2;
850 if (diff <= 0.02f) // Within 0.02f
852 return (diff / w2) <= 0.05f; // Within 5%.
855 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
856 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
857 if (I == NextReloadMap.end())
859 return &li_->getInterval(I->second);
862 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
863 bool isNew = DowngradedRegs.insert(Reg);
864 isNew = isNew; // Silence compiler warning.
865 assert(isNew && "Multiple reloads holding the same register?");
866 DowngradeMap.insert(std::make_pair(li->reg, Reg));
867 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
868 isNew = DowngradedRegs.insert(*AS);
869 isNew = isNew; // Silence compiler warning.
870 assert(isNew && "Multiple reloads holding the same register?");
871 DowngradeMap.insert(std::make_pair(li->reg, *AS));
876 void RALinScan::UpgradeRegister(unsigned Reg) {
878 DowngradedRegs.erase(Reg);
879 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
880 DowngradedRegs.erase(*AS);
886 bool operator()(LiveInterval* A, LiveInterval* B) {
887 return A->beginNumber() < B->beginNumber();
892 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
894 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
896 DOUT << "\tallocating current interval: ";
898 // This is an implicitly defined live interval, just assign any register.
899 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
901 unsigned physReg = vrm_->getRegAllocPref(cur->reg);
903 physReg = *RC->allocation_order_begin(*mf_);
904 DOUT << tri_->getName(physReg) << '\n';
905 // Note the register is not really in use.
906 vrm_->assignVirt2Phys(cur->reg, physReg);
912 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
913 unsigned StartPosition = cur->beginNumber();
914 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
916 // If start of this live interval is defined by a move instruction and its
917 // source is assigned a physical register that is compatible with the target
918 // register class, then we should try to assign it the same register.
919 // This can happen when the move is from a larger register class to a smaller
920 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
921 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
922 VNInfo *vni = cur->begin()->valno;
923 if (vni->def && vni->def != ~1U && vni->def != ~0U) {
924 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
925 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
927 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
929 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
931 else if (vrm_->isAssignedReg(SrcReg))
932 Reg = vrm_->getPhys(SrcReg);
935 Reg = tri_->getSubReg(Reg, SrcSubReg);
937 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
938 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
939 mri_->setRegAllocationHint(cur->reg,
940 MachineRegisterInfo::RA_Preference, Reg);
946 // For every interval in inactive we overlap with, mark the
947 // register as not free and update spill weights.
948 for (IntervalPtrs::const_iterator i = inactive_.begin(),
949 e = inactive_.end(); i != e; ++i) {
950 unsigned Reg = i->first->reg;
951 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
952 "Can only allocate virtual registers!");
953 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
954 // If this is not in a related reg class to the register we're allocating,
956 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
957 cur->overlapsFrom(*i->first, i->second-1)) {
958 Reg = vrm_->getPhys(Reg);
960 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
964 // Speculatively check to see if we can get a register right now. If not,
965 // we know we won't be able to by adding more constraints. If so, we can
966 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
967 // is very bad (it contains all callee clobbered registers for any functions
968 // with a call), so we want to avoid doing that if possible.
969 unsigned physReg = getFreePhysReg(cur);
970 unsigned BestPhysReg = physReg;
972 // We got a register. However, if it's in the fixed_ list, we might
973 // conflict with it. Check to see if we conflict with it or any of its
975 SmallSet<unsigned, 8> RegAliases;
976 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
977 RegAliases.insert(*AS);
979 bool ConflictsWithFixed = false;
980 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
981 IntervalPtr &IP = fixed_[i];
982 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
983 // Okay, this reg is on the fixed list. Check to see if we actually
985 LiveInterval *I = IP.first;
986 if (I->endNumber() > StartPosition) {
987 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
989 if (II != I->begin() && II->start > StartPosition)
991 if (cur->overlapsFrom(*I, II)) {
992 ConflictsWithFixed = true;
999 // Okay, the register picked by our speculative getFreePhysReg call turned
1000 // out to be in use. Actually add all of the conflicting fixed registers to
1001 // regUse_ so we can do an accurate query.
1002 if (ConflictsWithFixed) {
1003 // For every interval in fixed we overlap with, mark the register as not
1004 // free and update spill weights.
1005 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1006 IntervalPtr &IP = fixed_[i];
1007 LiveInterval *I = IP.first;
1009 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
1010 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1011 I->endNumber() > StartPosition) {
1012 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1014 if (II != I->begin() && II->start > StartPosition)
1016 if (cur->overlapsFrom(*I, II)) {
1017 unsigned reg = I->reg;
1019 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1024 // Using the newly updated regUse_ object, which includes conflicts in the
1025 // future, see if there are any registers available.
1026 physReg = getFreePhysReg(cur);
1030 // Restore the physical register tracker, removing information about the
1034 // If we find a free register, we are done: assign this virtual to
1035 // the free physical register and add this interval to the active
1038 DOUT << tri_->getName(physReg) << '\n';
1039 vrm_->assignVirt2Phys(cur->reg, physReg);
1041 active_.push_back(std::make_pair(cur, cur->begin()));
1042 handled_.push_back(cur);
1044 // "Upgrade" the physical register since it has been allocated.
1045 UpgradeRegister(physReg);
1046 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1047 // "Downgrade" physReg to try to keep physReg from being allocated until
1048 // the next reload from the same SS is allocated.
1049 mri_->setRegAllocationHint(NextReloadLI->reg,
1050 MachineRegisterInfo::RA_Preference, physReg);
1051 DowngradeRegister(cur, physReg);
1055 DOUT << "no free registers\n";
1057 // Compile the spill weights into an array that is better for scanning.
1058 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1059 for (std::vector<std::pair<unsigned, float> >::iterator
1060 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1061 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1063 // for each interval in active, update spill weights.
1064 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1066 unsigned reg = i->first->reg;
1067 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1068 "Can only allocate virtual registers!");
1069 reg = vrm_->getPhys(reg);
1070 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1073 DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
1075 // Find a register to spill.
1076 float minWeight = HUGE_VALF;
1077 unsigned minReg = 0;
1080 std::vector<std::pair<unsigned,float> > RegsWeights;
1081 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1082 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1083 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1085 float regWeight = SpillWeights[reg];
1086 if (minWeight > regWeight)
1088 RegsWeights.push_back(std::make_pair(reg, regWeight));
1091 // If we didn't find a register that is spillable, try aliases?
1093 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1094 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1096 // No need to worry about if the alias register size < regsize of RC.
1097 // We are going to spill all registers that alias it anyway.
1098 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1099 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1103 // Sort all potential spill candidates by weight.
1104 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare());
1105 minReg = RegsWeights[0].first;
1106 minWeight = RegsWeights[0].second;
1107 if (minWeight == HUGE_VALF) {
1108 // All registers must have inf weight. Just grab one!
1109 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
1110 if (cur->weight == HUGE_VALF ||
1111 li_->getApproximateInstructionCount(*cur) == 0) {
1112 // Spill a physical register around defs and uses.
1113 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1114 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1115 // in fixed_. Reset them.
1116 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1117 IntervalPtr &IP = fixed_[i];
1118 LiveInterval *I = IP.first;
1119 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1120 IP.second = I->advanceTo(I->begin(), StartPosition);
1123 DowngradedRegs.clear();
1124 assignRegOrStackSlotAtInterval(cur);
1126 cerr << "Ran out of registers during register allocation!\n";
1133 // Find up to 3 registers to consider as spill candidates.
1134 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1135 while (LastCandidate > 1) {
1136 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1141 DOUT << "\t\tregister(s) with min weight(s): ";
1142 DEBUG(for (unsigned i = 0; i != LastCandidate; ++i)
1143 DOUT << tri_->getName(RegsWeights[i].first)
1144 << " (" << RegsWeights[i].second << ")\n");
1146 // If the current has the minimum weight, we need to spill it and
1147 // add any added intervals back to unhandled, and restart
1149 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1150 DOUT << "\t\t\tspilling(c): " << *cur << '\n';
1151 SmallVector<LiveInterval*, 8> spillIs;
1152 std::vector<LiveInterval*> added;
1154 if (!NewSpillFramework) {
1155 added = li_->addIntervalsForSpills(*cur, spillIs, loopInfo, *vrm_);
1157 added = spiller_->spill(cur);
1160 std::sort(added.begin(), added.end(), LISorter());
1161 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1163 return; // Early exit if all spills were folded.
1165 // Merge added with unhandled. Note that we have already sorted
1166 // intervals returned by addIntervalsForSpills by their starting
1168 // This also update the NextReloadMap. That is, it adds mapping from a
1169 // register defined by a reload from SS to the next reload from SS in the
1170 // same basic block.
1171 MachineBasicBlock *LastReloadMBB = 0;
1172 LiveInterval *LastReload = 0;
1173 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1174 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1175 LiveInterval *ReloadLi = added[i];
1176 if (ReloadLi->weight == HUGE_VALF &&
1177 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1178 unsigned ReloadIdx = ReloadLi->beginNumber();
1179 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1180 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1181 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1182 // Last reload of same SS is in the same MBB. We want to try to
1183 // allocate both reloads the same register and make sure the reg
1184 // isn't clobbered in between if at all possible.
1185 assert(LastReload->beginNumber() < ReloadIdx);
1186 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1188 LastReloadMBB = ReloadMBB;
1189 LastReload = ReloadLi;
1190 LastReloadSS = ReloadSS;
1192 unhandled_.push(ReloadLi);
1199 // Push the current interval back to unhandled since we are going
1200 // to re-run at least this iteration. Since we didn't modify it it
1201 // should go back right in the front of the list
1202 unhandled_.push(cur);
1204 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1205 "did not choose a register to spill?");
1207 // We spill all intervals aliasing the register with
1208 // minimum weight, rollback to the interval with the earliest
1209 // start point and let the linear scan algorithm run again
1210 SmallVector<LiveInterval*, 8> spillIs;
1212 // Determine which intervals have to be spilled.
1213 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1215 // Set of spilled vregs (used later to rollback properly)
1216 SmallSet<unsigned, 8> spilled;
1218 // The earliest start of a Spilled interval indicates up to where
1219 // in handled we need to roll back
1221 LiveInterval *earliestStartInterval = cur;
1223 // Spill live intervals of virtual regs mapped to the physical register we
1224 // want to clear (and its aliases). We only spill those that overlap with the
1225 // current interval as the rest do not affect its allocation. we also keep
1226 // track of the earliest start of all spilled live intervals since this will
1227 // mark our rollback point.
1228 std::vector<LiveInterval*> added;
1229 while (!spillIs.empty()) {
1230 bool epicFail = false;
1231 LiveInterval *sli = spillIs.back();
1233 DOUT << "\t\t\tspilling(a): " << *sli << '\n';
1234 earliestStartInterval =
1235 (earliestStartInterval->beginNumber() < sli->beginNumber()) ?
1236 earliestStartInterval : sli;
1238 std::vector<LiveInterval*> newIs;
1239 if (!NewSpillFramework) {
1240 newIs = li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_);
1242 newIs = spiller_->spill(sli);
1244 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1245 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
1246 spilled.insert(sli->reg);
1253 unsigned earliestStart = earliestStartInterval->beginNumber();
1255 DOUT << "\t\trolling back to: " << earliestStart << '\n';
1257 // Scan handled in reverse order up to the earliest start of a
1258 // spilled live interval and undo each one, restoring the state of
1260 while (!handled_.empty()) {
1261 LiveInterval* i = handled_.back();
1262 // If this interval starts before t we are done.
1263 if (i->beginNumber() < earliestStart)
1265 DOUT << "\t\t\tundo changes for: " << *i << '\n';
1266 handled_.pop_back();
1268 // When undoing a live interval allocation we must know if it is active or
1269 // inactive to properly update regUse_ and the VirtRegMap.
1270 IntervalPtrs::iterator it;
1271 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1273 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1274 if (!spilled.count(i->reg))
1276 delRegUse(vrm_->getPhys(i->reg));
1277 vrm_->clearVirt(i->reg);
1278 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1279 inactive_.erase(it);
1280 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1281 if (!spilled.count(i->reg))
1283 vrm_->clearVirt(i->reg);
1285 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1286 "Can only allocate virtual registers!");
1287 vrm_->clearVirt(i->reg);
1291 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1292 if (ii == DowngradeMap.end())
1293 // It interval has a preference, it must be defined by a copy. Clear the
1294 // preference now since the source interval allocation may have been
1296 mri_->setRegAllocationHint(i->reg, MachineRegisterInfo::RA_None, 0);
1298 UpgradeRegister(ii->second);
1302 // Rewind the iterators in the active, inactive, and fixed lists back to the
1303 // point we reverted to.
1304 RevertVectorIteratorsTo(active_, earliestStart);
1305 RevertVectorIteratorsTo(inactive_, earliestStart);
1306 RevertVectorIteratorsTo(fixed_, earliestStart);
1308 // Scan the rest and undo each interval that expired after t and
1309 // insert it in active (the next iteration of the algorithm will
1310 // put it in inactive if required)
1311 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1312 LiveInterval *HI = handled_[i];
1313 if (!HI->expiredAt(earliestStart) &&
1314 HI->expiredAt(cur->beginNumber())) {
1315 DOUT << "\t\t\tundo changes for: " << *HI << '\n';
1316 active_.push_back(std::make_pair(HI, HI->begin()));
1317 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1318 addRegUse(vrm_->getPhys(HI->reg));
1322 // Merge added with unhandled.
1323 // This also update the NextReloadMap. That is, it adds mapping from a
1324 // register defined by a reload from SS to the next reload from SS in the
1325 // same basic block.
1326 MachineBasicBlock *LastReloadMBB = 0;
1327 LiveInterval *LastReload = 0;
1328 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1329 std::sort(added.begin(), added.end(), LISorter());
1330 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1331 LiveInterval *ReloadLi = added[i];
1332 if (ReloadLi->weight == HUGE_VALF &&
1333 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1334 unsigned ReloadIdx = ReloadLi->beginNumber();
1335 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1336 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1337 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1338 // Last reload of same SS is in the same MBB. We want to try to
1339 // allocate both reloads the same register and make sure the reg
1340 // isn't clobbered in between if at all possible.
1341 assert(LastReload->beginNumber() < ReloadIdx);
1342 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1344 LastReloadMBB = ReloadMBB;
1345 LastReload = ReloadLi;
1346 LastReloadSS = ReloadSS;
1348 unhandled_.push(ReloadLi);
1352 unsigned RALinScan::getFreePhysReg(const TargetRegisterClass *RC,
1353 unsigned MaxInactiveCount,
1354 SmallVector<unsigned, 256> &inactiveCounts,
1356 unsigned FreeReg = 0;
1357 unsigned FreeRegInactiveCount = 0;
1359 TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
1360 TargetRegisterClass::iterator E = RC->allocation_order_end(*mf_);
1361 assert(I != E && "No allocatable register in this register class!");
1363 // Scan for the first available register.
1364 for (; I != E; ++I) {
1366 // Ignore "downgraded" registers.
1367 if (SkipDGRegs && DowngradedRegs.count(Reg))
1369 if (isRegAvail(Reg)) {
1371 if (FreeReg < inactiveCounts.size())
1372 FreeRegInactiveCount = inactiveCounts[FreeReg];
1374 FreeRegInactiveCount = 0;
1379 // If there are no free regs, or if this reg has the max inactive count,
1380 // return this register.
1381 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount)
1384 // Continue scanning the registers, looking for the one with the highest
1385 // inactive count. Alkis found that this reduced register pressure very
1386 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1388 for (; I != E; ++I) {
1390 // Ignore "downgraded" registers.
1391 if (SkipDGRegs && DowngradedRegs.count(Reg))
1393 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1394 FreeRegInactiveCount < inactiveCounts[Reg]) {
1396 FreeRegInactiveCount = inactiveCounts[Reg];
1397 if (FreeRegInactiveCount == MaxInactiveCount)
1398 break; // We found the one with the max inactive count.
1405 /// getFreePhysReg - return a free physical register for this virtual register
1406 /// interval if we have one, otherwise return 0.
1407 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1408 SmallVector<unsigned, 256> inactiveCounts;
1409 unsigned MaxInactiveCount = 0;
1411 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1412 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1414 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1416 unsigned reg = i->first->reg;
1417 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1418 "Can only allocate virtual registers!");
1420 // If this is not in a related reg class to the register we're allocating,
1422 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1423 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1424 reg = vrm_->getPhys(reg);
1425 if (inactiveCounts.size() <= reg)
1426 inactiveCounts.resize(reg+1);
1427 ++inactiveCounts[reg];
1428 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1432 // If copy coalescer has assigned a "preferred" register, check if it's
1434 unsigned Preference = vrm_->getRegAllocPref(cur->reg);
1436 DOUT << "(preferred: " << tri_->getName(Preference) << ") ";
1437 if (isRegAvail(Preference) &&
1438 RC->contains(Preference))
1442 if (!DowngradedRegs.empty()) {
1443 unsigned FreeReg = getFreePhysReg(RC, MaxInactiveCount, inactiveCounts,
1448 return getFreePhysReg(RC, MaxInactiveCount, inactiveCounts, false);
1451 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1452 return new RALinScan();