1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/LiveStackAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegAllocRegistry.h"
27 #include "llvm/CodeGen/RegisterCoalescer.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/ADT/EquivalenceClasses.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
47 STATISTIC(NumIters , "Number of iterations performed");
48 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
49 STATISTIC(NumCoalesce, "Number of copies coalesced");
50 STATISTIC(NumDowngrade, "Number of registers downgraded");
53 NewHeuristic("new-spilling-heuristic",
54 cl::desc("Use new spilling heuristic"),
55 cl::init(false), cl::Hidden);
58 PreSplitIntervals("pre-alloc-split",
59 cl::desc("Pre-register allocation live interval splitting"),
60 cl::init(false), cl::Hidden);
62 static RegisterRegAlloc
63 linearscanRegAlloc("linearscan", "linear scan register allocator",
64 createLinearScanRegisterAllocator);
67 // When we allocate a register, add it to a fixed-size queue of
68 // registers to skip in subsequent allocations. This trades a small
69 // amount of register pressure and increased spills for flexibility in
70 // the post-pass scheduler.
72 // Note that in a the number of registers used for reloading spills
73 // will be one greater than the value of this option.
75 // One big limitation of this is that it doesn't differentiate between
76 // different register classes. So on x86-64, if there is xmm register
77 // pressure, it can caused fewer GPRs to be held in the queue.
78 static cl::opt<unsigned>
79 NumRecentlyUsedRegs("linearscan-skip-count",
80 cl::desc("Number of registers for linearscan to remember to skip."),
84 struct RALinScan : public MachineFunctionPass {
86 RALinScan() : MachineFunctionPass(&ID) {
87 // Initialize the queue to record recently-used registers.
88 if (NumRecentlyUsedRegs > 0)
89 RecentRegs.resize(NumRecentlyUsedRegs, 0);
90 RecentNext = RecentRegs.begin();
93 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
94 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
96 /// RelatedRegClasses - This structure is built the first time a function is
97 /// compiled, and keeps track of which register classes have registers that
98 /// belong to multiple classes or have aliases that are in other classes.
99 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
100 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
102 // NextReloadMap - For each register in the map, it maps to the another
103 // register which is defined by a reload from the same stack slot and
104 // both reloads are in the same basic block.
105 DenseMap<unsigned, unsigned> NextReloadMap;
107 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
108 // un-favored for allocation.
109 SmallSet<unsigned, 8> DowngradedRegs;
111 // DowngradeMap - A map from virtual registers to physical registers being
112 // downgraded for the virtual registers.
113 DenseMap<unsigned, unsigned> DowngradeMap;
115 MachineFunction* mf_;
116 MachineRegisterInfo* mri_;
117 const TargetMachine* tm_;
118 const TargetRegisterInfo* tri_;
119 const TargetInstrInfo* tii_;
120 BitVector allocatableRegs_;
123 const MachineLoopInfo *loopInfo;
125 /// handled_ - Intervals are added to the handled_ set in the order of their
126 /// start value. This is uses for backtracking.
127 std::vector<LiveInterval*> handled_;
129 /// fixed_ - Intervals that correspond to machine registers.
133 /// active_ - Intervals that are currently being processed, and which have a
134 /// live range active for the current point.
135 IntervalPtrs active_;
137 /// inactive_ - Intervals that are currently being processed, but which have
138 /// a hold at the current point.
139 IntervalPtrs inactive_;
141 typedef std::priority_queue<LiveInterval*,
142 SmallVector<LiveInterval*, 64>,
143 greater_ptr<LiveInterval> > IntervalHeap;
144 IntervalHeap unhandled_;
146 /// regUse_ - Tracks register usage.
147 SmallVector<unsigned, 32> regUse_;
148 SmallVector<unsigned, 32> regUseBackUp_;
150 /// vrm_ - Tracks register assignments.
153 std::auto_ptr<VirtRegRewriter> rewriter_;
155 std::auto_ptr<Spiller> spiller_;
157 // The queue of recently-used registers.
158 SmallVector<unsigned, 4> RecentRegs;
159 SmallVector<unsigned, 4>::iterator RecentNext;
161 // Record that we just picked this register.
162 void recordRecentlyUsed(unsigned reg) {
163 assert(reg != 0 && "Recently used register is NOREG!");
164 if (!RecentRegs.empty()) {
166 if (RecentNext == RecentRegs.end())
167 RecentNext = RecentRegs.begin();
172 virtual const char* getPassName() const {
173 return "Linear Scan Register Allocator";
176 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
177 AU.setPreservesCFG();
178 AU.addRequired<LiveIntervals>();
179 AU.addPreserved<SlotIndexes>();
181 AU.addRequiredID(StrongPHIEliminationID);
182 // Make sure PassManager knows which analyses to make available
183 // to coalescing and which analyses coalescing invalidates.
184 AU.addRequiredTransitive<RegisterCoalescer>();
185 if (PreSplitIntervals)
186 AU.addRequiredID(PreAllocSplittingID);
187 AU.addRequired<LiveStacks>();
188 AU.addPreserved<LiveStacks>();
189 AU.addRequired<MachineLoopInfo>();
190 AU.addPreserved<MachineLoopInfo>();
191 AU.addRequired<VirtRegMap>();
192 AU.addPreserved<VirtRegMap>();
193 AU.addPreservedID(MachineDominatorsID);
194 MachineFunctionPass::getAnalysisUsage(AU);
197 /// runOnMachineFunction - register allocate the whole function
198 bool runOnMachineFunction(MachineFunction&);
200 // Determine if we skip this register due to its being recently used.
201 bool isRecentlyUsed(unsigned reg) const {
202 return std::find(RecentRegs.begin(), RecentRegs.end(), reg) !=
207 /// linearScan - the linear scan algorithm
210 /// initIntervalSets - initialize the interval sets.
212 void initIntervalSets();
214 /// processActiveIntervals - expire old intervals and move non-overlapping
215 /// ones to the inactive list.
216 void processActiveIntervals(SlotIndex CurPoint);
218 /// processInactiveIntervals - expire old intervals and move overlapping
219 /// ones to the active list.
220 void processInactiveIntervals(SlotIndex CurPoint);
222 /// hasNextReloadInterval - Return the next liveinterval that's being
223 /// defined by a reload from the same SS as the specified one.
224 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
226 /// DowngradeRegister - Downgrade a register for allocation.
227 void DowngradeRegister(LiveInterval *li, unsigned Reg);
229 /// UpgradeRegister - Upgrade a register for allocation.
230 void UpgradeRegister(unsigned Reg);
232 /// assignRegOrStackSlotAtInterval - assign a register if one
233 /// is available, or spill.
234 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
236 void updateSpillWeights(std::vector<float> &Weights,
237 unsigned reg, float weight,
238 const TargetRegisterClass *RC);
240 /// findIntervalsToSpill - Determine the intervals to spill for the
241 /// specified interval. It's passed the physical registers whose spill
242 /// weight is the lowest among all the registers whose live intervals
243 /// conflict with the interval.
244 void findIntervalsToSpill(LiveInterval *cur,
245 std::vector<std::pair<unsigned,float> > &Candidates,
247 SmallVector<LiveInterval*, 8> &SpillIntervals);
249 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
250 /// try allocate the definition the same register as the source register
251 /// if the register is not defined during live time of the interval. This
252 /// eliminate a copy. This is used to coalesce copies which were not
253 /// coalesced away before allocation either due to dest and src being in
254 /// different register classes or because the coalescer was overly
256 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
259 /// Register usage / availability tracking helpers.
263 regUse_.resize(tri_->getNumRegs(), 0);
264 regUseBackUp_.resize(tri_->getNumRegs(), 0);
267 void finalizeRegUses() {
269 // Verify all the registers are "freed".
271 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
272 if (regUse_[i] != 0) {
273 errs() << tri_->getName(i) << " is still in use!\n";
281 regUseBackUp_.clear();
284 void addRegUse(unsigned physReg) {
285 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
286 "should be physical register!");
288 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
292 void delRegUse(unsigned physReg) {
293 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
294 "should be physical register!");
295 assert(regUse_[physReg] != 0);
297 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
298 assert(regUse_[*as] != 0);
303 bool isRegAvail(unsigned physReg) const {
304 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
305 "should be physical register!");
306 return regUse_[physReg] == 0;
309 void backUpRegUses() {
310 regUseBackUp_ = regUse_;
313 void restoreRegUses() {
314 regUse_ = regUseBackUp_;
318 /// Register handling helpers.
321 /// getFreePhysReg - return a free physical register for this virtual
322 /// register interval if we have one, otherwise return 0.
323 unsigned getFreePhysReg(LiveInterval* cur);
324 unsigned getFreePhysReg(LiveInterval* cur,
325 const TargetRegisterClass *RC,
326 unsigned MaxInactiveCount,
327 SmallVector<unsigned, 256> &inactiveCounts,
330 /// assignVirt2StackSlot - assigns this virtual register to a
331 /// stack slot. returns the stack slot
332 int assignVirt2StackSlot(unsigned virtReg);
334 void ComputeRelatedRegClasses();
336 template <typename ItTy>
337 void printIntervals(const char* const str, ItTy i, ItTy e) const {
340 errs() << str << " intervals:\n";
342 for (; i != e; ++i) {
343 errs() << "\t" << *i->first << " -> ";
345 unsigned reg = i->first->reg;
346 if (TargetRegisterInfo::isVirtualRegister(reg))
347 reg = vrm_->getPhys(reg);
349 errs() << tri_->getName(reg) << '\n';
354 char RALinScan::ID = 0;
357 static RegisterPass<RALinScan>
358 X("linearscan-regalloc", "Linear Scan Register Allocator");
360 void RALinScan::ComputeRelatedRegClasses() {
361 // First pass, add all reg classes to the union, and determine at least one
362 // reg class that each register is in.
363 bool HasAliases = false;
364 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
365 E = tri_->regclass_end(); RCI != E; ++RCI) {
366 RelatedRegClasses.insert(*RCI);
367 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
369 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
371 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
373 // Already processed this register. Just make sure we know that
374 // multiple register classes share a register.
375 RelatedRegClasses.unionSets(PRC, *RCI);
382 // Second pass, now that we know conservatively what register classes each reg
383 // belongs to, add info about aliases. We don't need to do this for targets
384 // without register aliases.
386 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
387 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
389 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
390 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
393 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
394 /// try allocate the definition the same register as the source register
395 /// if the register is not defined during live time of the interval. This
396 /// eliminate a copy. This is used to coalesce copies which were not
397 /// coalesced away before allocation either due to dest and src being in
398 /// different register classes or because the coalescer was overly
400 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
401 unsigned Preference = vrm_->getRegAllocPref(cur.reg);
402 if ((Preference && Preference == Reg) || !cur.containsOneValue())
405 VNInfo *vni = cur.begin()->valno;
406 if ((vni->def == SlotIndex()) ||
407 vni->isUnused() || !vni->isDefAccurate())
409 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
410 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg, PhysReg;
412 !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
415 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
416 if (!vrm_->isAssignedReg(SrcReg))
418 PhysReg = vrm_->getPhys(SrcReg);
423 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
424 if (!RC->contains(PhysReg))
428 if (!li_->conflictsWithPhysRegDef(cur, *vrm_, PhysReg)) {
429 DEBUG(errs() << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg)
431 vrm_->clearVirt(cur.reg);
432 vrm_->assignVirt2Phys(cur.reg, PhysReg);
434 // Remove unnecessary kills since a copy does not clobber the register.
435 if (li_->hasInterval(SrcReg)) {
436 LiveInterval &SrcLI = li_->getInterval(SrcReg);
437 for (MachineRegisterInfo::use_iterator I = mri_->use_begin(cur.reg),
438 E = mri_->use_end(); I != E; ++I) {
439 MachineOperand &O = I.getOperand();
442 MachineInstr *MI = &*I;
443 if (SrcLI.liveAt(li_->getInstructionIndex(MI).getDefIndex()))
455 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
457 mri_ = &fn.getRegInfo();
458 tm_ = &fn.getTarget();
459 tri_ = tm_->getRegisterInfo();
460 tii_ = tm_->getInstrInfo();
461 allocatableRegs_ = tri_->getAllocatableSet(fn);
462 li_ = &getAnalysis<LiveIntervals>();
463 ls_ = &getAnalysis<LiveStacks>();
464 loopInfo = &getAnalysis<MachineLoopInfo>();
466 // We don't run the coalescer here because we have no reason to
467 // interact with it. If the coalescer requires interaction, it
468 // won't do anything. If it doesn't require interaction, we assume
469 // it was run as a separate pass.
471 // If this is the first function compiled, compute the related reg classes.
472 if (RelatedRegClasses.empty())
473 ComputeRelatedRegClasses();
475 // Also resize register usage trackers.
478 vrm_ = &getAnalysis<VirtRegMap>();
479 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
481 spiller_.reset(createSpiller(mf_, li_, loopInfo, vrm_));
487 // Rewrite spill code and update the PhysRegsUsed set.
488 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
490 assert(unhandled_.empty() && "Unhandled live intervals remain!");
498 NextReloadMap.clear();
499 DowngradedRegs.clear();
500 DowngradeMap.clear();
506 /// initIntervalSets - initialize the interval sets.
508 void RALinScan::initIntervalSets()
510 assert(unhandled_.empty() && fixed_.empty() &&
511 active_.empty() && inactive_.empty() &&
512 "interval sets should be empty on initialization");
514 handled_.reserve(li_->getNumIntervals());
516 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
517 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
518 if (!i->second->empty()) {
519 mri_->setPhysRegUsed(i->second->reg);
520 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
523 if (i->second->empty()) {
524 assignRegOrStackSlotAtInterval(i->second);
527 unhandled_.push(i->second);
532 void RALinScan::linearScan() {
533 // linear scan algorithm
535 errs() << "********** LINEAR SCAN **********\n"
536 << "********** Function: "
537 << mf_->getFunction()->getName() << '\n';
538 printIntervals("fixed", fixed_.begin(), fixed_.end());
541 while (!unhandled_.empty()) {
542 // pick the interval with the earliest start point
543 LiveInterval* cur = unhandled_.top();
546 DEBUG(errs() << "\n*** CURRENT ***: " << *cur << '\n');
548 assert(!cur->empty() && "Empty interval in unhandled set.");
550 processActiveIntervals(cur->beginIndex());
551 processInactiveIntervals(cur->beginIndex());
553 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
554 "Can only allocate virtual registers!");
556 // Allocating a virtual register. try to find a free
557 // physical register or spill an interval (possibly this one) in order to
559 assignRegOrStackSlotAtInterval(cur);
562 printIntervals("active", active_.begin(), active_.end());
563 printIntervals("inactive", inactive_.begin(), inactive_.end());
567 // Expire any remaining active intervals
568 while (!active_.empty()) {
569 IntervalPtr &IP = active_.back();
570 unsigned reg = IP.first->reg;
571 DEBUG(errs() << "\tinterval " << *IP.first << " expired\n");
572 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
573 "Can only allocate virtual registers!");
574 reg = vrm_->getPhys(reg);
579 // Expire any remaining inactive intervals
581 for (IntervalPtrs::reverse_iterator
582 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
583 errs() << "\tinterval " << *i->first << " expired\n";
587 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
588 MachineFunction::iterator EntryMBB = mf_->begin();
589 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
590 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
591 LiveInterval &cur = *i->second;
593 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
596 else if (vrm_->isAssignedReg(cur.reg))
597 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
600 // Ignore splited live intervals.
601 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
604 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
606 const LiveRange &LR = *I;
607 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
608 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
609 if (LiveInMBBs[i] != EntryMBB) {
610 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
611 "Adding a virtual register to livein set?");
612 LiveInMBBs[i]->addLiveIn(Reg);
619 DEBUG(errs() << *vrm_);
621 // Look for physical registers that end up not being allocated even though
622 // register allocator had to spill other registers in its register class.
623 if (ls_->getNumIntervals() == 0)
625 if (!vrm_->FindUnusedRegisters(li_))
629 /// processActiveIntervals - expire old intervals and move non-overlapping ones
630 /// to the inactive list.
631 void RALinScan::processActiveIntervals(SlotIndex CurPoint)
633 DEBUG(errs() << "\tprocessing active intervals:\n");
635 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
636 LiveInterval *Interval = active_[i].first;
637 LiveInterval::iterator IntervalPos = active_[i].second;
638 unsigned reg = Interval->reg;
640 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
642 if (IntervalPos == Interval->end()) { // Remove expired intervals.
643 DEBUG(errs() << "\t\tinterval " << *Interval << " expired\n");
644 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
645 "Can only allocate virtual registers!");
646 reg = vrm_->getPhys(reg);
649 // Pop off the end of the list.
650 active_[i] = active_.back();
654 } else if (IntervalPos->start > CurPoint) {
655 // Move inactive intervals to inactive list.
656 DEBUG(errs() << "\t\tinterval " << *Interval << " inactive\n");
657 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
658 "Can only allocate virtual registers!");
659 reg = vrm_->getPhys(reg);
662 inactive_.push_back(std::make_pair(Interval, IntervalPos));
664 // Pop off the end of the list.
665 active_[i] = active_.back();
669 // Otherwise, just update the iterator position.
670 active_[i].second = IntervalPos;
675 /// processInactiveIntervals - expire old intervals and move overlapping
676 /// ones to the active list.
677 void RALinScan::processInactiveIntervals(SlotIndex CurPoint)
679 DEBUG(errs() << "\tprocessing inactive intervals:\n");
681 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
682 LiveInterval *Interval = inactive_[i].first;
683 LiveInterval::iterator IntervalPos = inactive_[i].second;
684 unsigned reg = Interval->reg;
686 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
688 if (IntervalPos == Interval->end()) { // remove expired intervals.
689 DEBUG(errs() << "\t\tinterval " << *Interval << " expired\n");
691 // Pop off the end of the list.
692 inactive_[i] = inactive_.back();
693 inactive_.pop_back();
695 } else if (IntervalPos->start <= CurPoint) {
696 // move re-activated intervals in active list
697 DEBUG(errs() << "\t\tinterval " << *Interval << " active\n");
698 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
699 "Can only allocate virtual registers!");
700 reg = vrm_->getPhys(reg);
703 active_.push_back(std::make_pair(Interval, IntervalPos));
705 // Pop off the end of the list.
706 inactive_[i] = inactive_.back();
707 inactive_.pop_back();
710 // Otherwise, just update the iterator position.
711 inactive_[i].second = IntervalPos;
716 /// updateSpillWeights - updates the spill weights of the specifed physical
717 /// register and its weight.
718 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
719 unsigned reg, float weight,
720 const TargetRegisterClass *RC) {
721 SmallSet<unsigned, 4> Processed;
722 SmallSet<unsigned, 4> SuperAdded;
723 SmallVector<unsigned, 4> Supers;
724 Weights[reg] += weight;
725 Processed.insert(reg);
726 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
727 Weights[*as] += weight;
728 Processed.insert(*as);
729 if (tri_->isSubRegister(*as, reg) &&
730 SuperAdded.insert(*as) &&
732 Supers.push_back(*as);
736 // If the alias is a super-register, and the super-register is in the
737 // register class we are trying to allocate. Then add the weight to all
738 // sub-registers of the super-register even if they are not aliases.
739 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
740 // bl should get the same spill weight otherwise it will be choosen
741 // as a spill candidate since spilling bh doesn't make ebx available.
742 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
743 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
744 if (!Processed.count(*sr))
745 Weights[*sr] += weight;
750 RALinScan::IntervalPtrs::iterator
751 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
752 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
754 if (I->first == LI) return I;
758 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, SlotIndex Point){
759 for (unsigned i = 0, e = V.size(); i != e; ++i) {
760 RALinScan::IntervalPtr &IP = V[i];
761 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
763 if (I != IP.first->begin()) --I;
768 /// addStackInterval - Create a LiveInterval for stack if the specified live
769 /// interval has been spilled.
770 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
772 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
773 int SS = vrm_.getStackSlot(cur->reg);
774 if (SS == VirtRegMap::NO_STACK_SLOT)
777 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
778 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
781 if (SI.hasAtLeastOneValue())
782 VNI = SI.getValNumInfo(0);
784 VNI = SI.getNextValue(SlotIndex(), 0, false,
785 ls_->getVNInfoAllocator());
787 LiveInterval &RI = li_->getInterval(cur->reg);
788 // FIXME: This may be overly conservative.
789 SI.MergeRangesInAsValue(RI, VNI);
792 /// getConflictWeight - Return the number of conflicts between cur
793 /// live interval and defs and uses of Reg weighted by loop depthes.
795 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
796 MachineRegisterInfo *mri_,
797 const MachineLoopInfo *loopInfo) {
799 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
800 E = mri_->reg_end(); I != E; ++I) {
801 MachineInstr *MI = &*I;
802 if (cur->liveAt(li_->getInstructionIndex(MI))) {
803 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
804 Conflicts += powf(10.0f, (float)loopDepth);
810 /// findIntervalsToSpill - Determine the intervals to spill for the
811 /// specified interval. It's passed the physical registers whose spill
812 /// weight is the lowest among all the registers whose live intervals
813 /// conflict with the interval.
814 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
815 std::vector<std::pair<unsigned,float> > &Candidates,
817 SmallVector<LiveInterval*, 8> &SpillIntervals) {
818 // We have figured out the *best* register to spill. But there are other
819 // registers that are pretty good as well (spill weight within 3%). Spill
820 // the one that has fewest defs and uses that conflict with cur.
821 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
822 SmallVector<LiveInterval*, 8> SLIs[3];
825 errs() << "\tConsidering " << NumCands << " candidates: ";
826 for (unsigned i = 0; i != NumCands; ++i)
827 errs() << tri_->getName(Candidates[i].first) << " ";
831 // Calculate the number of conflicts of each candidate.
832 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
833 unsigned Reg = i->first->reg;
834 unsigned PhysReg = vrm_->getPhys(Reg);
835 if (!cur->overlapsFrom(*i->first, i->second))
837 for (unsigned j = 0; j < NumCands; ++j) {
838 unsigned Candidate = Candidates[j].first;
839 if (tri_->regsOverlap(PhysReg, Candidate)) {
841 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
842 SLIs[j].push_back(i->first);
847 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
848 unsigned Reg = i->first->reg;
849 unsigned PhysReg = vrm_->getPhys(Reg);
850 if (!cur->overlapsFrom(*i->first, i->second-1))
852 for (unsigned j = 0; j < NumCands; ++j) {
853 unsigned Candidate = Candidates[j].first;
854 if (tri_->regsOverlap(PhysReg, Candidate)) {
856 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
857 SLIs[j].push_back(i->first);
862 // Which is the best candidate?
863 unsigned BestCandidate = 0;
864 float MinConflicts = Conflicts[0];
865 for (unsigned i = 1; i != NumCands; ++i) {
866 if (Conflicts[i] < MinConflicts) {
868 MinConflicts = Conflicts[i];
872 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
873 std::back_inserter(SpillIntervals));
877 struct WeightCompare {
879 const RALinScan &Allocator;
882 WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {};
884 typedef std::pair<unsigned, float> RegWeightPair;
885 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
886 return LHS.second < RHS.second && !Allocator.isRecentlyUsed(LHS.first);
891 static bool weightsAreClose(float w1, float w2) {
895 float diff = w1 - w2;
896 if (diff <= 0.02f) // Within 0.02f
898 return (diff / w2) <= 0.05f; // Within 5%.
901 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
902 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
903 if (I == NextReloadMap.end())
905 return &li_->getInterval(I->second);
908 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
909 bool isNew = DowngradedRegs.insert(Reg);
910 isNew = isNew; // Silence compiler warning.
911 assert(isNew && "Multiple reloads holding the same register?");
912 DowngradeMap.insert(std::make_pair(li->reg, Reg));
913 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
914 isNew = DowngradedRegs.insert(*AS);
915 isNew = isNew; // Silence compiler warning.
916 assert(isNew && "Multiple reloads holding the same register?");
917 DowngradeMap.insert(std::make_pair(li->reg, *AS));
922 void RALinScan::UpgradeRegister(unsigned Reg) {
924 DowngradedRegs.erase(Reg);
925 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
926 DowngradedRegs.erase(*AS);
932 bool operator()(LiveInterval* A, LiveInterval* B) {
933 return A->beginIndex() < B->beginIndex();
938 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
940 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
941 DEBUG(errs() << "\tallocating current interval: ");
943 // This is an implicitly defined live interval, just assign any register.
944 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
946 unsigned physReg = vrm_->getRegAllocPref(cur->reg);
948 physReg = *RC->allocation_order_begin(*mf_);
949 DEBUG(errs() << tri_->getName(physReg) << '\n');
950 // Note the register is not really in use.
951 vrm_->assignVirt2Phys(cur->reg, physReg);
957 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
958 SlotIndex StartPosition = cur->beginIndex();
959 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
961 // If start of this live interval is defined by a move instruction and its
962 // source is assigned a physical register that is compatible with the target
963 // register class, then we should try to assign it the same register.
964 // This can happen when the move is from a larger register class to a smaller
965 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
966 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
967 VNInfo *vni = cur->begin()->valno;
968 if ((vni->def != SlotIndex()) && !vni->isUnused() &&
969 vni->isDefAccurate()) {
970 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
971 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
973 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
975 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
977 else if (vrm_->isAssignedReg(SrcReg))
978 Reg = vrm_->getPhys(SrcReg);
981 Reg = tri_->getSubReg(Reg, SrcSubReg);
983 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
984 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
985 mri_->setRegAllocationHint(cur->reg, 0, Reg);
991 // For every interval in inactive we overlap with, mark the
992 // register as not free and update spill weights.
993 for (IntervalPtrs::const_iterator i = inactive_.begin(),
994 e = inactive_.end(); i != e; ++i) {
995 unsigned Reg = i->first->reg;
996 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
997 "Can only allocate virtual registers!");
998 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
999 // If this is not in a related reg class to the register we're allocating,
1001 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1002 cur->overlapsFrom(*i->first, i->second-1)) {
1003 Reg = vrm_->getPhys(Reg);
1005 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
1009 // Speculatively check to see if we can get a register right now. If not,
1010 // we know we won't be able to by adding more constraints. If so, we can
1011 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
1012 // is very bad (it contains all callee clobbered registers for any functions
1013 // with a call), so we want to avoid doing that if possible.
1014 unsigned physReg = getFreePhysReg(cur);
1015 unsigned BestPhysReg = physReg;
1017 // We got a register. However, if it's in the fixed_ list, we might
1018 // conflict with it. Check to see if we conflict with it or any of its
1020 SmallSet<unsigned, 8> RegAliases;
1021 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
1022 RegAliases.insert(*AS);
1024 bool ConflictsWithFixed = false;
1025 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1026 IntervalPtr &IP = fixed_[i];
1027 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
1028 // Okay, this reg is on the fixed list. Check to see if we actually
1030 LiveInterval *I = IP.first;
1031 if (I->endIndex() > StartPosition) {
1032 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1034 if (II != I->begin() && II->start > StartPosition)
1036 if (cur->overlapsFrom(*I, II)) {
1037 ConflictsWithFixed = true;
1044 // Okay, the register picked by our speculative getFreePhysReg call turned
1045 // out to be in use. Actually add all of the conflicting fixed registers to
1046 // regUse_ so we can do an accurate query.
1047 if (ConflictsWithFixed) {
1048 // For every interval in fixed we overlap with, mark the register as not
1049 // free and update spill weights.
1050 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1051 IntervalPtr &IP = fixed_[i];
1052 LiveInterval *I = IP.first;
1054 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
1055 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1056 I->endIndex() > StartPosition) {
1057 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1059 if (II != I->begin() && II->start > StartPosition)
1061 if (cur->overlapsFrom(*I, II)) {
1062 unsigned reg = I->reg;
1064 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1069 // Using the newly updated regUse_ object, which includes conflicts in the
1070 // future, see if there are any registers available.
1071 physReg = getFreePhysReg(cur);
1075 // Restore the physical register tracker, removing information about the
1079 // If we find a free register, we are done: assign this virtual to
1080 // the free physical register and add this interval to the active
1083 DEBUG(errs() << tri_->getName(physReg) << '\n');
1084 vrm_->assignVirt2Phys(cur->reg, physReg);
1086 active_.push_back(std::make_pair(cur, cur->begin()));
1087 handled_.push_back(cur);
1089 // "Upgrade" the physical register since it has been allocated.
1090 UpgradeRegister(physReg);
1091 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1092 // "Downgrade" physReg to try to keep physReg from being allocated until
1093 // the next reload from the same SS is allocated.
1094 mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
1095 DowngradeRegister(cur, physReg);
1099 DEBUG(errs() << "no free registers\n");
1101 // Compile the spill weights into an array that is better for scanning.
1102 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1103 for (std::vector<std::pair<unsigned, float> >::iterator
1104 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1105 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1107 // for each interval in active, update spill weights.
1108 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1110 unsigned reg = i->first->reg;
1111 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1112 "Can only allocate virtual registers!");
1113 reg = vrm_->getPhys(reg);
1114 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1117 DEBUG(errs() << "\tassigning stack slot at interval "<< *cur << ":\n");
1119 // Find a register to spill.
1120 float minWeight = HUGE_VALF;
1121 unsigned minReg = 0;
1124 std::vector<std::pair<unsigned,float> > RegsWeights;
1125 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1126 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1127 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1129 float regWeight = SpillWeights[reg];
1130 // Skip recently allocated registers.
1131 if (minWeight > regWeight && !isRecentlyUsed(reg))
1133 RegsWeights.push_back(std::make_pair(reg, regWeight));
1136 // If we didn't find a register that is spillable, try aliases?
1138 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1139 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1141 // No need to worry about if the alias register size < regsize of RC.
1142 // We are going to spill all registers that alias it anyway.
1143 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1144 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1148 // Sort all potential spill candidates by weight.
1149 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare(*this));
1150 minReg = RegsWeights[0].first;
1151 minWeight = RegsWeights[0].second;
1152 if (minWeight == HUGE_VALF) {
1153 // All registers must have inf weight. Just grab one!
1154 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
1155 if (cur->weight == HUGE_VALF ||
1156 li_->getApproximateInstructionCount(*cur) == 0) {
1157 // Spill a physical register around defs and uses.
1158 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1159 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1160 // in fixed_. Reset them.
1161 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1162 IntervalPtr &IP = fixed_[i];
1163 LiveInterval *I = IP.first;
1164 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1165 IP.second = I->advanceTo(I->begin(), StartPosition);
1168 DowngradedRegs.clear();
1169 assignRegOrStackSlotAtInterval(cur);
1171 assert(false && "Ran out of registers during register allocation!");
1172 llvm_report_error("Ran out of registers during register allocation!");
1178 // Find up to 3 registers to consider as spill candidates.
1179 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1180 while (LastCandidate > 1) {
1181 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1187 errs() << "\t\tregister(s) with min weight(s): ";
1189 for (unsigned i = 0; i != LastCandidate; ++i)
1190 errs() << tri_->getName(RegsWeights[i].first)
1191 << " (" << RegsWeights[i].second << ")\n";
1194 // If the current has the minimum weight, we need to spill it and
1195 // add any added intervals back to unhandled, and restart
1197 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1198 DEBUG(errs() << "\t\t\tspilling(c): " << *cur << '\n');
1199 SmallVector<LiveInterval*, 8> spillIs;
1200 std::vector<LiveInterval*> added;
1202 added = spiller_->spill(cur, spillIs);
1204 std::sort(added.begin(), added.end(), LISorter());
1205 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1207 return; // Early exit if all spills were folded.
1209 // Merge added with unhandled. Note that we have already sorted
1210 // intervals returned by addIntervalsForSpills by their starting
1212 // This also update the NextReloadMap. That is, it adds mapping from a
1213 // register defined by a reload from SS to the next reload from SS in the
1214 // same basic block.
1215 MachineBasicBlock *LastReloadMBB = 0;
1216 LiveInterval *LastReload = 0;
1217 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1218 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1219 LiveInterval *ReloadLi = added[i];
1220 if (ReloadLi->weight == HUGE_VALF &&
1221 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1222 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1223 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1224 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1225 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1226 // Last reload of same SS is in the same MBB. We want to try to
1227 // allocate both reloads the same register and make sure the reg
1228 // isn't clobbered in between if at all possible.
1229 assert(LastReload->beginIndex() < ReloadIdx);
1230 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1232 LastReloadMBB = ReloadMBB;
1233 LastReload = ReloadLi;
1234 LastReloadSS = ReloadSS;
1236 unhandled_.push(ReloadLi);
1243 // Push the current interval back to unhandled since we are going
1244 // to re-run at least this iteration. Since we didn't modify it it
1245 // should go back right in the front of the list
1246 unhandled_.push(cur);
1248 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1249 "did not choose a register to spill?");
1251 // We spill all intervals aliasing the register with
1252 // minimum weight, rollback to the interval with the earliest
1253 // start point and let the linear scan algorithm run again
1254 SmallVector<LiveInterval*, 8> spillIs;
1256 // Determine which intervals have to be spilled.
1257 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1259 // Set of spilled vregs (used later to rollback properly)
1260 SmallSet<unsigned, 8> spilled;
1262 // The earliest start of a Spilled interval indicates up to where
1263 // in handled we need to roll back
1264 assert(!spillIs.empty() && "No spill intervals?");
1265 SlotIndex earliestStart = spillIs[0]->beginIndex();
1267 // Spill live intervals of virtual regs mapped to the physical register we
1268 // want to clear (and its aliases). We only spill those that overlap with the
1269 // current interval as the rest do not affect its allocation. we also keep
1270 // track of the earliest start of all spilled live intervals since this will
1271 // mark our rollback point.
1272 std::vector<LiveInterval*> added;
1273 while (!spillIs.empty()) {
1274 LiveInterval *sli = spillIs.back();
1276 DEBUG(errs() << "\t\t\tspilling(a): " << *sli << '\n');
1277 if (sli->beginIndex() < earliestStart)
1278 earliestStart = sli->beginIndex();
1280 std::vector<LiveInterval*> newIs;
1281 newIs = spiller_->spill(sli, spillIs, &earliestStart);
1282 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1283 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
1284 spilled.insert(sli->reg);
1287 DEBUG(errs() << "\t\trolling back to: " << earliestStart << '\n');
1289 // Scan handled in reverse order up to the earliest start of a
1290 // spilled live interval and undo each one, restoring the state of
1292 while (!handled_.empty()) {
1293 LiveInterval* i = handled_.back();
1294 // If this interval starts before t we are done.
1295 if (!i->empty() && i->beginIndex() < earliestStart)
1297 DEBUG(errs() << "\t\t\tundo changes for: " << *i << '\n');
1298 handled_.pop_back();
1300 // When undoing a live interval allocation we must know if it is active or
1301 // inactive to properly update regUse_ and the VirtRegMap.
1302 IntervalPtrs::iterator it;
1303 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1305 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1306 if (!spilled.count(i->reg))
1308 delRegUse(vrm_->getPhys(i->reg));
1309 vrm_->clearVirt(i->reg);
1310 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1311 inactive_.erase(it);
1312 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1313 if (!spilled.count(i->reg))
1315 vrm_->clearVirt(i->reg);
1317 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1318 "Can only allocate virtual registers!");
1319 vrm_->clearVirt(i->reg);
1323 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1324 if (ii == DowngradeMap.end())
1325 // It interval has a preference, it must be defined by a copy. Clear the
1326 // preference now since the source interval allocation may have been
1328 mri_->setRegAllocationHint(i->reg, 0, 0);
1330 UpgradeRegister(ii->second);
1334 // Rewind the iterators in the active, inactive, and fixed lists back to the
1335 // point we reverted to.
1336 RevertVectorIteratorsTo(active_, earliestStart);
1337 RevertVectorIteratorsTo(inactive_, earliestStart);
1338 RevertVectorIteratorsTo(fixed_, earliestStart);
1340 // Scan the rest and undo each interval that expired after t and
1341 // insert it in active (the next iteration of the algorithm will
1342 // put it in inactive if required)
1343 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1344 LiveInterval *HI = handled_[i];
1345 if (!HI->expiredAt(earliestStart) &&
1346 HI->expiredAt(cur->beginIndex())) {
1347 DEBUG(errs() << "\t\t\tundo changes for: " << *HI << '\n');
1348 active_.push_back(std::make_pair(HI, HI->begin()));
1349 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1350 addRegUse(vrm_->getPhys(HI->reg));
1354 // Merge added with unhandled.
1355 // This also update the NextReloadMap. That is, it adds mapping from a
1356 // register defined by a reload from SS to the next reload from SS in the
1357 // same basic block.
1358 MachineBasicBlock *LastReloadMBB = 0;
1359 LiveInterval *LastReload = 0;
1360 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1361 std::sort(added.begin(), added.end(), LISorter());
1362 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1363 LiveInterval *ReloadLi = added[i];
1364 if (ReloadLi->weight == HUGE_VALF &&
1365 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1366 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1367 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1368 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1369 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1370 // Last reload of same SS is in the same MBB. We want to try to
1371 // allocate both reloads the same register and make sure the reg
1372 // isn't clobbered in between if at all possible.
1373 assert(LastReload->beginIndex() < ReloadIdx);
1374 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1376 LastReloadMBB = ReloadMBB;
1377 LastReload = ReloadLi;
1378 LastReloadSS = ReloadSS;
1380 unhandled_.push(ReloadLi);
1384 unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
1385 const TargetRegisterClass *RC,
1386 unsigned MaxInactiveCount,
1387 SmallVector<unsigned, 256> &inactiveCounts,
1389 unsigned FreeReg = 0;
1390 unsigned FreeRegInactiveCount = 0;
1392 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
1393 // Resolve second part of the hint (if possible) given the current allocation.
1394 unsigned physReg = Hint.second;
1396 TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
1397 physReg = vrm_->getPhys(physReg);
1399 TargetRegisterClass::iterator I, E;
1400 tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
1401 assert(I != E && "No allocatable register in this register class!");
1403 // Scan for the first available register.
1404 for (; I != E; ++I) {
1406 // Ignore "downgraded" registers.
1407 if (SkipDGRegs && DowngradedRegs.count(Reg))
1409 // Skip recently allocated registers.
1410 if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) {
1412 if (FreeReg < inactiveCounts.size())
1413 FreeRegInactiveCount = inactiveCounts[FreeReg];
1415 FreeRegInactiveCount = 0;
1420 // If there are no free regs, or if this reg has the max inactive count,
1421 // return this register.
1422 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) {
1423 // Remember what register we picked so we can skip it next time.
1424 if (FreeReg != 0) recordRecentlyUsed(FreeReg);
1428 // Continue scanning the registers, looking for the one with the highest
1429 // inactive count. Alkis found that this reduced register pressure very
1430 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1432 for (; I != E; ++I) {
1434 // Ignore "downgraded" registers.
1435 if (SkipDGRegs && DowngradedRegs.count(Reg))
1437 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1438 FreeRegInactiveCount < inactiveCounts[Reg] && !isRecentlyUsed(Reg)) {
1440 FreeRegInactiveCount = inactiveCounts[Reg];
1441 if (FreeRegInactiveCount == MaxInactiveCount)
1442 break; // We found the one with the max inactive count.
1446 // Remember what register we picked so we can skip it next time.
1447 recordRecentlyUsed(FreeReg);
1452 /// getFreePhysReg - return a free physical register for this virtual register
1453 /// interval if we have one, otherwise return 0.
1454 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1455 SmallVector<unsigned, 256> inactiveCounts;
1456 unsigned MaxInactiveCount = 0;
1458 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1459 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1461 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1463 unsigned reg = i->first->reg;
1464 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1465 "Can only allocate virtual registers!");
1467 // If this is not in a related reg class to the register we're allocating,
1469 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1470 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1471 reg = vrm_->getPhys(reg);
1472 if (inactiveCounts.size() <= reg)
1473 inactiveCounts.resize(reg+1);
1474 ++inactiveCounts[reg];
1475 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1479 // If copy coalescer has assigned a "preferred" register, check if it's
1481 unsigned Preference = vrm_->getRegAllocPref(cur->reg);
1483 DEBUG(errs() << "(preferred: " << tri_->getName(Preference) << ") ");
1484 if (isRegAvail(Preference) &&
1485 RC->contains(Preference))
1489 if (!DowngradedRegs.empty()) {
1490 unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
1495 return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
1498 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1499 return new RALinScan();