1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/LiveStackAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegAllocRegistry.h"
27 #include "llvm/CodeGen/RegisterCoalescer.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/ADT/EquivalenceClasses.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/Compiler.h"
46 STATISTIC(NumIters , "Number of iterations performed");
47 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
48 STATISTIC(NumCoalesce, "Number of copies coalesced");
49 STATISTIC(NumDowngrade, "Number of registers downgraded");
52 NewHeuristic("new-spilling-heuristic",
53 cl::desc("Use new spilling heuristic"),
54 cl::init(false), cl::Hidden);
57 PreSplitIntervals("pre-alloc-split",
58 cl::desc("Pre-register allocation live interval splitting"),
59 cl::init(false), cl::Hidden);
62 NewSpillFramework("new-spill-framework",
63 cl::desc("New spilling framework"),
64 cl::init(false), cl::Hidden);
66 static RegisterRegAlloc
67 linearscanRegAlloc("linearscan", "linear scan register allocator",
68 createLinearScanRegisterAllocator);
71 struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
73 RALinScan() : MachineFunctionPass(&ID) {}
75 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
76 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
78 /// RelatedRegClasses - This structure is built the first time a function is
79 /// compiled, and keeps track of which register classes have registers that
80 /// belong to multiple classes or have aliases that are in other classes.
81 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
82 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
84 // NextReloadMap - For each register in the map, it maps to the another
85 // register which is defined by a reload from the same stack slot and
86 // both reloads are in the same basic block.
87 DenseMap<unsigned, unsigned> NextReloadMap;
89 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
90 // un-favored for allocation.
91 SmallSet<unsigned, 8> DowngradedRegs;
93 // DowngradeMap - A map from virtual registers to physical registers being
94 // downgraded for the virtual registers.
95 DenseMap<unsigned, unsigned> DowngradeMap;
98 MachineRegisterInfo* mri_;
99 const TargetMachine* tm_;
100 const TargetRegisterInfo* tri_;
101 const TargetInstrInfo* tii_;
102 BitVector allocatableRegs_;
105 const MachineLoopInfo *loopInfo;
107 /// handled_ - Intervals are added to the handled_ set in the order of their
108 /// start value. This is uses for backtracking.
109 std::vector<LiveInterval*> handled_;
111 /// fixed_ - Intervals that correspond to machine registers.
115 /// active_ - Intervals that are currently being processed, and which have a
116 /// live range active for the current point.
117 IntervalPtrs active_;
119 /// inactive_ - Intervals that are currently being processed, but which have
120 /// a hold at the current point.
121 IntervalPtrs inactive_;
123 typedef std::priority_queue<LiveInterval*,
124 SmallVector<LiveInterval*, 64>,
125 greater_ptr<LiveInterval> > IntervalHeap;
126 IntervalHeap unhandled_;
128 /// regUse_ - Tracks register usage.
129 SmallVector<unsigned, 32> regUse_;
130 SmallVector<unsigned, 32> regUseBackUp_;
132 /// vrm_ - Tracks register assignments.
135 std::auto_ptr<VirtRegRewriter> rewriter_;
137 std::auto_ptr<Spiller> spiller_;
140 virtual const char* getPassName() const {
141 return "Linear Scan Register Allocator";
144 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
145 AU.addRequired<LiveIntervals>();
147 AU.addRequiredID(StrongPHIEliminationID);
148 // Make sure PassManager knows which analyses to make available
149 // to coalescing and which analyses coalescing invalidates.
150 AU.addRequiredTransitive<RegisterCoalescer>();
151 if (PreSplitIntervals)
152 AU.addRequiredID(PreAllocSplittingID);
153 AU.addRequired<LiveStacks>();
154 AU.addPreserved<LiveStacks>();
155 AU.addRequired<MachineLoopInfo>();
156 AU.addPreserved<MachineLoopInfo>();
157 AU.addRequired<VirtRegMap>();
158 AU.addPreserved<VirtRegMap>();
159 AU.addPreservedID(MachineDominatorsID);
160 MachineFunctionPass::getAnalysisUsage(AU);
163 /// runOnMachineFunction - register allocate the whole function
164 bool runOnMachineFunction(MachineFunction&);
167 /// linearScan - the linear scan algorithm
170 /// initIntervalSets - initialize the interval sets.
172 void initIntervalSets();
174 /// processActiveIntervals - expire old intervals and move non-overlapping
175 /// ones to the inactive list.
176 void processActiveIntervals(unsigned CurPoint);
178 /// processInactiveIntervals - expire old intervals and move overlapping
179 /// ones to the active list.
180 void processInactiveIntervals(unsigned CurPoint);
182 /// hasNextReloadInterval - Return the next liveinterval that's being
183 /// defined by a reload from the same SS as the specified one.
184 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
186 /// DowngradeRegister - Downgrade a register for allocation.
187 void DowngradeRegister(LiveInterval *li, unsigned Reg);
189 /// UpgradeRegister - Upgrade a register for allocation.
190 void UpgradeRegister(unsigned Reg);
192 /// assignRegOrStackSlotAtInterval - assign a register if one
193 /// is available, or spill.
194 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
196 void updateSpillWeights(std::vector<float> &Weights,
197 unsigned reg, float weight,
198 const TargetRegisterClass *RC);
200 /// findIntervalsToSpill - Determine the intervals to spill for the
201 /// specified interval. It's passed the physical registers whose spill
202 /// weight is the lowest among all the registers whose live intervals
203 /// conflict with the interval.
204 void findIntervalsToSpill(LiveInterval *cur,
205 std::vector<std::pair<unsigned,float> > &Candidates,
207 SmallVector<LiveInterval*, 8> &SpillIntervals);
209 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
210 /// try allocate the definition the same register as the source register
211 /// if the register is not defined during live time of the interval. This
212 /// eliminate a copy. This is used to coalesce copies which were not
213 /// coalesced away before allocation either due to dest and src being in
214 /// different register classes or because the coalescer was overly
216 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
219 /// Register usage / availability tracking helpers.
223 regUse_.resize(tri_->getNumRegs(), 0);
224 regUseBackUp_.resize(tri_->getNumRegs(), 0);
227 void finalizeRegUses() {
229 // Verify all the registers are "freed".
231 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
232 if (regUse_[i] != 0) {
233 cerr << tri_->getName(i) << " is still in use!\n";
241 regUseBackUp_.clear();
244 void addRegUse(unsigned physReg) {
245 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
246 "should be physical register!");
248 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
252 void delRegUse(unsigned physReg) {
253 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
254 "should be physical register!");
255 assert(regUse_[physReg] != 0);
257 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
258 assert(regUse_[*as] != 0);
263 bool isRegAvail(unsigned physReg) const {
264 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
265 "should be physical register!");
266 return regUse_[physReg] == 0;
269 void backUpRegUses() {
270 regUseBackUp_ = regUse_;
273 void restoreRegUses() {
274 regUse_ = regUseBackUp_;
278 /// Register handling helpers.
281 /// getFreePhysReg - return a free physical register for this virtual
282 /// register interval if we have one, otherwise return 0.
283 unsigned getFreePhysReg(LiveInterval* cur);
284 unsigned getFreePhysReg(const TargetRegisterClass *RC,
285 unsigned MaxInactiveCount,
286 SmallVector<unsigned, 256> &inactiveCounts,
289 /// assignVirt2StackSlot - assigns this virtual register to a
290 /// stack slot. returns the stack slot
291 int assignVirt2StackSlot(unsigned virtReg);
293 void ComputeRelatedRegClasses();
295 template <typename ItTy>
296 void printIntervals(const char* const str, ItTy i, ItTy e) const {
297 if (str) DOUT << str << " intervals:\n";
298 for (; i != e; ++i) {
299 DOUT << "\t" << *i->first << " -> ";
300 unsigned reg = i->first->reg;
301 if (TargetRegisterInfo::isVirtualRegister(reg)) {
302 reg = vrm_->getPhys(reg);
304 DOUT << tri_->getName(reg) << '\n';
308 char RALinScan::ID = 0;
311 static RegisterPass<RALinScan>
312 X("linearscan-regalloc", "Linear Scan Register Allocator");
314 void RALinScan::ComputeRelatedRegClasses() {
315 // First pass, add all reg classes to the union, and determine at least one
316 // reg class that each register is in.
317 bool HasAliases = false;
318 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
319 E = tri_->regclass_end(); RCI != E; ++RCI) {
320 RelatedRegClasses.insert(*RCI);
321 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
323 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
325 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
327 // Already processed this register. Just make sure we know that
328 // multiple register classes share a register.
329 RelatedRegClasses.unionSets(PRC, *RCI);
336 // Second pass, now that we know conservatively what register classes each reg
337 // belongs to, add info about aliases. We don't need to do this for targets
338 // without register aliases.
340 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
341 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
343 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
344 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
347 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
348 /// try allocate the definition the same register as the source register
349 /// if the register is not defined during live time of the interval. This
350 /// eliminate a copy. This is used to coalesce copies which were not
351 /// coalesced away before allocation either due to dest and src being in
352 /// different register classes or because the coalescer was overly
354 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
355 if ((cur.preference && cur.preference == Reg) || !cur.containsOneValue())
358 VNInfo *vni = cur.begin()->valno;
359 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
361 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
362 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg, PhysReg;
364 !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
367 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
368 if (!vrm_->isAssignedReg(SrcReg))
370 PhysReg = vrm_->getPhys(SrcReg);
375 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
376 if (!RC->contains(PhysReg))
380 if (!li_->conflictsWithPhysRegDef(cur, *vrm_, PhysReg)) {
381 DOUT << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg)
383 vrm_->clearVirt(cur.reg);
384 vrm_->assignVirt2Phys(cur.reg, PhysReg);
386 // Remove unnecessary kills since a copy does not clobber the register.
387 if (li_->hasInterval(SrcReg)) {
388 LiveInterval &SrcLI = li_->getInterval(SrcReg);
389 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(cur.reg),
390 E = mri_->reg_end(); I != E; ++I) {
391 MachineOperand &O = I.getOperand();
392 if (!O.isUse() || !O.isKill())
394 MachineInstr *MI = &*I;
395 if (SrcLI.liveAt(li_->getDefIndex(li_->getInstructionIndex(MI))))
407 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
409 mri_ = &fn.getRegInfo();
410 tm_ = &fn.getTarget();
411 tri_ = tm_->getRegisterInfo();
412 tii_ = tm_->getInstrInfo();
413 allocatableRegs_ = tri_->getAllocatableSet(fn);
414 li_ = &getAnalysis<LiveIntervals>();
415 ls_ = &getAnalysis<LiveStacks>();
416 loopInfo = &getAnalysis<MachineLoopInfo>();
418 // We don't run the coalescer here because we have no reason to
419 // interact with it. If the coalescer requires interaction, it
420 // won't do anything. If it doesn't require interaction, we assume
421 // it was run as a separate pass.
423 // If this is the first function compiled, compute the related reg classes.
424 if (RelatedRegClasses.empty())
425 ComputeRelatedRegClasses();
427 // Also resize register usage trackers.
430 vrm_ = &getAnalysis<VirtRegMap>();
431 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
433 if (NewSpillFramework) {
434 spiller_.reset(createSpiller(mf_, li_, ls_, vrm_));
441 // Rewrite spill code and update the PhysRegsUsed set.
442 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
444 assert(unhandled_.empty() && "Unhandled live intervals remain!");
452 NextReloadMap.clear();
453 DowngradedRegs.clear();
454 DowngradeMap.clear();
460 /// initIntervalSets - initialize the interval sets.
462 void RALinScan::initIntervalSets()
464 assert(unhandled_.empty() && fixed_.empty() &&
465 active_.empty() && inactive_.empty() &&
466 "interval sets should be empty on initialization");
468 handled_.reserve(li_->getNumIntervals());
470 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
471 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
472 mri_->setPhysRegUsed(i->second->reg);
473 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
475 unhandled_.push(i->second);
479 void RALinScan::linearScan()
481 // linear scan algorithm
482 DOUT << "********** LINEAR SCAN **********\n";
483 DOUT << "********** Function: " << mf_->getFunction()->getName() << '\n';
485 DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end()));
487 while (!unhandled_.empty()) {
488 // pick the interval with the earliest start point
489 LiveInterval* cur = unhandled_.top();
492 DOUT << "\n*** CURRENT ***: " << *cur << '\n';
495 processActiveIntervals(cur->beginNumber());
496 processInactiveIntervals(cur->beginNumber());
498 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
499 "Can only allocate virtual registers!");
502 // Allocating a virtual register. try to find a free
503 // physical register or spill an interval (possibly this one) in order to
505 assignRegOrStackSlotAtInterval(cur);
507 DEBUG(printIntervals("active", active_.begin(), active_.end()));
508 DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
511 // Expire any remaining active intervals
512 while (!active_.empty()) {
513 IntervalPtr &IP = active_.back();
514 unsigned reg = IP.first->reg;
515 DOUT << "\tinterval " << *IP.first << " expired\n";
516 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
517 "Can only allocate virtual registers!");
518 reg = vrm_->getPhys(reg);
523 // Expire any remaining inactive intervals
524 DEBUG(for (IntervalPtrs::reverse_iterator
525 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
526 DOUT << "\tinterval " << *i->first << " expired\n");
529 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
530 MachineFunction::iterator EntryMBB = mf_->begin();
531 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
532 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
533 LiveInterval &cur = *i->second;
535 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
538 else if (vrm_->isAssignedReg(cur.reg))
539 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
542 // Ignore splited live intervals.
543 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
546 // A register defined by an implicit_def can be liveout the def BB and livein
547 // to a use BB. Add it to the livein set of the use BB's.
548 if (!isPhys && cur.empty()) {
549 if (MachineInstr *DefMI = mri_->getVRegDef(cur.reg)) {
550 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
551 MachineBasicBlock *DefMBB = DefMI->getParent();
552 SmallPtrSet<MachineBasicBlock*, 4> Seen;
554 for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(cur.reg),
555 re = mri_->reg_end(); ri != re; ++ri) {
556 MachineInstr *UseMI = &*ri;
557 MachineBasicBlock *UseMBB = UseMI->getParent();
558 if (Seen.insert(UseMBB)) {
559 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
560 "Adding a virtual register to livein set?");
561 UseMBB->addLiveIn(Reg);
566 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
568 const LiveRange &LR = *I;
569 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
570 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
571 if (LiveInMBBs[i] != EntryMBB) {
572 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
573 "Adding a virtual register to livein set?");
574 LiveInMBBs[i]->addLiveIn(Reg);
583 // Look for physical registers that end up not being allocated even though
584 // register allocator had to spill other registers in its register class.
585 if (ls_->getNumIntervals() == 0)
587 if (!vrm_->FindUnusedRegisters(tri_, li_))
591 /// processActiveIntervals - expire old intervals and move non-overlapping ones
592 /// to the inactive list.
593 void RALinScan::processActiveIntervals(unsigned CurPoint)
595 DOUT << "\tprocessing active intervals:\n";
597 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
598 LiveInterval *Interval = active_[i].first;
599 LiveInterval::iterator IntervalPos = active_[i].second;
600 unsigned reg = Interval->reg;
602 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
604 if (IntervalPos == Interval->end()) { // Remove expired intervals.
605 DOUT << "\t\tinterval " << *Interval << " expired\n";
606 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
607 "Can only allocate virtual registers!");
608 reg = vrm_->getPhys(reg);
611 // Pop off the end of the list.
612 active_[i] = active_.back();
616 } else if (IntervalPos->start > CurPoint) {
617 // Move inactive intervals to inactive list.
618 DOUT << "\t\tinterval " << *Interval << " inactive\n";
619 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
620 "Can only allocate virtual registers!");
621 reg = vrm_->getPhys(reg);
624 inactive_.push_back(std::make_pair(Interval, IntervalPos));
626 // Pop off the end of the list.
627 active_[i] = active_.back();
631 // Otherwise, just update the iterator position.
632 active_[i].second = IntervalPos;
637 /// processInactiveIntervals - expire old intervals and move overlapping
638 /// ones to the active list.
639 void RALinScan::processInactiveIntervals(unsigned CurPoint)
641 DOUT << "\tprocessing inactive intervals:\n";
643 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
644 LiveInterval *Interval = inactive_[i].first;
645 LiveInterval::iterator IntervalPos = inactive_[i].second;
646 unsigned reg = Interval->reg;
648 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
650 if (IntervalPos == Interval->end()) { // remove expired intervals.
651 DOUT << "\t\tinterval " << *Interval << " expired\n";
653 // Pop off the end of the list.
654 inactive_[i] = inactive_.back();
655 inactive_.pop_back();
657 } else if (IntervalPos->start <= CurPoint) {
658 // move re-activated intervals in active list
659 DOUT << "\t\tinterval " << *Interval << " active\n";
660 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
661 "Can only allocate virtual registers!");
662 reg = vrm_->getPhys(reg);
665 active_.push_back(std::make_pair(Interval, IntervalPos));
667 // Pop off the end of the list.
668 inactive_[i] = inactive_.back();
669 inactive_.pop_back();
672 // Otherwise, just update the iterator position.
673 inactive_[i].second = IntervalPos;
678 /// updateSpillWeights - updates the spill weights of the specifed physical
679 /// register and its weight.
680 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
681 unsigned reg, float weight,
682 const TargetRegisterClass *RC) {
683 SmallSet<unsigned, 4> Processed;
684 SmallSet<unsigned, 4> SuperAdded;
685 SmallVector<unsigned, 4> Supers;
686 Weights[reg] += weight;
687 Processed.insert(reg);
688 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
689 Weights[*as] += weight;
690 Processed.insert(*as);
691 if (tri_->isSubRegister(*as, reg) &&
692 SuperAdded.insert(*as) &&
694 Supers.push_back(*as);
698 // If the alias is a super-register, and the super-register is in the
699 // register class we are trying to allocate. Then add the weight to all
700 // sub-registers of the super-register even if they are not aliases.
701 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
702 // bl should get the same spill weight otherwise it will be choosen
703 // as a spill candidate since spilling bh doesn't make ebx available.
704 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
705 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
706 if (!Processed.count(*sr))
707 Weights[*sr] += weight;
712 RALinScan::IntervalPtrs::iterator
713 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
714 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
716 if (I->first == LI) return I;
720 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
721 for (unsigned i = 0, e = V.size(); i != e; ++i) {
722 RALinScan::IntervalPtr &IP = V[i];
723 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
725 if (I != IP.first->begin()) --I;
730 /// addStackInterval - Create a LiveInterval for stack if the specified live
731 /// interval has been spilled.
732 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
734 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
735 int SS = vrm_.getStackSlot(cur->reg);
736 if (SS == VirtRegMap::NO_STACK_SLOT)
739 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
740 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
743 if (SI.hasAtLeastOneValue())
744 VNI = SI.getValNumInfo(0);
746 VNI = SI.getNextValue(~0U, 0, ls_->getVNInfoAllocator());
748 LiveInterval &RI = li_->getInterval(cur->reg);
749 // FIXME: This may be overly conservative.
750 SI.MergeRangesInAsValue(RI, VNI);
753 /// getConflictWeight - Return the number of conflicts between cur
754 /// live interval and defs and uses of Reg weighted by loop depthes.
756 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
757 MachineRegisterInfo *mri_,
758 const MachineLoopInfo *loopInfo) {
760 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
761 E = mri_->reg_end(); I != E; ++I) {
762 MachineInstr *MI = &*I;
763 if (cur->liveAt(li_->getInstructionIndex(MI))) {
764 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
765 Conflicts += powf(10.0f, (float)loopDepth);
771 /// findIntervalsToSpill - Determine the intervals to spill for the
772 /// specified interval. It's passed the physical registers whose spill
773 /// weight is the lowest among all the registers whose live intervals
774 /// conflict with the interval.
775 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
776 std::vector<std::pair<unsigned,float> > &Candidates,
778 SmallVector<LiveInterval*, 8> &SpillIntervals) {
779 // We have figured out the *best* register to spill. But there are other
780 // registers that are pretty good as well (spill weight within 3%). Spill
781 // the one that has fewest defs and uses that conflict with cur.
782 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
783 SmallVector<LiveInterval*, 8> SLIs[3];
785 DOUT << "\tConsidering " << NumCands << " candidates: ";
786 DEBUG(for (unsigned i = 0; i != NumCands; ++i)
787 DOUT << tri_->getName(Candidates[i].first) << " ";
790 // Calculate the number of conflicts of each candidate.
791 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
792 unsigned Reg = i->first->reg;
793 unsigned PhysReg = vrm_->getPhys(Reg);
794 if (!cur->overlapsFrom(*i->first, i->second))
796 for (unsigned j = 0; j < NumCands; ++j) {
797 unsigned Candidate = Candidates[j].first;
798 if (tri_->regsOverlap(PhysReg, Candidate)) {
800 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
801 SLIs[j].push_back(i->first);
806 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
807 unsigned Reg = i->first->reg;
808 unsigned PhysReg = vrm_->getPhys(Reg);
809 if (!cur->overlapsFrom(*i->first, i->second-1))
811 for (unsigned j = 0; j < NumCands; ++j) {
812 unsigned Candidate = Candidates[j].first;
813 if (tri_->regsOverlap(PhysReg, Candidate)) {
815 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
816 SLIs[j].push_back(i->first);
821 // Which is the best candidate?
822 unsigned BestCandidate = 0;
823 float MinConflicts = Conflicts[0];
824 for (unsigned i = 1; i != NumCands; ++i) {
825 if (Conflicts[i] < MinConflicts) {
827 MinConflicts = Conflicts[i];
831 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
832 std::back_inserter(SpillIntervals));
836 struct WeightCompare {
837 typedef std::pair<unsigned, float> RegWeightPair;
838 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
839 return LHS.second < RHS.second;
844 static bool weightsAreClose(float w1, float w2) {
848 float diff = w1 - w2;
849 if (diff <= 0.02f) // Within 0.02f
851 return (diff / w2) <= 0.05f; // Within 5%.
854 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
855 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
856 if (I == NextReloadMap.end())
858 return &li_->getInterval(I->second);
861 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
862 bool isNew = DowngradedRegs.insert(Reg);
863 isNew = isNew; // Silence compiler warning.
864 assert(isNew && "Multiple reloads holding the same register?");
865 DowngradeMap.insert(std::make_pair(li->reg, Reg));
866 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
867 isNew = DowngradedRegs.insert(*AS);
868 isNew = isNew; // Silence compiler warning.
869 assert(isNew && "Multiple reloads holding the same register?");
870 DowngradeMap.insert(std::make_pair(li->reg, *AS));
875 void RALinScan::UpgradeRegister(unsigned Reg) {
877 DowngradedRegs.erase(Reg);
878 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
879 DowngradedRegs.erase(*AS);
885 bool operator()(LiveInterval* A, LiveInterval* B) {
886 return A->beginNumber() < B->beginNumber();
891 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
893 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
895 DOUT << "\tallocating current interval: ";
897 // This is an implicitly defined live interval, just assign any register.
898 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
900 unsigned physReg = cur->preference;
902 physReg = *RC->allocation_order_begin(*mf_);
903 DOUT << tri_->getName(physReg) << '\n';
904 // Note the register is not really in use.
905 vrm_->assignVirt2Phys(cur->reg, physReg);
911 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
912 unsigned StartPosition = cur->beginNumber();
913 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
915 // If start of this live interval is defined by a move instruction and its
916 // source is assigned a physical register that is compatible with the target
917 // register class, then we should try to assign it the same register.
918 // This can happen when the move is from a larger register class to a smaller
919 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
920 if (!cur->preference && cur->hasAtLeastOneValue()) {
921 VNInfo *vni = cur->begin()->valno;
922 if (vni->def && vni->def != ~1U && vni->def != ~0U) {
923 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
924 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
926 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
928 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
930 else if (vrm_->isAssignedReg(SrcReg))
931 Reg = vrm_->getPhys(SrcReg);
934 Reg = tri_->getSubReg(Reg, SrcSubReg);
936 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
937 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
938 cur->preference = Reg;
944 // For every interval in inactive we overlap with, mark the
945 // register as not free and update spill weights.
946 for (IntervalPtrs::const_iterator i = inactive_.begin(),
947 e = inactive_.end(); i != e; ++i) {
948 unsigned Reg = i->first->reg;
949 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
950 "Can only allocate virtual registers!");
951 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
952 // If this is not in a related reg class to the register we're allocating,
954 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
955 cur->overlapsFrom(*i->first, i->second-1)) {
956 Reg = vrm_->getPhys(Reg);
958 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
962 // Speculatively check to see if we can get a register right now. If not,
963 // we know we won't be able to by adding more constraints. If so, we can
964 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
965 // is very bad (it contains all callee clobbered registers for any functions
966 // with a call), so we want to avoid doing that if possible.
967 unsigned physReg = getFreePhysReg(cur);
968 unsigned BestPhysReg = physReg;
970 // We got a register. However, if it's in the fixed_ list, we might
971 // conflict with it. Check to see if we conflict with it or any of its
973 SmallSet<unsigned, 8> RegAliases;
974 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
975 RegAliases.insert(*AS);
977 bool ConflictsWithFixed = false;
978 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
979 IntervalPtr &IP = fixed_[i];
980 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
981 // Okay, this reg is on the fixed list. Check to see if we actually
983 LiveInterval *I = IP.first;
984 if (I->endNumber() > StartPosition) {
985 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
987 if (II != I->begin() && II->start > StartPosition)
989 if (cur->overlapsFrom(*I, II)) {
990 ConflictsWithFixed = true;
997 // Okay, the register picked by our speculative getFreePhysReg call turned
998 // out to be in use. Actually add all of the conflicting fixed registers to
999 // regUse_ so we can do an accurate query.
1000 if (ConflictsWithFixed) {
1001 // For every interval in fixed we overlap with, mark the register as not
1002 // free and update spill weights.
1003 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1004 IntervalPtr &IP = fixed_[i];
1005 LiveInterval *I = IP.first;
1007 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
1008 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1009 I->endNumber() > StartPosition) {
1010 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1012 if (II != I->begin() && II->start > StartPosition)
1014 if (cur->overlapsFrom(*I, II)) {
1015 unsigned reg = I->reg;
1017 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1022 // Using the newly updated regUse_ object, which includes conflicts in the
1023 // future, see if there are any registers available.
1024 physReg = getFreePhysReg(cur);
1028 // Restore the physical register tracker, removing information about the
1032 // If we find a free register, we are done: assign this virtual to
1033 // the free physical register and add this interval to the active
1036 DOUT << tri_->getName(physReg) << '\n';
1037 vrm_->assignVirt2Phys(cur->reg, physReg);
1039 active_.push_back(std::make_pair(cur, cur->begin()));
1040 handled_.push_back(cur);
1042 // "Upgrade" the physical register since it has been allocated.
1043 UpgradeRegister(physReg);
1044 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1045 // "Downgrade" physReg to try to keep physReg from being allocated until
1046 // the next reload from the same SS is allocated.
1047 NextReloadLI->preference = physReg;
1048 DowngradeRegister(cur, physReg);
1052 DOUT << "no free registers\n";
1054 // Compile the spill weights into an array that is better for scanning.
1055 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1056 for (std::vector<std::pair<unsigned, float> >::iterator
1057 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1058 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1060 // for each interval in active, update spill weights.
1061 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1063 unsigned reg = i->first->reg;
1064 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1065 "Can only allocate virtual registers!");
1066 reg = vrm_->getPhys(reg);
1067 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1070 DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
1072 // Find a register to spill.
1073 float minWeight = HUGE_VALF;
1074 unsigned minReg = 0; /*cur->preference*/; // Try the pref register first.
1077 std::vector<std::pair<unsigned,float> > RegsWeights;
1078 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1079 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1080 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1082 float regWeight = SpillWeights[reg];
1083 if (minWeight > regWeight)
1085 RegsWeights.push_back(std::make_pair(reg, regWeight));
1088 // If we didn't find a register that is spillable, try aliases?
1090 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1091 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1093 // No need to worry about if the alias register size < regsize of RC.
1094 // We are going to spill all registers that alias it anyway.
1095 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1096 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1100 // Sort all potential spill candidates by weight.
1101 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare());
1102 minReg = RegsWeights[0].first;
1103 minWeight = RegsWeights[0].second;
1104 if (minWeight == HUGE_VALF) {
1105 // All registers must have inf weight. Just grab one!
1106 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
1107 if (cur->weight == HUGE_VALF ||
1108 li_->getApproximateInstructionCount(*cur) == 0) {
1109 // Spill a physical register around defs and uses.
1110 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1111 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1112 // in fixed_. Reset them.
1113 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1114 IntervalPtr &IP = fixed_[i];
1115 LiveInterval *I = IP.first;
1116 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1117 IP.second = I->advanceTo(I->begin(), StartPosition);
1120 DowngradedRegs.clear();
1121 assignRegOrStackSlotAtInterval(cur);
1123 cerr << "Ran out of registers during register allocation!\n";
1130 // Find up to 3 registers to consider as spill candidates.
1131 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1132 while (LastCandidate > 1) {
1133 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1138 DOUT << "\t\tregister(s) with min weight(s): ";
1139 DEBUG(for (unsigned i = 0; i != LastCandidate; ++i)
1140 DOUT << tri_->getName(RegsWeights[i].first)
1141 << " (" << RegsWeights[i].second << ")\n");
1143 // If the current has the minimum weight, we need to spill it and
1144 // add any added intervals back to unhandled, and restart
1146 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1147 DOUT << "\t\t\tspilling(c): " << *cur << '\n';
1148 SmallVector<LiveInterval*, 8> spillIs;
1149 std::vector<LiveInterval*> added;
1151 if (!NewSpillFramework) {
1152 added = li_->addIntervalsForSpills(*cur, spillIs, loopInfo, *vrm_);
1154 added = spiller_->spill(cur);
1157 std::sort(added.begin(), added.end(), LISorter());
1158 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1160 return; // Early exit if all spills were folded.
1162 // Merge added with unhandled. Note that we have already sorted
1163 // intervals returned by addIntervalsForSpills by their starting
1165 // This also update the NextReloadMap. That is, it adds mapping from a
1166 // register defined by a reload from SS to the next reload from SS in the
1167 // same basic block.
1168 MachineBasicBlock *LastReloadMBB = 0;
1169 LiveInterval *LastReload = 0;
1170 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1171 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1172 LiveInterval *ReloadLi = added[i];
1173 if (ReloadLi->weight == HUGE_VALF &&
1174 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1175 unsigned ReloadIdx = ReloadLi->beginNumber();
1176 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1177 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1178 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1179 // Last reload of same SS is in the same MBB. We want to try to
1180 // allocate both reloads the same register and make sure the reg
1181 // isn't clobbered in between if at all possible.
1182 assert(LastReload->beginNumber() < ReloadIdx);
1183 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1185 LastReloadMBB = ReloadMBB;
1186 LastReload = ReloadLi;
1187 LastReloadSS = ReloadSS;
1189 unhandled_.push(ReloadLi);
1196 // Push the current interval back to unhandled since we are going
1197 // to re-run at least this iteration. Since we didn't modify it it
1198 // should go back right in the front of the list
1199 unhandled_.push(cur);
1201 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1202 "did not choose a register to spill?");
1204 // We spill all intervals aliasing the register with
1205 // minimum weight, rollback to the interval with the earliest
1206 // start point and let the linear scan algorithm run again
1207 SmallVector<LiveInterval*, 8> spillIs;
1209 // Determine which intervals have to be spilled.
1210 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1212 // Set of spilled vregs (used later to rollback properly)
1213 SmallSet<unsigned, 8> spilled;
1215 // The earliest start of a Spilled interval indicates up to where
1216 // in handled we need to roll back
1218 LiveInterval *earliestStartInterval = cur;
1220 // Spill live intervals of virtual regs mapped to the physical register we
1221 // want to clear (and its aliases). We only spill those that overlap with the
1222 // current interval as the rest do not affect its allocation. we also keep
1223 // track of the earliest start of all spilled live intervals since this will
1224 // mark our rollback point.
1225 std::vector<LiveInterval*> added;
1226 while (!spillIs.empty()) {
1227 bool epicFail = false;
1228 LiveInterval *sli = spillIs.back();
1230 DOUT << "\t\t\tspilling(a): " << *sli << '\n';
1231 earliestStartInterval =
1232 (earliestStartInterval->beginNumber() < sli->beginNumber()) ?
1233 earliestStartInterval : sli;
1235 std::vector<LiveInterval*> newIs;
1236 if (!NewSpillFramework) {
1237 newIs = li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_);
1239 newIs = spiller_->spill(sli);
1241 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1242 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
1243 spilled.insert(sli->reg);
1250 unsigned earliestStart = earliestStartInterval->beginNumber();
1252 DOUT << "\t\trolling back to: " << earliestStart << '\n';
1254 // Scan handled in reverse order up to the earliest start of a
1255 // spilled live interval and undo each one, restoring the state of
1257 while (!handled_.empty()) {
1258 LiveInterval* i = handled_.back();
1259 // If this interval starts before t we are done.
1260 if (i->beginNumber() < earliestStart)
1262 DOUT << "\t\t\tundo changes for: " << *i << '\n';
1263 handled_.pop_back();
1265 // When undoing a live interval allocation we must know if it is active or
1266 // inactive to properly update regUse_ and the VirtRegMap.
1267 IntervalPtrs::iterator it;
1268 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1270 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1271 if (!spilled.count(i->reg))
1273 delRegUse(vrm_->getPhys(i->reg));
1274 vrm_->clearVirt(i->reg);
1275 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1276 inactive_.erase(it);
1277 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1278 if (!spilled.count(i->reg))
1280 vrm_->clearVirt(i->reg);
1282 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1283 "Can only allocate virtual registers!");
1284 vrm_->clearVirt(i->reg);
1288 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1289 if (ii == DowngradeMap.end())
1290 // It interval has a preference, it must be defined by a copy. Clear the
1291 // preference now since the source interval allocation may have been
1295 UpgradeRegister(ii->second);
1299 // Rewind the iterators in the active, inactive, and fixed lists back to the
1300 // point we reverted to.
1301 RevertVectorIteratorsTo(active_, earliestStart);
1302 RevertVectorIteratorsTo(inactive_, earliestStart);
1303 RevertVectorIteratorsTo(fixed_, earliestStart);
1305 // Scan the rest and undo each interval that expired after t and
1306 // insert it in active (the next iteration of the algorithm will
1307 // put it in inactive if required)
1308 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1309 LiveInterval *HI = handled_[i];
1310 if (!HI->expiredAt(earliestStart) &&
1311 HI->expiredAt(cur->beginNumber())) {
1312 DOUT << "\t\t\tundo changes for: " << *HI << '\n';
1313 active_.push_back(std::make_pair(HI, HI->begin()));
1314 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1315 addRegUse(vrm_->getPhys(HI->reg));
1319 // Merge added with unhandled.
1320 // This also update the NextReloadMap. That is, it adds mapping from a
1321 // register defined by a reload from SS to the next reload from SS in the
1322 // same basic block.
1323 MachineBasicBlock *LastReloadMBB = 0;
1324 LiveInterval *LastReload = 0;
1325 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1326 std::sort(added.begin(), added.end(), LISorter());
1327 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1328 LiveInterval *ReloadLi = added[i];
1329 if (ReloadLi->weight == HUGE_VALF &&
1330 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1331 unsigned ReloadIdx = ReloadLi->beginNumber();
1332 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1333 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1334 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1335 // Last reload of same SS is in the same MBB. We want to try to
1336 // allocate both reloads the same register and make sure the reg
1337 // isn't clobbered in between if at all possible.
1338 assert(LastReload->beginNumber() < ReloadIdx);
1339 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1341 LastReloadMBB = ReloadMBB;
1342 LastReload = ReloadLi;
1343 LastReloadSS = ReloadSS;
1345 unhandled_.push(ReloadLi);
1349 unsigned RALinScan::getFreePhysReg(const TargetRegisterClass *RC,
1350 unsigned MaxInactiveCount,
1351 SmallVector<unsigned, 256> &inactiveCounts,
1353 unsigned FreeReg = 0;
1354 unsigned FreeRegInactiveCount = 0;
1356 TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
1357 TargetRegisterClass::iterator E = RC->allocation_order_end(*mf_);
1358 assert(I != E && "No allocatable register in this register class!");
1360 // Scan for the first available register.
1361 for (; I != E; ++I) {
1363 // Ignore "downgraded" registers.
1364 if (SkipDGRegs && DowngradedRegs.count(Reg))
1366 if (isRegAvail(Reg)) {
1368 if (FreeReg < inactiveCounts.size())
1369 FreeRegInactiveCount = inactiveCounts[FreeReg];
1371 FreeRegInactiveCount = 0;
1376 // If there are no free regs, or if this reg has the max inactive count,
1377 // return this register.
1378 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount)
1381 // Continue scanning the registers, looking for the one with the highest
1382 // inactive count. Alkis found that this reduced register pressure very
1383 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1385 for (; I != E; ++I) {
1387 // Ignore "downgraded" registers.
1388 if (SkipDGRegs && DowngradedRegs.count(Reg))
1390 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1391 FreeRegInactiveCount < inactiveCounts[Reg]) {
1393 FreeRegInactiveCount = inactiveCounts[Reg];
1394 if (FreeRegInactiveCount == MaxInactiveCount)
1395 break; // We found the one with the max inactive count.
1402 /// getFreePhysReg - return a free physical register for this virtual register
1403 /// interval if we have one, otherwise return 0.
1404 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1405 SmallVector<unsigned, 256> inactiveCounts;
1406 unsigned MaxInactiveCount = 0;
1408 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1409 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1411 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1413 unsigned reg = i->first->reg;
1414 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1415 "Can only allocate virtual registers!");
1417 // If this is not in a related reg class to the register we're allocating,
1419 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1420 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1421 reg = vrm_->getPhys(reg);
1422 if (inactiveCounts.size() <= reg)
1423 inactiveCounts.resize(reg+1);
1424 ++inactiveCounts[reg];
1425 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1429 // If copy coalescer has assigned a "preferred" register, check if it's
1431 if (cur->preference) {
1432 DOUT << "(preferred: " << tri_->getName(cur->preference) << ") ";
1433 if (isRegAvail(cur->preference) &&
1434 RC->contains(cur->preference))
1435 return cur->preference;
1438 if (!DowngradedRegs.empty()) {
1439 unsigned FreeReg = getFreePhysReg(RC, MaxInactiveCount, inactiveCounts,
1444 return getFreePhysReg(RC, MaxInactiveCount, inactiveCounts, false);
1447 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1448 return new RALinScan();