1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/LiveStackAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegAllocRegistry.h"
27 #include "llvm/CodeGen/RegisterCoalescer.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/ADT/EquivalenceClasses.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/Compiler.h"
46 STATISTIC(NumIters , "Number of iterations performed");
47 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
48 STATISTIC(NumCoalesce, "Number of copies coalesced");
49 STATISTIC(NumDowngrade, "Number of registers downgraded");
52 NewHeuristic("new-spilling-heuristic",
53 cl::desc("Use new spilling heuristic"),
54 cl::init(false), cl::Hidden);
57 PreSplitIntervals("pre-alloc-split",
58 cl::desc("Pre-register allocation live interval splitting"),
59 cl::init(false), cl::Hidden);
62 NewSpillFramework("new-spill-framework",
63 cl::desc("New spilling framework"),
64 cl::init(false), cl::Hidden);
66 static RegisterRegAlloc
67 linearscanRegAlloc("linearscan", "linear scan register allocator",
68 createLinearScanRegisterAllocator);
71 struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
73 RALinScan() : MachineFunctionPass(&ID) {}
75 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
76 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
78 /// RelatedRegClasses - This structure is built the first time a function is
79 /// compiled, and keeps track of which register classes have registers that
80 /// belong to multiple classes or have aliases that are in other classes.
81 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
82 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
84 // NextReloadMap - For each register in the map, it maps to the another
85 // register which is defined by a reload from the same stack slot and
86 // both reloads are in the same basic block.
87 DenseMap<unsigned, unsigned> NextReloadMap;
89 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
90 // un-favored for allocation.
91 SmallSet<unsigned, 8> DowngradedRegs;
93 // DowngradeMap - A map from virtual registers to physical registers being
94 // downgraded for the virtual registers.
95 DenseMap<unsigned, unsigned> DowngradeMap;
98 MachineRegisterInfo* mri_;
99 const TargetMachine* tm_;
100 const TargetRegisterInfo* tri_;
101 const TargetInstrInfo* tii_;
102 BitVector allocatableRegs_;
105 const MachineLoopInfo *loopInfo;
107 /// handled_ - Intervals are added to the handled_ set in the order of their
108 /// start value. This is uses for backtracking.
109 std::vector<LiveInterval*> handled_;
111 /// fixed_ - Intervals that correspond to machine registers.
115 /// active_ - Intervals that are currently being processed, and which have a
116 /// live range active for the current point.
117 IntervalPtrs active_;
119 /// inactive_ - Intervals that are currently being processed, but which have
120 /// a hold at the current point.
121 IntervalPtrs inactive_;
123 typedef std::priority_queue<LiveInterval*,
124 SmallVector<LiveInterval*, 64>,
125 greater_ptr<LiveInterval> > IntervalHeap;
126 IntervalHeap unhandled_;
128 /// regUse_ - Tracks register usage.
129 SmallVector<unsigned, 32> regUse_;
130 SmallVector<unsigned, 32> regUseBackUp_;
132 /// vrm_ - Tracks register assignments.
135 std::auto_ptr<VirtRegRewriter> rewriter_;
137 std::auto_ptr<Spiller> spiller_;
140 virtual const char* getPassName() const {
141 return "Linear Scan Register Allocator";
144 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
145 AU.addRequired<LiveIntervals>();
147 AU.addRequiredID(StrongPHIEliminationID);
148 // Make sure PassManager knows which analyses to make available
149 // to coalescing and which analyses coalescing invalidates.
150 AU.addRequiredTransitive<RegisterCoalescer>();
151 if (PreSplitIntervals)
152 AU.addRequiredID(PreAllocSplittingID);
153 AU.addRequired<LiveStacks>();
154 AU.addPreserved<LiveStacks>();
155 AU.addRequired<MachineLoopInfo>();
156 AU.addPreserved<MachineLoopInfo>();
157 AU.addRequired<VirtRegMap>();
158 AU.addPreserved<VirtRegMap>();
159 AU.addPreservedID(MachineDominatorsID);
160 MachineFunctionPass::getAnalysisUsage(AU);
163 /// runOnMachineFunction - register allocate the whole function
164 bool runOnMachineFunction(MachineFunction&);
167 /// linearScan - the linear scan algorithm
170 /// initIntervalSets - initialize the interval sets.
172 void initIntervalSets();
174 /// processActiveIntervals - expire old intervals and move non-overlapping
175 /// ones to the inactive list.
176 void processActiveIntervals(unsigned CurPoint);
178 /// processInactiveIntervals - expire old intervals and move overlapping
179 /// ones to the active list.
180 void processInactiveIntervals(unsigned CurPoint);
182 /// hasNextReloadInterval - Return the next liveinterval that's being
183 /// defined by a reload from the same SS as the specified one.
184 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
186 /// DowngradeRegister - Downgrade a register for allocation.
187 void DowngradeRegister(LiveInterval *li, unsigned Reg);
189 /// UpgradeRegister - Upgrade a register for allocation.
190 void UpgradeRegister(unsigned Reg);
192 /// assignRegOrStackSlotAtInterval - assign a register if one
193 /// is available, or spill.
194 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
196 void updateSpillWeights(std::vector<float> &Weights,
197 unsigned reg, float weight,
198 const TargetRegisterClass *RC);
200 /// findIntervalsToSpill - Determine the intervals to spill for the
201 /// specified interval. It's passed the physical registers whose spill
202 /// weight is the lowest among all the registers whose live intervals
203 /// conflict with the interval.
204 void findIntervalsToSpill(LiveInterval *cur,
205 std::vector<std::pair<unsigned,float> > &Candidates,
207 SmallVector<LiveInterval*, 8> &SpillIntervals);
209 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
210 /// try allocate the definition the same register as the source register
211 /// if the register is not defined during live time of the interval. This
212 /// eliminate a copy. This is used to coalesce copies which were not
213 /// coalesced away before allocation either due to dest and src being in
214 /// different register classes or because the coalescer was overly
216 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
219 /// Register usage / availability tracking helpers.
223 regUse_.resize(tri_->getNumRegs(), 0);
224 regUseBackUp_.resize(tri_->getNumRegs(), 0);
227 void finalizeRegUses() {
229 // Verify all the registers are "freed".
231 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
232 if (regUse_[i] != 0) {
233 cerr << tri_->getName(i) << " is still in use!\n";
241 regUseBackUp_.clear();
244 void addRegUse(unsigned physReg) {
245 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
246 "should be physical register!");
248 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
252 void delRegUse(unsigned physReg) {
253 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
254 "should be physical register!");
255 assert(regUse_[physReg] != 0);
257 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
258 assert(regUse_[*as] != 0);
263 bool isRegAvail(unsigned physReg) const {
264 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
265 "should be physical register!");
266 return regUse_[physReg] == 0;
269 void backUpRegUses() {
270 regUseBackUp_ = regUse_;
273 void restoreRegUses() {
274 regUse_ = regUseBackUp_;
278 /// Register handling helpers.
281 /// getFreePhysReg - return a free physical register for this virtual
282 /// register interval if we have one, otherwise return 0.
283 unsigned getFreePhysReg(LiveInterval* cur);
284 unsigned getFreePhysReg(LiveInterval* cur,
285 const TargetRegisterClass *RC,
286 unsigned MaxInactiveCount,
287 SmallVector<unsigned, 256> &inactiveCounts,
290 /// assignVirt2StackSlot - assigns this virtual register to a
291 /// stack slot. returns the stack slot
292 int assignVirt2StackSlot(unsigned virtReg);
294 void ComputeRelatedRegClasses();
296 template <typename ItTy>
297 void printIntervals(const char* const str, ItTy i, ItTy e) const {
298 if (str) DOUT << str << " intervals:\n";
299 for (; i != e; ++i) {
300 DOUT << "\t" << *i->first << " -> ";
301 unsigned reg = i->first->reg;
302 if (TargetRegisterInfo::isVirtualRegister(reg)) {
303 reg = vrm_->getPhys(reg);
305 DOUT << tri_->getName(reg) << '\n';
309 char RALinScan::ID = 0;
312 static RegisterPass<RALinScan>
313 X("linearscan-regalloc", "Linear Scan Register Allocator");
315 void RALinScan::ComputeRelatedRegClasses() {
316 // First pass, add all reg classes to the union, and determine at least one
317 // reg class that each register is in.
318 bool HasAliases = false;
319 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
320 E = tri_->regclass_end(); RCI != E; ++RCI) {
321 RelatedRegClasses.insert(*RCI);
322 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
324 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
326 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
328 // Already processed this register. Just make sure we know that
329 // multiple register classes share a register.
330 RelatedRegClasses.unionSets(PRC, *RCI);
337 // Second pass, now that we know conservatively what register classes each reg
338 // belongs to, add info about aliases. We don't need to do this for targets
339 // without register aliases.
341 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
342 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
344 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
345 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
348 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
349 /// try allocate the definition the same register as the source register
350 /// if the register is not defined during live time of the interval. This
351 /// eliminate a copy. This is used to coalesce copies which were not
352 /// coalesced away before allocation either due to dest and src being in
353 /// different register classes or because the coalescer was overly
355 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
356 unsigned Preference = vrm_->getRegAllocPref(cur.reg);
357 if ((Preference && Preference == Reg) || !cur.containsOneValue())
360 VNInfo *vni = cur.begin()->valno;
361 if (!vni->def || vni->isUnused() || !vni->isDefAccurate())
363 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
364 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg, PhysReg;
366 !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
369 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
370 if (!vrm_->isAssignedReg(SrcReg))
372 PhysReg = vrm_->getPhys(SrcReg);
377 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
378 if (!RC->contains(PhysReg))
382 if (!li_->conflictsWithPhysRegDef(cur, *vrm_, PhysReg)) {
383 DOUT << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg)
385 vrm_->clearVirt(cur.reg);
386 vrm_->assignVirt2Phys(cur.reg, PhysReg);
388 // Remove unnecessary kills since a copy does not clobber the register.
389 if (li_->hasInterval(SrcReg)) {
390 LiveInterval &SrcLI = li_->getInterval(SrcReg);
391 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(cur.reg),
392 E = mri_->reg_end(); I != E; ++I) {
393 MachineOperand &O = I.getOperand();
394 if (!O.isUse() || !O.isKill())
396 MachineInstr *MI = &*I;
397 if (SrcLI.liveAt(li_->getDefIndex(li_->getInstructionIndex(MI))))
409 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
411 mri_ = &fn.getRegInfo();
412 tm_ = &fn.getTarget();
413 tri_ = tm_->getRegisterInfo();
414 tii_ = tm_->getInstrInfo();
415 allocatableRegs_ = tri_->getAllocatableSet(fn);
416 li_ = &getAnalysis<LiveIntervals>();
417 ls_ = &getAnalysis<LiveStacks>();
418 loopInfo = &getAnalysis<MachineLoopInfo>();
420 // We don't run the coalescer here because we have no reason to
421 // interact with it. If the coalescer requires interaction, it
422 // won't do anything. If it doesn't require interaction, we assume
423 // it was run as a separate pass.
425 // If this is the first function compiled, compute the related reg classes.
426 if (RelatedRegClasses.empty())
427 ComputeRelatedRegClasses();
429 // Also resize register usage trackers.
432 vrm_ = &getAnalysis<VirtRegMap>();
433 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
435 if (NewSpillFramework) {
436 spiller_.reset(createSpiller(mf_, li_, ls_, vrm_));
443 // Rewrite spill code and update the PhysRegsUsed set.
444 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
446 assert(unhandled_.empty() && "Unhandled live intervals remain!");
454 NextReloadMap.clear();
455 DowngradedRegs.clear();
456 DowngradeMap.clear();
462 /// initIntervalSets - initialize the interval sets.
464 void RALinScan::initIntervalSets()
466 assert(unhandled_.empty() && fixed_.empty() &&
467 active_.empty() && inactive_.empty() &&
468 "interval sets should be empty on initialization");
470 handled_.reserve(li_->getNumIntervals());
472 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
473 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
474 mri_->setPhysRegUsed(i->second->reg);
475 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
477 unhandled_.push(i->second);
481 void RALinScan::linearScan()
483 // linear scan algorithm
484 DOUT << "********** LINEAR SCAN **********\n";
485 DOUT << "********** Function: " << mf_->getFunction()->getName() << '\n';
487 DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end()));
489 while (!unhandled_.empty()) {
490 // pick the interval with the earliest start point
491 LiveInterval* cur = unhandled_.top();
494 DOUT << "\n*** CURRENT ***: " << *cur << '\n';
497 processActiveIntervals(cur->beginNumber());
498 processInactiveIntervals(cur->beginNumber());
500 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
501 "Can only allocate virtual registers!");
504 // Allocating a virtual register. try to find a free
505 // physical register or spill an interval (possibly this one) in order to
507 assignRegOrStackSlotAtInterval(cur);
509 DEBUG(printIntervals("active", active_.begin(), active_.end()));
510 DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
513 // Expire any remaining active intervals
514 while (!active_.empty()) {
515 IntervalPtr &IP = active_.back();
516 unsigned reg = IP.first->reg;
517 DOUT << "\tinterval " << *IP.first << " expired\n";
518 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
519 "Can only allocate virtual registers!");
520 reg = vrm_->getPhys(reg);
525 // Expire any remaining inactive intervals
526 DEBUG(for (IntervalPtrs::reverse_iterator
527 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
528 DOUT << "\tinterval " << *i->first << " expired\n");
531 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
532 MachineFunction::iterator EntryMBB = mf_->begin();
533 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
534 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
535 LiveInterval &cur = *i->second;
537 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
540 else if (vrm_->isAssignedReg(cur.reg))
541 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
544 // Ignore splited live intervals.
545 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
548 // A register defined by an implicit_def can be liveout the def BB and livein
549 // to a use BB. Add it to the livein set of the use BB's.
550 if (!isPhys && cur.empty()) {
551 if (MachineInstr *DefMI = mri_->getVRegDef(cur.reg)) {
552 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
553 MachineBasicBlock *DefMBB = DefMI->getParent();
554 SmallPtrSet<MachineBasicBlock*, 4> Seen;
556 for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(cur.reg),
557 re = mri_->reg_end(); ri != re; ++ri) {
558 MachineInstr *UseMI = &*ri;
559 MachineBasicBlock *UseMBB = UseMI->getParent();
560 if (Seen.insert(UseMBB)) {
561 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
562 "Adding a virtual register to livein set?");
563 UseMBB->addLiveIn(Reg);
568 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
570 const LiveRange &LR = *I;
571 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
572 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
573 if (LiveInMBBs[i] != EntryMBB) {
574 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
575 "Adding a virtual register to livein set?");
576 LiveInMBBs[i]->addLiveIn(Reg);
585 // Look for physical registers that end up not being allocated even though
586 // register allocator had to spill other registers in its register class.
587 if (ls_->getNumIntervals() == 0)
589 if (!vrm_->FindUnusedRegisters(li_))
593 /// processActiveIntervals - expire old intervals and move non-overlapping ones
594 /// to the inactive list.
595 void RALinScan::processActiveIntervals(unsigned CurPoint)
597 DOUT << "\tprocessing active intervals:\n";
599 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
600 LiveInterval *Interval = active_[i].first;
601 LiveInterval::iterator IntervalPos = active_[i].second;
602 unsigned reg = Interval->reg;
604 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
606 if (IntervalPos == Interval->end()) { // Remove expired intervals.
607 DOUT << "\t\tinterval " << *Interval << " expired\n";
608 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
609 "Can only allocate virtual registers!");
610 reg = vrm_->getPhys(reg);
613 // Pop off the end of the list.
614 active_[i] = active_.back();
618 } else if (IntervalPos->start > CurPoint) {
619 // Move inactive intervals to inactive list.
620 DOUT << "\t\tinterval " << *Interval << " inactive\n";
621 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
622 "Can only allocate virtual registers!");
623 reg = vrm_->getPhys(reg);
626 inactive_.push_back(std::make_pair(Interval, IntervalPos));
628 // Pop off the end of the list.
629 active_[i] = active_.back();
633 // Otherwise, just update the iterator position.
634 active_[i].second = IntervalPos;
639 /// processInactiveIntervals - expire old intervals and move overlapping
640 /// ones to the active list.
641 void RALinScan::processInactiveIntervals(unsigned CurPoint)
643 DOUT << "\tprocessing inactive intervals:\n";
645 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
646 LiveInterval *Interval = inactive_[i].first;
647 LiveInterval::iterator IntervalPos = inactive_[i].second;
648 unsigned reg = Interval->reg;
650 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
652 if (IntervalPos == Interval->end()) { // remove expired intervals.
653 DOUT << "\t\tinterval " << *Interval << " expired\n";
655 // Pop off the end of the list.
656 inactive_[i] = inactive_.back();
657 inactive_.pop_back();
659 } else if (IntervalPos->start <= CurPoint) {
660 // move re-activated intervals in active list
661 DOUT << "\t\tinterval " << *Interval << " active\n";
662 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
663 "Can only allocate virtual registers!");
664 reg = vrm_->getPhys(reg);
667 active_.push_back(std::make_pair(Interval, IntervalPos));
669 // Pop off the end of the list.
670 inactive_[i] = inactive_.back();
671 inactive_.pop_back();
674 // Otherwise, just update the iterator position.
675 inactive_[i].second = IntervalPos;
680 /// updateSpillWeights - updates the spill weights of the specifed physical
681 /// register and its weight.
682 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
683 unsigned reg, float weight,
684 const TargetRegisterClass *RC) {
685 SmallSet<unsigned, 4> Processed;
686 SmallSet<unsigned, 4> SuperAdded;
687 SmallVector<unsigned, 4> Supers;
688 Weights[reg] += weight;
689 Processed.insert(reg);
690 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
691 Weights[*as] += weight;
692 Processed.insert(*as);
693 if (tri_->isSubRegister(*as, reg) &&
694 SuperAdded.insert(*as) &&
696 Supers.push_back(*as);
700 // If the alias is a super-register, and the super-register is in the
701 // register class we are trying to allocate. Then add the weight to all
702 // sub-registers of the super-register even if they are not aliases.
703 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
704 // bl should get the same spill weight otherwise it will be choosen
705 // as a spill candidate since spilling bh doesn't make ebx available.
706 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
707 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
708 if (!Processed.count(*sr))
709 Weights[*sr] += weight;
714 RALinScan::IntervalPtrs::iterator
715 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
716 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
718 if (I->first == LI) return I;
722 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
723 for (unsigned i = 0, e = V.size(); i != e; ++i) {
724 RALinScan::IntervalPtr &IP = V[i];
725 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
727 if (I != IP.first->begin()) --I;
732 /// addStackInterval - Create a LiveInterval for stack if the specified live
733 /// interval has been spilled.
734 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
736 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
737 int SS = vrm_.getStackSlot(cur->reg);
738 if (SS == VirtRegMap::NO_STACK_SLOT)
741 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
742 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
745 if (SI.hasAtLeastOneValue())
746 VNI = SI.getValNumInfo(0);
748 VNI = SI.getNextValue(0, 0, false, ls_->getVNInfoAllocator());
750 LiveInterval &RI = li_->getInterval(cur->reg);
751 // FIXME: This may be overly conservative.
752 SI.MergeRangesInAsValue(RI, VNI);
755 /// getConflictWeight - Return the number of conflicts between cur
756 /// live interval and defs and uses of Reg weighted by loop depthes.
758 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
759 MachineRegisterInfo *mri_,
760 const MachineLoopInfo *loopInfo) {
762 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
763 E = mri_->reg_end(); I != E; ++I) {
764 MachineInstr *MI = &*I;
765 if (cur->liveAt(li_->getInstructionIndex(MI))) {
766 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
767 Conflicts += powf(10.0f, (float)loopDepth);
773 /// findIntervalsToSpill - Determine the intervals to spill for the
774 /// specified interval. It's passed the physical registers whose spill
775 /// weight is the lowest among all the registers whose live intervals
776 /// conflict with the interval.
777 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
778 std::vector<std::pair<unsigned,float> > &Candidates,
780 SmallVector<LiveInterval*, 8> &SpillIntervals) {
781 // We have figured out the *best* register to spill. But there are other
782 // registers that are pretty good as well (spill weight within 3%). Spill
783 // the one that has fewest defs and uses that conflict with cur.
784 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
785 SmallVector<LiveInterval*, 8> SLIs[3];
787 DOUT << "\tConsidering " << NumCands << " candidates: ";
788 DEBUG(for (unsigned i = 0; i != NumCands; ++i)
789 DOUT << tri_->getName(Candidates[i].first) << " ";
792 // Calculate the number of conflicts of each candidate.
793 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
794 unsigned Reg = i->first->reg;
795 unsigned PhysReg = vrm_->getPhys(Reg);
796 if (!cur->overlapsFrom(*i->first, i->second))
798 for (unsigned j = 0; j < NumCands; ++j) {
799 unsigned Candidate = Candidates[j].first;
800 if (tri_->regsOverlap(PhysReg, Candidate)) {
802 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
803 SLIs[j].push_back(i->first);
808 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
809 unsigned Reg = i->first->reg;
810 unsigned PhysReg = vrm_->getPhys(Reg);
811 if (!cur->overlapsFrom(*i->first, i->second-1))
813 for (unsigned j = 0; j < NumCands; ++j) {
814 unsigned Candidate = Candidates[j].first;
815 if (tri_->regsOverlap(PhysReg, Candidate)) {
817 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
818 SLIs[j].push_back(i->first);
823 // Which is the best candidate?
824 unsigned BestCandidate = 0;
825 float MinConflicts = Conflicts[0];
826 for (unsigned i = 1; i != NumCands; ++i) {
827 if (Conflicts[i] < MinConflicts) {
829 MinConflicts = Conflicts[i];
833 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
834 std::back_inserter(SpillIntervals));
838 struct WeightCompare {
839 typedef std::pair<unsigned, float> RegWeightPair;
840 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
841 return LHS.second < RHS.second;
846 static bool weightsAreClose(float w1, float w2) {
850 float diff = w1 - w2;
851 if (diff <= 0.02f) // Within 0.02f
853 return (diff / w2) <= 0.05f; // Within 5%.
856 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
857 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
858 if (I == NextReloadMap.end())
860 return &li_->getInterval(I->second);
863 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
864 bool isNew = DowngradedRegs.insert(Reg);
865 isNew = isNew; // Silence compiler warning.
866 assert(isNew && "Multiple reloads holding the same register?");
867 DowngradeMap.insert(std::make_pair(li->reg, Reg));
868 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
869 isNew = DowngradedRegs.insert(*AS);
870 isNew = isNew; // Silence compiler warning.
871 assert(isNew && "Multiple reloads holding the same register?");
872 DowngradeMap.insert(std::make_pair(li->reg, *AS));
877 void RALinScan::UpgradeRegister(unsigned Reg) {
879 DowngradedRegs.erase(Reg);
880 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
881 DowngradedRegs.erase(*AS);
887 bool operator()(LiveInterval* A, LiveInterval* B) {
888 return A->beginNumber() < B->beginNumber();
893 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
895 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
897 DOUT << "\tallocating current interval: ";
899 // This is an implicitly defined live interval, just assign any register.
900 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
902 unsigned physReg = vrm_->getRegAllocPref(cur->reg);
904 physReg = *RC->allocation_order_begin(*mf_);
905 DOUT << tri_->getName(physReg) << '\n';
906 // Note the register is not really in use.
907 vrm_->assignVirt2Phys(cur->reg, physReg);
913 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
914 unsigned StartPosition = cur->beginNumber();
915 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
917 // If start of this live interval is defined by a move instruction and its
918 // source is assigned a physical register that is compatible with the target
919 // register class, then we should try to assign it the same register.
920 // This can happen when the move is from a larger register class to a smaller
921 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
922 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
923 VNInfo *vni = cur->begin()->valno;
924 if (vni->def && !vni->isUnused() && vni->isDefAccurate()) {
925 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
926 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
928 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
930 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
932 else if (vrm_->isAssignedReg(SrcReg))
933 Reg = vrm_->getPhys(SrcReg);
936 Reg = tri_->getSubReg(Reg, SrcSubReg);
938 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
939 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
940 mri_->setRegAllocationHint(cur->reg, 0, Reg);
946 // For every interval in inactive we overlap with, mark the
947 // register as not free and update spill weights.
948 for (IntervalPtrs::const_iterator i = inactive_.begin(),
949 e = inactive_.end(); i != e; ++i) {
950 unsigned Reg = i->first->reg;
951 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
952 "Can only allocate virtual registers!");
953 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
954 // If this is not in a related reg class to the register we're allocating,
956 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
957 cur->overlapsFrom(*i->first, i->second-1)) {
958 Reg = vrm_->getPhys(Reg);
960 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
964 // Speculatively check to see if we can get a register right now. If not,
965 // we know we won't be able to by adding more constraints. If so, we can
966 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
967 // is very bad (it contains all callee clobbered registers for any functions
968 // with a call), so we want to avoid doing that if possible.
969 unsigned physReg = getFreePhysReg(cur);
970 unsigned BestPhysReg = physReg;
972 // We got a register. However, if it's in the fixed_ list, we might
973 // conflict with it. Check to see if we conflict with it or any of its
975 SmallSet<unsigned, 8> RegAliases;
976 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
977 RegAliases.insert(*AS);
979 bool ConflictsWithFixed = false;
980 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
981 IntervalPtr &IP = fixed_[i];
982 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
983 // Okay, this reg is on the fixed list. Check to see if we actually
985 LiveInterval *I = IP.first;
986 if (I->endNumber() > StartPosition) {
987 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
989 if (II != I->begin() && II->start > StartPosition)
991 if (cur->overlapsFrom(*I, II)) {
992 ConflictsWithFixed = true;
999 // Okay, the register picked by our speculative getFreePhysReg call turned
1000 // out to be in use. Actually add all of the conflicting fixed registers to
1001 // regUse_ so we can do an accurate query.
1002 if (ConflictsWithFixed) {
1003 // For every interval in fixed we overlap with, mark the register as not
1004 // free and update spill weights.
1005 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1006 IntervalPtr &IP = fixed_[i];
1007 LiveInterval *I = IP.first;
1009 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
1010 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1011 I->endNumber() > StartPosition) {
1012 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1014 if (II != I->begin() && II->start > StartPosition)
1016 if (cur->overlapsFrom(*I, II)) {
1017 unsigned reg = I->reg;
1019 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1024 // Using the newly updated regUse_ object, which includes conflicts in the
1025 // future, see if there are any registers available.
1026 physReg = getFreePhysReg(cur);
1030 // Restore the physical register tracker, removing information about the
1034 // If we find a free register, we are done: assign this virtual to
1035 // the free physical register and add this interval to the active
1038 DOUT << tri_->getName(physReg) << '\n';
1039 vrm_->assignVirt2Phys(cur->reg, physReg);
1041 active_.push_back(std::make_pair(cur, cur->begin()));
1042 handled_.push_back(cur);
1044 // "Upgrade" the physical register since it has been allocated.
1045 UpgradeRegister(physReg);
1046 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1047 // "Downgrade" physReg to try to keep physReg from being allocated until
1048 // the next reload from the same SS is allocated.
1049 mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
1050 DowngradeRegister(cur, physReg);
1054 DOUT << "no free registers\n";
1056 // Compile the spill weights into an array that is better for scanning.
1057 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1058 for (std::vector<std::pair<unsigned, float> >::iterator
1059 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1060 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1062 // for each interval in active, update spill weights.
1063 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1065 unsigned reg = i->first->reg;
1066 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1067 "Can only allocate virtual registers!");
1068 reg = vrm_->getPhys(reg);
1069 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1072 DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
1074 // Find a register to spill.
1075 float minWeight = HUGE_VALF;
1076 unsigned minReg = 0;
1079 std::vector<std::pair<unsigned,float> > RegsWeights;
1080 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1081 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1082 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1084 float regWeight = SpillWeights[reg];
1085 if (minWeight > regWeight)
1087 RegsWeights.push_back(std::make_pair(reg, regWeight));
1090 // If we didn't find a register that is spillable, try aliases?
1092 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1093 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1095 // No need to worry about if the alias register size < regsize of RC.
1096 // We are going to spill all registers that alias it anyway.
1097 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1098 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1102 // Sort all potential spill candidates by weight.
1103 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare());
1104 minReg = RegsWeights[0].first;
1105 minWeight = RegsWeights[0].second;
1106 if (minWeight == HUGE_VALF) {
1107 // All registers must have inf weight. Just grab one!
1108 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
1109 if (cur->weight == HUGE_VALF ||
1110 li_->getApproximateInstructionCount(*cur) == 0) {
1111 // Spill a physical register around defs and uses.
1112 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1113 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1114 // in fixed_. Reset them.
1115 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1116 IntervalPtr &IP = fixed_[i];
1117 LiveInterval *I = IP.first;
1118 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1119 IP.second = I->advanceTo(I->begin(), StartPosition);
1122 DowngradedRegs.clear();
1123 assignRegOrStackSlotAtInterval(cur);
1125 cerr << "Ran out of registers during register allocation!\n";
1132 // Find up to 3 registers to consider as spill candidates.
1133 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1134 while (LastCandidate > 1) {
1135 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1140 DOUT << "\t\tregister(s) with min weight(s): ";
1141 DEBUG(for (unsigned i = 0; i != LastCandidate; ++i)
1142 DOUT << tri_->getName(RegsWeights[i].first)
1143 << " (" << RegsWeights[i].second << ")\n");
1145 // If the current has the minimum weight, we need to spill it and
1146 // add any added intervals back to unhandled, and restart
1148 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1149 DOUT << "\t\t\tspilling(c): " << *cur << '\n';
1150 SmallVector<LiveInterval*, 8> spillIs;
1151 std::vector<LiveInterval*> added;
1153 if (!NewSpillFramework) {
1154 added = li_->addIntervalsForSpills(*cur, spillIs, loopInfo, *vrm_);
1156 added = spiller_->spill(cur);
1159 std::sort(added.begin(), added.end(), LISorter());
1160 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1162 return; // Early exit if all spills were folded.
1164 // Merge added with unhandled. Note that we have already sorted
1165 // intervals returned by addIntervalsForSpills by their starting
1167 // This also update the NextReloadMap. That is, it adds mapping from a
1168 // register defined by a reload from SS to the next reload from SS in the
1169 // same basic block.
1170 MachineBasicBlock *LastReloadMBB = 0;
1171 LiveInterval *LastReload = 0;
1172 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1173 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1174 LiveInterval *ReloadLi = added[i];
1175 if (ReloadLi->weight == HUGE_VALF &&
1176 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1177 unsigned ReloadIdx = ReloadLi->beginNumber();
1178 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1179 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1180 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1181 // Last reload of same SS is in the same MBB. We want to try to
1182 // allocate both reloads the same register and make sure the reg
1183 // isn't clobbered in between if at all possible.
1184 assert(LastReload->beginNumber() < ReloadIdx);
1185 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1187 LastReloadMBB = ReloadMBB;
1188 LastReload = ReloadLi;
1189 LastReloadSS = ReloadSS;
1191 unhandled_.push(ReloadLi);
1198 // Push the current interval back to unhandled since we are going
1199 // to re-run at least this iteration. Since we didn't modify it it
1200 // should go back right in the front of the list
1201 unhandled_.push(cur);
1203 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1204 "did not choose a register to spill?");
1206 // We spill all intervals aliasing the register with
1207 // minimum weight, rollback to the interval with the earliest
1208 // start point and let the linear scan algorithm run again
1209 SmallVector<LiveInterval*, 8> spillIs;
1211 // Determine which intervals have to be spilled.
1212 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1214 // Set of spilled vregs (used later to rollback properly)
1215 SmallSet<unsigned, 8> spilled;
1217 // The earliest start of a Spilled interval indicates up to where
1218 // in handled we need to roll back
1220 LiveInterval *earliestStartInterval = cur;
1222 // Spill live intervals of virtual regs mapped to the physical register we
1223 // want to clear (and its aliases). We only spill those that overlap with the
1224 // current interval as the rest do not affect its allocation. we also keep
1225 // track of the earliest start of all spilled live intervals since this will
1226 // mark our rollback point.
1227 std::vector<LiveInterval*> added;
1228 while (!spillIs.empty()) {
1229 bool epicFail = false;
1230 LiveInterval *sli = spillIs.back();
1232 DOUT << "\t\t\tspilling(a): " << *sli << '\n';
1233 earliestStartInterval =
1234 (earliestStartInterval->beginNumber() < sli->beginNumber()) ?
1235 earliestStartInterval : sli;
1237 std::vector<LiveInterval*> newIs;
1238 if (!NewSpillFramework) {
1239 newIs = li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_);
1241 newIs = spiller_->spill(sli);
1243 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1244 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
1245 spilled.insert(sli->reg);
1252 unsigned earliestStart = earliestStartInterval->beginNumber();
1254 DOUT << "\t\trolling back to: " << earliestStart << '\n';
1256 // Scan handled in reverse order up to the earliest start of a
1257 // spilled live interval and undo each one, restoring the state of
1259 while (!handled_.empty()) {
1260 LiveInterval* i = handled_.back();
1261 // If this interval starts before t we are done.
1262 if (i->beginNumber() < earliestStart)
1264 DOUT << "\t\t\tundo changes for: " << *i << '\n';
1265 handled_.pop_back();
1267 // When undoing a live interval allocation we must know if it is active or
1268 // inactive to properly update regUse_ and the VirtRegMap.
1269 IntervalPtrs::iterator it;
1270 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1272 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1273 if (!spilled.count(i->reg))
1275 delRegUse(vrm_->getPhys(i->reg));
1276 vrm_->clearVirt(i->reg);
1277 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1278 inactive_.erase(it);
1279 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1280 if (!spilled.count(i->reg))
1282 vrm_->clearVirt(i->reg);
1284 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1285 "Can only allocate virtual registers!");
1286 vrm_->clearVirt(i->reg);
1290 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1291 if (ii == DowngradeMap.end())
1292 // It interval has a preference, it must be defined by a copy. Clear the
1293 // preference now since the source interval allocation may have been
1295 mri_->setRegAllocationHint(i->reg, 0, 0);
1297 UpgradeRegister(ii->second);
1301 // Rewind the iterators in the active, inactive, and fixed lists back to the
1302 // point we reverted to.
1303 RevertVectorIteratorsTo(active_, earliestStart);
1304 RevertVectorIteratorsTo(inactive_, earliestStart);
1305 RevertVectorIteratorsTo(fixed_, earliestStart);
1307 // Scan the rest and undo each interval that expired after t and
1308 // insert it in active (the next iteration of the algorithm will
1309 // put it in inactive if required)
1310 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1311 LiveInterval *HI = handled_[i];
1312 if (!HI->expiredAt(earliestStart) &&
1313 HI->expiredAt(cur->beginNumber())) {
1314 DOUT << "\t\t\tundo changes for: " << *HI << '\n';
1315 active_.push_back(std::make_pair(HI, HI->begin()));
1316 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1317 addRegUse(vrm_->getPhys(HI->reg));
1321 // Merge added with unhandled.
1322 // This also update the NextReloadMap. That is, it adds mapping from a
1323 // register defined by a reload from SS to the next reload from SS in the
1324 // same basic block.
1325 MachineBasicBlock *LastReloadMBB = 0;
1326 LiveInterval *LastReload = 0;
1327 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1328 std::sort(added.begin(), added.end(), LISorter());
1329 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1330 LiveInterval *ReloadLi = added[i];
1331 if (ReloadLi->weight == HUGE_VALF &&
1332 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1333 unsigned ReloadIdx = ReloadLi->beginNumber();
1334 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1335 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1336 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1337 // Last reload of same SS is in the same MBB. We want to try to
1338 // allocate both reloads the same register and make sure the reg
1339 // isn't clobbered in between if at all possible.
1340 assert(LastReload->beginNumber() < ReloadIdx);
1341 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1343 LastReloadMBB = ReloadMBB;
1344 LastReload = ReloadLi;
1345 LastReloadSS = ReloadSS;
1347 unhandled_.push(ReloadLi);
1351 unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
1352 const TargetRegisterClass *RC,
1353 unsigned MaxInactiveCount,
1354 SmallVector<unsigned, 256> &inactiveCounts,
1356 unsigned FreeReg = 0;
1357 unsigned FreeRegInactiveCount = 0;
1359 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
1360 // Resolve second part of the hint (if possible) given the current allocation.
1361 unsigned physReg = Hint.second;
1363 TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
1364 physReg = vrm_->getPhys(physReg);
1366 TargetRegisterClass::iterator I, E;
1367 tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
1368 assert(I != E && "No allocatable register in this register class!");
1370 // Scan for the first available register.
1371 for (; I != E; ++I) {
1373 // Ignore "downgraded" registers.
1374 if (SkipDGRegs && DowngradedRegs.count(Reg))
1376 if (isRegAvail(Reg)) {
1378 if (FreeReg < inactiveCounts.size())
1379 FreeRegInactiveCount = inactiveCounts[FreeReg];
1381 FreeRegInactiveCount = 0;
1386 // If there are no free regs, or if this reg has the max inactive count,
1387 // return this register.
1388 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount)
1391 // Continue scanning the registers, looking for the one with the highest
1392 // inactive count. Alkis found that this reduced register pressure very
1393 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1395 for (; I != E; ++I) {
1397 // Ignore "downgraded" registers.
1398 if (SkipDGRegs && DowngradedRegs.count(Reg))
1400 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1401 FreeRegInactiveCount < inactiveCounts[Reg]) {
1403 FreeRegInactiveCount = inactiveCounts[Reg];
1404 if (FreeRegInactiveCount == MaxInactiveCount)
1405 break; // We found the one with the max inactive count.
1412 /// getFreePhysReg - return a free physical register for this virtual register
1413 /// interval if we have one, otherwise return 0.
1414 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1415 SmallVector<unsigned, 256> inactiveCounts;
1416 unsigned MaxInactiveCount = 0;
1418 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1419 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1421 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1423 unsigned reg = i->first->reg;
1424 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1425 "Can only allocate virtual registers!");
1427 // If this is not in a related reg class to the register we're allocating,
1429 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1430 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1431 reg = vrm_->getPhys(reg);
1432 if (inactiveCounts.size() <= reg)
1433 inactiveCounts.resize(reg+1);
1434 ++inactiveCounts[reg];
1435 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1439 // If copy coalescer has assigned a "preferred" register, check if it's
1441 unsigned Preference = vrm_->getRegAllocPref(cur->reg);
1443 DOUT << "(preferred: " << tri_->getName(Preference) << ") ";
1444 if (isRegAvail(Preference) &&
1445 RC->contains(Preference))
1449 if (!DowngradedRegs.empty()) {
1450 unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
1455 return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
1458 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1459 return new RALinScan();