lib/CodeGen/RegAllocGreedy.cpp

   1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the RAGreedy function pass for register allocation in
  11 // optimized builds.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "regalloc"
  16 #include "LiveIntervalUnion.h"
  17 #include "RegAllocBase.h"
  18 #include "Spiller.h"
  19 #include "VirtRegMap.h"
  20 #include "VirtRegRewriter.h"
  21 #include "llvm/ADT/OwningPtr.h"
  22 #include "llvm/Analysis/AliasAnalysis.h"
  23 #include "llvm/Function.h"
  24 #include "llvm/PassAnalysisSupport.h"
  25 #include "llvm/CodeGen/CalcSpillWeights.h"
  26 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
  27 #include "llvm/CodeGen/LiveStackAnalysis.h"
  28 #include "llvm/CodeGen/MachineFunctionPass.h"
  29 #include "llvm/CodeGen/MachineInstr.h"
  30 #include "llvm/CodeGen/MachineLoopInfo.h"
  31 #include "llvm/CodeGen/MachineRegisterInfo.h"
  32 #include "llvm/CodeGen/Passes.h"
  33 #include "llvm/CodeGen/RegAllocRegistry.h"
  34 #include "llvm/CodeGen/RegisterCoalescer.h"
  35 #include "llvm/Target/TargetMachine.h"
  36 #include "llvm/Target/TargetOptions.h"
  37 #include "llvm/Target/TargetRegisterInfo.h"
  38 #include "llvm/Support/Debug.h"
  39 #include "llvm/Support/ErrorHandling.h"
  40 #include "llvm/Support/raw_ostream.h"
  41
  42 using namespace llvm;
  43
  44 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
  45                                        createGreedyRegisterAllocator);
  46
  47 namespace {
  48 class RAGreedy : public MachineFunctionPass, public RegAllocBase {
  49   // context
  50   MachineFunction *MF;
  51   const TargetMachine *TM;
  52   MachineRegisterInfo *MRI;
  53
  54   BitVector ReservedRegs;
  55
  56   // analyses
  57   LiveStacks *LS;
  58
  59   // state
  60   std::auto_ptr<Spiller> SpillerInstance;
  61
  62 public:
  63   RAGreedy();
  64
  65   /// Return the pass name.
  66   virtual const char* getPassName() const {
  67     return "Basic Register Allocator";
  68   }
  69
  70   /// RAGreedy analysis usage.
  71   virtual void getAnalysisUsage(AnalysisUsage &AU) const;
  72
  73   virtual void releaseMemory();
  74
  75   virtual Spiller &spiller() { return *SpillerInstance; }
  76
  77   virtual unsigned selectOrSplit(LiveInterval &VirtReg,
  78                                  SmallVectorImpl<LiveInterval*> &SplitVRegs);
  79
  80   /// Perform register allocation.
  81   virtual bool runOnMachineFunction(MachineFunction &mf);
  82
  83   static char ID;
  84 };
  85 } // end anonymous namespace
  86
  87 char RAGreedy::ID = 0;
  88
  89 FunctionPass* llvm::createGreedyRegisterAllocator() {
  90   return new RAGreedy();
  91 }
  92
  93 RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
  94   initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
  95   initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
  96   initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
  97   initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
  98   initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
  99   initializeLiveStacksPass(*PassRegistry::getPassRegistry());
 100   initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
 101   initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
 102   initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
 103 }
 104
 105 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
 106   AU.setPreservesCFG();
 107   AU.addRequired<AliasAnalysis>();
 108   AU.addPreserved<AliasAnalysis>();
 109   AU.addRequired<LiveIntervals>();
 110   AU.addPreserved<SlotIndexes>();
 111   if (StrongPHIElim)
 112     AU.addRequiredID(StrongPHIEliminationID);
 113   AU.addRequiredTransitive<RegisterCoalescer>();
 114   AU.addRequired<CalculateSpillWeights>();
 115   AU.addRequired<LiveStacks>();
 116   AU.addPreserved<LiveStacks>();
 117   AU.addRequiredID(MachineDominatorsID);
 118   AU.addPreservedID(MachineDominatorsID);
 119   AU.addRequired<MachineLoopInfo>();
 120   AU.addPreserved<MachineLoopInfo>();
 121   AU.addRequired<VirtRegMap>();
 122   AU.addPreserved<VirtRegMap>();
 123   MachineFunctionPass::getAnalysisUsage(AU);
 124 }
 125
 126 void RAGreedy::releaseMemory() {
 127   SpillerInstance.reset(0);
 128   RegAllocBase::releaseMemory();
 129 }
 130
 131 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
 132                                 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
 133   // Populate a list of physical register spill candidates.
 134   SmallVector<unsigned, 8> PhysRegSpillCands;
 135
 136   // Check for an available register in this class.
 137   const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
 138   DEBUG(dbgs() << "RegClass: " << TRC->getName() << ' ');
 139
 140   for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
 141          E = TRC->allocation_order_end(*MF);
 142        I != E; ++I) {
 143
 144     unsigned PhysReg = *I;
 145     if (ReservedRegs.test(PhysReg)) continue;
 146
 147     // Check interference and as a side effect, intialize queries for this
 148     // VirtReg and its aliases.
 149     unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
 150     if (interfReg == 0) {
 151       // Found an available register.
 152       return PhysReg;
 153     }
 154     LiveInterval *interferingVirtReg =
 155       Queries[interfReg].firstInterference().liveUnionPos().value();
 156
 157     // The current VirtReg must either spillable, or one of its interferences
 158     // must have less spill weight.
 159     if (interferingVirtReg->weight < VirtReg.weight ) {
 160       PhysRegSpillCands.push_back(PhysReg);
 161     }
 162   }
 163   // Try to spill another interfering reg with less spill weight.
 164   //
 165   // FIXME: RAGreedy will sort this list by spill weight.
 166   for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
 167          PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
 168
 169     if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
 170
 171     assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
 172            "Interference after spill.");
 173     // Tell the caller to allocate to this newly freed physical register.
 174     return *PhysRegI;
 175   }
 176   // No other spill candidates were found, so spill the current VirtReg.
 177   DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
 178   SmallVector<LiveInterval*, 1> pendingSpills;
 179
 180   spiller().spill(&VirtReg, SplitVRegs, pendingSpills);
 181
 182   // The live virtual register requesting allocation was spilled, so tell
 183   // the caller not to allocate anything during this round.
 184   return 0;
 185 }
 186
 187 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
 188   DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
 189                << "********** Function: "
 190                << ((Value*)mf.getFunction())->getName() << '\n');
 191
 192   MF = &mf;
 193   TM = &mf.getTarget();
 194   MRI = &mf.getRegInfo();
 195
 196   const TargetRegisterInfo *TRI = TM->getRegisterInfo();
 197   RegAllocBase::init(*TRI, getAnalysis<VirtRegMap>(),
 198                      getAnalysis<LiveIntervals>());
 199
 200   ReservedRegs = TRI->getReservedRegs(*MF);
 201   SpillerInstance.reset(createSpiller(*this, *MF, *VRM));
 202   allocatePhysRegs();
 203   addMBBLiveIns(MF);
 204
 205   // Run rewriter
 206   std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
 207   rewriter->runOnMachineFunction(*MF, *VRM, LIS);
 208
 209   // The pass output is in VirtRegMap. Release all the transient data.
 210   releaseMemory();
 211
 212   return true;
 213 }
 214