1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/CodeGen/Passes.h"
17 #include "AllocationOrder.h"
18 #include "InterferenceCache.h"
19 #include "LiveDebugVariables.h"
20 #include "RegAllocBase.h"
21 #include "SpillPlacement.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/CodeGen/CalcSpillWeights.h"
27 #include "llvm/CodeGen/EdgeBundles.h"
28 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
29 #include "llvm/CodeGen/LiveRangeEdit.h"
30 #include "llvm/CodeGen/LiveRegMatrix.h"
31 #include "llvm/CodeGen/LiveStackAnalysis.h"
32 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
33 #include "llvm/CodeGen/MachineDominators.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineLoopInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/RegAllocRegistry.h"
38 #include "llvm/CodeGen/RegisterClassInfo.h"
39 #include "llvm/CodeGen/VirtRegMap.h"
40 #include "llvm/PassAnalysisSupport.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/Timer.h"
45 #include "llvm/Support/raw_ostream.h"
50 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
51 STATISTIC(NumLocalSplits, "Number of split local live ranges");
52 STATISTIC(NumEvicted, "Number of interferences evicted");
54 static cl::opt<SplitEditor::ComplementSpillMode>
55 SplitSpillMode("split-spill-mode", cl::Hidden,
56 cl::desc("Spill mode for splitting live ranges"),
57 cl::values(clEnumValN(SplitEditor::SM_Partition, "default", "Default"),
58 clEnumValN(SplitEditor::SM_Size, "size", "Optimize for size"),
59 clEnumValN(SplitEditor::SM_Speed, "speed", "Optimize for speed"),
61 cl::init(SplitEditor::SM_Partition));
63 static cl::opt<unsigned>
64 LastChanceRecoloringMaxDepth("lcr-max-depth", cl::Hidden,
65 cl::desc("Last chance recoloring max depth"),
68 static cl::opt<unsigned> LastChanceRecoloringMaxInterference(
69 "lcr-max-interf", cl::Hidden,
70 cl::desc("Last chance recoloring maximum number of considered"
71 " interference at a time"),
74 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
75 createGreedyRegisterAllocator);
78 class RAGreedy : public MachineFunctionPass,
80 private LiveRangeEdit::Delegate {
81 // Convenient shortcuts.
82 typedef std::priority_queue<std::pair<unsigned, unsigned> > PQueue;
83 typedef SmallPtrSet<LiveInterval *, 4> SmallLISet;
84 typedef SmallSet<unsigned, 16> SmallVirtRegSet;
89 // Shortcuts to some useful interface.
90 const TargetInstrInfo *TII;
91 const TargetRegisterInfo *TRI;
92 RegisterClassInfo RCI;
96 MachineBlockFrequencyInfo *MBFI;
97 MachineDominatorTree *DomTree;
98 MachineLoopInfo *Loops;
100 SpillPlacement *SpillPlacer;
101 LiveDebugVariables *DebugVars;
104 std::unique_ptr<Spiller> SpillerInstance;
106 unsigned NextCascade;
108 // Live ranges pass through a number of stages as we try to allocate them.
109 // Some of the stages may also create new live ranges:
111 // - Region splitting.
112 // - Per-block splitting.
113 // - Local splitting.
116 // Ranges produced by one of the stages skip the previous stages when they are
117 // dequeued. This improves performance because we can skip interference checks
118 // that are unlikely to give any results. It also guarantees that the live
119 // range splitting algorithm terminates, something that is otherwise hard to
121 enum LiveRangeStage {
122 /// Newly created live range that has never been queued.
125 /// Only attempt assignment and eviction. Then requeue as RS_Split.
128 /// Attempt live range splitting if assignment is impossible.
131 /// Attempt more aggressive live range splitting that is guaranteed to make
132 /// progress. This is used for split products that may not be making
136 /// Live range will be spilled. No more splitting will be attempted.
139 /// There is nothing more we can do to this live range. Abort compilation
140 /// if it can't be assigned.
145 static const char *const StageName[];
148 // RegInfo - Keep additional information about each live range.
150 LiveRangeStage Stage;
152 // Cascade - Eviction loop prevention. See canEvictInterference().
155 RegInfo() : Stage(RS_New), Cascade(0) {}
158 IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo;
160 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
161 return ExtraRegInfo[VirtReg.reg].Stage;
164 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) {
165 ExtraRegInfo.resize(MRI->getNumVirtRegs());
166 ExtraRegInfo[VirtReg.reg].Stage = Stage;
169 template<typename Iterator>
170 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
171 ExtraRegInfo.resize(MRI->getNumVirtRegs());
172 for (;Begin != End; ++Begin) {
173 unsigned Reg = *Begin;
174 if (ExtraRegInfo[Reg].Stage == RS_New)
175 ExtraRegInfo[Reg].Stage = NewStage;
179 /// Cost of evicting interference.
180 struct EvictionCost {
181 unsigned BrokenHints; ///< Total number of broken hints.
182 float MaxWeight; ///< Maximum spill weight evicted.
184 EvictionCost(): BrokenHints(0), MaxWeight(0) {}
186 bool isMax() const { return BrokenHints == ~0u; }
188 void setMax() { BrokenHints = ~0u; }
190 void setBrokenHints(unsigned NHints) { BrokenHints = NHints; }
192 bool operator<(const EvictionCost &O) const {
193 return std::tie(BrokenHints, MaxWeight) <
194 std::tie(O.BrokenHints, O.MaxWeight);
199 std::unique_ptr<SplitAnalysis> SA;
200 std::unique_ptr<SplitEditor> SE;
202 /// Cached per-block interference maps
203 InterferenceCache IntfCache;
205 /// All basic blocks where the current register has uses.
206 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
208 /// Global live range splitting candidate info.
209 struct GlobalSplitCandidate {
210 // Register intended for assignment, or 0.
213 // SplitKit interval index for this candidate.
216 // Interference for PhysReg.
217 InterferenceCache::Cursor Intf;
219 // Bundles where this candidate should be live.
220 BitVector LiveBundles;
221 SmallVector<unsigned, 8> ActiveBlocks;
223 void reset(InterferenceCache &Cache, unsigned Reg) {
226 Intf.setPhysReg(Cache, Reg);
228 ActiveBlocks.clear();
231 // Set B[i] = C for every live bundle where B[i] was NoCand.
232 unsigned getBundles(SmallVectorImpl<unsigned> &B, unsigned C) {
234 for (int i = LiveBundles.find_first(); i >= 0;
235 i = LiveBundles.find_next(i))
236 if (B[i] == NoCand) {
244 /// Candidate info for each PhysReg in AllocationOrder.
245 /// This vector never shrinks, but grows to the size of the largest register
247 SmallVector<GlobalSplitCandidate, 32> GlobalCand;
249 enum : unsigned { NoCand = ~0u };
251 /// Candidate map. Each edge bundle is assigned to a GlobalCand entry, or to
252 /// NoCand which indicates the stack interval.
253 SmallVector<unsigned, 32> BundleCand;
258 /// Return the pass name.
259 virtual const char* getPassName() const {
260 return "Greedy Register Allocator";
263 /// RAGreedy analysis usage.
264 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
265 virtual void releaseMemory();
266 virtual Spiller &spiller() { return *SpillerInstance; }
267 virtual void enqueue(LiveInterval *LI);
268 virtual LiveInterval *dequeue();
269 virtual unsigned selectOrSplit(LiveInterval&,
270 SmallVectorImpl<unsigned>&);
272 /// Perform register allocation.
273 virtual bool runOnMachineFunction(MachineFunction &mf);
278 unsigned selectOrSplitImpl(LiveInterval &, SmallVectorImpl<unsigned> &,
279 SmallVirtRegSet &, unsigned = 0);
281 bool LRE_CanEraseVirtReg(unsigned);
282 void LRE_WillShrinkVirtReg(unsigned);
283 void LRE_DidCloneVirtReg(unsigned, unsigned);
284 void enqueue(PQueue &CurQueue, LiveInterval *LI);
285 LiveInterval *dequeue(PQueue &CurQueue);
287 BlockFrequency calcSpillCost();
288 bool addSplitConstraints(InterferenceCache::Cursor, BlockFrequency&);
289 void addThroughConstraints(InterferenceCache::Cursor, ArrayRef<unsigned>);
290 void growRegion(GlobalSplitCandidate &Cand);
291 BlockFrequency calcGlobalSplitCost(GlobalSplitCandidate&);
292 bool calcCompactRegion(GlobalSplitCandidate&);
293 void splitAroundRegion(LiveRangeEdit&, ArrayRef<unsigned>);
294 void calcGapWeights(unsigned, SmallVectorImpl<float>&);
295 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
296 bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
297 bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
298 void evictInterference(LiveInterval&, unsigned,
299 SmallVectorImpl<unsigned>&);
300 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
301 SmallLISet &RecoloringCandidates,
302 const SmallVirtRegSet &FixedRegisters);
304 unsigned tryAssign(LiveInterval&, AllocationOrder&,
305 SmallVectorImpl<unsigned>&);
306 unsigned tryEvict(LiveInterval&, AllocationOrder&,
307 SmallVectorImpl<unsigned>&, unsigned = ~0u);
308 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
309 SmallVectorImpl<unsigned>&);
310 unsigned tryBlockSplit(LiveInterval&, AllocationOrder&,
311 SmallVectorImpl<unsigned>&);
312 unsigned tryInstructionSplit(LiveInterval&, AllocationOrder&,
313 SmallVectorImpl<unsigned>&);
314 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
315 SmallVectorImpl<unsigned>&);
316 unsigned trySplit(LiveInterval&, AllocationOrder&,
317 SmallVectorImpl<unsigned>&);
318 unsigned tryLastChanceRecoloring(LiveInterval &, AllocationOrder &,
319 SmallVectorImpl<unsigned> &,
320 SmallVirtRegSet &, unsigned);
321 bool tryRecoloringCandidates(PQueue &, SmallVectorImpl<unsigned> &,
322 SmallVirtRegSet &, unsigned);
324 } // end anonymous namespace
326 char RAGreedy::ID = 0;
329 const char *const RAGreedy::StageName[] = {
339 // Hysteresis to use when comparing floats.
340 // This helps stabilize decisions based on float comparisons.
341 const float Hysteresis = (2007 / 2048.0f); // 0.97998046875
344 FunctionPass* llvm::createGreedyRegisterAllocator() {
345 return new RAGreedy();
348 RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
349 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
350 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
351 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
352 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
353 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
354 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
355 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
356 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
357 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
358 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
359 initializeLiveRegMatrixPass(*PassRegistry::getPassRegistry());
360 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
361 initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
364 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
365 AU.setPreservesCFG();
366 AU.addRequired<MachineBlockFrequencyInfo>();
367 AU.addPreserved<MachineBlockFrequencyInfo>();
368 AU.addRequired<AliasAnalysis>();
369 AU.addPreserved<AliasAnalysis>();
370 AU.addRequired<LiveIntervals>();
371 AU.addPreserved<LiveIntervals>();
372 AU.addRequired<SlotIndexes>();
373 AU.addPreserved<SlotIndexes>();
374 AU.addRequired<LiveDebugVariables>();
375 AU.addPreserved<LiveDebugVariables>();
376 AU.addRequired<LiveStacks>();
377 AU.addPreserved<LiveStacks>();
378 AU.addRequired<MachineDominatorTree>();
379 AU.addPreserved<MachineDominatorTree>();
380 AU.addRequired<MachineLoopInfo>();
381 AU.addPreserved<MachineLoopInfo>();
382 AU.addRequired<VirtRegMap>();
383 AU.addPreserved<VirtRegMap>();
384 AU.addRequired<LiveRegMatrix>();
385 AU.addPreserved<LiveRegMatrix>();
386 AU.addRequired<EdgeBundles>();
387 AU.addRequired<SpillPlacement>();
388 MachineFunctionPass::getAnalysisUsage(AU);
392 //===----------------------------------------------------------------------===//
393 // LiveRangeEdit delegate methods
394 //===----------------------------------------------------------------------===//
396 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
397 if (VRM->hasPhys(VirtReg)) {
398 Matrix->unassign(LIS->getInterval(VirtReg));
401 // Unassigned virtreg is probably in the priority queue.
402 // RegAllocBase will erase it after dequeueing.
406 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
407 if (!VRM->hasPhys(VirtReg))
410 // Register is assigned, put it back on the queue for reassignment.
411 LiveInterval &LI = LIS->getInterval(VirtReg);
412 Matrix->unassign(LI);
416 void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
417 // Cloning a register we haven't even heard about yet? Just ignore it.
418 if (!ExtraRegInfo.inBounds(Old))
421 // LRE may clone a virtual register because dead code elimination causes it to
422 // be split into connected components. The new components are much smaller
423 // than the original, so they should get a new chance at being assigned.
424 // same stage as the parent.
425 ExtraRegInfo[Old].Stage = RS_Assign;
426 ExtraRegInfo.grow(New);
427 ExtraRegInfo[New] = ExtraRegInfo[Old];
430 void RAGreedy::releaseMemory() {
431 SpillerInstance.reset(0);
432 ExtraRegInfo.clear();
436 void RAGreedy::enqueue(LiveInterval *LI) { enqueue(Queue, LI); }
438 void RAGreedy::enqueue(PQueue &CurQueue, LiveInterval *LI) {
439 // Prioritize live ranges by size, assigning larger ranges first.
440 // The queue holds (size, reg) pairs.
441 const unsigned Size = LI->getSize();
442 const unsigned Reg = LI->reg;
443 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
444 "Can only enqueue virtual registers");
447 ExtraRegInfo.grow(Reg);
448 if (ExtraRegInfo[Reg].Stage == RS_New)
449 ExtraRegInfo[Reg].Stage = RS_Assign;
451 if (ExtraRegInfo[Reg].Stage == RS_Split) {
452 // Unsplit ranges that couldn't be allocated immediately are deferred until
453 // everything else has been allocated.
456 // Giant live ranges fall back to the global assignment heuristic, which
457 // prevents excessive spilling in pathological cases.
458 bool ReverseLocal = TRI->reverseLocalAssignment();
459 bool ForceGlobal = !ReverseLocal && TRI->mayOverrideLocalAssignment() &&
460 (Size / SlotIndex::InstrDist) > (2 * MRI->getRegClass(Reg)->getNumRegs());
462 if (ExtraRegInfo[Reg].Stage == RS_Assign && !ForceGlobal && !LI->empty() &&
463 LIS->intervalIsInOneMBB(*LI)) {
464 // Allocate original local ranges in linear instruction order. Since they
465 // are singly defined, this produces optimal coloring in the absence of
466 // global interference and other constraints.
468 Prio = LI->beginIndex().getInstrDistance(Indexes->getLastIndex());
470 // Allocating bottom up may allow many short LRGs to be assigned first
471 // to one of the cheap registers. This could be much faster for very
472 // large blocks on targets with many physical registers.
473 Prio = Indexes->getZeroIndex().getInstrDistance(LI->beginIndex());
477 // Allocate global and split ranges in long->short order. Long ranges that
478 // don't fit should be spilled (or split) ASAP so they don't create
479 // interference. Mark a bit to prioritize global above local ranges.
480 Prio = (1u << 29) + Size;
482 // Mark a higher bit to prioritize global and local above RS_Split.
485 // Boost ranges that have a physical register hint.
486 if (VRM->hasKnownPreference(Reg))
489 // The virtual register number is a tie breaker for same-sized ranges.
490 // Give lower vreg numbers higher priority to assign them first.
491 CurQueue.push(std::make_pair(Prio, ~Reg));
494 LiveInterval *RAGreedy::dequeue() { return dequeue(Queue); }
496 LiveInterval *RAGreedy::dequeue(PQueue &CurQueue) {
497 if (CurQueue.empty())
499 LiveInterval *LI = &LIS->getInterval(~CurQueue.top().second);
505 //===----------------------------------------------------------------------===//
507 //===----------------------------------------------------------------------===//
509 /// tryAssign - Try to assign VirtReg to an available register.
510 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
511 AllocationOrder &Order,
512 SmallVectorImpl<unsigned> &NewVRegs) {
515 while ((PhysReg = Order.next()))
516 if (!Matrix->checkInterference(VirtReg, PhysReg))
518 if (!PhysReg || Order.isHint())
521 // PhysReg is available, but there may be a better choice.
523 // If we missed a simple hint, try to cheaply evict interference from the
524 // preferred register.
525 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg))
526 if (Order.isHint(Hint)) {
527 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
528 EvictionCost MaxCost;
529 MaxCost.setBrokenHints(1);
530 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) {
531 evictInterference(VirtReg, Hint, NewVRegs);
536 // Try to evict interference from a cheaper alternative.
537 unsigned Cost = TRI->getCostPerUse(PhysReg);
539 // Most registers have 0 additional cost.
543 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
545 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
546 return CheapReg ? CheapReg : PhysReg;
550 //===----------------------------------------------------------------------===//
551 // Interference eviction
552 //===----------------------------------------------------------------------===//
554 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) {
555 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
557 while ((PhysReg = Order.next())) {
558 if (PhysReg == PrevReg)
561 MCRegUnitIterator Units(PhysReg, TRI);
562 for (; Units.isValid(); ++Units) {
563 // Instantiate a "subquery", not to be confused with the Queries array.
564 LiveIntervalUnion::Query subQ(&VirtReg, &Matrix->getLiveUnions()[*Units]);
565 if (subQ.checkInterference())
568 // If no units have interference, break out with the current PhysReg.
569 if (!Units.isValid())
573 DEBUG(dbgs() << "can reassign: " << VirtReg << " from "
574 << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI)
579 /// shouldEvict - determine if A should evict the assigned live range B. The
580 /// eviction policy defined by this function together with the allocation order
581 /// defined by enqueue() decides which registers ultimately end up being split
584 /// Cascade numbers are used to prevent infinite loops if this function is a
587 /// @param A The live range to be assigned.
588 /// @param IsHint True when A is about to be assigned to its preferred
590 /// @param B The live range to be evicted.
591 /// @param BreaksHint True when B is already assigned to its preferred register.
592 bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint,
593 LiveInterval &B, bool BreaksHint) {
594 bool CanSplit = getStage(B) < RS_Spill;
596 // Be fairly aggressive about following hints as long as the evictee can be
598 if (CanSplit && IsHint && !BreaksHint)
601 if (A.weight > B.weight) {
602 DEBUG(dbgs() << "should evict: " << B << " w= " << B.weight << '\n');
608 /// canEvictInterference - Return true if all interferences between VirtReg and
609 /// PhysReg can be evicted.
611 /// @param VirtReg Live range that is about to be assigned.
612 /// @param PhysReg Desired register for assignment.
613 /// @param IsHint True when PhysReg is VirtReg's preferred register.
614 /// @param MaxCost Only look for cheaper candidates and update with new cost
615 /// when returning true.
616 /// @returns True when interference can be evicted cheaper than MaxCost.
617 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
618 bool IsHint, EvictionCost &MaxCost) {
619 // It is only possible to evict virtual register interference.
620 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg)
623 bool IsLocal = LIS->intervalIsInOneMBB(VirtReg);
625 // Find VirtReg's cascade number. This will be unassigned if VirtReg was never
626 // involved in an eviction before. If a cascade number was assigned, deny
627 // evicting anything with the same or a newer cascade number. This prevents
628 // infinite eviction loops.
630 // This works out so a register without a cascade number is allowed to evict
631 // anything, and it can be evicted by anything.
632 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
634 Cascade = NextCascade;
637 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
638 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
639 // If there is 10 or more interferences, chances are one is heavier.
640 if (Q.collectInterferingVRegs(10) >= 10)
643 // Check if any interfering live range is heavier than MaxWeight.
644 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
645 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
646 assert(TargetRegisterInfo::isVirtualRegister(Intf->reg) &&
647 "Only expecting virtual register interference from query");
648 // Never evict spill products. They cannot split or spill.
649 if (getStage(*Intf) == RS_Done)
651 // Once a live range becomes small enough, it is urgent that we find a
652 // register for it. This is indicated by an infinite spill weight. These
653 // urgent live ranges get to evict almost anything.
655 // Also allow urgent evictions of unspillable ranges from a strictly
656 // larger allocation order.
657 bool Urgent = !VirtReg.isSpillable() &&
658 (Intf->isSpillable() ||
659 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
660 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
661 // Only evict older cascades or live ranges without a cascade.
662 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
663 if (Cascade <= IntfCascade) {
666 // We permit breaking cascades for urgent evictions. It should be the
667 // last resort, though, so make it really expensive.
668 Cost.BrokenHints += 10;
670 // Would this break a satisfied hint?
671 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
672 // Update eviction cost.
673 Cost.BrokenHints += BreaksHint;
674 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
675 // Abort if this would be too expensive.
676 if (!(Cost < MaxCost))
680 // Apply the eviction policy for non-urgent evictions.
681 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
683 // If !MaxCost.isMax(), then we're just looking for a cheap register.
684 // Evicting another local live range in this case could lead to suboptimal
686 if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf) &&
687 !canReassign(*Intf, PhysReg)) {
696 /// evictInterference - Evict any interferring registers that prevent VirtReg
697 /// from being assigned to Physreg. This assumes that canEvictInterference
699 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
700 SmallVectorImpl<unsigned> &NewVRegs) {
701 // Make sure that VirtReg has a cascade number, and assign that cascade
702 // number to every evicted register. These live ranges than then only be
703 // evicted by a newer cascade, preventing infinite loops.
704 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
706 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
708 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
709 << " interference: Cascade " << Cascade << '\n');
711 // Collect all interfering virtregs first.
712 SmallVector<LiveInterval*, 8> Intfs;
713 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
714 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
715 assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
716 ArrayRef<LiveInterval*> IVR = Q.interferingVRegs();
717 Intfs.append(IVR.begin(), IVR.end());
720 // Evict them second. This will invalidate the queries.
721 for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
722 LiveInterval *Intf = Intfs[i];
723 // The same VirtReg may be present in multiple RegUnits. Skip duplicates.
724 if (!VRM->hasPhys(Intf->reg))
726 Matrix->unassign(*Intf);
727 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
728 VirtReg.isSpillable() < Intf->isSpillable()) &&
729 "Cannot decrease cascade number, illegal eviction");
730 ExtraRegInfo[Intf->reg].Cascade = Cascade;
732 NewVRegs.push_back(Intf->reg);
736 /// tryEvict - Try to evict all interferences for a physreg.
737 /// @param VirtReg Currently unassigned virtual register.
738 /// @param Order Physregs to try.
739 /// @return Physreg to assign VirtReg, or 0.
740 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
741 AllocationOrder &Order,
742 SmallVectorImpl<unsigned> &NewVRegs,
743 unsigned CostPerUseLimit) {
744 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
746 // Keep track of the cheapest interference seen so far.
747 EvictionCost BestCost;
749 unsigned BestPhys = 0;
750 unsigned OrderLimit = Order.getOrder().size();
752 // When we are just looking for a reduced cost per use, don't break any
753 // hints, and only evict smaller spill weights.
754 if (CostPerUseLimit < ~0u) {
755 BestCost.BrokenHints = 0;
756 BestCost.MaxWeight = VirtReg.weight;
758 // Check of any registers in RC are below CostPerUseLimit.
759 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg);
760 unsigned MinCost = RegClassInfo.getMinCost(RC);
761 if (MinCost >= CostPerUseLimit) {
762 DEBUG(dbgs() << RC->getName() << " minimum cost = " << MinCost
763 << ", no cheaper registers to be found.\n");
767 // It is normal for register classes to have a long tail of registers with
768 // the same cost. We don't need to look at them if they're too expensive.
769 if (TRI->getCostPerUse(Order.getOrder().back()) >= CostPerUseLimit) {
770 OrderLimit = RegClassInfo.getLastCostChange(RC);
771 DEBUG(dbgs() << "Only trying the first " << OrderLimit << " regs.\n");
776 while (unsigned PhysReg = Order.next(OrderLimit)) {
777 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
779 // The first use of a callee-saved register in a function has cost 1.
780 // Don't start using a CSR when the CostPerUseLimit is low.
781 if (CostPerUseLimit == 1)
782 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
783 if (!MRI->isPhysRegUsed(CSR)) {
784 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
785 << PrintReg(CSR, TRI) << '\n');
789 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
795 // Stop if the hint can be used.
803 evictInterference(VirtReg, BestPhys, NewVRegs);
808 //===----------------------------------------------------------------------===//
810 //===----------------------------------------------------------------------===//
812 /// addSplitConstraints - Fill out the SplitConstraints vector based on the
813 /// interference pattern in Physreg and its aliases. Add the constraints to
814 /// SpillPlacement and return the static cost of this split in Cost, assuming
815 /// that all preferences in SplitConstraints are met.
816 /// Return false if there are no bundles with positive bias.
817 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
818 BlockFrequency &Cost) {
819 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
821 // Reset interference dependent info.
822 SplitConstraints.resize(UseBlocks.size());
823 BlockFrequency StaticCost = 0;
824 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
825 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
826 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
828 BC.Number = BI.MBB->getNumber();
829 Intf.moveToBlock(BC.Number);
830 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
831 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
832 BC.ChangesValue = BI.FirstDef.isValid();
834 if (!Intf.hasInterference())
837 // Number of spill code instructions to insert.
840 // Interference for the live-in value.
842 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
843 BC.Entry = SpillPlacement::MustSpill, ++Ins;
844 else if (Intf.first() < BI.FirstInstr)
845 BC.Entry = SpillPlacement::PrefSpill, ++Ins;
846 else if (Intf.first() < BI.LastInstr)
850 // Interference for the live-out value.
852 if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
853 BC.Exit = SpillPlacement::MustSpill, ++Ins;
854 else if (Intf.last() > BI.LastInstr)
855 BC.Exit = SpillPlacement::PrefSpill, ++Ins;
856 else if (Intf.last() > BI.FirstInstr)
860 // Accumulate the total frequency of inserted spill code.
862 StaticCost += SpillPlacer->getBlockFrequency(BC.Number);
866 // Add constraints for use-blocks. Note that these are the only constraints
867 // that may add a positive bias, it is downhill from here.
868 SpillPlacer->addConstraints(SplitConstraints);
869 return SpillPlacer->scanActiveBundles();
873 /// addThroughConstraints - Add constraints and links to SpillPlacer from the
874 /// live-through blocks in Blocks.
875 void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
876 ArrayRef<unsigned> Blocks) {
877 const unsigned GroupSize = 8;
878 SpillPlacement::BlockConstraint BCS[GroupSize];
879 unsigned TBS[GroupSize];
880 unsigned B = 0, T = 0;
882 for (unsigned i = 0; i != Blocks.size(); ++i) {
883 unsigned Number = Blocks[i];
884 Intf.moveToBlock(Number);
886 if (!Intf.hasInterference()) {
887 assert(T < GroupSize && "Array overflow");
889 if (++T == GroupSize) {
890 SpillPlacer->addLinks(makeArrayRef(TBS, T));
896 assert(B < GroupSize && "Array overflow");
897 BCS[B].Number = Number;
899 // Interference for the live-in value.
900 if (Intf.first() <= Indexes->getMBBStartIdx(Number))
901 BCS[B].Entry = SpillPlacement::MustSpill;
903 BCS[B].Entry = SpillPlacement::PrefSpill;
905 // Interference for the live-out value.
906 if (Intf.last() >= SA->getLastSplitPoint(Number))
907 BCS[B].Exit = SpillPlacement::MustSpill;
909 BCS[B].Exit = SpillPlacement::PrefSpill;
911 if (++B == GroupSize) {
912 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
913 SpillPlacer->addConstraints(Array);
918 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
919 SpillPlacer->addConstraints(Array);
920 SpillPlacer->addLinks(makeArrayRef(TBS, T));
923 void RAGreedy::growRegion(GlobalSplitCandidate &Cand) {
924 // Keep track of through blocks that have not been added to SpillPlacer.
925 BitVector Todo = SA->getThroughBlocks();
926 SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
927 unsigned AddedTo = 0;
929 unsigned Visited = 0;
933 ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive();
934 // Find new through blocks in the periphery of PrefRegBundles.
935 for (int i = 0, e = NewBundles.size(); i != e; ++i) {
936 unsigned Bundle = NewBundles[i];
937 // Look at all blocks connected to Bundle in the full graph.
938 ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle);
939 for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end();
942 if (!Todo.test(Block))
945 // This is a new through block. Add it to SpillPlacer later.
946 ActiveBlocks.push_back(Block);
952 // Any new blocks to add?
953 if (ActiveBlocks.size() == AddedTo)
956 // Compute through constraints from the interference, or assume that all
957 // through blocks prefer spilling when forming compact regions.
958 ArrayRef<unsigned> NewBlocks = makeArrayRef(ActiveBlocks).slice(AddedTo);
960 addThroughConstraints(Cand.Intf, NewBlocks);
962 // Provide a strong negative bias on through blocks to prevent unwanted
963 // liveness on loop backedges.
964 SpillPlacer->addPrefSpill(NewBlocks, /* Strong= */ true);
965 AddedTo = ActiveBlocks.size();
967 // Perhaps iterating can enable more bundles?
968 SpillPlacer->iterate();
970 DEBUG(dbgs() << ", v=" << Visited);
973 /// calcCompactRegion - Compute the set of edge bundles that should be live
974 /// when splitting the current live range into compact regions. Compact
975 /// regions can be computed without looking at interference. They are the
976 /// regions formed by removing all the live-through blocks from the live range.
978 /// Returns false if the current live range is already compact, or if the
979 /// compact regions would form single block regions anyway.
980 bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) {
981 // Without any through blocks, the live range is already compact.
982 if (!SA->getNumThroughBlocks())
985 // Compact regions don't correspond to any physreg.
986 Cand.reset(IntfCache, 0);
988 DEBUG(dbgs() << "Compact region bundles");
990 // Use the spill placer to determine the live bundles. GrowRegion pretends
991 // that all the through blocks have interference when PhysReg is unset.
992 SpillPlacer->prepare(Cand.LiveBundles);
994 // The static split cost will be zero since Cand.Intf reports no interference.
996 if (!addSplitConstraints(Cand.Intf, Cost)) {
997 DEBUG(dbgs() << ", none.\n");
1002 SpillPlacer->finish();
1004 if (!Cand.LiveBundles.any()) {
1005 DEBUG(dbgs() << ", none.\n");
1010 for (int i = Cand.LiveBundles.find_first(); i>=0;
1011 i = Cand.LiveBundles.find_next(i))
1012 dbgs() << " EB#" << i;
1018 /// calcSpillCost - Compute how expensive it would be to split the live range in
1019 /// SA around all use blocks instead of forming bundle regions.
1020 BlockFrequency RAGreedy::calcSpillCost() {
1021 BlockFrequency Cost = 0;
1022 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1023 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1024 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1025 unsigned Number = BI.MBB->getNumber();
1026 // We normally only need one spill instruction - a load or a store.
1027 Cost += SpillPlacer->getBlockFrequency(Number);
1029 // Unless the value is redefined in the block.
1030 if (BI.LiveIn && BI.LiveOut && BI.FirstDef)
1031 Cost += SpillPlacer->getBlockFrequency(Number);
1036 /// calcGlobalSplitCost - Return the global split cost of following the split
1037 /// pattern in LiveBundles. This cost should be added to the local cost of the
1038 /// interference pattern in SplitConstraints.
1040 BlockFrequency RAGreedy::calcGlobalSplitCost(GlobalSplitCandidate &Cand) {
1041 BlockFrequency GlobalCost = 0;
1042 const BitVector &LiveBundles = Cand.LiveBundles;
1043 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1044 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1045 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1046 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
1047 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)];
1048 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)];
1052 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
1054 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
1056 GlobalCost += SpillPlacer->getBlockFrequency(BC.Number);
1059 for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) {
1060 unsigned Number = Cand.ActiveBlocks[i];
1061 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)];
1062 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
1063 if (!RegIn && !RegOut)
1065 if (RegIn && RegOut) {
1066 // We need double spill code if this block has interference.
1067 Cand.Intf.moveToBlock(Number);
1068 if (Cand.Intf.hasInterference()) {
1069 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1070 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1074 // live-in / stack-out or stack-in live-out.
1075 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1080 /// splitAroundRegion - Split the current live range around the regions
1081 /// determined by BundleCand and GlobalCand.
1083 /// Before calling this function, GlobalCand and BundleCand must be initialized
1084 /// so each bundle is assigned to a valid candidate, or NoCand for the
1085 /// stack-bound bundles. The shared SA/SE SplitAnalysis and SplitEditor
1086 /// objects must be initialized for the current live range, and intervals
1087 /// created for the used candidates.
1089 /// @param LREdit The LiveRangeEdit object handling the current split.
1090 /// @param UsedCands List of used GlobalCand entries. Every BundleCand value
1091 /// must appear in this list.
1092 void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit,
1093 ArrayRef<unsigned> UsedCands) {
1094 // These are the intervals created for new global ranges. We may create more
1095 // intervals for local ranges.
1096 const unsigned NumGlobalIntvs = LREdit.size();
1097 DEBUG(dbgs() << "splitAroundRegion with " << NumGlobalIntvs << " globals.\n");
1098 assert(NumGlobalIntvs && "No global intervals configured");
1100 // Isolate even single instructions when dealing with a proper sub-class.
1101 // That guarantees register class inflation for the stack interval because it
1103 unsigned Reg = SA->getParent().reg;
1104 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1106 // First handle all the blocks with uses.
1107 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1108 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1109 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1110 unsigned Number = BI.MBB->getNumber();
1111 unsigned IntvIn = 0, IntvOut = 0;
1112 SlotIndex IntfIn, IntfOut;
1114 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
1115 if (CandIn != NoCand) {
1116 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
1117 IntvIn = Cand.IntvIdx;
1118 Cand.Intf.moveToBlock(Number);
1119 IntfIn = Cand.Intf.first();
1123 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
1124 if (CandOut != NoCand) {
1125 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
1126 IntvOut = Cand.IntvIdx;
1127 Cand.Intf.moveToBlock(Number);
1128 IntfOut = Cand.Intf.last();
1132 // Create separate intervals for isolated blocks with multiple uses.
1133 if (!IntvIn && !IntvOut) {
1134 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n");
1135 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
1136 SE->splitSingleBlock(BI);
1140 if (IntvIn && IntvOut)
1141 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
1143 SE->splitRegInBlock(BI, IntvIn, IntfIn);
1145 SE->splitRegOutBlock(BI, IntvOut, IntfOut);
1148 // Handle live-through blocks. The relevant live-through blocks are stored in
1149 // the ActiveBlocks list with each candidate. We need to filter out
1151 BitVector Todo = SA->getThroughBlocks();
1152 for (unsigned c = 0; c != UsedCands.size(); ++c) {
1153 ArrayRef<unsigned> Blocks = GlobalCand[UsedCands[c]].ActiveBlocks;
1154 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
1155 unsigned Number = Blocks[i];
1156 if (!Todo.test(Number))
1160 unsigned IntvIn = 0, IntvOut = 0;
1161 SlotIndex IntfIn, IntfOut;
1163 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
1164 if (CandIn != NoCand) {
1165 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
1166 IntvIn = Cand.IntvIdx;
1167 Cand.Intf.moveToBlock(Number);
1168 IntfIn = Cand.Intf.first();
1171 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
1172 if (CandOut != NoCand) {
1173 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
1174 IntvOut = Cand.IntvIdx;
1175 Cand.Intf.moveToBlock(Number);
1176 IntfOut = Cand.Intf.last();
1178 if (!IntvIn && !IntvOut)
1180 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
1186 SmallVector<unsigned, 8> IntvMap;
1187 SE->finish(&IntvMap);
1188 DebugVars->splitRegister(Reg, LREdit.regs(), *LIS);
1190 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1191 unsigned OrigBlocks = SA->getNumLiveBlocks();
1193 // Sort out the new intervals created by splitting. We get four kinds:
1194 // - Remainder intervals should not be split again.
1195 // - Candidate intervals can be assigned to Cand.PhysReg.
1196 // - Block-local splits are candidates for local splitting.
1197 // - DCE leftovers should go back on the queue.
1198 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1199 LiveInterval &Reg = LIS->getInterval(LREdit.get(i));
1201 // Ignore old intervals from DCE.
1202 if (getStage(Reg) != RS_New)
1205 // Remainder interval. Don't try splitting again, spill if it doesn't
1207 if (IntvMap[i] == 0) {
1208 setStage(Reg, RS_Spill);
1212 // Global intervals. Allow repeated splitting as long as the number of live
1213 // blocks is strictly decreasing.
1214 if (IntvMap[i] < NumGlobalIntvs) {
1215 if (SA->countLiveBlocks(&Reg) >= OrigBlocks) {
1216 DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks
1217 << " blocks as original.\n");
1218 // Don't allow repeated splitting as a safe guard against looping.
1219 setStage(Reg, RS_Split2);
1224 // Other intervals are treated as new. This includes local intervals created
1225 // for blocks with multiple uses, and anything created by DCE.
1229 MF->verify(this, "After splitting live range around region");
1232 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1233 SmallVectorImpl<unsigned> &NewVRegs) {
1234 unsigned NumCands = 0;
1235 unsigned BestCand = NoCand;
1236 BlockFrequency BestCost;
1237 SmallVector<unsigned, 8> UsedCands;
1239 // Check if we can split this live range around a compact region.
1240 bool HasCompact = calcCompactRegion(GlobalCand.front());
1242 // Yes, keep GlobalCand[0] as the compact region candidate.
1244 BestCost = BlockFrequency::getMaxFrequency();
1246 // No benefit from the compact region, our fallback will be per-block
1247 // splitting. Make sure we find a solution that is cheaper than spilling.
1248 BestCost = calcSpillCost();
1249 DEBUG(dbgs() << "Cost of isolating all blocks = ";
1250 MBFI->printBlockFreq(dbgs(), BestCost) << '\n');
1254 while (unsigned PhysReg = Order.next()) {
1255 // Discard bad candidates before we run out of interference cache cursors.
1256 // This will only affect register classes with a lot of registers (>32).
1257 if (NumCands == IntfCache.getMaxCursors()) {
1258 unsigned WorstCount = ~0u;
1260 for (unsigned i = 0; i != NumCands; ++i) {
1261 if (i == BestCand || !GlobalCand[i].PhysReg)
1263 unsigned Count = GlobalCand[i].LiveBundles.count();
1264 if (Count < WorstCount)
1265 Worst = i, WorstCount = Count;
1268 GlobalCand[Worst] = GlobalCand[NumCands];
1269 if (BestCand == NumCands)
1273 if (GlobalCand.size() <= NumCands)
1274 GlobalCand.resize(NumCands+1);
1275 GlobalSplitCandidate &Cand = GlobalCand[NumCands];
1276 Cand.reset(IntfCache, PhysReg);
1278 SpillPlacer->prepare(Cand.LiveBundles);
1279 BlockFrequency Cost;
1280 if (!addSplitConstraints(Cand.Intf, Cost)) {
1281 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n");
1284 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = ";
1285 MBFI->printBlockFreq(dbgs(), Cost));
1286 if (Cost >= BestCost) {
1288 if (BestCand == NoCand)
1289 dbgs() << " worse than no bundles\n";
1291 dbgs() << " worse than "
1292 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1298 SpillPlacer->finish();
1300 // No live bundles, defer to splitSingleBlocks().
1301 if (!Cand.LiveBundles.any()) {
1302 DEBUG(dbgs() << " no bundles.\n");
1306 Cost += calcGlobalSplitCost(Cand);
1308 dbgs() << ", total = "; MBFI->printBlockFreq(dbgs(), Cost)
1310 for (int i = Cand.LiveBundles.find_first(); i>=0;
1311 i = Cand.LiveBundles.find_next(i))
1312 dbgs() << " EB#" << i;
1315 if (Cost < BestCost) {
1316 BestCand = NumCands;
1322 // No solutions found, fall back to single block splitting.
1323 if (!HasCompact && BestCand == NoCand)
1326 // Prepare split editor.
1327 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1328 SE->reset(LREdit, SplitSpillMode);
1330 // Assign all edge bundles to the preferred candidate, or NoCand.
1331 BundleCand.assign(Bundles->getNumBundles(), NoCand);
1333 // Assign bundles for the best candidate region.
1334 if (BestCand != NoCand) {
1335 GlobalSplitCandidate &Cand = GlobalCand[BestCand];
1336 if (unsigned B = Cand.getBundles(BundleCand, BestCand)) {
1337 UsedCands.push_back(BestCand);
1338 Cand.IntvIdx = SE->openIntv();
1339 DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in "
1340 << B << " bundles, intv " << Cand.IntvIdx << ".\n");
1345 // Assign bundles for the compact region.
1347 GlobalSplitCandidate &Cand = GlobalCand.front();
1348 assert(!Cand.PhysReg && "Compact region has no physreg");
1349 if (unsigned B = Cand.getBundles(BundleCand, 0)) {
1350 UsedCands.push_back(0);
1351 Cand.IntvIdx = SE->openIntv();
1352 DEBUG(dbgs() << "Split for compact region in " << B << " bundles, intv "
1353 << Cand.IntvIdx << ".\n");
1358 splitAroundRegion(LREdit, UsedCands);
1363 //===----------------------------------------------------------------------===//
1364 // Per-Block Splitting
1365 //===----------------------------------------------------------------------===//
1367 /// tryBlockSplit - Split a global live range around every block with uses. This
1368 /// creates a lot of local live ranges, that will be split by tryLocalSplit if
1369 /// they don't allocate.
1370 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1371 SmallVectorImpl<unsigned> &NewVRegs) {
1372 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed");
1373 unsigned Reg = VirtReg.reg;
1374 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1375 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1376 SE->reset(LREdit, SplitSpillMode);
1377 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1378 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1379 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1380 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
1381 SE->splitSingleBlock(BI);
1383 // No blocks were split.
1387 // We did split for some blocks.
1388 SmallVector<unsigned, 8> IntvMap;
1389 SE->finish(&IntvMap);
1391 // Tell LiveDebugVariables about the new ranges.
1392 DebugVars->splitRegister(Reg, LREdit.regs(), *LIS);
1394 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1396 // Sort out the new intervals created by splitting. The remainder interval
1397 // goes straight to spilling, the new local ranges get to stay RS_New.
1398 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1399 LiveInterval &LI = LIS->getInterval(LREdit.get(i));
1400 if (getStage(LI) == RS_New && IntvMap[i] == 0)
1401 setStage(LI, RS_Spill);
1405 MF->verify(this, "After splitting live range around basic blocks");
1410 //===----------------------------------------------------------------------===//
1411 // Per-Instruction Splitting
1412 //===----------------------------------------------------------------------===//
1414 /// Get the number of allocatable registers that match the constraints of \p Reg
1415 /// on \p MI and that are also in \p SuperRC.
1416 static unsigned getNumAllocatableRegsForConstraints(
1417 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC,
1418 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1419 const RegisterClassInfo &RCI) {
1420 assert(SuperRC && "Invalid register class");
1422 const TargetRegisterClass *ConstrainedRC =
1423 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI,
1424 /* ExploreBundle */ true);
1427 return RCI.getNumAllocatableRegs(ConstrainedRC);
1430 /// tryInstructionSplit - Split a live range around individual instructions.
1431 /// This is normally not worthwhile since the spiller is doing essentially the
1432 /// same thing. However, when the live range is in a constrained register
1433 /// class, it may help to insert copies such that parts of the live range can
1434 /// be moved to a larger register class.
1436 /// This is similar to spilling to a larger register class.
1438 RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1439 SmallVectorImpl<unsigned> &NewVRegs) {
1440 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
1441 // There is no point to this if there are no larger sub-classes.
1442 if (!RegClassInfo.isProperSubClass(CurRC))
1445 // Always enable split spill mode, since we're effectively spilling to a
1447 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1448 SE->reset(LREdit, SplitEditor::SM_Size);
1450 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1451 if (Uses.size() <= 1)
1454 DEBUG(dbgs() << "Split around " << Uses.size() << " individual instrs.\n");
1456 const TargetRegisterClass *SuperRC = TRI->getLargestLegalSuperClass(CurRC);
1457 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC);
1458 // Split around every non-copy instruction if this split will relax
1459 // the constraints on the virtual register.
1460 // Otherwise, splitting just inserts uncoalescable copies that do not help
1462 for (unsigned i = 0; i != Uses.size(); ++i) {
1463 if (const MachineInstr *MI = Indexes->getInstructionFromIndex(Uses[i]))
1464 if (MI->isFullCopy() ||
1465 SuperRCNumAllocatableRegs ==
1466 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII,
1468 DEBUG(dbgs() << " skip:\t" << Uses[i] << '\t' << *MI);
1472 SlotIndex SegStart = SE->enterIntvBefore(Uses[i]);
1473 SlotIndex SegStop = SE->leaveIntvAfter(Uses[i]);
1474 SE->useIntv(SegStart, SegStop);
1477 if (LREdit.empty()) {
1478 DEBUG(dbgs() << "All uses were copies.\n");
1482 SmallVector<unsigned, 8> IntvMap;
1483 SE->finish(&IntvMap);
1484 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS);
1485 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1487 // Assign all new registers to RS_Spill. This was the last chance.
1488 setStage(LREdit.begin(), LREdit.end(), RS_Spill);
1493 //===----------------------------------------------------------------------===//
1495 //===----------------------------------------------------------------------===//
1498 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
1499 /// in order to use PhysReg between two entries in SA->UseSlots.
1501 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
1503 void RAGreedy::calcGapWeights(unsigned PhysReg,
1504 SmallVectorImpl<float> &GapWeight) {
1505 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1506 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1507 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1508 const unsigned NumGaps = Uses.size()-1;
1510 // Start and end points for the interference check.
1511 SlotIndex StartIdx =
1512 BI.LiveIn ? BI.FirstInstr.getBaseIndex() : BI.FirstInstr;
1514 BI.LiveOut ? BI.LastInstr.getBoundaryIndex() : BI.LastInstr;
1516 GapWeight.assign(NumGaps, 0.0f);
1518 // Add interference from each overlapping register.
1519 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1520 if (!Matrix->query(const_cast<LiveInterval&>(SA->getParent()), *Units)
1521 .checkInterference())
1524 // We know that VirtReg is a continuous interval from FirstInstr to
1525 // LastInstr, so we don't need InterferenceQuery.
1527 // Interference that overlaps an instruction is counted in both gaps
1528 // surrounding the instruction. The exception is interference before
1529 // StartIdx and after StopIdx.
1531 LiveIntervalUnion::SegmentIter IntI =
1532 Matrix->getLiveUnions()[*Units] .find(StartIdx);
1533 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
1534 // Skip the gaps before IntI.
1535 while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
1536 if (++Gap == NumGaps)
1541 // Update the gaps covered by IntI.
1542 const float weight = IntI.value()->weight;
1543 for (; Gap != NumGaps; ++Gap) {
1544 GapWeight[Gap] = std::max(GapWeight[Gap], weight);
1545 if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
1553 // Add fixed interference.
1554 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1555 const LiveRange &LR = LIS->getRegUnit(*Units);
1556 LiveRange::const_iterator I = LR.find(StartIdx);
1557 LiveRange::const_iterator E = LR.end();
1559 // Same loop as above. Mark any overlapped gaps as HUGE_VALF.
1560 for (unsigned Gap = 0; I != E && I->start < StopIdx; ++I) {
1561 while (Uses[Gap+1].getBoundaryIndex() < I->start)
1562 if (++Gap == NumGaps)
1567 for (; Gap != NumGaps; ++Gap) {
1568 GapWeight[Gap] = llvm::huge_valf;
1569 if (Uses[Gap+1].getBaseIndex() >= I->end)
1578 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
1581 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1582 SmallVectorImpl<unsigned> &NewVRegs) {
1583 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1584 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1586 // Note that it is possible to have an interval that is live-in or live-out
1587 // while only covering a single block - A phi-def can use undef values from
1588 // predecessors, and the block could be a single-block loop.
1589 // We don't bother doing anything clever about such a case, we simply assume
1590 // that the interval is continuous from FirstInstr to LastInstr. We should
1591 // make sure that we don't do anything illegal to such an interval, though.
1593 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1594 if (Uses.size() <= 2)
1596 const unsigned NumGaps = Uses.size()-1;
1599 dbgs() << "tryLocalSplit: ";
1600 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
1601 dbgs() << ' ' << Uses[i];
1605 // If VirtReg is live across any register mask operands, compute a list of
1606 // gaps with register masks.
1607 SmallVector<unsigned, 8> RegMaskGaps;
1608 if (Matrix->checkRegMaskInterference(VirtReg)) {
1609 // Get regmask slots for the whole block.
1610 ArrayRef<SlotIndex> RMS = LIS->getRegMaskSlotsInBlock(BI.MBB->getNumber());
1611 DEBUG(dbgs() << RMS.size() << " regmasks in block:");
1612 // Constrain to VirtReg's live range.
1613 unsigned ri = std::lower_bound(RMS.begin(), RMS.end(),
1614 Uses.front().getRegSlot()) - RMS.begin();
1615 unsigned re = RMS.size();
1616 for (unsigned i = 0; i != NumGaps && ri != re; ++i) {
1617 // Look for Uses[i] <= RMS <= Uses[i+1].
1618 assert(!SlotIndex::isEarlierInstr(RMS[ri], Uses[i]));
1619 if (SlotIndex::isEarlierInstr(Uses[i+1], RMS[ri]))
1621 // Skip a regmask on the same instruction as the last use. It doesn't
1622 // overlap the live range.
1623 if (SlotIndex::isSameInstr(Uses[i+1], RMS[ri]) && i+1 == NumGaps)
1625 DEBUG(dbgs() << ' ' << RMS[ri] << ':' << Uses[i] << '-' << Uses[i+1]);
1626 RegMaskGaps.push_back(i);
1627 // Advance ri to the next gap. A regmask on one of the uses counts in
1629 while (ri != re && SlotIndex::isEarlierInstr(RMS[ri], Uses[i+1]))
1632 DEBUG(dbgs() << '\n');
1635 // Since we allow local split results to be split again, there is a risk of
1636 // creating infinite loops. It is tempting to require that the new live
1637 // ranges have less instructions than the original. That would guarantee
1638 // convergence, but it is too strict. A live range with 3 instructions can be
1639 // split 2+3 (including the COPY), and we want to allow that.
1641 // Instead we use these rules:
1643 // 1. Allow any split for ranges with getStage() < RS_Split2. (Except for the
1644 // noop split, of course).
1645 // 2. Require progress be made for ranges with getStage() == RS_Split2. All
1646 // the new ranges must have fewer instructions than before the split.
1647 // 3. New ranges with the same number of instructions are marked RS_Split2,
1648 // smaller ranges are marked RS_New.
1650 // These rules allow a 3 -> 2+3 split once, which we need. They also prevent
1651 // excessive splitting and infinite loops.
1653 bool ProgressRequired = getStage(VirtReg) >= RS_Split2;
1655 // Best split candidate.
1656 unsigned BestBefore = NumGaps;
1657 unsigned BestAfter = 0;
1660 const float blockFreq =
1661 SpillPlacer->getBlockFrequency(BI.MBB->getNumber()).getFrequency() *
1662 (1.0f / MBFI->getEntryFreq());
1663 SmallVector<float, 8> GapWeight;
1666 while (unsigned PhysReg = Order.next()) {
1667 // Keep track of the largest spill weight that would need to be evicted in
1668 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
1669 calcGapWeights(PhysReg, GapWeight);
1671 // Remove any gaps with regmask clobbers.
1672 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
1673 for (unsigned i = 0, e = RegMaskGaps.size(); i != e; ++i)
1674 GapWeight[RegMaskGaps[i]] = llvm::huge_valf;
1676 // Try to find the best sequence of gaps to close.
1677 // The new spill weight must be larger than any gap interference.
1679 // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
1680 unsigned SplitBefore = 0, SplitAfter = 1;
1682 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
1683 // It is the spill weight that needs to be evicted.
1684 float MaxGap = GapWeight[0];
1687 // Live before/after split?
1688 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
1689 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
1691 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
1692 << Uses[SplitBefore] << '-' << Uses[SplitAfter]
1693 << " i=" << MaxGap);
1695 // Stop before the interval gets so big we wouldn't be making progress.
1696 if (!LiveBefore && !LiveAfter) {
1697 DEBUG(dbgs() << " all\n");
1700 // Should the interval be extended or shrunk?
1703 // How many gaps would the new range have?
1704 unsigned NewGaps = LiveBefore + SplitAfter - SplitBefore + LiveAfter;
1706 // Legally, without causing looping?
1707 bool Legal = !ProgressRequired || NewGaps < NumGaps;
1709 if (Legal && MaxGap < llvm::huge_valf) {
1710 // Estimate the new spill weight. Each instruction reads or writes the
1711 // register. Conservatively assume there are no read-modify-write
1714 // Try to guess the size of the new interval.
1715 const float EstWeight = normalizeSpillWeight(blockFreq * (NewGaps + 1),
1716 Uses[SplitBefore].distance(Uses[SplitAfter]) +
1717 (LiveBefore + LiveAfter)*SlotIndex::InstrDist);
1718 // Would this split be possible to allocate?
1719 // Never allocate all gaps, we wouldn't be making progress.
1720 DEBUG(dbgs() << " w=" << EstWeight);
1721 if (EstWeight * Hysteresis >= MaxGap) {
1723 float Diff = EstWeight - MaxGap;
1724 if (Diff > BestDiff) {
1725 DEBUG(dbgs() << " (best)");
1726 BestDiff = Hysteresis * Diff;
1727 BestBefore = SplitBefore;
1728 BestAfter = SplitAfter;
1735 if (++SplitBefore < SplitAfter) {
1736 DEBUG(dbgs() << " shrink\n");
1737 // Recompute the max when necessary.
1738 if (GapWeight[SplitBefore - 1] >= MaxGap) {
1739 MaxGap = GapWeight[SplitBefore];
1740 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
1741 MaxGap = std::max(MaxGap, GapWeight[i]);
1748 // Try to extend the interval.
1749 if (SplitAfter >= NumGaps) {
1750 DEBUG(dbgs() << " end\n");
1754 DEBUG(dbgs() << " extend\n");
1755 MaxGap = std::max(MaxGap, GapWeight[SplitAfter++]);
1759 // Didn't find any candidates?
1760 if (BestBefore == NumGaps)
1763 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
1764 << '-' << Uses[BestAfter] << ", " << BestDiff
1765 << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
1767 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1771 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
1772 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
1773 SE->useIntv(SegStart, SegStop);
1774 SmallVector<unsigned, 8> IntvMap;
1775 SE->finish(&IntvMap);
1776 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS);
1778 // If the new range has the same number of instructions as before, mark it as
1779 // RS_Split2 so the next split will be forced to make progress. Otherwise,
1780 // leave the new intervals as RS_New so they can compete.
1781 bool LiveBefore = BestBefore != 0 || BI.LiveIn;
1782 bool LiveAfter = BestAfter != NumGaps || BI.LiveOut;
1783 unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter;
1784 if (NewGaps >= NumGaps) {
1785 DEBUG(dbgs() << "Tagging non-progress ranges: ");
1786 assert(!ProgressRequired && "Didn't make progress when it was required.");
1787 for (unsigned i = 0, e = IntvMap.size(); i != e; ++i)
1788 if (IntvMap[i] == 1) {
1789 setStage(LIS->getInterval(LREdit.get(i)), RS_Split2);
1790 DEBUG(dbgs() << PrintReg(LREdit.get(i)));
1792 DEBUG(dbgs() << '\n');
1799 //===----------------------------------------------------------------------===//
1800 // Live Range Splitting
1801 //===----------------------------------------------------------------------===//
1803 /// trySplit - Try to split VirtReg or one of its interferences, making it
1805 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1806 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1807 SmallVectorImpl<unsigned>&NewVRegs) {
1808 // Ranges must be Split2 or less.
1809 if (getStage(VirtReg) >= RS_Spill)
1812 // Local intervals are handled separately.
1813 if (LIS->intervalIsInOneMBB(VirtReg)) {
1814 NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled);
1815 SA->analyze(&VirtReg);
1816 unsigned PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
1817 if (PhysReg || !NewVRegs.empty())
1819 return tryInstructionSplit(VirtReg, Order, NewVRegs);
1822 NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
1824 SA->analyze(&VirtReg);
1826 // FIXME: SplitAnalysis may repair broken live ranges coming from the
1827 // coalescer. That may cause the range to become allocatable which means that
1828 // tryRegionSplit won't be making progress. This check should be replaced with
1829 // an assertion when the coalescer is fixed.
1830 if (SA->didRepairRange()) {
1831 // VirtReg has changed, so all cached queries are invalid.
1832 Matrix->invalidateVirtRegs();
1833 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1837 // First try to split around a region spanning multiple blocks. RS_Split2
1838 // ranges already made dubious progress with region splitting, so they go
1839 // straight to single block splitting.
1840 if (getStage(VirtReg) < RS_Split2) {
1841 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1842 if (PhysReg || !NewVRegs.empty())
1846 // Then isolate blocks.
1847 return tryBlockSplit(VirtReg, Order, NewVRegs);
1850 //===----------------------------------------------------------------------===//
1851 // Last Chance Recoloring
1852 //===----------------------------------------------------------------------===//
1854 /// mayRecolorAllInterferences - Check if the virtual registers that
1855 /// interfere with \p VirtReg on \p PhysReg (or one of its aliases) may be
1856 /// recolored to free \p PhysReg.
1857 /// When true is returned, \p RecoloringCandidates has been augmented with all
1858 /// the live intervals that need to be recolored in order to free \p PhysReg
1860 /// \p FixedRegisters contains all the virtual registers that cannot be
1863 RAGreedy::mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
1864 SmallLISet &RecoloringCandidates,
1865 const SmallVirtRegSet &FixedRegisters) {
1866 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
1868 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1869 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
1870 // If there is LastChanceRecoloringMaxInterference or more interferences,
1871 // chances are one would not be recolorable.
1872 if (Q.collectInterferingVRegs(LastChanceRecoloringMaxInterference) >=
1873 LastChanceRecoloringMaxInterference) {
1874 DEBUG(dbgs() << "Early abort: too many interferences.\n");
1877 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
1878 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
1879 // If Intf is done and sit on the same register class as VirtReg,
1880 // it would not be recolorable as it is in the same state as VirtReg.
1881 if ((getStage(*Intf) == RS_Done &&
1882 MRI->getRegClass(Intf->reg) == CurRC) ||
1883 FixedRegisters.count(Intf->reg)) {
1884 DEBUG(dbgs() << "Early abort: the inteference is not recolorable.\n");
1887 RecoloringCandidates.insert(Intf);
1893 /// tryLastChanceRecoloring - Try to assign a color to \p VirtReg by recoloring
1894 /// its interferences.
1895 /// Last chance recoloring chooses a color for \p VirtReg and recolors every
1896 /// virtual register that was using it. The recoloring process may recursively
1897 /// use the last chance recoloring. Therefore, when a virtual register has been
1898 /// assigned a color by this mechanism, it is marked as Fixed, i.e., it cannot
1899 /// be last-chance-recolored again during this recoloring "session".
1902 /// vA can use {R1, R2 }
1903 /// vB can use { R2, R3}
1904 /// vC can use {R1 }
1905 /// Where vA, vB, and vC cannot be split anymore (they are reloads for
1906 /// instance) and they all interfere.
1908 /// vA is assigned R1
1909 /// vB is assigned R2
1910 /// vC tries to evict vA but vA is already done.
1911 /// Regular register allocation fails.
1913 /// Last chance recoloring kicks in:
1914 /// vC does as if vA was evicted => vC uses R1.
1915 /// vC is marked as fixed.
1916 /// vA needs to find a color.
1917 /// None are available.
1918 /// vA cannot evict vC: vC is a fixed virtual register now.
1919 /// vA does as if vB was evicted => vA uses R2.
1920 /// vB needs to find a color.
1921 /// R3 is available.
1922 /// Recoloring => vC = R1, vA = R2, vB = R3
1924 /// \p Order defines the preferred allocation order for \p VirtReg.
1925 /// \p NewRegs will contain any new virtual register that have been created
1926 /// (split, spill) during the process and that must be assigned.
1927 /// \p FixedRegisters contains all the virtual registers that cannot be
1929 /// \p Depth gives the current depth of the last chance recoloring.
1930 /// \return a physical register that can be used for VirtReg or ~0u if none
1932 unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg,
1933 AllocationOrder &Order,
1934 SmallVectorImpl<unsigned> &NewVRegs,
1935 SmallVirtRegSet &FixedRegisters,
1937 DEBUG(dbgs() << "Try last chance recoloring for " << VirtReg << '\n');
1938 // Ranges must be Done.
1939 assert((getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) &&
1940 "Last chance recoloring should really be last chance");
1941 // Set the max depth to LastChanceRecoloringMaxDepth.
1942 // We may want to reconsider that if we end up with a too large search space
1943 // for target with hundreds of registers.
1944 // Indeed, in that case we may want to cut the search space earlier.
1945 if (Depth >= LastChanceRecoloringMaxDepth) {
1946 DEBUG(dbgs() << "Abort because max depth has been reached.\n");
1950 // Set of Live intervals that will need to be recolored.
1951 SmallLISet RecoloringCandidates;
1952 // Record the original mapping virtual register to physical register in case
1953 // the recoloring fails.
1954 DenseMap<unsigned, unsigned> VirtRegToPhysReg;
1955 // Mark VirtReg as fixed, i.e., it will not be recolored pass this point in
1956 // this recoloring "session".
1957 FixedRegisters.insert(VirtReg.reg);
1960 while (unsigned PhysReg = Order.next()) {
1961 DEBUG(dbgs() << "Try to assign: " << VirtReg << " to "
1962 << PrintReg(PhysReg, TRI) << '\n');
1963 RecoloringCandidates.clear();
1964 VirtRegToPhysReg.clear();
1966 // It is only possible to recolor virtual register interference.
1967 if (Matrix->checkInterference(VirtReg, PhysReg) >
1968 LiveRegMatrix::IK_VirtReg) {
1969 DEBUG(dbgs() << "Some inteferences are not with virtual registers.\n");
1974 // Early give up on this PhysReg if it is obvious we cannot recolor all
1975 // the interferences.
1976 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates,
1978 DEBUG(dbgs() << "Some inteferences cannot be recolored.\n");
1982 // RecoloringCandidates contains all the virtual registers that interfer
1983 // with VirtReg on PhysReg (or one of its aliases).
1984 // Enqueue them for recoloring and perform the actual recoloring.
1985 PQueue RecoloringQueue;
1986 for (SmallLISet::iterator It = RecoloringCandidates.begin(),
1987 EndIt = RecoloringCandidates.end();
1988 It != EndIt; ++It) {
1989 unsigned ItVirtReg = (*It)->reg;
1990 enqueue(RecoloringQueue, *It);
1991 assert(VRM->hasPhys(ItVirtReg) &&
1992 "Interferences are supposed to be with allocated vairables");
1994 // Record the current allocation.
1995 VirtRegToPhysReg[ItVirtReg] = VRM->getPhys(ItVirtReg);
1996 // unset the related struct.
1997 Matrix->unassign(**It);
2000 // Do as if VirtReg was assigned to PhysReg so that the underlying
2001 // recoloring has the right information about the interferes and
2002 // available colors.
2003 Matrix->assign(VirtReg, PhysReg);
2005 // Save the current recoloring state.
2006 // If we cannot recolor all the interferences, we will have to start again
2007 // at this point for the next physical register.
2008 SmallVirtRegSet SaveFixedRegisters(FixedRegisters);
2009 if (tryRecoloringCandidates(RecoloringQueue, NewVRegs, FixedRegisters,
2011 // Do not mess up with the global assignment process.
2012 // I.e., VirtReg must be unassigned.
2013 Matrix->unassign(VirtReg);
2017 DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to "
2018 << PrintReg(PhysReg, TRI) << '\n');
2020 // The recoloring attempt failed, undo the changes.
2021 FixedRegisters = SaveFixedRegisters;
2022 Matrix->unassign(VirtReg);
2024 for (SmallLISet::iterator It = RecoloringCandidates.begin(),
2025 EndIt = RecoloringCandidates.end();
2026 It != EndIt; ++It) {
2027 unsigned ItVirtReg = (*It)->reg;
2028 if (VRM->hasPhys(ItVirtReg))
2029 Matrix->unassign(**It);
2030 Matrix->assign(**It, VirtRegToPhysReg[ItVirtReg]);
2034 // Last chance recoloring did not worked either, give up.
2038 /// tryRecoloringCandidates - Try to assign a new color to every register
2039 /// in \RecoloringQueue.
2040 /// \p NewRegs will contain any new virtual register created during the
2041 /// recoloring process.
2042 /// \p FixedRegisters[in/out] contains all the registers that have been
2044 /// \return true if all virtual registers in RecoloringQueue were successfully
2045 /// recolored, false otherwise.
2046 bool RAGreedy::tryRecoloringCandidates(PQueue &RecoloringQueue,
2047 SmallVectorImpl<unsigned> &NewVRegs,
2048 SmallVirtRegSet &FixedRegisters,
2050 while (!RecoloringQueue.empty()) {
2051 LiveInterval *LI = dequeue(RecoloringQueue);
2052 DEBUG(dbgs() << "Try to recolor: " << *LI << '\n');
2054 PhysReg = selectOrSplitImpl(*LI, NewVRegs, FixedRegisters, Depth + 1);
2055 if (PhysReg == ~0u || !PhysReg)
2057 DEBUG(dbgs() << "Recoloring of " << *LI
2058 << " succeeded with: " << PrintReg(PhysReg, TRI) << '\n');
2059 Matrix->assign(*LI, PhysReg);
2060 FixedRegisters.insert(LI->reg);
2065 //===----------------------------------------------------------------------===//
2067 //===----------------------------------------------------------------------===//
2069 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
2070 SmallVectorImpl<unsigned> &NewVRegs) {
2071 SmallVirtRegSet FixedRegisters;
2072 return selectOrSplitImpl(VirtReg, NewVRegs, FixedRegisters);
2075 unsigned RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg,
2076 SmallVectorImpl<unsigned> &NewVRegs,
2077 SmallVirtRegSet &FixedRegisters,
2079 // First try assigning a free register.
2080 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
2081 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
2084 LiveRangeStage Stage = getStage(VirtReg);
2085 DEBUG(dbgs() << StageName[Stage]
2086 << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n');
2088 // Try to evict a less worthy live range, but only for ranges from the primary
2089 // queue. The RS_Split ranges already failed to do this, and they should not
2090 // get a second chance until they have been split.
2091 if (Stage != RS_Split)
2092 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
2095 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
2097 // The first time we see a live range, don't try to split or spill.
2098 // Wait until the second time, when all smaller ranges have been allocated.
2099 // This gives a better picture of the interference to split around.
2100 if (Stage < RS_Split) {
2101 setStage(VirtReg, RS_Split);
2102 DEBUG(dbgs() << "wait for second round\n");
2103 NewVRegs.push_back(VirtReg.reg);
2107 // If we couldn't allocate a register from spilling, there is probably some
2108 // invalid inline assembly. The base class wil report it.
2109 if (Stage >= RS_Done || !VirtReg.isSpillable())
2110 return tryLastChanceRecoloring(VirtReg, Order, NewVRegs, FixedRegisters,
2113 // Try splitting VirtReg or interferences.
2114 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
2115 if (PhysReg || !NewVRegs.empty())
2118 // Finally spill VirtReg itself.
2119 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
2120 LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
2121 spiller().spill(LRE);
2122 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done);
2125 MF->verify(this, "After spilling");
2127 // The live virtual register requesting allocation was spilled, so tell
2128 // the caller not to allocate anything during this round.
2132 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
2133 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
2134 << "********** Function: " << mf.getName() << '\n');
2137 TRI = MF->getTarget().getRegisterInfo();
2138 TII = MF->getTarget().getInstrInfo();
2139 RCI.runOnMachineFunction(mf);
2141 MF->verify(this, "Before greedy register allocator");
2143 RegAllocBase::init(getAnalysis<VirtRegMap>(),
2144 getAnalysis<LiveIntervals>(),
2145 getAnalysis<LiveRegMatrix>());
2146 Indexes = &getAnalysis<SlotIndexes>();
2147 MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
2148 DomTree = &getAnalysis<MachineDominatorTree>();
2149 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
2150 Loops = &getAnalysis<MachineLoopInfo>();
2151 Bundles = &getAnalysis<EdgeBundles>();
2152 SpillPlacer = &getAnalysis<SpillPlacement>();
2153 DebugVars = &getAnalysis<LiveDebugVariables>();
2155 calculateSpillWeightsAndHints(*LIS, mf, *Loops, *MBFI);
2159 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
2160 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree, *MBFI));
2161 ExtraRegInfo.clear();
2162 ExtraRegInfo.resize(MRI->getNumVirtRegs());
2164 IntfCache.init(MF, Matrix->getLiveUnions(), Indexes, LIS, TRI);
2165 GlobalCand.resize(32); // This will grow as needed.