1 //===-- RegAllocBasic.cpp - basic register allocator ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RABasic function pass, which provides a minimal
11 // implementation of the basic register allocator.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "LiveDebugVariables.h"
17 #include "LiveIntervalUnion.h"
18 #include "LiveRangeEdit.h"
19 #include "RegAllocBase.h"
20 #include "RenderMachineFunction.h"
22 #include "VirtRegMap.h"
23 #include "llvm/ADT/OwningPtr.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Function.h"
27 #include "llvm/PassAnalysisSupport.h"
28 #include "llvm/CodeGen/CalcSpillWeights.h"
29 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
30 #include "llvm/CodeGen/LiveStackAnalysis.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineLoopInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/CodeGen/RegAllocRegistry.h"
37 #include "llvm/CodeGen/RegisterCoalescer.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/ADT/SparseBitVector.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/raw_ostream.h"
47 #include "llvm/Support/Timer.h"
54 STATISTIC(NumAssigned , "Number of registers assigned");
55 STATISTIC(NumUnassigned , "Number of registers unassigned");
56 STATISTIC(NumNewQueued , "Number of new live ranges queued");
58 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
59 createBasicRegisterAllocator);
61 // Temporary verification option until we can put verification inside
63 static cl::opt<bool, true>
64 VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
65 cl::desc("Verify during register allocation"));
67 const char *RegAllocBase::TimerGroupName = "Register Allocation";
68 bool RegAllocBase::VerifyEnabled = false;
71 struct CompSpillWeight {
72 bool operator()(LiveInterval *A, LiveInterval *B) const {
73 return A->weight < B->weight;
79 /// RABasic provides a minimal implementation of the basic register allocation
80 /// algorithm. It prioritizes live virtual registers by spill weight and spills
81 /// whenever a register is unavailable. This is not practical in production but
82 /// provides a useful baseline both for measuring other allocators and comparing
83 /// the speed of the basic algorithm against other styles of allocators.
84 class RABasic : public MachineFunctionPass, public RegAllocBase
88 BitVector ReservedRegs;
92 RenderMachineFunction *RMF;
95 std::auto_ptr<Spiller> SpillerInstance;
96 std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
97 CompSpillWeight> Queue;
101 /// Return the pass name.
102 virtual const char* getPassName() const {
103 return "Basic Register Allocator";
106 /// RABasic analysis usage.
107 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
109 virtual void releaseMemory();
111 virtual Spiller &spiller() { return *SpillerInstance; }
113 virtual float getPriority(LiveInterval *LI) { return LI->weight; }
115 virtual void enqueue(LiveInterval *LI) {
119 virtual LiveInterval *dequeue() {
122 LiveInterval *LI = Queue.top();
127 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
128 SmallVectorImpl<LiveInterval*> &SplitVRegs);
130 /// Perform register allocation.
131 virtual bool runOnMachineFunction(MachineFunction &mf);
136 char RABasic::ID = 0;
138 } // end anonymous namespace
140 RABasic::RABasic(): MachineFunctionPass(ID) {
141 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
142 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
143 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
144 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
145 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
146 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
147 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
148 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
149 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
150 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
151 initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
154 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
155 AU.setPreservesCFG();
156 AU.addRequired<AliasAnalysis>();
157 AU.addPreserved<AliasAnalysis>();
158 AU.addRequired<LiveIntervals>();
159 AU.addPreserved<SlotIndexes>();
160 AU.addRequired<LiveDebugVariables>();
161 AU.addPreserved<LiveDebugVariables>();
163 AU.addRequiredID(StrongPHIEliminationID);
164 AU.addRequiredTransitive<RegisterCoalescer>();
165 AU.addRequired<CalculateSpillWeights>();
166 AU.addRequired<LiveStacks>();
167 AU.addPreserved<LiveStacks>();
168 AU.addRequiredID(MachineDominatorsID);
169 AU.addPreservedID(MachineDominatorsID);
170 AU.addRequired<MachineLoopInfo>();
171 AU.addPreserved<MachineLoopInfo>();
172 AU.addRequired<VirtRegMap>();
173 AU.addPreserved<VirtRegMap>();
174 DEBUG(AU.addRequired<RenderMachineFunction>());
175 MachineFunctionPass::getAnalysisUsage(AU);
178 void RABasic::releaseMemory() {
179 SpillerInstance.reset(0);
180 RegAllocBase::releaseMemory();
184 // Verify each LiveIntervalUnion.
185 void RegAllocBase::verify() {
186 LiveVirtRegBitSet VisitedVRegs;
187 OwningArrayPtr<LiveVirtRegBitSet>
188 unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]);
190 // Verify disjoint unions.
191 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
192 DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
193 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
194 PhysReg2LiveUnion[PhysReg].verify(VRegs);
195 // Union + intersection test could be done efficiently in one pass, but
196 // don't add a method to SparseBitVector unless we really need it.
197 assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
198 VisitedVRegs |= VRegs;
201 // Verify vreg coverage.
202 for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
203 liItr != liEnd; ++liItr) {
204 unsigned reg = liItr->first;
205 if (TargetRegisterInfo::isPhysicalRegister(reg)) continue;
206 if (!VRM->hasPhys(reg)) continue; // spilled?
207 unsigned PhysReg = VRM->getPhys(reg);
208 if (!unionVRegs[PhysReg].test(reg)) {
209 dbgs() << "LiveVirtReg " << reg << " not in union " <<
210 TRI->getName(PhysReg) << "\n";
211 llvm_unreachable("unallocated live vreg");
214 // FIXME: I'm not sure how to verify spilled intervals.
218 //===----------------------------------------------------------------------===//
219 // RegAllocBase Implementation
220 //===----------------------------------------------------------------------===//
222 // Instantiate a LiveIntervalUnion for each physical register.
223 void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
227 static_cast<LiveIntervalUnion*>(malloc(sizeof(LiveIntervalUnion)*NRegs));
228 for (unsigned r = 0; r != NRegs; ++r)
229 new(Array + r) LiveIntervalUnion(r, allocator);
232 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
233 NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
234 TRI = &vrm.getTargetRegInfo();
235 MRI = &vrm.getRegInfo();
238 const unsigned NumRegs = TRI->getNumRegs();
239 if (NumRegs != PhysReg2LiveUnion.numRegs()) {
240 PhysReg2LiveUnion.init(UnionAllocator, NumRegs);
241 // Cache an interferece query for each physical reg
242 Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]);
246 void RegAllocBase::LiveUnionArray::clear() {
249 for (unsigned r = 0; r != NumRegs; ++r)
250 Array[r].~LiveIntervalUnion();
256 void RegAllocBase::releaseMemory() {
257 for (unsigned r = 0, e = PhysReg2LiveUnion.numRegs(); r != e; ++r)
258 PhysReg2LiveUnion[r].clear();
261 // Visit all the live registers. If they are already assigned to a physical
262 // register, unify them with the corresponding LiveIntervalUnion, otherwise push
263 // them on the priority queue for later assignment.
264 void RegAllocBase::seedLiveRegs() {
265 NamedRegionTimer T("Seed Live Regs", TimerGroupName, TimePassesIsEnabled);
266 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
267 unsigned RegNum = I->first;
268 LiveInterval &VirtReg = *I->second;
269 if (TargetRegisterInfo::isPhysicalRegister(RegNum))
270 PhysReg2LiveUnion[RegNum].unify(VirtReg);
276 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
277 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
278 << " to " << PrintReg(PhysReg, TRI) << '\n');
279 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
280 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
281 MRI->setPhysRegUsed(PhysReg);
282 PhysReg2LiveUnion[PhysReg].unify(VirtReg);
286 void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) {
287 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
288 << " from " << PrintReg(PhysReg, TRI) << '\n');
289 assert(VRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign");
290 PhysReg2LiveUnion[PhysReg].extract(VirtReg);
291 VRM->clearVirt(VirtReg.reg);
295 // Top-level driver to manage the queue of unassigned VirtRegs and call the
296 // selectOrSplit implementation.
297 void RegAllocBase::allocatePhysRegs() {
300 // Continue assigning vregs one at a time to available physical registers.
301 while (LiveInterval *VirtReg = dequeue()) {
302 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
304 // Unused registers can appear when the spiller coalesces snippets.
305 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
306 DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
307 LIS->removeInterval(VirtReg->reg);
311 // Invalidate all interference queries, live ranges could have changed.
312 invalidateVirtRegs();
314 // selectOrSplit requests the allocator to return an available physical
315 // register if possible and populate a list of new live intervals that
316 // result from splitting.
317 DEBUG(dbgs() << "\nselectOrSplit "
318 << MRI->getRegClass(VirtReg->reg)->getName()
319 << ':' << *VirtReg << '\n');
320 typedef SmallVector<LiveInterval*, 4> VirtRegVec;
321 VirtRegVec SplitVRegs;
322 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
324 if (AvailablePhysReg == ~0u) {
325 // selectOrSplit failed to find a register!
327 raw_string_ostream Msg(msg);
328 Msg << "Ran out of registers during register allocation!"
329 "\nCannot allocate: " << *VirtReg;
330 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg);
331 MachineInstr *MI = I.skipInstruction();) {
332 if (!MI->isInlineAsm())
334 Msg << "\nPlease check your inline asm statement for "
335 "invalid constraints:\n";
336 MI->print(Msg, &VRM->getMachineFunction().getTarget());
338 report_fatal_error(Msg.str());
341 if (AvailablePhysReg)
342 assign(*VirtReg, AvailablePhysReg);
344 for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
346 LiveInterval *SplitVirtReg = *I;
347 assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
348 if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
349 DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n');
350 LIS->removeInterval(SplitVirtReg->reg);
353 DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
354 assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
355 "expect split value in virtual register");
356 enqueue(SplitVirtReg);
362 // Check if this live virtual register interferes with a physical register. If
363 // not, then check for interference on each register that aliases with the
364 // physical register. Return the interfering register.
365 unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg,
367 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
368 if (query(VirtReg, *AliasI).checkInterference())
373 // Helper for spillInteferences() that spills all interfering vregs currently
374 // assigned to this physical register.
375 void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
376 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
377 LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
378 assert(Q.seenAllInterferences() && "need collectInterferences()");
379 const SmallVectorImpl<LiveInterval*> &PendingSpills = Q.interferingVRegs();
381 for (SmallVectorImpl<LiveInterval*>::const_iterator I = PendingSpills.begin(),
382 E = PendingSpills.end(); I != E; ++I) {
383 LiveInterval &SpilledVReg = **I;
384 DEBUG(dbgs() << "extracting from " <<
385 TRI->getName(PhysReg) << " " << SpilledVReg << '\n');
387 // Deallocate the interfering vreg by removing it from the union.
388 // A LiveInterval instance may not be in a union during modification!
389 unassign(SpilledVReg, PhysReg);
391 // Spill the extracted interval.
392 LiveRangeEdit LRE(SpilledVReg, SplitVRegs, 0, &PendingSpills);
393 spiller().spill(LRE);
395 // After extracting segments, the query's results are invalid. But keep the
396 // contents valid until we're done accessing pendingSpills.
400 // Spill or split all live virtual registers currently unified under PhysReg
401 // that interfere with VirtReg. The newly spilled or split live intervals are
402 // returned by appending them to SplitVRegs.
404 RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
405 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
406 // Record each interference and determine if all are spillable before mutating
407 // either the union or live intervals.
408 unsigned NumInterferences = 0;
409 // Collect interferences assigned to any alias of the physical register.
410 for (const unsigned *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
411 LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
412 NumInterferences += QAlias.collectInterferingVRegs();
413 if (QAlias.seenUnspillableVReg()) {
417 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
418 " interferences with " << VirtReg << "\n");
419 assert(NumInterferences > 0 && "expect interference");
421 // Spill each interfering vreg allocated to PhysReg or an alias.
422 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
423 spillReg(VirtReg, *AliasI, SplitVRegs);
427 // Add newly allocated physical registers to the MBB live in sets.
428 void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
429 NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled);
430 SlotIndexes *Indexes = LIS->getSlotIndexes();
434 LiveIntervalUnion::SegmentIter SI;
435 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
436 LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg];
437 if (LiveUnion.empty())
439 MachineFunction::iterator MBB = llvm::next(MF->begin());
440 MachineFunction::iterator MFE = MF->end();
441 SlotIndex Start, Stop;
442 tie(Start, Stop) = Indexes->getMBBRange(MBB);
443 SI.setMap(LiveUnion.getMap());
446 if (SI.start() <= Start) {
447 if (!MBB->isLiveIn(PhysReg))
448 MBB->addLiveIn(PhysReg);
449 } else if (SI.start() > Stop)
450 MBB = Indexes->getMBBFromIndex(SI.start().getPrevIndex());
453 tie(Start, Stop) = Indexes->getMBBRange(MBB);
460 //===----------------------------------------------------------------------===//
461 // RABasic Implementation
462 //===----------------------------------------------------------------------===//
464 // Driver for the register assignment and splitting heuristics.
465 // Manages iteration over the LiveIntervalUnions.
467 // This is a minimal implementation of register assignment and splitting that
468 // spills whenever we run out of registers.
470 // selectOrSplit can only be called once per live virtual register. We then do a
471 // single interference test for each register the correct class until we find an
472 // available register. So, the number of interference tests in the worst case is
473 // |vregs| * |machineregs|. And since the number of interference tests is
474 // minimal, there is no value in caching them outside the scope of
476 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
477 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
478 // Populate a list of physical register spill candidates.
479 SmallVector<unsigned, 8> PhysRegSpillCands;
481 // Check for an available register in this class.
482 const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
484 for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
485 E = TRC->allocation_order_end(*MF);
488 unsigned PhysReg = *I;
489 if (ReservedRegs.test(PhysReg)) continue;
491 // Check interference and as a side effect, intialize queries for this
492 // VirtReg and its aliases.
493 unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
494 if (interfReg == 0) {
495 // Found an available register.
498 LiveInterval *interferingVirtReg =
499 Queries[interfReg].firstInterference().liveUnionPos().value();
501 // The current VirtReg must either be spillable, or one of its interferences
502 // must have less spill weight.
503 if (interferingVirtReg->weight < VirtReg.weight ) {
504 PhysRegSpillCands.push_back(PhysReg);
507 // Try to spill another interfering reg with less spill weight.
508 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
509 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
511 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
513 assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
514 "Interference after spill.");
515 // Tell the caller to allocate to this newly freed physical register.
519 // No other spill candidates were found, so spill the current VirtReg.
520 DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
521 if (!VirtReg.isSpillable())
523 LiveRangeEdit LRE(VirtReg, SplitVRegs);
524 spiller().spill(LRE);
526 // The live virtual register requesting allocation was spilled, so tell
527 // the caller not to allocate anything during this round.
531 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
532 DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
533 << "********** Function: "
534 << ((Value*)mf.getFunction())->getName() << '\n');
537 DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
539 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
541 ReservedRegs = TRI->getReservedRegs(*MF);
543 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
549 // Diagnostic output before rewriting
550 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
552 // optional HTML output
553 DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
555 // FIXME: Verification currently must run before VirtRegRewriter. We should
556 // make the rewriter a separate pass and override verifyAnalysis instead. When
557 // that happens, verification naturally falls under VerifyMachineCode.
560 // Verify accuracy of LiveIntervals. The standard machine code verifier
561 // ensures that each LiveIntervals covers all uses of the virtual reg.
563 // FIXME: MachineVerifier is badly broken when using the standard
564 // spiller. Always use -spiller=inline with -verify-regalloc. Even with the
565 // inline spiller, some tests fail to verify because the coalescer does not
566 // always generate verifiable code.
567 MF->verify(this, "In RABasic::verify");
569 // Verify that LiveIntervals are partitioned into unions and disjoint within
576 VRM->rewrite(LIS->getSlotIndexes());
578 // Write out new DBG_VALUE instructions.
579 getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
581 // The pass output is in VirtRegMap. Release all the transient data.
587 FunctionPass* llvm::createBasicRegisterAllocator()
589 return new RABasic();