1 //===-- RegAllocBasic.cpp - Basic Register Allocator ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RABasic function pass, which provides a minimal
11 // implementation of the basic register allocator.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "RegAllocBase.h"
17 #include "LiveDebugVariables.h"
18 #include "LiveRangeEdit.h"
19 #include "RenderMachineFunction.h"
21 #include "VirtRegMap.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/Function.h"
24 #include "llvm/PassAnalysisSupport.h"
25 #include "llvm/CodeGen/CalcSpillWeights.h"
26 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
27 #include "llvm/CodeGen/LiveStackAnalysis.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineLoopInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/CodeGen/RegAllocRegistry.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/raw_ostream.h"
45 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
46 createBasicRegisterAllocator);
49 struct CompSpillWeight {
50 bool operator()(LiveInterval *A, LiveInterval *B) const {
51 return A->weight < B->weight;
57 /// RABasic provides a minimal implementation of the basic register allocation
58 /// algorithm. It prioritizes live virtual registers by spill weight and spills
59 /// whenever a register is unavailable. This is not practical in production but
60 /// provides a useful baseline both for measuring other allocators and comparing
61 /// the speed of the basic algorithm against other styles of allocators.
62 class RABasic : public MachineFunctionPass, public RegAllocBase
69 RenderMachineFunction *RMF;
72 std::auto_ptr<Spiller> SpillerInstance;
73 std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
74 CompSpillWeight> Queue;
78 /// Return the pass name.
79 virtual const char* getPassName() const {
80 return "Basic Register Allocator";
83 /// RABasic analysis usage.
84 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
86 virtual void releaseMemory();
88 virtual Spiller &spiller() { return *SpillerInstance; }
90 virtual float getPriority(LiveInterval *LI) { return LI->weight; }
92 virtual void enqueue(LiveInterval *LI) {
96 virtual LiveInterval *dequeue() {
99 LiveInterval *LI = Queue.top();
104 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
105 SmallVectorImpl<LiveInterval*> &SplitVRegs);
107 /// Perform register allocation.
108 virtual bool runOnMachineFunction(MachineFunction &mf);
110 // Helper for spilling all live virtual registers currently unified under preg
111 // that interfere with the most recently queried lvr. Return true if spilling
112 // was successful, and append any new spilled/split intervals to splitLVRs.
113 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
114 SmallVectorImpl<LiveInterval*> &SplitVRegs);
116 void spillReg(LiveInterval &VirtReg, unsigned PhysReg,
117 SmallVectorImpl<LiveInterval*> &SplitVRegs);
122 char RABasic::ID = 0;
124 } // end anonymous namespace
126 RABasic::RABasic(): MachineFunctionPass(ID) {
127 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
128 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
129 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
130 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
131 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
132 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
133 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
134 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
135 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
136 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
137 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
138 initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
141 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
142 AU.setPreservesCFG();
143 AU.addRequired<AliasAnalysis>();
144 AU.addPreserved<AliasAnalysis>();
145 AU.addRequired<LiveIntervals>();
146 AU.addPreserved<SlotIndexes>();
147 AU.addRequired<LiveDebugVariables>();
148 AU.addPreserved<LiveDebugVariables>();
150 AU.addRequiredID(StrongPHIEliminationID);
151 AU.addRequiredTransitiveID(RegisterCoalescerPassID);
152 AU.addRequired<CalculateSpillWeights>();
153 AU.addRequired<LiveStacks>();
154 AU.addPreserved<LiveStacks>();
155 AU.addRequiredID(MachineDominatorsID);
156 AU.addPreservedID(MachineDominatorsID);
157 AU.addRequired<MachineLoopInfo>();
158 AU.addPreserved<MachineLoopInfo>();
159 AU.addRequired<VirtRegMap>();
160 AU.addPreserved<VirtRegMap>();
161 DEBUG(AU.addRequired<RenderMachineFunction>());
162 MachineFunctionPass::getAnalysisUsage(AU);
165 void RABasic::releaseMemory() {
166 SpillerInstance.reset(0);
167 RegAllocBase::releaseMemory();
170 // Helper for spillInterferences() that spills all interfering vregs currently
171 // assigned to this physical register.
172 void RABasic::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
173 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
174 LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
175 assert(Q.seenAllInterferences() && "need collectInterferences()");
176 const SmallVectorImpl<LiveInterval*> &PendingSpills = Q.interferingVRegs();
178 for (SmallVectorImpl<LiveInterval*>::const_iterator I = PendingSpills.begin(),
179 E = PendingSpills.end(); I != E; ++I) {
180 LiveInterval &SpilledVReg = **I;
181 DEBUG(dbgs() << "extracting from " <<
182 TRI->getName(PhysReg) << " " << SpilledVReg << '\n');
184 // Deallocate the interfering vreg by removing it from the union.
185 // A LiveInterval instance may not be in a union during modification!
186 unassign(SpilledVReg, PhysReg);
188 // Spill the extracted interval.
189 LiveRangeEdit LRE(SpilledVReg, SplitVRegs, 0, &PendingSpills);
190 spiller().spill(LRE);
192 // After extracting segments, the query's results are invalid. But keep the
193 // contents valid until we're done accessing pendingSpills.
197 // Spill or split all live virtual registers currently unified under PhysReg
198 // that interfere with VirtReg. The newly spilled or split live intervals are
199 // returned by appending them to SplitVRegs.
200 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
201 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
202 // Record each interference and determine if all are spillable before mutating
203 // either the union or live intervals.
204 unsigned NumInterferences = 0;
205 // Collect interferences assigned to any alias of the physical register.
206 for (const unsigned *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
207 LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
208 NumInterferences += QAlias.collectInterferingVRegs();
209 if (QAlias.seenUnspillableVReg()) {
213 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
214 " interferences with " << VirtReg << "\n");
215 assert(NumInterferences > 0 && "expect interference");
217 // Spill each interfering vreg allocated to PhysReg or an alias.
218 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
219 spillReg(VirtReg, *AliasI, SplitVRegs);
223 // Driver for the register assignment and splitting heuristics.
224 // Manages iteration over the LiveIntervalUnions.
226 // This is a minimal implementation of register assignment and splitting that
227 // spills whenever we run out of registers.
229 // selectOrSplit can only be called once per live virtual register. We then do a
230 // single interference test for each register the correct class until we find an
231 // available register. So, the number of interference tests in the worst case is
232 // |vregs| * |machineregs|. And since the number of interference tests is
233 // minimal, there is no value in caching them outside the scope of
235 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
236 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
237 // Populate a list of physical register spill candidates.
238 SmallVector<unsigned, 8> PhysRegSpillCands;
240 // Check for an available register in this class.
241 ArrayRef<unsigned> Order =
242 RegClassInfo.getOrder(MRI->getRegClass(VirtReg.reg));
243 for (ArrayRef<unsigned>::iterator I = Order.begin(), E = Order.end(); I != E;
245 unsigned PhysReg = *I;
247 // Check interference and as a side effect, intialize queries for this
248 // VirtReg and its aliases.
249 unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
250 if (interfReg == 0) {
251 // Found an available register.
254 LiveIntervalUnion::Query &IntfQ = query(VirtReg, interfReg);
255 IntfQ.collectInterferingVRegs(1);
256 LiveInterval *interferingVirtReg = IntfQ.interferingVRegs().front();
258 // The current VirtReg must either be spillable, or one of its interferences
259 // must have less spill weight.
260 if (interferingVirtReg->weight < VirtReg.weight ) {
261 PhysRegSpillCands.push_back(PhysReg);
264 // Try to spill another interfering reg with less spill weight.
265 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
266 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
268 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
270 assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
271 "Interference after spill.");
272 // Tell the caller to allocate to this newly freed physical register.
276 // No other spill candidates were found, so spill the current VirtReg.
277 DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
278 if (!VirtReg.isSpillable())
280 LiveRangeEdit LRE(VirtReg, SplitVRegs);
281 spiller().spill(LRE);
283 // The live virtual register requesting allocation was spilled, so tell
284 // the caller not to allocate anything during this round.
288 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
289 DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
290 << "********** Function: "
291 << ((Value*)mf.getFunction())->getName() << '\n');
294 DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
296 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
297 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
303 // Diagnostic output before rewriting
304 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
306 // optional HTML output
307 DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
309 // FIXME: Verification currently must run before VirtRegRewriter. We should
310 // make the rewriter a separate pass and override verifyAnalysis instead. When
311 // that happens, verification naturally falls under VerifyMachineCode.
314 // Verify accuracy of LiveIntervals. The standard machine code verifier
315 // ensures that each LiveIntervals covers all uses of the virtual reg.
317 // FIXME: MachineVerifier is badly broken when using the standard
318 // spiller. Always use -spiller=inline with -verify-regalloc. Even with the
319 // inline spiller, some tests fail to verify because the coalescer does not
320 // always generate verifiable code.
321 MF->verify(this, "In RABasic::verify");
323 // Verify that LiveIntervals are partitioned into unions and disjoint within
330 VRM->rewrite(LIS->getSlotIndexes());
332 // Write out new DBG_VALUE instructions.
333 getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
335 // The pass output is in VirtRegMap. Release all the transient data.
341 FunctionPass* llvm::createBasicRegisterAllocator()
343 return new RABasic();