1 //===-- RegAllocBasic.cpp - basic register allocator ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RABasic function pass, which provides a minimal
11 // implementation of the basic register allocator.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "LiveIntervalUnion.h"
17 #include "RegAllocBase.h"
18 #include "RenderMachineFunction.h"
20 #include "VirtRegMap.h"
21 #include "VirtRegRewriter.h"
22 #include "llvm/ADT/OwningPtr.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Analysis/AliasAnalysis.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassAnalysisSupport.h"
27 #include "llvm/CodeGen/CalcSpillWeights.h"
28 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
29 #include "llvm/CodeGen/LiveStackAnalysis.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineInstr.h"
32 #include "llvm/CodeGen/MachineLoopInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/CodeGen/RegAllocRegistry.h"
36 #include "llvm/CodeGen/RegisterCoalescer.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/ADT/SparseBitVector.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/raw_ostream.h"
46 #include "llvm/Support/Timer.h"
52 STATISTIC(NumAssigned , "Number of registers assigned");
53 STATISTIC(NumUnassigned , "Number of registers unassigned");
54 STATISTIC(NumNewQueued , "Number of new live ranges queued");
56 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
57 createBasicRegisterAllocator);
59 // Temporary verification option until we can put verification inside
61 static cl::opt<bool, true>
62 VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
63 cl::desc("Verify during register allocation"));
65 const char *RegAllocBase::TimerGroupName = "Register Allocation";
66 bool RegAllocBase::VerifyEnabled = false;
69 /// RABasic provides a minimal implementation of the basic register allocation
70 /// algorithm. It prioritizes live virtual registers by spill weight and spills
71 /// whenever a register is unavailable. This is not practical in production but
72 /// provides a useful baseline both for measuring other allocators and comparing
73 /// the speed of the basic algorithm against other styles of allocators.
74 class RABasic : public MachineFunctionPass, public RegAllocBase
78 BitVector ReservedRegs;
82 RenderMachineFunction *RMF;
85 std::auto_ptr<Spiller> SpillerInstance;
90 /// Return the pass name.
91 virtual const char* getPassName() const {
92 return "Basic Register Allocator";
95 /// RABasic analysis usage.
96 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
98 virtual void releaseMemory();
100 virtual Spiller &spiller() { return *SpillerInstance; }
102 virtual float getPriority(LiveInterval *LI) { return LI->weight; }
104 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
105 SmallVectorImpl<LiveInterval*> &SplitVRegs);
107 /// Perform register allocation.
108 virtual bool runOnMachineFunction(MachineFunction &mf);
113 char RABasic::ID = 0;
115 } // end anonymous namespace
117 RABasic::RABasic(): MachineFunctionPass(ID) {
118 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
119 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
120 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
121 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
122 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
123 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
124 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
125 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
126 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
127 initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
130 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
131 AU.setPreservesCFG();
132 AU.addRequired<AliasAnalysis>();
133 AU.addPreserved<AliasAnalysis>();
134 AU.addRequired<LiveIntervals>();
135 AU.addPreserved<SlotIndexes>();
137 AU.addRequiredID(StrongPHIEliminationID);
138 AU.addRequiredTransitive<RegisterCoalescer>();
139 AU.addRequired<CalculateSpillWeights>();
140 AU.addRequired<LiveStacks>();
141 AU.addPreserved<LiveStacks>();
142 AU.addRequiredID(MachineDominatorsID);
143 AU.addPreservedID(MachineDominatorsID);
144 AU.addRequired<MachineLoopInfo>();
145 AU.addPreserved<MachineLoopInfo>();
146 AU.addRequired<VirtRegMap>();
147 AU.addPreserved<VirtRegMap>();
148 DEBUG(AU.addRequired<RenderMachineFunction>());
149 MachineFunctionPass::getAnalysisUsage(AU);
152 void RABasic::releaseMemory() {
153 SpillerInstance.reset(0);
154 RegAllocBase::releaseMemory();
158 // Verify each LiveIntervalUnion.
159 void RegAllocBase::verify() {
160 LiveVirtRegBitSet VisitedVRegs;
161 OwningArrayPtr<LiveVirtRegBitSet>
162 unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]);
164 // Verify disjoint unions.
165 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
166 DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
167 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
168 PhysReg2LiveUnion[PhysReg].verify(VRegs);
169 // Union + intersection test could be done efficiently in one pass, but
170 // don't add a method to SparseBitVector unless we really need it.
171 assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
172 VisitedVRegs |= VRegs;
175 // Verify vreg coverage.
176 for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
177 liItr != liEnd; ++liItr) {
178 unsigned reg = liItr->first;
179 if (TargetRegisterInfo::isPhysicalRegister(reg)) continue;
180 if (!VRM->hasPhys(reg)) continue; // spilled?
181 unsigned PhysReg = VRM->getPhys(reg);
182 if (!unionVRegs[PhysReg].test(reg)) {
183 dbgs() << "LiveVirtReg " << reg << " not in union " <<
184 TRI->getName(PhysReg) << "\n";
185 llvm_unreachable("unallocated live vreg");
188 // FIXME: I'm not sure how to verify spilled intervals.
192 //===----------------------------------------------------------------------===//
193 // RegAllocBase Implementation
194 //===----------------------------------------------------------------------===//
196 // Instantiate a LiveIntervalUnion for each physical register.
197 void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
201 static_cast<LiveIntervalUnion*>(malloc(sizeof(LiveIntervalUnion)*NRegs));
202 for (unsigned r = 0; r != NRegs; ++r)
203 new(Array + r) LiveIntervalUnion(r, allocator);
206 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
207 NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
208 TRI = &vrm.getTargetRegInfo();
209 MRI = &vrm.getRegInfo();
212 PhysReg2LiveUnion.init(UnionAllocator, TRI->getNumRegs());
213 // Cache an interferece query for each physical reg
214 Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]);
217 void RegAllocBase::LiveUnionArray::clear() {
220 for (unsigned r = 0; r != NumRegs; ++r)
221 Array[r].~LiveIntervalUnion();
227 void RegAllocBase::releaseMemory() {
228 PhysReg2LiveUnion.clear();
231 // Visit all the live virtual registers. If they are already assigned to a
232 // physical register, unify them with the corresponding LiveIntervalUnion,
233 // otherwise push them on the priority queue for later assignment.
235 seedLiveVirtRegs(std::priority_queue<std::pair<float, unsigned> > &VirtRegQ) {
236 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
237 unsigned RegNum = I->first;
238 LiveInterval &VirtReg = *I->second;
239 if (TargetRegisterInfo::isPhysicalRegister(RegNum))
240 PhysReg2LiveUnion[RegNum].unify(VirtReg);
242 VirtRegQ.push(std::make_pair(getPriority(&VirtReg), RegNum));
246 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
247 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
248 << " to " << PrintReg(PhysReg, TRI) << '\n');
249 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
250 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
251 PhysReg2LiveUnion[PhysReg].unify(VirtReg);
255 void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) {
256 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
257 << " from " << PrintReg(PhysReg, TRI) << '\n');
258 assert(VRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign");
259 PhysReg2LiveUnion[PhysReg].extract(VirtReg);
260 VRM->clearVirt(VirtReg.reg);
264 // Top-level driver to manage the queue of unassigned VirtRegs and call the
265 // selectOrSplit implementation.
266 void RegAllocBase::allocatePhysRegs() {
268 // Push each vreg onto a queue or "precolor" by adding it to a physreg union.
269 std::priority_queue<std::pair<float, unsigned> > VirtRegQ;
270 seedLiveVirtRegs(VirtRegQ);
272 // Continue assigning vregs one at a time to available physical registers.
273 while (!VirtRegQ.empty()) {
274 // Pop the highest priority vreg.
275 LiveInterval &VirtReg = LIS->getInterval(VirtRegQ.top().second);
278 // selectOrSplit requests the allocator to return an available physical
279 // register if possible and populate a list of new live intervals that
280 // result from splitting.
281 DEBUG(dbgs() << "\nselectOrSplit " << MRI->getRegClass(VirtReg.reg)->getName()
282 << ':' << VirtReg << '\n');
283 typedef SmallVector<LiveInterval*, 4> VirtRegVec;
284 VirtRegVec SplitVRegs;
285 unsigned AvailablePhysReg = selectOrSplit(VirtReg, SplitVRegs);
287 if (AvailablePhysReg)
288 assign(VirtReg, AvailablePhysReg);
290 for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
292 LiveInterval* SplitVirtReg = *I;
293 if (SplitVirtReg->empty()) continue;
294 DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
295 assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
296 "expect split value in virtual register");
297 VirtRegQ.push(std::make_pair(getPriority(SplitVirtReg),
304 // Check if this live virtual register interferes with a physical register. If
305 // not, then check for interference on each register that aliases with the
306 // physical register. Return the interfering register.
307 unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg,
309 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
310 if (query(VirtReg, *AliasI).checkInterference())
315 // Helper for spillInteferences() that spills all interfering vregs currently
316 // assigned to this physical register.
317 void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
318 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
319 LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
320 assert(Q.seenAllInterferences() && "need collectInterferences()");
321 const SmallVectorImpl<LiveInterval*> &PendingSpills = Q.interferingVRegs();
323 for (SmallVectorImpl<LiveInterval*>::const_iterator I = PendingSpills.begin(),
324 E = PendingSpills.end(); I != E; ++I) {
325 LiveInterval &SpilledVReg = **I;
326 DEBUG(dbgs() << "extracting from " <<
327 TRI->getName(PhysReg) << " " << SpilledVReg << '\n');
329 // Deallocate the interfering vreg by removing it from the union.
330 // A LiveInterval instance may not be in a union during modification!
331 unassign(SpilledVReg, PhysReg);
333 // Spill the extracted interval.
334 spiller().spill(&SpilledVReg, SplitVRegs, PendingSpills);
336 // After extracting segments, the query's results are invalid. But keep the
337 // contents valid until we're done accessing pendingSpills.
341 // Spill or split all live virtual registers currently unified under PhysReg
342 // that interfere with VirtReg. The newly spilled or split live intervals are
343 // returned by appending them to SplitVRegs.
345 RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
346 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
347 // Record each interference and determine if all are spillable before mutating
348 // either the union or live intervals.
349 unsigned NumInterferences = 0;
350 // Collect interferences assigned to any alias of the physical register.
351 for (const unsigned *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
352 LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
353 NumInterferences += QAlias.collectInterferingVRegs();
354 if (QAlias.seenUnspillableVReg()) {
358 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
359 " interferences with " << VirtReg << "\n");
360 assert(NumInterferences > 0 && "expect interference");
362 // Spill each interfering vreg allocated to PhysReg or an alias.
363 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
364 spillReg(VirtReg, *AliasI, SplitVRegs);
368 // Add newly allocated physical registers to the MBB live in sets.
369 void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
370 NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled);
371 typedef SmallVector<MachineBasicBlock*, 8> MBBVec;
373 MachineBasicBlock &entryMBB = *MF->begin();
375 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
376 LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg];
377 if (LiveUnion.empty())
379 for (LiveIntervalUnion::SegmentIter SI = LiveUnion.begin(); SI.valid();
382 // Find the set of basic blocks which this range is live into...
384 if (!LIS->findLiveInMBBs(SI.start(), SI.stop(), liveInMBBs)) continue;
386 // And add the physreg for this interval to their live-in sets.
387 for (MBBVec::iterator I = liveInMBBs.begin(), E = liveInMBBs.end();
389 MachineBasicBlock *MBB = *I;
390 if (MBB == &entryMBB) continue;
391 if (MBB->isLiveIn(PhysReg)) continue;
392 MBB->addLiveIn(PhysReg);
399 //===----------------------------------------------------------------------===//
400 // RABasic Implementation
401 //===----------------------------------------------------------------------===//
403 // Driver for the register assignment and splitting heuristics.
404 // Manages iteration over the LiveIntervalUnions.
406 // This is a minimal implementation of register assignment and splitting that
407 // spills whenever we run out of registers.
409 // selectOrSplit can only be called once per live virtual register. We then do a
410 // single interference test for each register the correct class until we find an
411 // available register. So, the number of interference tests in the worst case is
412 // |vregs| * |machineregs|. And since the number of interference tests is
413 // minimal, there is no value in caching them outside the scope of
415 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
416 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
417 // Populate a list of physical register spill candidates.
418 SmallVector<unsigned, 8> PhysRegSpillCands;
420 // Check for an available register in this class.
421 const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
423 for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
424 E = TRC->allocation_order_end(*MF);
427 unsigned PhysReg = *I;
428 if (ReservedRegs.test(PhysReg)) continue;
430 // Check interference and as a side effect, intialize queries for this
431 // VirtReg and its aliases.
432 unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
433 if (interfReg == 0) {
434 // Found an available register.
437 LiveInterval *interferingVirtReg =
438 Queries[interfReg].firstInterference().liveUnionPos().value();
440 // The current VirtReg must either be spillable, or one of its interferences
441 // must have less spill weight.
442 if (interferingVirtReg->weight < VirtReg.weight ) {
443 PhysRegSpillCands.push_back(PhysReg);
446 // Try to spill another interfering reg with less spill weight.
447 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
448 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
450 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
452 assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
453 "Interference after spill.");
454 // Tell the caller to allocate to this newly freed physical register.
457 // No other spill candidates were found, so spill the current VirtReg.
458 DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
459 SmallVector<LiveInterval*, 1> pendingSpills;
461 spiller().spill(&VirtReg, SplitVRegs, pendingSpills);
463 // The live virtual register requesting allocation was spilled, so tell
464 // the caller not to allocate anything during this round.
468 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
469 DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
470 << "********** Function: "
471 << ((Value*)mf.getFunction())->getName() << '\n');
474 DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
476 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
478 ReservedRegs = TRI->getReservedRegs(*MF);
480 SpillerInstance.reset(createSpiller(*this, *MF, *VRM));
486 // Diagnostic output before rewriting
487 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
489 // optional HTML output
490 DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
492 // FIXME: Verification currently must run before VirtRegRewriter. We should
493 // make the rewriter a separate pass and override verifyAnalysis instead. When
494 // that happens, verification naturally falls under VerifyMachineCode.
497 // Verify accuracy of LiveIntervals. The standard machine code verifier
498 // ensures that each LiveIntervals covers all uses of the virtual reg.
500 // FIXME: MachineVerifier is badly broken when using the standard
501 // spiller. Always use -spiller=inline with -verify-regalloc. Even with the
502 // inline spiller, some tests fail to verify because the coalescer does not
503 // always generate verifiable code.
504 MF->verify(this, "In RABasic::verify");
506 // Verify that LiveIntervals are partitioned into unions and disjoint within
513 std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
514 rewriter->runOnMachineFunction(*MF, *VRM, LIS);
516 // The pass output is in VirtRegMap. Release all the transient data.
522 FunctionPass* llvm::createBasicRegisterAllocator()
524 return new RABasic();