1 //===-- RegAllocBasic.cpp - basic register allocator ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RABasic function pass, which provides a minimal
11 // implementation of the basic register allocator.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "LiveIntervalUnion.h"
17 #include "RegAllocBase.h"
18 #include "RenderMachineFunction.h"
20 #include "VirtRegMap.h"
21 #include "VirtRegRewriter.h"
22 #include "llvm/ADT/OwningPtr.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/Function.h"
25 #include "llvm/PassAnalysisSupport.h"
26 #include "llvm/CodeGen/CalcSpillWeights.h"
27 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
28 #include "llvm/CodeGen/LiveStackAnalysis.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineLoopInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/RegAllocRegistry.h"
35 #include "llvm/CodeGen/RegisterCoalescer.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/ADT/SparseBitVector.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/raw_ostream.h"
45 #include "llvm/Support/Timer.h"
51 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
52 createBasicRegisterAllocator);
54 // Temporary verification option until we can put verification inside
56 static cl::opt<bool, true>
57 VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
58 cl::desc("Verify during register allocation"));
60 const char *RegAllocBase::TimerGroupName = "Register Allocation";
61 bool RegAllocBase::VerifyEnabled = false;
64 /// RABasic provides a minimal implementation of the basic register allocation
65 /// algorithm. It prioritizes live virtual registers by spill weight and spills
66 /// whenever a register is unavailable. This is not practical in production but
67 /// provides a useful baseline both for measuring other allocators and comparing
68 /// the speed of the basic algorithm against other styles of allocators.
69 class RABasic : public MachineFunctionPass, public RegAllocBase
73 BitVector ReservedRegs;
77 RenderMachineFunction *RMF;
80 std::auto_ptr<Spiller> SpillerInstance;
85 /// Return the pass name.
86 virtual const char* getPassName() const {
87 return "Basic Register Allocator";
90 /// RABasic analysis usage.
91 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
93 virtual void releaseMemory();
95 virtual Spiller &spiller() { return *SpillerInstance; }
97 virtual float getPriority(LiveInterval *LI) { return LI->weight; }
99 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
100 SmallVectorImpl<LiveInterval*> &SplitVRegs);
102 /// Perform register allocation.
103 virtual bool runOnMachineFunction(MachineFunction &mf);
108 char RABasic::ID = 0;
110 } // end anonymous namespace
112 RABasic::RABasic(): MachineFunctionPass(ID) {
113 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
114 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
115 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
116 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
117 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
118 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
119 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
120 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
121 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
122 initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
125 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
126 AU.setPreservesCFG();
127 AU.addRequired<AliasAnalysis>();
128 AU.addPreserved<AliasAnalysis>();
129 AU.addRequired<LiveIntervals>();
130 AU.addPreserved<SlotIndexes>();
132 AU.addRequiredID(StrongPHIEliminationID);
133 AU.addRequiredTransitive<RegisterCoalescer>();
134 AU.addRequired<CalculateSpillWeights>();
135 AU.addRequired<LiveStacks>();
136 AU.addPreserved<LiveStacks>();
137 AU.addRequiredID(MachineDominatorsID);
138 AU.addPreservedID(MachineDominatorsID);
139 AU.addRequired<MachineLoopInfo>();
140 AU.addPreserved<MachineLoopInfo>();
141 AU.addRequired<VirtRegMap>();
142 AU.addPreserved<VirtRegMap>();
143 DEBUG(AU.addRequired<RenderMachineFunction>());
144 MachineFunctionPass::getAnalysisUsage(AU);
147 void RABasic::releaseMemory() {
148 SpillerInstance.reset(0);
149 RegAllocBase::releaseMemory();
153 // Verify each LiveIntervalUnion.
154 void RegAllocBase::verify() {
155 LiveVirtRegBitSet VisitedVRegs;
156 OwningArrayPtr<LiveVirtRegBitSet>
157 unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]);
159 // Verify disjoint unions.
160 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
161 DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
162 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
163 PhysReg2LiveUnion[PhysReg].verify(VRegs);
164 // Union + intersection test could be done efficiently in one pass, but
165 // don't add a method to SparseBitVector unless we really need it.
166 assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
167 VisitedVRegs |= VRegs;
170 // Verify vreg coverage.
171 for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
172 liItr != liEnd; ++liItr) {
173 unsigned reg = liItr->first;
174 if (TargetRegisterInfo::isPhysicalRegister(reg)) continue;
175 if (!VRM->hasPhys(reg)) continue; // spilled?
176 unsigned PhysReg = VRM->getPhys(reg);
177 if (!unionVRegs[PhysReg].test(reg)) {
178 dbgs() << "LiveVirtReg " << reg << " not in union " <<
179 TRI->getName(PhysReg) << "\n";
180 llvm_unreachable("unallocated live vreg");
183 // FIXME: I'm not sure how to verify spilled intervals.
187 //===----------------------------------------------------------------------===//
188 // RegAllocBase Implementation
189 //===----------------------------------------------------------------------===//
191 // Instantiate a LiveIntervalUnion for each physical register.
192 void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
196 static_cast<LiveIntervalUnion*>(malloc(sizeof(LiveIntervalUnion)*NRegs));
197 for (unsigned r = 0; r != NRegs; ++r)
198 new(Array + r) LiveIntervalUnion(r, allocator);
201 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
202 NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
203 TRI = &vrm.getTargetRegInfo();
204 MRI = &vrm.getRegInfo();
207 PhysReg2LiveUnion.init(UnionAllocator, TRI->getNumRegs());
208 // Cache an interferece query for each physical reg
209 Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]);
212 void RegAllocBase::LiveUnionArray::clear() {
215 for (unsigned r = 0; r != NumRegs; ++r)
216 Array[r].~LiveIntervalUnion();
222 void RegAllocBase::releaseMemory() {
223 PhysReg2LiveUnion.clear();
226 // Visit all the live virtual registers. If they are already assigned to a
227 // physical register, unify them with the corresponding LiveIntervalUnion,
228 // otherwise push them on the priority queue for later assignment.
230 seedLiveVirtRegs(std::priority_queue<std::pair<float, unsigned> > &VirtRegQ) {
231 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
232 unsigned RegNum = I->first;
233 LiveInterval &VirtReg = *I->second;
234 if (TargetRegisterInfo::isPhysicalRegister(RegNum))
235 PhysReg2LiveUnion[RegNum].unify(VirtReg);
237 VirtRegQ.push(std::make_pair(getPriority(&VirtReg), RegNum));
241 // Top-level driver to manage the queue of unassigned VirtRegs and call the
242 // selectOrSplit implementation.
243 void RegAllocBase::allocatePhysRegs() {
245 // Push each vreg onto a queue or "precolor" by adding it to a physreg union.
246 std::priority_queue<std::pair<float, unsigned> > VirtRegQ;
247 seedLiveVirtRegs(VirtRegQ);
249 // Continue assigning vregs one at a time to available physical registers.
250 while (!VirtRegQ.empty()) {
251 // Pop the highest priority vreg.
252 LiveInterval &VirtReg = LIS->getInterval(VirtRegQ.top().second);
255 // selectOrSplit requests the allocator to return an available physical
256 // register if possible and populate a list of new live intervals that
257 // result from splitting.
258 DEBUG(dbgs() << "\nselectOrSplit " << MRI->getRegClass(VirtReg.reg)->getName()
259 << ':' << VirtReg << '\n');
260 typedef SmallVector<LiveInterval*, 4> VirtRegVec;
261 VirtRegVec SplitVRegs;
262 unsigned AvailablePhysReg = selectOrSplit(VirtReg, SplitVRegs);
264 if (AvailablePhysReg) {
265 DEBUG(dbgs() << "allocating: " << TRI->getName(AvailablePhysReg)
266 << " for " << VirtReg << '\n');
267 assert(!VRM->hasPhys(VirtReg.reg) && "duplicate vreg in union");
268 VRM->assignVirt2Phys(VirtReg.reg, AvailablePhysReg);
269 PhysReg2LiveUnion[AvailablePhysReg].unify(VirtReg);
271 for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
273 LiveInterval* SplitVirtReg = *I;
274 if (SplitVirtReg->empty()) continue;
275 DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
276 assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
277 "expect split value in virtual register");
278 VirtRegQ.push(std::make_pair(getPriority(SplitVirtReg),
284 // Check if this live virtual register interferes with a physical register. If
285 // not, then check for interference on each register that aliases with the
286 // physical register. Return the interfering register.
287 unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg,
289 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
290 if (query(VirtReg, *AliasI).checkInterference())
295 // Helper for spillInteferences() that spills all interfering vregs currently
296 // assigned to this physical register.
297 void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
298 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
299 LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
300 assert(Q.seenAllInterferences() && "need collectInterferences()");
301 const SmallVectorImpl<LiveInterval*> &PendingSpills = Q.interferingVRegs();
303 for (SmallVectorImpl<LiveInterval*>::const_iterator I = PendingSpills.begin(),
304 E = PendingSpills.end(); I != E; ++I) {
305 LiveInterval &SpilledVReg = **I;
306 DEBUG(dbgs() << "extracting from " <<
307 TRI->getName(PhysReg) << " " << SpilledVReg << '\n');
309 // Deallocate the interfering vreg by removing it from the union.
310 // A LiveInterval instance may not be in a union during modification!
311 PhysReg2LiveUnion[PhysReg].extract(SpilledVReg);
313 // Clear the vreg assignment.
314 VRM->clearVirt(SpilledVReg.reg);
316 // Spill the extracted interval.
317 spiller().spill(&SpilledVReg, SplitVRegs, PendingSpills);
319 // After extracting segments, the query's results are invalid. But keep the
320 // contents valid until we're done accessing pendingSpills.
324 // Spill or split all live virtual registers currently unified under PhysReg
325 // that interfere with VirtReg. The newly spilled or split live intervals are
326 // returned by appending them to SplitVRegs.
328 RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
329 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
330 // Record each interference and determine if all are spillable before mutating
331 // either the union or live intervals.
332 unsigned NumInterferences = 0;
333 // Collect interferences assigned to any alias of the physical register.
334 for (const unsigned *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
335 LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
336 NumInterferences += QAlias.collectInterferingVRegs();
337 if (QAlias.seenUnspillableVReg()) {
341 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
342 " interferences with " << VirtReg << "\n");
343 assert(NumInterferences > 0 && "expect interference");
345 // Spill each interfering vreg allocated to PhysReg or an alias.
346 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
347 spillReg(VirtReg, *AliasI, SplitVRegs);
351 // Add newly allocated physical registers to the MBB live in sets.
352 void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
353 NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled);
354 typedef SmallVector<MachineBasicBlock*, 8> MBBVec;
356 MachineBasicBlock &entryMBB = *MF->begin();
358 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
359 LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg];
360 if (LiveUnion.empty())
362 for (LiveIntervalUnion::SegmentIter SI = LiveUnion.begin(); SI.valid();
365 // Find the set of basic blocks which this range is live into...
367 if (!LIS->findLiveInMBBs(SI.start(), SI.stop(), liveInMBBs)) continue;
369 // And add the physreg for this interval to their live-in sets.
370 for (MBBVec::iterator I = liveInMBBs.begin(), E = liveInMBBs.end();
372 MachineBasicBlock *MBB = *I;
373 if (MBB == &entryMBB) continue;
374 if (MBB->isLiveIn(PhysReg)) continue;
375 MBB->addLiveIn(PhysReg);
382 //===----------------------------------------------------------------------===//
383 // RABasic Implementation
384 //===----------------------------------------------------------------------===//
386 // Driver for the register assignment and splitting heuristics.
387 // Manages iteration over the LiveIntervalUnions.
389 // This is a minimal implementation of register assignment and splitting that
390 // spills whenever we run out of registers.
392 // selectOrSplit can only be called once per live virtual register. We then do a
393 // single interference test for each register the correct class until we find an
394 // available register. So, the number of interference tests in the worst case is
395 // |vregs| * |machineregs|. And since the number of interference tests is
396 // minimal, there is no value in caching them outside the scope of
398 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
399 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
400 // Populate a list of physical register spill candidates.
401 SmallVector<unsigned, 8> PhysRegSpillCands;
403 // Check for an available register in this class.
404 const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
406 for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
407 E = TRC->allocation_order_end(*MF);
410 unsigned PhysReg = *I;
411 if (ReservedRegs.test(PhysReg)) continue;
413 // Check interference and as a side effect, intialize queries for this
414 // VirtReg and its aliases.
415 unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
416 if (interfReg == 0) {
417 // Found an available register.
420 LiveInterval *interferingVirtReg =
421 Queries[interfReg].firstInterference().liveUnionPos().value();
423 // The current VirtReg must either be spillable, or one of its interferences
424 // must have less spill weight.
425 if (interferingVirtReg->weight < VirtReg.weight ) {
426 PhysRegSpillCands.push_back(PhysReg);
429 // Try to spill another interfering reg with less spill weight.
430 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
431 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
433 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
435 assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
436 "Interference after spill.");
437 // Tell the caller to allocate to this newly freed physical register.
440 // No other spill candidates were found, so spill the current VirtReg.
441 DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
442 SmallVector<LiveInterval*, 1> pendingSpills;
444 spiller().spill(&VirtReg, SplitVRegs, pendingSpills);
446 // The live virtual register requesting allocation was spilled, so tell
447 // the caller not to allocate anything during this round.
451 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
452 DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
453 << "********** Function: "
454 << ((Value*)mf.getFunction())->getName() << '\n');
457 DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
459 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
461 ReservedRegs = TRI->getReservedRegs(*MF);
463 SpillerInstance.reset(createSpiller(*this, *MF, *VRM));
469 // Diagnostic output before rewriting
470 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
472 // optional HTML output
473 DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
475 // FIXME: Verification currently must run before VirtRegRewriter. We should
476 // make the rewriter a separate pass and override verifyAnalysis instead. When
477 // that happens, verification naturally falls under VerifyMachineCode.
480 // Verify accuracy of LiveIntervals. The standard machine code verifier
481 // ensures that each LiveIntervals covers all uses of the virtual reg.
483 // FIXME: MachineVerifier is badly broken when using the standard
484 // spiller. Always use -spiller=inline with -verify-regalloc. Even with the
485 // inline spiller, some tests fail to verify because the coalescer does not
486 // always generate verifiable code.
487 MF->verify(this, "In RABasic::verify");
489 // Verify that LiveIntervals are partitioned into unions and disjoint within
496 std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
497 rewriter->runOnMachineFunction(*MF, *VRM, LIS);
499 // The pass output is in VirtRegMap. Release all the transient data.
505 FunctionPass* llvm::createBasicRegisterAllocator()
507 return new RABasic();