1 //===-- RegAllocBasic.cpp - basic register allocator ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RABasic function pass, which provides a minimal
11 // implementation of the basic register allocator.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "LiveIntervalUnion.h"
17 #include "RegAllocBase.h"
18 #include "RenderMachineFunction.h"
20 #include "VirtRegMap.h"
21 #include "llvm/ADT/OwningPtr.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/Function.h"
25 #include "llvm/PassAnalysisSupport.h"
26 #include "llvm/CodeGen/CalcSpillWeights.h"
27 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
28 #include "llvm/CodeGen/LiveStackAnalysis.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineLoopInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/RegAllocRegistry.h"
35 #include "llvm/CodeGen/RegisterCoalescer.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/ADT/SparseBitVector.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/raw_ostream.h"
45 #include "llvm/Support/Timer.h"
51 STATISTIC(NumAssigned , "Number of registers assigned");
52 STATISTIC(NumUnassigned , "Number of registers unassigned");
53 STATISTIC(NumNewQueued , "Number of new live ranges queued");
55 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
56 createBasicRegisterAllocator);
58 // Temporary verification option until we can put verification inside
60 static cl::opt<bool, true>
61 VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
62 cl::desc("Verify during register allocation"));
64 const char *RegAllocBase::TimerGroupName = "Register Allocation";
65 bool RegAllocBase::VerifyEnabled = false;
68 /// RABasic provides a minimal implementation of the basic register allocation
69 /// algorithm. It prioritizes live virtual registers by spill weight and spills
70 /// whenever a register is unavailable. This is not practical in production but
71 /// provides a useful baseline both for measuring other allocators and comparing
72 /// the speed of the basic algorithm against other styles of allocators.
73 class RABasic : public MachineFunctionPass, public RegAllocBase
77 BitVector ReservedRegs;
81 RenderMachineFunction *RMF;
84 std::auto_ptr<Spiller> SpillerInstance;
89 /// Return the pass name.
90 virtual const char* getPassName() const {
91 return "Basic Register Allocator";
94 /// RABasic analysis usage.
95 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
97 virtual void releaseMemory();
99 virtual Spiller &spiller() { return *SpillerInstance; }
101 virtual float getPriority(LiveInterval *LI) { return LI->weight; }
103 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
104 SmallVectorImpl<LiveInterval*> &SplitVRegs);
106 /// Perform register allocation.
107 virtual bool runOnMachineFunction(MachineFunction &mf);
112 char RABasic::ID = 0;
114 } // end anonymous namespace
116 RABasic::RABasic(): MachineFunctionPass(ID) {
117 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
118 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
119 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
120 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
121 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
122 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
123 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
124 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
125 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
126 initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
129 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
130 AU.setPreservesCFG();
131 AU.addRequired<AliasAnalysis>();
132 AU.addPreserved<AliasAnalysis>();
133 AU.addRequired<LiveIntervals>();
134 AU.addPreserved<SlotIndexes>();
136 AU.addRequiredID(StrongPHIEliminationID);
137 AU.addRequiredTransitive<RegisterCoalescer>();
138 AU.addRequired<CalculateSpillWeights>();
139 AU.addRequired<LiveStacks>();
140 AU.addPreserved<LiveStacks>();
141 AU.addRequiredID(MachineDominatorsID);
142 AU.addPreservedID(MachineDominatorsID);
143 AU.addRequired<MachineLoopInfo>();
144 AU.addPreserved<MachineLoopInfo>();
145 AU.addRequired<VirtRegMap>();
146 AU.addPreserved<VirtRegMap>();
147 DEBUG(AU.addRequired<RenderMachineFunction>());
148 MachineFunctionPass::getAnalysisUsage(AU);
151 void RABasic::releaseMemory() {
152 SpillerInstance.reset(0);
153 RegAllocBase::releaseMemory();
157 // Verify each LiveIntervalUnion.
158 void RegAllocBase::verify() {
159 LiveVirtRegBitSet VisitedVRegs;
160 OwningArrayPtr<LiveVirtRegBitSet>
161 unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]);
163 // Verify disjoint unions.
164 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
165 DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
166 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
167 PhysReg2LiveUnion[PhysReg].verify(VRegs);
168 // Union + intersection test could be done efficiently in one pass, but
169 // don't add a method to SparseBitVector unless we really need it.
170 assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
171 VisitedVRegs |= VRegs;
174 // Verify vreg coverage.
175 for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
176 liItr != liEnd; ++liItr) {
177 unsigned reg = liItr->first;
178 if (TargetRegisterInfo::isPhysicalRegister(reg)) continue;
179 if (!VRM->hasPhys(reg)) continue; // spilled?
180 unsigned PhysReg = VRM->getPhys(reg);
181 if (!unionVRegs[PhysReg].test(reg)) {
182 dbgs() << "LiveVirtReg " << reg << " not in union " <<
183 TRI->getName(PhysReg) << "\n";
184 llvm_unreachable("unallocated live vreg");
187 // FIXME: I'm not sure how to verify spilled intervals.
191 //===----------------------------------------------------------------------===//
192 // RegAllocBase Implementation
193 //===----------------------------------------------------------------------===//
195 // Instantiate a LiveIntervalUnion for each physical register.
196 void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
200 static_cast<LiveIntervalUnion*>(malloc(sizeof(LiveIntervalUnion)*NRegs));
201 for (unsigned r = 0; r != NRegs; ++r)
202 new(Array + r) LiveIntervalUnion(r, allocator);
205 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
206 NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
207 TRI = &vrm.getTargetRegInfo();
208 MRI = &vrm.getRegInfo();
211 PhysReg2LiveUnion.init(UnionAllocator, TRI->getNumRegs());
212 // Cache an interferece query for each physical reg
213 Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]);
216 void RegAllocBase::LiveUnionArray::clear() {
219 for (unsigned r = 0; r != NumRegs; ++r)
220 Array[r].~LiveIntervalUnion();
226 void RegAllocBase::releaseMemory() {
227 PhysReg2LiveUnion.clear();
230 // Visit all the live virtual registers. If they are already assigned to a
231 // physical register, unify them with the corresponding LiveIntervalUnion,
232 // otherwise push them on the priority queue for later assignment.
234 seedLiveVirtRegs(std::priority_queue<std::pair<float, unsigned> > &VirtRegQ) {
235 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
236 unsigned RegNum = I->first;
237 LiveInterval &VirtReg = *I->second;
238 if (TargetRegisterInfo::isPhysicalRegister(RegNum))
239 PhysReg2LiveUnion[RegNum].unify(VirtReg);
241 VirtRegQ.push(std::make_pair(getPriority(&VirtReg), RegNum));
245 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
246 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
247 << " to " << PrintReg(PhysReg, TRI) << '\n');
248 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
249 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
250 PhysReg2LiveUnion[PhysReg].unify(VirtReg);
254 void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) {
255 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
256 << " from " << PrintReg(PhysReg, TRI) << '\n');
257 assert(VRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign");
258 PhysReg2LiveUnion[PhysReg].extract(VirtReg);
259 VRM->clearVirt(VirtReg.reg);
263 // Top-level driver to manage the queue of unassigned VirtRegs and call the
264 // selectOrSplit implementation.
265 void RegAllocBase::allocatePhysRegs() {
267 // Push each vreg onto a queue or "precolor" by adding it to a physreg union.
268 std::priority_queue<std::pair<float, unsigned> > VirtRegQ;
269 seedLiveVirtRegs(VirtRegQ);
271 // Continue assigning vregs one at a time to available physical registers.
272 while (!VirtRegQ.empty()) {
273 // Pop the highest priority vreg.
274 LiveInterval &VirtReg = LIS->getInterval(VirtRegQ.top().second);
277 // selectOrSplit requests the allocator to return an available physical
278 // register if possible and populate a list of new live intervals that
279 // result from splitting.
280 DEBUG(dbgs() << "\nselectOrSplit " << MRI->getRegClass(VirtReg.reg)->getName()
281 << ':' << VirtReg << '\n');
282 typedef SmallVector<LiveInterval*, 4> VirtRegVec;
283 VirtRegVec SplitVRegs;
284 unsigned AvailablePhysReg = selectOrSplit(VirtReg, SplitVRegs);
286 if (AvailablePhysReg)
287 assign(VirtReg, AvailablePhysReg);
289 for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
291 LiveInterval* SplitVirtReg = *I;
292 if (SplitVirtReg->empty()) continue;
293 DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
294 assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
295 "expect split value in virtual register");
296 VirtRegQ.push(std::make_pair(getPriority(SplitVirtReg),
303 // Check if this live virtual register interferes with a physical register. If
304 // not, then check for interference on each register that aliases with the
305 // physical register. Return the interfering register.
306 unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg,
308 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
309 if (query(VirtReg, *AliasI).checkInterference())
314 // Helper for spillInteferences() that spills all interfering vregs currently
315 // assigned to this physical register.
316 void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
317 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
318 LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
319 assert(Q.seenAllInterferences() && "need collectInterferences()");
320 const SmallVectorImpl<LiveInterval*> &PendingSpills = Q.interferingVRegs();
322 for (SmallVectorImpl<LiveInterval*>::const_iterator I = PendingSpills.begin(),
323 E = PendingSpills.end(); I != E; ++I) {
324 LiveInterval &SpilledVReg = **I;
325 DEBUG(dbgs() << "extracting from " <<
326 TRI->getName(PhysReg) << " " << SpilledVReg << '\n');
328 // Deallocate the interfering vreg by removing it from the union.
329 // A LiveInterval instance may not be in a union during modification!
330 unassign(SpilledVReg, PhysReg);
332 // Spill the extracted interval.
333 spiller().spill(&SpilledVReg, SplitVRegs, PendingSpills);
335 // After extracting segments, the query's results are invalid. But keep the
336 // contents valid until we're done accessing pendingSpills.
340 // Spill or split all live virtual registers currently unified under PhysReg
341 // that interfere with VirtReg. The newly spilled or split live intervals are
342 // returned by appending them to SplitVRegs.
344 RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
345 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
346 // Record each interference and determine if all are spillable before mutating
347 // either the union or live intervals.
348 unsigned NumInterferences = 0;
349 // Collect interferences assigned to any alias of the physical register.
350 for (const unsigned *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
351 LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
352 NumInterferences += QAlias.collectInterferingVRegs();
353 if (QAlias.seenUnspillableVReg()) {
357 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
358 " interferences with " << VirtReg << "\n");
359 assert(NumInterferences > 0 && "expect interference");
361 // Spill each interfering vreg allocated to PhysReg or an alias.
362 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
363 spillReg(VirtReg, *AliasI, SplitVRegs);
367 // Add newly allocated physical registers to the MBB live in sets.
368 void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
369 NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled);
370 typedef SmallVector<MachineBasicBlock*, 8> MBBVec;
372 MachineBasicBlock &entryMBB = *MF->begin();
374 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
375 LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg];
376 if (LiveUnion.empty())
378 for (LiveIntervalUnion::SegmentIter SI = LiveUnion.begin(); SI.valid();
381 // Find the set of basic blocks which this range is live into...
383 if (!LIS->findLiveInMBBs(SI.start(), SI.stop(), liveInMBBs)) continue;
385 // And add the physreg for this interval to their live-in sets.
386 for (MBBVec::iterator I = liveInMBBs.begin(), E = liveInMBBs.end();
388 MachineBasicBlock *MBB = *I;
389 if (MBB == &entryMBB) continue;
390 if (MBB->isLiveIn(PhysReg)) continue;
391 MBB->addLiveIn(PhysReg);
398 //===----------------------------------------------------------------------===//
399 // RABasic Implementation
400 //===----------------------------------------------------------------------===//
402 // Driver for the register assignment and splitting heuristics.
403 // Manages iteration over the LiveIntervalUnions.
405 // This is a minimal implementation of register assignment and splitting that
406 // spills whenever we run out of registers.
408 // selectOrSplit can only be called once per live virtual register. We then do a
409 // single interference test for each register the correct class until we find an
410 // available register. So, the number of interference tests in the worst case is
411 // |vregs| * |machineregs|. And since the number of interference tests is
412 // minimal, there is no value in caching them outside the scope of
414 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
415 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
416 // Populate a list of physical register spill candidates.
417 SmallVector<unsigned, 8> PhysRegSpillCands;
419 // Check for an available register in this class.
420 const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
422 for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
423 E = TRC->allocation_order_end(*MF);
426 unsigned PhysReg = *I;
427 if (ReservedRegs.test(PhysReg)) continue;
429 // Check interference and as a side effect, intialize queries for this
430 // VirtReg and its aliases.
431 unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
432 if (interfReg == 0) {
433 // Found an available register.
436 LiveInterval *interferingVirtReg =
437 Queries[interfReg].firstInterference().liveUnionPos().value();
439 // The current VirtReg must either be spillable, or one of its interferences
440 // must have less spill weight.
441 if (interferingVirtReg->weight < VirtReg.weight ) {
442 PhysRegSpillCands.push_back(PhysReg);
445 // Try to spill another interfering reg with less spill weight.
446 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
447 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
449 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
451 assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
452 "Interference after spill.");
453 // Tell the caller to allocate to this newly freed physical register.
456 // No other spill candidates were found, so spill the current VirtReg.
457 DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
458 SmallVector<LiveInterval*, 1> pendingSpills;
460 spiller().spill(&VirtReg, SplitVRegs, pendingSpills);
462 // The live virtual register requesting allocation was spilled, so tell
463 // the caller not to allocate anything during this round.
467 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
468 DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
469 << "********** Function: "
470 << ((Value*)mf.getFunction())->getName() << '\n');
473 DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
475 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
477 ReservedRegs = TRI->getReservedRegs(*MF);
479 SpillerInstance.reset(createSpiller(*this, *MF, *VRM));
485 // Diagnostic output before rewriting
486 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
488 // optional HTML output
489 DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
491 // FIXME: Verification currently must run before VirtRegRewriter. We should
492 // make the rewriter a separate pass and override verifyAnalysis instead. When
493 // that happens, verification naturally falls under VerifyMachineCode.
496 // Verify accuracy of LiveIntervals. The standard machine code verifier
497 // ensures that each LiveIntervals covers all uses of the virtual reg.
499 // FIXME: MachineVerifier is badly broken when using the standard
500 // spiller. Always use -spiller=inline with -verify-regalloc. Even with the
501 // inline spiller, some tests fail to verify because the coalescer does not
502 // always generate verifiable code.
503 MF->verify(this, "In RABasic::verify");
505 // Verify that LiveIntervals are partitioned into unions and disjoint within
512 VRM->rewrite(LIS->getSlotIndexes());
514 // The pass output is in VirtRegMap. Release all the transient data.
520 FunctionPass* llvm::createBasicRegisterAllocator()
522 return new RABasic();