1 //===-- RegAllocBase.h - basic regalloc interface and driver --*- C++ -*---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RegAllocBase class, which is the skeleton of a basic
11 // register allocation algorithm and interface for extending it. It provides the
12 // building blocks on which to construct other experimental allocators and test
13 // the validity of two principles:
15 // - If virtual and physical register liveness is modeled using intervals, then
16 // on-the-fly interference checking is cheap. Furthermore, interferences can be
17 // lazily cached and reused.
19 // - Register allocation complexity, and generated code performance is
20 // determined by the effectiveness of live range splitting rather than optimal
23 // Following the first principle, interfering checking revolves around the
24 // LiveIntervalUnion data structure.
26 // To fulfill the second principle, the basic allocator provides a driver for
27 // incremental splitting. It essentially punts on the problem of register
28 // coloring, instead driving the assignment of virtual to physical registers by
29 // the cost of splitting. The basic allocator allows for heuristic reassignment
30 // of registers, if a more sophisticated allocator chooses to do that.
32 // This framework provides a way to engineer the compile time vs. code
33 // quality trade-off without relying a particular theoretical solver.
35 //===----------------------------------------------------------------------===//
37 #ifndef LLVM_CODEGEN_REGALLOCBASE
38 #define LLVM_CODEGEN_REGALLOCBASE
40 #include "llvm/ADT/OwningPtr.h"
44 template<typename T> class SmallVectorImpl;
45 class TargetRegisterInfo;
50 // Heuristic that determines the priority of assigning virtual to physical
51 // registers. The main impact of the heuristic is expected to be compile time.
52 // The default is to simply compare spill weights.
53 struct LessSpillWeightPriority
54 : public std::binary_function<LiveInterval,LiveInterval, bool> {
55 bool operator()(const LiveInterval *Left, const LiveInterval *Right) const {
56 return Left->weight < Right->weight;
60 // Forward declare a priority queue of live virtual registers. If an
61 // implementation needs to prioritize by anything other than spill weight, then
62 // this will become an abstract base class with virtual calls to push/get.
63 class LiveVirtRegQueue;
65 /// RegAllocBase provides the register allocation driver and interface that can
66 /// be extended to add interesting heuristics.
68 /// Register allocators must override the selectOrSplit() method to implement
69 /// live range splitting. LessSpillWeightPriority is provided as a standard
70 /// comparator, but we may add an interface to override it if necessary.
73 // Array of LiveIntervalUnions indexed by physical register.
74 class LiveUnionArray {
76 OwningArrayPtr<LiveIntervalUnion> Array;
78 LiveUnionArray(): NumRegs(0) {}
80 unsigned numRegs() const { return NumRegs; }
82 void init(unsigned NRegs);
86 LiveIntervalUnion& operator[](unsigned PhysReg) {
87 assert(PhysReg < NumRegs && "physReg out of bounds");
88 return Array[PhysReg];
92 const TargetRegisterInfo *TRI;
95 LiveUnionArray PhysReg2LiveUnion;
97 // Current queries, one per physreg. They must be reinitialized each time we
98 // query on a new live virtual register.
99 OwningArrayPtr<LiveIntervalUnion::Query> Queries;
101 RegAllocBase(): TRI(0), VRM(0), LIS(0) {}
103 virtual ~RegAllocBase() {}
105 // A RegAlloc pass should call this before allocatePhysRegs.
106 void init(const TargetRegisterInfo &tri, VirtRegMap &vrm, LiveIntervals &lis);
108 // Get an initialized query to check interferences between lvr and preg. Note
109 // that Query::init must be called at least once for each physical register
110 // before querying a new live virtual register. This ties Queries and
111 // PhysReg2LiveUnion together.
112 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned PhysReg) {
113 Queries[PhysReg].init(&VirtReg, &PhysReg2LiveUnion[PhysReg]);
114 return Queries[PhysReg];
117 // The top-level driver. The output is a VirtRegMap that us updated with
118 // physical register assignments.
120 // If an implementation wants to override the LiveInterval comparator, we
121 // should modify this interface to allow passing in an instance derived from
123 void allocatePhysRegs();
125 // Get a temporary reference to a Spiller instance.
126 virtual Spiller &spiller() = 0;
128 // A RegAlloc pass should override this to provide the allocation heuristics.
129 // Each call must guarantee forward progess by returning an available PhysReg
130 // or new set of split live virtual registers. It is up to the splitter to
131 // converge quickly toward fully spilled live ranges.
132 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
133 SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;
135 // A RegAlloc pass should call this when PassManager releases its memory.
136 virtual void releaseMemory();
138 // Helper for checking interference between a live virtual register and a
139 // physical register, including all its register aliases. If an interference
140 // exists, return the interfering register, which may be preg or an alias.
141 unsigned checkPhysRegInterference(LiveInterval& VirtReg, unsigned PhysReg);
143 // Helper for spilling all live virtual registers currently unified under preg
144 // that interfere with the most recently queried lvr. Return true if spilling
145 // was successful, and append any new spilled/split intervals to splitLVRs.
146 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
147 SmallVectorImpl<LiveInterval*> &SplitVRegs);
150 // Verify each LiveIntervalUnion.
155 void seedLiveVirtRegs(LiveVirtRegQueue &VirtRegQ);
157 void spillReg(LiveInterval &VirtReg, unsigned PhysReg,
158 SmallVectorImpl<LiveInterval*> &SplitVRegs);
161 } // end namespace llvm
163 #endif // !defined(LLVM_CODEGEN_REGALLOCBASE)